drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else if (IS_GEN5(dev_priv))
 223                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 224         else
 225                 return 270000;
 226 }
 227
 228 static const struct intel_limit intel_limits_i8xx_dac = {
 229         .dot = { .min = 25000, .max = 350000 },
 230         .vco = { .min = 908000, .max = 1512000 },
 231         .n = { .min = 2, .max = 16 },
 232         .m = { .min = 96, .max = 140 },
 233         .m1 = { .min = 18, .max = 26 },
 234         .m2 = { .min = 6, .max = 16 },
 235         .p = { .min = 4, .max = 128 },
 236         .p1 = { .min = 2, .max = 33 },
 237         .p2 = { .dot_limit = 165000,
 238                 .p2_slow = 4, .p2_fast = 2 },
 239 };
 240
 241 static const struct intel_limit intel_limits_i8xx_dvo = {
 242         .dot = { .min = 25000, .max = 350000 },
 243         .vco = { .min = 908000, .max = 1512000 },
 244         .n = { .min = 2, .max = 16 },
 245         .m = { .min = 96, .max = 140 },
 246         .m1 = { .min = 18, .max = 26 },
 247         .m2 = { .min = 6, .max = 16 },
 248         .p = { .min = 4, .max = 128 },
 249         .p1 = { .min = 2, .max = 33 },
 250         .p2 = { .dot_limit = 165000,
 251                 .p2_slow = 4, .p2_fast = 4 },
 252 };
 253
 254 static const struct intel_limit intel_limits_i8xx_lvds = {
 255         .dot = { .min = 25000, .max = 350000 },
 256         .vco = { .min = 908000, .max = 1512000 },
 257         .n = { .min = 2, .max = 16 },
 258         .m = { .min = 96, .max = 140 },
 259         .m1 = { .min = 18, .max = 26 },
 260         .m2 = { .min = 6, .max = 16 },
 261         .p = { .min = 4, .max = 128 },
 262         .p1 = { .min = 1, .max = 6 },
 263         .p2 = { .dot_limit = 165000,
 264                 .p2_slow = 14, .p2_fast = 7 },
 265 };
 266
 267 static const struct intel_limit intel_limits_i9xx_sdvo = {
 268         .dot = { .min = 20000, .max = 400000 },
 269         .vco = { .min = 1400000, .max = 2800000 },
 270         .n = { .min = 1, .max = 6 },
 271         .m = { .min = 70, .max = 120 },
 272         .m1 = { .min = 8, .max = 18 },
 273         .m2 = { .min = 3, .max = 7 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const struct intel_limit intel_limits_i9xx_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1400000, .max = 2800000 },
 283         .n = { .min = 1, .max = 6 },
 284         .m = { .min = 70, .max = 120 },
 285         .m1 = { .min = 8, .max = 18 },
 286         .m2 = { .min = 3, .max = 7 },
 287         .p = { .min = 7, .max = 98 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 7 },
 291 };
 292
 293
 294 static const struct intel_limit intel_limits_g4x_sdvo = {
 295         .dot = { .min = 25000, .max = 270000 },
 296         .vco = { .min = 1750000, .max = 3500000},
 297         .n = { .min = 1, .max = 4 },
 298         .m = { .min = 104, .max = 138 },
 299         .m1 = { .min = 17, .max = 23 },
 300         .m2 = { .min = 5, .max = 11 },
 301         .p = { .min = 10, .max = 30 },
 302         .p1 = { .min = 1, .max = 3},
 303         .p2 = { .dot_limit = 270000,
 304                 .p2_slow = 10,
 305                 .p2_fast = 10
 306         },
 307 };
 308
 309 static const struct intel_limit intel_limits_g4x_hdmi = {
 310         .dot = { .min = 22000, .max = 400000 },
 311         .vco = { .min = 1750000, .max = 3500000},
 312         .n = { .min = 1, .max = 4 },
 313         .m = { .min = 104, .max = 138 },
 314         .m1 = { .min = 16, .max = 23 },
 315         .m2 = { .min = 5, .max = 11 },
 316         .p = { .min = 5, .max = 80 },
 317         .p1 = { .min = 1, .max = 8},
 318         .p2 = { .dot_limit = 165000,
 319                 .p2_slow = 10, .p2_fast = 5 },
 320 };
 321
 322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 323         .dot = { .min = 20000, .max = 115000 },
 324         .vco = { .min = 1750000, .max = 3500000 },
 325         .n = { .min = 1, .max = 3 },
 326         .m = { .min = 104, .max = 138 },
 327         .m1 = { .min = 17, .max = 23 },
 328         .m2 = { .min = 5, .max = 11 },
 329         .p = { .min = 28, .max = 112 },
 330         .p1 = { .min = 2, .max = 8 },
 331         .p2 = { .dot_limit = 0,
 332                 .p2_slow = 14, .p2_fast = 14
 333         },
 334 };
 335
 336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 337         .dot = { .min = 80000, .max = 224000 },
 338         .vco = { .min = 1750000, .max = 3500000 },
 339         .n = { .min = 1, .max = 3 },
 340         .m = { .min = 104, .max = 138 },
 341         .m1 = { .min = 17, .max = 23 },
 342         .m2 = { .min = 5, .max = 11 },
 343         .p = { .min = 14, .max = 42 },
 344         .p1 = { .min = 2, .max = 6 },
 345         .p2 = { .dot_limit = 0,
 346                 .p2_slow = 7, .p2_fast = 7
 347         },
 348 };
 349
 350 static const struct intel_limit intel_limits_pineview_sdvo = {
 351         .dot = { .min = 20000, .max = 400000},
 352         .vco = { .min = 1700000, .max = 3500000 },
 353         /* Pineview's Ncounter is a ring counter */
 354         .n = { .min = 3, .max = 6 },
 355         .m = { .min = 2, .max = 256 },
 356         /* Pineview only has one combined m divider, which we treat as m2. */
 357         .m1 = { .min = 0, .max = 0 },
 358         .m2 = { .min = 0, .max = 254 },
 359         .p = { .min = 5, .max = 80 },
 360         .p1 = { .min = 1, .max = 8 },
 361         .p2 = { .dot_limit = 200000,
 362                 .p2_slow = 10, .p2_fast = 5 },
 363 };
 364
 365 static const struct intel_limit intel_limits_pineview_lvds = {
 366         .dot = { .min = 20000, .max = 400000 },
 367         .vco = { .min = 1700000, .max = 3500000 },
 368         .n = { .min = 3, .max = 6 },
 369         .m = { .min = 2, .max = 256 },
 370         .m1 = { .min = 0, .max = 0 },
 371         .m2 = { .min = 0, .max = 254 },
 372         .p = { .min = 7, .max = 112 },
 373         .p1 = { .min = 1, .max = 8 },
 374         .p2 = { .dot_limit = 112000,
 375                 .p2_slow = 14, .p2_fast = 14 },
 376 };
 377
 378 /* Ironlake / Sandybridge
 379  *
 380  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 381  * the range value for them is (actual_value - 2).
 382  */
 383 static const struct intel_limit intel_limits_ironlake_dac = {
 384         .dot = { .min = 25000, .max = 350000 },
 385         .vco = { .min = 1760000, .max = 3510000 },
 386         .n = { .min = 1, .max = 5 },
 387         .m = { .min = 79, .max = 127 },
 388         .m1 = { .min = 12, .max = 22 },
 389         .m2 = { .min = 5, .max = 9 },
 390         .p = { .min = 5, .max = 80 },
 391         .p1 = { .min = 1, .max = 8 },
 392         .p2 = { .dot_limit = 225000,
 393                 .p2_slow = 10, .p2_fast = 5 },
 394 };
 395
 396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 397         .dot = { .min = 25000, .max = 350000 },
 398         .vco = { .min = 1760000, .max = 3510000 },
 399         .n = { .min = 1, .max = 3 },
 400         .m = { .min = 79, .max = 118 },
 401         .m1 = { .min = 12, .max = 22 },
 402         .m2 = { .min = 5, .max = 9 },
 403         .p = { .min = 28, .max = 112 },
 404         .p1 = { .min = 2, .max = 8 },
 405         .p2 = { .dot_limit = 225000,
 406                 .p2_slow = 14, .p2_fast = 14 },
 407 };
 408
 409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 410         .dot = { .min = 25000, .max = 350000 },
 411         .vco = { .min = 1760000, .max = 3510000 },
 412         .n = { .min = 1, .max = 3 },
 413         .m = { .min = 79, .max = 127 },
 414         .m1 = { .min = 12, .max = 22 },
 415         .m2 = { .min = 5, .max = 9 },
 416         .p = { .min = 14, .max = 56 },
 417         .p1 = { .min = 2, .max = 8 },
 418         .p2 = { .dot_limit = 225000,
 419                 .p2_slow = 7, .p2_fast = 7 },
 420 };
 421
 422 /* LVDS 100mhz refclk limits. */
 423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 424         .dot = { .min = 25000, .max = 350000 },
 425         .vco = { .min = 1760000, .max = 3510000 },
 426         .n = { .min = 1, .max = 2 },
 427         .m = { .min = 79, .max = 126 },
 428         .m1 = { .min = 12, .max = 22 },
 429         .m2 = { .min = 5, .max = 9 },
 430         .p = { .min = 28, .max = 112 },
 431         .p1 = { .min = 2, .max = 8 },
 432         .p2 = { .dot_limit = 225000,
 433                 .p2_slow = 14, .p2_fast = 14 },
 434 };
 435
 436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 437         .dot = { .min = 25000, .max = 350000 },
 438         .vco = { .min = 1760000, .max = 3510000 },
 439         .n = { .min = 1, .max = 3 },
 440         .m = { .min = 79, .max = 126 },
 441         .m1 = { .min = 12, .max = 22 },
 442         .m2 = { .min = 5, .max = 9 },
 443         .p = { .min = 14, .max = 42 },
 444         .p1 = { .min = 2, .max = 6 },
 445         .p2 = { .dot_limit = 225000,
 446                 .p2_slow = 7, .p2_fast = 7 },
 447 };
 448
 449 static const struct intel_limit intel_limits_vlv = {
 450          /*
 451           * These are the data rate limits (measured in fast clocks)
 452           * since those are the strictest limits we have. The fast
 453           * clock and actual rate limits are more relaxed, so checking
 454           * them would make no difference.
 455           */
 456         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 457         .vco = { .min = 4000000, .max = 6000000 },
 458         .n = { .min = 1, .max = 7 },
 459         .m1 = { .min = 2, .max = 3 },
 460         .m2 = { .min = 11, .max = 156 },
 461         .p1 = { .min = 2, .max = 3 },
 462         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 463 };
 464
 465 static const struct intel_limit intel_limits_chv = {
 466         /*
 467          * These are the data rate limits (measured in fast clocks)
 468          * since those are the strictest limits we have.  The fast
 469          * clock and actual rate limits are more relaxed, so checking
 470          * them would make no difference.
 471          */
 472         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 473         .vco = { .min = 4800000, .max = 6480000 },
 474         .n = { .min = 1, .max = 1 },
 475         .m1 = { .min = 2, .max = 2 },
 476         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 477         .p1 = { .min = 2, .max = 4 },
 478         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 479 };
 480
 481 static const struct intel_limit intel_limits_bxt = {
 482         /* FIXME: find real dot limits */
 483         .dot = { .min = 0, .max = INT_MAX },
 484         .vco = { .min = 4800000, .max = 6700000 },
 485         .n = { .min = 1, .max = 1 },
 486         .m1 = { .min = 2, .max = 2 },
 487         /* FIXME: find real m2 limits */
 488         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 489         .p1 = { .min = 2, .max = 4 },
 490         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 491 };
 492
 493 static bool
 494 needs_modeset(struct drm_crtc_state *state)
 495 {
 496         return drm_atomic_crtc_needs_modeset(state);
 497 }
 498
 499 /*
 500  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 501  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 502  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 503  * The helpers' return value is the rate of the clock that is fed to the
 504  * display engine's pipe which can be the above fast dot clock rate or a
 505  * divided-down version of it.
 506  */
 507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 509 {
 510         clock->m = clock->m2 + 2;
 511         clock->p = clock->p1 * clock->p2;
 512         if (WARN_ON(clock->n == 0 || clock->p == 0))
 513                 return 0;
 514         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 515         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 516
 517         return clock->dot;
 518 }
 519
 520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 521 {
 522         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 523 }
 524
 525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 526 {
 527         clock->m = i9xx_dpll_compute_m(clock);
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 530                 return 0;
 531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot;
 535 }
 536
 537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 538 {
 539         clock->m = clock->m1 * clock->m2;
 540         clock->p = clock->p1 * clock->p2;
 541         if (WARN_ON(clock->n == 0 || clock->p == 0))
 542                 return 0;
 543         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 544         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 545
 546         return clock->dot / 5;
 547 }
 548
 549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return 0;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558
 559         return clock->dot / 5;
 560 }
 561
 562 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 563 /**
 564  * Returns whether the given set of divisors are valid for a given refclk with
 565  * the given connectors.
 566  */
 567
 568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 569                                const struct intel_limit *limit,
 570                                const struct dpll *clock)
 571 {
 572         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 573                 INTELPllInvalid("n out of range\n");
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 577                 INTELPllInvalid("m2 out of range\n");
 578         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 579                 INTELPllInvalid("m1 out of range\n");
 580
 581         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 582             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 583                 if (clock->m1 <= clock->m2)
 584                         INTELPllInvalid("m1 <= m2\n");
 585
 586         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 587             !IS_GEN9_LP(dev_priv)) {
 588                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 589                         INTELPllInvalid("p out of range\n");
 590                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 591                         INTELPllInvalid("m out of range\n");
 592         }
 593
 594         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 595                 INTELPllInvalid("vco out of range\n");
 596         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 597          * connector, etc., rather than just a single range.
 598          */
 599         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 600                 INTELPllInvalid("dot out of range\n");
 601
 602         return true;
 603 }
 604
 605 static int
 606 i9xx_select_p2_div(const struct intel_limit *limit,
 607                    const struct intel_crtc_state *crtc_state,
 608                    int target)
 609 {
 610         struct drm_device *dev = crtc_state->base.crtc->dev;
 611
 612         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 613                 /*
 614                  * For LVDS just rely on its current settings for dual-channel.
 615                  * We haven't figured out how to reliably set up different
 616                  * single/dual channel state, if we even can.
 617                  */
 618                 if (intel_is_dual_link_lvds(dev))
 619                         return limit->p2.p2_fast;
 620                 else
 621                         return limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         return limit->p2.p2_slow;
 625                 else
 626                         return limit->p2.p2_fast;
 627         }
 628 }
 629
 630 /*
 631  * Returns a set of divisors for the desired target clock with the given
 632  * refclk, or FALSE.  The returned values represent the clock equation:
 633  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 634  *
 635  * Target and reference clocks are specified in kHz.
 636  *
 637  * If match_clock is provided, then best_clock P divider must match the P
 638  * divider from @match_clock used for LVDS downclocking.
 639  */
 640 static bool
 641 i9xx_find_best_dpll(const struct intel_limit *limit,
 642                     struct intel_crtc_state *crtc_state,
 643                     int target, int refclk, struct dpll *match_clock,
 644                     struct dpll *best_clock)
 645 {
 646         struct drm_device *dev = crtc_state->base.crtc->dev;
 647         struct dpll clock;
 648         int err = target;
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651
 652         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         if (clock.m2 >= clock.m1)
 659                                 break;
 660                         for (clock.n = limit->n.min;
 661                              clock.n <= limit->n.max; clock.n++) {
 662                                 for (clock.p1 = limit->p1.min;
 663                                         clock.p1 <= limit->p1.max; clock.p1++) {
 664                                         int this_err;
 665
 666                                         i9xx_calc_dpll_params(refclk, &clock);
 667                                         if (!intel_PLL_is_valid(to_i915(dev),
 668                                                                 limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 /*
 689  * Returns a set of divisors for the desired target clock with the given
 690  * refclk, or FALSE.  The returned values represent the clock equation:
 691  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 692  *
 693  * Target and reference clocks are specified in kHz.
 694  *
 695  * If match_clock is provided, then best_clock P divider must match the P
 696  * divider from @match_clock used for LVDS downclocking.
 697  */
 698 static bool
 699 pnv_find_best_dpll(const struct intel_limit *limit,
 700                    struct intel_crtc_state *crtc_state,
 701                    int target, int refclk, struct dpll *match_clock,
 702                    struct dpll *best_clock)
 703 {
 704         struct drm_device *dev = crtc_state->base.crtc->dev;
 705         struct dpll clock;
 706         int err = target;
 707
 708         memset(best_clock, 0, sizeof(*best_clock));
 709
 710         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 711
 712         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 713              clock.m1++) {
 714                 for (clock.m2 = limit->m2.min;
 715                      clock.m2 <= limit->m2.max; clock.m2++) {
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         pnv_calc_dpll_params(refclk, &clock);
 723                                         if (!intel_PLL_is_valid(to_i915(dev),
 724                                                                 limit,
 725                                                                 &clock))
 726                                                 continue;
 727                                         if (match_clock &&
 728                                             clock.p != match_clock->p)
 729                                                 continue;
 730
 731                                         this_err = abs(clock.dot - target);
 732                                         if (this_err < err) {
 733                                                 *best_clock = clock;
 734                                                 err = this_err;
 735                                         }
 736                                 }
 737                         }
 738                 }
 739         }
 740
 741         return (err != target);
 742 }
 743
 744 /*
 745  * Returns a set of divisors for the desired target clock with the given
 746  * refclk, or FALSE.  The returned values represent the clock equation:
 747  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 748  *
 749  * Target and reference clocks are specified in kHz.
 750  *
 751  * If match_clock is provided, then best_clock P divider must match the P
 752  * divider from @match_clock used for LVDS downclocking.
 753  */
 754 static bool
 755 g4x_find_best_dpll(const struct intel_limit *limit,
 756                    struct intel_crtc_state *crtc_state,
 757                    int target, int refclk, struct dpll *match_clock,
 758                    struct dpll *best_clock)
 759 {
 760         struct drm_device *dev = crtc_state->base.crtc->dev;
 761         struct dpll clock;
 762         int max_n;
 763         bool found = false;
 764         /* approximately equals target * 0.00585 */
 765         int err_most = (target >> 8) + (target >> 9);
 766
 767         memset(best_clock, 0, sizeof(*best_clock));
 768
 769         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 770
 771         max_n = limit->n.max;
 772         /* based on hardware requirement, prefer smaller n to precision */
 773         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 774                 /* based on hardware requirement, prefere larger m1,m2 */
 775                 for (clock.m1 = limit->m1.max;
 776                      clock.m1 >= limit->m1.min; clock.m1--) {
 777                         for (clock.m2 = limit->m2.max;
 778                              clock.m2 >= limit->m2.min; clock.m2--) {
 779                                 for (clock.p1 = limit->p1.max;
 780                                      clock.p1 >= limit->p1.min; clock.p1--) {
 781                                         int this_err;
 782
 783                                         i9xx_calc_dpll_params(refclk, &clock);
 784                                         if (!intel_PLL_is_valid(to_i915(dev),
 785                                                                 limit,
 786                                                                 &clock))
 787                                                 continue;
 788
 789                                         this_err = abs(clock.dot - target);
 790                                         if (this_err < err_most) {
 791                                                 *best_clock = clock;
 792                                                 err_most = this_err;
 793                                                 max_n = clock.n;
 794                                                 found = true;
 795                                         }
 796                                 }
 797                         }
 798                 }
 799         }
 800         return found;
 801 }
 802
 803 /*
 804  * Check if the calculated PLL configuration is more optimal compared to the
 805  * best configuration and error found so far. Return the calculated error.
 806  */
 807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 808                                const struct dpll *calculated_clock,
 809                                const struct dpll *best_clock,
 810                                unsigned int best_error_ppm,
 811                                unsigned int *error_ppm)
 812 {
 813         /*
 814          * For CHV ignore the error and consider only the P value.
 815          * Prefer a bigger P value based on HW requirements.
 816          */
 817         if (IS_CHERRYVIEW(to_i915(dev))) {
 818                 *error_ppm = 0;
 819
 820                 return calculated_clock->p > best_clock->p;
 821         }
 822
 823         if (WARN_ON_ONCE(!target_freq))
 824                 return false;
 825
 826         *error_ppm = div_u64(1000000ULL *
 827                                 abs(target_freq - calculated_clock->dot),
 828                              target_freq);
 829         /*
 830          * Prefer a better P value over a better (smaller) error if the error
 831          * is small. Ensure this preference for future configurations too by
 832          * setting the error to 0.
 833          */
 834         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 835                 *error_ppm = 0;
 836
 837                 return true;
 838         }
 839
 840         return *error_ppm + 10 < best_error_ppm;
 841 }
 842
 843 /*
 844  * Returns a set of divisors for the desired target clock with the given
 845  * refclk, or FALSE.  The returned values represent the clock equation:
 846  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 847  */
 848 static bool
 849 vlv_find_best_dpll(const struct intel_limit *limit,
 850                    struct intel_crtc_state *crtc_state,
 851                    int target, int refclk, struct dpll *match_clock,
 852                    struct dpll *best_clock)
 853 {
 854         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 855         struct drm_device *dev = crtc->base.dev;
 856         struct dpll clock;
 857         unsigned int bestppm = 1000000;
 858         /* min update 19.2 MHz */
 859         int max_n = min(limit->n.max, refclk / 19200);
 860         bool found = false;
 861
 862         target *= 5; /* fast clock */
 863
 864         memset(best_clock, 0, sizeof(*best_clock));
 865
 866         /* based on hardware requirement, prefer smaller n to precision */
 867         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 868                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 869                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 870                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 871                                 clock.p = clock.p1 * clock.p2;
 872                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 873                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 874                                         unsigned int ppm;
 875
 876                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 877                                                                      refclk * clock.m1);
 878
 879                                         vlv_calc_dpll_params(refclk, &clock);
 880
 881                                         if (!intel_PLL_is_valid(to_i915(dev),
 882                                                                 limit,
 883                                                                 &clock))
 884                                                 continue;
 885
 886                                         if (!vlv_PLL_is_optimal(dev, target,
 887                                                                 &clock,
 888                                                                 best_clock,
 889                                                                 bestppm, &ppm))
 890                                                 continue;
 891
 892                                         *best_clock = clock;
 893                                         bestppm = ppm;
 894                                         found = true;
 895                                 }
 896                         }
 897                 }
 898         }
 899
 900         return found;
 901 }
 902
 903 /*
 904  * Returns a set of divisors for the desired target clock with the given
 905  * refclk, or FALSE.  The returned values represent the clock equation:
 906  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 907  */
 908 static bool
 909 chv_find_best_dpll(const struct intel_limit *limit,
 910                    struct intel_crtc_state *crtc_state,
 911                    int target, int refclk, struct dpll *match_clock,
 912                    struct dpll *best_clock)
 913 {
 914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 915         struct drm_device *dev = crtc->base.dev;
 916         unsigned int best_error_ppm;
 917         struct dpll clock;
 918         uint64_t m2;
 919         int found = false;
 920
 921         memset(best_clock, 0, sizeof(*best_clock));
 922         best_error_ppm = 1000000;
 923
 924         /*
 925          * Based on hardware doc, the n always set to 1, and m1 always
 926          * set to 2.  If requires to support 200Mhz refclk, we need to
 927          * revisit this because n may not 1 anymore.
 928          */
 929         clock.n = 1, clock.m1 = 2;
 930         target *= 5;    /* fast clock */
 931
 932         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 933                 for (clock.p2 = limit->p2.p2_fast;
 934                                 clock.p2 >= limit->p2.p2_slow;
 935                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 936                         unsigned int error_ppm;
 937
 938                         clock.p = clock.p1 * clock.p2;
 939
 940                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 941                                         clock.n) << 22, refclk * clock.m1);
 942
 943                         if (m2 > INT_MAX/clock.m1)
 944                                 continue;
 945
 946                         clock.m2 = m2;
 947
 948                         chv_calc_dpll_params(refclk, &clock);
 949
 950                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 951                                 continue;
 952
 953                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 954                                                 best_error_ppm, &error_ppm))
 955                                 continue;
 956
 957                         *best_clock = clock;
 958                         best_error_ppm = error_ppm;
 959                         found = true;
 960                 }
 961         }
 962
 963         return found;
 964 }
 965
 966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 967                         struct dpll *best_clock)
 968 {
 969         int refclk = 100000;
 970         const struct intel_limit *limit = &intel_limits_bxt;
 971
 972         return chv_find_best_dpll(limit, crtc_state,
 973                                   target_clock, refclk, NULL, best_clock);
 974 }
 975
 976 bool intel_crtc_active(struct intel_crtc *crtc)
 977 {
 978         /* Be paranoid as we can arrive here with only partial
 979          * state retrieved from the hardware during setup.
 980          *
 981          * We can ditch the adjusted_mode.crtc_clock check as soon
 982          * as Haswell has gained clock readout/fastboot support.
 983          *
 984          * We can ditch the crtc->primary->fb check as soon as we can
 985          * properly reconstruct framebuffers.
 986          *
 987          * FIXME: The intel_crtc->active here should be switched to
 988          * crtc->state->active once we have proper CRTC states wired up
 989          * for atomic.
 990          */
 991         return crtc->active && crtc->base.primary->state->fb &&
 992                 crtc->config->base.adjusted_mode.crtc_clock;
 993 }
 994
 995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 996                                              enum pipe pipe)
 997 {
 998         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 999
1000         return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1004                                     enum pipe pipe)
1005 {
1006         i915_reg_t reg = PIPEDSL(pipe);
1007         u32 line1, line2;
1008         u32 line_mask;
1009
1010         if (IS_GEN2(dev_priv))
1011                 line_mask = DSL_LINEMASK_GEN2;
1012         else
1013                 line_mask = DSL_LINEMASK_GEN3;
1014
1015         line1 = I915_READ(reg) & line_mask;
1016         msleep(5);
1017         line2 = I915_READ(reg) & line_mask;
1018
1019         return line1 != line2;
1020 }
1021
1022 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1023 {
1024         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1025         enum pipe pipe = crtc->pipe;
1026
1027         /* Wait for the display line to settle/start moving */
1028         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1029                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1030                           pipe_name(pipe), onoff(state));
1031 }
1032
1033 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1034 {
1035         wait_for_pipe_scanline_moving(crtc, false);
1036 }
1037
1038 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1039 {
1040         wait_for_pipe_scanline_moving(crtc, true);
1041 }
1042
1043 /*
1044  * intel_wait_for_pipe_off - wait for pipe to turn off
1045  * @crtc: crtc whose pipe to wait for
1046  *
1047  * After disabling a pipe, we can't wait for vblank in the usual way,
1048  * spinning on the vblank interrupt status bit, since we won't actually
1049  * see an interrupt when the pipe is disabled.
1050  *
1051  * On Gen4 and above:
1052  *   wait for the pipe register state bit to turn off
1053  *
1054  * Otherwise:
1055  *   wait for the display line value to settle (it usually
1056  *   ends up stopping at the start of the next frame).
1057  *
1058  */
1059 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1060 {
1061         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1062         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1063
1064         if (INTEL_GEN(dev_priv) >= 4) {
1065                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1066
1067                 /* Wait for the Pipe State to go off */
1068                 if (intel_wait_for_register(dev_priv,
1069                                             reg, I965_PIPECONF_ACTIVE, 0,
1070                                             100))
1071                         WARN(1, "pipe_off wait timed out\n");
1072         } else {
1073                 intel_wait_for_pipe_scanline_stopped(crtc);
1074         }
1075 }
1076
1077 /* Only for pre-ILK configs */
1078 void assert_pll(struct drm_i915_private *dev_priv,
1079                 enum pipe pipe, bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         val = I915_READ(DPLL(pipe));
1085         cur_state = !!(val & DPLL_VCO_ENABLE);
1086         I915_STATE_WARN(cur_state != state,
1087              "PLL state assertion failure (expected %s, current %s)\n",
1088                         onoff(state), onoff(cur_state));
1089 }
1090
1091 /* XXX: the dsi pll is shared between MIPI DSI ports */
1092 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1093 {
1094         u32 val;
1095         bool cur_state;
1096
1097         mutex_lock(&dev_priv->sb_lock);
1098         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1099         mutex_unlock(&dev_priv->sb_lock);
1100
1101         cur_state = val & DSI_PLL_VCO_EN;
1102         I915_STATE_WARN(cur_state != state,
1103              "DSI PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1108                           enum pipe pipe, bool state)
1109 {
1110         bool cur_state;
1111         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1112                                                                       pipe);
1113
1114         if (HAS_DDI(dev_priv)) {
1115                 /* DDI does not have a specific FDI_TX register */
1116                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1117                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1118         } else {
1119                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1120                 cur_state = !!(val & FDI_TX_ENABLE);
1121         }
1122         I915_STATE_WARN(cur_state != state,
1123              "FDI TX state assertion failure (expected %s, current %s)\n",
1124                         onoff(state), onoff(cur_state));
1125 }
1126 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1127 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1128
1129 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1130                           enum pipe pipe, bool state)
1131 {
1132         u32 val;
1133         bool cur_state;
1134
1135         val = I915_READ(FDI_RX_CTL(pipe));
1136         cur_state = !!(val & FDI_RX_ENABLE);
1137         I915_STATE_WARN(cur_state != state,
1138              "FDI RX state assertion failure (expected %s, current %s)\n",
1139                         onoff(state), onoff(cur_state));
1140 }
1141 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1142 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1143
1144 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1145                                       enum pipe pipe)
1146 {
1147         u32 val;
1148
1149         /* ILK FDI PLL is always enabled */
1150         if (IS_GEN5(dev_priv))
1151                 return;
1152
1153         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1154         if (HAS_DDI(dev_priv))
1155                 return;
1156
1157         val = I915_READ(FDI_TX_CTL(pipe));
1158         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1159 }
1160
1161 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1162                        enum pipe pipe, bool state)
1163 {
1164         u32 val;
1165         bool cur_state;
1166
1167         val = I915_READ(FDI_RX_CTL(pipe));
1168         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1169         I915_STATE_WARN(cur_state != state,
1170              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1171                         onoff(state), onoff(cur_state));
1172 }
1173
1174 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1175 {
1176         i915_reg_t pp_reg;
1177         u32 val;
1178         enum pipe panel_pipe = PIPE_A;
1179         bool locked = true;
1180
1181         if (WARN_ON(HAS_DDI(dev_priv)))
1182                 return;
1183
1184         if (HAS_PCH_SPLIT(dev_priv)) {
1185                 u32 port_sel;
1186
1187                 pp_reg = PP_CONTROL(0);
1188                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1189
1190                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1191                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1192                         panel_pipe = PIPE_B;
1193                 /* XXX: else fix for eDP */
1194         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1195                 /* presumably write lock depends on pipe, not port select */
1196                 pp_reg = PP_CONTROL(pipe);
1197                 panel_pipe = pipe;
1198         } else {
1199                 pp_reg = PP_CONTROL(0);
1200                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1201                         panel_pipe = PIPE_B;
1202         }
1203
1204         val = I915_READ(pp_reg);
1205         if (!(val & PANEL_POWER_ON) ||
1206             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1207                 locked = false;
1208
1209         I915_STATE_WARN(panel_pipe == pipe && locked,
1210              "panel assertion failure, pipe %c regs locked\n",
1211              pipe_name(pipe));
1212 }
1213
1214 static void assert_cursor(struct drm_i915_private *dev_priv,
1215                           enum pipe pipe, bool state)
1216 {
1217         bool cur_state;
1218
1219         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1220                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1221         else
1222                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1223
1224         I915_STATE_WARN(cur_state != state,
1225              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1226                         pipe_name(pipe), onoff(state), onoff(cur_state));
1227 }
1228 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1229 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1230
1231 void assert_pipe(struct drm_i915_private *dev_priv,
1232                  enum pipe pipe, bool state)
1233 {
1234         bool cur_state;
1235         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1236                                                                       pipe);
1237         enum intel_display_power_domain power_domain;
1238
1239         /* we keep both pipes enabled on 830 */
1240         if (IS_I830(dev_priv))
1241                 state = true;
1242
1243         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1244         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1245                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1246                 cur_state = !!(val & PIPECONF_ENABLE);
1247
1248                 intel_display_power_put(dev_priv, power_domain);
1249         } else {
1250                 cur_state = false;
1251         }
1252
1253         I915_STATE_WARN(cur_state != state,
1254              "pipe %c assertion failure (expected %s, current %s)\n",
1255                         pipe_name(pipe), onoff(state), onoff(cur_state));
1256 }
1257
1258 static void assert_plane(struct drm_i915_private *dev_priv,
1259                          enum plane plane, bool state)
1260 {
1261         u32 val;
1262         bool cur_state;
1263
1264         val = I915_READ(DSPCNTR(plane));
1265         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1266         I915_STATE_WARN(cur_state != state,
1267              "plane %c assertion failure (expected %s, current %s)\n",
1268                         plane_name(plane), onoff(state), onoff(cur_state));
1269 }
1270
1271 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1272 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1273
1274 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1275                                    enum pipe pipe)
1276 {
1277         int i;
1278
1279         /* Primary planes are fixed to pipes on gen4+ */
1280         if (INTEL_GEN(dev_priv) >= 4) {
1281                 u32 val = I915_READ(DSPCNTR(pipe));
1282                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for_each_pipe(dev_priv, i) {
1290                 u32 val = I915_READ(DSPCNTR(i));
1291                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1292                         DISPPLANE_SEL_PIPE_SHIFT;
1293                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1294                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295                      plane_name(i), pipe_name(pipe));
1296         }
1297 }
1298
1299 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1300                                     enum pipe pipe)
1301 {
1302         int sprite;
1303
1304         if (INTEL_GEN(dev_priv) >= 9) {
1305                 for_each_sprite(dev_priv, pipe, sprite) {
1306                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1307                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1308                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1309                              sprite, pipe_name(pipe));
1310                 }
1311         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1312                 for_each_sprite(dev_priv, pipe, sprite) {
1313                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1314                         I915_STATE_WARN(val & SP_ENABLE,
1315                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1316                              sprite_name(pipe, sprite), pipe_name(pipe));
1317                 }
1318         } else if (INTEL_GEN(dev_priv) >= 7) {
1319                 u32 val = I915_READ(SPRCTL(pipe));
1320                 I915_STATE_WARN(val & SPRITE_ENABLE,
1321                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322                      plane_name(pipe), pipe_name(pipe));
1323         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1324                 u32 val = I915_READ(DVSCNTR(pipe));
1325                 I915_STATE_WARN(val & DVS_ENABLE,
1326                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327                      plane_name(pipe), pipe_name(pipe));
1328         }
1329 }
1330
1331 static void assert_vblank_disabled(struct drm_crtc *crtc)
1332 {
1333         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1334                 drm_crtc_vblank_put(crtc);
1335 }
1336
1337 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1338                                     enum pipe pipe)
1339 {
1340         u32 val;
1341         bool enabled;
1342
1343         val = I915_READ(PCH_TRANSCONF(pipe));
1344         enabled = !!(val & TRANS_ENABLE);
1345         I915_STATE_WARN(enabled,
1346              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1347              pipe_name(pipe));
1348 }
1349
1350 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1351                             enum pipe pipe, u32 port_sel, u32 val)
1352 {
1353         if ((val & DP_PORT_EN) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv)) {
1357                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1358                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1359                         return false;
1360         } else if (IS_CHERRYVIEW(dev_priv)) {
1361                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & SDVO_ENABLE) == 0)
1374                 return false;
1375
1376         if (HAS_PCH_CPT(dev_priv)) {
1377                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1378                         return false;
1379         } else if (IS_CHERRYVIEW(dev_priv)) {
1380                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1381                         return false;
1382         } else {
1383                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1384                         return false;
1385         }
1386         return true;
1387 }
1388
1389 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1390                               enum pipe pipe, u32 val)
1391 {
1392         if ((val & LVDS_PORT_EN) == 0)
1393                 return false;
1394
1395         if (HAS_PCH_CPT(dev_priv)) {
1396                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1397                         return false;
1398         } else {
1399                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1400                         return false;
1401         }
1402         return true;
1403 }
1404
1405 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1406                               enum pipe pipe, u32 val)
1407 {
1408         if ((val & ADPA_DAC_ENABLE) == 0)
1409                 return false;
1410         if (HAS_PCH_CPT(dev_priv)) {
1411                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1412                         return false;
1413         } else {
1414                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1415                         return false;
1416         }
1417         return true;
1418 }
1419
1420 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1421                                    enum pipe pipe, i915_reg_t reg,
1422                                    u32 port_sel)
1423 {
1424         u32 val = I915_READ(reg);
1425         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1426              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1427              i915_mmio_reg_offset(reg), pipe_name(pipe));
1428
1429         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1430              && (val & DP_PIPEB_SELECT),
1431              "IBX PCH dp port still using transcoder B\n");
1432 }
1433
1434 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1435                                      enum pipe pipe, i915_reg_t reg)
1436 {
1437         u32 val = I915_READ(reg);
1438         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1439              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              i915_mmio_reg_offset(reg), pipe_name(pipe));
1441
1442         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1443              && (val & SDVO_PIPE_B_SELECT),
1444              "IBX PCH hdmi port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1448                                       enum pipe pipe)
1449 {
1450         u32 val;
1451
1452         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1453         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1454         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1455
1456         val = I915_READ(PCH_ADPA);
1457         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1458              "PCH VGA enabled on transcoder %c, should be disabled\n",
1459              pipe_name(pipe));
1460
1461         val = I915_READ(PCH_LVDS);
1462         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1463              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1464              pipe_name(pipe));
1465
1466         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1467         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1468         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1469 }
1470
1471 static void _vlv_enable_pll(struct intel_crtc *crtc,
1472                             const struct intel_crtc_state *pipe_config)
1473 {
1474         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1475         enum pipe pipe = crtc->pipe;
1476
1477         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1478         POSTING_READ(DPLL(pipe));
1479         udelay(150);
1480
1481         if (intel_wait_for_register(dev_priv,
1482                                     DPLL(pipe),
1483                                     DPLL_LOCK_VLV,
1484                                     DPLL_LOCK_VLV,
1485                                     1))
1486                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1487 }
1488
1489 static void vlv_enable_pll(struct intel_crtc *crtc,
1490                            const struct intel_crtc_state *pipe_config)
1491 {
1492         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493         enum pipe pipe = crtc->pipe;
1494
1495         assert_pipe_disabled(dev_priv, pipe);
1496
1497         /* PLL is protected by panel, make sure we can write it */
1498         assert_panel_unlocked(dev_priv, pipe);
1499
1500         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1501                 _vlv_enable_pll(crtc, pipe_config);
1502
1503         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1504         POSTING_READ(DPLL_MD(pipe));
1505 }
1506
1507
1508 static void _chv_enable_pll(struct intel_crtc *crtc,
1509                             const struct intel_crtc_state *pipe_config)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1512         enum pipe pipe = crtc->pipe;
1513         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1514         u32 tmp;
1515
1516         mutex_lock(&dev_priv->sb_lock);
1517
1518         /* Enable back the 10bit clock to display controller */
1519         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1520         tmp |= DPIO_DCLKP_EN;
1521         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1522
1523         mutex_unlock(&dev_priv->sb_lock);
1524
1525         /*
1526          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1527          */
1528         udelay(1);
1529
1530         /* Enable PLL */
1531         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1532
1533         /* Check PLL is locked */
1534         if (intel_wait_for_register(dev_priv,
1535                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1536                                     1))
1537                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1538 }
1539
1540 static void chv_enable_pll(struct intel_crtc *crtc,
1541                            const struct intel_crtc_state *pipe_config)
1542 {
1543         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1544         enum pipe pipe = crtc->pipe;
1545
1546         assert_pipe_disabled(dev_priv, pipe);
1547
1548         /* PLL is protected by panel, make sure we can write it */
1549         assert_panel_unlocked(dev_priv, pipe);
1550
1551         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1552                 _chv_enable_pll(crtc, pipe_config);
1553
1554         if (pipe != PIPE_A) {
1555                 /*
1556                  * WaPixelRepeatModeFixForC0:chv
1557                  *
1558                  * DPLLCMD is AWOL. Use chicken bits to propagate
1559                  * the value from DPLLBMD to either pipe B or C.
1560                  */
1561                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1562                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1563                 I915_WRITE(CBR4_VLV, 0);
1564                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1565
1566                 /*
1567                  * DPLLB VGA mode also seems to cause problems.
1568                  * We should always have it disabled.
1569                  */
1570                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1571         } else {
1572                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1573                 POSTING_READ(DPLL_MD(pipe));
1574         }
1575 }
1576
1577 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1578 {
1579         struct intel_crtc *crtc;
1580         int count = 0;
1581
1582         for_each_intel_crtc(&dev_priv->drm, crtc) {
1583                 count += crtc->base.state->active &&
1584                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1585         }
1586
1587         return count;
1588 }
1589
1590 static void i9xx_enable_pll(struct intel_crtc *crtc,
1591                             const struct intel_crtc_state *crtc_state)
1592 {
1593         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1594         i915_reg_t reg = DPLL(crtc->pipe);
1595         u32 dpll = crtc_state->dpll_hw_state.dpll;
1596         int i;
1597
1598         assert_pipe_disabled(dev_priv, crtc->pipe);
1599
1600         /* PLL is protected by panel, make sure we can write it */
1601         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1602                 assert_panel_unlocked(dev_priv, crtc->pipe);
1603
1604         /* Enable DVO 2x clock on both PLLs if necessary */
1605         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1606                 /*
1607                  * It appears to be important that we don't enable this
1608                  * for the current pipe before otherwise configuring the
1609                  * PLL. No idea how this should be handled if multiple
1610                  * DVO outputs are enabled simultaneosly.
1611                  */
1612                 dpll |= DPLL_DVO_2X_MODE;
1613                 I915_WRITE(DPLL(!crtc->pipe),
1614                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1615         }
1616
1617         /*
1618          * Apparently we need to have VGA mode enabled prior to changing
1619          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1620          * dividers, even though the register value does change.
1621          */
1622         I915_WRITE(reg, 0);
1623
1624         I915_WRITE(reg, dpll);
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_GEN(dev_priv) >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc_state->dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         for (i = 0; i < 3; i++) {
1644                 I915_WRITE(reg, dpll);
1645                 POSTING_READ(reg);
1646                 udelay(150); /* wait for warmup */
1647         }
1648 }
1649
1650 static void i9xx_disable_pll(struct intel_crtc *crtc)
1651 {
1652         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1653         enum pipe pipe = crtc->pipe;
1654
1655         /* Disable DVO 2x clock on both PLLs if necessary */
1656         if (IS_I830(dev_priv) &&
1657             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1658             !intel_num_dvo_pipes(dev_priv)) {
1659                 I915_WRITE(DPLL(PIPE_B),
1660                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1661                 I915_WRITE(DPLL(PIPE_A),
1662                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1663         }
1664
1665         /* Don't disable pipe or pipe PLLs if needed */
1666         if (IS_I830(dev_priv))
1667                 return;
1668
1669         /* Make sure the pipe isn't still relying on us */
1670         assert_pipe_disabled(dev_priv, pipe);
1671
1672         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1673         POSTING_READ(DPLL(pipe));
1674 }
1675
1676 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1677 {
1678         u32 val;
1679
1680         /* Make sure the pipe isn't still relying on us */
1681         assert_pipe_disabled(dev_priv, pipe);
1682
1683         val = DPLL_INTEGRATED_REF_CLK_VLV |
1684                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1685         if (pipe != PIPE_A)
1686                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1687
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690 }
1691
1692 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1693 {
1694         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1695         u32 val;
1696
1697         /* Make sure the pipe isn't still relying on us */
1698         assert_pipe_disabled(dev_priv, pipe);
1699
1700         val = DPLL_SSC_REF_CLK_CHV |
1701                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1702         if (pipe != PIPE_A)
1703                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1704
1705         I915_WRITE(DPLL(pipe), val);
1706         POSTING_READ(DPLL(pipe));
1707
1708         mutex_lock(&dev_priv->sb_lock);
1709
1710         /* Disable 10bit clock to display controller */
1711         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1712         val &= ~DPIO_DCLKP_EN;
1713         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1714
1715         mutex_unlock(&dev_priv->sb_lock);
1716 }
1717
1718 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1719                          struct intel_digital_port *dport,
1720                          unsigned int expected_mask)
1721 {
1722         u32 port_mask;
1723         i915_reg_t dpll_reg;
1724
1725         switch (dport->port) {
1726         case PORT_B:
1727                 port_mask = DPLL_PORTB_READY_MASK;
1728                 dpll_reg = DPLL(0);
1729                 break;
1730         case PORT_C:
1731                 port_mask = DPLL_PORTC_READY_MASK;
1732                 dpll_reg = DPLL(0);
1733                 expected_mask <<= 4;
1734                 break;
1735         case PORT_D:
1736                 port_mask = DPLL_PORTD_READY_MASK;
1737                 dpll_reg = DPIO_PHY_STATUS;
1738                 break;
1739         default:
1740                 BUG();
1741         }
1742
1743         if (intel_wait_for_register(dev_priv,
1744                                     dpll_reg, port_mask, expected_mask,
1745                                     1000))
1746                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1747                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1748 }
1749
1750 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1751                                            enum pipe pipe)
1752 {
1753         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1754                                                                 pipe);
1755         i915_reg_t reg;
1756         uint32_t val, pipeconf_val;
1757
1758         /* Make sure PCH DPLL is enabled */
1759         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1760
1761         /* FDI must be feeding us bits for PCH ports */
1762         assert_fdi_tx_enabled(dev_priv, pipe);
1763         assert_fdi_rx_enabled(dev_priv, pipe);
1764
1765         if (HAS_PCH_CPT(dev_priv)) {
1766                 /* Workaround: Set the timing override bit before enabling the
1767                  * pch transcoder. */
1768                 reg = TRANS_CHICKEN2(pipe);
1769                 val = I915_READ(reg);
1770                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1771                 I915_WRITE(reg, val);
1772         }
1773
1774         reg = PCH_TRANSCONF(pipe);
1775         val = I915_READ(reg);
1776         pipeconf_val = I915_READ(PIPECONF(pipe));
1777
1778         if (HAS_PCH_IBX(dev_priv)) {
1779                 /*
1780                  * Make the BPC in transcoder be consistent with
1781                  * that in pipeconf reg. For HDMI we must use 8bpc
1782                  * here for both 8bpc and 12bpc.
1783                  */
1784                 val &= ~PIPECONF_BPC_MASK;
1785                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1786                         val |= PIPECONF_8BPC;
1787                 else
1788                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1789         }
1790
1791         val &= ~TRANS_INTERLACE_MASK;
1792         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1793                 if (HAS_PCH_IBX(dev_priv) &&
1794                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1795                         val |= TRANS_LEGACY_INTERLACED_ILK;
1796                 else
1797                         val |= TRANS_INTERLACED;
1798         else
1799                 val |= TRANS_PROGRESSIVE;
1800
1801         I915_WRITE(reg, val | TRANS_ENABLE);
1802         if (intel_wait_for_register(dev_priv,
1803                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1804                                     100))
1805                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1806 }
1807
1808 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1809                                       enum transcoder cpu_transcoder)
1810 {
1811         u32 val, pipeconf_val;
1812
1813         /* FDI must be feeding us bits for PCH ports */
1814         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1815         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1816
1817         /* Workaround: set timing override bit. */
1818         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1819         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1820         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1821
1822         val = TRANS_ENABLE;
1823         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1824
1825         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1826             PIPECONF_INTERLACED_ILK)
1827                 val |= TRANS_INTERLACED;
1828         else
1829                 val |= TRANS_PROGRESSIVE;
1830
1831         I915_WRITE(LPT_TRANSCONF, val);
1832         if (intel_wait_for_register(dev_priv,
1833                                     LPT_TRANSCONF,
1834                                     TRANS_STATE_ENABLE,
1835                                     TRANS_STATE_ENABLE,
1836                                     100))
1837                 DRM_ERROR("Failed to enable PCH transcoder\n");
1838 }
1839
1840 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1841                                             enum pipe pipe)
1842 {
1843         i915_reg_t reg;
1844         uint32_t val;
1845
1846         /* FDI relies on the transcoder */
1847         assert_fdi_tx_disabled(dev_priv, pipe);
1848         assert_fdi_rx_disabled(dev_priv, pipe);
1849
1850         /* Ports must be off as well */
1851         assert_pch_ports_disabled(dev_priv, pipe);
1852
1853         reg = PCH_TRANSCONF(pipe);
1854         val = I915_READ(reg);
1855         val &= ~TRANS_ENABLE;
1856         I915_WRITE(reg, val);
1857         /* wait for PCH transcoder off, transcoder state */
1858         if (intel_wait_for_register(dev_priv,
1859                                     reg, TRANS_STATE_ENABLE, 0,
1860                                     50))
1861                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1862
1863         if (HAS_PCH_CPT(dev_priv)) {
1864                 /* Workaround: Clear the timing override chicken bit again. */
1865                 reg = TRANS_CHICKEN2(pipe);
1866                 val = I915_READ(reg);
1867                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1868                 I915_WRITE(reg, val);
1869         }
1870 }
1871
1872 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1873 {
1874         u32 val;
1875
1876         val = I915_READ(LPT_TRANSCONF);
1877         val &= ~TRANS_ENABLE;
1878         I915_WRITE(LPT_TRANSCONF, val);
1879         /* wait for PCH transcoder off, transcoder state */
1880         if (intel_wait_for_register(dev_priv,
1881                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1882                                     50))
1883                 DRM_ERROR("Failed to disable PCH transcoder\n");
1884
1885         /* Workaround: clear timing override bit. */
1886         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1887         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1888         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1889 }
1890
1891 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1892 {
1893         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1894
1895         WARN_ON(!crtc->config->has_pch_encoder);
1896
1897         if (HAS_PCH_LPT(dev_priv))
1898                 return PIPE_A;
1899         else
1900                 return crtc->pipe;
1901 }
1902
1903 /**
1904  * intel_enable_pipe - enable a pipe, asserting requirements
1905  * @crtc: crtc responsible for the pipe
1906  *
1907  * Enable @crtc's pipe, making sure that various hardware specific requirements
1908  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1909  */
1910 static void intel_enable_pipe(struct intel_crtc *crtc)
1911 {
1912         struct drm_device *dev = crtc->base.dev;
1913         struct drm_i915_private *dev_priv = to_i915(dev);
1914         enum pipe pipe = crtc->pipe;
1915         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1916         i915_reg_t reg;
1917         u32 val;
1918
1919         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1920
1921         assert_planes_disabled(dev_priv, pipe);
1922         assert_cursor_disabled(dev_priv, pipe);
1923         assert_sprites_disabled(dev_priv, pipe);
1924
1925         /*
1926          * A pipe without a PLL won't actually be able to drive bits from
1927          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1928          * need the check.
1929          */
1930         if (HAS_GMCH_DISPLAY(dev_priv)) {
1931                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1932                         assert_dsi_pll_enabled(dev_priv);
1933                 else
1934                         assert_pll_enabled(dev_priv, pipe);
1935         } else {
1936                 if (crtc->config->has_pch_encoder) {
1937                         /* if driving the PCH, we need FDI enabled */
1938                         assert_fdi_rx_pll_enabled(dev_priv,
1939                                                   intel_crtc_pch_transcoder(crtc));
1940                         assert_fdi_tx_pll_enabled(dev_priv,
1941                                                   (enum pipe) cpu_transcoder);
1942                 }
1943                 /* FIXME: assert CPU port conditions for SNB+ */
1944         }
1945
1946         reg = PIPECONF(cpu_transcoder);
1947         val = I915_READ(reg);
1948         if (val & PIPECONF_ENABLE) {
1949                 /* we keep both pipes enabled on 830 */
1950                 WARN_ON(!IS_I830(dev_priv));
1951                 return;
1952         }
1953
1954         I915_WRITE(reg, val | PIPECONF_ENABLE);
1955         POSTING_READ(reg);
1956
1957         /*
1958          * Until the pipe starts PIPEDSL reads will return a stale value,
1959          * which causes an apparent vblank timestamp jump when PIPEDSL
1960          * resets to its proper value. That also messes up the frame count
1961          * when it's derived from the timestamps. So let's wait for the
1962          * pipe to start properly before we call drm_crtc_vblank_on()
1963          */
1964         if (dev->max_vblank_count == 0)
1965                 intel_wait_for_pipe_scanline_moving(crtc);
1966 }
1967
1968 /**
1969  * intel_disable_pipe - disable a pipe, asserting requirements
1970  * @crtc: crtc whose pipes is to be disabled
1971  *
1972  * Disable the pipe of @crtc, making sure that various hardware
1973  * specific requirements are met, if applicable, e.g. plane
1974  * disabled, panel fitter off, etc.
1975  *
1976  * Will wait until the pipe has shut down before returning.
1977  */
1978 static void intel_disable_pipe(struct intel_crtc *crtc)
1979 {
1980         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1981         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1982         enum pipe pipe = crtc->pipe;
1983         i915_reg_t reg;
1984         u32 val;
1985
1986         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1987
1988         /*
1989          * Make sure planes won't keep trying to pump pixels to us,
1990          * or we might hang the display.
1991          */
1992         assert_planes_disabled(dev_priv, pipe);
1993         assert_cursor_disabled(dev_priv, pipe);
1994         assert_sprites_disabled(dev_priv, pipe);
1995
1996         reg = PIPECONF(cpu_transcoder);
1997         val = I915_READ(reg);
1998         if ((val & PIPECONF_ENABLE) == 0)
1999                 return;
2000
2001         /*
2002          * Double wide has implications for planes
2003          * so best keep it disabled when not needed.
2004          */
2005         if (crtc->config->double_wide)
2006                 val &= ~PIPECONF_DOUBLE_WIDE;
2007
2008         /* Don't disable pipe or pipe PLLs if needed */
2009         if (!IS_I830(dev_priv))
2010                 val &= ~PIPECONF_ENABLE;
2011
2012         I915_WRITE(reg, val);
2013         if ((val & PIPECONF_ENABLE) == 0)
2014                 intel_wait_for_pipe_off(crtc);
2015 }
2016
2017 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2018 {
2019         return IS_GEN2(dev_priv) ? 2048 : 4096;
2020 }
2021
2022 static unsigned int
2023 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2024 {
2025         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2026         unsigned int cpp = fb->format->cpp[plane];
2027
2028         switch (fb->modifier) {
2029         case DRM_FORMAT_MOD_LINEAR:
2030                 return cpp;
2031         case I915_FORMAT_MOD_X_TILED:
2032                 if (IS_GEN2(dev_priv))
2033                         return 128;
2034                 else
2035                         return 512;
2036         case I915_FORMAT_MOD_Y_TILED_CCS:
2037                 if (plane == 1)
2038                         return 128;
2039                 /* fall through */
2040         case I915_FORMAT_MOD_Y_TILED:
2041                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2042                         return 128;
2043                 else
2044                         return 512;
2045         case I915_FORMAT_MOD_Yf_TILED_CCS:
2046                 if (plane == 1)
2047                         return 128;
2048                 /* fall through */
2049         case I915_FORMAT_MOD_Yf_TILED:
2050                 switch (cpp) {
2051                 case 1:
2052                         return 64;
2053                 case 2:
2054                 case 4:
2055                         return 128;
2056                 case 8:
2057                 case 16:
2058                         return 256;
2059                 default:
2060                         MISSING_CASE(cpp);
2061                         return cpp;
2062                 }
2063                 break;
2064         default:
2065                 MISSING_CASE(fb->modifier);
2066                 return cpp;
2067         }
2068 }
2069
2070 static unsigned int
2071 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2072 {
2073         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2074                 return 1;
2075         else
2076                 return intel_tile_size(to_i915(fb->dev)) /
2077                         intel_tile_width_bytes(fb, plane);
2078 }
2079
2080 /* Return the tile dimensions in pixel units */
2081 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2082                             unsigned int *tile_width,
2083                             unsigned int *tile_height)
2084 {
2085         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2086         unsigned int cpp = fb->format->cpp[plane];
2087
2088         *tile_width = tile_width_bytes / cpp;
2089         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2090 }
2091
2092 unsigned int
2093 intel_fb_align_height(const struct drm_framebuffer *fb,
2094                       int plane, unsigned int height)
2095 {
2096         unsigned int tile_height = intel_tile_height(fb, plane);
2097
2098         return ALIGN(height, tile_height);
2099 }
2100
2101 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2102 {
2103         unsigned int size = 0;
2104         int i;
2105
2106         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2107                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2108
2109         return size;
2110 }
2111
2112 static void
2113 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2114                         const struct drm_framebuffer *fb,
2115                         unsigned int rotation)
2116 {
2117         view->type = I915_GGTT_VIEW_NORMAL;
2118         if (drm_rotation_90_or_270(rotation)) {
2119                 view->type = I915_GGTT_VIEW_ROTATED;
2120                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2121         }
2122 }
2123
2124 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2125 {
2126         if (IS_I830(dev_priv))
2127                 return 16 * 1024;
2128         else if (IS_I85X(dev_priv))
2129                 return 256;
2130         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2131                 return 32;
2132         else
2133                 return 4 * 1024;
2134 }
2135
2136 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2137 {
2138         if (INTEL_INFO(dev_priv)->gen >= 9)
2139                 return 256 * 1024;
2140         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2141                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2142                 return 128 * 1024;
2143         else if (INTEL_INFO(dev_priv)->gen >= 4)
2144                 return 4 * 1024;
2145         else
2146                 return 0;
2147 }
2148
2149 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2150                                          int plane)
2151 {
2152         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2153
2154         /* AUX_DIST needs only 4K alignment */
2155         if (plane == 1)
2156                 return 4096;
2157
2158         switch (fb->modifier) {
2159         case DRM_FORMAT_MOD_LINEAR:
2160                 return intel_linear_alignment(dev_priv);
2161         case I915_FORMAT_MOD_X_TILED:
2162                 if (INTEL_GEN(dev_priv) >= 9)
2163                         return 256 * 1024;
2164                 return 0;
2165         case I915_FORMAT_MOD_Y_TILED_CCS:
2166         case I915_FORMAT_MOD_Yf_TILED_CCS:
2167         case I915_FORMAT_MOD_Y_TILED:
2168         case I915_FORMAT_MOD_Yf_TILED:
2169                 return 1 * 1024 * 1024;
2170         default:
2171                 MISSING_CASE(fb->modifier);
2172                 return 0;
2173         }
2174 }
2175
2176 struct i915_vma *
2177 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2178 {
2179         struct drm_device *dev = fb->dev;
2180         struct drm_i915_private *dev_priv = to_i915(dev);
2181         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2182         struct i915_ggtt_view view;
2183         struct i915_vma *vma;
2184         u32 alignment;
2185
2186         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2187
2188         alignment = intel_surf_alignment(fb, 0);
2189
2190         intel_fill_fb_ggtt_view(&view, fb, rotation);
2191
2192         /* Note that the w/a also requires 64 PTE of padding following the
2193          * bo. We currently fill all unused PTE with the shadow page and so
2194          * we should always have valid PTE following the scanout preventing
2195          * the VT-d warning.
2196          */
2197         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2198                 alignment = 256 * 1024;
2199
2200         /*
2201          * Global gtt pte registers are special registers which actually forward
2202          * writes to a chunk of system memory. Which means that there is no risk
2203          * that the register values disappear as soon as we call
2204          * intel_runtime_pm_put(), so it is correct to wrap only the
2205          * pin/unpin/fence and not more.
2206          */
2207         intel_runtime_pm_get(dev_priv);
2208
2209         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2210
2211         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2212         if (IS_ERR(vma))
2213                 goto err;
2214
2215         if (i915_vma_is_map_and_fenceable(vma)) {
2216                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2217                  * fence, whereas 965+ only requires a fence if using
2218                  * framebuffer compression.  For simplicity, we always, when
2219                  * possible, install a fence as the cost is not that onerous.
2220                  *
2221                  * If we fail to fence the tiled scanout, then either the
2222                  * modeset will reject the change (which is highly unlikely as
2223                  * the affected systems, all but one, do not have unmappable
2224                  * space) or we will not be able to enable full powersaving
2225                  * techniques (also likely not to apply due to various limits
2226                  * FBC and the like impose on the size of the buffer, which
2227                  * presumably we violated anyway with this unmappable buffer).
2228                  * Anyway, it is presumably better to stumble onwards with
2229                  * something and try to run the system in a "less than optimal"
2230                  * mode that matches the user configuration.
2231                  */
2232                 i915_vma_pin_fence(vma);
2233         }
2234
2235         i915_vma_get(vma);
2236 err:
2237         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2238
2239         intel_runtime_pm_put(dev_priv);
2240         return vma;
2241 }
2242
2243 void intel_unpin_fb_vma(struct i915_vma *vma)
2244 {
2245         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2246
2247         i915_vma_unpin_fence(vma);
2248         i915_gem_object_unpin_from_display_plane(vma);
2249         i915_vma_put(vma);
2250 }
2251
2252 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2253                           unsigned int rotation)
2254 {
2255         if (drm_rotation_90_or_270(rotation))
2256                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2257         else
2258                 return fb->pitches[plane];
2259 }
2260
2261 /*
2262  * Convert the x/y offsets into a linear offset.
2263  * Only valid with 0/180 degree rotation, which is fine since linear
2264  * offset is only used with linear buffers on pre-hsw and tiled buffers
2265  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2266  */
2267 u32 intel_fb_xy_to_linear(int x, int y,
2268                           const struct intel_plane_state *state,
2269                           int plane)
2270 {
2271         const struct drm_framebuffer *fb = state->base.fb;
2272         unsigned int cpp = fb->format->cpp[plane];
2273         unsigned int pitch = fb->pitches[plane];
2274
2275         return y * pitch + x * cpp;
2276 }
2277
2278 /*
2279  * Add the x/y offsets derived from fb->offsets[] to the user
2280  * specified plane src x/y offsets. The resulting x/y offsets
2281  * specify the start of scanout from the beginning of the gtt mapping.
2282  */
2283 void intel_add_fb_offsets(int *x, int *y,
2284                           const struct intel_plane_state *state,
2285                           int plane)
2286
2287 {
2288         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2289         unsigned int rotation = state->base.rotation;
2290
2291         if (drm_rotation_90_or_270(rotation)) {
2292                 *x += intel_fb->rotated[plane].x;
2293                 *y += intel_fb->rotated[plane].y;
2294         } else {
2295                 *x += intel_fb->normal[plane].x;
2296                 *y += intel_fb->normal[plane].y;
2297         }
2298 }
2299
2300 static u32 __intel_adjust_tile_offset(int *x, int *y,
2301                                       unsigned int tile_width,
2302                                       unsigned int tile_height,
2303                                       unsigned int tile_size,
2304                                       unsigned int pitch_tiles,
2305                                       u32 old_offset,
2306                                       u32 new_offset)
2307 {
2308         unsigned int pitch_pixels = pitch_tiles * tile_width;
2309         unsigned int tiles;
2310
2311         WARN_ON(old_offset & (tile_size - 1));
2312         WARN_ON(new_offset & (tile_size - 1));
2313         WARN_ON(new_offset > old_offset);
2314
2315         tiles = (old_offset - new_offset) / tile_size;
2316
2317         *y += tiles / pitch_tiles * tile_height;
2318         *x += tiles % pitch_tiles * tile_width;
2319
2320         /* minimize x in case it got needlessly big */
2321         *y += *x / pitch_pixels * tile_height;
2322         *x %= pitch_pixels;
2323
2324         return new_offset;
2325 }
2326
2327 static u32 _intel_adjust_tile_offset(int *x, int *y,
2328                                      const struct drm_framebuffer *fb, int plane,
2329                                      unsigned int rotation,
2330                                      u32 old_offset, u32 new_offset)
2331 {
2332         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2333         unsigned int cpp = fb->format->cpp[plane];
2334         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2335
2336         WARN_ON(new_offset > old_offset);
2337
2338         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2339                 unsigned int tile_size, tile_width, tile_height;
2340                 unsigned int pitch_tiles;
2341
2342                 tile_size = intel_tile_size(dev_priv);
2343                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2344
2345                 if (drm_rotation_90_or_270(rotation)) {
2346                         pitch_tiles = pitch / tile_height;
2347                         swap(tile_width, tile_height);
2348                 } else {
2349                         pitch_tiles = pitch / (tile_width * cpp);
2350                 }
2351
2352                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2353                                            tile_size, pitch_tiles,
2354                                            old_offset, new_offset);
2355         } else {
2356                 old_offset += *y * pitch + *x * cpp;
2357
2358                 *y = (old_offset - new_offset) / pitch;
2359                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2360         }
2361
2362         return new_offset;
2363 }
2364
2365 /*
2366  * Adjust the tile offset by moving the difference into
2367  * the x/y offsets.
2368  */
2369 static u32 intel_adjust_tile_offset(int *x, int *y,
2370                                     const struct intel_plane_state *state, int plane,
2371                                     u32 old_offset, u32 new_offset)
2372 {
2373         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2374                                          state->base.rotation,
2375                                          old_offset, new_offset);
2376 }
2377
2378 /*
2379  * Computes the linear offset to the base tile and adjusts
2380  * x, y. bytes per pixel is assumed to be a power-of-two.
2381  *
2382  * In the 90/270 rotated case, x and y are assumed
2383  * to be already rotated to match the rotated GTT view, and
2384  * pitch is the tile_height aligned framebuffer height.
2385  *
2386  * This function is used when computing the derived information
2387  * under intel_framebuffer, so using any of that information
2388  * here is not allowed. Anything under drm_framebuffer can be
2389  * used. This is why the user has to pass in the pitch since it
2390  * is specified in the rotated orientation.
2391  */
2392 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2393                                       int *x, int *y,
2394                                       const struct drm_framebuffer *fb, int plane,
2395                                       unsigned int pitch,
2396                                       unsigned int rotation,
2397                                       u32 alignment)
2398 {
2399         uint64_t fb_modifier = fb->modifier;
2400         unsigned int cpp = fb->format->cpp[plane];
2401         u32 offset, offset_aligned;
2402
2403         if (alignment)
2404                 alignment--;
2405
2406         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2407                 unsigned int tile_size, tile_width, tile_height;
2408                 unsigned int tile_rows, tiles, pitch_tiles;
2409
2410                 tile_size = intel_tile_size(dev_priv);
2411                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2412
2413                 if (drm_rotation_90_or_270(rotation)) {
2414                         pitch_tiles = pitch / tile_height;
2415                         swap(tile_width, tile_height);
2416                 } else {
2417                         pitch_tiles = pitch / (tile_width * cpp);
2418                 }
2419
2420                 tile_rows = *y / tile_height;
2421                 *y %= tile_height;
2422
2423                 tiles = *x / tile_width;
2424                 *x %= tile_width;
2425
2426                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2427                 offset_aligned = offset & ~alignment;
2428
2429                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2430                                            tile_size, pitch_tiles,
2431                                            offset, offset_aligned);
2432         } else {
2433                 offset = *y * pitch + *x * cpp;
2434                 offset_aligned = offset & ~alignment;
2435
2436                 *y = (offset & alignment) / pitch;
2437                 *x = ((offset & alignment) - *y * pitch) / cpp;
2438         }
2439
2440         return offset_aligned;
2441 }
2442
2443 u32 intel_compute_tile_offset(int *x, int *y,
2444                               const struct intel_plane_state *state,
2445                               int plane)
2446 {
2447         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2448         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2449         const struct drm_framebuffer *fb = state->base.fb;
2450         unsigned int rotation = state->base.rotation;
2451         int pitch = intel_fb_pitch(fb, plane, rotation);
2452         u32 alignment;
2453
2454         if (intel_plane->id == PLANE_CURSOR)
2455                 alignment = intel_cursor_alignment(dev_priv);
2456         else
2457                 alignment = intel_surf_alignment(fb, plane);
2458
2459         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2460                                           rotation, alignment);
2461 }
2462
2463 /* Convert the fb->offset[] into x/y offsets */
2464 static int intel_fb_offset_to_xy(int *x, int *y,
2465                                  const struct drm_framebuffer *fb, int plane)
2466 {
2467         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2468
2469         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2470             fb->offsets[plane] % intel_tile_size(dev_priv))
2471                 return -EINVAL;
2472
2473         *x = 0;
2474         *y = 0;
2475
2476         _intel_adjust_tile_offset(x, y,
2477                                   fb, plane, DRM_MODE_ROTATE_0,
2478                                   fb->offsets[plane], 0);
2479
2480         return 0;
2481 }
2482
2483 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2484 {
2485         switch (fb_modifier) {
2486         case I915_FORMAT_MOD_X_TILED:
2487                 return I915_TILING_X;
2488         case I915_FORMAT_MOD_Y_TILED:
2489         case I915_FORMAT_MOD_Y_TILED_CCS:
2490                 return I915_TILING_Y;
2491         default:
2492                 return I915_TILING_NONE;
2493         }
2494 }
2495
2496 static const struct drm_format_info ccs_formats[] = {
2497         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2498         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2499         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2500         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2501 };
2502
2503 static const struct drm_format_info *
2504 lookup_format_info(const struct drm_format_info formats[],
2505                    int num_formats, u32 format)
2506 {
2507         int i;
2508
2509         for (i = 0; i < num_formats; i++) {
2510                 if (formats[i].format == format)
2511                         return &formats[i];
2512         }
2513
2514         return NULL;
2515 }
2516
2517 static const struct drm_format_info *
2518 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2519 {
2520         switch (cmd->modifier[0]) {
2521         case I915_FORMAT_MOD_Y_TILED_CCS:
2522         case I915_FORMAT_MOD_Yf_TILED_CCS:
2523                 return lookup_format_info(ccs_formats,
2524                                           ARRAY_SIZE(ccs_formats),
2525                                           cmd->pixel_format);
2526         default:
2527                 return NULL;
2528         }
2529 }
2530
2531 static int
2532 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2533                    struct drm_framebuffer *fb)
2534 {
2535         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2536         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2537         u32 gtt_offset_rotated = 0;
2538         unsigned int max_size = 0;
2539         int i, num_planes = fb->format->num_planes;
2540         unsigned int tile_size = intel_tile_size(dev_priv);
2541
2542         for (i = 0; i < num_planes; i++) {
2543                 unsigned int width, height;
2544                 unsigned int cpp, size;
2545                 u32 offset;
2546                 int x, y;
2547                 int ret;
2548
2549                 cpp = fb->format->cpp[i];
2550                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2551                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2552
2553                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2554                 if (ret) {
2555                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2556                                       i, fb->offsets[i]);
2557                         return ret;
2558                 }
2559
2560                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2561                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2562                         int hsub = fb->format->hsub;
2563                         int vsub = fb->format->vsub;
2564                         int tile_width, tile_height;
2565                         int main_x, main_y;
2566                         int ccs_x, ccs_y;
2567
2568                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2569                         tile_width *= hsub;
2570                         tile_height *= vsub;
2571
2572                         ccs_x = (x * hsub) % tile_width;
2573                         ccs_y = (y * vsub) % tile_height;
2574                         main_x = intel_fb->normal[0].x % tile_width;
2575                         main_y = intel_fb->normal[0].y % tile_height;
2576
2577                         /*
2578                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2579                          * x/y offsets must match between CCS and the main surface.
2580                          */
2581                         if (main_x != ccs_x || main_y != ccs_y) {
2582                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2583                                               main_x, main_y,
2584                                               ccs_x, ccs_y,
2585                                               intel_fb->normal[0].x,
2586                                               intel_fb->normal[0].y,
2587                                               x, y);
2588                                 return -EINVAL;
2589                         }
2590                 }
2591
2592                 /*
2593                  * The fence (if used) is aligned to the start of the object
2594                  * so having the framebuffer wrap around across the edge of the
2595                  * fenced region doesn't really work. We have no API to configure
2596                  * the fence start offset within the object (nor could we probably
2597                  * on gen2/3). So it's just easier if we just require that the
2598                  * fb layout agrees with the fence layout. We already check that the
2599                  * fb stride matches the fence stride elsewhere.
2600                  */
2601                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2602                     (x + width) * cpp > fb->pitches[i]) {
2603                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2604                                       i, fb->offsets[i]);
2605                         return -EINVAL;
2606                 }
2607
2608                 /*
2609                  * First pixel of the framebuffer from
2610                  * the start of the normal gtt mapping.
2611                  */
2612                 intel_fb->normal[i].x = x;
2613                 intel_fb->normal[i].y = y;
2614
2615                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2616                                                     fb, i, fb->pitches[i],
2617                                                     DRM_MODE_ROTATE_0, tile_size);
2618                 offset /= tile_size;
2619
2620                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2621                         unsigned int tile_width, tile_height;
2622                         unsigned int pitch_tiles;
2623                         struct drm_rect r;
2624
2625                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2626
2627                         rot_info->plane[i].offset = offset;
2628                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2629                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2630                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2631
2632                         intel_fb->rotated[i].pitch =
2633                                 rot_info->plane[i].height * tile_height;
2634
2635                         /* how many tiles does this plane need */
2636                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2637                         /*
2638                          * If the plane isn't horizontally tile aligned,
2639                          * we need one more tile.
2640                          */
2641                         if (x != 0)
2642                                 size++;
2643
2644                         /* rotate the x/y offsets to match the GTT view */
2645                         r.x1 = x;
2646                         r.y1 = y;
2647                         r.x2 = x + width;
2648                         r.y2 = y + height;
2649                         drm_rect_rotate(&r,
2650                                         rot_info->plane[i].width * tile_width,
2651                                         rot_info->plane[i].height * tile_height,
2652                                         DRM_MODE_ROTATE_270);
2653                         x = r.x1;
2654                         y = r.y1;
2655
2656                         /* rotate the tile dimensions to match the GTT view */
2657                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2658                         swap(tile_width, tile_height);
2659
2660                         /*
2661                          * We only keep the x/y offsets, so push all of the
2662                          * gtt offset into the x/y offsets.
2663                          */
2664                         __intel_adjust_tile_offset(&x, &y,
2665                                                    tile_width, tile_height,
2666                                                    tile_size, pitch_tiles,
2667                                                    gtt_offset_rotated * tile_size, 0);
2668
2669                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2670
2671                         /*
2672                          * First pixel of the framebuffer from
2673                          * the start of the rotated gtt mapping.
2674                          */
2675                         intel_fb->rotated[i].x = x;
2676                         intel_fb->rotated[i].y = y;
2677                 } else {
2678                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2679                                             x * cpp, tile_size);
2680                 }
2681
2682                 /* how many tiles in total needed in the bo */
2683                 max_size = max(max_size, offset + size);
2684         }
2685
2686         if (max_size * tile_size > intel_fb->obj->base.size) {
2687                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2688                               max_size * tile_size, intel_fb->obj->base.size);
2689                 return -EINVAL;
2690         }
2691
2692         return 0;
2693 }
2694
2695 static int i9xx_format_to_fourcc(int format)
2696 {
2697         switch (format) {
2698         case DISPPLANE_8BPP:
2699                 return DRM_FORMAT_C8;
2700         case DISPPLANE_BGRX555:
2701                 return DRM_FORMAT_XRGB1555;
2702         case DISPPLANE_BGRX565:
2703                 return DRM_FORMAT_RGB565;
2704         default:
2705         case DISPPLANE_BGRX888:
2706                 return DRM_FORMAT_XRGB8888;
2707         case DISPPLANE_RGBX888:
2708                 return DRM_FORMAT_XBGR8888;
2709         case DISPPLANE_BGRX101010:
2710                 return DRM_FORMAT_XRGB2101010;
2711         case DISPPLANE_RGBX101010:
2712                 return DRM_FORMAT_XBGR2101010;
2713         }
2714 }
2715
2716 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2717 {
2718         switch (format) {
2719         case PLANE_CTL_FORMAT_RGB_565:
2720                 return DRM_FORMAT_RGB565;
2721         default:
2722         case PLANE_CTL_FORMAT_XRGB_8888:
2723                 if (rgb_order) {
2724                         if (alpha)
2725                                 return DRM_FORMAT_ABGR8888;
2726                         else
2727                                 return DRM_FORMAT_XBGR8888;
2728                 } else {
2729                         if (alpha)
2730                                 return DRM_FORMAT_ARGB8888;
2731                         else
2732                                 return DRM_FORMAT_XRGB8888;
2733                 }
2734         case PLANE_CTL_FORMAT_XRGB_2101010:
2735                 if (rgb_order)
2736                         return DRM_FORMAT_XBGR2101010;
2737                 else
2738                         return DRM_FORMAT_XRGB2101010;
2739         }
2740 }
2741
2742 static bool
2743 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2744                               struct intel_initial_plane_config *plane_config)
2745 {
2746         struct drm_device *dev = crtc->base.dev;
2747         struct drm_i915_private *dev_priv = to_i915(dev);
2748         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2749         struct drm_i915_gem_object *obj = NULL;
2750         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2751         struct drm_framebuffer *fb = &plane_config->fb->base;
2752         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2753         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2754                                     PAGE_SIZE);
2755
2756         size_aligned -= base_aligned;
2757
2758         if (plane_config->size == 0)
2759                 return false;
2760
2761         /* If the FB is too big, just don't use it since fbdev is not very
2762          * important and we should probably use that space with FBC or other
2763          * features. */
2764         if (size_aligned * 2 > ggtt->stolen_usable_size)
2765                 return false;
2766
2767         mutex_lock(&dev->struct_mutex);
2768         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2769                                                              base_aligned,
2770                                                              base_aligned,
2771                                                              size_aligned);
2772         mutex_unlock(&dev->struct_mutex);
2773         if (!obj)
2774                 return false;
2775
2776         if (plane_config->tiling == I915_TILING_X)
2777                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2778
2779         mode_cmd.pixel_format = fb->format->format;
2780         mode_cmd.width = fb->width;
2781         mode_cmd.height = fb->height;
2782         mode_cmd.pitches[0] = fb->pitches[0];
2783         mode_cmd.modifier[0] = fb->modifier;
2784         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2785
2786         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2787                 DRM_DEBUG_KMS("intel fb init failed\n");
2788                 goto out_unref_obj;
2789         }
2790
2791
2792         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2793         return true;
2794
2795 out_unref_obj:
2796         i915_gem_object_put(obj);
2797         return false;
2798 }
2799
2800 static void
2801 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2802                         struct intel_plane_state *plane_state,
2803                         bool visible)
2804 {
2805         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2806
2807         plane_state->base.visible = visible;
2808
2809         /* FIXME pre-g4x don't work like this */
2810         if (visible) {
2811                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2812                 crtc_state->active_planes |= BIT(plane->id);
2813         } else {
2814                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2815                 crtc_state->active_planes &= ~BIT(plane->id);
2816         }
2817
2818         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2819                       crtc_state->base.crtc->name,
2820                       crtc_state->active_planes);
2821 }
2822
2823 static void
2824 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2825                              struct intel_initial_plane_config *plane_config)
2826 {
2827         struct drm_device *dev = intel_crtc->base.dev;
2828         struct drm_i915_private *dev_priv = to_i915(dev);
2829         struct drm_crtc *c;
2830         struct drm_i915_gem_object *obj;
2831         struct drm_plane *primary = intel_crtc->base.primary;
2832         struct drm_plane_state *plane_state = primary->state;
2833         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2834         struct intel_plane *intel_plane = to_intel_plane(primary);
2835         struct intel_plane_state *intel_state =
2836                 to_intel_plane_state(plane_state);
2837         struct drm_framebuffer *fb;
2838
2839         if (!plane_config->fb)
2840                 return;
2841
2842         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2843                 fb = &plane_config->fb->base;
2844                 goto valid_fb;
2845         }
2846
2847         kfree(plane_config->fb);
2848
2849         /*
2850          * Failed to alloc the obj, check to see if we should share
2851          * an fb with another CRTC instead
2852          */
2853         for_each_crtc(dev, c) {
2854                 struct intel_plane_state *state;
2855
2856                 if (c == &intel_crtc->base)
2857                         continue;
2858
2859                 if (!to_intel_crtc(c)->active)
2860                         continue;
2861
2862                 state = to_intel_plane_state(c->primary->state);
2863                 if (!state->vma)
2864                         continue;
2865
2866                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2867                         fb = c->primary->fb;
2868                         drm_framebuffer_get(fb);
2869                         goto valid_fb;
2870                 }
2871         }
2872
2873         /*
2874          * We've failed to reconstruct the BIOS FB.  Current display state
2875          * indicates that the primary plane is visible, but has a NULL FB,
2876          * which will lead to problems later if we don't fix it up.  The
2877          * simplest solution is to just disable the primary plane now and
2878          * pretend the BIOS never had it enabled.
2879          */
2880         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2881                                 to_intel_plane_state(plane_state),
2882                                 false);
2883         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2884         trace_intel_disable_plane(primary, intel_crtc);
2885         intel_plane->disable_plane(intel_plane, intel_crtc);
2886
2887         return;
2888
2889 valid_fb:
2890         mutex_lock(&dev->struct_mutex);
2891         intel_state->vma =
2892                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2893         mutex_unlock(&dev->struct_mutex);
2894         if (IS_ERR(intel_state->vma)) {
2895                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2896                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2897
2898                 intel_state->vma = NULL;
2899                 drm_framebuffer_put(fb);
2900                 return;
2901         }
2902
2903         plane_state->src_x = 0;
2904         plane_state->src_y = 0;
2905         plane_state->src_w = fb->width << 16;
2906         plane_state->src_h = fb->height << 16;
2907
2908         plane_state->crtc_x = 0;
2909         plane_state->crtc_y = 0;
2910         plane_state->crtc_w = fb->width;
2911         plane_state->crtc_h = fb->height;
2912
2913         intel_state->base.src = drm_plane_state_src(plane_state);
2914         intel_state->base.dst = drm_plane_state_dest(plane_state);
2915
2916         obj = intel_fb_obj(fb);
2917         if (i915_gem_object_is_tiled(obj))
2918                 dev_priv->preserve_bios_swizzle = true;
2919
2920         drm_framebuffer_get(fb);
2921         primary->fb = primary->state->fb = fb;
2922         primary->crtc = primary->state->crtc = &intel_crtc->base;
2923
2924         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2925                                 to_intel_plane_state(plane_state),
2926                                 true);
2927
2928         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2929                   &obj->frontbuffer_bits);
2930 }
2931
2932 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2933                                unsigned int rotation)
2934 {
2935         int cpp = fb->format->cpp[plane];
2936
2937         switch (fb->modifier) {
2938         case DRM_FORMAT_MOD_LINEAR:
2939         case I915_FORMAT_MOD_X_TILED:
2940                 switch (cpp) {
2941                 case 8:
2942                         return 4096;
2943                 case 4:
2944                 case 2:
2945                 case 1:
2946                         return 8192;
2947                 default:
2948                         MISSING_CASE(cpp);
2949                         break;
2950                 }
2951                 break;
2952         case I915_FORMAT_MOD_Y_TILED_CCS:
2953         case I915_FORMAT_MOD_Yf_TILED_CCS:
2954                 /* FIXME AUX plane? */
2955         case I915_FORMAT_MOD_Y_TILED:
2956         case I915_FORMAT_MOD_Yf_TILED:
2957                 switch (cpp) {
2958                 case 8:
2959                         return 2048;
2960                 case 4:
2961                         return 4096;
2962                 case 2:
2963                 case 1:
2964                         return 8192;
2965                 default:
2966                         MISSING_CASE(cpp);
2967                         break;
2968                 }
2969                 break;
2970         default:
2971                 MISSING_CASE(fb->modifier);
2972         }
2973
2974         return 2048;
2975 }
2976
2977 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2978                                            int main_x, int main_y, u32 main_offset)
2979 {
2980         const struct drm_framebuffer *fb = plane_state->base.fb;
2981         int hsub = fb->format->hsub;
2982         int vsub = fb->format->vsub;
2983         int aux_x = plane_state->aux.x;
2984         int aux_y = plane_state->aux.y;
2985         u32 aux_offset = plane_state->aux.offset;
2986         u32 alignment = intel_surf_alignment(fb, 1);
2987
2988         while (aux_offset >= main_offset && aux_y <= main_y) {
2989                 int x, y;
2990
2991                 if (aux_x == main_x && aux_y == main_y)
2992                         break;
2993
2994                 if (aux_offset == 0)
2995                         break;
2996
2997                 x = aux_x / hsub;
2998                 y = aux_y / vsub;
2999                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
3000                                                       aux_offset, aux_offset - alignment);
3001                 aux_x = x * hsub + aux_x % hsub;
3002                 aux_y = y * vsub + aux_y % vsub;
3003         }
3004
3005         if (aux_x != main_x || aux_y != main_y)
3006                 return false;
3007
3008         plane_state->aux.offset = aux_offset;
3009         plane_state->aux.x = aux_x;
3010         plane_state->aux.y = aux_y;
3011
3012         return true;
3013 }
3014
3015 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3016 {
3017         const struct drm_framebuffer *fb = plane_state->base.fb;
3018         unsigned int rotation = plane_state->base.rotation;
3019         int x = plane_state->base.src.x1 >> 16;
3020         int y = plane_state->base.src.y1 >> 16;
3021         int w = drm_rect_width(&plane_state->base.src) >> 16;
3022         int h = drm_rect_height(&plane_state->base.src) >> 16;
3023         int max_width = skl_max_plane_width(fb, 0, rotation);
3024         int max_height = 4096;
3025         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3026
3027         if (w > max_width || h > max_height) {
3028                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3029                               w, h, max_width, max_height);
3030                 return -EINVAL;
3031         }
3032
3033         intel_add_fb_offsets(&x, &y, plane_state, 0);
3034         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3035         alignment = intel_surf_alignment(fb, 0);
3036
3037         /*
3038          * AUX surface offset is specified as the distance from the
3039          * main surface offset, and it must be non-negative. Make
3040          * sure that is what we will get.
3041          */
3042         if (offset > aux_offset)
3043                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3044                                                   offset, aux_offset & ~(alignment - 1));
3045
3046         /*
3047          * When using an X-tiled surface, the plane blows up
3048          * if the x offset + width exceed the stride.
3049          *
3050          * TODO: linear and Y-tiled seem fine, Yf untested,
3051          */
3052         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3053                 int cpp = fb->format->cpp[0];
3054
3055                 while ((x + w) * cpp > fb->pitches[0]) {
3056                         if (offset == 0) {
3057                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3058                                 return -EINVAL;
3059                         }
3060
3061                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3062                                                           offset, offset - alignment);
3063                 }
3064         }
3065
3066         /*
3067          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3068          * they match with the main surface x/y offsets.
3069          */
3070         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3071             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3072                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3073                         if (offset == 0)
3074                                 break;
3075
3076                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3077                                                           offset, offset - alignment);
3078                 }
3079
3080                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3081                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3082                         return -EINVAL;
3083                 }
3084         }
3085
3086         plane_state->main.offset = offset;
3087         plane_state->main.x = x;
3088         plane_state->main.y = y;
3089
3090         return 0;
3091 }
3092
3093 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3094 {
3095         const struct drm_framebuffer *fb = plane_state->base.fb;
3096         unsigned int rotation = plane_state->base.rotation;
3097         int max_width = skl_max_plane_width(fb, 1, rotation);
3098         int max_height = 4096;
3099         int x = plane_state->base.src.x1 >> 17;
3100         int y = plane_state->base.src.y1 >> 17;
3101         int w = drm_rect_width(&plane_state->base.src) >> 17;
3102         int h = drm_rect_height(&plane_state->base.src) >> 17;
3103         u32 offset;
3104
3105         intel_add_fb_offsets(&x, &y, plane_state, 1);
3106         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3107
3108         /* FIXME not quite sure how/if these apply to the chroma plane */
3109         if (w > max_width || h > max_height) {
3110                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3111                               w, h, max_width, max_height);
3112                 return -EINVAL;
3113         }
3114
3115         plane_state->aux.offset = offset;
3116         plane_state->aux.x = x;
3117         plane_state->aux.y = y;
3118
3119         return 0;
3120 }
3121
3122 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3123 {
3124         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3125         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3126         const struct drm_framebuffer *fb = plane_state->base.fb;
3127         int src_x = plane_state->base.src.x1 >> 16;
3128         int src_y = plane_state->base.src.y1 >> 16;
3129         int hsub = fb->format->hsub;
3130         int vsub = fb->format->vsub;
3131         int x = src_x / hsub;
3132         int y = src_y / vsub;
3133         u32 offset;
3134
3135         switch (plane->id) {
3136         case PLANE_PRIMARY:
3137         case PLANE_SPRITE0:
3138                 break;
3139         default:
3140                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3141                 return -EINVAL;
3142         }
3143
3144         if (crtc->pipe == PIPE_C) {
3145                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3146                 return -EINVAL;
3147         }
3148
3149         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3150                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3151                               plane_state->base.rotation);
3152                 return -EINVAL;
3153         }
3154
3155         intel_add_fb_offsets(&x, &y, plane_state, 1);
3156         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3157
3158         plane_state->aux.offset = offset;
3159         plane_state->aux.x = x * hsub + src_x % hsub;
3160         plane_state->aux.y = y * vsub + src_y % vsub;
3161
3162         return 0;
3163 }
3164
3165 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3166 {
3167         const struct drm_framebuffer *fb = plane_state->base.fb;
3168         unsigned int rotation = plane_state->base.rotation;
3169         int ret;
3170
3171         if (!plane_state->base.visible)
3172                 return 0;
3173
3174         /* Rotate src coordinates to match rotated GTT view */
3175         if (drm_rotation_90_or_270(rotation))
3176                 drm_rect_rotate(&plane_state->base.src,
3177                                 fb->width << 16, fb->height << 16,
3178                                 DRM_MODE_ROTATE_270);
3179
3180         /*
3181          * Handle the AUX surface first since
3182          * the main surface setup depends on it.
3183          */
3184         if (fb->format->format == DRM_FORMAT_NV12) {
3185                 ret = skl_check_nv12_aux_surface(plane_state);
3186                 if (ret)
3187                         return ret;
3188         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3189                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3190                 ret = skl_check_ccs_aux_surface(plane_state);
3191                 if (ret)
3192                         return ret;
3193         } else {
3194                 plane_state->aux.offset = ~0xfff;
3195                 plane_state->aux.x = 0;
3196                 plane_state->aux.y = 0;
3197         }
3198
3199         ret = skl_check_main_surface(plane_state);
3200         if (ret)
3201                 return ret;
3202
3203         return 0;
3204 }
3205
3206 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3207                           const struct intel_plane_state *plane_state)
3208 {
3209         struct drm_i915_private *dev_priv =
3210                 to_i915(plane_state->base.plane->dev);
3211         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3212         const struct drm_framebuffer *fb = plane_state->base.fb;
3213         unsigned int rotation = plane_state->base.rotation;
3214         u32 dspcntr;
3215
3216         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3217
3218         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3219             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3220                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3221
3222         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3223                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3224
3225         if (INTEL_GEN(dev_priv) < 4)
3226                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3227
3228         switch (fb->format->format) {
3229         case DRM_FORMAT_C8:
3230                 dspcntr |= DISPPLANE_8BPP;
3231                 break;
3232         case DRM_FORMAT_XRGB1555:
3233                 dspcntr |= DISPPLANE_BGRX555;
3234                 break;
3235         case DRM_FORMAT_RGB565:
3236                 dspcntr |= DISPPLANE_BGRX565;
3237                 break;
3238         case DRM_FORMAT_XRGB8888:
3239                 dspcntr |= DISPPLANE_BGRX888;
3240                 break;
3241         case DRM_FORMAT_XBGR8888:
3242                 dspcntr |= DISPPLANE_RGBX888;
3243                 break;
3244         case DRM_FORMAT_XRGB2101010:
3245                 dspcntr |= DISPPLANE_BGRX101010;
3246                 break;
3247         case DRM_FORMAT_XBGR2101010:
3248                 dspcntr |= DISPPLANE_RGBX101010;
3249                 break;
3250         default:
3251                 MISSING_CASE(fb->format->format);
3252                 return 0;
3253         }
3254
3255         if (INTEL_GEN(dev_priv) >= 4 &&
3256             fb->modifier == I915_FORMAT_MOD_X_TILED)
3257                 dspcntr |= DISPPLANE_TILED;
3258
3259         if (rotation & DRM_MODE_ROTATE_180)
3260                 dspcntr |= DISPPLANE_ROTATE_180;
3261
3262         if (rotation & DRM_MODE_REFLECT_X)
3263                 dspcntr |= DISPPLANE_MIRROR;
3264
3265         return dspcntr;
3266 }
3267
3268 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3269 {
3270         struct drm_i915_private *dev_priv =
3271                 to_i915(plane_state->base.plane->dev);
3272         int src_x = plane_state->base.src.x1 >> 16;
3273         int src_y = plane_state->base.src.y1 >> 16;
3274         u32 offset;
3275
3276         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3277
3278         if (INTEL_GEN(dev_priv) >= 4)
3279                 offset = intel_compute_tile_offset(&src_x, &src_y,
3280                                                    plane_state, 0);
3281         else
3282                 offset = 0;
3283
3284         /* HSW/BDW do this automagically in hardware */
3285         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3286                 unsigned int rotation = plane_state->base.rotation;
3287                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3288                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3289
3290                 if (rotation & DRM_MODE_ROTATE_180) {
3291                         src_x += src_w - 1;
3292                         src_y += src_h - 1;
3293                 } else if (rotation & DRM_MODE_REFLECT_X) {
3294                         src_x += src_w - 1;
3295                 }
3296         }
3297
3298         plane_state->main.offset = offset;
3299         plane_state->main.x = src_x;
3300         plane_state->main.y = src_y;
3301
3302         return 0;
3303 }
3304
3305 static void i9xx_update_primary_plane(struct intel_plane *primary,
3306                                       const struct intel_crtc_state *crtc_state,
3307                                       const struct intel_plane_state *plane_state)
3308 {
3309         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3310         const struct drm_framebuffer *fb = plane_state->base.fb;
3311         enum plane plane = primary->plane;
3312         u32 linear_offset;
3313         u32 dspcntr = plane_state->ctl;
3314         i915_reg_t reg = DSPCNTR(plane);
3315         int x = plane_state->main.x;
3316         int y = plane_state->main.y;
3317         unsigned long irqflags;
3318         u32 dspaddr_offset;
3319
3320         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3321
3322         if (INTEL_GEN(dev_priv) >= 4)
3323                 dspaddr_offset = plane_state->main.offset;
3324         else
3325                 dspaddr_offset = linear_offset;
3326
3327         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3328
3329         if (INTEL_GEN(dev_priv) < 4) {
3330                 /* pipesrc and dspsize control the size that is scaled from,
3331                  * which should always be the user's requested size.
3332                  */
3333                 I915_WRITE_FW(DSPSIZE(plane),
3334                               ((crtc_state->pipe_src_h - 1) << 16) |
3335                               (crtc_state->pipe_src_w - 1));
3336                 I915_WRITE_FW(DSPPOS(plane), 0);
3337         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3338                 I915_WRITE_FW(PRIMSIZE(plane),
3339                               ((crtc_state->pipe_src_h - 1) << 16) |
3340                               (crtc_state->pipe_src_w - 1));
3341                 I915_WRITE_FW(PRIMPOS(plane), 0);
3342                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3343         }
3344
3345         I915_WRITE_FW(reg, dspcntr);
3346
3347         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3348         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3349                 I915_WRITE_FW(DSPSURF(plane),
3350                               intel_plane_ggtt_offset(plane_state) +
3351                               dspaddr_offset);
3352                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3353         } else if (INTEL_GEN(dev_priv) >= 4) {
3354                 I915_WRITE_FW(DSPSURF(plane),
3355                               intel_plane_ggtt_offset(plane_state) +
3356                               dspaddr_offset);
3357                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3358                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3359         } else {
3360                 I915_WRITE_FW(DSPADDR(plane),
3361                               intel_plane_ggtt_offset(plane_state) +
3362                               dspaddr_offset);
3363         }
3364         POSTING_READ_FW(reg);
3365
3366         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3367 }
3368
3369 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3370                                        struct intel_crtc *crtc)
3371 {
3372         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3373         enum plane plane = primary->plane;
3374         unsigned long irqflags;
3375
3376         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3377
3378         I915_WRITE_FW(DSPCNTR(plane), 0);
3379         if (INTEL_INFO(dev_priv)->gen >= 4)
3380                 I915_WRITE_FW(DSPSURF(plane), 0);
3381         else
3382                 I915_WRITE_FW(DSPADDR(plane), 0);
3383         POSTING_READ_FW(DSPCNTR(plane));
3384
3385         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3386 }
3387
3388 static u32
3389 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3390 {
3391         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3392                 return 64;
3393         else
3394                 return intel_tile_width_bytes(fb, plane);
3395 }
3396
3397 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3398 {
3399         struct drm_device *dev = intel_crtc->base.dev;
3400         struct drm_i915_private *dev_priv = to_i915(dev);
3401
3402         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3403         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3404         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3405 }
3406
3407 /*
3408  * This function detaches (aka. unbinds) unused scalers in hardware
3409  */
3410 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3411 {
3412         struct intel_crtc_scaler_state *scaler_state;
3413         int i;
3414
3415         scaler_state = &intel_crtc->config->scaler_state;
3416
3417         /* loop through and disable scalers that aren't in use */
3418         for (i = 0; i < intel_crtc->num_scalers; i++) {
3419                 if (!scaler_state->scalers[i].in_use)
3420                         skl_detach_scaler(intel_crtc, i);
3421         }
3422 }
3423
3424 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3425                      unsigned int rotation)
3426 {
3427         u32 stride;
3428
3429         if (plane >= fb->format->num_planes)
3430                 return 0;
3431
3432         stride = intel_fb_pitch(fb, plane, rotation);
3433
3434         /*
3435          * The stride is either expressed as a multiple of 64 bytes chunks for
3436          * linear buffers or in number of tiles for tiled buffers.
3437          */
3438         if (drm_rotation_90_or_270(rotation))
3439                 stride /= intel_tile_height(fb, plane);
3440         else
3441                 stride /= intel_fb_stride_alignment(fb, plane);
3442
3443         return stride;
3444 }
3445
3446 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3447 {
3448         switch (pixel_format) {
3449         case DRM_FORMAT_C8:
3450                 return PLANE_CTL_FORMAT_INDEXED;
3451         case DRM_FORMAT_RGB565:
3452                 return PLANE_CTL_FORMAT_RGB_565;
3453         case DRM_FORMAT_XBGR8888:
3454                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3455         case DRM_FORMAT_XRGB8888:
3456                 return PLANE_CTL_FORMAT_XRGB_8888;
3457         /*
3458          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3459          * to be already pre-multiplied. We need to add a knob (or a different
3460          * DRM_FORMAT) for user-space to configure that.
3461          */
3462         case DRM_FORMAT_ABGR8888:
3463                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3464                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3465         case DRM_FORMAT_ARGB8888:
3466                 return PLANE_CTL_FORMAT_XRGB_8888 |
3467                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3468         case DRM_FORMAT_XRGB2101010:
3469                 return PLANE_CTL_FORMAT_XRGB_2101010;
3470         case DRM_FORMAT_XBGR2101010:
3471                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3472         case DRM_FORMAT_YUYV:
3473                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3474         case DRM_FORMAT_YVYU:
3475                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3476         case DRM_FORMAT_UYVY:
3477                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3478         case DRM_FORMAT_VYUY:
3479                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3480         default:
3481                 MISSING_CASE(pixel_format);
3482         }
3483
3484         return 0;
3485 }
3486
3487 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3488 {
3489         switch (fb_modifier) {
3490         case DRM_FORMAT_MOD_LINEAR:
3491                 break;
3492         case I915_FORMAT_MOD_X_TILED:
3493                 return PLANE_CTL_TILED_X;
3494         case I915_FORMAT_MOD_Y_TILED:
3495                 return PLANE_CTL_TILED_Y;
3496         case I915_FORMAT_MOD_Y_TILED_CCS:
3497                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3498         case I915_FORMAT_MOD_Yf_TILED:
3499                 return PLANE_CTL_TILED_YF;
3500         case I915_FORMAT_MOD_Yf_TILED_CCS:
3501                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3502         default:
3503                 MISSING_CASE(fb_modifier);
3504         }
3505
3506         return 0;
3507 }
3508
3509 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3510 {
3511         switch (rotation) {
3512         case DRM_MODE_ROTATE_0:
3513                 break;
3514         /*
3515          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3516          * while i915 HW rotation is clockwise, thats why this swapping.
3517          */
3518         case DRM_MODE_ROTATE_90:
3519                 return PLANE_CTL_ROTATE_270;
3520         case DRM_MODE_ROTATE_180:
3521                 return PLANE_CTL_ROTATE_180;
3522         case DRM_MODE_ROTATE_270:
3523                 return PLANE_CTL_ROTATE_90;
3524         default:
3525                 MISSING_CASE(rotation);
3526         }
3527
3528         return 0;
3529 }
3530
3531 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3532                   const struct intel_plane_state *plane_state)
3533 {
3534         struct drm_i915_private *dev_priv =
3535                 to_i915(plane_state->base.plane->dev);
3536         const struct drm_framebuffer *fb = plane_state->base.fb;
3537         unsigned int rotation = plane_state->base.rotation;
3538         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3539         u32 plane_ctl;
3540
3541         plane_ctl = PLANE_CTL_ENABLE;
3542
3543         if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3544                 plane_ctl |=
3545                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3546                         PLANE_CTL_PIPE_CSC_ENABLE |
3547                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3548         }
3549
3550         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3551         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3552         plane_ctl |= skl_plane_ctl_rotation(rotation);
3553
3554         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3555                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3556         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3557                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3558
3559         return plane_ctl;
3560 }
3561
3562 static int
3563 __intel_display_resume(struct drm_device *dev,
3564                        struct drm_atomic_state *state,
3565                        struct drm_modeset_acquire_ctx *ctx)
3566 {
3567         struct drm_crtc_state *crtc_state;
3568         struct drm_crtc *crtc;
3569         int i, ret;
3570
3571         intel_modeset_setup_hw_state(dev, ctx);
3572         i915_redisable_vga(to_i915(dev));
3573
3574         if (!state)
3575                 return 0;
3576
3577         /*
3578          * We've duplicated the state, pointers to the old state are invalid.
3579          *
3580          * Don't attempt to use the old state until we commit the duplicated state.
3581          */
3582         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3583                 /*
3584                  * Force recalculation even if we restore
3585                  * current state. With fast modeset this may not result
3586                  * in a modeset when the state is compatible.
3587                  */
3588                 crtc_state->mode_changed = true;
3589         }
3590
3591         /* ignore any reset values/BIOS leftovers in the WM registers */
3592         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3593                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3594
3595         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3596
3597         WARN_ON(ret == -EDEADLK);
3598         return ret;
3599 }
3600
3601 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3602 {
3603         return intel_has_gpu_reset(dev_priv) &&
3604                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3605 }
3606
3607 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3608 {
3609         struct drm_device *dev = &dev_priv->drm;
3610         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3611         struct drm_atomic_state *state;
3612         int ret;
3613
3614
3615         /* reset doesn't touch the display */
3616         if (!i915_modparams.force_reset_modeset_test &&
3617             !gpu_reset_clobbers_display(dev_priv))
3618                 return;
3619
3620         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3621         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3622         wake_up_all(&dev_priv->gpu_error.wait_queue);
3623
3624         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3625                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3626                 i915_gem_set_wedged(dev_priv);
3627         }
3628
3629         /*
3630          * Need mode_config.mutex so that we don't
3631          * trample ongoing ->detect() and whatnot.
3632          */
3633         mutex_lock(&dev->mode_config.mutex);
3634         drm_modeset_acquire_init(ctx, 0);
3635         while (1) {
3636                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3637                 if (ret != -EDEADLK)
3638                         break;
3639
3640                 drm_modeset_backoff(ctx);
3641         }
3642         /*
3643          * Disabling the crtcs gracefully seems nicer. Also the
3644          * g33 docs say we should at least disable all the planes.
3645          */
3646         state = drm_atomic_helper_duplicate_state(dev, ctx);
3647         if (IS_ERR(state)) {
3648                 ret = PTR_ERR(state);
3649                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3650                 return;
3651         }
3652
3653         ret = drm_atomic_helper_disable_all(dev, ctx);
3654         if (ret) {
3655                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3656                 drm_atomic_state_put(state);
3657                 return;
3658         }
3659
3660         dev_priv->modeset_restore_state = state;
3661         state->acquire_ctx = ctx;
3662 }
3663
3664 void intel_finish_reset(struct drm_i915_private *dev_priv)
3665 {
3666         struct drm_device *dev = &dev_priv->drm;
3667         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3668         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3669         int ret;
3670
3671         /* reset doesn't touch the display */
3672         if (!i915_modparams.force_reset_modeset_test &&
3673             !gpu_reset_clobbers_display(dev_priv))
3674                 return;
3675
3676         if (!state)
3677                 goto unlock;
3678
3679         dev_priv->modeset_restore_state = NULL;
3680
3681         /* reset doesn't touch the display */
3682         if (!gpu_reset_clobbers_display(dev_priv)) {
3683                 /* for testing only restore the display */
3684                 ret = __intel_display_resume(dev, state, ctx);
3685                 if (ret)
3686                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3687         } else {
3688                 /*
3689                  * The display has been reset as well,
3690                  * so need a full re-initialization.
3691                  */
3692                 intel_runtime_pm_disable_interrupts(dev_priv);
3693                 intel_runtime_pm_enable_interrupts(dev_priv);
3694
3695                 intel_pps_unlock_regs_wa(dev_priv);
3696                 intel_modeset_init_hw(dev);
3697                 intel_init_clock_gating(dev_priv);
3698
3699                 spin_lock_irq(&dev_priv->irq_lock);
3700                 if (dev_priv->display.hpd_irq_setup)
3701                         dev_priv->display.hpd_irq_setup(dev_priv);
3702                 spin_unlock_irq(&dev_priv->irq_lock);
3703
3704                 ret = __intel_display_resume(dev, state, ctx);
3705                 if (ret)
3706                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3707
3708                 intel_hpd_init(dev_priv);
3709         }
3710
3711         drm_atomic_state_put(state);
3712 unlock:
3713         drm_modeset_drop_locks(ctx);
3714         drm_modeset_acquire_fini(ctx);
3715         mutex_unlock(&dev->mode_config.mutex);
3716
3717         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3718 }
3719
3720 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3721                                      const struct intel_crtc_state *new_crtc_state)
3722 {
3723         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3724         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3725
3726         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3727         crtc->base.mode = new_crtc_state->base.mode;
3728
3729         /*
3730          * Update pipe size and adjust fitter if needed: the reason for this is
3731          * that in compute_mode_changes we check the native mode (not the pfit
3732          * mode) to see if we can flip rather than do a full mode set. In the
3733          * fastboot case, we'll flip, but if we don't update the pipesrc and
3734          * pfit state, we'll end up with a big fb scanned out into the wrong
3735          * sized surface.
3736          */
3737
3738         I915_WRITE(PIPESRC(crtc->pipe),
3739                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3740                    (new_crtc_state->pipe_src_h - 1));
3741
3742         /* on skylake this is done by detaching scalers */
3743         if (INTEL_GEN(dev_priv) >= 9) {
3744                 skl_detach_scalers(crtc);
3745
3746                 if (new_crtc_state->pch_pfit.enabled)
3747                         skylake_pfit_enable(crtc);
3748         } else if (HAS_PCH_SPLIT(dev_priv)) {
3749                 if (new_crtc_state->pch_pfit.enabled)
3750                         ironlake_pfit_enable(crtc);
3751                 else if (old_crtc_state->pch_pfit.enabled)
3752                         ironlake_pfit_disable(crtc, true);
3753         }
3754 }
3755
3756 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3757 {
3758         struct drm_device *dev = crtc->base.dev;
3759         struct drm_i915_private *dev_priv = to_i915(dev);
3760         int pipe = crtc->pipe;
3761         i915_reg_t reg;
3762         u32 temp;
3763
3764         /* enable normal train */
3765         reg = FDI_TX_CTL(pipe);
3766         temp = I915_READ(reg);
3767         if (IS_IVYBRIDGE(dev_priv)) {
3768                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3769                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3770         } else {
3771                 temp &= ~FDI_LINK_TRAIN_NONE;
3772                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3773         }
3774         I915_WRITE(reg, temp);
3775
3776         reg = FDI_RX_CTL(pipe);
3777         temp = I915_READ(reg);
3778         if (HAS_PCH_CPT(dev_priv)) {
3779                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3780                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3781         } else {
3782                 temp &= ~FDI_LINK_TRAIN_NONE;
3783                 temp |= FDI_LINK_TRAIN_NONE;
3784         }
3785         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3786
3787         /* wait one idle pattern time */
3788         POSTING_READ(reg);
3789         udelay(1000);
3790
3791         /* IVB wants error correction enabled */
3792         if (IS_IVYBRIDGE(dev_priv))
3793                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3794                            FDI_FE_ERRC_ENABLE);
3795 }
3796
3797 /* The FDI link training functions for ILK/Ibexpeak. */
3798 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3799                                     const struct intel_crtc_state *crtc_state)
3800 {
3801         struct drm_device *dev = crtc->base.dev;
3802         struct drm_i915_private *dev_priv = to_i915(dev);
3803         int pipe = crtc->pipe;
3804         i915_reg_t reg;
3805         u32 temp, tries;
3806
3807         /* FDI needs bits from pipe first */
3808         assert_pipe_enabled(dev_priv, pipe);
3809
3810         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3811            for train result */
3812         reg = FDI_RX_IMR(pipe);
3813         temp = I915_READ(reg);
3814         temp &= ~FDI_RX_SYMBOL_LOCK;
3815         temp &= ~FDI_RX_BIT_LOCK;
3816         I915_WRITE(reg, temp);
3817         I915_READ(reg);
3818         udelay(150);
3819
3820         /* enable CPU FDI TX and PCH FDI RX */
3821         reg = FDI_TX_CTL(pipe);
3822         temp = I915_READ(reg);
3823         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3824         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3825         temp &= ~FDI_LINK_TRAIN_NONE;
3826         temp |= FDI_LINK_TRAIN_PATTERN_1;
3827         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3828
3829         reg = FDI_RX_CTL(pipe);
3830         temp = I915_READ(reg);
3831         temp &= ~FDI_LINK_TRAIN_NONE;
3832         temp |= FDI_LINK_TRAIN_PATTERN_1;
3833         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3834
3835         POSTING_READ(reg);
3836         udelay(150);
3837
3838         /* Ironlake workaround, enable clock pointer after FDI enable*/
3839         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3840         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3841                    FDI_RX_PHASE_SYNC_POINTER_EN);
3842
3843         reg = FDI_RX_IIR(pipe);
3844         for (tries = 0; tries < 5; tries++) {
3845                 temp = I915_READ(reg);
3846                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3847
3848                 if ((temp & FDI_RX_BIT_LOCK)) {
3849                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3850                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3851                         break;
3852                 }
3853         }
3854         if (tries == 5)
3855                 DRM_ERROR("FDI train 1 fail!\n");
3856
3857         /* Train 2 */
3858         reg = FDI_TX_CTL(pipe);
3859         temp = I915_READ(reg);
3860         temp &= ~FDI_LINK_TRAIN_NONE;
3861         temp |= FDI_LINK_TRAIN_PATTERN_2;
3862         I915_WRITE(reg, temp);
3863
3864         reg = FDI_RX_CTL(pipe);
3865         temp = I915_READ(reg);
3866         temp &= ~FDI_LINK_TRAIN_NONE;
3867         temp |= FDI_LINK_TRAIN_PATTERN_2;
3868         I915_WRITE(reg, temp);
3869
3870         POSTING_READ(reg);
3871         udelay(150);
3872
3873         reg = FDI_RX_IIR(pipe);
3874         for (tries = 0; tries < 5; tries++) {
3875                 temp = I915_READ(reg);
3876                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3877
3878                 if (temp & FDI_RX_SYMBOL_LOCK) {
3879                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3880                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3881                         break;
3882                 }
3883         }
3884         if (tries == 5)
3885                 DRM_ERROR("FDI train 2 fail!\n");
3886
3887         DRM_DEBUG_KMS("FDI train done\n");
3888
3889 }
3890
3891 static const int snb_b_fdi_train_param[] = {
3892         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3893         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3894         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3895         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3896 };
3897
3898 /* The FDI link training functions for SNB/Cougarpoint. */
3899 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3900                                 const struct intel_crtc_state *crtc_state)
3901 {
3902         struct drm_device *dev = crtc->base.dev;
3903         struct drm_i915_private *dev_priv = to_i915(dev);
3904         int pipe = crtc->pipe;
3905         i915_reg_t reg;
3906         u32 temp, i, retry;
3907
3908         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3909            for train result */
3910         reg = FDI_RX_IMR(pipe);
3911         temp = I915_READ(reg);
3912         temp &= ~FDI_RX_SYMBOL_LOCK;
3913         temp &= ~FDI_RX_BIT_LOCK;
3914         I915_WRITE(reg, temp);
3915
3916         POSTING_READ(reg);
3917         udelay(150);
3918
3919         /* enable CPU FDI TX and PCH FDI RX */
3920         reg = FDI_TX_CTL(pipe);
3921         temp = I915_READ(reg);
3922         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3923         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3924         temp &= ~FDI_LINK_TRAIN_NONE;
3925         temp |= FDI_LINK_TRAIN_PATTERN_1;
3926         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3927         /* SNB-B */
3928         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3929         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3930
3931         I915_WRITE(FDI_RX_MISC(pipe),
3932                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3933
3934         reg = FDI_RX_CTL(pipe);
3935         temp = I915_READ(reg);
3936         if (HAS_PCH_CPT(dev_priv)) {
3937                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3938                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3939         } else {
3940                 temp &= ~FDI_LINK_TRAIN_NONE;
3941                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3942         }
3943         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3944
3945         POSTING_READ(reg);
3946         udelay(150);
3947
3948         for (i = 0; i < 4; i++) {
3949                 reg = FDI_TX_CTL(pipe);
3950                 temp = I915_READ(reg);
3951                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3952                 temp |= snb_b_fdi_train_param[i];
3953                 I915_WRITE(reg, temp);
3954
3955                 POSTING_READ(reg);
3956                 udelay(500);
3957
3958                 for (retry = 0; retry < 5; retry++) {
3959                         reg = FDI_RX_IIR(pipe);
3960                         temp = I915_READ(reg);
3961                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3962                         if (temp & FDI_RX_BIT_LOCK) {
3963                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3964                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3965                                 break;
3966                         }
3967                         udelay(50);
3968                 }
3969                 if (retry < 5)
3970                         break;
3971         }
3972         if (i == 4)
3973                 DRM_ERROR("FDI train 1 fail!\n");
3974
3975         /* Train 2 */
3976         reg = FDI_TX_CTL(pipe);
3977         temp = I915_READ(reg);
3978         temp &= ~FDI_LINK_TRAIN_NONE;
3979         temp |= FDI_LINK_TRAIN_PATTERN_2;
3980         if (IS_GEN6(dev_priv)) {
3981                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3982                 /* SNB-B */
3983                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3984         }
3985         I915_WRITE(reg, temp);
3986
3987         reg = FDI_RX_CTL(pipe);
3988         temp = I915_READ(reg);
3989         if (HAS_PCH_CPT(dev_priv)) {
3990                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3991                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3992         } else {
3993                 temp &= ~FDI_LINK_TRAIN_NONE;
3994                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3995         }
3996         I915_WRITE(reg, temp);
3997
3998         POSTING_READ(reg);
3999         udelay(150);
4000
4001         for (i = 0; i < 4; i++) {
4002                 reg = FDI_TX_CTL(pipe);
4003                 temp = I915_READ(reg);
4004                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4005                 temp |= snb_b_fdi_train_param[i];
4006                 I915_WRITE(reg, temp);
4007
4008                 POSTING_READ(reg);
4009                 udelay(500);
4010
4011                 for (retry = 0; retry < 5; retry++) {
4012                         reg = FDI_RX_IIR(pipe);
4013                         temp = I915_READ(reg);
4014                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4015                         if (temp & FDI_RX_SYMBOL_LOCK) {
4016                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4017                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4018                                 break;
4019                         }
4020                         udelay(50);
4021                 }
4022                 if (retry < 5)
4023                         break;
4024         }
4025         if (i == 4)
4026                 DRM_ERROR("FDI train 2 fail!\n");
4027
4028         DRM_DEBUG_KMS("FDI train done.\n");
4029 }
4030
4031 /* Manual link training for Ivy Bridge A0 parts */
4032 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4033                                       const struct intel_crtc_state *crtc_state)
4034 {
4035         struct drm_device *dev = crtc->base.dev;
4036         struct drm_i915_private *dev_priv = to_i915(dev);
4037         int pipe = crtc->pipe;
4038         i915_reg_t reg;
4039         u32 temp, i, j;
4040
4041         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4042            for train result */
4043         reg = FDI_RX_IMR(pipe);
4044         temp = I915_READ(reg);
4045         temp &= ~FDI_RX_SYMBOL_LOCK;
4046         temp &= ~FDI_RX_BIT_LOCK;
4047         I915_WRITE(reg, temp);
4048
4049         POSTING_READ(reg);
4050         udelay(150);
4051
4052         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4053                       I915_READ(FDI_RX_IIR(pipe)));
4054
4055         /* Try each vswing and preemphasis setting twice before moving on */
4056         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4057                 /* disable first in case we need to retry */
4058                 reg = FDI_TX_CTL(pipe);
4059                 temp = I915_READ(reg);
4060                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4061                 temp &= ~FDI_TX_ENABLE;
4062                 I915_WRITE(reg, temp);
4063
4064                 reg = FDI_RX_CTL(pipe);
4065                 temp = I915_READ(reg);
4066                 temp &= ~FDI_LINK_TRAIN_AUTO;
4067                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4068                 temp &= ~FDI_RX_ENABLE;
4069                 I915_WRITE(reg, temp);
4070
4071                 /* enable CPU FDI TX and PCH FDI RX */
4072                 reg = FDI_TX_CTL(pipe);
4073                 temp = I915_READ(reg);
4074                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4075                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4076                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4077                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4078                 temp |= snb_b_fdi_train_param[j/2];
4079                 temp |= FDI_COMPOSITE_SYNC;
4080                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4081
4082                 I915_WRITE(FDI_RX_MISC(pipe),
4083                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4084
4085                 reg = FDI_RX_CTL(pipe);
4086                 temp = I915_READ(reg);
4087                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4088                 temp |= FDI_COMPOSITE_SYNC;
4089                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4090
4091                 POSTING_READ(reg);
4092                 udelay(1); /* should be 0.5us */
4093
4094                 for (i = 0; i < 4; i++) {
4095                         reg = FDI_RX_IIR(pipe);
4096                         temp = I915_READ(reg);
4097                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4098
4099                         if (temp & FDI_RX_BIT_LOCK ||
4100                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4101                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4102                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4103                                               i);
4104                                 break;
4105                         }
4106                         udelay(1); /* should be 0.5us */
4107                 }
4108                 if (i == 4) {
4109                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4110                         continue;
4111                 }
4112
4113                 /* Train 2 */
4114                 reg = FDI_TX_CTL(pipe);
4115                 temp = I915_READ(reg);
4116                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4117                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4118                 I915_WRITE(reg, temp);
4119
4120                 reg = FDI_RX_CTL(pipe);
4121                 temp = I915_READ(reg);
4122                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4123                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4124                 I915_WRITE(reg, temp);
4125
4126                 POSTING_READ(reg);
4127                 udelay(2); /* should be 1.5us */
4128
4129                 for (i = 0; i < 4; i++) {
4130                         reg = FDI_RX_IIR(pipe);
4131                         temp = I915_READ(reg);
4132                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4133
4134                         if (temp & FDI_RX_SYMBOL_LOCK ||
4135                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4136                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4137                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4138                                               i);
4139                                 goto train_done;
4140                         }
4141                         udelay(2); /* should be 1.5us */
4142                 }
4143                 if (i == 4)
4144                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4145         }
4146
4147 train_done:
4148         DRM_DEBUG_KMS("FDI train done.\n");
4149 }
4150
4151 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4152 {
4153         struct drm_device *dev = intel_crtc->base.dev;
4154         struct drm_i915_private *dev_priv = to_i915(dev);
4155         int pipe = intel_crtc->pipe;
4156         i915_reg_t reg;
4157         u32 temp;
4158
4159         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4160         reg = FDI_RX_CTL(pipe);
4161         temp = I915_READ(reg);
4162         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4163         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4164         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4165         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4166
4167         POSTING_READ(reg);
4168         udelay(200);
4169
4170         /* Switch from Rawclk to PCDclk */
4171         temp = I915_READ(reg);
4172         I915_WRITE(reg, temp | FDI_PCDCLK);
4173
4174         POSTING_READ(reg);
4175         udelay(200);
4176
4177         /* Enable CPU FDI TX PLL, always on for Ironlake */
4178         reg = FDI_TX_CTL(pipe);
4179         temp = I915_READ(reg);
4180         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4181                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4182
4183                 POSTING_READ(reg);
4184                 udelay(100);
4185         }
4186 }
4187
4188 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4189 {
4190         struct drm_device *dev = intel_crtc->base.dev;
4191         struct drm_i915_private *dev_priv = to_i915(dev);
4192         int pipe = intel_crtc->pipe;
4193         i915_reg_t reg;
4194         u32 temp;
4195
4196         /* Switch from PCDclk to Rawclk */
4197         reg = FDI_RX_CTL(pipe);
4198         temp = I915_READ(reg);
4199         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4200
4201         /* Disable CPU FDI TX PLL */
4202         reg = FDI_TX_CTL(pipe);
4203         temp = I915_READ(reg);
4204         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4205
4206         POSTING_READ(reg);
4207         udelay(100);
4208
4209         reg = FDI_RX_CTL(pipe);
4210         temp = I915_READ(reg);
4211         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4212
4213         /* Wait for the clocks to turn off. */
4214         POSTING_READ(reg);
4215         udelay(100);
4216 }
4217
4218 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4219 {
4220         struct drm_device *dev = crtc->dev;
4221         struct drm_i915_private *dev_priv = to_i915(dev);
4222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223         int pipe = intel_crtc->pipe;
4224         i915_reg_t reg;
4225         u32 temp;
4226
4227         /* disable CPU FDI tx and PCH FDI rx */
4228         reg = FDI_TX_CTL(pipe);
4229         temp = I915_READ(reg);
4230         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4231         POSTING_READ(reg);
4232
4233         reg = FDI_RX_CTL(pipe);
4234         temp = I915_READ(reg);
4235         temp &= ~(0x7 << 16);
4236         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4237         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4238
4239         POSTING_READ(reg);
4240         udelay(100);
4241
4242         /* Ironlake workaround, disable clock pointer after downing FDI */
4243         if (HAS_PCH_IBX(dev_priv))
4244                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4245
4246         /* still set train pattern 1 */
4247         reg = FDI_TX_CTL(pipe);
4248         temp = I915_READ(reg);
4249         temp &= ~FDI_LINK_TRAIN_NONE;
4250         temp |= FDI_LINK_TRAIN_PATTERN_1;
4251         I915_WRITE(reg, temp);
4252
4253         reg = FDI_RX_CTL(pipe);
4254         temp = I915_READ(reg);
4255         if (HAS_PCH_CPT(dev_priv)) {
4256                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4257                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4258         } else {
4259                 temp &= ~FDI_LINK_TRAIN_NONE;
4260                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4261         }
4262         /* BPC in FDI rx is consistent with that in PIPECONF */
4263         temp &= ~(0x07 << 16);
4264         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4265         I915_WRITE(reg, temp);
4266
4267         POSTING_READ(reg);
4268         udelay(100);
4269 }
4270
4271 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4272 {
4273         struct drm_crtc *crtc;
4274         bool cleanup_done;
4275
4276         drm_for_each_crtc(crtc, &dev_priv->drm) {
4277                 struct drm_crtc_commit *commit;
4278                 spin_lock(&crtc->commit_lock);
4279                 commit = list_first_entry_or_null(&crtc->commit_list,
4280                                                   struct drm_crtc_commit, commit_entry);
4281                 cleanup_done = commit ?
4282                         try_wait_for_completion(&commit->cleanup_done) : true;
4283                 spin_unlock(&crtc->commit_lock);
4284
4285                 if (cleanup_done)
4286                         continue;
4287
4288                 drm_crtc_wait_one_vblank(crtc);
4289
4290                 return true;
4291         }
4292
4293         return false;
4294 }
4295
4296 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4297 {
4298         u32 temp;
4299
4300         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4301
4302         mutex_lock(&dev_priv->sb_lock);
4303
4304         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4305         temp |= SBI_SSCCTL_DISABLE;
4306         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4307
4308         mutex_unlock(&dev_priv->sb_lock);
4309 }
4310
4311 /* Program iCLKIP clock to the desired frequency */
4312 static void lpt_program_iclkip(struct intel_crtc *crtc)
4313 {
4314         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4315         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4316         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4317         u32 temp;
4318
4319         lpt_disable_iclkip(dev_priv);
4320
4321         /* The iCLK virtual clock root frequency is in MHz,
4322          * but the adjusted_mode->crtc_clock in in KHz. To get the
4323          * divisors, it is necessary to divide one by another, so we
4324          * convert the virtual clock precision to KHz here for higher
4325          * precision.
4326          */
4327         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4328                 u32 iclk_virtual_root_freq = 172800 * 1000;
4329                 u32 iclk_pi_range = 64;
4330                 u32 desired_divisor;
4331
4332                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4333                                                     clock << auxdiv);
4334                 divsel = (desired_divisor / iclk_pi_range) - 2;
4335                 phaseinc = desired_divisor % iclk_pi_range;
4336
4337                 /*
4338                  * Near 20MHz is a corner case which is
4339                  * out of range for the 7-bit divisor
4340                  */
4341                 if (divsel <= 0x7f)
4342                         break;
4343         }
4344
4345         /* This should not happen with any sane values */
4346         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4347                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4348         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4349                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4350
4351         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4352                         clock,
4353                         auxdiv,
4354                         divsel,
4355                         phasedir,
4356                         phaseinc);
4357
4358         mutex_lock(&dev_priv->sb_lock);
4359
4360         /* Program SSCDIVINTPHASE6 */
4361         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4362         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4363         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4364         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4365         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4366         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4367         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4368         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4369
4370         /* Program SSCAUXDIV */
4371         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4372         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4373         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4374         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4375
4376         /* Enable modulator and associated divider */
4377         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4378         temp &= ~SBI_SSCCTL_DISABLE;
4379         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4380
4381         mutex_unlock(&dev_priv->sb_lock);
4382
4383         /* Wait for initialization time */
4384         udelay(24);
4385
4386         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4387 }
4388
4389 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4390 {
4391         u32 divsel, phaseinc, auxdiv;
4392         u32 iclk_virtual_root_freq = 172800 * 1000;
4393         u32 iclk_pi_range = 64;
4394         u32 desired_divisor;
4395         u32 temp;
4396
4397         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4398                 return 0;
4399
4400         mutex_lock(&dev_priv->sb_lock);
4401
4402         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4403         if (temp & SBI_SSCCTL_DISABLE) {
4404                 mutex_unlock(&dev_priv->sb_lock);
4405                 return 0;
4406         }
4407
4408         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4409         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4410                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4411         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4412                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4413
4414         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4415         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4416                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4417
4418         mutex_unlock(&dev_priv->sb_lock);
4419
4420         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4421
4422         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4423                                  desired_divisor << auxdiv);
4424 }
4425
4426 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4427                                                 enum pipe pch_transcoder)
4428 {
4429         struct drm_device *dev = crtc->base.dev;
4430         struct drm_i915_private *dev_priv = to_i915(dev);
4431         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4432
4433         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4434                    I915_READ(HTOTAL(cpu_transcoder)));
4435         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4436                    I915_READ(HBLANK(cpu_transcoder)));
4437         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4438                    I915_READ(HSYNC(cpu_transcoder)));
4439
4440         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4441                    I915_READ(VTOTAL(cpu_transcoder)));
4442         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4443                    I915_READ(VBLANK(cpu_transcoder)));
4444         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4445                    I915_READ(VSYNC(cpu_transcoder)));
4446         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4447                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4448 }
4449
4450 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4451 {
4452         struct drm_i915_private *dev_priv = to_i915(dev);
4453         uint32_t temp;
4454
4455         temp = I915_READ(SOUTH_CHICKEN1);
4456         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4457                 return;
4458
4459         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4460         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4461
4462         temp &= ~FDI_BC_BIFURCATION_SELECT;
4463         if (enable)
4464                 temp |= FDI_BC_BIFURCATION_SELECT;
4465
4466         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4467         I915_WRITE(SOUTH_CHICKEN1, temp);
4468         POSTING_READ(SOUTH_CHICKEN1);
4469 }
4470
4471 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4472 {
4473         struct drm_device *dev = intel_crtc->base.dev;
4474
4475         switch (intel_crtc->pipe) {
4476         case PIPE_A:
4477                 break;
4478         case PIPE_B:
4479                 if (intel_crtc->config->fdi_lanes > 2)
4480                         cpt_set_fdi_bc_bifurcation(dev, false);
4481                 else
4482                         cpt_set_fdi_bc_bifurcation(dev, true);
4483
4484                 break;
4485         case PIPE_C:
4486                 cpt_set_fdi_bc_bifurcation(dev, true);
4487
4488                 break;
4489         default:
4490                 BUG();
4491         }
4492 }
4493
4494 /* Return which DP Port should be selected for Transcoder DP control */
4495 static enum port
4496 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4497 {
4498         struct drm_device *dev = crtc->base.dev;
4499         struct intel_encoder *encoder;
4500
4501         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4502                 if (encoder->type == INTEL_OUTPUT_DP ||
4503                     encoder->type == INTEL_OUTPUT_EDP)
4504                         return enc_to_dig_port(&encoder->base)->port;
4505         }
4506
4507         return -1;
4508 }
4509
4510 /*
4511  * Enable PCH resources required for PCH ports:
4512  *   - PCH PLLs
4513  *   - FDI training & RX/TX
4514  *   - update transcoder timings
4515  *   - DP transcoding bits
4516  *   - transcoder
4517  */
4518 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4519 {
4520         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4521         struct drm_device *dev = crtc->base.dev;
4522         struct drm_i915_private *dev_priv = to_i915(dev);
4523         int pipe = crtc->pipe;
4524         u32 temp;
4525
4526         assert_pch_transcoder_disabled(dev_priv, pipe);
4527
4528         if (IS_IVYBRIDGE(dev_priv))
4529                 ivybridge_update_fdi_bc_bifurcation(crtc);
4530
4531         /* Write the TU size bits before fdi link training, so that error
4532          * detection works. */
4533         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4534                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4535
4536         /* For PCH output, training FDI link */
4537         dev_priv->display.fdi_link_train(crtc, crtc_state);
4538
4539         /* We need to program the right clock selection before writing the pixel
4540          * mutliplier into the DPLL. */
4541         if (HAS_PCH_CPT(dev_priv)) {
4542                 u32 sel;
4543
4544                 temp = I915_READ(PCH_DPLL_SEL);
4545                 temp |= TRANS_DPLL_ENABLE(pipe);
4546                 sel = TRANS_DPLLB_SEL(pipe);
4547                 if (crtc_state->shared_dpll ==
4548                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4549                         temp |= sel;
4550                 else
4551                         temp &= ~sel;
4552                 I915_WRITE(PCH_DPLL_SEL, temp);
4553         }
4554
4555         /* XXX: pch pll's can be enabled any time before we enable the PCH
4556          * transcoder, and we actually should do this to not upset any PCH
4557          * transcoder that already use the clock when we share it.
4558          *
4559          * Note that enable_shared_dpll tries to do the right thing, but
4560          * get_shared_dpll unconditionally resets the pll - we need that to have
4561          * the right LVDS enable sequence. */
4562         intel_enable_shared_dpll(crtc);
4563
4564         /* set transcoder timing, panel must allow it */
4565         assert_panel_unlocked(dev_priv, pipe);
4566         ironlake_pch_transcoder_set_timings(crtc, pipe);
4567
4568         intel_fdi_normal_train(crtc);
4569
4570         /* For PCH DP, enable TRANS_DP_CTL */
4571         if (HAS_PCH_CPT(dev_priv) &&
4572             intel_crtc_has_dp_encoder(crtc_state)) {
4573                 const struct drm_display_mode *adjusted_mode =
4574                         &crtc_state->base.adjusted_mode;
4575                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4576                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4577                 temp = I915_READ(reg);
4578                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4579                           TRANS_DP_SYNC_MASK |
4580                           TRANS_DP_BPC_MASK);
4581                 temp |= TRANS_DP_OUTPUT_ENABLE;
4582                 temp |= bpc << 9; /* same format but at 11:9 */
4583
4584                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4585                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4586                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4587                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4588
4589                 switch (intel_trans_dp_port_sel(crtc)) {
4590                 case PORT_B:
4591                         temp |= TRANS_DP_PORT_SEL_B;
4592                         break;
4593                 case PORT_C:
4594                         temp |= TRANS_DP_PORT_SEL_C;
4595                         break;
4596                 case PORT_D:
4597                         temp |= TRANS_DP_PORT_SEL_D;
4598                         break;
4599                 default:
4600                         BUG();
4601                 }
4602
4603                 I915_WRITE(reg, temp);
4604         }
4605
4606         ironlake_enable_pch_transcoder(dev_priv, pipe);
4607 }
4608
4609 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4610 {
4611         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4612         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4613         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4614
4615         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4616
4617         lpt_program_iclkip(crtc);
4618
4619         /* Set transcoder timing. */
4620         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4621
4622         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4623 }
4624
4625 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4626 {
4627         struct drm_i915_private *dev_priv = to_i915(dev);
4628         i915_reg_t dslreg = PIPEDSL(pipe);
4629         u32 temp;
4630
4631         temp = I915_READ(dslreg);
4632         udelay(500);
4633         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4634                 if (wait_for(I915_READ(dslreg) != temp, 5))
4635                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4636         }
4637 }
4638
4639 static int
4640 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4641                   unsigned int scaler_user, int *scaler_id,
4642                   int src_w, int src_h, int dst_w, int dst_h)
4643 {
4644         struct intel_crtc_scaler_state *scaler_state =
4645                 &crtc_state->scaler_state;
4646         struct intel_crtc *intel_crtc =
4647                 to_intel_crtc(crtc_state->base.crtc);
4648         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4649         const struct drm_display_mode *adjusted_mode =
4650                 &crtc_state->base.adjusted_mode;
4651         int need_scaling;
4652
4653         /*
4654          * Src coordinates are already rotated by 270 degrees for
4655          * the 90/270 degree plane rotation cases (to match the
4656          * GTT mapping), hence no need to account for rotation here.
4657          */
4658         need_scaling = src_w != dst_w || src_h != dst_h;
4659
4660         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4661                 need_scaling = true;
4662
4663         /*
4664          * Scaling/fitting not supported in IF-ID mode in GEN9+
4665          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4666          * Once NV12 is enabled, handle it here while allocating scaler
4667          * for NV12.
4668          */
4669         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4670             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4671                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4672                 return -EINVAL;
4673         }
4674
4675         /*
4676          * if plane is being disabled or scaler is no more required or force detach
4677          *  - free scaler binded to this plane/crtc
4678          *  - in order to do this, update crtc->scaler_usage
4679          *
4680          * Here scaler state in crtc_state is set free so that
4681          * scaler can be assigned to other user. Actual register
4682          * update to free the scaler is done in plane/panel-fit programming.
4683          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4684          */
4685         if (force_detach || !need_scaling) {
4686                 if (*scaler_id >= 0) {
4687                         scaler_state->scaler_users &= ~(1 << scaler_user);
4688                         scaler_state->scalers[*scaler_id].in_use = 0;
4689
4690                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4691                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4692                                 intel_crtc->pipe, scaler_user, *scaler_id,
4693                                 scaler_state->scaler_users);
4694                         *scaler_id = -1;
4695                 }
4696                 return 0;
4697         }
4698
4699         /* range checks */
4700         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4701                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4702
4703                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4704                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4705                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4706                         "size is out of scaler range\n",
4707                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4708                 return -EINVAL;
4709         }
4710
4711         /* mark this plane as a scaler user in crtc_state */
4712         scaler_state->scaler_users |= (1 << scaler_user);
4713         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4714                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4715                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4716                 scaler_state->scaler_users);
4717
4718         return 0;
4719 }
4720
4721 /**
4722  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4723  *
4724  * @state: crtc's scaler state
4725  *
4726  * Return
4727  *     0 - scaler_usage updated successfully
4728  *    error - requested scaling cannot be supported or other error condition
4729  */
4730 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4731 {
4732         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4733
4734         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4735                 &state->scaler_state.scaler_id,
4736                 state->pipe_src_w, state->pipe_src_h,
4737                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4738 }
4739
4740 /**
4741  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4742  *
4743  * @state: crtc's scaler state
4744  * @plane_state: atomic plane state to update
4745  *
4746  * Return
4747  *     0 - scaler_usage updated successfully
4748  *    error - requested scaling cannot be supported or other error condition
4749  */
4750 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4751                                    struct intel_plane_state *plane_state)
4752 {
4753
4754         struct intel_plane *intel_plane =
4755                 to_intel_plane(plane_state->base.plane);
4756         struct drm_framebuffer *fb = plane_state->base.fb;
4757         int ret;
4758
4759         bool force_detach = !fb || !plane_state->base.visible;
4760
4761         ret = skl_update_scaler(crtc_state, force_detach,
4762                                 drm_plane_index(&intel_plane->base),
4763                                 &plane_state->scaler_id,
4764                                 drm_rect_width(&plane_state->base.src) >> 16,
4765                                 drm_rect_height(&plane_state->base.src) >> 16,
4766                                 drm_rect_width(&plane_state->base.dst),
4767                                 drm_rect_height(&plane_state->base.dst));
4768
4769         if (ret || plane_state->scaler_id < 0)
4770                 return ret;
4771
4772         /* check colorkey */
4773         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4774                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4775                               intel_plane->base.base.id,
4776                               intel_plane->base.name);
4777                 return -EINVAL;
4778         }
4779
4780         /* Check src format */
4781         switch (fb->format->format) {
4782         case DRM_FORMAT_RGB565:
4783         case DRM_FORMAT_XBGR8888:
4784         case DRM_FORMAT_XRGB8888:
4785         case DRM_FORMAT_ABGR8888:
4786         case DRM_FORMAT_ARGB8888:
4787         case DRM_FORMAT_XRGB2101010:
4788         case DRM_FORMAT_XBGR2101010:
4789         case DRM_FORMAT_YUYV:
4790         case DRM_FORMAT_YVYU:
4791         case DRM_FORMAT_UYVY:
4792         case DRM_FORMAT_VYUY:
4793                 break;
4794         default:
4795                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4796                               intel_plane->base.base.id, intel_plane->base.name,
4797                               fb->base.id, fb->format->format);
4798                 return -EINVAL;
4799         }
4800
4801         return 0;
4802 }
4803
4804 static void skylake_scaler_disable(struct intel_crtc *crtc)
4805 {
4806         int i;
4807
4808         for (i = 0; i < crtc->num_scalers; i++)
4809                 skl_detach_scaler(crtc, i);
4810 }
4811
4812 static void skylake_pfit_enable(struct intel_crtc *crtc)
4813 {
4814         struct drm_device *dev = crtc->base.dev;
4815         struct drm_i915_private *dev_priv = to_i915(dev);
4816         int pipe = crtc->pipe;
4817         struct intel_crtc_scaler_state *scaler_state =
4818                 &crtc->config->scaler_state;
4819
4820         if (crtc->config->pch_pfit.enabled) {
4821                 int id;
4822
4823                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4824                         return;
4825
4826                 id = scaler_state->scaler_id;
4827                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4828                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4829                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4830                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4831         }
4832 }
4833
4834 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4835 {
4836         struct drm_device *dev = crtc->base.dev;
4837         struct drm_i915_private *dev_priv = to_i915(dev);
4838         int pipe = crtc->pipe;
4839
4840         if (crtc->config->pch_pfit.enabled) {
4841                 /* Force use of hard-coded filter coefficients
4842                  * as some pre-programmed values are broken,
4843                  * e.g. x201.
4844                  */
4845                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4846                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4847                                                  PF_PIPE_SEL_IVB(pipe));
4848                 else
4849                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4850                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4851                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4852         }
4853 }
4854
4855 void hsw_enable_ips(struct intel_crtc *crtc)
4856 {
4857         struct drm_device *dev = crtc->base.dev;
4858         struct drm_i915_private *dev_priv = to_i915(dev);
4859
4860         if (!crtc->config->ips_enabled)
4861                 return;
4862
4863         /*
4864          * We can only enable IPS after we enable a plane and wait for a vblank
4865          * This function is called from post_plane_update, which is run after
4866          * a vblank wait.
4867          */
4868
4869         assert_plane_enabled(dev_priv, crtc->plane);
4870         if (IS_BROADWELL(dev_priv)) {
4871                 mutex_lock(&dev_priv->pcu_lock);
4872                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4873                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4874                 mutex_unlock(&dev_priv->pcu_lock);
4875                 /* Quoting Art Runyan: "its not safe to expect any particular
4876                  * value in IPS_CTL bit 31 after enabling IPS through the
4877                  * mailbox." Moreover, the mailbox may return a bogus state,
4878                  * so we need to just enable it and continue on.
4879                  */
4880         } else {
4881                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4882                 /* The bit only becomes 1 in the next vblank, so this wait here
4883                  * is essentially intel_wait_for_vblank. If we don't have this
4884                  * and don't wait for vblanks until the end of crtc_enable, then
4885                  * the HW state readout code will complain that the expected
4886                  * IPS_CTL value is not the one we read. */
4887                 if (intel_wait_for_register(dev_priv,
4888                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4889                                             50))
4890                         DRM_ERROR("Timed out waiting for IPS enable\n");
4891         }
4892 }
4893
4894 void hsw_disable_ips(struct intel_crtc *crtc)
4895 {
4896         struct drm_device *dev = crtc->base.dev;
4897         struct drm_i915_private *dev_priv = to_i915(dev);
4898
4899         if (!crtc->config->ips_enabled)
4900                 return;
4901
4902         assert_plane_enabled(dev_priv, crtc->plane);
4903         if (IS_BROADWELL(dev_priv)) {
4904                 mutex_lock(&dev_priv->pcu_lock);
4905                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4906                 mutex_unlock(&dev_priv->pcu_lock);
4907                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4908                 if (intel_wait_for_register(dev_priv,
4909                                             IPS_CTL, IPS_ENABLE, 0,
4910                                             42))
4911                         DRM_ERROR("Timed out waiting for IPS disable\n");
4912         } else {
4913                 I915_WRITE(IPS_CTL, 0);
4914                 POSTING_READ(IPS_CTL);
4915         }
4916
4917         /* We need to wait for a vblank before we can disable the plane. */
4918         intel_wait_for_vblank(dev_priv, crtc->pipe);
4919 }
4920
4921 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4922 {
4923         if (intel_crtc->overlay) {
4924                 struct drm_device *dev = intel_crtc->base.dev;
4925
4926                 mutex_lock(&dev->struct_mutex);
4927                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4928                 mutex_unlock(&dev->struct_mutex);
4929         }
4930
4931         /* Let userspace switch the overlay on again. In most cases userspace
4932          * has to recompute where to put it anyway.
4933          */
4934 }
4935
4936 /**
4937  * intel_post_enable_primary - Perform operations after enabling primary plane
4938  * @crtc: the CRTC whose primary plane was just enabled
4939  *
4940  * Performs potentially sleeping operations that must be done after the primary
4941  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4942  * called due to an explicit primary plane update, or due to an implicit
4943  * re-enable that is caused when a sprite plane is updated to no longer
4944  * completely hide the primary plane.
4945  */
4946 static void
4947 intel_post_enable_primary(struct drm_crtc *crtc)
4948 {
4949         struct drm_device *dev = crtc->dev;
4950         struct drm_i915_private *dev_priv = to_i915(dev);
4951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4952         int pipe = intel_crtc->pipe;
4953
4954         /*
4955          * FIXME IPS should be fine as long as one plane is
4956          * enabled, but in practice it seems to have problems
4957          * when going from primary only to sprite only and vice
4958          * versa.
4959          */
4960         hsw_enable_ips(intel_crtc);
4961
4962         /*
4963          * Gen2 reports pipe underruns whenever all planes are disabled.
4964          * So don't enable underrun reporting before at least some planes
4965          * are enabled.
4966          * FIXME: Need to fix the logic to work when we turn off all planes
4967          * but leave the pipe running.
4968          */
4969         if (IS_GEN2(dev_priv))
4970                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4971
4972         /* Underruns don't always raise interrupts, so check manually. */
4973         intel_check_cpu_fifo_underruns(dev_priv);
4974         intel_check_pch_fifo_underruns(dev_priv);
4975 }
4976
4977 /* FIXME move all this to pre_plane_update() with proper state tracking */
4978 static void
4979 intel_pre_disable_primary(struct drm_crtc *crtc)
4980 {
4981         struct drm_device *dev = crtc->dev;
4982         struct drm_i915_private *dev_priv = to_i915(dev);
4983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984         int pipe = intel_crtc->pipe;
4985
4986         /*
4987          * Gen2 reports pipe underruns whenever all planes are disabled.
4988          * So diasble underrun reporting before all the planes get disabled.
4989          * FIXME: Need to fix the logic to work when we turn off all planes
4990          * but leave the pipe running.
4991          */
4992         if (IS_GEN2(dev_priv))
4993                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4994
4995         /*
4996          * FIXME IPS should be fine as long as one plane is
4997          * enabled, but in practice it seems to have problems
4998          * when going from primary only to sprite only and vice
4999          * versa.
5000          */
5001         hsw_disable_ips(intel_crtc);
5002 }
5003
5004 /* FIXME get rid of this and use pre_plane_update */
5005 static void
5006 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5007 {
5008         struct drm_device *dev = crtc->dev;
5009         struct drm_i915_private *dev_priv = to_i915(dev);
5010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011         int pipe = intel_crtc->pipe;
5012
5013         intel_pre_disable_primary(crtc);
5014
5015         /*
5016          * Vblank time updates from the shadow to live plane control register
5017          * are blocked if the memory self-refresh mode is active at that
5018          * moment. So to make sure the plane gets truly disabled, disable
5019          * first the self-refresh mode. The self-refresh enable bit in turn
5020          * will be checked/applied by the HW only at the next frame start
5021          * event which is after the vblank start event, so we need to have a
5022          * wait-for-vblank between disabling the plane and the pipe.
5023          */
5024         if (HAS_GMCH_DISPLAY(dev_priv) &&
5025             intel_set_memory_cxsr(dev_priv, false))
5026                 intel_wait_for_vblank(dev_priv, pipe);
5027 }
5028
5029 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5030 {
5031         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5032         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5033         struct intel_crtc_state *pipe_config =
5034                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5035                                                 crtc);
5036         struct drm_plane *primary = crtc->base.primary;
5037         struct drm_plane_state *old_pri_state =
5038                 drm_atomic_get_existing_plane_state(old_state, primary);
5039
5040         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5041
5042         if (pipe_config->update_wm_post && pipe_config->base.active)
5043                 intel_update_watermarks(crtc);
5044
5045         if (old_pri_state) {
5046                 struct intel_plane_state *primary_state =
5047                         intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5048                                                          to_intel_plane(primary));
5049                 struct intel_plane_state *old_primary_state =
5050                         to_intel_plane_state(old_pri_state);
5051
5052                 intel_fbc_post_update(crtc);
5053
5054                 if (primary_state->base.visible &&
5055                     (needs_modeset(&pipe_config->base) ||
5056                      !old_primary_state->base.visible))
5057                         intel_post_enable_primary(&crtc->base);
5058         }
5059 }
5060
5061 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5062                                    struct intel_crtc_state *pipe_config)
5063 {
5064         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5065         struct drm_device *dev = crtc->base.dev;
5066         struct drm_i915_private *dev_priv = to_i915(dev);
5067         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5068         struct drm_plane *primary = crtc->base.primary;
5069         struct drm_plane_state *old_pri_state =
5070                 drm_atomic_get_existing_plane_state(old_state, primary);
5071         bool modeset = needs_modeset(&pipe_config->base);
5072         struct intel_atomic_state *old_intel_state =
5073                 to_intel_atomic_state(old_state);
5074
5075         if (old_pri_state) {
5076                 struct intel_plane_state *primary_state =
5077                         intel_atomic_get_new_plane_state(old_intel_state,
5078                                                          to_intel_plane(primary));
5079                 struct intel_plane_state *old_primary_state =
5080                         to_intel_plane_state(old_pri_state);
5081
5082                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5083
5084                 if (old_primary_state->base.visible &&
5085                     (modeset || !primary_state->base.visible))
5086                         intel_pre_disable_primary(&crtc->base);
5087         }
5088
5089         /*
5090          * Vblank time updates from the shadow to live plane control register
5091          * are blocked if the memory self-refresh mode is active at that
5092          * moment. So to make sure the plane gets truly disabled, disable
5093          * first the self-refresh mode. The self-refresh enable bit in turn
5094          * will be checked/applied by the HW only at the next frame start
5095          * event which is after the vblank start event, so we need to have a
5096          * wait-for-vblank between disabling the plane and the pipe.
5097          */
5098         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5099             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5100                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5101
5102         /*
5103          * IVB workaround: must disable low power watermarks for at least
5104          * one frame before enabling scaling.  LP watermarks can be re-enabled
5105          * when scaling is disabled.
5106          *
5107          * WaCxSRDisabledForSpriteScaling:ivb
5108          */
5109         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5110                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5111
5112         /*
5113          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5114          * watermark programming here.
5115          */
5116         if (needs_modeset(&pipe_config->base))
5117                 return;
5118
5119         /*
5120          * For platforms that support atomic watermarks, program the
5121          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5122          * will be the intermediate values that are safe for both pre- and
5123          * post- vblank; when vblank happens, the 'active' values will be set
5124          * to the final 'target' values and we'll do this again to get the
5125          * optimal watermarks.  For gen9+ platforms, the values we program here
5126          * will be the final target values which will get automatically latched
5127          * at vblank time; no further programming will be necessary.
5128          *
5129          * If a platform hasn't been transitioned to atomic watermarks yet,
5130          * we'll continue to update watermarks the old way, if flags tell
5131          * us to.
5132          */
5133         if (dev_priv->display.initial_watermarks != NULL)
5134                 dev_priv->display.initial_watermarks(old_intel_state,
5135                                                      pipe_config);
5136         else if (pipe_config->update_wm_pre)
5137                 intel_update_watermarks(crtc);
5138 }
5139
5140 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5141 {
5142         struct drm_device *dev = crtc->dev;
5143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5144         struct drm_plane *p;
5145         int pipe = intel_crtc->pipe;
5146
5147         intel_crtc_dpms_overlay_disable(intel_crtc);
5148
5149         drm_for_each_plane_mask(p, dev, plane_mask)
5150                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5151
5152         /*
5153          * FIXME: Once we grow proper nuclear flip support out of this we need
5154          * to compute the mask of flip planes precisely. For the time being
5155          * consider this a flip to a NULL plane.
5156          */
5157         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5158 }
5159
5160 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5161                                           struct intel_crtc_state *crtc_state,
5162                                           struct drm_atomic_state *old_state)
5163 {
5164         struct drm_connector_state *conn_state;
5165         struct drm_connector *conn;
5166         int i;
5167
5168         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5169                 struct intel_encoder *encoder =
5170                         to_intel_encoder(conn_state->best_encoder);
5171
5172                 if (conn_state->crtc != crtc)
5173                         continue;
5174
5175                 if (encoder->pre_pll_enable)
5176                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5177         }
5178 }
5179
5180 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5181                                       struct intel_crtc_state *crtc_state,
5182                                       struct drm_atomic_state *old_state)
5183 {
5184         struct drm_connector_state *conn_state;
5185         struct drm_connector *conn;
5186         int i;
5187
5188         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5189                 struct intel_encoder *encoder =
5190                         to_intel_encoder(conn_state->best_encoder);
5191
5192                 if (conn_state->crtc != crtc)
5193                         continue;
5194
5195                 if (encoder->pre_enable)
5196                         encoder->pre_enable(encoder, crtc_state, conn_state);
5197         }
5198 }
5199
5200 static void intel_encoders_enable(struct drm_crtc *crtc,
5201                                   struct intel_crtc_state *crtc_state,
5202                                   struct drm_atomic_state *old_state)
5203 {
5204         struct drm_connector_state *conn_state;
5205         struct drm_connector *conn;
5206         int i;
5207
5208         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5209                 struct intel_encoder *encoder =
5210                         to_intel_encoder(conn_state->best_encoder);
5211
5212                 if (conn_state->crtc != crtc)
5213                         continue;
5214
5215                 encoder->enable(encoder, crtc_state, conn_state);
5216                 intel_opregion_notify_encoder(encoder, true);
5217         }
5218 }
5219
5220 static void intel_encoders_disable(struct drm_crtc *crtc,
5221                                    struct intel_crtc_state *old_crtc_state,
5222                                    struct drm_atomic_state *old_state)
5223 {
5224         struct drm_connector_state *old_conn_state;
5225         struct drm_connector *conn;
5226         int i;
5227
5228         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5229                 struct intel_encoder *encoder =
5230                         to_intel_encoder(old_conn_state->best_encoder);
5231
5232                 if (old_conn_state->crtc != crtc)
5233                         continue;
5234
5235                 intel_opregion_notify_encoder(encoder, false);
5236                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5237         }
5238 }
5239
5240 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5241                                         struct intel_crtc_state *old_crtc_state,
5242                                         struct drm_atomic_state *old_state)
5243 {
5244         struct drm_connector_state *old_conn_state;
5245         struct drm_connector *conn;
5246         int i;
5247
5248         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5249                 struct intel_encoder *encoder =
5250                         to_intel_encoder(old_conn_state->best_encoder);
5251
5252                 if (old_conn_state->crtc != crtc)
5253                         continue;
5254
5255                 if (encoder->post_disable)
5256                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5257         }
5258 }
5259
5260 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5261                                             struct intel_crtc_state *old_crtc_state,
5262                                             struct drm_atomic_state *old_state)
5263 {
5264         struct drm_connector_state *old_conn_state;
5265         struct drm_connector *conn;
5266         int i;
5267
5268         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5269                 struct intel_encoder *encoder =
5270                         to_intel_encoder(old_conn_state->best_encoder);
5271
5272                 if (old_conn_state->crtc != crtc)
5273                         continue;
5274
5275                 if (encoder->post_pll_disable)
5276                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5277         }
5278 }
5279
5280 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5281                                  struct drm_atomic_state *old_state)
5282 {
5283         struct drm_crtc *crtc = pipe_config->base.crtc;
5284         struct drm_device *dev = crtc->dev;
5285         struct drm_i915_private *dev_priv = to_i915(dev);
5286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5287         int pipe = intel_crtc->pipe;
5288         struct intel_atomic_state *old_intel_state =
5289                 to_intel_atomic_state(old_state);
5290
5291         if (WARN_ON(intel_crtc->active))
5292                 return;
5293
5294         /*
5295          * Sometimes spurious CPU pipe underruns happen during FDI
5296          * training, at least with VGA+HDMI cloning. Suppress them.
5297          *
5298          * On ILK we get an occasional spurious CPU pipe underruns
5299          * between eDP port A enable and vdd enable. Also PCH port
5300          * enable seems to result in the occasional CPU pipe underrun.
5301          *
5302          * Spurious PCH underruns also occur during PCH enabling.
5303          */
5304         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5305                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5306         if (intel_crtc->config->has_pch_encoder)
5307                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5308
5309         if (intel_crtc->config->has_pch_encoder)
5310                 intel_prepare_shared_dpll(intel_crtc);
5311
5312         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5313                 intel_dp_set_m_n(intel_crtc, M1_N1);
5314
5315         intel_set_pipe_timings(intel_crtc);
5316         intel_set_pipe_src_size(intel_crtc);
5317
5318         if (intel_crtc->config->has_pch_encoder) {
5319                 intel_cpu_transcoder_set_m_n(intel_crtc,
5320                                      &intel_crtc->config->fdi_m_n, NULL);
5321         }
5322
5323         ironlake_set_pipeconf(crtc);
5324
5325         intel_crtc->active = true;
5326
5327         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5328
5329         if (intel_crtc->config->has_pch_encoder) {
5330                 /* Note: FDI PLL enabling _must_ be done before we enable the
5331                  * cpu pipes, hence this is separate from all the other fdi/pch
5332                  * enabling. */
5333                 ironlake_fdi_pll_enable(intel_crtc);
5334         } else {
5335                 assert_fdi_tx_disabled(dev_priv, pipe);
5336                 assert_fdi_rx_disabled(dev_priv, pipe);
5337         }
5338
5339         ironlake_pfit_enable(intel_crtc);
5340
5341         /*
5342          * On ILK+ LUT must be loaded before the pipe is running but with
5343          * clocks enabled
5344          */
5345         intel_color_load_luts(&pipe_config->base);
5346
5347         if (dev_priv->display.initial_watermarks != NULL)
5348                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5349         intel_enable_pipe(intel_crtc);
5350
5351         if (intel_crtc->config->has_pch_encoder)
5352                 ironlake_pch_enable(pipe_config);
5353
5354         assert_vblank_disabled(crtc);
5355         drm_crtc_vblank_on(crtc);
5356
5357         intel_encoders_enable(crtc, pipe_config, old_state);
5358
5359         if (HAS_PCH_CPT(dev_priv))
5360                 cpt_verify_modeset(dev, intel_crtc->pipe);
5361
5362         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5363         if (intel_crtc->config->has_pch_encoder)
5364                 intel_wait_for_vblank(dev_priv, pipe);
5365         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5366         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5367 }
5368
5369 /* IPS only exists on ULT machines and is tied to pipe A. */
5370 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5371 {
5372         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5373 }
5374
5375 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5376                                             enum pipe pipe, bool apply)
5377 {
5378         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5379         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5380
5381         if (apply)
5382                 val |= mask;
5383         else
5384                 val &= ~mask;
5385
5386         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5387 }
5388
5389 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5390                                 struct drm_atomic_state *old_state)
5391 {
5392         struct drm_crtc *crtc = pipe_config->base.crtc;
5393         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5395         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5396         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5397         struct intel_atomic_state *old_intel_state =
5398                 to_intel_atomic_state(old_state);
5399         bool psl_clkgate_wa;
5400
5401         if (WARN_ON(intel_crtc->active))
5402                 return;
5403
5404         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5405
5406         if (intel_crtc->config->shared_dpll)
5407                 intel_enable_shared_dpll(intel_crtc);
5408
5409         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5410                 intel_dp_set_m_n(intel_crtc, M1_N1);
5411
5412         if (!transcoder_is_dsi(cpu_transcoder))
5413                 intel_set_pipe_timings(intel_crtc);
5414
5415         intel_set_pipe_src_size(intel_crtc);
5416
5417         if (cpu_transcoder != TRANSCODER_EDP &&
5418             !transcoder_is_dsi(cpu_transcoder)) {
5419                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5420                            intel_crtc->config->pixel_multiplier - 1);
5421         }
5422
5423         if (intel_crtc->config->has_pch_encoder) {
5424                 intel_cpu_transcoder_set_m_n(intel_crtc,
5425                                      &intel_crtc->config->fdi_m_n, NULL);
5426         }
5427
5428         if (!transcoder_is_dsi(cpu_transcoder))
5429                 haswell_set_pipeconf(crtc);
5430
5431         haswell_set_pipemisc(crtc);
5432
5433         intel_color_set_csc(&pipe_config->base);
5434
5435         intel_crtc->active = true;
5436
5437         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5438
5439         if (!transcoder_is_dsi(cpu_transcoder))
5440                 intel_ddi_enable_pipe_clock(pipe_config);
5441
5442         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5443         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5444                          intel_crtc->config->pch_pfit.enabled;
5445         if (psl_clkgate_wa)
5446                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5447
5448         if (INTEL_GEN(dev_priv) >= 9)
5449                 skylake_pfit_enable(intel_crtc);
5450         else
5451                 ironlake_pfit_enable(intel_crtc);
5452
5453         /*
5454          * On ILK+ LUT must be loaded before the pipe is running but with
5455          * clocks enabled
5456          */
5457         intel_color_load_luts(&pipe_config->base);
5458
5459         intel_ddi_set_pipe_settings(pipe_config);
5460         if (!transcoder_is_dsi(cpu_transcoder))
5461                 intel_ddi_enable_transcoder_func(pipe_config);
5462
5463         if (dev_priv->display.initial_watermarks != NULL)
5464                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5465
5466         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5467         if (!transcoder_is_dsi(cpu_transcoder))
5468                 intel_enable_pipe(intel_crtc);
5469
5470         if (intel_crtc->config->has_pch_encoder)
5471                 lpt_pch_enable(pipe_config);
5472
5473         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5474                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5475
5476         assert_vblank_disabled(crtc);
5477         drm_crtc_vblank_on(crtc);
5478
5479         intel_encoders_enable(crtc, pipe_config, old_state);
5480
5481         if (psl_clkgate_wa) {
5482                 intel_wait_for_vblank(dev_priv, pipe);
5483                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5484         }
5485
5486         /* If we change the relative order between pipe/planes enabling, we need
5487          * to change the workaround. */
5488         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5489         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5490                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5491                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5492         }
5493 }
5494
5495 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5496 {
5497         struct drm_device *dev = crtc->base.dev;
5498         struct drm_i915_private *dev_priv = to_i915(dev);
5499         int pipe = crtc->pipe;
5500
5501         /* To avoid upsetting the power well on haswell only disable the pfit if
5502          * it's in use. The hw state code will make sure we get this right. */
5503         if (force || crtc->config->pch_pfit.enabled) {
5504                 I915_WRITE(PF_CTL(pipe), 0);
5505                 I915_WRITE(PF_WIN_POS(pipe), 0);
5506                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5507         }
5508 }
5509
5510 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5511                                   struct drm_atomic_state *old_state)
5512 {
5513         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5514         struct drm_device *dev = crtc->dev;
5515         struct drm_i915_private *dev_priv = to_i915(dev);
5516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5517         int pipe = intel_crtc->pipe;
5518
5519         /*
5520          * Sometimes spurious CPU pipe underruns happen when the
5521          * pipe is already disabled, but FDI RX/TX is still enabled.
5522          * Happens at least with VGA+HDMI cloning. Suppress them.
5523          */
5524         if (intel_crtc->config->has_pch_encoder) {
5525                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5526                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5527         }
5528
5529         intel_encoders_disable(crtc, old_crtc_state, old_state);
5530
5531         drm_crtc_vblank_off(crtc);
5532         assert_vblank_disabled(crtc);
5533
5534         intel_disable_pipe(intel_crtc);
5535
5536         ironlake_pfit_disable(intel_crtc, false);
5537
5538         if (intel_crtc->config->has_pch_encoder)
5539                 ironlake_fdi_disable(crtc);
5540
5541         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5542
5543         if (intel_crtc->config->has_pch_encoder) {
5544                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5545
5546                 if (HAS_PCH_CPT(dev_priv)) {
5547                         i915_reg_t reg;
5548                         u32 temp;
5549
5550                         /* disable TRANS_DP_CTL */
5551                         reg = TRANS_DP_CTL(pipe);
5552                         temp = I915_READ(reg);
5553                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5554                                   TRANS_DP_PORT_SEL_MASK);
5555                         temp |= TRANS_DP_PORT_SEL_NONE;
5556                         I915_WRITE(reg, temp);
5557
5558                         /* disable DPLL_SEL */
5559                         temp = I915_READ(PCH_DPLL_SEL);
5560                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5561                         I915_WRITE(PCH_DPLL_SEL, temp);
5562                 }
5563
5564                 ironlake_fdi_pll_disable(intel_crtc);
5565         }
5566
5567         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5568         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5569 }
5570
5571 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5572                                  struct drm_atomic_state *old_state)
5573 {
5574         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5575         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5577         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5578
5579         intel_encoders_disable(crtc, old_crtc_state, old_state);
5580
5581         drm_crtc_vblank_off(crtc);
5582         assert_vblank_disabled(crtc);
5583
5584         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5585         if (!transcoder_is_dsi(cpu_transcoder))
5586                 intel_disable_pipe(intel_crtc);
5587
5588         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5589                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5590
5591         if (!transcoder_is_dsi(cpu_transcoder))
5592                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5593
5594         if (INTEL_GEN(dev_priv) >= 9)
5595                 skylake_scaler_disable(intel_crtc);
5596         else
5597                 ironlake_pfit_disable(intel_crtc, false);
5598
5599         if (!transcoder_is_dsi(cpu_transcoder))
5600                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5601
5602         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5603 }
5604
5605 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5606 {
5607         struct drm_device *dev = crtc->base.dev;
5608         struct drm_i915_private *dev_priv = to_i915(dev);
5609         struct intel_crtc_state *pipe_config = crtc->config;
5610
5611         if (!pipe_config->gmch_pfit.control)
5612                 return;
5613
5614         /*
5615          * The panel fitter should only be adjusted whilst the pipe is disabled,
5616          * according to register description and PRM.
5617          */
5618         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5619         assert_pipe_disabled(dev_priv, crtc->pipe);
5620
5621         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5622         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5623
5624         /* Border color in case we don't scale up to the full screen. Black by
5625          * default, change to something else for debugging. */
5626         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5627 }
5628
5629 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5630 {
5631         switch (port) {
5632         case PORT_A:
5633                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5634         case PORT_B:
5635                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5636         case PORT_C:
5637                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5638         case PORT_D:
5639                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5640         case PORT_E:
5641                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5642         default:
5643                 MISSING_CASE(port);
5644                 return POWER_DOMAIN_PORT_OTHER;
5645         }
5646 }
5647
5648 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5649                                   struct intel_crtc_state *crtc_state)
5650 {
5651         struct drm_device *dev = crtc->dev;
5652         struct drm_i915_private *dev_priv = to_i915(dev);
5653         struct drm_encoder *encoder;
5654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655         enum pipe pipe = intel_crtc->pipe;
5656         u64 mask;
5657         enum transcoder transcoder = crtc_state->cpu_transcoder;
5658
5659         if (!crtc_state->base.active)
5660                 return 0;
5661
5662         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5663         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5664         if (crtc_state->pch_pfit.enabled ||
5665             crtc_state->pch_pfit.force_thru)
5666                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5667
5668         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5669                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5670
5671                 mask |= BIT_ULL(intel_encoder->power_domain);
5672         }
5673
5674         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5675                 mask |= BIT(POWER_DOMAIN_AUDIO);
5676
5677         if (crtc_state->shared_dpll)
5678                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5679
5680         return mask;
5681 }
5682
5683 static u64
5684 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5685                                struct intel_crtc_state *crtc_state)
5686 {
5687         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5689         enum intel_display_power_domain domain;
5690         u64 domains, new_domains, old_domains;
5691
5692         old_domains = intel_crtc->enabled_power_domains;
5693         intel_crtc->enabled_power_domains = new_domains =
5694                 get_crtc_power_domains(crtc, crtc_state);
5695
5696         domains = new_domains & ~old_domains;
5697
5698         for_each_power_domain(domain, domains)
5699                 intel_display_power_get(dev_priv, domain);
5700
5701         return old_domains & ~new_domains;
5702 }
5703
5704 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5705                                       u64 domains)
5706 {
5707         enum intel_display_power_domain domain;
5708
5709         for_each_power_domain(domain, domains)
5710                 intel_display_power_put(dev_priv, domain);
5711 }
5712
5713 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5714                                    struct drm_atomic_state *old_state)
5715 {
5716         struct intel_atomic_state *old_intel_state =
5717                 to_intel_atomic_state(old_state);
5718         struct drm_crtc *crtc = pipe_config->base.crtc;
5719         struct drm_device *dev = crtc->dev;
5720         struct drm_i915_private *dev_priv = to_i915(dev);
5721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5722         int pipe = intel_crtc->pipe;
5723
5724         if (WARN_ON(intel_crtc->active))
5725                 return;
5726
5727         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5728                 intel_dp_set_m_n(intel_crtc, M1_N1);
5729
5730         intel_set_pipe_timings(intel_crtc);
5731         intel_set_pipe_src_size(intel_crtc);
5732
5733         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5734                 struct drm_i915_private *dev_priv = to_i915(dev);
5735
5736                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5737                 I915_WRITE(CHV_CANVAS(pipe), 0);
5738         }
5739
5740         i9xx_set_pipeconf(intel_crtc);
5741
5742         intel_crtc->active = true;
5743
5744         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5745
5746         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5747
5748         if (IS_CHERRYVIEW(dev_priv)) {
5749                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5750                 chv_enable_pll(intel_crtc, intel_crtc->config);
5751         } else {
5752                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5753                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5754         }
5755
5756         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5757
5758         i9xx_pfit_enable(intel_crtc);
5759
5760         intel_color_load_luts(&pipe_config->base);
5761
5762         dev_priv->display.initial_watermarks(old_intel_state,
5763                                              pipe_config);
5764         intel_enable_pipe(intel_crtc);
5765
5766         assert_vblank_disabled(crtc);
5767         drm_crtc_vblank_on(crtc);
5768
5769         intel_encoders_enable(crtc, pipe_config, old_state);
5770 }
5771
5772 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5773 {
5774         struct drm_device *dev = crtc->base.dev;
5775         struct drm_i915_private *dev_priv = to_i915(dev);
5776
5777         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5778         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5779 }
5780
5781 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5782                              struct drm_atomic_state *old_state)
5783 {
5784         struct intel_atomic_state *old_intel_state =
5785                 to_intel_atomic_state(old_state);
5786         struct drm_crtc *crtc = pipe_config->base.crtc;
5787         struct drm_device *dev = crtc->dev;
5788         struct drm_i915_private *dev_priv = to_i915(dev);
5789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5790         enum pipe pipe = intel_crtc->pipe;
5791
5792         if (WARN_ON(intel_crtc->active))
5793                 return;
5794
5795         i9xx_set_pll_dividers(intel_crtc);
5796
5797         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5798                 intel_dp_set_m_n(intel_crtc, M1_N1);
5799
5800         intel_set_pipe_timings(intel_crtc);
5801         intel_set_pipe_src_size(intel_crtc);
5802
5803         i9xx_set_pipeconf(intel_crtc);
5804
5805         intel_crtc->active = true;
5806
5807         if (!IS_GEN2(dev_priv))
5808                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5809
5810         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5811
5812         i9xx_enable_pll(intel_crtc, pipe_config);
5813
5814         i9xx_pfit_enable(intel_crtc);
5815
5816         intel_color_load_luts(&pipe_config->base);
5817
5818         if (dev_priv->display.initial_watermarks != NULL)
5819                 dev_priv->display.initial_watermarks(old_intel_state,
5820                                                      intel_crtc->config);
5821         else
5822                 intel_update_watermarks(intel_crtc);
5823         intel_enable_pipe(intel_crtc);
5824
5825         assert_vblank_disabled(crtc);
5826         drm_crtc_vblank_on(crtc);
5827
5828         intel_encoders_enable(crtc, pipe_config, old_state);
5829 }
5830
5831 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5832 {
5833         struct drm_device *dev = crtc->base.dev;
5834         struct drm_i915_private *dev_priv = to_i915(dev);
5835
5836         if (!crtc->config->gmch_pfit.control)
5837                 return;
5838
5839         assert_pipe_disabled(dev_priv, crtc->pipe);
5840
5841         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5842                          I915_READ(PFIT_CONTROL));
5843         I915_WRITE(PFIT_CONTROL, 0);
5844 }
5845
5846 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5847                               struct drm_atomic_state *old_state)
5848 {
5849         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5850         struct drm_device *dev = crtc->dev;
5851         struct drm_i915_private *dev_priv = to_i915(dev);
5852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5853         int pipe = intel_crtc->pipe;
5854
5855         /*
5856          * On gen2 planes are double buffered but the pipe isn't, so we must
5857          * wait for planes to fully turn off before disabling the pipe.
5858          */
5859         if (IS_GEN2(dev_priv))
5860                 intel_wait_for_vblank(dev_priv, pipe);
5861
5862         intel_encoders_disable(crtc, old_crtc_state, old_state);
5863
5864         drm_crtc_vblank_off(crtc);
5865         assert_vblank_disabled(crtc);
5866
5867         intel_disable_pipe(intel_crtc);
5868
5869         i9xx_pfit_disable(intel_crtc);
5870
5871         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5872
5873         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5874                 if (IS_CHERRYVIEW(dev_priv))
5875                         chv_disable_pll(dev_priv, pipe);
5876                 else if (IS_VALLEYVIEW(dev_priv))
5877                         vlv_disable_pll(dev_priv, pipe);
5878                 else
5879                         i9xx_disable_pll(intel_crtc);
5880         }
5881
5882         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5883
5884         if (!IS_GEN2(dev_priv))
5885                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5886
5887         if (!dev_priv->display.initial_watermarks)
5888                 intel_update_watermarks(intel_crtc);
5889
5890         /* clock the pipe down to 640x480@60 to potentially save power */
5891         if (IS_I830(dev_priv))
5892                 i830_enable_pipe(dev_priv, pipe);
5893 }
5894
5895 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5896                                         struct drm_modeset_acquire_ctx *ctx)
5897 {
5898         struct intel_encoder *encoder;
5899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5900         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5901         enum intel_display_power_domain domain;
5902         u64 domains;
5903         struct drm_atomic_state *state;
5904         struct intel_crtc_state *crtc_state;
5905         int ret;
5906
5907         if (!intel_crtc->active)
5908                 return;
5909
5910         if (crtc->primary->state->visible) {
5911                 intel_pre_disable_primary_noatomic(crtc);
5912
5913                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5914                 crtc->primary->state->visible = false;
5915         }
5916
5917         state = drm_atomic_state_alloc(crtc->dev);
5918         if (!state) {
5919                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5920                               crtc->base.id, crtc->name);
5921                 return;
5922         }
5923
5924         state->acquire_ctx = ctx;
5925
5926         /* Everything's already locked, -EDEADLK can't happen. */
5927         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5928         ret = drm_atomic_add_affected_connectors(state, crtc);
5929
5930         WARN_ON(IS_ERR(crtc_state) || ret);
5931
5932         dev_priv->display.crtc_disable(crtc_state, state);
5933
5934         drm_atomic_state_put(state);
5935
5936         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5937                       crtc->base.id, crtc->name);
5938
5939         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5940         crtc->state->active = false;
5941         intel_crtc->active = false;
5942         crtc->enabled = false;
5943         crtc->state->connector_mask = 0;
5944         crtc->state->encoder_mask = 0;
5945
5946         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5947                 encoder->base.crtc = NULL;
5948
5949         intel_fbc_disable(intel_crtc);
5950         intel_update_watermarks(intel_crtc);
5951         intel_disable_shared_dpll(intel_crtc);
5952
5953         domains = intel_crtc->enabled_power_domains;
5954         for_each_power_domain(domain, domains)
5955                 intel_display_power_put(dev_priv, domain);
5956         intel_crtc->enabled_power_domains = 0;
5957
5958         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5959         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5960 }
5961
5962 /*
5963  * turn all crtc's off, but do not adjust state
5964  * This has to be paired with a call to intel_modeset_setup_hw_state.
5965  */
5966 int intel_display_suspend(struct drm_device *dev)
5967 {
5968         struct drm_i915_private *dev_priv = to_i915(dev);
5969         struct drm_atomic_state *state;
5970         int ret;
5971
5972         state = drm_atomic_helper_suspend(dev);
5973         ret = PTR_ERR_OR_ZERO(state);
5974         if (ret)
5975                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5976         else
5977                 dev_priv->modeset_restore_state = state;
5978         return ret;
5979 }
5980
5981 void intel_encoder_destroy(struct drm_encoder *encoder)
5982 {
5983         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5984
5985         drm_encoder_cleanup(encoder);
5986         kfree(intel_encoder);
5987 }
5988
5989 /* Cross check the actual hw state with our own modeset state tracking (and it's
5990  * internal consistency). */
5991 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5992                                          struct drm_connector_state *conn_state)
5993 {
5994         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5995
5996         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5997                       connector->base.base.id,
5998                       connector->base.name);
5999
6000         if (connector->get_hw_state(connector)) {
6001                 struct intel_encoder *encoder = connector->encoder;
6002
6003                 I915_STATE_WARN(!crtc_state,
6004                          "connector enabled without attached crtc\n");
6005
6006                 if (!crtc_state)
6007                         return;
6008
6009                 I915_STATE_WARN(!crtc_state->active,
6010                       "connector is active, but attached crtc isn't\n");
6011
6012                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6013                         return;
6014
6015                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6016                         "atomic encoder doesn't match attached encoder\n");
6017
6018                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6019                         "attached encoder crtc differs from connector crtc\n");
6020         } else {
6021                 I915_STATE_WARN(crtc_state && crtc_state->active,
6022                         "attached crtc is active, but connector isn't\n");
6023                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6024                         "best encoder set without crtc!\n");
6025         }
6026 }
6027
6028 int intel_connector_init(struct intel_connector *connector)
6029 {
6030         struct intel_digital_connector_state *conn_state;
6031
6032         /*
6033          * Allocate enough memory to hold intel_digital_connector_state,
6034          * This might be a few bytes too many, but for connectors that don't
6035          * need it we'll free the state and allocate a smaller one on the first
6036          * succesful commit anyway.
6037          */
6038         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6039         if (!conn_state)
6040                 return -ENOMEM;
6041
6042         __drm_atomic_helper_connector_reset(&connector->base,
6043                                             &conn_state->base);
6044
6045         return 0;
6046 }
6047
6048 struct intel_connector *intel_connector_alloc(void)
6049 {
6050         struct intel_connector *connector;
6051
6052         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6053         if (!connector)
6054                 return NULL;
6055
6056         if (intel_connector_init(connector) < 0) {
6057                 kfree(connector);
6058                 return NULL;
6059         }
6060
6061         return connector;
6062 }
6063
6064 /*
6065  * Free the bits allocated by intel_connector_alloc.
6066  * This should only be used after intel_connector_alloc has returned
6067  * successfully, and before drm_connector_init returns successfully.
6068  * Otherwise the destroy callbacks for the connector and the state should
6069  * take care of proper cleanup/free
6070  */
6071 void intel_connector_free(struct intel_connector *connector)
6072 {
6073         kfree(to_intel_digital_connector_state(connector->base.state));
6074         kfree(connector);
6075 }
6076
6077 /* Simple connector->get_hw_state implementation for encoders that support only
6078  * one connector and no cloning and hence the encoder state determines the state
6079  * of the connector. */
6080 bool intel_connector_get_hw_state(struct intel_connector *connector)
6081 {
6082         enum pipe pipe = 0;
6083         struct intel_encoder *encoder = connector->encoder;
6084
6085         return encoder->get_hw_state(encoder, &pipe);
6086 }
6087
6088 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6089 {
6090         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6091                 return crtc_state->fdi_lanes;
6092
6093         return 0;
6094 }
6095
6096 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6097                                      struct intel_crtc_state *pipe_config)
6098 {
6099         struct drm_i915_private *dev_priv = to_i915(dev);
6100         struct drm_atomic_state *state = pipe_config->base.state;
6101         struct intel_crtc *other_crtc;
6102         struct intel_crtc_state *other_crtc_state;
6103
6104         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6105                       pipe_name(pipe), pipe_config->fdi_lanes);
6106         if (pipe_config->fdi_lanes > 4) {
6107                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6108                               pipe_name(pipe), pipe_config->fdi_lanes);
6109                 return -EINVAL;
6110         }
6111
6112         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6113                 if (pipe_config->fdi_lanes > 2) {
6114                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6115                                       pipe_config->fdi_lanes);
6116                         return -EINVAL;
6117                 } else {
6118                         return 0;
6119                 }
6120         }
6121
6122         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6123                 return 0;
6124
6125         /* Ivybridge 3 pipe is really complicated */
6126         switch (pipe) {
6127         case PIPE_A:
6128                 return 0;
6129         case PIPE_B:
6130                 if (pipe_config->fdi_lanes <= 2)
6131                         return 0;
6132
6133                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6134                 other_crtc_state =
6135                         intel_atomic_get_crtc_state(state, other_crtc);
6136                 if (IS_ERR(other_crtc_state))
6137                         return PTR_ERR(other_crtc_state);
6138
6139                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6140                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6141                                       pipe_name(pipe), pipe_config->fdi_lanes);
6142                         return -EINVAL;
6143                 }
6144                 return 0;
6145         case PIPE_C:
6146                 if (pipe_config->fdi_lanes > 2) {
6147                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6148                                       pipe_name(pipe), pipe_config->fdi_lanes);
6149                         return -EINVAL;
6150                 }
6151
6152                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6153                 other_crtc_state =
6154                         intel_atomic_get_crtc_state(state, other_crtc);
6155                 if (IS_ERR(other_crtc_state))
6156                         return PTR_ERR(other_crtc_state);
6157
6158                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6159                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6160                         return -EINVAL;
6161                 }
6162                 return 0;
6163         default:
6164                 BUG();
6165         }
6166 }
6167
6168 #define RETRY 1
6169 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6170                                        struct intel_crtc_state *pipe_config)
6171 {
6172         struct drm_device *dev = intel_crtc->base.dev;
6173         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6174         int lane, link_bw, fdi_dotclock, ret;
6175         bool needs_recompute = false;
6176
6177 retry:
6178         /* FDI is a binary signal running at ~2.7GHz, encoding
6179          * each output octet as 10 bits. The actual frequency
6180          * is stored as a divider into a 100MHz clock, and the
6181          * mode pixel clock is stored in units of 1KHz.
6182          * Hence the bw of each lane in terms of the mode signal
6183          * is:
6184          */
6185         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6186
6187         fdi_dotclock = adjusted_mode->crtc_clock;
6188
6189         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6190                                            pipe_config->pipe_bpp);
6191
6192         pipe_config->fdi_lanes = lane;
6193
6194         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6195                                link_bw, &pipe_config->fdi_m_n, false);
6196
6197         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6198         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6199                 pipe_config->pipe_bpp -= 2*3;
6200                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6201                               pipe_config->pipe_bpp);
6202                 needs_recompute = true;
6203                 pipe_config->bw_constrained = true;
6204
6205                 goto retry;
6206         }
6207
6208         if (needs_recompute)
6209                 return RETRY;
6210
6211         return ret;
6212 }
6213
6214 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6215                                      struct intel_crtc_state *pipe_config)
6216 {
6217         if (pipe_config->ips_force_disable)
6218                 return false;
6219
6220         if (pipe_config->pipe_bpp > 24)
6221                 return false;
6222
6223         /* HSW can handle pixel rate up to cdclk? */
6224         if (IS_HASWELL(dev_priv))
6225                 return true;
6226
6227         /*
6228          * We compare against max which means we must take
6229          * the increased cdclk requirement into account when
6230          * calculating the new cdclk.
6231          *
6232          * Should measure whether using a lower cdclk w/o IPS
6233          */
6234         return pipe_config->pixel_rate <=
6235                 dev_priv->max_cdclk_freq * 95 / 100;
6236 }
6237
6238 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6239                                    struct intel_crtc_state *pipe_config)
6240 {
6241         struct drm_device *dev = crtc->base.dev;
6242         struct drm_i915_private *dev_priv = to_i915(dev);
6243
6244         pipe_config->ips_enabled = i915_modparams.enable_ips &&
6245                 hsw_crtc_supports_ips(crtc) &&
6246                 pipe_config_supports_ips(dev_priv, pipe_config);
6247 }
6248
6249 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6250 {
6251         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6252
6253         /* GDG double wide on either pipe, otherwise pipe A only */
6254         return INTEL_INFO(dev_priv)->gen < 4 &&
6255                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6256 }
6257
6258 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6259 {
6260         uint32_t pixel_rate;
6261
6262         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6263
6264         /*
6265          * We only use IF-ID interlacing. If we ever use
6266          * PF-ID we'll need to adjust the pixel_rate here.
6267          */
6268
6269         if (pipe_config->pch_pfit.enabled) {
6270                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6271                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6272
6273                 pipe_w = pipe_config->pipe_src_w;
6274                 pipe_h = pipe_config->pipe_src_h;
6275
6276                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6277                 pfit_h = pfit_size & 0xFFFF;
6278                 if (pipe_w < pfit_w)
6279                         pipe_w = pfit_w;
6280                 if (pipe_h < pfit_h)
6281                         pipe_h = pfit_h;
6282
6283                 if (WARN_ON(!pfit_w || !pfit_h))
6284                         return pixel_rate;
6285
6286                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6287                                      pfit_w * pfit_h);
6288         }
6289
6290         return pixel_rate;
6291 }
6292
6293 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6294 {
6295         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6296
6297         if (HAS_GMCH_DISPLAY(dev_priv))
6298                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6299                 crtc_state->pixel_rate =
6300                         crtc_state->base.adjusted_mode.crtc_clock;
6301         else
6302                 crtc_state->pixel_rate =
6303                         ilk_pipe_pixel_rate(crtc_state);
6304 }
6305
6306 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6307                                      struct intel_crtc_state *pipe_config)
6308 {
6309         struct drm_device *dev = crtc->base.dev;
6310         struct drm_i915_private *dev_priv = to_i915(dev);
6311         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6312         int clock_limit = dev_priv->max_dotclk_freq;
6313
6314         if (INTEL_GEN(dev_priv) < 4) {
6315                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6316
6317                 /*
6318                  * Enable double wide mode when the dot clock
6319                  * is > 90% of the (display) core speed.
6320                  */
6321                 if (intel_crtc_supports_double_wide(crtc) &&
6322                     adjusted_mode->crtc_clock > clock_limit) {
6323                         clock_limit = dev_priv->max_dotclk_freq;
6324                         pipe_config->double_wide = true;
6325                 }
6326         }
6327
6328         if (adjusted_mode->crtc_clock > clock_limit) {
6329                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6330                               adjusted_mode->crtc_clock, clock_limit,
6331                               yesno(pipe_config->double_wide));
6332                 return -EINVAL;
6333         }
6334
6335         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6336                 /*
6337                  * There is only one pipe CSC unit per pipe, and we need that
6338                  * for output conversion from RGB->YCBCR. So if CTM is already
6339                  * applied we can't support YCBCR420 output.
6340                  */
6341                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6342                 return -EINVAL;
6343         }
6344
6345         /*
6346          * Pipe horizontal size must be even in:
6347          * - DVO ganged mode
6348          * - LVDS dual channel mode
6349          * - Double wide pipe
6350          */
6351         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6352              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6353                 pipe_config->pipe_src_w &= ~1;
6354
6355         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6356          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6357          */
6358         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6359                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6360                 return -EINVAL;
6361
6362         intel_crtc_compute_pixel_rate(pipe_config);
6363
6364         if (HAS_IPS(dev_priv))
6365                 hsw_compute_ips_config(crtc, pipe_config);
6366
6367         if (pipe_config->has_pch_encoder)
6368                 return ironlake_fdi_compute_config(crtc, pipe_config);
6369
6370         return 0;
6371 }
6372
6373 static void
6374 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6375 {
6376         while (*num > DATA_LINK_M_N_MASK ||
6377                *den > DATA_LINK_M_N_MASK) {
6378                 *num >>= 1;
6379                 *den >>= 1;
6380         }
6381 }
6382
6383 static void compute_m_n(unsigned int m, unsigned int n,
6384                         uint32_t *ret_m, uint32_t *ret_n,
6385                         bool reduce_m_n)
6386 {
6387         /*
6388          * Reduce M/N as much as possible without loss in precision. Several DP
6389          * dongles in particular seem to be fussy about too large *link* M/N
6390          * values. The passed in values are more likely to have the least
6391          * significant bits zero than M after rounding below, so do this first.
6392          */
6393         if (reduce_m_n) {
6394                 while ((m & 1) == 0 && (n & 1) == 0) {
6395                         m >>= 1;
6396                         n >>= 1;
6397                 }
6398         }
6399
6400         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6401         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6402         intel_reduce_m_n_ratio(ret_m, ret_n);
6403 }
6404
6405 void
6406 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6407                        int pixel_clock, int link_clock,
6408                        struct intel_link_m_n *m_n,
6409                        bool reduce_m_n)
6410 {
6411         m_n->tu = 64;
6412
6413         compute_m_n(bits_per_pixel * pixel_clock,
6414                     link_clock * nlanes * 8,
6415                     &m_n->gmch_m, &m_n->gmch_n,
6416                     reduce_m_n);
6417
6418         compute_m_n(pixel_clock, link_clock,
6419                     &m_n->link_m, &m_n->link_n,
6420                     reduce_m_n);
6421 }
6422
6423 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6424 {
6425         if (i915_modparams.panel_use_ssc >= 0)
6426                 return i915_modparams.panel_use_ssc != 0;
6427         return dev_priv->vbt.lvds_use_ssc
6428                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6429 }
6430
6431 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6432 {
6433         return (1 << dpll->n) << 16 | dpll->m2;
6434 }
6435
6436 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6437 {
6438         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6439 }
6440
6441 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6442                                      struct intel_crtc_state *crtc_state,
6443                                      struct dpll *reduced_clock)
6444 {
6445         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6446         u32 fp, fp2 = 0;
6447
6448         if (IS_PINEVIEW(dev_priv)) {
6449                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6450                 if (reduced_clock)
6451                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6452         } else {
6453                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6454                 if (reduced_clock)
6455                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6456         }
6457
6458         crtc_state->dpll_hw_state.fp0 = fp;
6459
6460         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6461             reduced_clock) {
6462                 crtc_state->dpll_hw_state.fp1 = fp2;
6463         } else {
6464                 crtc_state->dpll_hw_state.fp1 = fp;
6465         }
6466 }
6467
6468 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6469                 pipe)
6470 {
6471         u32 reg_val;
6472
6473         /*
6474          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6475          * and set it to a reasonable value instead.
6476          */
6477         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6478         reg_val &= 0xffffff00;
6479         reg_val |= 0x00000030;
6480         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6481
6482         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6483         reg_val &= 0x00ffffff;
6484         reg_val |= 0x8c000000;
6485         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6486
6487         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6488         reg_val &= 0xffffff00;
6489         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6490
6491         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6492         reg_val &= 0x00ffffff;
6493         reg_val |= 0xb0000000;
6494         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6495 }
6496
6497 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6498                                          struct intel_link_m_n *m_n)
6499 {
6500         struct drm_device *dev = crtc->base.dev;
6501         struct drm_i915_private *dev_priv = to_i915(dev);
6502         int pipe = crtc->pipe;
6503
6504         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6505         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6506         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6507         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6508 }
6509
6510 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6511                                          struct intel_link_m_n *m_n,
6512                                          struct intel_link_m_n *m2_n2)
6513 {
6514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6515         int pipe = crtc->pipe;
6516         enum transcoder transcoder = crtc->config->cpu_transcoder;
6517
6518         if (INTEL_GEN(dev_priv) >= 5) {
6519                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6520                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6521                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6522                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6523                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6524                  * for gen < 8) and if DRRS is supported (to make sure the
6525                  * registers are not unnecessarily accessed).
6526                  */
6527                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6528                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6529                         I915_WRITE(PIPE_DATA_M2(transcoder),
6530                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6531                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6532                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6533                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6534                 }
6535         } else {
6536                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6537                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6538                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6539                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6540         }
6541 }
6542
6543 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6544 {
6545         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6546
6547         if (m_n == M1_N1) {
6548                 dp_m_n = &crtc->config->dp_m_n;
6549                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6550         } else if (m_n == M2_N2) {
6551
6552                 /*
6553                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6554                  * needs to be programmed into M1_N1.
6555                  */
6556                 dp_m_n = &crtc->config->dp_m2_n2;
6557         } else {
6558                 DRM_ERROR("Unsupported divider value\n");
6559                 return;
6560         }
6561
6562         if (crtc->config->has_pch_encoder)
6563                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6564         else
6565                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6566 }
6567
6568 static void vlv_compute_dpll(struct intel_crtc *crtc,
6569                              struct intel_crtc_state *pipe_config)
6570 {
6571         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6572                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6573         if (crtc->pipe != PIPE_A)
6574                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6575
6576         /* DPLL not used with DSI, but still need the rest set up */
6577         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6578                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6579                         DPLL_EXT_BUFFER_ENABLE_VLV;
6580
6581         pipe_config->dpll_hw_state.dpll_md =
6582                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6583 }
6584
6585 static void chv_compute_dpll(struct intel_crtc *crtc,
6586                              struct intel_crtc_state *pipe_config)
6587 {
6588         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6589                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6590         if (crtc->pipe != PIPE_A)
6591                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6592
6593         /* DPLL not used with DSI, but still need the rest set up */
6594         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6595                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6596
6597         pipe_config->dpll_hw_state.dpll_md =
6598                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6599 }
6600
6601 static void vlv_prepare_pll(struct intel_crtc *crtc,
6602                             const struct intel_crtc_state *pipe_config)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = to_i915(dev);
6606         enum pipe pipe = crtc->pipe;
6607         u32 mdiv;
6608         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6609         u32 coreclk, reg_val;
6610
6611         /* Enable Refclk */
6612         I915_WRITE(DPLL(pipe),
6613                    pipe_config->dpll_hw_state.dpll &
6614                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6615
6616         /* No need to actually set up the DPLL with DSI */
6617         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6618                 return;
6619
6620         mutex_lock(&dev_priv->sb_lock);
6621
6622         bestn = pipe_config->dpll.n;
6623         bestm1 = pipe_config->dpll.m1;
6624         bestm2 = pipe_config->dpll.m2;
6625         bestp1 = pipe_config->dpll.p1;
6626         bestp2 = pipe_config->dpll.p2;
6627
6628         /* See eDP HDMI DPIO driver vbios notes doc */
6629
6630         /* PLL B needs special handling */
6631         if (pipe == PIPE_B)
6632                 vlv_pllb_recal_opamp(dev_priv, pipe);
6633
6634         /* Set up Tx target for periodic Rcomp update */
6635         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6636
6637         /* Disable target IRef on PLL */
6638         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6639         reg_val &= 0x00ffffff;
6640         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6641
6642         /* Disable fast lock */
6643         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6644
6645         /* Set idtafcrecal before PLL is enabled */
6646         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6647         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6648         mdiv |= ((bestn << DPIO_N_SHIFT));
6649         mdiv |= (1 << DPIO_K_SHIFT);
6650
6651         /*
6652          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6653          * but we don't support that).
6654          * Note: don't use the DAC post divider as it seems unstable.
6655          */
6656         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6657         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6658
6659         mdiv |= DPIO_ENABLE_CALIBRATION;
6660         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6661
6662         /* Set HBR and RBR LPF coefficients */
6663         if (pipe_config->port_clock == 162000 ||
6664             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6665             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6666                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6667                                  0x009f0003);
6668         else
6669                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6670                                  0x00d0000f);
6671
6672         if (intel_crtc_has_dp_encoder(pipe_config)) {
6673                 /* Use SSC source */
6674                 if (pipe == PIPE_A)
6675                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6676                                          0x0df40000);
6677                 else
6678                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6679                                          0x0df70000);
6680         } else { /* HDMI or VGA */
6681                 /* Use bend source */
6682                 if (pipe == PIPE_A)
6683                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6684                                          0x0df70000);
6685                 else
6686                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6687                                          0x0df40000);
6688         }
6689
6690         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6691         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6692         if (intel_crtc_has_dp_encoder(crtc->config))
6693                 coreclk |= 0x01000000;
6694         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6695
6696         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6697         mutex_unlock(&dev_priv->sb_lock);
6698 }
6699
6700 static void chv_prepare_pll(struct intel_crtc *crtc,
6701                             const struct intel_crtc_state *pipe_config)
6702 {
6703         struct drm_device *dev = crtc->base.dev;
6704         struct drm_i915_private *dev_priv = to_i915(dev);
6705         enum pipe pipe = crtc->pipe;
6706         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6707         u32 loopfilter, tribuf_calcntr;
6708         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6709         u32 dpio_val;
6710         int vco;
6711
6712         /* Enable Refclk and SSC */
6713         I915_WRITE(DPLL(pipe),
6714                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6715
6716         /* No need to actually set up the DPLL with DSI */
6717         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6718                 return;
6719
6720         bestn = pipe_config->dpll.n;
6721         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6722         bestm1 = pipe_config->dpll.m1;
6723         bestm2 = pipe_config->dpll.m2 >> 22;
6724         bestp1 = pipe_config->dpll.p1;
6725         bestp2 = pipe_config->dpll.p2;
6726         vco = pipe_config->dpll.vco;
6727         dpio_val = 0;
6728         loopfilter = 0;
6729
6730         mutex_lock(&dev_priv->sb_lock);
6731
6732         /* p1 and p2 divider */
6733         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6734                         5 << DPIO_CHV_S1_DIV_SHIFT |
6735                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6736                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6737                         1 << DPIO_CHV_K_DIV_SHIFT);
6738
6739         /* Feedback post-divider - m2 */
6740         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6741
6742         /* Feedback refclk divider - n and m1 */
6743         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6744                         DPIO_CHV_M1_DIV_BY_2 |
6745                         1 << DPIO_CHV_N_DIV_SHIFT);
6746
6747         /* M2 fraction division */
6748         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6749
6750         /* M2 fraction division enable */
6751         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6752         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6753         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6754         if (bestm2_frac)
6755                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6756         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6757
6758         /* Program digital lock detect threshold */
6759         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6760         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6761                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6762         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6763         if (!bestm2_frac)
6764                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6765         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6766
6767         /* Loop filter */
6768         if (vco == 5400000) {
6769                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6770                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6771                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6772                 tribuf_calcntr = 0x9;
6773         } else if (vco <= 6200000) {
6774                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6775                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6776                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6777                 tribuf_calcntr = 0x9;
6778         } else if (vco <= 6480000) {
6779                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6780                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6781                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6782                 tribuf_calcntr = 0x8;
6783         } else {
6784                 /* Not supported. Apply the same limits as in the max case */
6785                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6786                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6787                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6788                 tribuf_calcntr = 0;
6789         }
6790         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6791
6792         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6793         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6794         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6795         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6796
6797         /* AFC Recal */
6798         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6799                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6800                         DPIO_AFC_RECAL);
6801
6802         mutex_unlock(&dev_priv->sb_lock);
6803 }
6804
6805 /**
6806  * vlv_force_pll_on - forcibly enable just the PLL
6807  * @dev_priv: i915 private structure
6808  * @pipe: pipe PLL to enable
6809  * @dpll: PLL configuration
6810  *
6811  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6812  * in cases where we need the PLL enabled even when @pipe is not going to
6813  * be enabled.
6814  */
6815 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6816                      const struct dpll *dpll)
6817 {
6818         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6819         struct intel_crtc_state *pipe_config;
6820
6821         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6822         if (!pipe_config)
6823                 return -ENOMEM;
6824
6825         pipe_config->base.crtc = &crtc->base;
6826         pipe_config->pixel_multiplier = 1;
6827         pipe_config->dpll = *dpll;
6828
6829         if (IS_CHERRYVIEW(dev_priv)) {
6830                 chv_compute_dpll(crtc, pipe_config);
6831                 chv_prepare_pll(crtc, pipe_config);
6832                 chv_enable_pll(crtc, pipe_config);
6833         } else {
6834                 vlv_compute_dpll(crtc, pipe_config);
6835                 vlv_prepare_pll(crtc, pipe_config);
6836                 vlv_enable_pll(crtc, pipe_config);
6837         }
6838
6839         kfree(pipe_config);
6840
6841         return 0;
6842 }
6843
6844 /**
6845  * vlv_force_pll_off - forcibly disable just the PLL
6846  * @dev_priv: i915 private structure
6847  * @pipe: pipe PLL to disable
6848  *
6849  * Disable the PLL for @pipe. To be used in cases where we need
6850  * the PLL enabled even when @pipe is not going to be enabled.
6851  */
6852 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6853 {
6854         if (IS_CHERRYVIEW(dev_priv))
6855                 chv_disable_pll(dev_priv, pipe);
6856         else
6857                 vlv_disable_pll(dev_priv, pipe);
6858 }
6859
6860 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6861                               struct intel_crtc_state *crtc_state,
6862                               struct dpll *reduced_clock)
6863 {
6864         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6865         u32 dpll;
6866         struct dpll *clock = &crtc_state->dpll;
6867
6868         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6869
6870         dpll = DPLL_VGA_MODE_DIS;
6871
6872         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6873                 dpll |= DPLLB_MODE_LVDS;
6874         else
6875                 dpll |= DPLLB_MODE_DAC_SERIAL;
6876
6877         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6878             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6879                 dpll |= (crtc_state->pixel_multiplier - 1)
6880                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6881         }
6882
6883         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6884             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6885                 dpll |= DPLL_SDVO_HIGH_SPEED;
6886
6887         if (intel_crtc_has_dp_encoder(crtc_state))
6888                 dpll |= DPLL_SDVO_HIGH_SPEED;
6889
6890         /* compute bitmask from p1 value */
6891         if (IS_PINEVIEW(dev_priv))
6892                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6893         else {
6894                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6895                 if (IS_G4X(dev_priv) && reduced_clock)
6896                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6897         }
6898         switch (clock->p2) {
6899         case 5:
6900                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6901                 break;
6902         case 7:
6903                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6904                 break;
6905         case 10:
6906                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6907                 break;
6908         case 14:
6909                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6910                 break;
6911         }
6912         if (INTEL_GEN(dev_priv) >= 4)
6913                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6914
6915         if (crtc_state->sdvo_tv_clock)
6916                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6917         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6918                  intel_panel_use_ssc(dev_priv))
6919                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6920         else
6921                 dpll |= PLL_REF_INPUT_DREFCLK;
6922
6923         dpll |= DPLL_VCO_ENABLE;
6924         crtc_state->dpll_hw_state.dpll = dpll;
6925
6926         if (INTEL_GEN(dev_priv) >= 4) {
6927                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6928                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6929                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6930         }
6931 }
6932
6933 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6934                               struct intel_crtc_state *crtc_state,
6935                               struct dpll *reduced_clock)
6936 {
6937         struct drm_device *dev = crtc->base.dev;
6938         struct drm_i915_private *dev_priv = to_i915(dev);
6939         u32 dpll;
6940         struct dpll *clock = &crtc_state->dpll;
6941
6942         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6943
6944         dpll = DPLL_VGA_MODE_DIS;
6945
6946         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6947                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6948         } else {
6949                 if (clock->p1 == 2)
6950                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6951                 else
6952                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6953                 if (clock->p2 == 4)
6954                         dpll |= PLL_P2_DIVIDE_BY_4;
6955         }
6956
6957         if (!IS_I830(dev_priv) &&
6958             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6959                 dpll |= DPLL_DVO_2X_MODE;
6960
6961         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6962             intel_panel_use_ssc(dev_priv))
6963                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6964         else
6965                 dpll |= PLL_REF_INPUT_DREFCLK;
6966
6967         dpll |= DPLL_VCO_ENABLE;
6968         crtc_state->dpll_hw_state.dpll = dpll;
6969 }
6970
6971 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6972 {
6973         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6974         enum pipe pipe = intel_crtc->pipe;
6975         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6976         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6977         uint32_t crtc_vtotal, crtc_vblank_end;
6978         int vsyncshift = 0;
6979
6980         /* We need to be careful not to changed the adjusted mode, for otherwise
6981          * the hw state checker will get angry at the mismatch. */
6982         crtc_vtotal = adjusted_mode->crtc_vtotal;
6983         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6984
6985         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6986                 /* the chip adds 2 halflines automatically */
6987                 crtc_vtotal -= 1;
6988                 crtc_vblank_end -= 1;
6989
6990                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6991                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6992                 else
6993                         vsyncshift = adjusted_mode->crtc_hsync_start -
6994                                 adjusted_mode->crtc_htotal / 2;
6995                 if (vsyncshift < 0)
6996                         vsyncshift += adjusted_mode->crtc_htotal;
6997         }
6998
6999         if (INTEL_GEN(dev_priv) > 3)
7000                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7001
7002         I915_WRITE(HTOTAL(cpu_transcoder),
7003                    (adjusted_mode->crtc_hdisplay - 1) |
7004                    ((adjusted_mode->crtc_htotal - 1) << 16));
7005         I915_WRITE(HBLANK(cpu_transcoder),
7006                    (adjusted_mode->crtc_hblank_start - 1) |
7007                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7008         I915_WRITE(HSYNC(cpu_transcoder),
7009                    (adjusted_mode->crtc_hsync_start - 1) |
7010                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7011
7012         I915_WRITE(VTOTAL(cpu_transcoder),
7013                    (adjusted_mode->crtc_vdisplay - 1) |
7014                    ((crtc_vtotal - 1) << 16));
7015         I915_WRITE(VBLANK(cpu_transcoder),
7016                    (adjusted_mode->crtc_vblank_start - 1) |
7017                    ((crtc_vblank_end - 1) << 16));
7018         I915_WRITE(VSYNC(cpu_transcoder),
7019                    (adjusted_mode->crtc_vsync_start - 1) |
7020                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7021
7022         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7023          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7024          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7025          * bits. */
7026         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7027             (pipe == PIPE_B || pipe == PIPE_C))
7028                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7029
7030 }
7031
7032 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7033 {
7034         struct drm_device *dev = intel_crtc->base.dev;
7035         struct drm_i915_private *dev_priv = to_i915(dev);
7036         enum pipe pipe = intel_crtc->pipe;
7037
7038         /* pipesrc controls the size that is scaled from, which should
7039          * always be the user's requested size.
7040          */
7041         I915_WRITE(PIPESRC(pipe),
7042                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7043                    (intel_crtc->config->pipe_src_h - 1));
7044 }
7045
7046 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7047                                    struct intel_crtc_state *pipe_config)
7048 {
7049         struct drm_device *dev = crtc->base.dev;
7050         struct drm_i915_private *dev_priv = to_i915(dev);
7051         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7052         uint32_t tmp;
7053
7054         tmp = I915_READ(HTOTAL(cpu_transcoder));
7055         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7056         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7057         tmp = I915_READ(HBLANK(cpu_transcoder));
7058         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7059         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7060         tmp = I915_READ(HSYNC(cpu_transcoder));
7061         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7062         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7063
7064         tmp = I915_READ(VTOTAL(cpu_transcoder));
7065         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7066         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7067         tmp = I915_READ(VBLANK(cpu_transcoder));
7068         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7069         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7070         tmp = I915_READ(VSYNC(cpu_transcoder));
7071         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7072         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7073
7074         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7075                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7076                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7077                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7078         }
7079 }
7080
7081 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7082                                     struct intel_crtc_state *pipe_config)
7083 {
7084         struct drm_device *dev = crtc->base.dev;
7085         struct drm_i915_private *dev_priv = to_i915(dev);
7086         u32 tmp;
7087
7088         tmp = I915_READ(PIPESRC(crtc->pipe));
7089         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7090         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7091
7092         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7093         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7094 }
7095
7096 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7097                                  struct intel_crtc_state *pipe_config)
7098 {
7099         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7100         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7101         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7102         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7103
7104         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7105         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7106         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7107         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7108
7109         mode->flags = pipe_config->base.adjusted_mode.flags;
7110         mode->type = DRM_MODE_TYPE_DRIVER;
7111
7112         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7113
7114         mode->hsync = drm_mode_hsync(mode);
7115         mode->vrefresh = drm_mode_vrefresh(mode);
7116         drm_mode_set_name(mode);
7117 }
7118
7119 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7120 {
7121         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7122         uint32_t pipeconf;
7123
7124         pipeconf = 0;
7125
7126         /* we keep both pipes enabled on 830 */
7127         if (IS_I830(dev_priv))
7128                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7129
7130         if (intel_crtc->config->double_wide)
7131                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7132
7133         /* only g4x and later have fancy bpc/dither controls */
7134         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7135             IS_CHERRYVIEW(dev_priv)) {
7136                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7137                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7138                         pipeconf |= PIPECONF_DITHER_EN |
7139                                     PIPECONF_DITHER_TYPE_SP;
7140
7141                 switch (intel_crtc->config->pipe_bpp) {
7142                 case 18:
7143                         pipeconf |= PIPECONF_6BPC;
7144                         break;
7145                 case 24:
7146                         pipeconf |= PIPECONF_8BPC;
7147                         break;
7148                 case 30:
7149                         pipeconf |= PIPECONF_10BPC;
7150                         break;
7151                 default:
7152                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7153                         BUG();
7154                 }
7155         }
7156
7157         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7158                 if (INTEL_GEN(dev_priv) < 4 ||
7159                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7160                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7161                 else
7162                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7163         } else
7164                 pipeconf |= PIPECONF_PROGRESSIVE;
7165
7166         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7167              intel_crtc->config->limited_color_range)
7168                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7169
7170         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7171         POSTING_READ(PIPECONF(intel_crtc->pipe));
7172 }
7173
7174 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7175                                    struct intel_crtc_state *crtc_state)
7176 {
7177         struct drm_device *dev = crtc->base.dev;
7178         struct drm_i915_private *dev_priv = to_i915(dev);
7179         const struct intel_limit *limit;
7180         int refclk = 48000;
7181
7182         memset(&crtc_state->dpll_hw_state, 0,
7183                sizeof(crtc_state->dpll_hw_state));
7184
7185         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7186                 if (intel_panel_use_ssc(dev_priv)) {
7187                         refclk = dev_priv->vbt.lvds_ssc_freq;
7188                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7189                 }
7190
7191                 limit = &intel_limits_i8xx_lvds;
7192         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7193                 limit = &intel_limits_i8xx_dvo;
7194         } else {
7195                 limit = &intel_limits_i8xx_dac;
7196         }
7197
7198         if (!crtc_state->clock_set &&
7199             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7200                                  refclk, NULL, &crtc_state->dpll)) {
7201                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7202                 return -EINVAL;
7203         }
7204
7205         i8xx_compute_dpll(crtc, crtc_state, NULL);
7206
7207         return 0;
7208 }
7209
7210 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7211                                   struct intel_crtc_state *crtc_state)
7212 {
7213         struct drm_device *dev = crtc->base.dev;
7214         struct drm_i915_private *dev_priv = to_i915(dev);
7215         const struct intel_limit *limit;
7216         int refclk = 96000;
7217
7218         memset(&crtc_state->dpll_hw_state, 0,
7219                sizeof(crtc_state->dpll_hw_state));
7220
7221         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7222                 if (intel_panel_use_ssc(dev_priv)) {
7223                         refclk = dev_priv->vbt.lvds_ssc_freq;
7224                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7225                 }
7226
7227                 if (intel_is_dual_link_lvds(dev))
7228                         limit = &intel_limits_g4x_dual_channel_lvds;
7229                 else
7230                         limit = &intel_limits_g4x_single_channel_lvds;
7231         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7232                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7233                 limit = &intel_limits_g4x_hdmi;
7234         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7235                 limit = &intel_limits_g4x_sdvo;
7236         } else {
7237                 /* The option is for other outputs */
7238                 limit = &intel_limits_i9xx_sdvo;
7239         }
7240
7241         if (!crtc_state->clock_set &&
7242             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7243                                 refclk, NULL, &crtc_state->dpll)) {
7244                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7245                 return -EINVAL;
7246         }
7247
7248         i9xx_compute_dpll(crtc, crtc_state, NULL);
7249
7250         return 0;
7251 }
7252
7253 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7254                                   struct intel_crtc_state *crtc_state)
7255 {
7256         struct drm_device *dev = crtc->base.dev;
7257         struct drm_i915_private *dev_priv = to_i915(dev);
7258         const struct intel_limit *limit;
7259         int refclk = 96000;
7260
7261         memset(&crtc_state->dpll_hw_state, 0,
7262                sizeof(crtc_state->dpll_hw_state));
7263
7264         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7265                 if (intel_panel_use_ssc(dev_priv)) {
7266                         refclk = dev_priv->vbt.lvds_ssc_freq;
7267                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7268                 }
7269
7270                 limit = &intel_limits_pineview_lvds;
7271         } else {
7272                 limit = &intel_limits_pineview_sdvo;
7273         }
7274
7275         if (!crtc_state->clock_set &&
7276             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7277                                 refclk, NULL, &crtc_state->dpll)) {
7278                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7279                 return -EINVAL;
7280         }
7281
7282         i9xx_compute_dpll(crtc, crtc_state, NULL);
7283
7284         return 0;
7285 }
7286
7287 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7288                                    struct intel_crtc_state *crtc_state)
7289 {
7290         struct drm_device *dev = crtc->base.dev;
7291         struct drm_i915_private *dev_priv = to_i915(dev);
7292         const struct intel_limit *limit;
7293         int refclk = 96000;
7294
7295         memset(&crtc_state->dpll_hw_state, 0,
7296                sizeof(crtc_state->dpll_hw_state));
7297
7298         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7299                 if (intel_panel_use_ssc(dev_priv)) {
7300                         refclk = dev_priv->vbt.lvds_ssc_freq;
7301                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7302                 }
7303
7304                 limit = &intel_limits_i9xx_lvds;
7305         } else {
7306                 limit = &intel_limits_i9xx_sdvo;
7307         }
7308
7309         if (!crtc_state->clock_set &&
7310             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7311                                  refclk, NULL, &crtc_state->dpll)) {
7312                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7313                 return -EINVAL;
7314         }
7315
7316         i9xx_compute_dpll(crtc, crtc_state, NULL);
7317
7318         return 0;
7319 }
7320
7321 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7322                                   struct intel_crtc_state *crtc_state)
7323 {
7324         int refclk = 100000;
7325         const struct intel_limit *limit = &intel_limits_chv;
7326
7327         memset(&crtc_state->dpll_hw_state, 0,
7328                sizeof(crtc_state->dpll_hw_state));
7329
7330         if (!crtc_state->clock_set &&
7331             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7332                                 refclk, NULL, &crtc_state->dpll)) {
7333                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7334                 return -EINVAL;
7335         }
7336
7337         chv_compute_dpll(crtc, crtc_state);
7338
7339         return 0;
7340 }
7341
7342 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7343                                   struct intel_crtc_state *crtc_state)
7344 {
7345         int refclk = 100000;
7346         const struct intel_limit *limit = &intel_limits_vlv;
7347
7348         memset(&crtc_state->dpll_hw_state, 0,
7349                sizeof(crtc_state->dpll_hw_state));
7350
7351         if (!crtc_state->clock_set &&
7352             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7353                                 refclk, NULL, &crtc_state->dpll)) {
7354                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7355                 return -EINVAL;
7356         }
7357
7358         vlv_compute_dpll(crtc, crtc_state);
7359
7360         return 0;
7361 }
7362
7363 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7364                                  struct intel_crtc_state *pipe_config)
7365 {
7366         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7367         uint32_t tmp;
7368
7369         if (INTEL_GEN(dev_priv) <= 3 &&
7370             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7371                 return;
7372
7373         tmp = I915_READ(PFIT_CONTROL);
7374         if (!(tmp & PFIT_ENABLE))
7375                 return;
7376
7377         /* Check whether the pfit is attached to our pipe. */
7378         if (INTEL_GEN(dev_priv) < 4) {
7379                 if (crtc->pipe != PIPE_B)
7380                         return;
7381         } else {
7382                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7383                         return;
7384         }
7385
7386         pipe_config->gmch_pfit.control = tmp;
7387         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7388 }
7389
7390 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7391                                struct intel_crtc_state *pipe_config)
7392 {
7393         struct drm_device *dev = crtc->base.dev;
7394         struct drm_i915_private *dev_priv = to_i915(dev);
7395         int pipe = pipe_config->cpu_transcoder;
7396         struct dpll clock;
7397         u32 mdiv;
7398         int refclk = 100000;
7399
7400         /* In case of DSI, DPLL will not be used */
7401         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7402                 return;
7403
7404         mutex_lock(&dev_priv->sb_lock);
7405         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7406         mutex_unlock(&dev_priv->sb_lock);
7407
7408         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7409         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7410         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7411         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7412         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7413
7414         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7415 }
7416
7417 static void
7418 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7419                               struct intel_initial_plane_config *plane_config)
7420 {
7421         struct drm_device *dev = crtc->base.dev;
7422         struct drm_i915_private *dev_priv = to_i915(dev);
7423         u32 val, base, offset;
7424         int pipe = crtc->pipe, plane = crtc->plane;
7425         int fourcc, pixel_format;
7426         unsigned int aligned_height;
7427         struct drm_framebuffer *fb;
7428         struct intel_framebuffer *intel_fb;
7429
7430         val = I915_READ(DSPCNTR(plane));
7431         if (!(val & DISPLAY_PLANE_ENABLE))
7432                 return;
7433
7434         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7435         if (!intel_fb) {
7436                 DRM_DEBUG_KMS("failed to alloc fb\n");
7437                 return;
7438         }
7439
7440         fb = &intel_fb->base;
7441
7442         fb->dev = dev;
7443
7444         if (INTEL_GEN(dev_priv) >= 4) {
7445                 if (val & DISPPLANE_TILED) {
7446                         plane_config->tiling = I915_TILING_X;
7447                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7448                 }
7449         }
7450
7451         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7452         fourcc = i9xx_format_to_fourcc(pixel_format);
7453         fb->format = drm_format_info(fourcc);
7454
7455         if (INTEL_GEN(dev_priv) >= 4) {
7456                 if (plane_config->tiling)
7457                         offset = I915_READ(DSPTILEOFF(plane));
7458                 else
7459                         offset = I915_READ(DSPLINOFF(plane));
7460                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7461         } else {
7462                 base = I915_READ(DSPADDR(plane));
7463         }
7464         plane_config->base = base;
7465
7466         val = I915_READ(PIPESRC(pipe));
7467         fb->width = ((val >> 16) & 0xfff) + 1;
7468         fb->height = ((val >> 0) & 0xfff) + 1;
7469
7470         val = I915_READ(DSPSTRIDE(pipe));
7471         fb->pitches[0] = val & 0xffffffc0;
7472
7473         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7474
7475         plane_config->size = fb->pitches[0] * aligned_height;
7476
7477         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7478                       pipe_name(pipe), plane, fb->width, fb->height,
7479                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7480                       plane_config->size);
7481
7482         plane_config->fb = intel_fb;
7483 }
7484
7485 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7486                                struct intel_crtc_state *pipe_config)
7487 {
7488         struct drm_device *dev = crtc->base.dev;
7489         struct drm_i915_private *dev_priv = to_i915(dev);
7490         int pipe = pipe_config->cpu_transcoder;
7491         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7492         struct dpll clock;
7493         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7494         int refclk = 100000;
7495
7496         /* In case of DSI, DPLL will not be used */
7497         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7498                 return;
7499
7500         mutex_lock(&dev_priv->sb_lock);
7501         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7502         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7503         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7504         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7505         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7506         mutex_unlock(&dev_priv->sb_lock);
7507
7508         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7509         clock.m2 = (pll_dw0 & 0xff) << 22;
7510         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7511                 clock.m2 |= pll_dw2 & 0x3fffff;
7512         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7513         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7514         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7515
7516         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7517 }
7518
7519 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7520                                  struct intel_crtc_state *pipe_config)
7521 {
7522         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7523         enum intel_display_power_domain power_domain;
7524         uint32_t tmp;
7525         bool ret;
7526
7527         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7528         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7529                 return false;
7530
7531         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7532         pipe_config->shared_dpll = NULL;
7533
7534         ret = false;
7535
7536         tmp = I915_READ(PIPECONF(crtc->pipe));
7537         if (!(tmp & PIPECONF_ENABLE))
7538                 goto out;
7539
7540         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7541             IS_CHERRYVIEW(dev_priv)) {
7542                 switch (tmp & PIPECONF_BPC_MASK) {
7543                 case PIPECONF_6BPC:
7544                         pipe_config->pipe_bpp = 18;
7545                         break;
7546                 case PIPECONF_8BPC:
7547                         pipe_config->pipe_bpp = 24;
7548                         break;
7549                 case PIPECONF_10BPC:
7550                         pipe_config->pipe_bpp = 30;
7551                         break;
7552                 default:
7553                         break;
7554                 }
7555         }
7556
7557         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7558             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7559                 pipe_config->limited_color_range = true;
7560
7561         if (INTEL_GEN(dev_priv) < 4)
7562                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7563
7564         intel_get_pipe_timings(crtc, pipe_config);
7565         intel_get_pipe_src_size(crtc, pipe_config);
7566
7567         i9xx_get_pfit_config(crtc, pipe_config);
7568
7569         if (INTEL_GEN(dev_priv) >= 4) {
7570                 /* No way to read it out on pipes B and C */
7571                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7572                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7573                 else
7574                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7575                 pipe_config->pixel_multiplier =
7576                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7577                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7578                 pipe_config->dpll_hw_state.dpll_md = tmp;
7579         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7580                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7581                 tmp = I915_READ(DPLL(crtc->pipe));
7582                 pipe_config->pixel_multiplier =
7583                         ((tmp & SDVO_MULTIPLIER_MASK)
7584                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7585         } else {
7586                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7587                  * port and will be fixed up in the encoder->get_config
7588                  * function. */
7589                 pipe_config->pixel_multiplier = 1;
7590         }
7591         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7592         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7593                 /*
7594                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7595                  * on 830. Filter it out here so that we don't
7596                  * report errors due to that.
7597                  */
7598                 if (IS_I830(dev_priv))
7599                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7600
7601                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7602                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7603         } else {
7604                 /* Mask out read-only status bits. */
7605                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7606                                                      DPLL_PORTC_READY_MASK |
7607                                                      DPLL_PORTB_READY_MASK);
7608         }
7609
7610         if (IS_CHERRYVIEW(dev_priv))
7611                 chv_crtc_clock_get(crtc, pipe_config);
7612         else if (IS_VALLEYVIEW(dev_priv))
7613                 vlv_crtc_clock_get(crtc, pipe_config);
7614         else
7615                 i9xx_crtc_clock_get(crtc, pipe_config);
7616
7617         /*
7618          * Normally the dotclock is filled in by the encoder .get_config()
7619          * but in case the pipe is enabled w/o any ports we need a sane
7620          * default.
7621          */
7622         pipe_config->base.adjusted_mode.crtc_clock =
7623                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7624
7625         ret = true;
7626
7627 out:
7628         intel_display_power_put(dev_priv, power_domain);
7629
7630         return ret;
7631 }
7632
7633 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7634 {
7635         struct intel_encoder *encoder;
7636         int i;
7637         u32 val, final;
7638         bool has_lvds = false;
7639         bool has_cpu_edp = false;
7640         bool has_panel = false;
7641         bool has_ck505 = false;
7642         bool can_ssc = false;
7643         bool using_ssc_source = false;
7644
7645         /* We need to take the global config into account */
7646         for_each_intel_encoder(&dev_priv->drm, encoder) {
7647                 switch (encoder->type) {
7648                 case INTEL_OUTPUT_LVDS:
7649                         has_panel = true;
7650                         has_lvds = true;
7651                         break;
7652                 case INTEL_OUTPUT_EDP:
7653                         has_panel = true;
7654                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7655                                 has_cpu_edp = true;
7656                         break;
7657                 default:
7658                         break;
7659                 }
7660         }
7661
7662         if (HAS_PCH_IBX(dev_priv)) {
7663                 has_ck505 = dev_priv->vbt.display_clock_mode;
7664                 can_ssc = has_ck505;
7665         } else {
7666                 has_ck505 = false;
7667                 can_ssc = true;
7668         }
7669
7670         /* Check if any DPLLs are using the SSC source */
7671         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7672                 u32 temp = I915_READ(PCH_DPLL(i));
7673
7674                 if (!(temp & DPLL_VCO_ENABLE))
7675                         continue;
7676
7677                 if ((temp & PLL_REF_INPUT_MASK) ==
7678                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7679                         using_ssc_source = true;
7680                         break;
7681                 }
7682         }
7683
7684         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7685                       has_panel, has_lvds, has_ck505, using_ssc_source);
7686
7687         /* Ironlake: try to setup display ref clock before DPLL
7688          * enabling. This is only under driver's control after
7689          * PCH B stepping, previous chipset stepping should be
7690          * ignoring this setting.
7691          */
7692         val = I915_READ(PCH_DREF_CONTROL);
7693
7694         /* As we must carefully and slowly disable/enable each source in turn,
7695          * compute the final state we want first and check if we need to
7696          * make any changes at all.
7697          */
7698         final = val;
7699         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7700         if (has_ck505)
7701                 final |= DREF_NONSPREAD_CK505_ENABLE;
7702         else
7703                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7704
7705         final &= ~DREF_SSC_SOURCE_MASK;
7706         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7707         final &= ~DREF_SSC1_ENABLE;
7708
7709         if (has_panel) {
7710                 final |= DREF_SSC_SOURCE_ENABLE;
7711
7712                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7713                         final |= DREF_SSC1_ENABLE;
7714
7715                 if (has_cpu_edp) {
7716                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7717                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7718                         else
7719                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7720                 } else
7721                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7722         } else if (using_ssc_source) {
7723                 final |= DREF_SSC_SOURCE_ENABLE;
7724                 final |= DREF_SSC1_ENABLE;
7725         }
7726
7727         if (final == val)
7728                 return;
7729
7730         /* Always enable nonspread source */
7731         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7732
7733         if (has_ck505)
7734                 val |= DREF_NONSPREAD_CK505_ENABLE;
7735         else
7736                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7737
7738         if (has_panel) {
7739                 val &= ~DREF_SSC_SOURCE_MASK;
7740                 val |= DREF_SSC_SOURCE_ENABLE;
7741
7742                 /* SSC must be turned on before enabling the CPU output  */
7743                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7744                         DRM_DEBUG_KMS("Using SSC on panel\n");
7745                         val |= DREF_SSC1_ENABLE;
7746                 } else
7747                         val &= ~DREF_SSC1_ENABLE;
7748
7749                 /* Get SSC going before enabling the outputs */
7750                 I915_WRITE(PCH_DREF_CONTROL, val);
7751                 POSTING_READ(PCH_DREF_CONTROL);
7752                 udelay(200);
7753
7754                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7755
7756                 /* Enable CPU source on CPU attached eDP */
7757                 if (has_cpu_edp) {
7758                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7759                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7760                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7761                         } else
7762                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7763                 } else
7764                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7765
7766                 I915_WRITE(PCH_DREF_CONTROL, val);
7767                 POSTING_READ(PCH_DREF_CONTROL);
7768                 udelay(200);
7769         } else {
7770                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7771
7772                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7773
7774                 /* Turn off CPU output */
7775                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7776
7777                 I915_WRITE(PCH_DREF_CONTROL, val);
7778                 POSTING_READ(PCH_DREF_CONTROL);
7779                 udelay(200);
7780
7781                 if (!using_ssc_source) {
7782                         DRM_DEBUG_KMS("Disabling SSC source\n");
7783
7784                         /* Turn off the SSC source */
7785                         val &= ~DREF_SSC_SOURCE_MASK;
7786                         val |= DREF_SSC_SOURCE_DISABLE;
7787
7788                         /* Turn off SSC1 */
7789                         val &= ~DREF_SSC1_ENABLE;
7790
7791                         I915_WRITE(PCH_DREF_CONTROL, val);
7792                         POSTING_READ(PCH_DREF_CONTROL);
7793                         udelay(200);
7794                 }
7795         }
7796
7797         BUG_ON(val != final);
7798 }
7799
7800 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7801 {
7802         uint32_t tmp;
7803
7804         tmp = I915_READ(SOUTH_CHICKEN2);
7805         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7806         I915_WRITE(SOUTH_CHICKEN2, tmp);
7807
7808         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7809                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7810                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7811
7812         tmp = I915_READ(SOUTH_CHICKEN2);
7813         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7814         I915_WRITE(SOUTH_CHICKEN2, tmp);
7815
7816         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7817                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7818                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7819 }
7820
7821 /* WaMPhyProgramming:hsw */
7822 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7823 {
7824         uint32_t tmp;
7825
7826         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7827         tmp &= ~(0xFF << 24);
7828         tmp |= (0x12 << 24);
7829         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7830
7831         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7832         tmp |= (1 << 11);
7833         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7834
7835         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7836         tmp |= (1 << 11);
7837         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7838
7839         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7840         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7841         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7842
7843         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7844         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7845         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7846
7847         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7848         tmp &= ~(7 << 13);
7849         tmp |= (5 << 13);
7850         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7851
7852         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7853         tmp &= ~(7 << 13);
7854         tmp |= (5 << 13);
7855         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7856
7857         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7858         tmp &= ~0xFF;
7859         tmp |= 0x1C;
7860         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7861
7862         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7863         tmp &= ~0xFF;
7864         tmp |= 0x1C;
7865         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7866
7867         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7868         tmp &= ~(0xFF << 16);
7869         tmp |= (0x1C << 16);
7870         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7871
7872         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7873         tmp &= ~(0xFF << 16);
7874         tmp |= (0x1C << 16);
7875         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7876
7877         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7878         tmp |= (1 << 27);
7879         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7880
7881         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7882         tmp |= (1 << 27);
7883         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7884
7885         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7886         tmp &= ~(0xF << 28);
7887         tmp |= (4 << 28);
7888         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7889
7890         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7891         tmp &= ~(0xF << 28);
7892         tmp |= (4 << 28);
7893         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7894 }
7895
7896 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7897  * Programming" based on the parameters passed:
7898  * - Sequence to enable CLKOUT_DP
7899  * - Sequence to enable CLKOUT_DP without spread
7900  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7901  */
7902 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7903                                  bool with_spread, bool with_fdi)
7904 {
7905         uint32_t reg, tmp;
7906
7907         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7908                 with_spread = true;
7909         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7910             with_fdi, "LP PCH doesn't have FDI\n"))
7911                 with_fdi = false;
7912
7913         mutex_lock(&dev_priv->sb_lock);
7914
7915         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7916         tmp &= ~SBI_SSCCTL_DISABLE;
7917         tmp |= SBI_SSCCTL_PATHALT;
7918         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7919
7920         udelay(24);
7921
7922         if (with_spread) {
7923                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7924                 tmp &= ~SBI_SSCCTL_PATHALT;
7925                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7926
7927                 if (with_fdi) {
7928                         lpt_reset_fdi_mphy(dev_priv);
7929                         lpt_program_fdi_mphy(dev_priv);
7930                 }
7931         }
7932
7933         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7934         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7935         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7936         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7937
7938         mutex_unlock(&dev_priv->sb_lock);
7939 }
7940
7941 /* Sequence to disable CLKOUT_DP */
7942 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7943 {
7944         uint32_t reg, tmp;
7945
7946         mutex_lock(&dev_priv->sb_lock);
7947
7948         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7949         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7950         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7951         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7952
7953         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7954         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7955                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7956                         tmp |= SBI_SSCCTL_PATHALT;
7957                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7958                         udelay(32);
7959                 }
7960                 tmp |= SBI_SSCCTL_DISABLE;
7961                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7962         }
7963
7964         mutex_unlock(&dev_priv->sb_lock);
7965 }
7966
7967 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7968
7969 static const uint16_t sscdivintphase[] = {
7970         [BEND_IDX( 50)] = 0x3B23,
7971         [BEND_IDX( 45)] = 0x3B23,
7972         [BEND_IDX( 40)] = 0x3C23,
7973         [BEND_IDX( 35)] = 0x3C23,
7974         [BEND_IDX( 30)] = 0x3D23,
7975         [BEND_IDX( 25)] = 0x3D23,
7976         [BEND_IDX( 20)] = 0x3E23,
7977         [BEND_IDX( 15)] = 0x3E23,
7978         [BEND_IDX( 10)] = 0x3F23,
7979         [BEND_IDX(  5)] = 0x3F23,
7980         [BEND_IDX(  0)] = 0x0025,
7981         [BEND_IDX( -5)] = 0x0025,
7982         [BEND_IDX(-10)] = 0x0125,
7983         [BEND_IDX(-15)] = 0x0125,
7984         [BEND_IDX(-20)] = 0x0225,
7985         [BEND_IDX(-25)] = 0x0225,
7986         [BEND_IDX(-30)] = 0x0325,
7987         [BEND_IDX(-35)] = 0x0325,
7988         [BEND_IDX(-40)] = 0x0425,
7989         [BEND_IDX(-45)] = 0x0425,
7990         [BEND_IDX(-50)] = 0x0525,
7991 };
7992
7993 /*
7994  * Bend CLKOUT_DP
7995  * steps -50 to 50 inclusive, in steps of 5
7996  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7997  * change in clock period = -(steps / 10) * 5.787 ps
7998  */
7999 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8000 {
8001         uint32_t tmp;
8002         int idx = BEND_IDX(steps);
8003
8004         if (WARN_ON(steps % 5 != 0))
8005                 return;
8006
8007         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8008                 return;
8009
8010         mutex_lock(&dev_priv->sb_lock);
8011
8012         if (steps % 10 != 0)
8013                 tmp = 0xAAAAAAAB;
8014         else
8015                 tmp = 0x00000000;
8016         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8017
8018         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8019         tmp &= 0xffff0000;
8020         tmp |= sscdivintphase[idx];
8021         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8022
8023         mutex_unlock(&dev_priv->sb_lock);
8024 }
8025
8026 #undef BEND_IDX
8027
8028 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8029 {
8030         struct intel_encoder *encoder;
8031         bool has_vga = false;
8032
8033         for_each_intel_encoder(&dev_priv->drm, encoder) {
8034                 switch (encoder->type) {
8035                 case INTEL_OUTPUT_ANALOG:
8036                         has_vga = true;
8037                         break;
8038                 default:
8039                         break;
8040                 }
8041         }
8042
8043         if (has_vga) {
8044                 lpt_bend_clkout_dp(dev_priv, 0);
8045                 lpt_enable_clkout_dp(dev_priv, true, true);
8046         } else {
8047                 lpt_disable_clkout_dp(dev_priv);
8048         }
8049 }
8050
8051 /*
8052  * Initialize reference clocks when the driver loads
8053  */
8054 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8055 {
8056         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8057                 ironlake_init_pch_refclk(dev_priv);
8058         else if (HAS_PCH_LPT(dev_priv))
8059                 lpt_init_pch_refclk(dev_priv);
8060 }
8061
8062 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8063 {
8064         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8066         int pipe = intel_crtc->pipe;
8067         uint32_t val;
8068
8069         val = 0;
8070
8071         switch (intel_crtc->config->pipe_bpp) {
8072         case 18:
8073                 val |= PIPECONF_6BPC;
8074                 break;
8075         case 24:
8076                 val |= PIPECONF_8BPC;
8077                 break;
8078         case 30:
8079                 val |= PIPECONF_10BPC;
8080                 break;
8081         case 36:
8082                 val |= PIPECONF_12BPC;
8083                 break;
8084         default:
8085                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8086                 BUG();
8087         }
8088
8089         if (intel_crtc->config->dither)
8090                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8091
8092         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8093                 val |= PIPECONF_INTERLACED_ILK;
8094         else
8095                 val |= PIPECONF_PROGRESSIVE;
8096
8097         if (intel_crtc->config->limited_color_range)
8098                 val |= PIPECONF_COLOR_RANGE_SELECT;
8099
8100         I915_WRITE(PIPECONF(pipe), val);
8101         POSTING_READ(PIPECONF(pipe));
8102 }
8103
8104 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8105 {
8106         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8108         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8109         u32 val = 0;
8110
8111         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8112                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8113
8114         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8115                 val |= PIPECONF_INTERLACED_ILK;
8116         else
8117                 val |= PIPECONF_PROGRESSIVE;
8118
8119         I915_WRITE(PIPECONF(cpu_transcoder), val);
8120         POSTING_READ(PIPECONF(cpu_transcoder));
8121 }
8122
8123 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8124 {
8125         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8127         struct intel_crtc_state *config = intel_crtc->config;
8128
8129         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8130                 u32 val = 0;
8131
8132                 switch (intel_crtc->config->pipe_bpp) {
8133                 case 18:
8134                         val |= PIPEMISC_DITHER_6_BPC;
8135                         break;
8136                 case 24:
8137                         val |= PIPEMISC_DITHER_8_BPC;
8138                         break;
8139                 case 30:
8140                         val |= PIPEMISC_DITHER_10_BPC;
8141                         break;
8142                 case 36:
8143                         val |= PIPEMISC_DITHER_12_BPC;
8144                         break;
8145                 default:
8146                         /* Case prevented by pipe_config_set_bpp. */
8147                         BUG();
8148                 }
8149
8150                 if (intel_crtc->config->dither)
8151                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8152
8153                 if (config->ycbcr420) {
8154                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8155                                 PIPEMISC_YUV420_ENABLE |
8156                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8157                 }
8158
8159                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8160         }
8161 }
8162
8163 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8164 {
8165         /*
8166          * Account for spread spectrum to avoid
8167          * oversubscribing the link. Max center spread
8168          * is 2.5%; use 5% for safety's sake.
8169          */
8170         u32 bps = target_clock * bpp * 21 / 20;
8171         return DIV_ROUND_UP(bps, link_bw * 8);
8172 }
8173
8174 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8175 {
8176         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8177 }
8178
8179 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8180                                   struct intel_crtc_state *crtc_state,
8181                                   struct dpll *reduced_clock)
8182 {
8183         struct drm_crtc *crtc = &intel_crtc->base;
8184         struct drm_device *dev = crtc->dev;
8185         struct drm_i915_private *dev_priv = to_i915(dev);
8186         u32 dpll, fp, fp2;
8187         int factor;
8188
8189         /* Enable autotuning of the PLL clock (if permissible) */
8190         factor = 21;
8191         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8192                 if ((intel_panel_use_ssc(dev_priv) &&
8193                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8194                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8195                         factor = 25;
8196         } else if (crtc_state->sdvo_tv_clock)
8197                 factor = 20;
8198
8199         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8200
8201         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8202                 fp |= FP_CB_TUNE;
8203
8204         if (reduced_clock) {
8205                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8206
8207                 if (reduced_clock->m < factor * reduced_clock->n)
8208                         fp2 |= FP_CB_TUNE;
8209         } else {
8210                 fp2 = fp;
8211         }
8212
8213         dpll = 0;
8214
8215         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8216                 dpll |= DPLLB_MODE_LVDS;
8217         else
8218                 dpll |= DPLLB_MODE_DAC_SERIAL;
8219
8220         dpll |= (crtc_state->pixel_multiplier - 1)
8221                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8222
8223         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8224             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8225                 dpll |= DPLL_SDVO_HIGH_SPEED;
8226
8227         if (intel_crtc_has_dp_encoder(crtc_state))
8228                 dpll |= DPLL_SDVO_HIGH_SPEED;
8229
8230         /*
8231          * The high speed IO clock is only really required for
8232          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8233          * possible to share the DPLL between CRT and HDMI. Enabling
8234          * the clock needlessly does no real harm, except use up a
8235          * bit of power potentially.
8236          *
8237          * We'll limit this to IVB with 3 pipes, since it has only two
8238          * DPLLs and so DPLL sharing is the only way to get three pipes
8239          * driving PCH ports at the same time. On SNB we could do this,
8240          * and potentially avoid enabling the second DPLL, but it's not
8241          * clear if it''s a win or loss power wise. No point in doing
8242          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8243          */
8244         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8245             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8246                 dpll |= DPLL_SDVO_HIGH_SPEED;
8247
8248         /* compute bitmask from p1 value */
8249         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8250         /* also FPA1 */
8251         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8252
8253         switch (crtc_state->dpll.p2) {
8254         case 5:
8255                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8256                 break;
8257         case 7:
8258                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8259                 break;
8260         case 10:
8261                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8262                 break;
8263         case 14:
8264                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8265                 break;
8266         }
8267
8268         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8269             intel_panel_use_ssc(dev_priv))
8270                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8271         else
8272                 dpll |= PLL_REF_INPUT_DREFCLK;
8273
8274         dpll |= DPLL_VCO_ENABLE;
8275
8276         crtc_state->dpll_hw_state.dpll = dpll;
8277         crtc_state->dpll_hw_state.fp0 = fp;
8278         crtc_state->dpll_hw_state.fp1 = fp2;
8279 }
8280
8281 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8282                                        struct intel_crtc_state *crtc_state)
8283 {
8284         struct drm_device *dev = crtc->base.dev;
8285         struct drm_i915_private *dev_priv = to_i915(dev);
8286         const struct intel_limit *limit;
8287         int refclk = 120000;
8288
8289         memset(&crtc_state->dpll_hw_state, 0,
8290                sizeof(crtc_state->dpll_hw_state));
8291
8292         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8293         if (!crtc_state->has_pch_encoder)
8294                 return 0;
8295
8296         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8297                 if (intel_panel_use_ssc(dev_priv)) {
8298                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8299                                       dev_priv->vbt.lvds_ssc_freq);
8300                         refclk = dev_priv->vbt.lvds_ssc_freq;
8301                 }
8302
8303                 if (intel_is_dual_link_lvds(dev)) {
8304                         if (refclk == 100000)
8305                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8306                         else
8307                                 limit = &intel_limits_ironlake_dual_lvds;
8308                 } else {
8309                         if (refclk == 100000)
8310                                 limit = &intel_limits_ironlake_single_lvds_100m;
8311                         else
8312                                 limit = &intel_limits_ironlake_single_lvds;
8313                 }
8314         } else {
8315                 limit = &intel_limits_ironlake_dac;
8316         }
8317
8318         if (!crtc_state->clock_set &&
8319             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8320                                 refclk, NULL, &crtc_state->dpll)) {
8321                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8322                 return -EINVAL;
8323         }
8324
8325         ironlake_compute_dpll(crtc, crtc_state, NULL);
8326
8327         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8328                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8329                                  pipe_name(crtc->pipe));
8330                 return -EINVAL;
8331         }
8332
8333         return 0;
8334 }
8335
8336 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8337                                          struct intel_link_m_n *m_n)
8338 {
8339         struct drm_device *dev = crtc->base.dev;
8340         struct drm_i915_private *dev_priv = to_i915(dev);
8341         enum pipe pipe = crtc->pipe;
8342
8343         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8344         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8345         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8346                 & ~TU_SIZE_MASK;
8347         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8348         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8349                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8350 }
8351
8352 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8353                                          enum transcoder transcoder,
8354                                          struct intel_link_m_n *m_n,
8355                                          struct intel_link_m_n *m2_n2)
8356 {
8357         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8358         enum pipe pipe = crtc->pipe;
8359
8360         if (INTEL_GEN(dev_priv) >= 5) {
8361                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8362                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8363                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8364                         & ~TU_SIZE_MASK;
8365                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8366                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8367                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8368                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8369                  * gen < 8) and if DRRS is supported (to make sure the
8370                  * registers are not unnecessarily read).
8371                  */
8372                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8373                         crtc->config->has_drrs) {
8374                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8375                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8376                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8377                                         & ~TU_SIZE_MASK;
8378                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8379                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8380                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8381                 }
8382         } else {
8383                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8384                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8385                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8386                         & ~TU_SIZE_MASK;
8387                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8388                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8389                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8390         }
8391 }
8392
8393 void intel_dp_get_m_n(struct intel_crtc *crtc,
8394                       struct intel_crtc_state *pipe_config)
8395 {
8396         if (pipe_config->has_pch_encoder)
8397                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8398         else
8399                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8400                                              &pipe_config->dp_m_n,
8401                                              &pipe_config->dp_m2_n2);
8402 }
8403
8404 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8405                                         struct intel_crtc_state *pipe_config)
8406 {
8407         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8408                                      &pipe_config->fdi_m_n, NULL);
8409 }
8410
8411 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8412                                     struct intel_crtc_state *pipe_config)
8413 {
8414         struct drm_device *dev = crtc->base.dev;
8415         struct drm_i915_private *dev_priv = to_i915(dev);
8416         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8417         uint32_t ps_ctrl = 0;
8418         int id = -1;
8419         int i;
8420
8421         /* find scaler attached to this pipe */
8422         for (i = 0; i < crtc->num_scalers; i++) {
8423                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8424                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8425                         id = i;
8426                         pipe_config->pch_pfit.enabled = true;
8427                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8428                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8429                         break;
8430                 }
8431         }
8432
8433         scaler_state->scaler_id = id;
8434         if (id >= 0) {
8435                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8436         } else {
8437                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8438         }
8439 }
8440
8441 static void
8442 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8443                                  struct intel_initial_plane_config *plane_config)
8444 {
8445         struct drm_device *dev = crtc->base.dev;
8446         struct drm_i915_private *dev_priv = to_i915(dev);
8447         u32 val, base, offset, stride_mult, tiling;
8448         int pipe = crtc->pipe;
8449         int fourcc, pixel_format;
8450         unsigned int aligned_height;
8451         struct drm_framebuffer *fb;
8452         struct intel_framebuffer *intel_fb;
8453
8454         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8455         if (!intel_fb) {
8456                 DRM_DEBUG_KMS("failed to alloc fb\n");
8457                 return;
8458         }
8459
8460         fb = &intel_fb->base;
8461
8462         fb->dev = dev;
8463
8464         val = I915_READ(PLANE_CTL(pipe, 0));
8465         if (!(val & PLANE_CTL_ENABLE))
8466                 goto error;
8467
8468         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8469         fourcc = skl_format_to_fourcc(pixel_format,
8470                                       val & PLANE_CTL_ORDER_RGBX,
8471                                       val & PLANE_CTL_ALPHA_MASK);
8472         fb->format = drm_format_info(fourcc);
8473
8474         tiling = val & PLANE_CTL_TILED_MASK;
8475         switch (tiling) {
8476         case PLANE_CTL_TILED_LINEAR:
8477                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8478                 break;
8479         case PLANE_CTL_TILED_X:
8480                 plane_config->tiling = I915_TILING_X;
8481                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8482                 break;
8483         case PLANE_CTL_TILED_Y:
8484                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8485                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8486                 else
8487                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8488                 break;
8489         case PLANE_CTL_TILED_YF:
8490                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8491                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8492                 else
8493                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8494                 break;
8495         default:
8496                 MISSING_CASE(tiling);
8497                 goto error;
8498         }
8499
8500         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8501         plane_config->base = base;
8502
8503         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8504
8505         val = I915_READ(PLANE_SIZE(pipe, 0));
8506         fb->height = ((val >> 16) & 0xfff) + 1;
8507         fb->width = ((val >> 0) & 0x1fff) + 1;
8508
8509         val = I915_READ(PLANE_STRIDE(pipe, 0));
8510         stride_mult = intel_fb_stride_alignment(fb, 0);
8511         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8512
8513         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8514
8515         plane_config->size = fb->pitches[0] * aligned_height;
8516
8517         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8518                       pipe_name(pipe), fb->width, fb->height,
8519                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8520                       plane_config->size);
8521
8522         plane_config->fb = intel_fb;
8523         return;
8524
8525 error:
8526         kfree(intel_fb);
8527 }
8528
8529 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8530                                      struct intel_crtc_state *pipe_config)
8531 {
8532         struct drm_device *dev = crtc->base.dev;
8533         struct drm_i915_private *dev_priv = to_i915(dev);
8534         uint32_t tmp;
8535
8536         tmp = I915_READ(PF_CTL(crtc->pipe));
8537
8538         if (tmp & PF_ENABLE) {
8539                 pipe_config->pch_pfit.enabled = true;
8540                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8541                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8542
8543                 /* We currently do not free assignements of panel fitters on
8544                  * ivb/hsw (since we don't use the higher upscaling modes which
8545                  * differentiates them) so just WARN about this case for now. */
8546                 if (IS_GEN7(dev_priv)) {
8547                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8548                                 PF_PIPE_SEL_IVB(crtc->pipe));
8549                 }
8550         }
8551 }
8552
8553 static void
8554 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8555                                   struct intel_initial_plane_config *plane_config)
8556 {
8557         struct drm_device *dev = crtc->base.dev;
8558         struct drm_i915_private *dev_priv = to_i915(dev);
8559         u32 val, base, offset;
8560         int pipe = crtc->pipe;
8561         int fourcc, pixel_format;
8562         unsigned int aligned_height;
8563         struct drm_framebuffer *fb;
8564         struct intel_framebuffer *intel_fb;
8565
8566         val = I915_READ(DSPCNTR(pipe));
8567         if (!(val & DISPLAY_PLANE_ENABLE))
8568                 return;
8569
8570         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8571         if (!intel_fb) {
8572                 DRM_DEBUG_KMS("failed to alloc fb\n");
8573                 return;
8574         }
8575
8576         fb = &intel_fb->base;
8577
8578         fb->dev = dev;
8579
8580         if (INTEL_GEN(dev_priv) >= 4) {
8581                 if (val & DISPPLANE_TILED) {
8582                         plane_config->tiling = I915_TILING_X;
8583                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8584                 }
8585         }
8586
8587         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8588         fourcc = i9xx_format_to_fourcc(pixel_format);
8589         fb->format = drm_format_info(fourcc);
8590
8591         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8592         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8593                 offset = I915_READ(DSPOFFSET(pipe));
8594         } else {
8595                 if (plane_config->tiling)
8596                         offset = I915_READ(DSPTILEOFF(pipe));
8597                 else
8598                         offset = I915_READ(DSPLINOFF(pipe));
8599         }
8600         plane_config->base = base;
8601
8602         val = I915_READ(PIPESRC(pipe));
8603         fb->width = ((val >> 16) & 0xfff) + 1;
8604         fb->height = ((val >> 0) & 0xfff) + 1;
8605
8606         val = I915_READ(DSPSTRIDE(pipe));
8607         fb->pitches[0] = val & 0xffffffc0;
8608
8609         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8610
8611         plane_config->size = fb->pitches[0] * aligned_height;
8612
8613         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8614                       pipe_name(pipe), fb->width, fb->height,
8615                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8616                       plane_config->size);
8617
8618         plane_config->fb = intel_fb;
8619 }
8620
8621 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8622                                      struct intel_crtc_state *pipe_config)
8623 {
8624         struct drm_device *dev = crtc->base.dev;
8625         struct drm_i915_private *dev_priv = to_i915(dev);
8626         enum intel_display_power_domain power_domain;
8627         uint32_t tmp;
8628         bool ret;
8629
8630         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8631         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8632                 return false;
8633
8634         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8635         pipe_config->shared_dpll = NULL;
8636
8637         ret = false;
8638         tmp = I915_READ(PIPECONF(crtc->pipe));
8639         if (!(tmp & PIPECONF_ENABLE))
8640                 goto out;
8641
8642         switch (tmp & PIPECONF_BPC_MASK) {
8643         case PIPECONF_6BPC:
8644                 pipe_config->pipe_bpp = 18;
8645                 break;
8646         case PIPECONF_8BPC:
8647                 pipe_config->pipe_bpp = 24;
8648                 break;
8649         case PIPECONF_10BPC:
8650                 pipe_config->pipe_bpp = 30;
8651                 break;
8652         case PIPECONF_12BPC:
8653                 pipe_config->pipe_bpp = 36;
8654                 break;
8655         default:
8656                 break;
8657         }
8658
8659         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8660                 pipe_config->limited_color_range = true;
8661
8662         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8663                 struct intel_shared_dpll *pll;
8664                 enum intel_dpll_id pll_id;
8665
8666                 pipe_config->has_pch_encoder = true;
8667
8668                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8669                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8670                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8671
8672                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8673
8674                 if (HAS_PCH_IBX(dev_priv)) {
8675                         /*
8676                          * The pipe->pch transcoder and pch transcoder->pll
8677                          * mapping is fixed.
8678                          */
8679                         pll_id = (enum intel_dpll_id) crtc->pipe;
8680                 } else {
8681                         tmp = I915_READ(PCH_DPLL_SEL);
8682                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8683                                 pll_id = DPLL_ID_PCH_PLL_B;
8684                         else
8685                                 pll_id= DPLL_ID_PCH_PLL_A;
8686                 }
8687
8688                 pipe_config->shared_dpll =
8689                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8690                 pll = pipe_config->shared_dpll;
8691
8692                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8693                                                  &pipe_config->dpll_hw_state));
8694
8695                 tmp = pipe_config->dpll_hw_state.dpll;
8696                 pipe_config->pixel_multiplier =
8697                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8698                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8699
8700                 ironlake_pch_clock_get(crtc, pipe_config);
8701         } else {
8702                 pipe_config->pixel_multiplier = 1;
8703         }
8704
8705         intel_get_pipe_timings(crtc, pipe_config);
8706         intel_get_pipe_src_size(crtc, pipe_config);
8707
8708         ironlake_get_pfit_config(crtc, pipe_config);
8709
8710         ret = true;
8711
8712 out:
8713         intel_display_power_put(dev_priv, power_domain);
8714
8715         return ret;
8716 }
8717
8718 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8719 {
8720         struct drm_device *dev = &dev_priv->drm;
8721         struct intel_crtc *crtc;
8722
8723         for_each_intel_crtc(dev, crtc)
8724                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8725                      pipe_name(crtc->pipe));
8726
8727         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8728                         "Display power well on\n");
8729         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8730         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8731         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8732         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8733         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8734              "CPU PWM1 enabled\n");
8735         if (IS_HASWELL(dev_priv))
8736                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8737                      "CPU PWM2 enabled\n");
8738         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8739              "PCH PWM1 enabled\n");
8740         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8741              "Utility pin enabled\n");
8742         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8743
8744         /*
8745          * In theory we can still leave IRQs enabled, as long as only the HPD
8746          * interrupts remain enabled. We used to check for that, but since it's
8747          * gen-specific and since we only disable LCPLL after we fully disable
8748          * the interrupts, the check below should be enough.
8749          */
8750         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8751 }
8752
8753 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8754 {
8755         if (IS_HASWELL(dev_priv))
8756                 return I915_READ(D_COMP_HSW);
8757         else
8758                 return I915_READ(D_COMP_BDW);
8759 }
8760
8761 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8762 {
8763         if (IS_HASWELL(dev_priv)) {
8764                 mutex_lock(&dev_priv->pcu_lock);
8765                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8766                                             val))
8767                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8768                 mutex_unlock(&dev_priv->pcu_lock);
8769         } else {
8770                 I915_WRITE(D_COMP_BDW, val);
8771                 POSTING_READ(D_COMP_BDW);
8772         }
8773 }
8774
8775 /*
8776  * This function implements pieces of two sequences from BSpec:
8777  * - Sequence for display software to disable LCPLL
8778  * - Sequence for display software to allow package C8+
8779  * The steps implemented here are just the steps that actually touch the LCPLL
8780  * register. Callers should take care of disabling all the display engine
8781  * functions, doing the mode unset, fixing interrupts, etc.
8782  */
8783 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8784                               bool switch_to_fclk, bool allow_power_down)
8785 {
8786         uint32_t val;
8787
8788         assert_can_disable_lcpll(dev_priv);
8789
8790         val = I915_READ(LCPLL_CTL);
8791
8792         if (switch_to_fclk) {
8793                 val |= LCPLL_CD_SOURCE_FCLK;
8794                 I915_WRITE(LCPLL_CTL, val);
8795
8796                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8797                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8798                         DRM_ERROR("Switching to FCLK failed\n");
8799
8800                 val = I915_READ(LCPLL_CTL);
8801         }
8802
8803         val |= LCPLL_PLL_DISABLE;
8804         I915_WRITE(LCPLL_CTL, val);
8805         POSTING_READ(LCPLL_CTL);
8806
8807         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8808                 DRM_ERROR("LCPLL still locked\n");
8809
8810         val = hsw_read_dcomp(dev_priv);
8811         val |= D_COMP_COMP_DISABLE;
8812         hsw_write_dcomp(dev_priv, val);
8813         ndelay(100);
8814
8815         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8816                      1))
8817                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8818
8819         if (allow_power_down) {
8820                 val = I915_READ(LCPLL_CTL);
8821                 val |= LCPLL_POWER_DOWN_ALLOW;
8822                 I915_WRITE(LCPLL_CTL, val);
8823                 POSTING_READ(LCPLL_CTL);
8824         }
8825 }
8826
8827 /*
8828  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8829  * source.
8830  */
8831 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8832 {
8833         uint32_t val;
8834
8835         val = I915_READ(LCPLL_CTL);
8836
8837         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8838                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8839                 return;
8840
8841         /*
8842          * Make sure we're not on PC8 state before disabling PC8, otherwise
8843          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8844          */
8845         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8846
8847         if (val & LCPLL_POWER_DOWN_ALLOW) {
8848                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8849                 I915_WRITE(LCPLL_CTL, val);
8850                 POSTING_READ(LCPLL_CTL);
8851         }
8852
8853         val = hsw_read_dcomp(dev_priv);
8854         val |= D_COMP_COMP_FORCE;
8855         val &= ~D_COMP_COMP_DISABLE;
8856         hsw_write_dcomp(dev_priv, val);
8857
8858         val = I915_READ(LCPLL_CTL);
8859         val &= ~LCPLL_PLL_DISABLE;
8860         I915_WRITE(LCPLL_CTL, val);
8861
8862         if (intel_wait_for_register(dev_priv,
8863                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8864                                     5))
8865                 DRM_ERROR("LCPLL not locked yet\n");
8866
8867         if (val & LCPLL_CD_SOURCE_FCLK) {
8868                 val = I915_READ(LCPLL_CTL);
8869                 val &= ~LCPLL_CD_SOURCE_FCLK;
8870                 I915_WRITE(LCPLL_CTL, val);
8871
8872                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8873                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8874                         DRM_ERROR("Switching back to LCPLL failed\n");
8875         }
8876
8877         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8878         intel_update_cdclk(dev_priv);
8879 }
8880
8881 /*
8882  * Package states C8 and deeper are really deep PC states that can only be
8883  * reached when all the devices on the system allow it, so even if the graphics
8884  * device allows PC8+, it doesn't mean the system will actually get to these
8885  * states. Our driver only allows PC8+ when going into runtime PM.
8886  *
8887  * The requirements for PC8+ are that all the outputs are disabled, the power
8888  * well is disabled and most interrupts are disabled, and these are also
8889  * requirements for runtime PM. When these conditions are met, we manually do
8890  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8891  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8892  * hang the machine.
8893  *
8894  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8895  * the state of some registers, so when we come back from PC8+ we need to
8896  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8897  * need to take care of the registers kept by RC6. Notice that this happens even
8898  * if we don't put the device in PCI D3 state (which is what currently happens
8899  * because of the runtime PM support).
8900  *
8901  * For more, read "Display Sequences for Package C8" on the hardware
8902  * documentation.
8903  */
8904 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8905 {
8906         uint32_t val;
8907
8908         DRM_DEBUG_KMS("Enabling package C8+\n");
8909
8910         if (HAS_PCH_LPT_LP(dev_priv)) {
8911                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8912                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8913                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8914         }
8915
8916         lpt_disable_clkout_dp(dev_priv);
8917         hsw_disable_lcpll(dev_priv, true, true);
8918 }
8919
8920 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8921 {
8922         uint32_t val;
8923
8924         DRM_DEBUG_KMS("Disabling package C8+\n");
8925
8926         hsw_restore_lcpll(dev_priv);
8927         lpt_init_pch_refclk(dev_priv);
8928
8929         if (HAS_PCH_LPT_LP(dev_priv)) {
8930                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8931                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8932                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8933         }
8934 }
8935
8936 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8937                                       struct intel_crtc_state *crtc_state)
8938 {
8939         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8940                 struct intel_encoder *encoder =
8941                         intel_ddi_get_crtc_new_encoder(crtc_state);
8942
8943                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8944                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8945                                          pipe_name(crtc->pipe));
8946                         return -EINVAL;
8947                 }
8948         }
8949
8950         return 0;
8951 }
8952
8953 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8954                                    enum port port,
8955                                    struct intel_crtc_state *pipe_config)
8956 {
8957         enum intel_dpll_id id;
8958         u32 temp;
8959
8960         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8961         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8962
8963         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8964                 return;
8965
8966         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8967 }
8968
8969 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8970                                 enum port port,
8971                                 struct intel_crtc_state *pipe_config)
8972 {
8973         enum intel_dpll_id id;
8974
8975         switch (port) {
8976         case PORT_A:
8977                 id = DPLL_ID_SKL_DPLL0;
8978                 break;
8979         case PORT_B:
8980                 id = DPLL_ID_SKL_DPLL1;
8981                 break;
8982         case PORT_C:
8983                 id = DPLL_ID_SKL_DPLL2;
8984                 break;
8985         default:
8986                 DRM_ERROR("Incorrect port type\n");
8987                 return;
8988         }
8989
8990         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8991 }
8992
8993 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8994                                 enum port port,
8995                                 struct intel_crtc_state *pipe_config)
8996 {
8997         enum intel_dpll_id id;
8998         u32 temp;
8999
9000         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9001         id = temp >> (port * 3 + 1);
9002
9003         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9004                 return;
9005
9006         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9007 }
9008
9009 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9010                                 enum port port,
9011                                 struct intel_crtc_state *pipe_config)
9012 {
9013         enum intel_dpll_id id;
9014         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9015
9016         switch (ddi_pll_sel) {
9017         case PORT_CLK_SEL_WRPLL1:
9018                 id = DPLL_ID_WRPLL1;
9019                 break;
9020         case PORT_CLK_SEL_WRPLL2:
9021                 id = DPLL_ID_WRPLL2;
9022                 break;
9023         case PORT_CLK_SEL_SPLL:
9024                 id = DPLL_ID_SPLL;
9025                 break;
9026         case PORT_CLK_SEL_LCPLL_810:
9027                 id = DPLL_ID_LCPLL_810;
9028                 break;
9029         case PORT_CLK_SEL_LCPLL_1350:
9030                 id = DPLL_ID_LCPLL_1350;
9031                 break;
9032         case PORT_CLK_SEL_LCPLL_2700:
9033                 id = DPLL_ID_LCPLL_2700;
9034                 break;
9035         default:
9036                 MISSING_CASE(ddi_pll_sel);
9037                 /* fall through */
9038         case PORT_CLK_SEL_NONE:
9039                 return;
9040         }
9041
9042         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9043 }
9044
9045 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9046                                      struct intel_crtc_state *pipe_config,
9047                                      u64 *power_domain_mask)
9048 {
9049         struct drm_device *dev = crtc->base.dev;
9050         struct drm_i915_private *dev_priv = to_i915(dev);
9051         enum intel_display_power_domain power_domain;
9052         u32 tmp;
9053
9054         /*
9055          * The pipe->transcoder mapping is fixed with the exception of the eDP
9056          * transcoder handled below.
9057          */
9058         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9059
9060         /*
9061          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9062          * consistency and less surprising code; it's in always on power).
9063          */
9064         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9065         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9066                 enum pipe trans_edp_pipe;
9067                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9068                 default:
9069                         WARN(1, "unknown pipe linked to edp transcoder\n");
9070                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9071                 case TRANS_DDI_EDP_INPUT_A_ON:
9072                         trans_edp_pipe = PIPE_A;
9073                         break;
9074                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9075                         trans_edp_pipe = PIPE_B;
9076                         break;
9077                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9078                         trans_edp_pipe = PIPE_C;
9079                         break;
9080                 }
9081
9082                 if (trans_edp_pipe == crtc->pipe)
9083                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9084         }
9085
9086         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9087         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9088                 return false;
9089         *power_domain_mask |= BIT_ULL(power_domain);
9090
9091         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9092
9093         return tmp & PIPECONF_ENABLE;
9094 }
9095
9096 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9097                                          struct intel_crtc_state *pipe_config,
9098                                          u64 *power_domain_mask)
9099 {
9100         struct drm_device *dev = crtc->base.dev;
9101         struct drm_i915_private *dev_priv = to_i915(dev);
9102         enum intel_display_power_domain power_domain;
9103         enum port port;
9104         enum transcoder cpu_transcoder;
9105         u32 tmp;
9106
9107         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9108                 if (port == PORT_A)
9109                         cpu_transcoder = TRANSCODER_DSI_A;
9110                 else
9111                         cpu_transcoder = TRANSCODER_DSI_C;
9112
9113                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9114                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9115                         continue;
9116                 *power_domain_mask |= BIT_ULL(power_domain);
9117
9118                 /*
9119                  * The PLL needs to be enabled with a valid divider
9120                  * configuration, otherwise accessing DSI registers will hang
9121                  * the machine. See BSpec North Display Engine
9122                  * registers/MIPI[BXT]. We can break out here early, since we
9123                  * need the same DSI PLL to be enabled for both DSI ports.
9124                  */
9125                 if (!intel_dsi_pll_is_enabled(dev_priv))
9126                         break;
9127
9128                 /* XXX: this works for video mode only */
9129                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9130                 if (!(tmp & DPI_ENABLE))
9131                         continue;
9132
9133                 tmp = I915_READ(MIPI_CTRL(port));
9134                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9135                         continue;
9136
9137                 pipe_config->cpu_transcoder = cpu_transcoder;
9138                 break;
9139         }
9140
9141         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9142 }
9143
9144 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9145                                        struct intel_crtc_state *pipe_config)
9146 {
9147         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9148         struct intel_shared_dpll *pll;
9149         enum port port;
9150         uint32_t tmp;
9151
9152         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9153
9154         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9155
9156         if (IS_CANNONLAKE(dev_priv))
9157                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9158         else if (IS_GEN9_BC(dev_priv))
9159                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9160         else if (IS_GEN9_LP(dev_priv))
9161                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9162         else
9163                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9164
9165         pll = pipe_config->shared_dpll;
9166         if (pll) {
9167                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9168                                                  &pipe_config->dpll_hw_state));
9169         }
9170
9171         /*
9172          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9173          * DDI E. So just check whether this pipe is wired to DDI E and whether
9174          * the PCH transcoder is on.
9175          */
9176         if (INTEL_GEN(dev_priv) < 9 &&
9177             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9178                 pipe_config->has_pch_encoder = true;
9179
9180                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9181                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9182                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9183
9184                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9185         }
9186 }
9187
9188 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9189                                     struct intel_crtc_state *pipe_config)
9190 {
9191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9192         enum intel_display_power_domain power_domain;
9193         u64 power_domain_mask;
9194         bool active;
9195
9196         intel_crtc_init_scalers(crtc, pipe_config);
9197
9198         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9199         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9200                 return false;
9201         power_domain_mask = BIT_ULL(power_domain);
9202
9203         pipe_config->shared_dpll = NULL;
9204
9205         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9206
9207         if (IS_GEN9_LP(dev_priv) &&
9208             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9209                 WARN_ON(active);
9210                 active = true;
9211         }
9212
9213         if (!active)
9214                 goto out;
9215
9216         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9217                 haswell_get_ddi_port_state(crtc, pipe_config);
9218                 intel_get_pipe_timings(crtc, pipe_config);
9219         }
9220
9221         intel_get_pipe_src_size(crtc, pipe_config);
9222
9223         pipe_config->gamma_mode =
9224                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9225
9226         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9227                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9228                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9229
9230                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9231                         bool blend_mode_420 = tmp &
9232                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9233
9234                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9235                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9236                             pipe_config->ycbcr420 != blend_mode_420)
9237                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9238                 } else if (clrspace_yuv) {
9239                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9240                 }
9241         }
9242
9243         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9244         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9245                 power_domain_mask |= BIT_ULL(power_domain);
9246                 if (INTEL_GEN(dev_priv) >= 9)
9247                         skylake_get_pfit_config(crtc, pipe_config);
9248                 else
9249                         ironlake_get_pfit_config(crtc, pipe_config);
9250         }
9251
9252         if (IS_HASWELL(dev_priv))
9253                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9254                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9255
9256         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9257             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9258                 pipe_config->pixel_multiplier =
9259                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9260         } else {
9261                 pipe_config->pixel_multiplier = 1;
9262         }
9263
9264 out:
9265         for_each_power_domain(power_domain, power_domain_mask)
9266                 intel_display_power_put(dev_priv, power_domain);
9267
9268         return active;
9269 }
9270
9271 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9272 {
9273         struct drm_i915_private *dev_priv =
9274                 to_i915(plane_state->base.plane->dev);
9275         const struct drm_framebuffer *fb = plane_state->base.fb;
9276         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9277         u32 base;
9278
9279         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9280                 base = obj->phys_handle->busaddr;
9281         else
9282                 base = intel_plane_ggtt_offset(plane_state);
9283
9284         base += plane_state->main.offset;
9285
9286         /* ILK+ do this automagically */
9287         if (HAS_GMCH_DISPLAY(dev_priv) &&
9288             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9289                 base += (plane_state->base.crtc_h *
9290                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9291
9292         return base;
9293 }
9294
9295 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9296 {
9297         int x = plane_state->base.crtc_x;
9298         int y = plane_state->base.crtc_y;
9299         u32 pos = 0;
9300
9301         if (x < 0) {
9302                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9303                 x = -x;
9304         }
9305         pos |= x << CURSOR_X_SHIFT;
9306
9307         if (y < 0) {
9308                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9309                 y = -y;
9310         }
9311         pos |= y << CURSOR_Y_SHIFT;
9312
9313         return pos;
9314 }
9315
9316 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9317 {
9318         const struct drm_mode_config *config =
9319                 &plane_state->base.plane->dev->mode_config;
9320         int width = plane_state->base.crtc_w;
9321         int height = plane_state->base.crtc_h;
9322
9323         return width > 0 && width <= config->cursor_width &&
9324                 height > 0 && height <= config->cursor_height;
9325 }
9326
9327 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9328                               struct intel_plane_state *plane_state)
9329 {
9330         const struct drm_framebuffer *fb = plane_state->base.fb;
9331         int src_x, src_y;
9332         u32 offset;
9333         int ret;
9334
9335         ret = drm_plane_helper_check_state(&plane_state->base,
9336                                            &plane_state->clip,
9337                                            DRM_PLANE_HELPER_NO_SCALING,
9338                                            DRM_PLANE_HELPER_NO_SCALING,
9339                                            true, true);
9340         if (ret)
9341                 return ret;
9342
9343         if (!fb)
9344                 return 0;
9345
9346         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9347                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9348                 return -EINVAL;
9349         }
9350
9351         src_x = plane_state->base.src_x >> 16;
9352         src_y = plane_state->base.src_y >> 16;
9353
9354         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9355         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9356
9357         if (src_x != 0 || src_y != 0) {
9358                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9359                 return -EINVAL;
9360         }
9361
9362         plane_state->main.offset = offset;
9363
9364         return 0;
9365 }
9366
9367 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9368                            const struct intel_plane_state *plane_state)
9369 {
9370         const struct drm_framebuffer *fb = plane_state->base.fb;
9371
9372         return CURSOR_ENABLE |
9373                 CURSOR_GAMMA_ENABLE |
9374                 CURSOR_FORMAT_ARGB |
9375                 CURSOR_STRIDE(fb->pitches[0]);
9376 }
9377
9378 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9379 {
9380         int width = plane_state->base.crtc_w;
9381
9382         /*
9383          * 845g/865g are only limited by the width of their cursors,
9384          * the height is arbitrary up to the precision of the register.
9385          */
9386         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9387 }
9388
9389 static int i845_check_cursor(struct intel_plane *plane,
9390                              struct intel_crtc_state *crtc_state,
9391                              struct intel_plane_state *plane_state)
9392 {
9393         const struct drm_framebuffer *fb = plane_state->base.fb;
9394         int ret;
9395
9396         ret = intel_check_cursor(crtc_state, plane_state);
9397         if (ret)
9398                 return ret;
9399
9400         /* if we want to turn off the cursor ignore width and height */
9401         if (!fb)
9402                 return 0;
9403
9404         /* Check for which cursor types we support */
9405         if (!i845_cursor_size_ok(plane_state)) {
9406                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9407                           plane_state->base.crtc_w,
9408                           plane_state->base.crtc_h);
9409                 return -EINVAL;
9410         }
9411
9412         switch (fb->pitches[0]) {
9413         case 256:
9414         case 512:
9415         case 1024:
9416         case 2048:
9417                 break;
9418         default:
9419                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9420                               fb->pitches[0]);
9421                 return -EINVAL;
9422         }
9423
9424         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9425
9426         return 0;
9427 }
9428
9429 static void i845_update_cursor(struct intel_plane *plane,
9430                                const struct intel_crtc_state *crtc_state,
9431                                const struct intel_plane_state *plane_state)
9432 {
9433         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9434         u32 cntl = 0, base = 0, pos = 0, size = 0;
9435         unsigned long irqflags;
9436
9437         if (plane_state && plane_state->base.visible) {
9438                 unsigned int width = plane_state->base.crtc_w;
9439                 unsigned int height = plane_state->base.crtc_h;
9440
9441                 cntl = plane_state->ctl;
9442                 size = (height << 12) | width;
9443
9444                 base = intel_cursor_base(plane_state);
9445                 pos = intel_cursor_position(plane_state);
9446         }
9447
9448         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9449
9450         /* On these chipsets we can only modify the base/size/stride
9451          * whilst the cursor is disabled.
9452          */
9453         if (plane->cursor.base != base ||
9454             plane->cursor.size != size ||
9455             plane->cursor.cntl != cntl) {
9456                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9457                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9458                 I915_WRITE_FW(CURSIZE, size);
9459                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9460                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9461
9462                 plane->cursor.base = base;
9463                 plane->cursor.size = size;
9464                 plane->cursor.cntl = cntl;
9465         } else {
9466                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9467         }
9468
9469         POSTING_READ_FW(CURCNTR(PIPE_A));
9470
9471         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9472 }
9473
9474 static void i845_disable_cursor(struct intel_plane *plane,
9475                                 struct intel_crtc *crtc)
9476 {
9477         i845_update_cursor(plane, NULL, NULL);
9478 }
9479
9480 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9481                            const struct intel_plane_state *plane_state)
9482 {
9483         struct drm_i915_private *dev_priv =
9484                 to_i915(plane_state->base.plane->dev);
9485         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9486         u32 cntl;
9487
9488         cntl = MCURSOR_GAMMA_ENABLE;
9489
9490         if (HAS_DDI(dev_priv))
9491                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9492
9493         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9494
9495         switch (plane_state->base.crtc_w) {
9496         case 64:
9497                 cntl |= CURSOR_MODE_64_ARGB_AX;
9498                 break;
9499         case 128:
9500                 cntl |= CURSOR_MODE_128_ARGB_AX;
9501                 break;
9502         case 256:
9503                 cntl |= CURSOR_MODE_256_ARGB_AX;
9504                 break;
9505         default:
9506                 MISSING_CASE(plane_state->base.crtc_w);
9507                 return 0;
9508         }
9509
9510         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9511                 cntl |= CURSOR_ROTATE_180;
9512
9513         return cntl;
9514 }
9515
9516 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9517 {
9518         struct drm_i915_private *dev_priv =
9519                 to_i915(plane_state->base.plane->dev);
9520         int width = plane_state->base.crtc_w;
9521         int height = plane_state->base.crtc_h;
9522
9523         if (!intel_cursor_size_ok(plane_state))
9524                 return false;
9525
9526         /* Cursor width is limited to a few power-of-two sizes */
9527         switch (width) {
9528         case 256:
9529         case 128:
9530         case 64:
9531                 break;
9532         default:
9533                 return false;
9534         }
9535
9536         /*
9537          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9538          * height from 8 lines up to the cursor width, when the
9539          * cursor is not rotated. Everything else requires square
9540          * cursors.
9541          */
9542         if (HAS_CUR_FBC(dev_priv) &&
9543             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9544                 if (height < 8 || height > width)
9545                         return false;
9546         } else {
9547                 if (height != width)
9548                         return false;
9549         }
9550
9551         return true;
9552 }
9553
9554 static int i9xx_check_cursor(struct intel_plane *plane,
9555                              struct intel_crtc_state *crtc_state,
9556                              struct intel_plane_state *plane_state)
9557 {
9558         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9559         const struct drm_framebuffer *fb = plane_state->base.fb;
9560         enum pipe pipe = plane->pipe;
9561         int ret;
9562
9563         ret = intel_check_cursor(crtc_state, plane_state);
9564         if (ret)
9565                 return ret;
9566
9567         /* if we want to turn off the cursor ignore width and height */
9568         if (!fb)
9569                 return 0;
9570
9571         /* Check for which cursor types we support */
9572         if (!i9xx_cursor_size_ok(plane_state)) {
9573                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9574                           plane_state->base.crtc_w,
9575                           plane_state->base.crtc_h);
9576                 return -EINVAL;
9577         }
9578
9579         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9580                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9581                               fb->pitches[0], plane_state->base.crtc_w);
9582                 return -EINVAL;
9583         }
9584
9585         /*
9586          * There's something wrong with the cursor on CHV pipe C.
9587          * If it straddles the left edge of the screen then
9588          * moving it away from the edge or disabling it often
9589          * results in a pipe underrun, and often that can lead to
9590          * dead pipe (constant underrun reported, and it scans
9591          * out just a solid color). To recover from that, the
9592          * display power well must be turned off and on again.
9593          * Refuse the put the cursor into that compromised position.
9594          */
9595         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9596             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9597                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9598                 return -EINVAL;
9599         }
9600
9601         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9602
9603         return 0;
9604 }
9605
9606 static void i9xx_update_cursor(struct intel_plane *plane,
9607                                const struct intel_crtc_state *crtc_state,
9608                                const struct intel_plane_state *plane_state)
9609 {
9610         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9611         enum pipe pipe = plane->pipe;
9612         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9613         unsigned long irqflags;
9614
9615         if (plane_state && plane_state->base.visible) {
9616                 cntl = plane_state->ctl;
9617
9618                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9619                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9620
9621                 base = intel_cursor_base(plane_state);
9622                 pos = intel_cursor_position(plane_state);
9623         }
9624
9625         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9626
9627         /*
9628          * On some platforms writing CURCNTR first will also
9629          * cause CURPOS to be armed by the CURBASE write.
9630          * Without the CURCNTR write the CURPOS write would
9631          * arm itself. Thus we always start the full update
9632          * with a CURCNTR write.
9633          *
9634          * On other platforms CURPOS always requires the
9635          * CURBASE write to arm the update. Additonally
9636          * a write to any of the cursor register will cancel
9637          * an already armed cursor update. Thus leaving out
9638          * the CURBASE write after CURPOS could lead to a
9639          * cursor that doesn't appear to move, or even change
9640          * shape. Thus we always write CURBASE.
9641          *
9642          * CURCNTR and CUR_FBC_CTL are always
9643          * armed by the CURBASE write only.
9644          */
9645         if (plane->cursor.base != base ||
9646             plane->cursor.size != fbc_ctl ||
9647             plane->cursor.cntl != cntl) {
9648                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9649                 if (HAS_CUR_FBC(dev_priv))
9650                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9651                 I915_WRITE_FW(CURPOS(pipe), pos);
9652                 I915_WRITE_FW(CURBASE(pipe), base);
9653
9654                 plane->cursor.base = base;
9655                 plane->cursor.size = fbc_ctl;
9656                 plane->cursor.cntl = cntl;
9657         } else {
9658                 I915_WRITE_FW(CURPOS(pipe), pos);
9659                 I915_WRITE_FW(CURBASE(pipe), base);
9660         }
9661
9662         POSTING_READ_FW(CURBASE(pipe));
9663
9664         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9665 }
9666
9667 static void i9xx_disable_cursor(struct intel_plane *plane,
9668                                 struct intel_crtc *crtc)
9669 {
9670         i9xx_update_cursor(plane, NULL, NULL);
9671 }
9672
9673
9674 /* VESA 640x480x72Hz mode to set on the pipe */
9675 static const struct drm_display_mode load_detect_mode = {
9676         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9677                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9678 };
9679
9680 struct drm_framebuffer *
9681 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9682                          struct drm_mode_fb_cmd2 *mode_cmd)
9683 {
9684         struct intel_framebuffer *intel_fb;
9685         int ret;
9686
9687         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9688         if (!intel_fb)
9689                 return ERR_PTR(-ENOMEM);
9690
9691         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9692         if (ret)
9693                 goto err;
9694
9695         return &intel_fb->base;
9696
9697 err:
9698         kfree(intel_fb);
9699         return ERR_PTR(ret);
9700 }
9701
9702 static u32
9703 intel_framebuffer_pitch_for_width(int width, int bpp)
9704 {
9705         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9706         return ALIGN(pitch, 64);
9707 }
9708
9709 static u32
9710 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9711 {
9712         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9713         return PAGE_ALIGN(pitch * mode->vdisplay);
9714 }
9715
9716 static struct drm_framebuffer *
9717 intel_framebuffer_create_for_mode(struct drm_device *dev,
9718                                   const struct drm_display_mode *mode,
9719                                   int depth, int bpp)
9720 {
9721         struct drm_framebuffer *fb;
9722         struct drm_i915_gem_object *obj;
9723         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9724
9725         obj = i915_gem_object_create(to_i915(dev),
9726                                     intel_framebuffer_size_for_mode(mode, bpp));
9727         if (IS_ERR(obj))
9728                 return ERR_CAST(obj);
9729
9730         mode_cmd.width = mode->hdisplay;
9731         mode_cmd.height = mode->vdisplay;
9732         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9733                                                                 bpp);
9734         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9735
9736         fb = intel_framebuffer_create(obj, &mode_cmd);
9737         if (IS_ERR(fb))
9738                 i915_gem_object_put(obj);
9739
9740         return fb;
9741 }
9742
9743 static struct drm_framebuffer *
9744 mode_fits_in_fbdev(struct drm_device *dev,
9745                    const struct drm_display_mode *mode)
9746 {
9747 #ifdef CONFIG_DRM_FBDEV_EMULATION
9748         struct drm_i915_private *dev_priv = to_i915(dev);
9749         struct drm_i915_gem_object *obj;
9750         struct drm_framebuffer *fb;
9751
9752         if (!dev_priv->fbdev)
9753                 return NULL;
9754
9755         if (!dev_priv->fbdev->fb)
9756                 return NULL;
9757
9758         obj = dev_priv->fbdev->fb->obj;
9759         BUG_ON(!obj);
9760
9761         fb = &dev_priv->fbdev->fb->base;
9762         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9763                                                                fb->format->cpp[0] * 8))
9764                 return NULL;
9765
9766         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9767                 return NULL;
9768
9769         drm_framebuffer_get(fb);
9770         return fb;
9771 #else
9772         return NULL;
9773 #endif
9774 }
9775
9776 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9777                                            struct drm_crtc *crtc,
9778                                            const struct drm_display_mode *mode,
9779                                            struct drm_framebuffer *fb,
9780                                            int x, int y)
9781 {
9782         struct drm_plane_state *plane_state;
9783         int hdisplay, vdisplay;
9784         int ret;
9785
9786         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9787         if (IS_ERR(plane_state))
9788                 return PTR_ERR(plane_state);
9789
9790         if (mode)
9791                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9792         else
9793                 hdisplay = vdisplay = 0;
9794
9795         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9796         if (ret)
9797                 return ret;
9798         drm_atomic_set_fb_for_plane(plane_state, fb);
9799         plane_state->crtc_x = 0;
9800         plane_state->crtc_y = 0;
9801         plane_state->crtc_w = hdisplay;
9802         plane_state->crtc_h = vdisplay;
9803         plane_state->src_x = x << 16;
9804         plane_state->src_y = y << 16;
9805         plane_state->src_w = hdisplay << 16;
9806         plane_state->src_h = vdisplay << 16;
9807
9808         return 0;
9809 }
9810
9811 int intel_get_load_detect_pipe(struct drm_connector *connector,
9812                                const struct drm_display_mode *mode,
9813                                struct intel_load_detect_pipe *old,
9814                                struct drm_modeset_acquire_ctx *ctx)
9815 {
9816         struct intel_crtc *intel_crtc;
9817         struct intel_encoder *intel_encoder =
9818                 intel_attached_encoder(connector);
9819         struct drm_crtc *possible_crtc;
9820         struct drm_encoder *encoder = &intel_encoder->base;
9821         struct drm_crtc *crtc = NULL;
9822         struct drm_device *dev = encoder->dev;
9823         struct drm_i915_private *dev_priv = to_i915(dev);
9824         struct drm_framebuffer *fb;
9825         struct drm_mode_config *config = &dev->mode_config;
9826         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9827         struct drm_connector_state *connector_state;
9828         struct intel_crtc_state *crtc_state;
9829         int ret, i = -1;
9830
9831         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9832                       connector->base.id, connector->name,
9833                       encoder->base.id, encoder->name);
9834
9835         old->restore_state = NULL;
9836
9837         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9838
9839         /*
9840          * Algorithm gets a little messy:
9841          *
9842          *   - if the connector already has an assigned crtc, use it (but make
9843          *     sure it's on first)
9844          *
9845          *   - try to find the first unused crtc that can drive this connector,
9846          *     and use that if we find one
9847          */
9848
9849         /* See if we already have a CRTC for this connector */
9850         if (connector->state->crtc) {
9851                 crtc = connector->state->crtc;
9852
9853                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9854                 if (ret)
9855                         goto fail;
9856
9857                 /* Make sure the crtc and connector are running */
9858                 goto found;
9859         }
9860
9861         /* Find an unused one (if possible) */
9862         for_each_crtc(dev, possible_crtc) {
9863                 i++;
9864                 if (!(encoder->possible_crtcs & (1 << i)))
9865                         continue;
9866
9867                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9868                 if (ret)
9869                         goto fail;
9870
9871                 if (possible_crtc->state->enable) {
9872                         drm_modeset_unlock(&possible_crtc->mutex);
9873                         continue;
9874                 }
9875
9876                 crtc = possible_crtc;
9877                 break;
9878         }
9879
9880         /*
9881          * If we didn't find an unused CRTC, don't use any.
9882          */
9883         if (!crtc) {
9884                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9885                 ret = -ENODEV;
9886                 goto fail;
9887         }
9888
9889 found:
9890         intel_crtc = to_intel_crtc(crtc);
9891
9892         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9893         if (ret)
9894                 goto fail;
9895
9896         state = drm_atomic_state_alloc(dev);
9897         restore_state = drm_atomic_state_alloc(dev);
9898         if (!state || !restore_state) {
9899                 ret = -ENOMEM;
9900                 goto fail;
9901         }
9902
9903         state->acquire_ctx = ctx;
9904         restore_state->acquire_ctx = ctx;
9905
9906         connector_state = drm_atomic_get_connector_state(state, connector);
9907         if (IS_ERR(connector_state)) {
9908                 ret = PTR_ERR(connector_state);
9909                 goto fail;
9910         }
9911
9912         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9913         if (ret)
9914                 goto fail;
9915
9916         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9917         if (IS_ERR(crtc_state)) {
9918                 ret = PTR_ERR(crtc_state);
9919                 goto fail;
9920         }
9921
9922         crtc_state->base.active = crtc_state->base.enable = true;
9923
9924         if (!mode)
9925                 mode = &load_detect_mode;
9926
9927         /* We need a framebuffer large enough to accommodate all accesses
9928          * that the plane may generate whilst we perform load detection.
9929          * We can not rely on the fbcon either being present (we get called
9930          * during its initialisation to detect all boot displays, or it may
9931          * not even exist) or that it is large enough to satisfy the
9932          * requested mode.
9933          */
9934         fb = mode_fits_in_fbdev(dev, mode);
9935         if (fb == NULL) {
9936                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9937                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9938         } else
9939                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9940         if (IS_ERR(fb)) {
9941                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9942                 ret = PTR_ERR(fb);
9943                 goto fail;
9944         }
9945
9946         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9947         drm_framebuffer_put(fb);
9948         if (ret)
9949                 goto fail;
9950
9951         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9952         if (ret)
9953                 goto fail;
9954
9955         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9956         if (!ret)
9957                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9958         if (!ret)
9959                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9960         if (ret) {
9961                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9962                 goto fail;
9963         }
9964
9965         ret = drm_atomic_commit(state);
9966         if (ret) {
9967                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9968                 goto fail;
9969         }
9970
9971         old->restore_state = restore_state;
9972         drm_atomic_state_put(state);
9973
9974         /* let the connector get through one full cycle before testing */
9975         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9976         return true;
9977
9978 fail:
9979         if (state) {
9980                 drm_atomic_state_put(state);
9981                 state = NULL;
9982         }
9983         if (restore_state) {
9984                 drm_atomic_state_put(restore_state);
9985                 restore_state = NULL;
9986         }
9987
9988         if (ret == -EDEADLK)
9989                 return ret;
9990
9991         return false;
9992 }
9993
9994 void intel_release_load_detect_pipe(struct drm_connector *connector,
9995                                     struct intel_load_detect_pipe *old,
9996                                     struct drm_modeset_acquire_ctx *ctx)
9997 {
9998         struct intel_encoder *intel_encoder =
9999                 intel_attached_encoder(connector);
10000         struct drm_encoder *encoder = &intel_encoder->base;
10001         struct drm_atomic_state *state = old->restore_state;
10002         int ret;
10003
10004         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10005                       connector->base.id, connector->name,
10006                       encoder->base.id, encoder->name);
10007
10008         if (!state)
10009                 return;
10010
10011         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10012         if (ret)
10013                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10014         drm_atomic_state_put(state);
10015 }
10016
10017 static int i9xx_pll_refclk(struct drm_device *dev,
10018                            const struct intel_crtc_state *pipe_config)
10019 {
10020         struct drm_i915_private *dev_priv = to_i915(dev);
10021         u32 dpll = pipe_config->dpll_hw_state.dpll;
10022
10023         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10024                 return dev_priv->vbt.lvds_ssc_freq;
10025         else if (HAS_PCH_SPLIT(dev_priv))
10026                 return 120000;
10027         else if (!IS_GEN2(dev_priv))
10028                 return 96000;
10029         else
10030                 return 48000;
10031 }
10032
10033 /* Returns the clock of the currently programmed mode of the given pipe. */
10034 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10035                                 struct intel_crtc_state *pipe_config)
10036 {
10037         struct drm_device *dev = crtc->base.dev;
10038         struct drm_i915_private *dev_priv = to_i915(dev);
10039         int pipe = pipe_config->cpu_transcoder;
10040         u32 dpll = pipe_config->dpll_hw_state.dpll;
10041         u32 fp;
10042         struct dpll clock;
10043         int port_clock;
10044         int refclk = i9xx_pll_refclk(dev, pipe_config);
10045
10046         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10047                 fp = pipe_config->dpll_hw_state.fp0;
10048         else
10049                 fp = pipe_config->dpll_hw_state.fp1;
10050
10051         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10052         if (IS_PINEVIEW(dev_priv)) {
10053                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10054                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10055         } else {
10056                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10057                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10058         }
10059
10060         if (!IS_GEN2(dev_priv)) {
10061                 if (IS_PINEVIEW(dev_priv))
10062                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10063                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10064                 else
10065                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10066                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10067
10068                 switch (dpll & DPLL_MODE_MASK) {
10069                 case DPLLB_MODE_DAC_SERIAL:
10070                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10071                                 5 : 10;
10072                         break;
10073                 case DPLLB_MODE_LVDS:
10074                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10075                                 7 : 14;
10076                         break;
10077                 default:
10078                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10079                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10080                         return;
10081                 }
10082
10083                 if (IS_PINEVIEW(dev_priv))
10084                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10085                 else
10086                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10087         } else {
10088                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10089                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10090
10091                 if (is_lvds) {
10092                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10093                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10094
10095                         if (lvds & LVDS_CLKB_POWER_UP)
10096                                 clock.p2 = 7;
10097                         else
10098                                 clock.p2 = 14;
10099                 } else {
10100                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10101                                 clock.p1 = 2;
10102                         else {
10103                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10104                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10105                         }
10106                         if (dpll & PLL_P2_DIVIDE_BY_4)
10107                                 clock.p2 = 4;
10108                         else
10109                                 clock.p2 = 2;
10110                 }
10111
10112                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10113         }
10114
10115         /*
10116          * This value includes pixel_multiplier. We will use
10117          * port_clock to compute adjusted_mode.crtc_clock in the
10118          * encoder's get_config() function.
10119          */
10120         pipe_config->port_clock = port_clock;
10121 }
10122
10123 int intel_dotclock_calculate(int link_freq,
10124                              const struct intel_link_m_n *m_n)
10125 {
10126         /*
10127          * The calculation for the data clock is:
10128          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10129          * But we want to avoid losing precison if possible, so:
10130          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10131          *
10132          * and the link clock is simpler:
10133          * link_clock = (m * link_clock) / n
10134          */
10135
10136         if (!m_n->link_n)
10137                 return 0;
10138
10139         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10140 }
10141
10142 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10143                                    struct intel_crtc_state *pipe_config)
10144 {
10145         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10146
10147         /* read out port_clock from the DPLL */
10148         i9xx_crtc_clock_get(crtc, pipe_config);
10149
10150         /*
10151          * In case there is an active pipe without active ports,
10152          * we may need some idea for the dotclock anyway.
10153          * Calculate one based on the FDI configuration.
10154          */
10155         pipe_config->base.adjusted_mode.crtc_clock =
10156                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10157                                          &pipe_config->fdi_m_n);
10158 }
10159
10160 /* Returns the currently programmed mode of the given encoder. */
10161 struct drm_display_mode *
10162 intel_encoder_current_mode(struct intel_encoder *encoder)
10163 {
10164         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10165         struct intel_crtc_state *crtc_state;
10166         struct drm_display_mode *mode;
10167         struct intel_crtc *crtc;
10168         enum pipe pipe;
10169
10170         if (!encoder->get_hw_state(encoder, &pipe))
10171                 return NULL;
10172
10173         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10174
10175         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10176         if (!mode)
10177                 return NULL;
10178
10179         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10180         if (!crtc_state) {
10181                 kfree(mode);
10182                 return NULL;
10183         }
10184
10185         crtc_state->base.crtc = &crtc->base;
10186
10187         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10188                 kfree(crtc_state);
10189                 kfree(mode);
10190                 return NULL;
10191         }
10192
10193         encoder->get_config(encoder, crtc_state);
10194
10195         intel_mode_from_pipe_config(mode, crtc_state);
10196
10197         kfree(crtc_state);
10198
10199         return mode;
10200 }
10201
10202 static void intel_crtc_destroy(struct drm_crtc *crtc)
10203 {
10204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10205
10206         drm_crtc_cleanup(crtc);
10207         kfree(intel_crtc);
10208 }
10209
10210 /**
10211  * intel_wm_need_update - Check whether watermarks need updating
10212  * @plane: drm plane
10213  * @state: new plane state
10214  *
10215  * Check current plane state versus the new one to determine whether
10216  * watermarks need to be recalculated.
10217  *
10218  * Returns true or false.
10219  */
10220 static bool intel_wm_need_update(struct drm_plane *plane,
10221                                  struct drm_plane_state *state)
10222 {
10223         struct intel_plane_state *new = to_intel_plane_state(state);
10224         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10225
10226         /* Update watermarks on tiling or size changes. */
10227         if (new->base.visible != cur->base.visible)
10228                 return true;
10229
10230         if (!cur->base.fb || !new->base.fb)
10231                 return false;
10232
10233         if (cur->base.fb->modifier != new->base.fb->modifier ||
10234             cur->base.rotation != new->base.rotation ||
10235             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10236             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10237             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10238             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10239                 return true;
10240
10241         return false;
10242 }
10243
10244 static bool needs_scaling(const struct intel_plane_state *state)
10245 {
10246         int src_w = drm_rect_width(&state->base.src) >> 16;
10247         int src_h = drm_rect_height(&state->base.src) >> 16;
10248         int dst_w = drm_rect_width(&state->base.dst);
10249         int dst_h = drm_rect_height(&state->base.dst);
10250
10251         return (src_w != dst_w || src_h != dst_h);
10252 }
10253
10254 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10255                                     struct drm_crtc_state *crtc_state,
10256                                     const struct intel_plane_state *old_plane_state,
10257                                     struct drm_plane_state *plane_state)
10258 {
10259         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10260         struct drm_crtc *crtc = crtc_state->crtc;
10261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10262         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10263         struct drm_device *dev = crtc->dev;
10264         struct drm_i915_private *dev_priv = to_i915(dev);
10265         bool mode_changed = needs_modeset(crtc_state);
10266         bool was_crtc_enabled = old_crtc_state->base.active;
10267         bool is_crtc_enabled = crtc_state->active;
10268         bool turn_off, turn_on, visible, was_visible;
10269         struct drm_framebuffer *fb = plane_state->fb;
10270         int ret;
10271
10272         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10273                 ret = skl_update_scaler_plane(
10274                         to_intel_crtc_state(crtc_state),
10275                         to_intel_plane_state(plane_state));
10276                 if (ret)
10277                         return ret;
10278         }
10279
10280         was_visible = old_plane_state->base.visible;
10281         visible = plane_state->visible;
10282
10283         if (!was_crtc_enabled && WARN_ON(was_visible))
10284                 was_visible = false;
10285
10286         /*
10287          * Visibility is calculated as if the crtc was on, but
10288          * after scaler setup everything depends on it being off
10289          * when the crtc isn't active.
10290          *
10291          * FIXME this is wrong for watermarks. Watermarks should also
10292          * be computed as if the pipe would be active. Perhaps move
10293          * per-plane wm computation to the .check_plane() hook, and
10294          * only combine the results from all planes in the current place?
10295          */
10296         if (!is_crtc_enabled) {
10297                 plane_state->visible = visible = false;
10298                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10299         }
10300
10301         if (!was_visible && !visible)
10302                 return 0;
10303
10304         if (fb != old_plane_state->base.fb)
10305                 pipe_config->fb_changed = true;
10306
10307         turn_off = was_visible && (!visible || mode_changed);
10308         turn_on = visible && (!was_visible || mode_changed);
10309
10310         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10311                          intel_crtc->base.base.id, intel_crtc->base.name,
10312                          plane->base.base.id, plane->base.name,
10313                          fb ? fb->base.id : -1);
10314
10315         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10316                          plane->base.base.id, plane->base.name,
10317                          was_visible, visible,
10318                          turn_off, turn_on, mode_changed);
10319
10320         if (turn_on) {
10321                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10322                         pipe_config->update_wm_pre = true;
10323
10324                 /* must disable cxsr around plane enable/disable */
10325                 if (plane->id != PLANE_CURSOR)
10326                         pipe_config->disable_cxsr = true;
10327         } else if (turn_off) {
10328                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10329                         pipe_config->update_wm_post = true;
10330
10331                 /* must disable cxsr around plane enable/disable */
10332                 if (plane->id != PLANE_CURSOR)
10333                         pipe_config->disable_cxsr = true;
10334         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10335                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10336                         /* FIXME bollocks */
10337                         pipe_config->update_wm_pre = true;
10338                         pipe_config->update_wm_post = true;
10339                 }
10340         }
10341
10342         if (visible || was_visible)
10343                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10344
10345         /*
10346          * WaCxSRDisabledForSpriteScaling:ivb
10347          *
10348          * cstate->update_wm was already set above, so this flag will
10349          * take effect when we commit and program watermarks.
10350          */
10351         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10352             needs_scaling(to_intel_plane_state(plane_state)) &&
10353             !needs_scaling(old_plane_state))
10354                 pipe_config->disable_lp_wm = true;
10355
10356         return 0;
10357 }
10358
10359 static bool encoders_cloneable(const struct intel_encoder *a,
10360                                const struct intel_encoder *b)
10361 {
10362         /* masks could be asymmetric, so check both ways */
10363         return a == b || (a->cloneable & (1 << b->type) &&
10364                           b->cloneable & (1 << a->type));
10365 }
10366
10367 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10368                                          struct intel_crtc *crtc,
10369                                          struct intel_encoder *encoder)
10370 {
10371         struct intel_encoder *source_encoder;
10372         struct drm_connector *connector;
10373         struct drm_connector_state *connector_state;
10374         int i;
10375
10376         for_each_new_connector_in_state(state, connector, connector_state, i) {
10377                 if (connector_state->crtc != &crtc->base)
10378                         continue;
10379
10380                 source_encoder =
10381                         to_intel_encoder(connector_state->best_encoder);
10382                 if (!encoders_cloneable(encoder, source_encoder))
10383                         return false;
10384         }
10385
10386         return true;
10387 }
10388
10389 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10390                                    struct drm_crtc_state *crtc_state)
10391 {
10392         struct drm_device *dev = crtc->dev;
10393         struct drm_i915_private *dev_priv = to_i915(dev);
10394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10395         struct intel_crtc_state *pipe_config =
10396                 to_intel_crtc_state(crtc_state);
10397         struct drm_atomic_state *state = crtc_state->state;
10398         int ret;
10399         bool mode_changed = needs_modeset(crtc_state);
10400
10401         if (mode_changed && !crtc_state->active)
10402                 pipe_config->update_wm_post = true;
10403
10404         if (mode_changed && crtc_state->enable &&
10405             dev_priv->display.crtc_compute_clock &&
10406             !WARN_ON(pipe_config->shared_dpll)) {
10407                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10408                                                            pipe_config);
10409                 if (ret)
10410                         return ret;
10411         }
10412
10413         if (crtc_state->color_mgmt_changed) {
10414                 ret = intel_color_check(crtc, crtc_state);
10415                 if (ret)
10416                         return ret;
10417
10418                 /*
10419                  * Changing color management on Intel hardware is
10420                  * handled as part of planes update.
10421                  */
10422                 crtc_state->planes_changed = true;
10423         }
10424
10425         ret = 0;
10426         if (dev_priv->display.compute_pipe_wm) {
10427                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10428                 if (ret) {
10429                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10430                         return ret;
10431                 }
10432         }
10433
10434         if (dev_priv->display.compute_intermediate_wm &&
10435             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10436                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10437                         return 0;
10438
10439                 /*
10440                  * Calculate 'intermediate' watermarks that satisfy both the
10441                  * old state and the new state.  We can program these
10442                  * immediately.
10443                  */
10444                 ret = dev_priv->display.compute_intermediate_wm(dev,
10445                                                                 intel_crtc,
10446                                                                 pipe_config);
10447                 if (ret) {
10448                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10449                         return ret;
10450                 }
10451         } else if (dev_priv->display.compute_intermediate_wm) {
10452                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10453                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10454         }
10455
10456         if (INTEL_GEN(dev_priv) >= 9) {
10457                 if (mode_changed)
10458                         ret = skl_update_scaler_crtc(pipe_config);
10459
10460                 if (!ret)
10461                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10462                                                             pipe_config);
10463                 if (!ret)
10464                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10465                                                          pipe_config);
10466         }
10467
10468         return ret;
10469 }
10470
10471 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10472         .atomic_begin = intel_begin_crtc_commit,
10473         .atomic_flush = intel_finish_crtc_commit,
10474         .atomic_check = intel_crtc_atomic_check,
10475 };
10476
10477 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10478 {
10479         struct intel_connector *connector;
10480         struct drm_connector_list_iter conn_iter;
10481
10482         drm_connector_list_iter_begin(dev, &conn_iter);
10483         for_each_intel_connector_iter(connector, &conn_iter) {
10484                 if (connector->base.state->crtc)
10485                         drm_connector_unreference(&connector->base);
10486
10487                 if (connector->base.encoder) {
10488                         connector->base.state->best_encoder =
10489                                 connector->base.encoder;
10490                         connector->base.state->crtc =
10491                                 connector->base.encoder->crtc;
10492
10493                         drm_connector_reference(&connector->base);
10494                 } else {
10495                         connector->base.state->best_encoder = NULL;
10496                         connector->base.state->crtc = NULL;
10497                 }
10498         }
10499         drm_connector_list_iter_end(&conn_iter);
10500 }
10501
10502 static void
10503 connected_sink_compute_bpp(struct intel_connector *connector,
10504                            struct intel_crtc_state *pipe_config)
10505 {
10506         const struct drm_display_info *info = &connector->base.display_info;
10507         int bpp = pipe_config->pipe_bpp;
10508
10509         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10510                       connector->base.base.id,
10511                       connector->base.name);
10512
10513         /* Don't use an invalid EDID bpc value */
10514         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10515                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10516                               bpp, info->bpc * 3);
10517                 pipe_config->pipe_bpp = info->bpc * 3;
10518         }
10519
10520         /* Clamp bpp to 8 on screens without EDID 1.4 */
10521         if (info->bpc == 0 && bpp > 24) {
10522                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10523                               bpp);
10524                 pipe_config->pipe_bpp = 24;
10525         }
10526 }
10527
10528 static int
10529 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10530                           struct intel_crtc_state *pipe_config)
10531 {
10532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10533         struct drm_atomic_state *state;
10534         struct drm_connector *connector;
10535         struct drm_connector_state *connector_state;
10536         int bpp, i;
10537
10538         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10539             IS_CHERRYVIEW(dev_priv)))
10540                 bpp = 10*3;
10541         else if (INTEL_GEN(dev_priv) >= 5)
10542                 bpp = 12*3;
10543         else
10544                 bpp = 8*3;
10545
10546
10547         pipe_config->pipe_bpp = bpp;
10548
10549         state = pipe_config->base.state;
10550
10551         /* Clamp display bpp to EDID value */
10552         for_each_new_connector_in_state(state, connector, connector_state, i) {
10553                 if (connector_state->crtc != &crtc->base)
10554                         continue;
10555
10556                 connected_sink_compute_bpp(to_intel_connector(connector),
10557                                            pipe_config);
10558         }
10559
10560         return bpp;
10561 }
10562
10563 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10564 {
10565         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10566                         "type: 0x%x flags: 0x%x\n",
10567                 mode->crtc_clock,
10568                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10569                 mode->crtc_hsync_end, mode->crtc_htotal,
10570                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10571                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10572 }
10573
10574 static inline void
10575 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10576                       unsigned int lane_count, struct intel_link_m_n *m_n)
10577 {
10578         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10579                       id, lane_count,
10580                       m_n->gmch_m, m_n->gmch_n,
10581                       m_n->link_m, m_n->link_n, m_n->tu);
10582 }
10583
10584 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10585
10586 static const char * const output_type_str[] = {
10587         OUTPUT_TYPE(UNUSED),
10588         OUTPUT_TYPE(ANALOG),
10589         OUTPUT_TYPE(DVO),
10590         OUTPUT_TYPE(SDVO),
10591         OUTPUT_TYPE(LVDS),
10592         OUTPUT_TYPE(TVOUT),
10593         OUTPUT_TYPE(HDMI),
10594         OUTPUT_TYPE(DP),
10595         OUTPUT_TYPE(EDP),
10596         OUTPUT_TYPE(DSI),
10597         OUTPUT_TYPE(UNKNOWN),
10598         OUTPUT_TYPE(DP_MST),
10599 };
10600
10601 #undef OUTPUT_TYPE
10602
10603 static void snprintf_output_types(char *buf, size_t len,
10604                                   unsigned int output_types)
10605 {
10606         char *str = buf;
10607         int i;
10608
10609         str[0] = '\0';
10610
10611         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10612                 int r;
10613
10614                 if ((output_types & BIT(i)) == 0)
10615                         continue;
10616
10617                 r = snprintf(str, len, "%s%s",
10618                              str != buf ? "," : "", output_type_str[i]);
10619                 if (r >= len)
10620                         break;
10621                 str += r;
10622                 len -= r;
10623
10624                 output_types &= ~BIT(i);
10625         }
10626
10627         WARN_ON_ONCE(output_types != 0);
10628 }
10629
10630 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10631                                    struct intel_crtc_state *pipe_config,
10632                                    const char *context)
10633 {
10634         struct drm_device *dev = crtc->base.dev;
10635         struct drm_i915_private *dev_priv = to_i915(dev);
10636         struct drm_plane *plane;
10637         struct intel_plane *intel_plane;
10638         struct intel_plane_state *state;
10639         struct drm_framebuffer *fb;
10640         char buf[64];
10641
10642         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10643                       crtc->base.base.id, crtc->base.name, context);
10644
10645         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10646         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10647                       buf, pipe_config->output_types);
10648
10649         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10650                       transcoder_name(pipe_config->cpu_transcoder),
10651                       pipe_config->pipe_bpp, pipe_config->dither);
10652
10653         if (pipe_config->has_pch_encoder)
10654                 intel_dump_m_n_config(pipe_config, "fdi",
10655                                       pipe_config->fdi_lanes,
10656                                       &pipe_config->fdi_m_n);
10657
10658         if (pipe_config->ycbcr420)
10659                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10660
10661         if (intel_crtc_has_dp_encoder(pipe_config)) {
10662                 intel_dump_m_n_config(pipe_config, "dp m_n",
10663                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10664                 if (pipe_config->has_drrs)
10665                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10666                                               pipe_config->lane_count,
10667                                               &pipe_config->dp_m2_n2);
10668         }
10669
10670         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10671                       pipe_config->has_audio, pipe_config->has_infoframe);
10672
10673         DRM_DEBUG_KMS("requested mode:\n");
10674         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10675         DRM_DEBUG_KMS("adjusted mode:\n");
10676         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10677         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10678         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10679                       pipe_config->port_clock,
10680                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10681                       pipe_config->pixel_rate);
10682
10683         if (INTEL_GEN(dev_priv) >= 9)
10684                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10685                               crtc->num_scalers,
10686                               pipe_config->scaler_state.scaler_users,
10687                               pipe_config->scaler_state.scaler_id);
10688
10689         if (HAS_GMCH_DISPLAY(dev_priv))
10690                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10691                               pipe_config->gmch_pfit.control,
10692                               pipe_config->gmch_pfit.pgm_ratios,
10693                               pipe_config->gmch_pfit.lvds_border_bits);
10694         else
10695                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10696                               pipe_config->pch_pfit.pos,
10697                               pipe_config->pch_pfit.size,
10698                               enableddisabled(pipe_config->pch_pfit.enabled));
10699
10700         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10701                       pipe_config->ips_enabled, pipe_config->double_wide);
10702
10703         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10704
10705         DRM_DEBUG_KMS("planes on this crtc\n");
10706         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10707                 struct drm_format_name_buf format_name;
10708                 intel_plane = to_intel_plane(plane);
10709                 if (intel_plane->pipe != crtc->pipe)
10710                         continue;
10711
10712                 state = to_intel_plane_state(plane->state);
10713                 fb = state->base.fb;
10714                 if (!fb) {
10715                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10716                                       plane->base.id, plane->name, state->scaler_id);
10717                         continue;
10718                 }
10719
10720                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10721                               plane->base.id, plane->name,
10722                               fb->base.id, fb->width, fb->height,
10723                               drm_get_format_name(fb->format->format, &format_name));
10724                 if (INTEL_GEN(dev_priv) >= 9)
10725                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10726                                       state->scaler_id,
10727                                       state->base.src.x1 >> 16,
10728                                       state->base.src.y1 >> 16,
10729                                       drm_rect_width(&state->base.src) >> 16,
10730                                       drm_rect_height(&state->base.src) >> 16,
10731                                       state->base.dst.x1, state->base.dst.y1,
10732                                       drm_rect_width(&state->base.dst),
10733                                       drm_rect_height(&state->base.dst));
10734         }
10735 }
10736
10737 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10738 {
10739         struct drm_device *dev = state->dev;
10740         struct drm_connector *connector;
10741         struct drm_connector_list_iter conn_iter;
10742         unsigned int used_ports = 0;
10743         unsigned int used_mst_ports = 0;
10744
10745         /*
10746          * Walk the connector list instead of the encoder
10747          * list to detect the problem on ddi platforms
10748          * where there's just one encoder per digital port.
10749          */
10750         drm_connector_list_iter_begin(dev, &conn_iter);
10751         drm_for_each_connector_iter(connector, &conn_iter) {
10752                 struct drm_connector_state *connector_state;
10753                 struct intel_encoder *encoder;
10754
10755                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10756                 if (!connector_state)
10757                         connector_state = connector->state;
10758
10759                 if (!connector_state->best_encoder)
10760                         continue;
10761
10762                 encoder = to_intel_encoder(connector_state->best_encoder);
10763
10764                 WARN_ON(!connector_state->crtc);
10765
10766                 switch (encoder->type) {
10767                         unsigned int port_mask;
10768                 case INTEL_OUTPUT_UNKNOWN:
10769                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10770                                 break;
10771                 case INTEL_OUTPUT_DP:
10772                 case INTEL_OUTPUT_HDMI:
10773                 case INTEL_OUTPUT_EDP:
10774                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10775
10776                         /* the same port mustn't appear more than once */
10777                         if (used_ports & port_mask)
10778                                 return false;
10779
10780                         used_ports |= port_mask;
10781                         break;
10782                 case INTEL_OUTPUT_DP_MST:
10783                         used_mst_ports |=
10784                                 1 << enc_to_mst(&encoder->base)->primary->port;
10785                         break;
10786                 default:
10787                         break;
10788                 }
10789         }
10790         drm_connector_list_iter_end(&conn_iter);
10791
10792         /* can't mix MST and SST/HDMI on the same port */
10793         if (used_ports & used_mst_ports)
10794                 return false;
10795
10796         return true;
10797 }
10798
10799 static void
10800 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10801 {
10802         struct drm_i915_private *dev_priv =
10803                 to_i915(crtc_state->base.crtc->dev);
10804         struct intel_crtc_scaler_state scaler_state;
10805         struct intel_dpll_hw_state dpll_hw_state;
10806         struct intel_shared_dpll *shared_dpll;
10807         struct intel_crtc_wm_state wm_state;
10808         bool force_thru, ips_force_disable;
10809
10810         /* FIXME: before the switch to atomic started, a new pipe_config was
10811          * kzalloc'd. Code that depends on any field being zero should be
10812          * fixed, so that the crtc_state can be safely duplicated. For now,
10813          * only fields that are know to not cause problems are preserved. */
10814
10815         scaler_state = crtc_state->scaler_state;
10816         shared_dpll = crtc_state->shared_dpll;
10817         dpll_hw_state = crtc_state->dpll_hw_state;
10818         force_thru = crtc_state->pch_pfit.force_thru;
10819         ips_force_disable = crtc_state->ips_force_disable;
10820         if (IS_G4X(dev_priv) ||
10821             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10822                 wm_state = crtc_state->wm;
10823
10824         /* Keep base drm_crtc_state intact, only clear our extended struct */
10825         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10826         memset(&crtc_state->base + 1, 0,
10827                sizeof(*crtc_state) - sizeof(crtc_state->base));
10828
10829         crtc_state->scaler_state = scaler_state;
10830         crtc_state->shared_dpll = shared_dpll;
10831         crtc_state->dpll_hw_state = dpll_hw_state;
10832         crtc_state->pch_pfit.force_thru = force_thru;
10833         crtc_state->ips_force_disable = ips_force_disable;
10834         if (IS_G4X(dev_priv) ||
10835             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10836                 crtc_state->wm = wm_state;
10837 }
10838
10839 static int
10840 intel_modeset_pipe_config(struct drm_crtc *crtc,
10841                           struct intel_crtc_state *pipe_config)
10842 {
10843         struct drm_atomic_state *state = pipe_config->base.state;
10844         struct intel_encoder *encoder;
10845         struct drm_connector *connector;
10846         struct drm_connector_state *connector_state;
10847         int base_bpp, ret = -EINVAL;
10848         int i;
10849         bool retry = true;
10850
10851         clear_intel_crtc_state(pipe_config);
10852
10853         pipe_config->cpu_transcoder =
10854                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10855
10856         /*
10857          * Sanitize sync polarity flags based on requested ones. If neither
10858          * positive or negative polarity is requested, treat this as meaning
10859          * negative polarity.
10860          */
10861         if (!(pipe_config->base.adjusted_mode.flags &
10862               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10863                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10864
10865         if (!(pipe_config->base.adjusted_mode.flags &
10866               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10867                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10868
10869         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10870                                              pipe_config);
10871         if (base_bpp < 0)
10872                 goto fail;
10873
10874         /*
10875          * Determine the real pipe dimensions. Note that stereo modes can
10876          * increase the actual pipe size due to the frame doubling and
10877          * insertion of additional space for blanks between the frame. This
10878          * is stored in the crtc timings. We use the requested mode to do this
10879          * computation to clearly distinguish it from the adjusted mode, which
10880          * can be changed by the connectors in the below retry loop.
10881          */
10882         drm_mode_get_hv_timing(&pipe_config->base.mode,
10883                                &pipe_config->pipe_src_w,
10884                                &pipe_config->pipe_src_h);
10885
10886         for_each_new_connector_in_state(state, connector, connector_state, i) {
10887                 if (connector_state->crtc != crtc)
10888                         continue;
10889
10890                 encoder = to_intel_encoder(connector_state->best_encoder);
10891
10892                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10893                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10894                         goto fail;
10895                 }
10896
10897                 /*
10898                  * Determine output_types before calling the .compute_config()
10899                  * hooks so that the hooks can use this information safely.
10900                  */
10901                 pipe_config->output_types |= 1 << encoder->type;
10902         }
10903
10904 encoder_retry:
10905         /* Ensure the port clock defaults are reset when retrying. */
10906         pipe_config->port_clock = 0;
10907         pipe_config->pixel_multiplier = 1;
10908
10909         /* Fill in default crtc timings, allow encoders to overwrite them. */
10910         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10911                               CRTC_STEREO_DOUBLE);
10912
10913         /* Pass our mode to the connectors and the CRTC to give them a chance to
10914          * adjust it according to limitations or connector properties, and also
10915          * a chance to reject the mode entirely.
10916          */
10917         for_each_new_connector_in_state(state, connector, connector_state, i) {
10918                 if (connector_state->crtc != crtc)
10919                         continue;
10920
10921                 encoder = to_intel_encoder(connector_state->best_encoder);
10922
10923                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10924                         DRM_DEBUG_KMS("Encoder config failure\n");
10925                         goto fail;
10926                 }
10927         }
10928
10929         /* Set default port clock if not overwritten by the encoder. Needs to be
10930          * done afterwards in case the encoder adjusts the mode. */
10931         if (!pipe_config->port_clock)
10932                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10933                         * pipe_config->pixel_multiplier;
10934
10935         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10936         if (ret < 0) {
10937                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10938                 goto fail;
10939         }
10940
10941         if (ret == RETRY) {
10942                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10943                         ret = -EINVAL;
10944                         goto fail;
10945                 }
10946
10947                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10948                 retry = false;
10949                 goto encoder_retry;
10950         }
10951
10952         /* Dithering seems to not pass-through bits correctly when it should, so
10953          * only enable it on 6bpc panels and when its not a compliance
10954          * test requesting 6bpc video pattern.
10955          */
10956         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10957                 !pipe_config->dither_force_disable;
10958         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10959                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10960
10961 fail:
10962         return ret;
10963 }
10964
10965 static void
10966 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10967 {
10968         struct drm_crtc *crtc;
10969         struct drm_crtc_state *new_crtc_state;
10970         int i;
10971
10972         /* Double check state. */
10973         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10974                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10975
10976                 /*
10977                  * Update legacy state to satisfy fbc code. This can
10978                  * be removed when fbc uses the atomic state.
10979                  */
10980                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10981                         struct drm_plane_state *plane_state = crtc->primary->state;
10982
10983                         crtc->primary->fb = plane_state->fb;
10984                         crtc->x = plane_state->src_x >> 16;
10985                         crtc->y = plane_state->src_y >> 16;
10986                 }
10987         }
10988 }
10989
10990 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10991 {
10992         int diff;
10993
10994         if (clock1 == clock2)
10995                 return true;
10996
10997         if (!clock1 || !clock2)
10998                 return false;
10999
11000         diff = abs(clock1 - clock2);
11001
11002         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11003                 return true;
11004
11005         return false;
11006 }
11007
11008 static bool
11009 intel_compare_m_n(unsigned int m, unsigned int n,
11010                   unsigned int m2, unsigned int n2,
11011                   bool exact)
11012 {
11013         if (m == m2 && n == n2)
11014                 return true;
11015
11016         if (exact || !m || !n || !m2 || !n2)
11017                 return false;
11018
11019         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11020
11021         if (n > n2) {
11022                 while (n > n2) {
11023                         m2 <<= 1;
11024                         n2 <<= 1;
11025                 }
11026         } else if (n < n2) {
11027                 while (n < n2) {
11028                         m <<= 1;
11029                         n <<= 1;
11030                 }
11031         }
11032
11033         if (n != n2)
11034                 return false;
11035
11036         return intel_fuzzy_clock_check(m, m2);
11037 }
11038
11039 static bool
11040 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11041                        struct intel_link_m_n *m2_n2,
11042                        bool adjust)
11043 {
11044         if (m_n->tu == m2_n2->tu &&
11045             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11046                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11047             intel_compare_m_n(m_n->link_m, m_n->link_n,
11048                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11049                 if (adjust)
11050                         *m2_n2 = *m_n;
11051
11052                 return true;
11053         }
11054
11055         return false;
11056 }
11057
11058 static void __printf(3, 4)
11059 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11060 {
11061         char *level;
11062         unsigned int category;
11063         struct va_format vaf;
11064         va_list args;
11065
11066         if (adjust) {
11067                 level = KERN_DEBUG;
11068                 category = DRM_UT_KMS;
11069         } else {
11070                 level = KERN_ERR;
11071                 category = DRM_UT_NONE;
11072         }
11073
11074         va_start(args, format);
11075         vaf.fmt = format;
11076         vaf.va = &args;
11077
11078         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11079
11080         va_end(args);
11081 }
11082
11083 static bool
11084 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11085                           struct intel_crtc_state *current_config,
11086                           struct intel_crtc_state *pipe_config,
11087                           bool adjust)
11088 {
11089         bool ret = true;
11090
11091 #define PIPE_CONF_CHECK_X(name) \
11092         if (current_config->name != pipe_config->name) { \
11093                 pipe_config_err(adjust, __stringify(name), \
11094                           "(expected 0x%08x, found 0x%08x)\n", \
11095                           current_config->name, \
11096                           pipe_config->name); \
11097                 ret = false; \
11098         }
11099
11100 #define PIPE_CONF_CHECK_I(name) \
11101         if (current_config->name != pipe_config->name) { \
11102                 pipe_config_err(adjust, __stringify(name), \
11103                           "(expected %i, found %i)\n", \
11104                           current_config->name, \
11105                           pipe_config->name); \
11106                 ret = false; \
11107         }
11108
11109 #define PIPE_CONF_CHECK_P(name) \
11110         if (current_config->name != pipe_config->name) { \
11111                 pipe_config_err(adjust, __stringify(name), \
11112                           "(expected %p, found %p)\n", \
11113                           current_config->name, \
11114                           pipe_config->name); \
11115                 ret = false; \
11116         }
11117
11118 #define PIPE_CONF_CHECK_M_N(name) \
11119         if (!intel_compare_link_m_n(&current_config->name, \
11120                                     &pipe_config->name,\
11121                                     adjust)) { \
11122                 pipe_config_err(adjust, __stringify(name), \
11123                           "(expected tu %i gmch %i/%i link %i/%i, " \
11124                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11125                           current_config->name.tu, \
11126                           current_config->name.gmch_m, \
11127                           current_config->name.gmch_n, \
11128                           current_config->name.link_m, \
11129                           current_config->name.link_n, \
11130                           pipe_config->name.tu, \
11131                           pipe_config->name.gmch_m, \
11132                           pipe_config->name.gmch_n, \
11133                           pipe_config->name.link_m, \
11134                           pipe_config->name.link_n); \
11135                 ret = false; \
11136         }
11137
11138 /* This is required for BDW+ where there is only one set of registers for
11139  * switching between high and low RR.
11140  * This macro can be used whenever a comparison has to be made between one
11141  * hw state and multiple sw state variables.
11142  */
11143 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11144         if (!intel_compare_link_m_n(&current_config->name, \
11145                                     &pipe_config->name, adjust) && \
11146             !intel_compare_link_m_n(&current_config->alt_name, \
11147                                     &pipe_config->name, adjust)) { \
11148                 pipe_config_err(adjust, __stringify(name), \
11149                           "(expected tu %i gmch %i/%i link %i/%i, " \
11150                           "or tu %i gmch %i/%i link %i/%i, " \
11151                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11152                           current_config->name.tu, \
11153                           current_config->name.gmch_m, \
11154                           current_config->name.gmch_n, \
11155                           current_config->name.link_m, \
11156                           current_config->name.link_n, \
11157                           current_config->alt_name.tu, \
11158                           current_config->alt_name.gmch_m, \
11159                           current_config->alt_name.gmch_n, \
11160                           current_config->alt_name.link_m, \
11161                           current_config->alt_name.link_n, \
11162                           pipe_config->name.tu, \
11163                           pipe_config->name.gmch_m, \
11164                           pipe_config->name.gmch_n, \
11165                           pipe_config->name.link_m, \
11166                           pipe_config->name.link_n); \
11167                 ret = false; \
11168         }
11169
11170 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11171         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11172                 pipe_config_err(adjust, __stringify(name), \
11173                           "(%x) (expected %i, found %i)\n", \
11174                           (mask), \
11175                           current_config->name & (mask), \
11176                           pipe_config->name & (mask)); \
11177                 ret = false; \
11178         }
11179
11180 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11181         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11182                 pipe_config_err(adjust, __stringify(name), \
11183                           "(expected %i, found %i)\n", \
11184                           current_config->name, \
11185                           pipe_config->name); \
11186                 ret = false; \
11187         }
11188
11189 #define PIPE_CONF_QUIRK(quirk)  \
11190         ((current_config->quirks | pipe_config->quirks) & (quirk))
11191
11192         PIPE_CONF_CHECK_I(cpu_transcoder);
11193
11194         PIPE_CONF_CHECK_I(has_pch_encoder);
11195         PIPE_CONF_CHECK_I(fdi_lanes);
11196         PIPE_CONF_CHECK_M_N(fdi_m_n);
11197
11198         PIPE_CONF_CHECK_I(lane_count);
11199         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11200
11201         if (INTEL_GEN(dev_priv) < 8) {
11202                 PIPE_CONF_CHECK_M_N(dp_m_n);
11203
11204                 if (current_config->has_drrs)
11205                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11206         } else
11207                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11208
11209         PIPE_CONF_CHECK_X(output_types);
11210
11211         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11212         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11213         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11214         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11215         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11216         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11217
11218         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11219         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11220         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11221         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11222         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11223         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11224
11225         PIPE_CONF_CHECK_I(pixel_multiplier);
11226         PIPE_CONF_CHECK_I(has_hdmi_sink);
11227         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11228             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11229                 PIPE_CONF_CHECK_I(limited_color_range);
11230
11231         PIPE_CONF_CHECK_I(hdmi_scrambling);
11232         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11233         PIPE_CONF_CHECK_I(has_infoframe);
11234         PIPE_CONF_CHECK_I(ycbcr420);
11235
11236         PIPE_CONF_CHECK_I(has_audio);
11237
11238         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11239                               DRM_MODE_FLAG_INTERLACE);
11240
11241         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11242                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11243                                       DRM_MODE_FLAG_PHSYNC);
11244                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11245                                       DRM_MODE_FLAG_NHSYNC);
11246                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11247                                       DRM_MODE_FLAG_PVSYNC);
11248                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11249                                       DRM_MODE_FLAG_NVSYNC);
11250         }
11251
11252         PIPE_CONF_CHECK_X(gmch_pfit.control);
11253         /* pfit ratios are autocomputed by the hw on gen4+ */
11254         if (INTEL_GEN(dev_priv) < 4)
11255                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11256         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11257
11258         if (!adjust) {
11259                 PIPE_CONF_CHECK_I(pipe_src_w);
11260                 PIPE_CONF_CHECK_I(pipe_src_h);
11261
11262                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11263                 if (current_config->pch_pfit.enabled) {
11264                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11265                         PIPE_CONF_CHECK_X(pch_pfit.size);
11266                 }
11267
11268                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11269                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11270         }
11271
11272         /* BDW+ don't expose a synchronous way to read the state */
11273         if (IS_HASWELL(dev_priv))
11274                 PIPE_CONF_CHECK_I(ips_enabled);
11275
11276         PIPE_CONF_CHECK_I(double_wide);
11277
11278         PIPE_CONF_CHECK_P(shared_dpll);
11279         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11280         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11281         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11282         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11283         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11284         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11285         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11286         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11287         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11288         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11289         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11290         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11291         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11292         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11293         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11294         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11295         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11296         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11297         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11298         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11299         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11300
11301         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11302         PIPE_CONF_CHECK_X(dsi_pll.div);
11303
11304         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11305                 PIPE_CONF_CHECK_I(pipe_bpp);
11306
11307         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11308         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11309
11310 #undef PIPE_CONF_CHECK_X
11311 #undef PIPE_CONF_CHECK_I
11312 #undef PIPE_CONF_CHECK_P
11313 #undef PIPE_CONF_CHECK_FLAGS
11314 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11315 #undef PIPE_CONF_QUIRK
11316
11317         return ret;
11318 }
11319
11320 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11321                                            const struct intel_crtc_state *pipe_config)
11322 {
11323         if (pipe_config->has_pch_encoder) {
11324                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11325                                                             &pipe_config->fdi_m_n);
11326                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11327
11328                 /*
11329                  * FDI already provided one idea for the dotclock.
11330                  * Yell if the encoder disagrees.
11331                  */
11332                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11333                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11334                      fdi_dotclock, dotclock);
11335         }
11336 }
11337
11338 static void verify_wm_state(struct drm_crtc *crtc,
11339                             struct drm_crtc_state *new_state)
11340 {
11341         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11342         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11343         struct skl_pipe_wm hw_wm, *sw_wm;
11344         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11345         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11347         const enum pipe pipe = intel_crtc->pipe;
11348         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11349
11350         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11351                 return;
11352
11353         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11354         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11355
11356         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11357         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11358
11359         /* planes */
11360         for_each_universal_plane(dev_priv, pipe, plane) {
11361                 hw_plane_wm = &hw_wm.planes[plane];
11362                 sw_plane_wm = &sw_wm->planes[plane];
11363
11364                 /* Watermarks */
11365                 for (level = 0; level <= max_level; level++) {
11366                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11367                                                 &sw_plane_wm->wm[level]))
11368                                 continue;
11369
11370                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11371                                   pipe_name(pipe), plane + 1, level,
11372                                   sw_plane_wm->wm[level].plane_en,
11373                                   sw_plane_wm->wm[level].plane_res_b,
11374                                   sw_plane_wm->wm[level].plane_res_l,
11375                                   hw_plane_wm->wm[level].plane_en,
11376                                   hw_plane_wm->wm[level].plane_res_b,
11377                                   hw_plane_wm->wm[level].plane_res_l);
11378                 }
11379
11380                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11381                                          &sw_plane_wm->trans_wm)) {
11382                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11383                                   pipe_name(pipe), plane + 1,
11384                                   sw_plane_wm->trans_wm.plane_en,
11385                                   sw_plane_wm->trans_wm.plane_res_b,
11386                                   sw_plane_wm->trans_wm.plane_res_l,
11387                                   hw_plane_wm->trans_wm.plane_en,
11388                                   hw_plane_wm->trans_wm.plane_res_b,
11389                                   hw_plane_wm->trans_wm.plane_res_l);
11390                 }
11391
11392                 /* DDB */
11393                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11394                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11395
11396                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11397                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11398                                   pipe_name(pipe), plane + 1,
11399                                   sw_ddb_entry->start, sw_ddb_entry->end,
11400                                   hw_ddb_entry->start, hw_ddb_entry->end);
11401                 }
11402         }
11403
11404         /*
11405          * cursor
11406          * If the cursor plane isn't active, we may not have updated it's ddb
11407          * allocation. In that case since the ddb allocation will be updated
11408          * once the plane becomes visible, we can skip this check
11409          */
11410         if (1) {
11411                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11412                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11413
11414                 /* Watermarks */
11415                 for (level = 0; level <= max_level; level++) {
11416                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11417                                                 &sw_plane_wm->wm[level]))
11418                                 continue;
11419
11420                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11421                                   pipe_name(pipe), level,
11422                                   sw_plane_wm->wm[level].plane_en,
11423                                   sw_plane_wm->wm[level].plane_res_b,
11424                                   sw_plane_wm->wm[level].plane_res_l,
11425                                   hw_plane_wm->wm[level].plane_en,
11426                                   hw_plane_wm->wm[level].plane_res_b,
11427                                   hw_plane_wm->wm[level].plane_res_l);
11428                 }
11429
11430                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11431                                          &sw_plane_wm->trans_wm)) {
11432                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11433                                   pipe_name(pipe),
11434                                   sw_plane_wm->trans_wm.plane_en,
11435                                   sw_plane_wm->trans_wm.plane_res_b,
11436                                   sw_plane_wm->trans_wm.plane_res_l,
11437                                   hw_plane_wm->trans_wm.plane_en,
11438                                   hw_plane_wm->trans_wm.plane_res_b,
11439                                   hw_plane_wm->trans_wm.plane_res_l);
11440                 }
11441
11442                 /* DDB */
11443                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11444                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11445
11446                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11447                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11448                                   pipe_name(pipe),
11449                                   sw_ddb_entry->start, sw_ddb_entry->end,
11450                                   hw_ddb_entry->start, hw_ddb_entry->end);
11451                 }
11452         }
11453 }
11454
11455 static void
11456 verify_connector_state(struct drm_device *dev,
11457                        struct drm_atomic_state *state,
11458                        struct drm_crtc *crtc)
11459 {
11460         struct drm_connector *connector;
11461         struct drm_connector_state *new_conn_state;
11462         int i;
11463
11464         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11465                 struct drm_encoder *encoder = connector->encoder;
11466                 struct drm_crtc_state *crtc_state = NULL;
11467
11468                 if (new_conn_state->crtc != crtc)
11469                         continue;
11470
11471                 if (crtc)
11472                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11473
11474                 intel_connector_verify_state(crtc_state, new_conn_state);
11475
11476                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11477                      "connector's atomic encoder doesn't match legacy encoder\n");
11478         }
11479 }
11480
11481 static void
11482 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11483 {
11484         struct intel_encoder *encoder;
11485         struct drm_connector *connector;
11486         struct drm_connector_state *old_conn_state, *new_conn_state;
11487         int i;
11488
11489         for_each_intel_encoder(dev, encoder) {
11490                 bool enabled = false, found = false;
11491                 enum pipe pipe;
11492
11493                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11494                               encoder->base.base.id,
11495                               encoder->base.name);
11496
11497                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11498                                                    new_conn_state, i) {
11499                         if (old_conn_state->best_encoder == &encoder->base)
11500                                 found = true;
11501
11502                         if (new_conn_state->best_encoder != &encoder->base)
11503                                 continue;
11504                         found = enabled = true;
11505
11506                         I915_STATE_WARN(new_conn_state->crtc !=
11507                                         encoder->base.crtc,
11508                              "connector's crtc doesn't match encoder crtc\n");
11509                 }
11510
11511                 if (!found)
11512                         continue;
11513
11514                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11515                      "encoder's enabled state mismatch "
11516                      "(expected %i, found %i)\n",
11517                      !!encoder->base.crtc, enabled);
11518
11519                 if (!encoder->base.crtc) {
11520                         bool active;
11521
11522                         active = encoder->get_hw_state(encoder, &pipe);
11523                         I915_STATE_WARN(active,
11524                              "encoder detached but still enabled on pipe %c.\n",
11525                              pipe_name(pipe));
11526                 }
11527         }
11528 }
11529
11530 static void
11531 verify_crtc_state(struct drm_crtc *crtc,
11532                   struct drm_crtc_state *old_crtc_state,
11533                   struct drm_crtc_state *new_crtc_state)
11534 {
11535         struct drm_device *dev = crtc->dev;
11536         struct drm_i915_private *dev_priv = to_i915(dev);
11537         struct intel_encoder *encoder;
11538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11539         struct intel_crtc_state *pipe_config, *sw_config;
11540         struct drm_atomic_state *old_state;
11541         bool active;
11542
11543         old_state = old_crtc_state->state;
11544         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11545         pipe_config = to_intel_crtc_state(old_crtc_state);
11546         memset(pipe_config, 0, sizeof(*pipe_config));
11547         pipe_config->base.crtc = crtc;
11548         pipe_config->base.state = old_state;
11549
11550         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11551
11552         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11553
11554         /* we keep both pipes enabled on 830 */
11555         if (IS_I830(dev_priv))
11556                 active = new_crtc_state->active;
11557
11558         I915_STATE_WARN(new_crtc_state->active != active,
11559              "crtc active state doesn't match with hw state "
11560              "(expected %i, found %i)\n", new_crtc_state->active, active);
11561
11562         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11563              "transitional active state does not match atomic hw state "
11564              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11565
11566         for_each_encoder_on_crtc(dev, crtc, encoder) {
11567                 enum pipe pipe;
11568
11569                 active = encoder->get_hw_state(encoder, &pipe);
11570                 I915_STATE_WARN(active != new_crtc_state->active,
11571                         "[ENCODER:%i] active %i with crtc active %i\n",
11572                         encoder->base.base.id, active, new_crtc_state->active);
11573
11574                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11575                                 "Encoder connected to wrong pipe %c\n",
11576                                 pipe_name(pipe));
11577
11578                 if (active) {
11579                         pipe_config->output_types |= 1 << encoder->type;
11580                         encoder->get_config(encoder, pipe_config);
11581                 }
11582         }
11583
11584         intel_crtc_compute_pixel_rate(pipe_config);
11585
11586         if (!new_crtc_state->active)
11587                 return;
11588
11589         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11590
11591         sw_config = to_intel_crtc_state(new_crtc_state);
11592         if (!intel_pipe_config_compare(dev_priv, sw_config,
11593                                        pipe_config, false)) {
11594                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11595                 intel_dump_pipe_config(intel_crtc, pipe_config,
11596                                        "[hw state]");
11597                 intel_dump_pipe_config(intel_crtc, sw_config,
11598                                        "[sw state]");
11599         }
11600 }
11601
11602 static void
11603 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11604                          struct intel_shared_dpll *pll,
11605                          struct drm_crtc *crtc,
11606                          struct drm_crtc_state *new_state)
11607 {
11608         struct intel_dpll_hw_state dpll_hw_state;
11609         unsigned crtc_mask;
11610         bool active;
11611
11612         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11613
11614         DRM_DEBUG_KMS("%s\n", pll->name);
11615
11616         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11617
11618         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11619                 I915_STATE_WARN(!pll->on && pll->active_mask,
11620                      "pll in active use but not on in sw tracking\n");
11621                 I915_STATE_WARN(pll->on && !pll->active_mask,
11622                      "pll is on but not used by any active crtc\n");
11623                 I915_STATE_WARN(pll->on != active,
11624                      "pll on state mismatch (expected %i, found %i)\n",
11625                      pll->on, active);
11626         }
11627
11628         if (!crtc) {
11629                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11630                                 "more active pll users than references: %x vs %x\n",
11631                                 pll->active_mask, pll->state.crtc_mask);
11632
11633                 return;
11634         }
11635
11636         crtc_mask = 1 << drm_crtc_index(crtc);
11637
11638         if (new_state->active)
11639                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11640                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11641                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11642         else
11643                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11644                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11645                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11646
11647         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11648                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11649                         crtc_mask, pll->state.crtc_mask);
11650
11651         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11652                                           &dpll_hw_state,
11653                                           sizeof(dpll_hw_state)),
11654                         "pll hw state mismatch\n");
11655 }
11656
11657 static void
11658 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11659                          struct drm_crtc_state *old_crtc_state,
11660                          struct drm_crtc_state *new_crtc_state)
11661 {
11662         struct drm_i915_private *dev_priv = to_i915(dev);
11663         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11664         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11665
11666         if (new_state->shared_dpll)
11667                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11668
11669         if (old_state->shared_dpll &&
11670             old_state->shared_dpll != new_state->shared_dpll) {
11671                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11672                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11673
11674                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11675                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11676                                 pipe_name(drm_crtc_index(crtc)));
11677                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11678                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11679                                 pipe_name(drm_crtc_index(crtc)));
11680         }
11681 }
11682
11683 static void
11684 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11685                           struct drm_atomic_state *state,
11686                           struct drm_crtc_state *old_state,
11687                           struct drm_crtc_state *new_state)
11688 {
11689         if (!needs_modeset(new_state) &&
11690             !to_intel_crtc_state(new_state)->update_pipe)
11691                 return;
11692
11693         verify_wm_state(crtc, new_state);
11694         verify_connector_state(crtc->dev, state, crtc);
11695         verify_crtc_state(crtc, old_state, new_state);
11696         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11697 }
11698
11699 static void
11700 verify_disabled_dpll_state(struct drm_device *dev)
11701 {
11702         struct drm_i915_private *dev_priv = to_i915(dev);
11703         int i;
11704
11705         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11706                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11707 }
11708
11709 static void
11710 intel_modeset_verify_disabled(struct drm_device *dev,
11711                               struct drm_atomic_state *state)
11712 {
11713         verify_encoder_state(dev, state);
11714         verify_connector_state(dev, state, NULL);
11715         verify_disabled_dpll_state(dev);
11716 }
11717
11718 static void update_scanline_offset(struct intel_crtc *crtc)
11719 {
11720         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11721
11722         /*
11723          * The scanline counter increments at the leading edge of hsync.
11724          *
11725          * On most platforms it starts counting from vtotal-1 on the
11726          * first active line. That means the scanline counter value is
11727          * always one less than what we would expect. Ie. just after
11728          * start of vblank, which also occurs at start of hsync (on the
11729          * last active line), the scanline counter will read vblank_start-1.
11730          *
11731          * On gen2 the scanline counter starts counting from 1 instead
11732          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11733          * to keep the value positive), instead of adding one.
11734          *
11735          * On HSW+ the behaviour of the scanline counter depends on the output
11736          * type. For DP ports it behaves like most other platforms, but on HDMI
11737          * there's an extra 1 line difference. So we need to add two instead of
11738          * one to the value.
11739          *
11740          * On VLV/CHV DSI the scanline counter would appear to increment
11741          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11742          * that means we can't tell whether we're in vblank or not while
11743          * we're on that particular line. We must still set scanline_offset
11744          * to 1 so that the vblank timestamps come out correct when we query
11745          * the scanline counter from within the vblank interrupt handler.
11746          * However if queried just before the start of vblank we'll get an
11747          * answer that's slightly in the future.
11748          */
11749         if (IS_GEN2(dev_priv)) {
11750                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11751                 int vtotal;
11752
11753                 vtotal = adjusted_mode->crtc_vtotal;
11754                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11755                         vtotal /= 2;
11756
11757                 crtc->scanline_offset = vtotal - 1;
11758         } else if (HAS_DDI(dev_priv) &&
11759                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11760                 crtc->scanline_offset = 2;
11761         } else
11762                 crtc->scanline_offset = 1;
11763 }
11764
11765 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11766 {
11767         struct drm_device *dev = state->dev;
11768         struct drm_i915_private *dev_priv = to_i915(dev);
11769         struct drm_crtc *crtc;
11770         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11771         int i;
11772
11773         if (!dev_priv->display.crtc_compute_clock)
11774                 return;
11775
11776         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11777                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11778                 struct intel_shared_dpll *old_dpll =
11779                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11780
11781                 if (!needs_modeset(new_crtc_state))
11782                         continue;
11783
11784                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11785
11786                 if (!old_dpll)
11787                         continue;
11788
11789                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11790         }
11791 }
11792
11793 /*
11794  * This implements the workaround described in the "notes" section of the mode
11795  * set sequence documentation. When going from no pipes or single pipe to
11796  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11797  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11798  */
11799 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11800 {
11801         struct drm_crtc_state *crtc_state;
11802         struct intel_crtc *intel_crtc;
11803         struct drm_crtc *crtc;
11804         struct intel_crtc_state *first_crtc_state = NULL;
11805         struct intel_crtc_state *other_crtc_state = NULL;
11806         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11807         int i;
11808
11809         /* look at all crtc's that are going to be enabled in during modeset */
11810         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11811                 intel_crtc = to_intel_crtc(crtc);
11812
11813                 if (!crtc_state->active || !needs_modeset(crtc_state))
11814                         continue;
11815
11816                 if (first_crtc_state) {
11817                         other_crtc_state = to_intel_crtc_state(crtc_state);
11818                         break;
11819                 } else {
11820                         first_crtc_state = to_intel_crtc_state(crtc_state);
11821                         first_pipe = intel_crtc->pipe;
11822                 }
11823         }
11824
11825         /* No workaround needed? */
11826         if (!first_crtc_state)
11827                 return 0;
11828
11829         /* w/a possibly needed, check how many crtc's are already enabled. */
11830         for_each_intel_crtc(state->dev, intel_crtc) {
11831                 struct intel_crtc_state *pipe_config;
11832
11833                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11834                 if (IS_ERR(pipe_config))
11835                         return PTR_ERR(pipe_config);
11836
11837                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11838
11839                 if (!pipe_config->base.active ||
11840                     needs_modeset(&pipe_config->base))
11841                         continue;
11842
11843                 /* 2 or more enabled crtcs means no need for w/a */
11844                 if (enabled_pipe != INVALID_PIPE)
11845                         return 0;
11846
11847                 enabled_pipe = intel_crtc->pipe;
11848         }
11849
11850         if (enabled_pipe != INVALID_PIPE)
11851                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11852         else if (other_crtc_state)
11853                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11854
11855         return 0;
11856 }
11857
11858 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11859 {
11860         struct drm_crtc *crtc;
11861
11862         /* Add all pipes to the state */
11863         for_each_crtc(state->dev, crtc) {
11864                 struct drm_crtc_state *crtc_state;
11865
11866                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11867                 if (IS_ERR(crtc_state))
11868                         return PTR_ERR(crtc_state);
11869         }
11870
11871         return 0;
11872 }
11873
11874 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11875 {
11876         struct drm_crtc *crtc;
11877
11878         /*
11879          * Add all pipes to the state, and force
11880          * a modeset on all the active ones.
11881          */
11882         for_each_crtc(state->dev, crtc) {
11883                 struct drm_crtc_state *crtc_state;
11884                 int ret;
11885
11886                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11887                 if (IS_ERR(crtc_state))
11888                         return PTR_ERR(crtc_state);
11889
11890                 if (!crtc_state->active || needs_modeset(crtc_state))
11891                         continue;
11892
11893                 crtc_state->mode_changed = true;
11894
11895                 ret = drm_atomic_add_affected_connectors(state, crtc);
11896                 if (ret)
11897                         return ret;
11898
11899                 ret = drm_atomic_add_affected_planes(state, crtc);
11900                 if (ret)
11901                         return ret;
11902         }
11903
11904         return 0;
11905 }
11906
11907 static int intel_modeset_checks(struct drm_atomic_state *state)
11908 {
11909         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11910         struct drm_i915_private *dev_priv = to_i915(state->dev);
11911         struct drm_crtc *crtc;
11912         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11913         int ret = 0, i;
11914
11915         if (!check_digital_port_conflicts(state)) {
11916                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11917                 return -EINVAL;
11918         }
11919
11920         intel_state->modeset = true;
11921         intel_state->active_crtcs = dev_priv->active_crtcs;
11922         intel_state->cdclk.logical = dev_priv->cdclk.logical;
11923         intel_state->cdclk.actual = dev_priv->cdclk.actual;
11924
11925         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11926                 if (new_crtc_state->active)
11927                         intel_state->active_crtcs |= 1 << i;
11928                 else
11929                         intel_state->active_crtcs &= ~(1 << i);
11930
11931                 if (old_crtc_state->active != new_crtc_state->active)
11932                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11933         }
11934
11935         /*
11936          * See if the config requires any additional preparation, e.g.
11937          * to adjust global state with pipes off.  We need to do this
11938          * here so we can get the modeset_pipe updated config for the new
11939          * mode set on this crtc.  For other crtcs we need to use the
11940          * adjusted_mode bits in the crtc directly.
11941          */
11942         if (dev_priv->display.modeset_calc_cdclk) {
11943                 ret = dev_priv->display.modeset_calc_cdclk(state);
11944                 if (ret < 0)
11945                         return ret;
11946
11947                 /*
11948                  * Writes to dev_priv->cdclk.logical must protected by
11949                  * holding all the crtc locks, even if we don't end up
11950                  * touching the hardware
11951                  */
11952                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11953                                                &intel_state->cdclk.logical)) {
11954                         ret = intel_lock_all_pipes(state);
11955                         if (ret < 0)
11956                                 return ret;
11957                 }
11958
11959                 /* All pipes must be switched off while we change the cdclk. */
11960                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11961                                                &intel_state->cdclk.actual)) {
11962                         ret = intel_modeset_all_pipes(state);
11963                         if (ret < 0)
11964                                 return ret;
11965                 }
11966
11967                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11968                               intel_state->cdclk.logical.cdclk,
11969                               intel_state->cdclk.actual.cdclk);
11970         } else {
11971                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11972         }
11973
11974         intel_modeset_clear_plls(state);
11975
11976         if (IS_HASWELL(dev_priv))
11977                 return haswell_mode_set_planes_workaround(state);
11978
11979         return 0;
11980 }
11981
11982 /*
11983  * Handle calculation of various watermark data at the end of the atomic check
11984  * phase.  The code here should be run after the per-crtc and per-plane 'check'
11985  * handlers to ensure that all derived state has been updated.
11986  */
11987 static int calc_watermark_data(struct drm_atomic_state *state)
11988 {
11989         struct drm_device *dev = state->dev;
11990         struct drm_i915_private *dev_priv = to_i915(dev);
11991
11992         /* Is there platform-specific watermark information to calculate? */
11993         if (dev_priv->display.compute_global_watermarks)
11994                 return dev_priv->display.compute_global_watermarks(state);
11995
11996         return 0;
11997 }
11998
11999 /**
12000  * intel_atomic_check - validate state object
12001  * @dev: drm device
12002  * @state: state to validate
12003  */
12004 static int intel_atomic_check(struct drm_device *dev,
12005                               struct drm_atomic_state *state)
12006 {
12007         struct drm_i915_private *dev_priv = to_i915(dev);
12008         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12009         struct drm_crtc *crtc;
12010         struct drm_crtc_state *old_crtc_state, *crtc_state;
12011         int ret, i;
12012         bool any_ms = false;
12013
12014         ret = drm_atomic_helper_check_modeset(dev, state);
12015         if (ret)
12016                 return ret;
12017
12018         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12019                 struct intel_crtc_state *pipe_config =
12020                         to_intel_crtc_state(crtc_state);
12021
12022                 /* Catch I915_MODE_FLAG_INHERITED */
12023                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12024                         crtc_state->mode_changed = true;
12025
12026                 if (!needs_modeset(crtc_state))
12027                         continue;
12028
12029                 if (!crtc_state->enable) {
12030                         any_ms = true;
12031                         continue;
12032                 }
12033
12034                 /* FIXME: For only active_changed we shouldn't need to do any
12035                  * state recomputation at all. */
12036
12037                 ret = drm_atomic_add_affected_connectors(state, crtc);
12038                 if (ret)
12039                         return ret;
12040
12041                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12042                 if (ret) {
12043                         intel_dump_pipe_config(to_intel_crtc(crtc),
12044                                                pipe_config, "[failed]");
12045                         return ret;
12046                 }
12047
12048                 if (i915_modparams.fastboot &&
12049                     intel_pipe_config_compare(dev_priv,
12050                                         to_intel_crtc_state(old_crtc_state),
12051                                         pipe_config, true)) {
12052                         crtc_state->mode_changed = false;
12053                         pipe_config->update_pipe = true;
12054                 }
12055
12056                 if (needs_modeset(crtc_state))
12057                         any_ms = true;
12058
12059                 ret = drm_atomic_add_affected_planes(state, crtc);
12060                 if (ret)
12061                         return ret;
12062
12063                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12064                                        needs_modeset(crtc_state) ?
12065                                        "[modeset]" : "[fastset]");
12066         }
12067
12068         if (any_ms) {
12069                 ret = intel_modeset_checks(state);
12070
12071                 if (ret)
12072                         return ret;
12073         } else {
12074                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12075         }
12076
12077         ret = drm_atomic_helper_check_planes(dev, state);
12078         if (ret)
12079                 return ret;
12080
12081         intel_fbc_choose_crtc(dev_priv, state);
12082         return calc_watermark_data(state);
12083 }
12084
12085 static int intel_atomic_prepare_commit(struct drm_device *dev,
12086                                        struct drm_atomic_state *state)
12087 {
12088         return drm_atomic_helper_prepare_planes(dev, state);
12089 }
12090
12091 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12092 {
12093         struct drm_device *dev = crtc->base.dev;
12094
12095         if (!dev->max_vblank_count)
12096                 return drm_crtc_accurate_vblank_count(&crtc->base);
12097
12098         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12099 }
12100
12101 static void intel_update_crtc(struct drm_crtc *crtc,
12102                               struct drm_atomic_state *state,
12103                               struct drm_crtc_state *old_crtc_state,
12104                               struct drm_crtc_state *new_crtc_state)
12105 {
12106         struct drm_device *dev = crtc->dev;
12107         struct drm_i915_private *dev_priv = to_i915(dev);
12108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12109         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12110         bool modeset = needs_modeset(new_crtc_state);
12111
12112         if (modeset) {
12113                 update_scanline_offset(intel_crtc);
12114                 dev_priv->display.crtc_enable(pipe_config, state);
12115         } else {
12116                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12117                                        pipe_config);
12118         }
12119
12120         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12121                 intel_fbc_enable(
12122                     intel_crtc, pipe_config,
12123                     to_intel_plane_state(crtc->primary->state));
12124         }
12125
12126         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12127 }
12128
12129 static void intel_update_crtcs(struct drm_atomic_state *state)
12130 {
12131         struct drm_crtc *crtc;
12132         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12133         int i;
12134
12135         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12136                 if (!new_crtc_state->active)
12137                         continue;
12138
12139                 intel_update_crtc(crtc, state, old_crtc_state,
12140                                   new_crtc_state);
12141         }
12142 }
12143
12144 static void skl_update_crtcs(struct drm_atomic_state *state)
12145 {
12146         struct drm_i915_private *dev_priv = to_i915(state->dev);
12147         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12148         struct drm_crtc *crtc;
12149         struct intel_crtc *intel_crtc;
12150         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12151         struct intel_crtc_state *cstate;
12152         unsigned int updated = 0;
12153         bool progress;
12154         enum pipe pipe;
12155         int i;
12156
12157         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12158
12159         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12160                 /* ignore allocations for crtc's that have been turned off. */
12161                 if (new_crtc_state->active)
12162                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12163
12164         /*
12165          * Whenever the number of active pipes changes, we need to make sure we
12166          * update the pipes in the right order so that their ddb allocations
12167          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12168          * cause pipe underruns and other bad stuff.
12169          */
12170         do {
12171                 progress = false;
12172
12173                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12174                         bool vbl_wait = false;
12175                         unsigned int cmask = drm_crtc_mask(crtc);
12176
12177                         intel_crtc = to_intel_crtc(crtc);
12178                         cstate = to_intel_crtc_state(new_crtc_state);
12179                         pipe = intel_crtc->pipe;
12180
12181                         if (updated & cmask || !cstate->base.active)
12182                                 continue;
12183
12184                         if (skl_ddb_allocation_overlaps(dev_priv,
12185                                                         entries,
12186                                                         &cstate->wm.skl.ddb,
12187                                                         i))
12188                                 continue;
12189
12190                         updated |= cmask;
12191                         entries[i] = &cstate->wm.skl.ddb;
12192
12193                         /*
12194                          * If this is an already active pipe, it's DDB changed,
12195                          * and this isn't the last pipe that needs updating
12196                          * then we need to wait for a vblank to pass for the
12197                          * new ddb allocation to take effect.
12198                          */
12199                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12200                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12201                             !new_crtc_state->active_changed &&
12202                             intel_state->wm_results.dirty_pipes != updated)
12203                                 vbl_wait = true;
12204
12205                         intel_update_crtc(crtc, state, old_crtc_state,
12206                                           new_crtc_state);
12207
12208                         if (vbl_wait)
12209                                 intel_wait_for_vblank(dev_priv, pipe);
12210
12211                         progress = true;
12212                 }
12213         } while (progress);
12214 }
12215
12216 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12217 {
12218         struct intel_atomic_state *state, *next;
12219         struct llist_node *freed;
12220
12221         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12222         llist_for_each_entry_safe(state, next, freed, freed)
12223                 drm_atomic_state_put(&state->base);
12224 }
12225
12226 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12227 {
12228         struct drm_i915_private *dev_priv =
12229                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12230
12231         intel_atomic_helper_free_state(dev_priv);
12232 }
12233
12234 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12235 {
12236         struct wait_queue_entry wait_fence, wait_reset;
12237         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12238
12239         init_wait_entry(&wait_fence, 0);
12240         init_wait_entry(&wait_reset, 0);
12241         for (;;) {
12242                 prepare_to_wait(&intel_state->commit_ready.wait,
12243                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12244                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12245                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12246
12247
12248                 if (i915_sw_fence_done(&intel_state->commit_ready)
12249                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12250                         break;
12251
12252                 schedule();
12253         }
12254         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12255         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12256 }
12257
12258 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12259 {
12260         struct drm_device *dev = state->dev;
12261         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12262         struct drm_i915_private *dev_priv = to_i915(dev);
12263         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12264         struct drm_crtc *crtc;
12265         struct intel_crtc_state *intel_cstate;
12266         u64 put_domains[I915_MAX_PIPES] = {};
12267         int i;
12268
12269         intel_atomic_commit_fence_wait(intel_state);
12270
12271         drm_atomic_helper_wait_for_dependencies(state);
12272
12273         if (intel_state->modeset)
12274                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12275
12276         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12277                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12278
12279                 if (needs_modeset(new_crtc_state) ||
12280                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12281
12282                         put_domains[to_intel_crtc(crtc)->pipe] =
12283                                 modeset_get_crtc_power_domains(crtc,
12284                                         to_intel_crtc_state(new_crtc_state));
12285                 }
12286
12287                 if (!needs_modeset(new_crtc_state))
12288                         continue;
12289
12290                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12291                                        to_intel_crtc_state(new_crtc_state));
12292
12293                 if (old_crtc_state->active) {
12294                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12295                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12296                         intel_crtc->active = false;
12297                         intel_fbc_disable(intel_crtc);
12298                         intel_disable_shared_dpll(intel_crtc);
12299
12300                         /*
12301                          * Underruns don't always raise
12302                          * interrupts, so check manually.
12303                          */
12304                         intel_check_cpu_fifo_underruns(dev_priv);
12305                         intel_check_pch_fifo_underruns(dev_priv);
12306
12307                         if (!new_crtc_state->active) {
12308                                 /*
12309                                  * Make sure we don't call initial_watermarks
12310                                  * for ILK-style watermark updates.
12311                                  *
12312                                  * No clue what this is supposed to achieve.
12313                                  */
12314                                 if (INTEL_GEN(dev_priv) >= 9)
12315                                         dev_priv->display.initial_watermarks(intel_state,
12316                                                                              to_intel_crtc_state(new_crtc_state));
12317                         }
12318                 }
12319         }
12320
12321         /* Only after disabling all output pipelines that will be changed can we
12322          * update the the output configuration. */
12323         intel_modeset_update_crtc_state(state);
12324
12325         if (intel_state->modeset) {
12326                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12327
12328                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12329
12330                 /*
12331                  * SKL workaround: bspec recommends we disable the SAGV when we
12332                  * have more then one pipe enabled
12333                  */
12334                 if (!intel_can_enable_sagv(state))
12335                         intel_disable_sagv(dev_priv);
12336
12337                 intel_modeset_verify_disabled(dev, state);
12338         }
12339
12340         /* Complete the events for pipes that have now been disabled */
12341         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12342                 bool modeset = needs_modeset(new_crtc_state);
12343
12344                 /* Complete events for now disable pipes here. */
12345                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12346                         spin_lock_irq(&dev->event_lock);
12347                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12348                         spin_unlock_irq(&dev->event_lock);
12349
12350                         new_crtc_state->event = NULL;
12351                 }
12352         }
12353
12354         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12355         dev_priv->display.update_crtcs(state);
12356
12357         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12358          * already, but still need the state for the delayed optimization. To
12359          * fix this:
12360          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12361          * - schedule that vblank worker _before_ calling hw_done
12362          * - at the start of commit_tail, cancel it _synchrously
12363          * - switch over to the vblank wait helper in the core after that since
12364          *   we don't need out special handling any more.
12365          */
12366         drm_atomic_helper_wait_for_flip_done(dev, state);
12367
12368         /*
12369          * Now that the vblank has passed, we can go ahead and program the
12370          * optimal watermarks on platforms that need two-step watermark
12371          * programming.
12372          *
12373          * TODO: Move this (and other cleanup) to an async worker eventually.
12374          */
12375         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12376                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12377
12378                 if (dev_priv->display.optimize_watermarks)
12379                         dev_priv->display.optimize_watermarks(intel_state,
12380                                                               intel_cstate);
12381         }
12382
12383         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12384                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12385
12386                 if (put_domains[i])
12387                         modeset_put_power_domains(dev_priv, put_domains[i]);
12388
12389                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12390         }
12391
12392         if (intel_state->modeset && intel_can_enable_sagv(state))
12393                 intel_enable_sagv(dev_priv);
12394
12395         drm_atomic_helper_commit_hw_done(state);
12396
12397         if (intel_state->modeset) {
12398                 /* As one of the primary mmio accessors, KMS has a high
12399                  * likelihood of triggering bugs in unclaimed access. After we
12400                  * finish modesetting, see if an error has been flagged, and if
12401                  * so enable debugging for the next modeset - and hope we catch
12402                  * the culprit.
12403                  */
12404                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12405                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12406         }
12407
12408         drm_atomic_helper_cleanup_planes(dev, state);
12409
12410         drm_atomic_helper_commit_cleanup_done(state);
12411
12412         drm_atomic_state_put(state);
12413
12414         intel_atomic_helper_free_state(dev_priv);
12415 }
12416
12417 static void intel_atomic_commit_work(struct work_struct *work)
12418 {
12419         struct drm_atomic_state *state =
12420                 container_of(work, struct drm_atomic_state, commit_work);
12421
12422         intel_atomic_commit_tail(state);
12423 }
12424
12425 static int __i915_sw_fence_call
12426 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12427                           enum i915_sw_fence_notify notify)
12428 {
12429         struct intel_atomic_state *state =
12430                 container_of(fence, struct intel_atomic_state, commit_ready);
12431
12432         switch (notify) {
12433         case FENCE_COMPLETE:
12434                 /* we do blocking waits in the worker, nothing to do here */
12435                 break;
12436         case FENCE_FREE:
12437                 {
12438                         struct intel_atomic_helper *helper =
12439                                 &to_i915(state->base.dev)->atomic_helper;
12440
12441                         if (llist_add(&state->freed, &helper->free_list))
12442                                 schedule_work(&helper->free_work);
12443                         break;
12444                 }
12445         }
12446
12447         return NOTIFY_DONE;
12448 }
12449
12450 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12451 {
12452         struct drm_plane_state *old_plane_state, *new_plane_state;
12453         struct drm_plane *plane;
12454         int i;
12455
12456         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12457                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12458                                   intel_fb_obj(new_plane_state->fb),
12459                                   to_intel_plane(plane)->frontbuffer_bit);
12460 }
12461
12462 /**
12463  * intel_atomic_commit - commit validated state object
12464  * @dev: DRM device
12465  * @state: the top-level driver state object
12466  * @nonblock: nonblocking commit
12467  *
12468  * This function commits a top-level state object that has been validated
12469  * with drm_atomic_helper_check().
12470  *
12471  * RETURNS
12472  * Zero for success or -errno.
12473  */
12474 static int intel_atomic_commit(struct drm_device *dev,
12475                                struct drm_atomic_state *state,
12476                                bool nonblock)
12477 {
12478         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12479         struct drm_i915_private *dev_priv = to_i915(dev);
12480         int ret = 0;
12481
12482         drm_atomic_state_get(state);
12483         i915_sw_fence_init(&intel_state->commit_ready,
12484                            intel_atomic_commit_ready);
12485
12486         /*
12487          * The intel_legacy_cursor_update() fast path takes care
12488          * of avoiding the vblank waits for simple cursor
12489          * movement and flips. For cursor on/off and size changes,
12490          * we want to perform the vblank waits so that watermark
12491          * updates happen during the correct frames. Gen9+ have
12492          * double buffered watermarks and so shouldn't need this.
12493          *
12494          * Unset state->legacy_cursor_update before the call to
12495          * drm_atomic_helper_setup_commit() because otherwise
12496          * drm_atomic_helper_wait_for_flip_done() is a noop and
12497          * we get FIFO underruns because we didn't wait
12498          * for vblank.
12499          *
12500          * FIXME doing watermarks and fb cleanup from a vblank worker
12501          * (assuming we had any) would solve these problems.
12502          */
12503         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12504                 struct intel_crtc_state *new_crtc_state;
12505                 struct intel_crtc *crtc;
12506                 int i;
12507
12508                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12509                         if (new_crtc_state->wm.need_postvbl_update ||
12510                             new_crtc_state->update_wm_post)
12511                                 state->legacy_cursor_update = false;
12512         }
12513
12514         ret = intel_atomic_prepare_commit(dev, state);
12515         if (ret) {
12516                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12517                 i915_sw_fence_commit(&intel_state->commit_ready);
12518                 return ret;
12519         }
12520
12521         ret = drm_atomic_helper_setup_commit(state, nonblock);
12522         if (!ret)
12523                 ret = drm_atomic_helper_swap_state(state, true);
12524
12525         if (ret) {
12526                 i915_sw_fence_commit(&intel_state->commit_ready);
12527
12528                 drm_atomic_helper_cleanup_planes(dev, state);
12529                 return ret;
12530         }
12531         dev_priv->wm.distrust_bios_wm = false;
12532         intel_shared_dpll_swap_state(state);
12533         intel_atomic_track_fbs(state);
12534
12535         if (intel_state->modeset) {
12536                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12537                        sizeof(intel_state->min_cdclk));
12538                 dev_priv->active_crtcs = intel_state->active_crtcs;
12539                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12540                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12541         }
12542
12543         drm_atomic_state_get(state);
12544         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12545
12546         i915_sw_fence_commit(&intel_state->commit_ready);
12547         if (nonblock)
12548                 queue_work(system_unbound_wq, &state->commit_work);
12549         else
12550                 intel_atomic_commit_tail(state);
12551
12552
12553         return 0;
12554 }
12555
12556 static const struct drm_crtc_funcs intel_crtc_funcs = {
12557         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12558         .set_config = drm_atomic_helper_set_config,
12559         .destroy = intel_crtc_destroy,
12560         .page_flip = drm_atomic_helper_page_flip,
12561         .atomic_duplicate_state = intel_crtc_duplicate_state,
12562         .atomic_destroy_state = intel_crtc_destroy_state,
12563         .set_crc_source = intel_crtc_set_crc_source,
12564 };
12565
12566 struct wait_rps_boost {
12567         struct wait_queue_entry wait;
12568
12569         struct drm_crtc *crtc;
12570         struct drm_i915_gem_request *request;
12571 };
12572
12573 static int do_rps_boost(struct wait_queue_entry *_wait,
12574                         unsigned mode, int sync, void *key)
12575 {
12576         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12577         struct drm_i915_gem_request *rq = wait->request;
12578
12579         gen6_rps_boost(rq, NULL);
12580         i915_gem_request_put(rq);
12581
12582         drm_crtc_vblank_put(wait->crtc);
12583
12584         list_del(&wait->wait.entry);
12585         kfree(wait);
12586         return 1;
12587 }
12588
12589 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12590                                        struct dma_fence *fence)
12591 {
12592         struct wait_rps_boost *wait;
12593
12594         if (!dma_fence_is_i915(fence))
12595                 return;
12596
12597         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12598                 return;
12599
12600         if (drm_crtc_vblank_get(crtc))
12601                 return;
12602
12603         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12604         if (!wait) {
12605                 drm_crtc_vblank_put(crtc);
12606                 return;
12607         }
12608
12609         wait->request = to_request(dma_fence_get(fence));
12610         wait->crtc = crtc;
12611
12612         wait->wait.func = do_rps_boost;
12613         wait->wait.flags = 0;
12614
12615         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12616 }
12617
12618 /**
12619  * intel_prepare_plane_fb - Prepare fb for usage on plane
12620  * @plane: drm plane to prepare for
12621  * @fb: framebuffer to prepare for presentation
12622  *
12623  * Prepares a framebuffer for usage on a display plane.  Generally this
12624  * involves pinning the underlying object and updating the frontbuffer tracking
12625  * bits.  Some older platforms need special physical address handling for
12626  * cursor planes.
12627  *
12628  * Must be called with struct_mutex held.
12629  *
12630  * Returns 0 on success, negative error code on failure.
12631  */
12632 int
12633 intel_prepare_plane_fb(struct drm_plane *plane,
12634                        struct drm_plane_state *new_state)
12635 {
12636         struct intel_atomic_state *intel_state =
12637                 to_intel_atomic_state(new_state->state);
12638         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12639         struct drm_framebuffer *fb = new_state->fb;
12640         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12641         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12642         int ret;
12643
12644         if (old_obj) {
12645                 struct drm_crtc_state *crtc_state =
12646                         drm_atomic_get_existing_crtc_state(new_state->state,
12647                                                            plane->state->crtc);
12648
12649                 /* Big Hammer, we also need to ensure that any pending
12650                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12651                  * current scanout is retired before unpinning the old
12652                  * framebuffer. Note that we rely on userspace rendering
12653                  * into the buffer attached to the pipe they are waiting
12654                  * on. If not, userspace generates a GPU hang with IPEHR
12655                  * point to the MI_WAIT_FOR_EVENT.
12656                  *
12657                  * This should only fail upon a hung GPU, in which case we
12658                  * can safely continue.
12659                  */
12660                 if (needs_modeset(crtc_state)) {
12661                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12662                                                               old_obj->resv, NULL,
12663                                                               false, 0,
12664                                                               GFP_KERNEL);
12665                         if (ret < 0)
12666                                 return ret;
12667                 }
12668         }
12669
12670         if (new_state->fence) { /* explicit fencing */
12671                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12672                                                     new_state->fence,
12673                                                     I915_FENCE_TIMEOUT,
12674                                                     GFP_KERNEL);
12675                 if (ret < 0)
12676                         return ret;
12677         }
12678
12679         if (!obj)
12680                 return 0;
12681
12682         ret = i915_gem_object_pin_pages(obj);
12683         if (ret)
12684                 return ret;
12685
12686         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12687         if (ret) {
12688                 i915_gem_object_unpin_pages(obj);
12689                 return ret;
12690         }
12691
12692         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12693             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12694                 const int align = intel_cursor_alignment(dev_priv);
12695
12696                 ret = i915_gem_object_attach_phys(obj, align);
12697         } else {
12698                 struct i915_vma *vma;
12699
12700                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12701                 if (!IS_ERR(vma))
12702                         to_intel_plane_state(new_state)->vma = vma;
12703                 else
12704                         ret =  PTR_ERR(vma);
12705         }
12706
12707         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12708
12709         mutex_unlock(&dev_priv->drm.struct_mutex);
12710         i915_gem_object_unpin_pages(obj);
12711         if (ret)
12712                 return ret;
12713
12714         if (!new_state->fence) { /* implicit fencing */
12715                 struct dma_fence *fence;
12716
12717                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12718                                                       obj->resv, NULL,
12719                                                       false, I915_FENCE_TIMEOUT,
12720                                                       GFP_KERNEL);
12721                 if (ret < 0)
12722                         return ret;
12723
12724                 fence = reservation_object_get_excl_rcu(obj->resv);
12725                 if (fence) {
12726                         add_rps_boost_after_vblank(new_state->crtc, fence);
12727                         dma_fence_put(fence);
12728                 }
12729         } else {
12730                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12731         }
12732
12733         return 0;
12734 }
12735
12736 /**
12737  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12738  * @plane: drm plane to clean up for
12739  * @fb: old framebuffer that was on plane
12740  *
12741  * Cleans up a framebuffer that has just been removed from a plane.
12742  *
12743  * Must be called with struct_mutex held.
12744  */
12745 void
12746 intel_cleanup_plane_fb(struct drm_plane *plane,
12747                        struct drm_plane_state *old_state)
12748 {
12749         struct i915_vma *vma;
12750
12751         /* Should only be called after a successful intel_prepare_plane_fb()! */
12752         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12753         if (vma) {
12754                 mutex_lock(&plane->dev->struct_mutex);
12755                 intel_unpin_fb_vma(vma);
12756                 mutex_unlock(&plane->dev->struct_mutex);
12757         }
12758 }
12759
12760 int
12761 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12762 {
12763         struct drm_i915_private *dev_priv;
12764         int max_scale;
12765         int crtc_clock, max_dotclk;
12766
12767         if (!intel_crtc || !crtc_state->base.enable)
12768                 return DRM_PLANE_HELPER_NO_SCALING;
12769
12770         dev_priv = to_i915(intel_crtc->base.dev);
12771
12772         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12773         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12774
12775         if (IS_GEMINILAKE(dev_priv))
12776                 max_dotclk *= 2;
12777
12778         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12779                 return DRM_PLANE_HELPER_NO_SCALING;
12780
12781         /*
12782          * skl max scale is lower of:
12783          *    close to 3 but not 3, -1 is for that purpose
12784          *            or
12785          *    cdclk/crtc_clock
12786          */
12787         max_scale = min((1 << 16) * 3 - 1,
12788                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12789
12790         return max_scale;
12791 }
12792
12793 static int
12794 intel_check_primary_plane(struct intel_plane *plane,
12795                           struct intel_crtc_state *crtc_state,
12796                           struct intel_plane_state *state)
12797 {
12798         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12799         struct drm_crtc *crtc = state->base.crtc;
12800         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12801         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12802         bool can_position = false;
12803         int ret;
12804
12805         if (INTEL_GEN(dev_priv) >= 9) {
12806                 /* use scaler when colorkey is not required */
12807                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12808                         min_scale = 1;
12809                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12810                 }
12811                 can_position = true;
12812         }
12813
12814         ret = drm_plane_helper_check_state(&state->base,
12815                                            &state->clip,
12816                                            min_scale, max_scale,
12817                                            can_position, true);
12818         if (ret)
12819                 return ret;
12820
12821         if (!state->base.fb)
12822                 return 0;
12823
12824         if (INTEL_GEN(dev_priv) >= 9) {
12825                 ret = skl_check_plane_surface(state);
12826                 if (ret)
12827                         return ret;
12828
12829                 state->ctl = skl_plane_ctl(crtc_state, state);
12830         } else {
12831                 ret = i9xx_check_plane_surface(state);
12832                 if (ret)
12833                         return ret;
12834
12835                 state->ctl = i9xx_plane_ctl(crtc_state, state);
12836         }
12837
12838         return 0;
12839 }
12840
12841 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12842                                     struct drm_crtc_state *old_crtc_state)
12843 {
12844         struct drm_device *dev = crtc->dev;
12845         struct drm_i915_private *dev_priv = to_i915(dev);
12846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12847         struct intel_crtc_state *old_intel_cstate =
12848                 to_intel_crtc_state(old_crtc_state);
12849         struct intel_atomic_state *old_intel_state =
12850                 to_intel_atomic_state(old_crtc_state->state);
12851         struct intel_crtc_state *intel_cstate =
12852                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12853         bool modeset = needs_modeset(&intel_cstate->base);
12854
12855         if (!modeset &&
12856             (intel_cstate->base.color_mgmt_changed ||
12857              intel_cstate->update_pipe)) {
12858                 intel_color_set_csc(&intel_cstate->base);
12859                 intel_color_load_luts(&intel_cstate->base);
12860         }
12861
12862         /* Perform vblank evasion around commit operation */
12863         intel_pipe_update_start(intel_cstate);
12864
12865         if (modeset)
12866                 goto out;
12867
12868         if (intel_cstate->update_pipe)
12869                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12870         else if (INTEL_GEN(dev_priv) >= 9)
12871                 skl_detach_scalers(intel_crtc);
12872
12873 out:
12874         if (dev_priv->display.atomic_update_watermarks)
12875                 dev_priv->display.atomic_update_watermarks(old_intel_state,
12876                                                            intel_cstate);
12877 }
12878
12879 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12880                                      struct drm_crtc_state *old_crtc_state)
12881 {
12882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12883         struct intel_atomic_state *old_intel_state =
12884                 to_intel_atomic_state(old_crtc_state->state);
12885         struct intel_crtc_state *new_crtc_state =
12886                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12887
12888         intel_pipe_update_end(new_crtc_state);
12889 }
12890
12891 /**
12892  * intel_plane_destroy - destroy a plane
12893  * @plane: plane to destroy
12894  *
12895  * Common destruction function for all types of planes (primary, cursor,
12896  * sprite).
12897  */
12898 void intel_plane_destroy(struct drm_plane *plane)
12899 {
12900         drm_plane_cleanup(plane);
12901         kfree(to_intel_plane(plane));
12902 }
12903
12904 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12905 {
12906         switch (format) {
12907         case DRM_FORMAT_C8:
12908         case DRM_FORMAT_RGB565:
12909         case DRM_FORMAT_XRGB1555:
12910         case DRM_FORMAT_XRGB8888:
12911                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12912                         modifier == I915_FORMAT_MOD_X_TILED;
12913         default:
12914                 return false;
12915         }
12916 }
12917
12918 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12919 {
12920         switch (format) {
12921         case DRM_FORMAT_C8:
12922         case DRM_FORMAT_RGB565:
12923         case DRM_FORMAT_XRGB8888:
12924         case DRM_FORMAT_XBGR8888:
12925         case DRM_FORMAT_XRGB2101010:
12926         case DRM_FORMAT_XBGR2101010:
12927                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12928                         modifier == I915_FORMAT_MOD_X_TILED;
12929         default:
12930                 return false;
12931         }
12932 }
12933
12934 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12935 {
12936         switch (format) {
12937         case DRM_FORMAT_XRGB8888:
12938         case DRM_FORMAT_XBGR8888:
12939         case DRM_FORMAT_ARGB8888:
12940         case DRM_FORMAT_ABGR8888:
12941                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12942                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12943                         return true;
12944                 /* fall through */
12945         case DRM_FORMAT_RGB565:
12946         case DRM_FORMAT_XRGB2101010:
12947         case DRM_FORMAT_XBGR2101010:
12948         case DRM_FORMAT_YUYV:
12949         case DRM_FORMAT_YVYU:
12950         case DRM_FORMAT_UYVY:
12951         case DRM_FORMAT_VYUY:
12952                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12953                         return true;
12954                 /* fall through */
12955         case DRM_FORMAT_C8:
12956                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12957                     modifier == I915_FORMAT_MOD_X_TILED ||
12958                     modifier == I915_FORMAT_MOD_Y_TILED)
12959                         return true;
12960                 /* fall through */
12961         default:
12962                 return false;
12963         }
12964 }
12965
12966 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12967                                                      uint32_t format,
12968                                                      uint64_t modifier)
12969 {
12970         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12971
12972         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12973                 return false;
12974
12975         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
12976             modifier != DRM_FORMAT_MOD_LINEAR)
12977                 return false;
12978
12979         if (INTEL_GEN(dev_priv) >= 9)
12980                 return skl_mod_supported(format, modifier);
12981         else if (INTEL_GEN(dev_priv) >= 4)
12982                 return i965_mod_supported(format, modifier);
12983         else
12984                 return i8xx_mod_supported(format, modifier);
12985
12986         unreachable();
12987 }
12988
12989 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
12990                                                     uint32_t format,
12991                                                     uint64_t modifier)
12992 {
12993         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12994                 return false;
12995
12996         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
12997 }
12998
12999 static struct drm_plane_funcs intel_plane_funcs = {
13000         .update_plane = drm_atomic_helper_update_plane,
13001         .disable_plane = drm_atomic_helper_disable_plane,
13002         .destroy = intel_plane_destroy,
13003         .atomic_get_property = intel_plane_atomic_get_property,
13004         .atomic_set_property = intel_plane_atomic_set_property,
13005         .atomic_duplicate_state = intel_plane_duplicate_state,
13006         .atomic_destroy_state = intel_plane_destroy_state,
13007         .format_mod_supported = intel_primary_plane_format_mod_supported,
13008 };
13009
13010 static int
13011 intel_legacy_cursor_update(struct drm_plane *plane,
13012                            struct drm_crtc *crtc,
13013                            struct drm_framebuffer *fb,
13014                            int crtc_x, int crtc_y,
13015                            unsigned int crtc_w, unsigned int crtc_h,
13016                            uint32_t src_x, uint32_t src_y,
13017                            uint32_t src_w, uint32_t src_h,
13018                            struct drm_modeset_acquire_ctx *ctx)
13019 {
13020         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13021         int ret;
13022         struct drm_plane_state *old_plane_state, *new_plane_state;
13023         struct intel_plane *intel_plane = to_intel_plane(plane);
13024         struct drm_framebuffer *old_fb;
13025         struct drm_crtc_state *crtc_state = crtc->state;
13026         struct i915_vma *old_vma, *vma;
13027
13028         /*
13029          * When crtc is inactive or there is a modeset pending,
13030          * wait for it to complete in the slowpath
13031          */
13032         if (!crtc_state->active || needs_modeset(crtc_state) ||
13033             to_intel_crtc_state(crtc_state)->update_pipe)
13034                 goto slow;
13035
13036         old_plane_state = plane->state;
13037         /*
13038          * Don't do an async update if there is an outstanding commit modifying
13039          * the plane.  This prevents our async update's changes from getting
13040          * overridden by a previous synchronous update's state.
13041          */
13042         if (old_plane_state->commit &&
13043             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13044                 goto slow;
13045
13046         /*
13047          * If any parameters change that may affect watermarks,
13048          * take the slowpath. Only changing fb or position should be
13049          * in the fastpath.
13050          */
13051         if (old_plane_state->crtc != crtc ||
13052             old_plane_state->src_w != src_w ||
13053             old_plane_state->src_h != src_h ||
13054             old_plane_state->crtc_w != crtc_w ||
13055             old_plane_state->crtc_h != crtc_h ||
13056             !old_plane_state->fb != !fb)
13057                 goto slow;
13058
13059         new_plane_state = intel_plane_duplicate_state(plane);
13060         if (!new_plane_state)
13061                 return -ENOMEM;
13062
13063         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13064
13065         new_plane_state->src_x = src_x;
13066         new_plane_state->src_y = src_y;
13067         new_plane_state->src_w = src_w;
13068         new_plane_state->src_h = src_h;
13069         new_plane_state->crtc_x = crtc_x;
13070         new_plane_state->crtc_y = crtc_y;
13071         new_plane_state->crtc_w = crtc_w;
13072         new_plane_state->crtc_h = crtc_h;
13073
13074         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13075                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13076                                                   to_intel_plane_state(plane->state),
13077                                                   to_intel_plane_state(new_plane_state));
13078         if (ret)
13079                 goto out_free;
13080
13081         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13082         if (ret)
13083                 goto out_free;
13084
13085         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13086                 int align = intel_cursor_alignment(dev_priv);
13087
13088                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13089                 if (ret) {
13090                         DRM_DEBUG_KMS("failed to attach phys object\n");
13091                         goto out_unlock;
13092                 }
13093         } else {
13094                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13095                 if (IS_ERR(vma)) {
13096                         DRM_DEBUG_KMS("failed to pin object\n");
13097
13098                         ret = PTR_ERR(vma);
13099                         goto out_unlock;
13100                 }
13101
13102                 to_intel_plane_state(new_plane_state)->vma = vma;
13103         }
13104
13105         old_fb = old_plane_state->fb;
13106
13107         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13108                           intel_plane->frontbuffer_bit);
13109
13110         /* Swap plane state */
13111         plane->state = new_plane_state;
13112
13113         if (plane->state->visible) {
13114                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13115                 intel_plane->update_plane(intel_plane,
13116                                           to_intel_crtc_state(crtc->state),
13117                                           to_intel_plane_state(plane->state));
13118         } else {
13119                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13120                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13121         }
13122
13123         old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13124         if (old_vma)
13125                 intel_unpin_fb_vma(old_vma);
13126
13127 out_unlock:
13128         mutex_unlock(&dev_priv->drm.struct_mutex);
13129 out_free:
13130         if (ret)
13131                 intel_plane_destroy_state(plane, new_plane_state);
13132         else
13133                 intel_plane_destroy_state(plane, old_plane_state);
13134         return ret;
13135
13136 slow:
13137         return drm_atomic_helper_update_plane(plane, crtc, fb,
13138                                               crtc_x, crtc_y, crtc_w, crtc_h,
13139                                               src_x, src_y, src_w, src_h, ctx);
13140 }
13141
13142 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13143         .update_plane = intel_legacy_cursor_update,
13144         .disable_plane = drm_atomic_helper_disable_plane,
13145         .destroy = intel_plane_destroy,
13146         .atomic_get_property = intel_plane_atomic_get_property,
13147         .atomic_set_property = intel_plane_atomic_set_property,
13148         .atomic_duplicate_state = intel_plane_duplicate_state,
13149         .atomic_destroy_state = intel_plane_destroy_state,
13150         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13151 };
13152
13153 static struct intel_plane *
13154 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13155 {
13156         struct intel_plane *primary = NULL;
13157         struct intel_plane_state *state = NULL;
13158         const uint32_t *intel_primary_formats;
13159         unsigned int supported_rotations;
13160         unsigned int num_formats;
13161         const uint64_t *modifiers;
13162         int ret;
13163
13164         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13165         if (!primary) {
13166                 ret = -ENOMEM;
13167                 goto fail;
13168         }
13169
13170         state = intel_create_plane_state(&primary->base);
13171         if (!state) {
13172                 ret = -ENOMEM;
13173                 goto fail;
13174         }
13175
13176         primary->base.state = &state->base;
13177
13178         primary->can_scale = false;
13179         primary->max_downscale = 1;
13180         if (INTEL_GEN(dev_priv) >= 9) {
13181                 primary->can_scale = true;
13182                 state->scaler_id = -1;
13183         }
13184         primary->pipe = pipe;
13185         /*
13186          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13187          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13188          */
13189         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13190                 primary->plane = (enum plane) !pipe;
13191         else
13192                 primary->plane = (enum plane) pipe;
13193         primary->id = PLANE_PRIMARY;
13194         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13195         primary->check_plane = intel_check_primary_plane;
13196
13197         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13198                 intel_primary_formats = skl_primary_formats;
13199                 num_formats = ARRAY_SIZE(skl_primary_formats);
13200                 modifiers = skl_format_modifiers_ccs;
13201
13202                 primary->update_plane = skl_update_plane;
13203                 primary->disable_plane = skl_disable_plane;
13204         } else if (INTEL_GEN(dev_priv) >= 9) {
13205                 intel_primary_formats = skl_primary_formats;
13206                 num_formats = ARRAY_SIZE(skl_primary_formats);
13207                 if (pipe < PIPE_C)
13208                         modifiers = skl_format_modifiers_ccs;
13209                 else
13210                         modifiers = skl_format_modifiers_noccs;
13211
13212                 primary->update_plane = skl_update_plane;
13213                 primary->disable_plane = skl_disable_plane;
13214         } else if (INTEL_GEN(dev_priv) >= 4) {
13215                 intel_primary_formats = i965_primary_formats;
13216                 num_formats = ARRAY_SIZE(i965_primary_formats);
13217                 modifiers = i9xx_format_modifiers;
13218
13219                 primary->update_plane = i9xx_update_primary_plane;
13220                 primary->disable_plane = i9xx_disable_primary_plane;
13221         } else {
13222                 intel_primary_formats = i8xx_primary_formats;
13223                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13224                 modifiers = i9xx_format_modifiers;
13225
13226                 primary->update_plane = i9xx_update_primary_plane;
13227                 primary->disable_plane = i9xx_disable_primary_plane;
13228         }
13229
13230         if (INTEL_GEN(dev_priv) >= 9)
13231                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13232                                                0, &intel_plane_funcs,
13233                                                intel_primary_formats, num_formats,
13234                                                modifiers,
13235                                                DRM_PLANE_TYPE_PRIMARY,
13236                                                "plane 1%c", pipe_name(pipe));
13237         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13238                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13239                                                0, &intel_plane_funcs,
13240                                                intel_primary_formats, num_formats,
13241                                                modifiers,
13242                                                DRM_PLANE_TYPE_PRIMARY,
13243                                                "primary %c", pipe_name(pipe));
13244         else
13245                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13246                                                0, &intel_plane_funcs,
13247                                                intel_primary_formats, num_formats,
13248                                                modifiers,
13249                                                DRM_PLANE_TYPE_PRIMARY,
13250                                                "plane %c", plane_name(primary->plane));
13251         if (ret)
13252                 goto fail;
13253
13254         if (INTEL_GEN(dev_priv) >= 9) {
13255                 supported_rotations =
13256                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13257                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13258         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13259                 supported_rotations =
13260                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13261                         DRM_MODE_REFLECT_X;
13262         } else if (INTEL_GEN(dev_priv) >= 4) {
13263                 supported_rotations =
13264                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13265         } else {
13266                 supported_rotations = DRM_MODE_ROTATE_0;
13267         }
13268
13269         if (INTEL_GEN(dev_priv) >= 4)
13270                 drm_plane_create_rotation_property(&primary->base,
13271                                                    DRM_MODE_ROTATE_0,
13272                                                    supported_rotations);
13273
13274         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13275
13276         return primary;
13277
13278 fail:
13279         kfree(state);
13280         kfree(primary);
13281
13282         return ERR_PTR(ret);
13283 }
13284
13285 static struct intel_plane *
13286 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13287                           enum pipe pipe)
13288 {
13289         struct intel_plane *cursor = NULL;
13290         struct intel_plane_state *state = NULL;
13291         int ret;
13292
13293         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13294         if (!cursor) {
13295                 ret = -ENOMEM;
13296                 goto fail;
13297         }
13298
13299         state = intel_create_plane_state(&cursor->base);
13300         if (!state) {
13301                 ret = -ENOMEM;
13302                 goto fail;
13303         }
13304
13305         cursor->base.state = &state->base;
13306
13307         cursor->can_scale = false;
13308         cursor->max_downscale = 1;
13309         cursor->pipe = pipe;
13310         cursor->plane = pipe;
13311         cursor->id = PLANE_CURSOR;
13312         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13313
13314         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13315                 cursor->update_plane = i845_update_cursor;
13316                 cursor->disable_plane = i845_disable_cursor;
13317                 cursor->check_plane = i845_check_cursor;
13318         } else {
13319                 cursor->update_plane = i9xx_update_cursor;
13320                 cursor->disable_plane = i9xx_disable_cursor;
13321                 cursor->check_plane = i9xx_check_cursor;
13322         }
13323
13324         cursor->cursor.base = ~0;
13325         cursor->cursor.cntl = ~0;
13326
13327         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13328                 cursor->cursor.size = ~0;
13329
13330         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13331                                        0, &intel_cursor_plane_funcs,
13332                                        intel_cursor_formats,
13333                                        ARRAY_SIZE(intel_cursor_formats),
13334                                        cursor_format_modifiers,
13335                                        DRM_PLANE_TYPE_CURSOR,
13336                                        "cursor %c", pipe_name(pipe));
13337         if (ret)
13338                 goto fail;
13339
13340         if (INTEL_GEN(dev_priv) >= 4)
13341                 drm_plane_create_rotation_property(&cursor->base,
13342                                                    DRM_MODE_ROTATE_0,
13343                                                    DRM_MODE_ROTATE_0 |
13344                                                    DRM_MODE_ROTATE_180);
13345
13346         if (INTEL_GEN(dev_priv) >= 9)
13347                 state->scaler_id = -1;
13348
13349         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13350
13351         return cursor;
13352
13353 fail:
13354         kfree(state);
13355         kfree(cursor);
13356
13357         return ERR_PTR(ret);
13358 }
13359
13360 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13361                                     struct intel_crtc_state *crtc_state)
13362 {
13363         struct intel_crtc_scaler_state *scaler_state =
13364                 &crtc_state->scaler_state;
13365         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13366         int i;
13367
13368         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13369         if (!crtc->num_scalers)
13370                 return;
13371
13372         for (i = 0; i < crtc->num_scalers; i++) {
13373                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13374
13375                 scaler->in_use = 0;
13376                 scaler->mode = PS_SCALER_MODE_DYN;
13377         }
13378
13379         scaler_state->scaler_id = -1;
13380 }
13381
13382 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13383 {
13384         struct intel_crtc *intel_crtc;
13385         struct intel_crtc_state *crtc_state = NULL;
13386         struct intel_plane *primary = NULL;
13387         struct intel_plane *cursor = NULL;
13388         int sprite, ret;
13389
13390         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13391         if (!intel_crtc)
13392                 return -ENOMEM;
13393
13394         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13395         if (!crtc_state) {
13396                 ret = -ENOMEM;
13397                 goto fail;
13398         }
13399         intel_crtc->config = crtc_state;
13400         intel_crtc->base.state = &crtc_state->base;
13401         crtc_state->base.crtc = &intel_crtc->base;
13402
13403         primary = intel_primary_plane_create(dev_priv, pipe);
13404         if (IS_ERR(primary)) {
13405                 ret = PTR_ERR(primary);
13406                 goto fail;
13407         }
13408         intel_crtc->plane_ids_mask |= BIT(primary->id);
13409
13410         for_each_sprite(dev_priv, pipe, sprite) {
13411                 struct intel_plane *plane;
13412
13413                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13414                 if (IS_ERR(plane)) {
13415                         ret = PTR_ERR(plane);
13416                         goto fail;
13417                 }
13418                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13419         }
13420
13421         cursor = intel_cursor_plane_create(dev_priv, pipe);
13422         if (IS_ERR(cursor)) {
13423                 ret = PTR_ERR(cursor);
13424                 goto fail;
13425         }
13426         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13427
13428         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13429                                         &primary->base, &cursor->base,
13430                                         &intel_crtc_funcs,
13431                                         "pipe %c", pipe_name(pipe));
13432         if (ret)
13433                 goto fail;
13434
13435         intel_crtc->pipe = pipe;
13436         intel_crtc->plane = primary->plane;
13437
13438         /* initialize shared scalers */
13439         intel_crtc_init_scalers(intel_crtc, crtc_state);
13440
13441         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13442                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13443         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13444         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13445
13446         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13447
13448         intel_color_init(&intel_crtc->base);
13449
13450         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13451
13452         return 0;
13453
13454 fail:
13455         /*
13456          * drm_mode_config_cleanup() will free up any
13457          * crtcs/planes already initialized.
13458          */
13459         kfree(crtc_state);
13460         kfree(intel_crtc);
13461
13462         return ret;
13463 }
13464
13465 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13466 {
13467         struct drm_device *dev = connector->base.dev;
13468
13469         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13470
13471         if (!connector->base.state->crtc)
13472                 return INVALID_PIPE;
13473
13474         return to_intel_crtc(connector->base.state->crtc)->pipe;
13475 }
13476
13477 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13478                                 struct drm_file *file)
13479 {
13480         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13481         struct drm_crtc *drmmode_crtc;
13482         struct intel_crtc *crtc;
13483
13484         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13485         if (!drmmode_crtc)
13486                 return -ENOENT;
13487
13488         crtc = to_intel_crtc(drmmode_crtc);
13489         pipe_from_crtc_id->pipe = crtc->pipe;
13490
13491         return 0;
13492 }
13493
13494 static int intel_encoder_clones(struct intel_encoder *encoder)
13495 {
13496         struct drm_device *dev = encoder->base.dev;
13497         struct intel_encoder *source_encoder;
13498         int index_mask = 0;
13499         int entry = 0;
13500
13501         for_each_intel_encoder(dev, source_encoder) {
13502                 if (encoders_cloneable(encoder, source_encoder))
13503                         index_mask |= (1 << entry);
13504
13505                 entry++;
13506         }
13507
13508         return index_mask;
13509 }
13510
13511 static bool has_edp_a(struct drm_i915_private *dev_priv)
13512 {
13513         if (!IS_MOBILE(dev_priv))
13514                 return false;
13515
13516         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13517                 return false;
13518
13519         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13520                 return false;
13521
13522         return true;
13523 }
13524
13525 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13526 {
13527         if (INTEL_GEN(dev_priv) >= 9)
13528                 return false;
13529
13530         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13531                 return false;
13532
13533         if (IS_CHERRYVIEW(dev_priv))
13534                 return false;
13535
13536         if (HAS_PCH_LPT_H(dev_priv) &&
13537             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13538                 return false;
13539
13540         /* DDI E can't be used if DDI A requires 4 lanes */
13541         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13542                 return false;
13543
13544         if (!dev_priv->vbt.int_crt_support)
13545                 return false;
13546
13547         return true;
13548 }
13549
13550 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13551 {
13552         int pps_num;
13553         int pps_idx;
13554
13555         if (HAS_DDI(dev_priv))
13556                 return;
13557         /*
13558          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13559          * everywhere where registers can be write protected.
13560          */
13561         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13562                 pps_num = 2;
13563         else
13564                 pps_num = 1;
13565
13566         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13567                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13568
13569                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13570                 I915_WRITE(PP_CONTROL(pps_idx), val);
13571         }
13572 }
13573
13574 static void intel_pps_init(struct drm_i915_private *dev_priv)
13575 {
13576         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13577                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13578         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13579                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13580         else
13581                 dev_priv->pps_mmio_base = PPS_BASE;
13582
13583         intel_pps_unlock_regs_wa(dev_priv);
13584 }
13585
13586 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13587 {
13588         struct intel_encoder *encoder;
13589         bool dpd_is_edp = false;
13590
13591         intel_pps_init(dev_priv);
13592
13593         /*
13594          * intel_edp_init_connector() depends on this completing first, to
13595          * prevent the registeration of both eDP and LVDS and the incorrect
13596          * sharing of the PPS.
13597          */
13598         intel_lvds_init(dev_priv);
13599
13600         if (intel_crt_present(dev_priv))
13601                 intel_crt_init(dev_priv);
13602
13603         if (IS_GEN9_LP(dev_priv)) {
13604                 /*
13605                  * FIXME: Broxton doesn't support port detection via the
13606                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13607                  * detect the ports.
13608                  */
13609                 intel_ddi_init(dev_priv, PORT_A);
13610                 intel_ddi_init(dev_priv, PORT_B);
13611                 intel_ddi_init(dev_priv, PORT_C);
13612
13613                 intel_dsi_init(dev_priv);
13614         } else if (HAS_DDI(dev_priv)) {
13615                 int found;
13616
13617                 /*
13618                  * Haswell uses DDI functions to detect digital outputs.
13619                  * On SKL pre-D0 the strap isn't connected, so we assume
13620                  * it's there.
13621                  */
13622                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13623                 /* WaIgnoreDDIAStrap: skl */
13624                 if (found || IS_GEN9_BC(dev_priv))
13625                         intel_ddi_init(dev_priv, PORT_A);
13626
13627                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13628                  * register */
13629                 found = I915_READ(SFUSE_STRAP);
13630
13631                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13632                         intel_ddi_init(dev_priv, PORT_B);
13633                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13634                         intel_ddi_init(dev_priv, PORT_C);
13635                 if (found & SFUSE_STRAP_DDID_DETECTED)
13636                         intel_ddi_init(dev_priv, PORT_D);
13637                 /*
13638                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13639                  */
13640                 if (IS_GEN9_BC(dev_priv) &&
13641                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13642                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13643                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13644                         intel_ddi_init(dev_priv, PORT_E);
13645
13646         } else if (HAS_PCH_SPLIT(dev_priv)) {
13647                 int found;
13648                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13649
13650                 if (has_edp_a(dev_priv))
13651                         intel_dp_init(dev_priv, DP_A, PORT_A);
13652
13653                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13654                         /* PCH SDVOB multiplex with HDMIB */
13655                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13656                         if (!found)
13657                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13658                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13659                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13660                 }
13661
13662                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13663                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13664
13665                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13666                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13667
13668                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13669                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13670
13671                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13672                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13673         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13674                 bool has_edp, has_port;
13675
13676                 /*
13677                  * The DP_DETECTED bit is the latched state of the DDC
13678                  * SDA pin at boot. However since eDP doesn't require DDC
13679                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13680                  * eDP ports may have been muxed to an alternate function.
13681                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13682                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13683                  * detect eDP ports.
13684                  *
13685                  * Sadly the straps seem to be missing sometimes even for HDMI
13686                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13687                  * and VBT for the presence of the port. Additionally we can't
13688                  * trust the port type the VBT declares as we've seen at least
13689                  * HDMI ports that the VBT claim are DP or eDP.
13690                  */
13691                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13692                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13693                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13694                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13695                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13696                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13697
13698                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13699                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13700                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13701                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13702                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13703                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13704
13705                 if (IS_CHERRYVIEW(dev_priv)) {
13706                         /*
13707                          * eDP not supported on port D,
13708                          * so no need to worry about it
13709                          */
13710                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13711                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13712                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13713                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13714                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13715                 }
13716
13717                 intel_dsi_init(dev_priv);
13718         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13719                 bool found = false;
13720
13721                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13722                         DRM_DEBUG_KMS("probing SDVOB\n");
13723                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13724                         if (!found && IS_G4X(dev_priv)) {
13725                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13726                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13727                         }
13728
13729                         if (!found && IS_G4X(dev_priv))
13730                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13731                 }
13732
13733                 /* Before G4X SDVOC doesn't have its own detect register */
13734
13735                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13736                         DRM_DEBUG_KMS("probing SDVOC\n");
13737                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13738                 }
13739
13740                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13741
13742                         if (IS_G4X(dev_priv)) {
13743                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13744                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13745                         }
13746                         if (IS_G4X(dev_priv))
13747                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13748                 }
13749
13750                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13751                         intel_dp_init(dev_priv, DP_D, PORT_D);
13752         } else if (IS_GEN2(dev_priv))
13753                 intel_dvo_init(dev_priv);
13754
13755         if (SUPPORTS_TV(dev_priv))
13756                 intel_tv_init(dev_priv);
13757
13758         intel_psr_init(dev_priv);
13759
13760         for_each_intel_encoder(&dev_priv->drm, encoder) {
13761                 encoder->base.possible_crtcs = encoder->crtc_mask;
13762                 encoder->base.possible_clones =
13763                         intel_encoder_clones(encoder);
13764         }
13765
13766         intel_init_pch_refclk(dev_priv);
13767
13768         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13769 }
13770
13771 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13772 {
13773         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13774
13775         drm_framebuffer_cleanup(fb);
13776
13777         i915_gem_object_lock(intel_fb->obj);
13778         WARN_ON(!intel_fb->obj->framebuffer_references--);
13779         i915_gem_object_unlock(intel_fb->obj);
13780
13781         i915_gem_object_put(intel_fb->obj);
13782
13783         kfree(intel_fb);
13784 }
13785
13786 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13787                                                 struct drm_file *file,
13788                                                 unsigned int *handle)
13789 {
13790         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13791         struct drm_i915_gem_object *obj = intel_fb->obj;
13792
13793         if (obj->userptr.mm) {
13794                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13795                 return -EINVAL;
13796         }
13797
13798         return drm_gem_handle_create(file, &obj->base, handle);
13799 }
13800
13801 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13802                                         struct drm_file *file,
13803                                         unsigned flags, unsigned color,
13804                                         struct drm_clip_rect *clips,
13805                                         unsigned num_clips)
13806 {
13807         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13808
13809         i915_gem_object_flush_if_display(obj);
13810         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13811
13812         return 0;
13813 }
13814
13815 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13816         .destroy = intel_user_framebuffer_destroy,
13817         .create_handle = intel_user_framebuffer_create_handle,
13818         .dirty = intel_user_framebuffer_dirty,
13819 };
13820
13821 static
13822 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13823                          uint64_t fb_modifier, uint32_t pixel_format)
13824 {
13825         u32 gen = INTEL_GEN(dev_priv);
13826
13827         if (gen >= 9) {
13828                 int cpp = drm_format_plane_cpp(pixel_format, 0);
13829
13830                 /* "The stride in bytes must not exceed the of the size of 8K
13831                  *  pixels and 32K bytes."
13832                  */
13833                 return min(8192 * cpp, 32768);
13834         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13835                 return 32*1024;
13836         } else if (gen >= 4) {
13837                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13838                         return 16*1024;
13839                 else
13840                         return 32*1024;
13841         } else if (gen >= 3) {
13842                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13843                         return 8*1024;
13844                 else
13845                         return 16*1024;
13846         } else {
13847                 /* XXX DSPC is limited to 4k tiled */
13848                 return 8*1024;
13849         }
13850 }
13851
13852 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13853                                   struct drm_i915_gem_object *obj,
13854                                   struct drm_mode_fb_cmd2 *mode_cmd)
13855 {
13856         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13857         struct drm_framebuffer *fb = &intel_fb->base;
13858         struct drm_format_name_buf format_name;
13859         u32 pitch_limit;
13860         unsigned int tiling, stride;
13861         int ret = -EINVAL;
13862         int i;
13863
13864         i915_gem_object_lock(obj);
13865         obj->framebuffer_references++;
13866         tiling = i915_gem_object_get_tiling(obj);
13867         stride = i915_gem_object_get_stride(obj);
13868         i915_gem_object_unlock(obj);
13869
13870         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13871                 /*
13872                  * If there's a fence, enforce that
13873                  * the fb modifier and tiling mode match.
13874                  */
13875                 if (tiling != I915_TILING_NONE &&
13876                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13877                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13878                         goto err;
13879                 }
13880         } else {
13881                 if (tiling == I915_TILING_X) {
13882                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13883                 } else if (tiling == I915_TILING_Y) {
13884                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13885                         goto err;
13886                 }
13887         }
13888
13889         /* Passed in modifier sanity checking. */
13890         switch (mode_cmd->modifier[0]) {
13891         case I915_FORMAT_MOD_Y_TILED_CCS:
13892         case I915_FORMAT_MOD_Yf_TILED_CCS:
13893                 switch (mode_cmd->pixel_format) {
13894                 case DRM_FORMAT_XBGR8888:
13895                 case DRM_FORMAT_ABGR8888:
13896                 case DRM_FORMAT_XRGB8888:
13897                 case DRM_FORMAT_ARGB8888:
13898                         break;
13899                 default:
13900                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13901                         goto err;
13902                 }
13903                 /* fall through */
13904         case I915_FORMAT_MOD_Y_TILED:
13905         case I915_FORMAT_MOD_Yf_TILED:
13906                 if (INTEL_GEN(dev_priv) < 9) {
13907                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13908                                       mode_cmd->modifier[0]);
13909                         goto err;
13910                 }
13911         case DRM_FORMAT_MOD_LINEAR:
13912         case I915_FORMAT_MOD_X_TILED:
13913                 break;
13914         default:
13915                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13916                               mode_cmd->modifier[0]);
13917                 goto err;
13918         }
13919
13920         /*
13921          * gen2/3 display engine uses the fence if present,
13922          * so the tiling mode must match the fb modifier exactly.
13923          */
13924         if (INTEL_INFO(dev_priv)->gen < 4 &&
13925             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13926                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13927                 goto err;
13928         }
13929
13930         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13931                                            mode_cmd->pixel_format);
13932         if (mode_cmd->pitches[0] > pitch_limit) {
13933                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13934                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13935                               "tiled" : "linear",
13936                               mode_cmd->pitches[0], pitch_limit);
13937                 goto err;
13938         }
13939
13940         /*
13941          * If there's a fence, enforce that
13942          * the fb pitch and fence stride match.
13943          */
13944         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13945                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13946                               mode_cmd->pitches[0], stride);
13947                 goto err;
13948         }
13949
13950         /* Reject formats not supported by any plane early. */
13951         switch (mode_cmd->pixel_format) {
13952         case DRM_FORMAT_C8:
13953         case DRM_FORMAT_RGB565:
13954         case DRM_FORMAT_XRGB8888:
13955         case DRM_FORMAT_ARGB8888:
13956                 break;
13957         case DRM_FORMAT_XRGB1555:
13958                 if (INTEL_GEN(dev_priv) > 3) {
13959                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13960                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13961                         goto err;
13962                 }
13963                 break;
13964         case DRM_FORMAT_ABGR8888:
13965                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13966                     INTEL_GEN(dev_priv) < 9) {
13967                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13968                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13969                         goto err;
13970                 }
13971                 break;
13972         case DRM_FORMAT_XBGR8888:
13973         case DRM_FORMAT_XRGB2101010:
13974         case DRM_FORMAT_XBGR2101010:
13975                 if (INTEL_GEN(dev_priv) < 4) {
13976                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13977                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13978                         goto err;
13979                 }
13980                 break;
13981         case DRM_FORMAT_ABGR2101010:
13982                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13983                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13984                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13985                         goto err;
13986                 }
13987                 break;
13988         case DRM_FORMAT_YUYV:
13989         case DRM_FORMAT_UYVY:
13990         case DRM_FORMAT_YVYU:
13991         case DRM_FORMAT_VYUY:
13992                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13993                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13994                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13995                         goto err;
13996                 }
13997                 break;
13998         default:
13999                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14000                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14001                 goto err;
14002         }
14003
14004         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14005         if (mode_cmd->offsets[0] != 0)
14006                 goto err;
14007
14008         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14009
14010         for (i = 0; i < fb->format->num_planes; i++) {
14011                 u32 stride_alignment;
14012
14013                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14014                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14015                         goto err;
14016                 }
14017
14018                 stride_alignment = intel_fb_stride_alignment(fb, i);
14019
14020                 /*
14021                  * Display WA #0531: skl,bxt,kbl,glk
14022                  *
14023                  * Render decompression and plane width > 3840
14024                  * combined with horizontal panning requires the
14025                  * plane stride to be a multiple of 4. We'll just
14026                  * require the entire fb to accommodate that to avoid
14027                  * potential runtime errors at plane configuration time.
14028                  */
14029                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14030                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14031                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14032                         stride_alignment *= 4;
14033
14034                 if (fb->pitches[i] & (stride_alignment - 1)) {
14035                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14036                                       i, fb->pitches[i], stride_alignment);
14037                         goto err;
14038                 }
14039         }
14040
14041         intel_fb->obj = obj;
14042
14043         ret = intel_fill_fb_info(dev_priv, fb);
14044         if (ret)
14045                 goto err;
14046
14047         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14048         if (ret) {
14049                 DRM_ERROR("framebuffer init failed %d\n", ret);
14050                 goto err;
14051         }
14052
14053         return 0;
14054
14055 err:
14056         i915_gem_object_lock(obj);
14057         obj->framebuffer_references--;
14058         i915_gem_object_unlock(obj);
14059         return ret;
14060 }
14061
14062 static struct drm_framebuffer *
14063 intel_user_framebuffer_create(struct drm_device *dev,
14064                               struct drm_file *filp,
14065                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14066 {
14067         struct drm_framebuffer *fb;
14068         struct drm_i915_gem_object *obj;
14069         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14070
14071         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14072         if (!obj)
14073                 return ERR_PTR(-ENOENT);
14074
14075         fb = intel_framebuffer_create(obj, &mode_cmd);
14076         if (IS_ERR(fb))
14077                 i915_gem_object_put(obj);
14078
14079         return fb;
14080 }
14081
14082 static void intel_atomic_state_free(struct drm_atomic_state *state)
14083 {
14084         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14085
14086         drm_atomic_state_default_release(state);
14087
14088         i915_sw_fence_fini(&intel_state->commit_ready);
14089
14090         kfree(state);
14091 }
14092
14093 static const struct drm_mode_config_funcs intel_mode_funcs = {
14094         .fb_create = intel_user_framebuffer_create,
14095         .get_format_info = intel_get_format_info,
14096         .output_poll_changed = intel_fbdev_output_poll_changed,
14097         .atomic_check = intel_atomic_check,
14098         .atomic_commit = intel_atomic_commit,
14099         .atomic_state_alloc = intel_atomic_state_alloc,
14100         .atomic_state_clear = intel_atomic_state_clear,
14101         .atomic_state_free = intel_atomic_state_free,
14102 };
14103
14104 /**
14105  * intel_init_display_hooks - initialize the display modesetting hooks
14106  * @dev_priv: device private
14107  */
14108 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14109 {
14110         intel_init_cdclk_hooks(dev_priv);
14111
14112         if (INTEL_INFO(dev_priv)->gen >= 9) {
14113                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14114                 dev_priv->display.get_initial_plane_config =
14115                         skylake_get_initial_plane_config;
14116                 dev_priv->display.crtc_compute_clock =
14117                         haswell_crtc_compute_clock;
14118                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14119                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14120         } else if (HAS_DDI(dev_priv)) {
14121                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14122                 dev_priv->display.get_initial_plane_config =
14123                         ironlake_get_initial_plane_config;
14124                 dev_priv->display.crtc_compute_clock =
14125                         haswell_crtc_compute_clock;
14126                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14127                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14128         } else if (HAS_PCH_SPLIT(dev_priv)) {
14129                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14130                 dev_priv->display.get_initial_plane_config =
14131                         ironlake_get_initial_plane_config;
14132                 dev_priv->display.crtc_compute_clock =
14133                         ironlake_crtc_compute_clock;
14134                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14135                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14136         } else if (IS_CHERRYVIEW(dev_priv)) {
14137                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14138                 dev_priv->display.get_initial_plane_config =
14139                         i9xx_get_initial_plane_config;
14140                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14141                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14142                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14143         } else if (IS_VALLEYVIEW(dev_priv)) {
14144                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14145                 dev_priv->display.get_initial_plane_config =
14146                         i9xx_get_initial_plane_config;
14147                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14148                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14149                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14150         } else if (IS_G4X(dev_priv)) {
14151                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14152                 dev_priv->display.get_initial_plane_config =
14153                         i9xx_get_initial_plane_config;
14154                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14155                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14156                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14157         } else if (IS_PINEVIEW(dev_priv)) {
14158                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14159                 dev_priv->display.get_initial_plane_config =
14160                         i9xx_get_initial_plane_config;
14161                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14162                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14163                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14164         } else if (!IS_GEN2(dev_priv)) {
14165                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14166                 dev_priv->display.get_initial_plane_config =
14167                         i9xx_get_initial_plane_config;
14168                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14169                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14170                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14171         } else {
14172                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14173                 dev_priv->display.get_initial_plane_config =
14174                         i9xx_get_initial_plane_config;
14175                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14176                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14177                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14178         }
14179
14180         if (IS_GEN5(dev_priv)) {
14181                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14182         } else if (IS_GEN6(dev_priv)) {
14183                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14184         } else if (IS_IVYBRIDGE(dev_priv)) {
14185                 /* FIXME: detect B0+ stepping and use auto training */
14186                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14187         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14188                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14189         }
14190
14191         if (INTEL_GEN(dev_priv) >= 9)
14192                 dev_priv->display.update_crtcs = skl_update_crtcs;
14193         else
14194                 dev_priv->display.update_crtcs = intel_update_crtcs;
14195 }
14196
14197 /*
14198  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14199  */
14200 static void quirk_ssc_force_disable(struct drm_device *dev)
14201 {
14202         struct drm_i915_private *dev_priv = to_i915(dev);
14203         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14204         DRM_INFO("applying lvds SSC disable quirk\n");
14205 }
14206
14207 /*
14208  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14209  * brightness value
14210  */
14211 static void quirk_invert_brightness(struct drm_device *dev)
14212 {
14213         struct drm_i915_private *dev_priv = to_i915(dev);
14214         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14215         DRM_INFO("applying inverted panel brightness quirk\n");
14216 }
14217
14218 /* Some VBT's incorrectly indicate no backlight is present */
14219 static void quirk_backlight_present(struct drm_device *dev)
14220 {
14221         struct drm_i915_private *dev_priv = to_i915(dev);
14222         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14223         DRM_INFO("applying backlight present quirk\n");
14224 }
14225
14226 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14227  * which is 300 ms greater than eDP spec T12 min.
14228  */
14229 static void quirk_increase_t12_delay(struct drm_device *dev)
14230 {
14231         struct drm_i915_private *dev_priv = to_i915(dev);
14232
14233         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14234         DRM_INFO("Applying T12 delay quirk\n");
14235 }
14236
14237 struct intel_quirk {
14238         int device;
14239         int subsystem_vendor;
14240         int subsystem_device;
14241         void (*hook)(struct drm_device *dev);
14242 };
14243
14244 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14245 struct intel_dmi_quirk {
14246         void (*hook)(struct drm_device *dev);
14247         const struct dmi_system_id (*dmi_id_list)[];
14248 };
14249
14250 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14251 {
14252         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14253         return 1;
14254 }
14255
14256 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14257         {
14258                 .dmi_id_list = &(const struct dmi_system_id[]) {
14259                         {
14260                                 .callback = intel_dmi_reverse_brightness,
14261                                 .ident = "NCR Corporation",
14262                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14263                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14264                                 },
14265                         },
14266                         { }  /* terminating entry */
14267                 },
14268                 .hook = quirk_invert_brightness,
14269         },
14270 };
14271
14272 static struct intel_quirk intel_quirks[] = {
14273         /* Lenovo U160 cannot use SSC on LVDS */
14274         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14275
14276         /* Sony Vaio Y cannot use SSC on LVDS */
14277         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14278
14279         /* Acer Aspire 5734Z must invert backlight brightness */
14280         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14281
14282         /* Acer/eMachines G725 */
14283         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14284
14285         /* Acer/eMachines e725 */
14286         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14287
14288         /* Acer/Packard Bell NCL20 */
14289         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14290
14291         /* Acer Aspire 4736Z */
14292         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14293
14294         /* Acer Aspire 5336 */
14295         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14296
14297         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14298         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14299
14300         /* Acer C720 Chromebook (Core i3 4005U) */
14301         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14302
14303         /* Apple Macbook 2,1 (Core 2 T7400) */
14304         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14305
14306         /* Apple Macbook 4,1 */
14307         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14308
14309         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14310         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14311
14312         /* HP Chromebook 14 (Celeron 2955U) */
14313         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14314
14315         /* Dell Chromebook 11 */
14316         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14317
14318         /* Dell Chromebook 11 (2015 version) */
14319         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14320
14321         /* Toshiba Satellite P50-C-18C */
14322         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14323 };
14324
14325 static void intel_init_quirks(struct drm_device *dev)
14326 {
14327         struct pci_dev *d = dev->pdev;
14328         int i;
14329
14330         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14331                 struct intel_quirk *q = &intel_quirks[i];
14332
14333                 if (d->device == q->device &&
14334                     (d->subsystem_vendor == q->subsystem_vendor ||
14335                      q->subsystem_vendor == PCI_ANY_ID) &&
14336                     (d->subsystem_device == q->subsystem_device ||
14337                      q->subsystem_device == PCI_ANY_ID))
14338                         q->hook(dev);
14339         }
14340         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14341                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14342                         intel_dmi_quirks[i].hook(dev);
14343         }
14344 }
14345
14346 /* Disable the VGA plane that we never use */
14347 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14348 {
14349         struct pci_dev *pdev = dev_priv->drm.pdev;
14350         u8 sr1;
14351         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14352
14353         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14354         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14355         outb(SR01, VGA_SR_INDEX);
14356         sr1 = inb(VGA_SR_DATA);
14357         outb(sr1 | 1<<5, VGA_SR_DATA);
14358         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14359         udelay(300);
14360
14361         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14362         POSTING_READ(vga_reg);
14363 }
14364
14365 void intel_modeset_init_hw(struct drm_device *dev)
14366 {
14367         struct drm_i915_private *dev_priv = to_i915(dev);
14368
14369         intel_update_cdclk(dev_priv);
14370         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14371 }
14372
14373 /*
14374  * Calculate what we think the watermarks should be for the state we've read
14375  * out of the hardware and then immediately program those watermarks so that
14376  * we ensure the hardware settings match our internal state.
14377  *
14378  * We can calculate what we think WM's should be by creating a duplicate of the
14379  * current state (which was constructed during hardware readout) and running it
14380  * through the atomic check code to calculate new watermark values in the
14381  * state object.
14382  */
14383 static void sanitize_watermarks(struct drm_device *dev)
14384 {
14385         struct drm_i915_private *dev_priv = to_i915(dev);
14386         struct drm_atomic_state *state;
14387         struct intel_atomic_state *intel_state;
14388         struct drm_crtc *crtc;
14389         struct drm_crtc_state *cstate;
14390         struct drm_modeset_acquire_ctx ctx;
14391         int ret;
14392         int i;
14393
14394         /* Only supported on platforms that use atomic watermark design */
14395         if (!dev_priv->display.optimize_watermarks)
14396                 return;
14397
14398         /*
14399          * We need to hold connection_mutex before calling duplicate_state so
14400          * that the connector loop is protected.
14401          */
14402         drm_modeset_acquire_init(&ctx, 0);
14403 retry:
14404         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14405         if (ret == -EDEADLK) {
14406                 drm_modeset_backoff(&ctx);
14407                 goto retry;
14408         } else if (WARN_ON(ret)) {
14409                 goto fail;
14410         }
14411
14412         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14413         if (WARN_ON(IS_ERR(state)))
14414                 goto fail;
14415
14416         intel_state = to_intel_atomic_state(state);
14417
14418         /*
14419          * Hardware readout is the only time we don't want to calculate
14420          * intermediate watermarks (since we don't trust the current
14421          * watermarks).
14422          */
14423         if (!HAS_GMCH_DISPLAY(dev_priv))
14424                 intel_state->skip_intermediate_wm = true;
14425
14426         ret = intel_atomic_check(dev, state);
14427         if (ret) {
14428                 /*
14429                  * If we fail here, it means that the hardware appears to be
14430                  * programmed in a way that shouldn't be possible, given our
14431                  * understanding of watermark requirements.  This might mean a
14432                  * mistake in the hardware readout code or a mistake in the
14433                  * watermark calculations for a given platform.  Raise a WARN
14434                  * so that this is noticeable.
14435                  *
14436                  * If this actually happens, we'll have to just leave the
14437                  * BIOS-programmed watermarks untouched and hope for the best.
14438                  */
14439                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14440                 goto put_state;
14441         }
14442
14443         /* Write calculated watermark values back */
14444         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14445                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14446
14447                 cs->wm.need_postvbl_update = true;
14448                 dev_priv->display.optimize_watermarks(intel_state, cs);
14449         }
14450
14451 put_state:
14452         drm_atomic_state_put(state);
14453 fail:
14454         drm_modeset_drop_locks(&ctx);
14455         drm_modeset_acquire_fini(&ctx);
14456 }
14457
14458 int intel_modeset_init(struct drm_device *dev)
14459 {
14460         struct drm_i915_private *dev_priv = to_i915(dev);
14461         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14462         enum pipe pipe;
14463         struct intel_crtc *crtc;
14464
14465         drm_mode_config_init(dev);
14466
14467         dev->mode_config.min_width = 0;
14468         dev->mode_config.min_height = 0;
14469
14470         dev->mode_config.preferred_depth = 24;
14471         dev->mode_config.prefer_shadow = 1;
14472
14473         dev->mode_config.allow_fb_modifiers = true;
14474
14475         dev->mode_config.funcs = &intel_mode_funcs;
14476
14477         init_llist_head(&dev_priv->atomic_helper.free_list);
14478         INIT_WORK(&dev_priv->atomic_helper.free_work,
14479                   intel_atomic_helper_free_state_worker);
14480
14481         intel_init_quirks(dev);
14482
14483         intel_init_pm(dev_priv);
14484
14485         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14486                 return 0;
14487
14488         /*
14489          * There may be no VBT; and if the BIOS enabled SSC we can
14490          * just keep using it to avoid unnecessary flicker.  Whereas if the
14491          * BIOS isn't using it, don't assume it will work even if the VBT
14492          * indicates as much.
14493          */
14494         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14495                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14496                                             DREF_SSC1_ENABLE);
14497
14498                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14499                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14500                                      bios_lvds_use_ssc ? "en" : "dis",
14501                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14502                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14503                 }
14504         }
14505
14506         if (IS_GEN2(dev_priv)) {
14507                 dev->mode_config.max_width = 2048;
14508                 dev->mode_config.max_height = 2048;
14509         } else if (IS_GEN3(dev_priv)) {
14510                 dev->mode_config.max_width = 4096;
14511                 dev->mode_config.max_height = 4096;
14512         } else {
14513                 dev->mode_config.max_width = 8192;
14514                 dev->mode_config.max_height = 8192;
14515         }
14516
14517         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14518                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14519                 dev->mode_config.cursor_height = 1023;
14520         } else if (IS_GEN2(dev_priv)) {
14521                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14522                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14523         } else {
14524                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14525                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14526         }
14527
14528         dev->mode_config.fb_base = ggtt->mappable_base;
14529
14530         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14531                       INTEL_INFO(dev_priv)->num_pipes,
14532                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14533
14534         for_each_pipe(dev_priv, pipe) {
14535                 int ret;
14536
14537                 ret = intel_crtc_init(dev_priv, pipe);
14538                 if (ret) {
14539                         drm_mode_config_cleanup(dev);
14540                         return ret;
14541                 }
14542         }
14543
14544         intel_shared_dpll_init(dev);
14545
14546         intel_update_czclk(dev_priv);
14547         intel_modeset_init_hw(dev);
14548
14549         if (dev_priv->max_cdclk_freq == 0)
14550                 intel_update_max_cdclk(dev_priv);
14551
14552         /* Just disable it once at startup */
14553         i915_disable_vga(dev_priv);
14554         intel_setup_outputs(dev_priv);
14555
14556         drm_modeset_lock_all(dev);
14557         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14558         drm_modeset_unlock_all(dev);
14559
14560         for_each_intel_crtc(dev, crtc) {
14561                 struct intel_initial_plane_config plane_config = {};
14562
14563                 if (!crtc->active)
14564                         continue;
14565
14566                 /*
14567                  * Note that reserving the BIOS fb up front prevents us
14568                  * from stuffing other stolen allocations like the ring
14569                  * on top.  This prevents some ugliness at boot time, and
14570                  * can even allow for smooth boot transitions if the BIOS
14571                  * fb is large enough for the active pipe configuration.
14572                  */
14573                 dev_priv->display.get_initial_plane_config(crtc,
14574                                                            &plane_config);
14575
14576                 /*
14577                  * If the fb is shared between multiple heads, we'll
14578                  * just get the first one.
14579                  */
14580                 intel_find_initial_plane_obj(crtc, &plane_config);
14581         }
14582
14583         /*
14584          * Make sure hardware watermarks really match the state we read out.
14585          * Note that we need to do this after reconstructing the BIOS fb's
14586          * since the watermark calculation done here will use pstate->fb.
14587          */
14588         if (!HAS_GMCH_DISPLAY(dev_priv))
14589                 sanitize_watermarks(dev);
14590
14591         return 0;
14592 }
14593
14594 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14595 {
14596         /* 640x480@60Hz, ~25175 kHz */
14597         struct dpll clock = {
14598                 .m1 = 18,
14599                 .m2 = 7,
14600                 .p1 = 13,
14601                 .p2 = 4,
14602                 .n = 2,
14603         };
14604         u32 dpll, fp;
14605         int i;
14606
14607         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14608
14609         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14610                       pipe_name(pipe), clock.vco, clock.dot);
14611
14612         fp = i9xx_dpll_compute_fp(&clock);
14613         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14614                 DPLL_VGA_MODE_DIS |
14615                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14616                 PLL_P2_DIVIDE_BY_4 |
14617                 PLL_REF_INPUT_DREFCLK |
14618                 DPLL_VCO_ENABLE;
14619
14620         I915_WRITE(FP0(pipe), fp);
14621         I915_WRITE(FP1(pipe), fp);
14622
14623         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14624         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14625         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14626         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14627         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14628         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14629         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14630
14631         /*
14632          * Apparently we need to have VGA mode enabled prior to changing
14633          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14634          * dividers, even though the register value does change.
14635          */
14636         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14637         I915_WRITE(DPLL(pipe), dpll);
14638
14639         /* Wait for the clocks to stabilize. */
14640         POSTING_READ(DPLL(pipe));
14641         udelay(150);
14642
14643         /* The pixel multiplier can only be updated once the
14644          * DPLL is enabled and the clocks are stable.
14645          *
14646          * So write it again.
14647          */
14648         I915_WRITE(DPLL(pipe), dpll);
14649
14650         /* We do this three times for luck */
14651         for (i = 0; i < 3 ; i++) {
14652                 I915_WRITE(DPLL(pipe), dpll);
14653                 POSTING_READ(DPLL(pipe));
14654                 udelay(150); /* wait for warmup */
14655         }
14656
14657         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14658         POSTING_READ(PIPECONF(pipe));
14659 }
14660
14661 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14662 {
14663         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14664
14665         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14666                       pipe_name(pipe));
14667
14668         assert_plane_disabled(dev_priv, PLANE_A);
14669         assert_plane_disabled(dev_priv, PLANE_B);
14670
14671         I915_WRITE(PIPECONF(pipe), 0);
14672         POSTING_READ(PIPECONF(pipe));
14673
14674         intel_wait_for_pipe_scanline_stopped(crtc);
14675
14676         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14677         POSTING_READ(DPLL(pipe));
14678 }
14679
14680 static bool
14681 intel_check_plane_mapping(struct intel_crtc *crtc)
14682 {
14683         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14684         u32 val;
14685
14686         if (INTEL_INFO(dev_priv)->num_pipes == 1)
14687                 return true;
14688
14689         val = I915_READ(DSPCNTR(!crtc->plane));
14690
14691         if ((val & DISPLAY_PLANE_ENABLE) &&
14692             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14693                 return false;
14694
14695         return true;
14696 }
14697
14698 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14699 {
14700         struct drm_device *dev = crtc->base.dev;
14701         struct intel_encoder *encoder;
14702
14703         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14704                 return true;
14705
14706         return false;
14707 }
14708
14709 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14710 {
14711         struct drm_device *dev = encoder->base.dev;
14712         struct intel_connector *connector;
14713
14714         for_each_connector_on_encoder(dev, &encoder->base, connector)
14715                 return connector;
14716
14717         return NULL;
14718 }
14719
14720 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14721                               enum pipe pch_transcoder)
14722 {
14723         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14724                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14725 }
14726
14727 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14728                                 struct drm_modeset_acquire_ctx *ctx)
14729 {
14730         struct drm_device *dev = crtc->base.dev;
14731         struct drm_i915_private *dev_priv = to_i915(dev);
14732         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14733
14734         /* Clear any frame start delays used for debugging left by the BIOS */
14735         if (!transcoder_is_dsi(cpu_transcoder)) {
14736                 i915_reg_t reg = PIPECONF(cpu_transcoder);
14737
14738                 I915_WRITE(reg,
14739                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14740         }
14741
14742         /* restore vblank interrupts to correct state */
14743         drm_crtc_vblank_reset(&crtc->base);
14744         if (crtc->active) {
14745                 struct intel_plane *plane;
14746
14747                 drm_crtc_vblank_on(&crtc->base);
14748
14749                 /* Disable everything but the primary plane */
14750                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14751                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14752                                 continue;
14753
14754                         trace_intel_disable_plane(&plane->base, crtc);
14755                         plane->disable_plane(plane, crtc);
14756                 }
14757         }
14758
14759         /* We need to sanitize the plane -> pipe mapping first because this will
14760          * disable the crtc (and hence change the state) if it is wrong. Note
14761          * that gen4+ has a fixed plane -> pipe mapping.  */
14762         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14763                 bool plane;
14764
14765                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14766                               crtc->base.base.id, crtc->base.name);
14767
14768                 /* Pipe has the wrong plane attached and the plane is active.
14769                  * Temporarily change the plane mapping and disable everything
14770                  * ...  */
14771                 plane = crtc->plane;
14772                 crtc->base.primary->state->visible = true;
14773                 crtc->plane = !plane;
14774                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14775                 crtc->plane = plane;
14776         }
14777
14778         /* Adjust the state of the output pipe according to whether we
14779          * have active connectors/encoders. */
14780         if (crtc->active && !intel_crtc_has_encoders(crtc))
14781                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14782
14783         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14784                 /*
14785                  * We start out with underrun reporting disabled to avoid races.
14786                  * For correct bookkeeping mark this on active crtcs.
14787                  *
14788                  * Also on gmch platforms we dont have any hardware bits to
14789                  * disable the underrun reporting. Which means we need to start
14790                  * out with underrun reporting disabled also on inactive pipes,
14791                  * since otherwise we'll complain about the garbage we read when
14792                  * e.g. coming up after runtime pm.
14793                  *
14794                  * No protection against concurrent access is required - at
14795                  * worst a fifo underrun happens which also sets this to false.
14796                  */
14797                 crtc->cpu_fifo_underrun_disabled = true;
14798                 /*
14799                  * We track the PCH trancoder underrun reporting state
14800                  * within the crtc. With crtc for pipe A housing the underrun
14801                  * reporting state for PCH transcoder A, crtc for pipe B housing
14802                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14803                  * and marking underrun reporting as disabled for the non-existing
14804                  * PCH transcoders B and C would prevent enabling the south
14805                  * error interrupt (see cpt_can_enable_serr_int()).
14806                  */
14807                 if (has_pch_trancoder(dev_priv, crtc->pipe))
14808                         crtc->pch_fifo_underrun_disabled = true;
14809         }
14810 }
14811
14812 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14813 {
14814         struct intel_connector *connector;
14815
14816         /* We need to check both for a crtc link (meaning that the
14817          * encoder is active and trying to read from a pipe) and the
14818          * pipe itself being active. */
14819         bool has_active_crtc = encoder->base.crtc &&
14820                 to_intel_crtc(encoder->base.crtc)->active;
14821
14822         connector = intel_encoder_find_connector(encoder);
14823         if (connector && !has_active_crtc) {
14824                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14825                               encoder->base.base.id,
14826                               encoder->base.name);
14827
14828                 /* Connector is active, but has no active pipe. This is
14829                  * fallout from our resume register restoring. Disable
14830                  * the encoder manually again. */
14831                 if (encoder->base.crtc) {
14832                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14833
14834                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14835                                       encoder->base.base.id,
14836                                       encoder->base.name);
14837                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14838                         if (encoder->post_disable)
14839                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14840                 }
14841                 encoder->base.crtc = NULL;
14842
14843                 /* Inconsistent output/port/pipe state happens presumably due to
14844                  * a bug in one of the get_hw_state functions. Or someplace else
14845                  * in our code, like the register restore mess on resume. Clamp
14846                  * things to off as a safer default. */
14847
14848                 connector->base.dpms = DRM_MODE_DPMS_OFF;
14849                 connector->base.encoder = NULL;
14850         }
14851         /* Enabled encoders without active connectors will be fixed in
14852          * the crtc fixup. */
14853 }
14854
14855 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14856 {
14857         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14858
14859         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14860                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14861                 i915_disable_vga(dev_priv);
14862         }
14863 }
14864
14865 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14866 {
14867         /* This function can be called both from intel_modeset_setup_hw_state or
14868          * at a very early point in our resume sequence, where the power well
14869          * structures are not yet restored. Since this function is at a very
14870          * paranoid "someone might have enabled VGA while we were not looking"
14871          * level, just check if the power well is enabled instead of trying to
14872          * follow the "don't touch the power well if we don't need it" policy
14873          * the rest of the driver uses. */
14874         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14875                 return;
14876
14877         i915_redisable_vga_power_on(dev_priv);
14878
14879         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14880 }
14881
14882 static bool primary_get_hw_state(struct intel_plane *plane)
14883 {
14884         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14885
14886         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14887 }
14888
14889 /* FIXME read out full plane state for all planes */
14890 static void readout_plane_state(struct intel_crtc *crtc)
14891 {
14892         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14893         bool visible;
14894
14895         visible = crtc->active && primary_get_hw_state(primary);
14896
14897         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14898                                 to_intel_plane_state(primary->base.state),
14899                                 visible);
14900 }
14901
14902 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14903 {
14904         struct drm_i915_private *dev_priv = to_i915(dev);
14905         enum pipe pipe;
14906         struct intel_crtc *crtc;
14907         struct intel_encoder *encoder;
14908         struct intel_connector *connector;
14909         struct drm_connector_list_iter conn_iter;
14910         int i;
14911
14912         dev_priv->active_crtcs = 0;
14913
14914         for_each_intel_crtc(dev, crtc) {
14915                 struct intel_crtc_state *crtc_state =
14916                         to_intel_crtc_state(crtc->base.state);
14917
14918                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14919                 memset(crtc_state, 0, sizeof(*crtc_state));
14920                 crtc_state->base.crtc = &crtc->base;
14921
14922                 crtc_state->base.active = crtc_state->base.enable =
14923                         dev_priv->display.get_pipe_config(crtc, crtc_state);
14924
14925                 crtc->base.enabled = crtc_state->base.enable;
14926                 crtc->active = crtc_state->base.active;
14927
14928                 if (crtc_state->base.active)
14929                         dev_priv->active_crtcs |= 1 << crtc->pipe;
14930
14931                 readout_plane_state(crtc);
14932
14933                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14934                               crtc->base.base.id, crtc->base.name,
14935                               enableddisabled(crtc_state->base.active));
14936         }
14937
14938         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14939                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14940
14941                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14942                                                   &pll->state.hw_state);
14943                 pll->state.crtc_mask = 0;
14944                 for_each_intel_crtc(dev, crtc) {
14945                         struct intel_crtc_state *crtc_state =
14946                                 to_intel_crtc_state(crtc->base.state);
14947
14948                         if (crtc_state->base.active &&
14949                             crtc_state->shared_dpll == pll)
14950                                 pll->state.crtc_mask |= 1 << crtc->pipe;
14951                 }
14952                 pll->active_mask = pll->state.crtc_mask;
14953
14954                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14955                               pll->name, pll->state.crtc_mask, pll->on);
14956         }
14957
14958         for_each_intel_encoder(dev, encoder) {
14959                 pipe = 0;
14960
14961                 if (encoder->get_hw_state(encoder, &pipe)) {
14962                         struct intel_crtc_state *crtc_state;
14963
14964                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14965                         crtc_state = to_intel_crtc_state(crtc->base.state);
14966
14967                         encoder->base.crtc = &crtc->base;
14968                         crtc_state->output_types |= 1 << encoder->type;
14969                         encoder->get_config(encoder, crtc_state);
14970                 } else {
14971                         encoder->base.crtc = NULL;
14972                 }
14973
14974                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14975                               encoder->base.base.id, encoder->base.name,
14976                               enableddisabled(encoder->base.crtc),
14977                               pipe_name(pipe));
14978         }
14979
14980         drm_connector_list_iter_begin(dev, &conn_iter);
14981         for_each_intel_connector_iter(connector, &conn_iter) {
14982                 if (connector->get_hw_state(connector)) {
14983                         connector->base.dpms = DRM_MODE_DPMS_ON;
14984
14985                         encoder = connector->encoder;
14986                         connector->base.encoder = &encoder->base;
14987
14988                         if (encoder->base.crtc &&
14989                             encoder->base.crtc->state->active) {
14990                                 /*
14991                                  * This has to be done during hardware readout
14992                                  * because anything calling .crtc_disable may
14993                                  * rely on the connector_mask being accurate.
14994                                  */
14995                                 encoder->base.crtc->state->connector_mask |=
14996                                         1 << drm_connector_index(&connector->base);
14997                                 encoder->base.crtc->state->encoder_mask |=
14998                                         1 << drm_encoder_index(&encoder->base);
14999                         }
15000
15001                 } else {
15002                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15003                         connector->base.encoder = NULL;
15004                 }
15005                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15006                               connector->base.base.id, connector->base.name,
15007                               enableddisabled(connector->base.encoder));
15008         }
15009         drm_connector_list_iter_end(&conn_iter);
15010
15011         for_each_intel_crtc(dev, crtc) {
15012                 struct intel_crtc_state *crtc_state =
15013                         to_intel_crtc_state(crtc->base.state);
15014                 int min_cdclk = 0;
15015
15016                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15017                 if (crtc_state->base.active) {
15018                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15019                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15020                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15021
15022                         /*
15023                          * The initial mode needs to be set in order to keep
15024                          * the atomic core happy. It wants a valid mode if the
15025                          * crtc's enabled, so we do the above call.
15026                          *
15027                          * But we don't set all the derived state fully, hence
15028                          * set a flag to indicate that a full recalculation is
15029                          * needed on the next commit.
15030                          */
15031                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15032
15033                         intel_crtc_compute_pixel_rate(crtc_state);
15034
15035                         if (dev_priv->display.modeset_calc_cdclk) {
15036                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15037                                 if (WARN_ON(min_cdclk < 0))
15038                                         min_cdclk = 0;
15039                         }
15040
15041                         drm_calc_timestamping_constants(&crtc->base,
15042                                                         &crtc_state->base.adjusted_mode);
15043                         update_scanline_offset(crtc);
15044                 }
15045
15046                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15047
15048                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15049         }
15050 }
15051
15052 static void
15053 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15054 {
15055         struct intel_encoder *encoder;
15056
15057         for_each_intel_encoder(&dev_priv->drm, encoder) {
15058                 u64 get_domains;
15059                 enum intel_display_power_domain domain;
15060
15061                 if (!encoder->get_power_domains)
15062                         continue;
15063
15064                 get_domains = encoder->get_power_domains(encoder);
15065                 for_each_power_domain(domain, get_domains)
15066                         intel_display_power_get(dev_priv, domain);
15067         }
15068 }
15069
15070 /* Scan out the current hw modeset state,
15071  * and sanitizes it to the current state
15072  */
15073 static void
15074 intel_modeset_setup_hw_state(struct drm_device *dev,
15075                              struct drm_modeset_acquire_ctx *ctx)
15076 {
15077         struct drm_i915_private *dev_priv = to_i915(dev);
15078         enum pipe pipe;
15079         struct intel_crtc *crtc;
15080         struct intel_encoder *encoder;
15081         int i;
15082
15083         if (IS_HASWELL(dev_priv)) {
15084                 /*
15085                  * WaRsPkgCStateDisplayPMReq:hsw
15086                  * System hang if this isn't done before disabling all planes!
15087                  */
15088                 I915_WRITE(CHICKEN_PAR1_1,
15089                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15090         }
15091
15092         intel_modeset_readout_hw_state(dev);
15093
15094         /* HW state is read out, now we need to sanitize this mess. */
15095         get_encoder_power_domains(dev_priv);
15096
15097         for_each_intel_encoder(dev, encoder) {
15098                 intel_sanitize_encoder(encoder);
15099         }
15100
15101         for_each_pipe(dev_priv, pipe) {
15102                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15103
15104                 intel_sanitize_crtc(crtc, ctx);
15105                 intel_dump_pipe_config(crtc, crtc->config,
15106                                        "[setup_hw_state]");
15107         }
15108
15109         intel_modeset_update_connector_atomic_state(dev);
15110
15111         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15112                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15113
15114                 if (!pll->on || pll->active_mask)
15115                         continue;
15116
15117                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15118
15119                 pll->funcs.disable(dev_priv, pll);
15120                 pll->on = false;
15121         }
15122
15123         if (IS_G4X(dev_priv)) {
15124                 g4x_wm_get_hw_state(dev);
15125                 g4x_wm_sanitize(dev_priv);
15126         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15127                 vlv_wm_get_hw_state(dev);
15128                 vlv_wm_sanitize(dev_priv);
15129         } else if (INTEL_GEN(dev_priv) >= 9) {
15130                 skl_wm_get_hw_state(dev);
15131         } else if (HAS_PCH_SPLIT(dev_priv)) {
15132                 ilk_wm_get_hw_state(dev);
15133         }
15134
15135         for_each_intel_crtc(dev, crtc) {
15136                 u64 put_domains;
15137
15138                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15139                 if (WARN_ON(put_domains))
15140                         modeset_put_power_domains(dev_priv, put_domains);
15141         }
15142         intel_display_set_init_power(dev_priv, false);
15143
15144         intel_power_domains_verify_state(dev_priv);
15145
15146         intel_fbc_init_pipe_state(dev_priv);
15147 }
15148
15149 void intel_display_resume(struct drm_device *dev)
15150 {
15151         struct drm_i915_private *dev_priv = to_i915(dev);
15152         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15153         struct drm_modeset_acquire_ctx ctx;
15154         int ret;
15155
15156         dev_priv->modeset_restore_state = NULL;
15157         if (state)
15158                 state->acquire_ctx = &ctx;
15159
15160         drm_modeset_acquire_init(&ctx, 0);
15161
15162         while (1) {
15163                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15164                 if (ret != -EDEADLK)
15165                         break;
15166
15167                 drm_modeset_backoff(&ctx);
15168         }
15169
15170         if (!ret)
15171                 ret = __intel_display_resume(dev, state, &ctx);
15172
15173         intel_enable_ipc(dev_priv);
15174         drm_modeset_drop_locks(&ctx);
15175         drm_modeset_acquire_fini(&ctx);
15176
15177         if (ret)
15178                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15179         if (state)
15180                 drm_atomic_state_put(state);
15181 }
15182
15183 void intel_modeset_gem_init(struct drm_device *dev)
15184 {
15185         struct drm_i915_private *dev_priv = to_i915(dev);
15186
15187         intel_init_gt_powersave(dev_priv);
15188
15189         intel_init_clock_gating(dev_priv);
15190
15191         intel_setup_overlay(dev_priv);
15192 }
15193
15194 int intel_connector_register(struct drm_connector *connector)
15195 {
15196         struct intel_connector *intel_connector = to_intel_connector(connector);
15197         int ret;
15198
15199         ret = intel_backlight_device_register(intel_connector);
15200         if (ret)
15201                 goto err;
15202
15203         return 0;
15204
15205 err:
15206         return ret;
15207 }
15208
15209 void intel_connector_unregister(struct drm_connector *connector)
15210 {
15211         struct intel_connector *intel_connector = to_intel_connector(connector);
15212
15213         intel_backlight_device_unregister(intel_connector);
15214         intel_panel_destroy_backlight(connector);
15215 }
15216
15217 static void intel_hpd_poll_fini(struct drm_device *dev)
15218 {
15219         struct intel_connector *connector;
15220         struct drm_connector_list_iter conn_iter;
15221
15222         /* First disable polling... */
15223         drm_kms_helper_poll_fini(dev);
15224
15225         /* Then kill the work that may have been queued by hpd. */
15226         drm_connector_list_iter_begin(dev, &conn_iter);
15227         for_each_intel_connector_iter(connector, &conn_iter) {
15228                 if (connector->modeset_retry_work.func)
15229                         cancel_work_sync(&connector->modeset_retry_work);
15230         }
15231         drm_connector_list_iter_end(&conn_iter);
15232 }
15233
15234 void intel_modeset_cleanup(struct drm_device *dev)
15235 {
15236         struct drm_i915_private *dev_priv = to_i915(dev);
15237
15238         flush_work(&dev_priv->atomic_helper.free_work);
15239         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15240
15241         intel_disable_gt_powersave(dev_priv);
15242
15243         /*
15244          * Interrupts and polling as the first thing to avoid creating havoc.
15245          * Too much stuff here (turning of connectors, ...) would
15246          * experience fancy races otherwise.
15247          */
15248         intel_irq_uninstall(dev_priv);
15249
15250         /*
15251          * Due to the hpd irq storm handling the hotplug work can re-arm the
15252          * poll handlers. Hence disable polling after hpd handling is shut down.
15253          */
15254         intel_hpd_poll_fini(dev);
15255
15256         /* poll work can call into fbdev, hence clean that up afterwards */
15257         intel_fbdev_fini(dev_priv);
15258
15259         intel_unregister_dsm_handler();
15260
15261         intel_fbc_global_disable(dev_priv);
15262
15263         /* flush any delayed tasks or pending work */
15264         flush_scheduled_work();
15265
15266         drm_mode_config_cleanup(dev);
15267
15268         intel_cleanup_overlay(dev_priv);
15269
15270         intel_cleanup_gt_powersave(dev_priv);
15271
15272         intel_teardown_gmbus(dev_priv);
15273 }
15274
15275 void intel_connector_attach_encoder(struct intel_connector *connector,
15276                                     struct intel_encoder *encoder)
15277 {
15278         connector->encoder = encoder;
15279         drm_mode_connector_attach_encoder(&connector->base,
15280                                           &encoder->base);
15281 }
15282
15283 /*
15284  * set vga decode state - true == enable VGA decode
15285  */
15286 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15287 {
15288         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15289         u16 gmch_ctrl;
15290
15291         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15292                 DRM_ERROR("failed to read control word\n");
15293                 return -EIO;
15294         }
15295
15296         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15297                 return 0;
15298
15299         if (state)
15300                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15301         else
15302                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15303
15304         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15305                 DRM_ERROR("failed to write control word\n");
15306                 return -EIO;
15307         }
15308
15309         return 0;
15310 }
15311
15312 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15313
15314 struct intel_display_error_state {
15315
15316         u32 power_well_driver;
15317
15318         int num_transcoders;
15319
15320         struct intel_cursor_error_state {
15321                 u32 control;
15322                 u32 position;
15323                 u32 base;
15324                 u32 size;
15325         } cursor[I915_MAX_PIPES];
15326
15327         struct intel_pipe_error_state {
15328                 bool power_domain_on;
15329                 u32 source;
15330                 u32 stat;
15331         } pipe[I915_MAX_PIPES];
15332
15333         struct intel_plane_error_state {
15334                 u32 control;
15335                 u32 stride;
15336                 u32 size;
15337                 u32 pos;
15338                 u32 addr;
15339                 u32 surface;
15340                 u32 tile_offset;
15341         } plane[I915_MAX_PIPES];
15342
15343         struct intel_transcoder_error_state {
15344                 bool power_domain_on;
15345                 enum transcoder cpu_transcoder;
15346
15347                 u32 conf;
15348
15349                 u32 htotal;
15350                 u32 hblank;
15351                 u32 hsync;
15352                 u32 vtotal;
15353                 u32 vblank;
15354                 u32 vsync;
15355         } transcoder[4];
15356 };
15357
15358 struct intel_display_error_state *
15359 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15360 {
15361         struct intel_display_error_state *error;
15362         int transcoders[] = {
15363                 TRANSCODER_A,
15364                 TRANSCODER_B,
15365                 TRANSCODER_C,
15366                 TRANSCODER_EDP,
15367         };
15368         int i;
15369
15370         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15371                 return NULL;
15372
15373         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15374         if (error == NULL)
15375                 return NULL;
15376
15377         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15378                 error->power_well_driver =
15379                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15380
15381         for_each_pipe(dev_priv, i) {
15382                 error->pipe[i].power_domain_on =
15383                         __intel_display_power_is_enabled(dev_priv,
15384                                                          POWER_DOMAIN_PIPE(i));
15385                 if (!error->pipe[i].power_domain_on)
15386                         continue;
15387
15388                 error->cursor[i].control = I915_READ(CURCNTR(i));
15389                 error->cursor[i].position = I915_READ(CURPOS(i));
15390                 error->cursor[i].base = I915_READ(CURBASE(i));
15391
15392                 error->plane[i].control = I915_READ(DSPCNTR(i));
15393                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15394                 if (INTEL_GEN(dev_priv) <= 3) {
15395                         error->plane[i].size = I915_READ(DSPSIZE(i));
15396                         error->plane[i].pos = I915_READ(DSPPOS(i));
15397                 }
15398                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15399                         error->plane[i].addr = I915_READ(DSPADDR(i));
15400                 if (INTEL_GEN(dev_priv) >= 4) {
15401                         error->plane[i].surface = I915_READ(DSPSURF(i));
15402                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15403                 }
15404
15405                 error->pipe[i].source = I915_READ(PIPESRC(i));
15406
15407                 if (HAS_GMCH_DISPLAY(dev_priv))
15408                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15409         }
15410
15411         /* Note: this does not include DSI transcoders. */
15412         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15413         if (HAS_DDI(dev_priv))
15414                 error->num_transcoders++; /* Account for eDP. */
15415
15416         for (i = 0; i < error->num_transcoders; i++) {
15417                 enum transcoder cpu_transcoder = transcoders[i];
15418
15419                 error->transcoder[i].power_domain_on =
15420                         __intel_display_power_is_enabled(dev_priv,
15421                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15422                 if (!error->transcoder[i].power_domain_on)
15423                         continue;
15424
15425                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15426
15427                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15428                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15429                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15430                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15431                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15432                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15433                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15434         }
15435
15436         return error;
15437 }
15438
15439 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15440
15441 void
15442 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15443                                 struct intel_display_error_state *error)
15444 {
15445         struct drm_i915_private *dev_priv = m->i915;
15446         int i;
15447
15448         if (!error)
15449                 return;
15450
15451         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15452         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15453                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15454                            error->power_well_driver);
15455         for_each_pipe(dev_priv, i) {
15456                 err_printf(m, "Pipe [%d]:\n", i);
15457                 err_printf(m, "  Power: %s\n",
15458                            onoff(error->pipe[i].power_domain_on));
15459                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15460                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15461
15462                 err_printf(m, "Plane [%d]:\n", i);
15463                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15464                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15465                 if (INTEL_GEN(dev_priv) <= 3) {
15466                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15467                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15468                 }
15469                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15470                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15471                 if (INTEL_GEN(dev_priv) >= 4) {
15472                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15473                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15474                 }
15475
15476                 err_printf(m, "Cursor [%d]:\n", i);
15477                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15478                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15479                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15480         }
15481
15482         for (i = 0; i < error->num_transcoders; i++) {
15483                 err_printf(m, "CPU transcoder: %s\n",
15484                            transcoder_name(error->transcoder[i].cpu_transcoder));
15485                 err_printf(m, "  Power: %s\n",
15486                            onoff(error->transcoder[i].power_domain_on));
15487                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15488                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15489                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15490                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15491                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15492                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15493                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15494         }
15495 }
15496
15497 #endif