drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #include "drm_crtc_helper.h"
  34
  35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  36
  37 typedef struct {
  38     /* given values */
  39     int n;
  40     int m1, m2;
  41     int p1, p2;
  42     /* derived values */
  43     int dot;
  44     int vco;
  45     int m;
  46     int p;
  47 } intel_clock_t;
  48
  49 typedef struct {
  50     int min, max;
  51 } intel_range_t;
  52
  53 typedef struct {
  54     int dot_limit;
  55     int p2_slow, p2_fast;
  56 } intel_p2_t;
  57
  58 #define INTEL_P2_NUM                  2
  59 typedef struct intel_limit intel_limit_t;
  60 struct intel_limit {
  61     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  62     intel_p2_t      p2;
  63     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64                       int, int, intel_clock_t *);
  65 };
  66
  67 #define I8XX_DOT_MIN              25000
  68 #define I8XX_DOT_MAX             350000
  69 #define I8XX_VCO_MIN             930000
  70 #define I8XX_VCO_MAX            1400000
  71 #define I8XX_N_MIN                    3
  72 #define I8XX_N_MAX                   16
  73 #define I8XX_M_MIN                   96
  74 #define I8XX_M_MAX                  140
  75 #define I8XX_M1_MIN                  18
  76 #define I8XX_M1_MAX                  26
  77 #define I8XX_M2_MIN                   6
  78 #define I8XX_M2_MAX                  16
  79 #define I8XX_P_MIN                    4
  80 #define I8XX_P_MAX                  128
  81 #define I8XX_P1_MIN                   2
  82 #define I8XX_P1_MAX                  33
  83 #define I8XX_P1_LVDS_MIN              1
  84 #define I8XX_P1_LVDS_MAX              6
  85 #define I8XX_P2_SLOW                  4
  86 #define I8XX_P2_FAST                  2
  87 #define I8XX_P2_LVDS_SLOW             14
  88 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  89 #define I8XX_P2_SLOW_LIMIT       165000
  90
  91 #define I9XX_DOT_MIN              20000
  92 #define I9XX_DOT_MAX             400000
  93 #define I9XX_VCO_MIN            1400000
  94 #define I9XX_VCO_MAX            2800000
  95 #define IGD_VCO_MIN             1700000
  96 #define IGD_VCO_MAX             3500000
  97 #define I9XX_N_MIN                    1
  98 #define I9XX_N_MAX                    6
  99 /* IGD's Ncounter is a ring counter */
 100 #define IGD_N_MIN                     3
 101 #define IGD_N_MAX                     6
 102 #define I9XX_M_MIN                   70
 103 #define I9XX_M_MAX                  120
 104 #define IGD_M_MIN                     2
 105 #define IGD_M_MAX                   256
 106 #define I9XX_M1_MIN                  10
 107 #define I9XX_M1_MAX                  22
 108 #define I9XX_M2_MIN                   5
 109 #define I9XX_M2_MAX                   9
 110 /* IGD M1 is reserved, and must be 0 */
 111 #define IGD_M1_MIN                    0
 112 #define IGD_M1_MAX                    0
 113 #define IGD_M2_MIN                    0
 114 #define IGD_M2_MAX                    254
 115 #define I9XX_P_SDVO_DAC_MIN           5
 116 #define I9XX_P_SDVO_DAC_MAX          80
 117 #define I9XX_P_LVDS_MIN               7
 118 #define I9XX_P_LVDS_MAX              98
 119 #define IGD_P_LVDS_MIN                7
 120 #define IGD_P_LVDS_MAX               112
 121 #define I9XX_P1_MIN                   1
 122 #define I9XX_P1_MAX                   8
 123 #define I9XX_P2_SDVO_DAC_SLOW                10
 124 #define I9XX_P2_SDVO_DAC_FAST                 5
 125 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 126 #define I9XX_P2_LVDS_SLOW                    14
 127 #define I9XX_P2_LVDS_FAST                     7
 128 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 129
 130 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 131 #define INTEL_LIMIT_I8XX_LVDS       1
 132 #define INTEL_LIMIT_I9XX_SDVO_DAC   2
 133 #define INTEL_LIMIT_I9XX_LVDS       3
 134 #define INTEL_LIMIT_G4X_SDVO        4
 135 #define INTEL_LIMIT_G4X_HDMI_DAC   5
 136 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
 137 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
 138 #define INTEL_LIMIT_IGD_SDVO_DAC    8
 139 #define INTEL_LIMIT_IGD_LVDS        9
 140
 141 /*The parameter is for SDVO on G4x platform*/
 142 #define G4X_DOT_SDVO_MIN           25000
 143 #define G4X_DOT_SDVO_MAX           270000
 144 #define G4X_VCO_MIN                1750000
 145 #define G4X_VCO_MAX                3500000
 146 #define G4X_N_SDVO_MIN             1
 147 #define G4X_N_SDVO_MAX             4
 148 #define G4X_M_SDVO_MIN             104
 149 #define G4X_M_SDVO_MAX             138
 150 #define G4X_M1_SDVO_MIN            17
 151 #define G4X_M1_SDVO_MAX            23
 152 #define G4X_M2_SDVO_MIN            5
 153 #define G4X_M2_SDVO_MAX            11
 154 #define G4X_P_SDVO_MIN             10
 155 #define G4X_P_SDVO_MAX             30
 156 #define G4X_P1_SDVO_MIN            1
 157 #define G4X_P1_SDVO_MAX            3
 158 #define G4X_P2_SDVO_SLOW           10
 159 #define G4X_P2_SDVO_FAST           10
 160 #define G4X_P2_SDVO_LIMIT          270000
 161
 162 /*The parameter is for HDMI_DAC on G4x platform*/
 163 #define G4X_DOT_HDMI_DAC_MIN           22000
 164 #define G4X_DOT_HDMI_DAC_MAX           400000
 165 #define G4X_N_HDMI_DAC_MIN             1
 166 #define G4X_N_HDMI_DAC_MAX             4
 167 #define G4X_M_HDMI_DAC_MIN             104
 168 #define G4X_M_HDMI_DAC_MAX             138
 169 #define G4X_M1_HDMI_DAC_MIN            16
 170 #define G4X_M1_HDMI_DAC_MAX            23
 171 #define G4X_M2_HDMI_DAC_MIN            5
 172 #define G4X_M2_HDMI_DAC_MAX            11
 173 #define G4X_P_HDMI_DAC_MIN             5
 174 #define G4X_P_HDMI_DAC_MAX             80
 175 #define G4X_P1_HDMI_DAC_MIN            1
 176 #define G4X_P1_HDMI_DAC_MAX            8
 177 #define G4X_P2_HDMI_DAC_SLOW           10
 178 #define G4X_P2_HDMI_DAC_FAST           5
 179 #define G4X_P2_HDMI_DAC_LIMIT          165000
 180
 181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 199
 200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 218
 219 static bool
 220 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 221                     int target, int refclk, intel_clock_t *best_clock);
 222 static bool
 223 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 224                         int target, int refclk, intel_clock_t *best_clock);
 225
 226 static const intel_limit_t intel_limits[] = {
 227     { /* INTEL_LIMIT_I8XX_DVO_DAC */
 228         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 229         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 230         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 231         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 232         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 233         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 234         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 235         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 236         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 237                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 238         .find_pll = intel_find_best_PLL,
 239     },
 240     { /* INTEL_LIMIT_I8XX_LVDS */
 241         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 242         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 243         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 244         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 245         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 246         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 247         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 248         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 249         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 250                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 251         .find_pll = intel_find_best_PLL,
 252     },
 253     { /* INTEL_LIMIT_I9XX_SDVO_DAC */
 254         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 255         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 256         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 257         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 258         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 259         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 260         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 261         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 262         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 263                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 264         .find_pll = intel_find_best_PLL,
 265     },
 266     { /* INTEL_LIMIT_I9XX_LVDS */
 267         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 268         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 269         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 270         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 271         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 272         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 273         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 274         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 275         /* The single-channel range is 25-112Mhz, and dual-channel
 276          * is 80-224Mhz.  Prefer single channel as much as possible.
 277          */
 278         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 279                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 280         .find_pll = intel_find_best_PLL,
 281     },
 282     /* below parameter and function is for G4X Chipset Family*/
 283     { /* INTEL_LIMIT_G4X_SDVO */
 284         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 285         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 286         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 287         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 288         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 289         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 290         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 291         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 292         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 293                  .p2_slow = G4X_P2_SDVO_SLOW,
 294                  .p2_fast = G4X_P2_SDVO_FAST
 295         },
 296         .find_pll = intel_g4x_find_best_PLL,
 297     },
 298     { /* INTEL_LIMIT_G4X_HDMI_DAC */
 299         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 300         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 301         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 302         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 303         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 304         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 305         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 306         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 307         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 308                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 309                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 310         },
 311         .find_pll = intel_g4x_find_best_PLL,
 312     },
 313     { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
 314         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 315                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 316         .vco = { .min = G4X_VCO_MIN,
 317                  .max = G4X_VCO_MAX },
 318         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 319                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 320         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 321                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 322         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 323                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 324         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 325                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 326         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 327                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 328         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 329                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 330         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 331                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 332                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 333         },
 334         .find_pll = intel_g4x_find_best_PLL,
 335     },
 336     { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
 337         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 338                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 339         .vco = { .min = G4X_VCO_MIN,
 340                  .max = G4X_VCO_MAX },
 341         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 342                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 343         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 344                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 345         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 346                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 347         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 348                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 349         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 350                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 351         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 352                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 353         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 354                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 355                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 356         },
 357         .find_pll = intel_g4x_find_best_PLL,
 358     },
 359     { /* INTEL_LIMIT_IGD_SDVO */
 360         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 361         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 362         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 363         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 364         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 365         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 366         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 367         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 368         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 369                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 370         .find_pll = intel_find_best_PLL,
 371     },
 372     { /* INTEL_LIMIT_IGD_LVDS */
 373         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 374         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 375         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 376         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 377         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 378         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 379         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 380         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 381         /* IGD only supports single-channel mode. */
 382         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 384         .find_pll = intel_find_best_PLL,
 385     },
 386
 387 };
 388
 389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 397                     LVDS_CLKB_POWER_UP)
 398                         /* LVDS with dual channel */
 399                         limit = &intel_limits
 400                                         [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
 401                 else
 402                         /* LVDS with dual channel */
 403                         limit = &intel_limits
 404                                         [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 406                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 407                 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 409                 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
 410         } else /* The option is for other outputs */
 411                 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 412
 413         return limit;
 414 }
 415
 416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 417 {
 418         struct drm_device *dev = crtc->dev;
 419         const intel_limit_t *limit;
 420
 421         if (IS_G4X(dev)) {
 422                 limit = intel_g4x_limit(crtc);
 423         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
 426                 else
 427                         limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 428         } else if (IS_IGD(dev)) {
 429                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 430                         limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
 431                 else
 432                         limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
 433         } else {
 434                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 435                         limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
 436                 else
 437                         limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
 438         }
 439         return limit;
 440 }
 441
 442 /* m1 is reserved as 0 in IGD, n is a ring counter */
 443 static void igd_clock(int refclk, intel_clock_t *clock)
 444 {
 445         clock->m = clock->m2 + 2;
 446         clock->p = clock->p1 * clock->p2;
 447         clock->vco = refclk * clock->m / clock->n;
 448         clock->dot = clock->vco / clock->p;
 449 }
 450
 451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 452 {
 453         if (IS_IGD(dev)) {
 454                 igd_clock(refclk, clock);
 455                 return;
 456         }
 457         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 458         clock->p = clock->p1 * clock->p2;
 459         clock->vco = refclk * clock->m / (clock->n + 2);
 460         clock->dot = clock->vco / clock->p;
 461 }
 462
 463 /**
 464  * Returns whether any output on the specified pipe is of the specified type
 465  */
 466 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 467 {
 468     struct drm_device *dev = crtc->dev;
 469     struct drm_mode_config *mode_config = &dev->mode_config;
 470     struct drm_connector *l_entry;
 471
 472     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 473             if (l_entry->encoder &&
 474                 l_entry->encoder->crtc == crtc) {
 475                     struct intel_output *intel_output = to_intel_output(l_entry);
 476                     if (intel_output->type == type)
 477                             return true;
 478             }
 479     }
 480     return false;
 481 }
 482
 483 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 484 /**
 485  * Returns whether the given set of divisors are valid for a given refclk with
 486  * the given connectors.
 487  */
 488
 489 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 490 {
 491         const intel_limit_t *limit = intel_limit (crtc);
 492         struct drm_device *dev = crtc->dev;
 493
 494         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 495                 INTELPllInvalid ("p1 out of range\n");
 496         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 497                 INTELPllInvalid ("p out of range\n");
 498         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 499                 INTELPllInvalid ("m2 out of range\n");
 500         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 501                 INTELPllInvalid ("m1 out of range\n");
 502         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 503                 INTELPllInvalid ("m1 <= m2\n");
 504         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 505                 INTELPllInvalid ("m out of range\n");
 506         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 507                 INTELPllInvalid ("n out of range\n");
 508         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 509                 INTELPllInvalid ("vco out of range\n");
 510         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 511          * connector, etc., rather than just a single range.
 512          */
 513         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 514                 INTELPllInvalid ("dot out of range\n");
 515
 516         return true;
 517 }
 518
 519 static bool
 520 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 521                     int target, int refclk, intel_clock_t *best_clock)
 522
 523 {
 524         struct drm_device *dev = crtc->dev;
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         intel_clock_t clock;
 527         int err = target;
 528
 529         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 530             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 531                 /*
 532                  * For LVDS, if the panel is on, just rely on its current
 533                  * settings for dual-channel.  We haven't figured out how to
 534                  * reliably set up different single/dual channel state, if we
 535                  * even can.
 536                  */
 537                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 538                     LVDS_CLKB_POWER_UP)
 539                         clock.p2 = limit->p2.p2_fast;
 540                 else
 541                         clock.p2 = limit->p2.p2_slow;
 542         } else {
 543                 if (target < limit->p2.dot_limit)
 544                         clock.p2 = limit->p2.p2_slow;
 545                 else
 546                         clock.p2 = limit->p2.p2_fast;
 547         }
 548
 549         memset (best_clock, 0, sizeof (*best_clock));
 550
 551         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 552                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 553                         /* m1 is always 0 in IGD */
 554                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 555                                 break;
 556                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 557                              clock.n++) {
 558                                 for (clock.p1 = limit->p1.min;
 559                                      clock.p1 <= limit->p1.max; clock.p1++) {
 560                                         int this_err;
 561
 562                                         intel_clock(dev, refclk, &clock);
 563
 564                                         if (!intel_PLL_is_valid(crtc, &clock))
 565                                                 continue;
 566
 567                                         this_err = abs(clock.dot - target);
 568                                         if (this_err < err) {
 569                                                 *best_clock = clock;
 570                                                 err = this_err;
 571                                         }
 572                                 }
 573                         }
 574                 }
 575         }
 576
 577         return (err != target);
 578 }
 579
 580 static bool
 581 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 582                         int target, int refclk, intel_clock_t *best_clock)
 583 {
 584         struct drm_device *dev = crtc->dev;
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         intel_clock_t clock;
 587         int max_n;
 588         bool found;
 589         /* approximately equals target * 0.00488 */
 590         int err_most = (target >> 8) + (target >> 10);
 591         found = false;
 592
 593         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 594                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 595                     LVDS_CLKB_POWER_UP)
 596                         clock.p2 = limit->p2.p2_fast;
 597                 else
 598                         clock.p2 = limit->p2.p2_slow;
 599         } else {
 600                 if (target < limit->p2.dot_limit)
 601                         clock.p2 = limit->p2.p2_slow;
 602                 else
 603                         clock.p2 = limit->p2.p2_fast;
 604         }
 605
 606         memset(best_clock, 0, sizeof(*best_clock));
 607         max_n = limit->n.max;
 608         /* based on hardware requriment prefer smaller n to precision */
 609         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 610                 /* based on hardware requirment prefere larger m1,m2, p1 */
 611                 for (clock.m1 = limit->m1.max;
 612                      clock.m1 >= limit->m1.min; clock.m1--) {
 613                         for (clock.m2 = limit->m2.max;
 614                              clock.m2 >= limit->m2.min; clock.m2--) {
 615                                 for (clock.p1 = limit->p1.max;
 616                                      clock.p1 >= limit->p1.min; clock.p1--) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(crtc, &clock))
 621                                                 continue;
 622                                         this_err = abs(clock.dot - target) ;
 623                                         if (this_err < err_most) {
 624                                                 *best_clock = clock;
 625                                                 err_most = this_err;
 626                                                 max_n = clock.n;
 627                                                 found = true;
 628                                         }
 629                                 }
 630                         }
 631                 }
 632         }
 633
 634         return found;
 635 }
 636
 637 void
 638 intel_wait_for_vblank(struct drm_device *dev)
 639 {
 640         /* Wait for 20ms, i.e. one cycle at 50hz. */
 641         mdelay(20);
 642 }
 643
 644 static int
 645 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 646                     struct drm_framebuffer *old_fb)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         struct drm_i915_master_private *master_priv;
 651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 652         struct intel_framebuffer *intel_fb;
 653         struct drm_i915_gem_object *obj_priv;
 654         struct drm_gem_object *obj;
 655         int pipe = intel_crtc->pipe;
 656         unsigned long Start, Offset;
 657         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 658         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 659         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 660         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 661         u32 dspcntr, alignment;
 662         int ret;
 663
 664         /* no fb bound */
 665         if (!crtc->fb) {
 666                 DRM_DEBUG("No FB bound\n");
 667                 return 0;
 668         }
 669
 670         switch (pipe) {
 671         case 0:
 672         case 1:
 673                 break;
 674         default:
 675                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 676                 return -EINVAL;
 677         }
 678
 679         intel_fb = to_intel_framebuffer(crtc->fb);
 680         obj = intel_fb->obj;
 681         obj_priv = obj->driver_private;
 682
 683         switch (obj_priv->tiling_mode) {
 684         case I915_TILING_NONE:
 685                 alignment = 64 * 1024;
 686                 break;
 687         case I915_TILING_X:
 688                 /* pin() will align the object as required by fence */
 689                 alignment = 0;
 690                 break;
 691         case I915_TILING_Y:
 692                 /* FIXME: Is this true? */
 693                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 694                 return -EINVAL;
 695         default:
 696                 BUG();
 697         }
 698
 699         mutex_lock(&dev->struct_mutex);
 700         ret = i915_gem_object_pin(intel_fb->obj, alignment);
 701         if (ret != 0) {
 702                 mutex_unlock(&dev->struct_mutex);
 703                 return ret;
 704         }
 705
 706         ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
 707         if (ret != 0) {
 708                 i915_gem_object_unpin(intel_fb->obj);
 709                 mutex_unlock(&dev->struct_mutex);
 710                 return ret;
 711         }
 712
 713         dspcntr = I915_READ(dspcntr_reg);
 714         /* Mask out pixel format bits in case we change it */
 715         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 716         switch (crtc->fb->bits_per_pixel) {
 717         case 8:
 718                 dspcntr |= DISPPLANE_8BPP;
 719                 break;
 720         case 16:
 721                 if (crtc->fb->depth == 15)
 722                         dspcntr |= DISPPLANE_15_16BPP;
 723                 else
 724                         dspcntr |= DISPPLANE_16BPP;
 725                 break;
 726         case 24:
 727         case 32:
 728                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 729                 break;
 730         default:
 731                 DRM_ERROR("Unknown color depth\n");
 732                 i915_gem_object_unpin(intel_fb->obj);
 733                 mutex_unlock(&dev->struct_mutex);
 734                 return -EINVAL;
 735         }
 736         I915_WRITE(dspcntr_reg, dspcntr);
 737
 738         Start = obj_priv->gtt_offset;
 739         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 740
 741         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 742         I915_WRITE(dspstride, crtc->fb->pitch);
 743         if (IS_I965G(dev)) {
 744                 I915_WRITE(dspbase, Offset);
 745                 I915_READ(dspbase);
 746                 I915_WRITE(dspsurf, Start);
 747                 I915_READ(dspsurf);
 748         } else {
 749                 I915_WRITE(dspbase, Start + Offset);
 750                 I915_READ(dspbase);
 751         }
 752
 753         intel_wait_for_vblank(dev);
 754
 755         if (old_fb) {
 756                 intel_fb = to_intel_framebuffer(old_fb);
 757                 i915_gem_object_unpin(intel_fb->obj);
 758         }
 759         mutex_unlock(&dev->struct_mutex);
 760
 761         if (!dev->primary->master)
 762                 return 0;
 763
 764         master_priv = dev->primary->master->driver_priv;
 765         if (!master_priv->sarea_priv)
 766                 return 0;
 767
 768         if (pipe) {
 769                 master_priv->sarea_priv->pipeB_x = x;
 770                 master_priv->sarea_priv->pipeB_y = y;
 771         } else {
 772                 master_priv->sarea_priv->pipeA_x = x;
 773                 master_priv->sarea_priv->pipeA_y = y;
 774         }
 775
 776         return 0;
 777 }
 778
 779
 780
 781 /**
 782  * Sets the power management mode of the pipe and plane.
 783  *
 784  * This code should probably grow support for turning the cursor off and back
 785  * on appropriately at the same time as we're turning the pipe off/on.
 786  */
 787 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 788 {
 789         struct drm_device *dev = crtc->dev;
 790         struct drm_i915_master_private *master_priv;
 791         struct drm_i915_private *dev_priv = dev->dev_private;
 792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 793         int pipe = intel_crtc->pipe;
 794         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
 795         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 796         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
 797         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 798         u32 temp;
 799         bool enabled;
 800
 801         /* XXX: When our outputs are all unaware of DPMS modes other than off
 802          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 803          */
 804         switch (mode) {
 805         case DRM_MODE_DPMS_ON:
 806         case DRM_MODE_DPMS_STANDBY:
 807         case DRM_MODE_DPMS_SUSPEND:
 808                 /* Enable the DPLL */
 809                 temp = I915_READ(dpll_reg);
 810                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 811                         I915_WRITE(dpll_reg, temp);
 812                         I915_READ(dpll_reg);
 813                         /* Wait for the clocks to stabilize. */
 814                         udelay(150);
 815                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 816                         I915_READ(dpll_reg);
 817                         /* Wait for the clocks to stabilize. */
 818                         udelay(150);
 819                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 820                         I915_READ(dpll_reg);
 821                         /* Wait for the clocks to stabilize. */
 822                         udelay(150);
 823                 }
 824
 825                 /* Enable the pipe */
 826                 temp = I915_READ(pipeconf_reg);
 827                 if ((temp & PIPEACONF_ENABLE) == 0)
 828                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
 829
 830                 /* Enable the plane */
 831                 temp = I915_READ(dspcntr_reg);
 832                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 833                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
 834                         /* Flush the plane changes */
 835                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 836                 }
 837
 838                 intel_crtc_load_lut(crtc);
 839
 840                 /* Give the overlay scaler a chance to enable if it's on this pipe */
 841                 //intel_crtc_dpms_video(crtc, true); TODO
 842         break;
 843         case DRM_MODE_DPMS_OFF:
 844                 /* Give the overlay scaler a chance to disable if it's on this pipe */
 845                 //intel_crtc_dpms_video(crtc, FALSE); TODO
 846
 847                 /* Disable the VGA plane that we never use */
 848                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 849
 850                 /* Disable display plane */
 851                 temp = I915_READ(dspcntr_reg);
 852                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 853                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
 854                         /* Flush the plane changes */
 855                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 856                         I915_READ(dspbase_reg);
 857                 }
 858
 859                 if (!IS_I9XX(dev)) {
 860                         /* Wait for vblank for the disable to take effect */
 861                         intel_wait_for_vblank(dev);
 862                 }
 863
 864                 /* Next, disable display pipes */
 865                 temp = I915_READ(pipeconf_reg);
 866                 if ((temp & PIPEACONF_ENABLE) != 0) {
 867                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
 868                         I915_READ(pipeconf_reg);
 869                 }
 870
 871                 /* Wait for vblank for the disable to take effect. */
 872                 intel_wait_for_vblank(dev);
 873
 874                 temp = I915_READ(dpll_reg);
 875                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 876                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
 877                         I915_READ(dpll_reg);
 878                 }
 879
 880                 /* Wait for the clocks to turn off. */
 881                 udelay(150);
 882                 break;
 883         }
 884
 885         if (!dev->primary->master)
 886                 return;
 887
 888         master_priv = dev->primary->master->driver_priv;
 889         if (!master_priv->sarea_priv)
 890                 return;
 891
 892         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
 893
 894         switch (pipe) {
 895         case 0:
 896                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
 897                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
 898                 break;
 899         case 1:
 900                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
 901                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
 902                 break;
 903         default:
 904                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 905                 break;
 906         }
 907
 908         intel_crtc->dpms_mode = mode;
 909 }
 910
 911 static void intel_crtc_prepare (struct drm_crtc *crtc)
 912 {
 913         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 914         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 915 }
 916
 917 static void intel_crtc_commit (struct drm_crtc *crtc)
 918 {
 919         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 920         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 921 }
 922
 923 void intel_encoder_prepare (struct drm_encoder *encoder)
 924 {
 925         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 926         /* lvds has its own version of prepare see intel_lvds_prepare */
 927         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 928 }
 929
 930 void intel_encoder_commit (struct drm_encoder *encoder)
 931 {
 932         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 933         /* lvds has its own version of commit see intel_lvds_commit */
 934         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 935 }
 936
 937 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 938                                   struct drm_display_mode *mode,
 939                                   struct drm_display_mode *adjusted_mode)
 940 {
 941         return true;
 942 }
 943
 944
 945 /** Returns the core display clock speed for i830 - i945 */
 946 static int intel_get_core_clock_speed(struct drm_device *dev)
 947 {
 948
 949         /* Core clock values taken from the published datasheets.
 950          * The 830 may go up to 166 Mhz, which we should check.
 951          */
 952         if (IS_I945G(dev))
 953                 return 400000;
 954         else if (IS_I915G(dev))
 955                 return 333000;
 956         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
 957                 return 200000;
 958         else if (IS_I915GM(dev)) {
 959                 u16 gcfgc = 0;
 960
 961                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
 962
 963                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
 964                         return 133000;
 965                 else {
 966                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 967                         case GC_DISPLAY_CLOCK_333_MHZ:
 968                                 return 333000;
 969                         default:
 970                         case GC_DISPLAY_CLOCK_190_200_MHZ:
 971                                 return 190000;
 972                         }
 973                 }
 974         } else if (IS_I865G(dev))
 975                 return 266000;
 976         else if (IS_I855(dev)) {
 977                 u16 hpllcc = 0;
 978                 /* Assume that the hardware is in the high speed state.  This
 979                  * should be the default.
 980                  */
 981                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 982                 case GC_CLOCK_133_200:
 983                 case GC_CLOCK_100_200:
 984                         return 200000;
 985                 case GC_CLOCK_166_250:
 986                         return 250000;
 987                 case GC_CLOCK_100_133:
 988                         return 133000;
 989                 }
 990         } else /* 852, 830 */
 991                 return 133000;
 992
 993         return 0; /* Silence gcc warning */
 994 }
 995
 996
 997 /**
 998  * Return the pipe currently connected to the panel fitter,
 999  * or -1 if the panel fitter is not present or not in use
1000  */
1001 static int intel_panel_fitter_pipe (struct drm_device *dev)
1002 {
1003         struct drm_i915_private *dev_priv = dev->dev_private;
1004         u32  pfit_control;
1005
1006         /* i830 doesn't have a panel fitter */
1007         if (IS_I830(dev))
1008                 return -1;
1009
1010         pfit_control = I915_READ(PFIT_CONTROL);
1011
1012         /* See if the panel fitter is in use */
1013         if ((pfit_control & PFIT_ENABLE) == 0)
1014                 return -1;
1015
1016         /* 965 can place panel fitter on either pipe */
1017         if (IS_I965G(dev))
1018                 return (pfit_control >> 29) & 0x3;
1019
1020         /* older chips can only use pipe 1 */
1021         return 1;
1022 }
1023
1024 static int intel_crtc_mode_set(struct drm_crtc *crtc,
1025                                struct drm_display_mode *mode,
1026                                struct drm_display_mode *adjusted_mode,
1027                                int x, int y,
1028                                struct drm_framebuffer *old_fb)
1029 {
1030         struct drm_device *dev = crtc->dev;
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1033         int pipe = intel_crtc->pipe;
1034         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
1035         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1036         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
1037         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1038         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1039         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1040         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1041         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1042         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1043         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1044         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1045         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
1046         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
1047         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
1048         int refclk, num_outputs = 0;
1049         intel_clock_t clock;
1050         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1051         bool ok, is_sdvo = false, is_dvo = false;
1052         bool is_crt = false, is_lvds = false, is_tv = false;
1053         struct drm_mode_config *mode_config = &dev->mode_config;
1054         struct drm_connector *connector;
1055         const intel_limit_t *limit;
1056         int ret;
1057
1058         drm_vblank_pre_modeset(dev, pipe);
1059
1060         list_for_each_entry(connector, &mode_config->connector_list, head) {
1061                 struct intel_output *intel_output = to_intel_output(connector);
1062
1063                 if (!connector->encoder || connector->encoder->crtc != crtc)
1064                         continue;
1065
1066                 switch (intel_output->type) {
1067                 case INTEL_OUTPUT_LVDS:
1068                         is_lvds = true;
1069                         break;
1070                 case INTEL_OUTPUT_SDVO:
1071                 case INTEL_OUTPUT_HDMI:
1072                         is_sdvo = true;
1073                         if (intel_output->needs_tv_clock)
1074                                 is_tv = true;
1075                         break;
1076                 case INTEL_OUTPUT_DVO:
1077                         is_dvo = true;
1078                         break;
1079                 case INTEL_OUTPUT_TVOUT:
1080                         is_tv = true;
1081                         break;
1082                 case INTEL_OUTPUT_ANALOG:
1083                         is_crt = true;
1084                         break;
1085                 }
1086
1087                 num_outputs++;
1088         }
1089
1090         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1091                 refclk = dev_priv->lvds_ssc_freq * 1000;
1092                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1093         } else if (IS_I9XX(dev)) {
1094                 refclk = 96000;
1095         } else {
1096                 refclk = 48000;
1097         }
1098
1099         /*
1100          * Returns a set of divisors for the desired target clock with the given
1101          * refclk, or FALSE.  The returned values represent the clock equation:
1102          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1103          */
1104         limit = intel_limit(crtc);
1105         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1106         if (!ok) {
1107                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1108                 return -EINVAL;
1109         }
1110
1111         /* SDVO TV has fixed PLL values depend on its clock range,
1112            this mirrors vbios setting. */
1113         if (is_sdvo && is_tv) {
1114                 if (adjusted_mode->clock >= 100000
1115                                 && adjusted_mode->clock < 140500) {
1116                         clock.p1 = 2;
1117                         clock.p2 = 10;
1118                         clock.n = 3;
1119                         clock.m1 = 16;
1120                         clock.m2 = 8;
1121                 } else if (adjusted_mode->clock >= 140500
1122                                 && adjusted_mode->clock <= 200000) {
1123                         clock.p1 = 1;
1124                         clock.p2 = 10;
1125                         clock.n = 6;
1126                         clock.m1 = 12;
1127                         clock.m2 = 8;
1128                 }
1129         }
1130
1131         if (IS_IGD(dev))
1132                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1133         else
1134                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1135
1136         dpll = DPLL_VGA_MODE_DIS;
1137         if (IS_I9XX(dev)) {
1138                 if (is_lvds)
1139                         dpll |= DPLLB_MODE_LVDS;
1140                 else
1141                         dpll |= DPLLB_MODE_DAC_SERIAL;
1142                 if (is_sdvo) {
1143                         dpll |= DPLL_DVO_HIGH_SPEED;
1144                         if (IS_I945G(dev) || IS_I945GM(dev)) {
1145                                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1146                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1147                         }
1148                 }
1149
1150                 /* compute bitmask from p1 value */
1151                 if (IS_IGD(dev))
1152                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1153                 else
1154                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1155                 switch (clock.p2) {
1156                 case 5:
1157                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1158                         break;
1159                 case 7:
1160                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1161                         break;
1162                 case 10:
1163                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1164                         break;
1165                 case 14:
1166                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1167                         break;
1168                 }
1169                 if (IS_I965G(dev))
1170                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1171         } else {
1172                 if (is_lvds) {
1173                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1174                 } else {
1175                         if (clock.p1 == 2)
1176                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1177                         else
1178                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1179                         if (clock.p2 == 4)
1180                                 dpll |= PLL_P2_DIVIDE_BY_4;
1181                 }
1182         }
1183
1184         if (is_sdvo && is_tv)
1185                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1186         else if (is_tv)
1187                 /* XXX: just matching BIOS for now */
1188                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1189                 dpll |= 3;
1190         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1191                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1192         else
1193                 dpll |= PLL_REF_INPUT_DREFCLK;
1194
1195         /* setup pipeconf */
1196         pipeconf = I915_READ(pipeconf_reg);
1197
1198         /* Set up the display plane register */
1199         dspcntr = DISPPLANE_GAMMA_ENABLE;
1200
1201         if (pipe == 0)
1202                 dspcntr |= DISPPLANE_SEL_PIPE_A;
1203         else
1204                 dspcntr |= DISPPLANE_SEL_PIPE_B;
1205
1206         if (pipe == 0 && !IS_I965G(dev)) {
1207                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1208                  * core speed.
1209                  *
1210                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1211                  * pipe == 0 check?
1212                  */
1213                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1214                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1215                 else
1216                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1217         }
1218
1219         dspcntr |= DISPLAY_PLANE_ENABLE;
1220         pipeconf |= PIPEACONF_ENABLE;
1221         dpll |= DPLL_VCO_ENABLE;
1222
1223
1224         /* Disable the panel fitter if it was on our pipe */
1225         if (intel_panel_fitter_pipe(dev) == pipe)
1226                 I915_WRITE(PFIT_CONTROL, 0);
1227
1228         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1229         drm_mode_debug_printmodeline(mode);
1230
1231
1232         if (dpll & DPLL_VCO_ENABLE) {
1233                 I915_WRITE(fp_reg, fp);
1234                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1235                 I915_READ(dpll_reg);
1236                 udelay(150);
1237         }
1238
1239         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1240          * This is an exception to the general rule that mode_set doesn't turn
1241          * things on.
1242          */
1243         if (is_lvds) {
1244                 u32 lvds = I915_READ(LVDS);
1245
1246                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1247                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1248                  * set the DPLLs for dual-channel mode or not.
1249                  */
1250                 if (clock.p2 == 7)
1251                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1252                 else
1253                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1254
1255                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1256                  * appropriately here, but we need to look more thoroughly into how
1257                  * panels behave in the two modes.
1258                  */
1259
1260                 I915_WRITE(LVDS, lvds);
1261                 I915_READ(LVDS);
1262         }
1263
1264         I915_WRITE(fp_reg, fp);
1265         I915_WRITE(dpll_reg, dpll);
1266         I915_READ(dpll_reg);
1267         /* Wait for the clocks to stabilize. */
1268         udelay(150);
1269
1270         if (IS_I965G(dev)) {
1271                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1272                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1273                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1274         } else {
1275                 /* write it again -- the BIOS does, after all */
1276                 I915_WRITE(dpll_reg, dpll);
1277         }
1278         I915_READ(dpll_reg);
1279         /* Wait for the clocks to stabilize. */
1280         udelay(150);
1281
1282         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1283                    ((adjusted_mode->crtc_htotal - 1) << 16));
1284         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1285                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1286         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1287                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1288         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1289                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1290         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1291                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1292         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1293                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1294         /* pipesrc and dspsize control the size that is scaled from, which should
1295          * always be the user's requested size.
1296          */
1297         I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
1298         I915_WRITE(dsppos_reg, 0);
1299         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1300         I915_WRITE(pipeconf_reg, pipeconf);
1301         I915_READ(pipeconf_reg);
1302
1303         intel_wait_for_vblank(dev);
1304
1305         I915_WRITE(dspcntr_reg, dspcntr);
1306
1307         /* Flush the plane changes */
1308         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1309         if (ret != 0)
1310             return ret;
1311
1312         drm_vblank_post_modeset(dev, pipe);
1313
1314         return 0;
1315 }
1316
1317 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1318 void intel_crtc_load_lut(struct drm_crtc *crtc)
1319 {
1320         struct drm_device *dev = crtc->dev;
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1323         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1324         int i;
1325
1326         /* The clocks have to be on to load the palette. */
1327         if (!crtc->enabled)
1328                 return;
1329
1330         for (i = 0; i < 256; i++) {
1331                 I915_WRITE(palreg + 4 * i,
1332                            (intel_crtc->lut_r[i] << 16) |
1333                            (intel_crtc->lut_g[i] << 8) |
1334                            intel_crtc->lut_b[i]);
1335         }
1336 }
1337
1338 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1339                                  struct drm_file *file_priv,
1340                                  uint32_t handle,
1341                                  uint32_t width, uint32_t height)
1342 {
1343         struct drm_device *dev = crtc->dev;
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1346         struct drm_gem_object *bo;
1347         struct drm_i915_gem_object *obj_priv;
1348         int pipe = intel_crtc->pipe;
1349         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1350         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1351         uint32_t temp;
1352         size_t addr;
1353         int ret;
1354
1355         DRM_DEBUG("\n");
1356
1357         /* if we want to turn off the cursor ignore width and height */
1358         if (!handle) {
1359                 DRM_DEBUG("cursor off\n");
1360                 temp = CURSOR_MODE_DISABLE;
1361                 addr = 0;
1362                 bo = NULL;
1363                 mutex_lock(&dev->struct_mutex);
1364                 goto finish;
1365         }
1366
1367         /* Currently we only support 64x64 cursors */
1368         if (width != 64 || height != 64) {
1369                 DRM_ERROR("we currently only support 64x64 cursors\n");
1370                 return -EINVAL;
1371         }
1372
1373         bo = drm_gem_object_lookup(dev, file_priv, handle);
1374         if (!bo)
1375                 return -ENOENT;
1376
1377         obj_priv = bo->driver_private;
1378
1379         if (bo->size < width * height * 4) {
1380                 DRM_ERROR("buffer is to small\n");
1381                 ret = -ENOMEM;
1382                 goto fail;
1383         }
1384
1385         /* we only need to pin inside GTT if cursor is non-phy */
1386         mutex_lock(&dev->struct_mutex);
1387         if (!dev_priv->cursor_needs_physical) {
1388                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1389                 if (ret) {
1390                         DRM_ERROR("failed to pin cursor bo\n");
1391                         goto fail_locked;
1392                 }
1393                 addr = obj_priv->gtt_offset;
1394         } else {
1395                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1396                 if (ret) {
1397                         DRM_ERROR("failed to attach phys object\n");
1398                         goto fail_locked;
1399                 }
1400                 addr = obj_priv->phys_obj->handle->busaddr;
1401         }
1402
1403         temp = 0;
1404         /* set the pipe for the cursor */
1405         temp |= (pipe << 28);
1406         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1407
1408  finish:
1409         I915_WRITE(control, temp);
1410         I915_WRITE(base, addr);
1411
1412         if (intel_crtc->cursor_bo) {
1413                 if (dev_priv->cursor_needs_physical) {
1414                         if (intel_crtc->cursor_bo != bo)
1415                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1416                 } else
1417                         i915_gem_object_unpin(intel_crtc->cursor_bo);
1418                 drm_gem_object_unreference(intel_crtc->cursor_bo);
1419         }
1420         mutex_unlock(&dev->struct_mutex);
1421
1422         intel_crtc->cursor_addr = addr;
1423         intel_crtc->cursor_bo = bo;
1424
1425         return 0;
1426 fail:
1427         mutex_lock(&dev->struct_mutex);
1428 fail_locked:
1429         drm_gem_object_unreference(bo);
1430         mutex_unlock(&dev->struct_mutex);
1431         return ret;
1432 }
1433
1434 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1435 {
1436         struct drm_device *dev = crtc->dev;
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1439         int pipe = intel_crtc->pipe;
1440         uint32_t temp = 0;
1441         uint32_t adder;
1442
1443         if (x < 0) {
1444                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1445                 x = -x;
1446         }
1447         if (y < 0) {
1448                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1449                 y = -y;
1450         }
1451
1452         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1453         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1454
1455         adder = intel_crtc->cursor_addr;
1456         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1457         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1458
1459         return 0;
1460 }
1461
1462 /** Sets the color ramps on behalf of RandR */
1463 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1464                                  u16 blue, int regno)
1465 {
1466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1467
1468         intel_crtc->lut_r[regno] = red >> 8;
1469         intel_crtc->lut_g[regno] = green >> 8;
1470         intel_crtc->lut_b[regno] = blue >> 8;
1471 }
1472
1473 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1474                                  u16 *blue, uint32_t size)
1475 {
1476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1477         int i;
1478
1479         if (size != 256)
1480                 return;
1481
1482         for (i = 0; i < 256; i++) {
1483                 intel_crtc->lut_r[i] = red[i] >> 8;
1484                 intel_crtc->lut_g[i] = green[i] >> 8;
1485                 intel_crtc->lut_b[i] = blue[i] >> 8;
1486         }
1487
1488         intel_crtc_load_lut(crtc);
1489 }
1490
1491 /**
1492  * Get a pipe with a simple mode set on it for doing load-based monitor
1493  * detection.
1494  *
1495  * It will be up to the load-detect code to adjust the pipe as appropriate for
1496  * its requirements.  The pipe will be connected to no other outputs.
1497  *
1498  * Currently this code will only succeed if there is a pipe with no outputs
1499  * configured for it.  In the future, it could choose to temporarily disable
1500  * some outputs to free up a pipe for its use.
1501  *
1502  * \return crtc, or NULL if no pipes are available.
1503  */
1504
1505 /* VESA 640x480x72Hz mode to set on the pipe */
1506 static struct drm_display_mode load_detect_mode = {
1507         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1508                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1509 };
1510
1511 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1512                                             struct drm_display_mode *mode,
1513                                             int *dpms_mode)
1514 {
1515         struct intel_crtc *intel_crtc;
1516         struct drm_crtc *possible_crtc;
1517         struct drm_crtc *supported_crtc =NULL;
1518         struct drm_encoder *encoder = &intel_output->enc;
1519         struct drm_crtc *crtc = NULL;
1520         struct drm_device *dev = encoder->dev;
1521         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1522         struct drm_crtc_helper_funcs *crtc_funcs;
1523         int i = -1;
1524
1525         /*
1526          * Algorithm gets a little messy:
1527          *   - if the connector already has an assigned crtc, use it (but make
1528          *     sure it's on first)
1529          *   - try to find the first unused crtc that can drive this connector,
1530          *     and use that if we find one
1531          *   - if there are no unused crtcs available, try to use the first
1532          *     one we found that supports the connector
1533          */
1534
1535         /* See if we already have a CRTC for this connector */
1536         if (encoder->crtc) {
1537                 crtc = encoder->crtc;
1538                 /* Make sure the crtc and connector are running */
1539                 intel_crtc = to_intel_crtc(crtc);
1540                 *dpms_mode = intel_crtc->dpms_mode;
1541                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1542                         crtc_funcs = crtc->helper_private;
1543                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1544                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1545                 }
1546                 return crtc;
1547         }
1548
1549         /* Find an unused one (if possible) */
1550         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1551                 i++;
1552                 if (!(encoder->possible_crtcs & (1 << i)))
1553                         continue;
1554                 if (!possible_crtc->enabled) {
1555                         crtc = possible_crtc;
1556                         break;
1557                 }
1558                 if (!supported_crtc)
1559                         supported_crtc = possible_crtc;
1560         }
1561
1562         /*
1563          * If we didn't find an unused CRTC, don't use any.
1564          */
1565         if (!crtc) {
1566                 return NULL;
1567         }
1568
1569         encoder->crtc = crtc;
1570         intel_output->load_detect_temp = true;
1571
1572         intel_crtc = to_intel_crtc(crtc);
1573         *dpms_mode = intel_crtc->dpms_mode;
1574
1575         if (!crtc->enabled) {
1576                 if (!mode)
1577                         mode = &load_detect_mode;
1578                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
1579         } else {
1580                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1581                         crtc_funcs = crtc->helper_private;
1582                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1583                 }
1584
1585                 /* Add this connector to the crtc */
1586                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1587                 encoder_funcs->commit(encoder);
1588         }
1589         /* let the connector get through one full cycle before testing */
1590         intel_wait_for_vblank(dev);
1591
1592         return crtc;
1593 }
1594
1595 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1596 {
1597         struct drm_encoder *encoder = &intel_output->enc;
1598         struct drm_device *dev = encoder->dev;
1599         struct drm_crtc *crtc = encoder->crtc;
1600         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1601         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1602
1603         if (intel_output->load_detect_temp) {
1604                 encoder->crtc = NULL;
1605                 intel_output->load_detect_temp = false;
1606                 crtc->enabled = drm_helper_crtc_in_use(crtc);
1607                 drm_helper_disable_unused_functions(dev);
1608         }
1609
1610         /* Switch crtc and output back off if necessary */
1611         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1612                 if (encoder->crtc == crtc)
1613                         encoder_funcs->dpms(encoder, dpms_mode);
1614                 crtc_funcs->dpms(crtc, dpms_mode);
1615         }
1616 }
1617
1618 /* Returns the clock of the currently programmed mode of the given pipe. */
1619 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1620 {
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1623         int pipe = intel_crtc->pipe;
1624         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1625         u32 fp;
1626         intel_clock_t clock;
1627
1628         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1629                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1630         else
1631                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1632
1633         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1634         if (IS_IGD(dev)) {
1635                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
1636                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
1637         } else {
1638                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1639                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1640         }
1641
1642         if (IS_I9XX(dev)) {
1643                 if (IS_IGD(dev))
1644                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
1645                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
1646                 else
1647                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1648                                DPLL_FPA01_P1_POST_DIV_SHIFT);
1649
1650                 switch (dpll & DPLL_MODE_MASK) {
1651                 case DPLLB_MODE_DAC_SERIAL:
1652                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1653                                 5 : 10;
1654                         break;
1655                 case DPLLB_MODE_LVDS:
1656                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1657                                 7 : 14;
1658                         break;
1659                 default:
1660                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1661                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
1662                         return 0;
1663                 }
1664
1665                 /* XXX: Handle the 100Mhz refclk */
1666                 intel_clock(dev, 96000, &clock);
1667         } else {
1668                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1669
1670                 if (is_lvds) {
1671                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1672                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
1673                         clock.p2 = 14;
1674
1675                         if ((dpll & PLL_REF_INPUT_MASK) ==
1676                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1677                                 /* XXX: might not be 66MHz */
1678                                 intel_clock(dev, 66000, &clock);
1679                         } else
1680                                 intel_clock(dev, 48000, &clock);
1681                 } else {
1682                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
1683                                 clock.p1 = 2;
1684                         else {
1685                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1686                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1687                         }
1688                         if (dpll & PLL_P2_DIVIDE_BY_4)
1689                                 clock.p2 = 4;
1690                         else
1691                                 clock.p2 = 2;
1692
1693                         intel_clock(dev, 48000, &clock);
1694                 }
1695         }
1696
1697         /* XXX: It would be nice to validate the clocks, but we can't reuse
1698          * i830PllIsValid() because it relies on the xf86_config connector
1699          * configuration being accurate, which it isn't necessarily.
1700          */
1701
1702         return clock.dot;
1703 }
1704
1705 /** Returns the currently programmed mode of the given pipe. */
1706 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1707                                              struct drm_crtc *crtc)
1708 {
1709         struct drm_i915_private *dev_priv = dev->dev_private;
1710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1711         int pipe = intel_crtc->pipe;
1712         struct drm_display_mode *mode;
1713         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1714         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1715         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1716         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1717
1718         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1719         if (!mode)
1720                 return NULL;
1721
1722         mode->clock = intel_crtc_clock_get(dev, crtc);
1723         mode->hdisplay = (htot & 0xffff) + 1;
1724         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1725         mode->hsync_start = (hsync & 0xffff) + 1;
1726         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1727         mode->vdisplay = (vtot & 0xffff) + 1;
1728         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1729         mode->vsync_start = (vsync & 0xffff) + 1;
1730         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1731
1732         drm_mode_set_name(mode);
1733         drm_mode_set_crtcinfo(mode, 0);
1734
1735         return mode;
1736 }
1737
1738 static void intel_crtc_destroy(struct drm_crtc *crtc)
1739 {
1740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1741
1742         drm_crtc_cleanup(crtc);
1743         kfree(intel_crtc);
1744 }
1745
1746 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1747         .dpms = intel_crtc_dpms,
1748         .mode_fixup = intel_crtc_mode_fixup,
1749         .mode_set = intel_crtc_mode_set,
1750         .mode_set_base = intel_pipe_set_base,
1751         .prepare = intel_crtc_prepare,
1752         .commit = intel_crtc_commit,
1753 };
1754
1755 static const struct drm_crtc_funcs intel_crtc_funcs = {
1756         .cursor_set = intel_crtc_cursor_set,
1757         .cursor_move = intel_crtc_cursor_move,
1758         .gamma_set = intel_crtc_gamma_set,
1759         .set_config = drm_crtc_helper_set_config,
1760         .destroy = intel_crtc_destroy,
1761 };
1762
1763
1764 static void intel_crtc_init(struct drm_device *dev, int pipe)
1765 {
1766         struct intel_crtc *intel_crtc;
1767         int i;
1768
1769         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1770         if (intel_crtc == NULL)
1771                 return;
1772
1773         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1774
1775         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1776         intel_crtc->pipe = pipe;
1777         for (i = 0; i < 256; i++) {
1778                 intel_crtc->lut_r[i] = i;
1779                 intel_crtc->lut_g[i] = i;
1780                 intel_crtc->lut_b[i] = i;
1781         }
1782
1783         intel_crtc->cursor_addr = 0;
1784         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1785         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1786
1787         intel_crtc->mode_set.crtc = &intel_crtc->base;
1788         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1789         intel_crtc->mode_set.num_connectors = 0;
1790
1791         if (i915_fbpercrtc) {
1792
1793
1794
1795         }
1796 }
1797
1798 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1799 {
1800         struct drm_crtc *crtc = NULL;
1801
1802         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1803                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1804                 if (intel_crtc->pipe == pipe)
1805                         break;
1806         }
1807         return crtc;
1808 }
1809
1810 static int intel_connector_clones(struct drm_device *dev, int type_mask)
1811 {
1812         int index_mask = 0;
1813         struct drm_connector *connector;
1814         int entry = 0;
1815
1816         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1817                 struct intel_output *intel_output = to_intel_output(connector);
1818                 if (type_mask & (1 << intel_output->type))
1819                         index_mask |= (1 << entry);
1820                 entry++;
1821         }
1822         return index_mask;
1823 }
1824
1825
1826 static void intel_setup_outputs(struct drm_device *dev)
1827 {
1828         struct drm_i915_private *dev_priv = dev->dev_private;
1829         struct drm_connector *connector;
1830
1831         intel_crt_init(dev);
1832
1833         /* Set up integrated LVDS */
1834         if (IS_MOBILE(dev) && !IS_I830(dev))
1835                 intel_lvds_init(dev);
1836
1837         if (IS_I9XX(dev)) {
1838                 int found;
1839                 u32 reg;
1840
1841                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1842                         found = intel_sdvo_init(dev, SDVOB);
1843                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1844                                 intel_hdmi_init(dev, SDVOB);
1845                 }
1846
1847                 /* Before G4X SDVOC doesn't have its own detect register */
1848                 if (IS_G4X(dev))
1849                         reg = SDVOC;
1850                 else
1851                         reg = SDVOB;
1852
1853                 if (I915_READ(reg) & SDVO_DETECTED) {
1854                         found = intel_sdvo_init(dev, SDVOC);
1855                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1856                                 intel_hdmi_init(dev, SDVOC);
1857                 }
1858         } else
1859                 intel_dvo_init(dev);
1860
1861         if (IS_I9XX(dev) && IS_MOBILE(dev))
1862                 intel_tv_init(dev);
1863
1864         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1865                 struct intel_output *intel_output = to_intel_output(connector);
1866                 struct drm_encoder *encoder = &intel_output->enc;
1867                 int crtc_mask = 0, clone_mask = 0;
1868
1869                 /* valid crtcs */
1870                 switch(intel_output->type) {
1871                 case INTEL_OUTPUT_HDMI:
1872                         crtc_mask = ((1 << 0)|
1873                                      (1 << 1));
1874                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1875                         break;
1876                 case INTEL_OUTPUT_DVO:
1877                 case INTEL_OUTPUT_SDVO:
1878                         crtc_mask = ((1 << 0)|
1879                                      (1 << 1));
1880                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1881                                       (1 << INTEL_OUTPUT_DVO) |
1882                                       (1 << INTEL_OUTPUT_SDVO));
1883                         break;
1884                 case INTEL_OUTPUT_ANALOG:
1885                         crtc_mask = ((1 << 0)|
1886                                      (1 << 1));
1887                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1888                                       (1 << INTEL_OUTPUT_DVO) |
1889                                       (1 << INTEL_OUTPUT_SDVO));
1890                         break;
1891                 case INTEL_OUTPUT_LVDS:
1892                         crtc_mask = (1 << 1);
1893                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
1894                         break;
1895                 case INTEL_OUTPUT_TVOUT:
1896                         crtc_mask = ((1 << 0) |
1897                                      (1 << 1));
1898                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1899                         break;
1900                 }
1901                 encoder->possible_crtcs = crtc_mask;
1902                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1903         }
1904 }
1905
1906 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1907 {
1908         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1909         struct drm_device *dev = fb->dev;
1910
1911         if (fb->fbdev)
1912                 intelfb_remove(dev, fb);
1913
1914         drm_framebuffer_cleanup(fb);
1915         mutex_lock(&dev->struct_mutex);
1916         drm_gem_object_unreference(intel_fb->obj);
1917         mutex_unlock(&dev->struct_mutex);
1918
1919         kfree(intel_fb);
1920 }
1921
1922 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1923                                                 struct drm_file *file_priv,
1924                                                 unsigned int *handle)
1925 {
1926         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1927         struct drm_gem_object *object = intel_fb->obj;
1928
1929         return drm_gem_handle_create(file_priv, object, handle);
1930 }
1931
1932 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1933         .destroy = intel_user_framebuffer_destroy,
1934         .create_handle = intel_user_framebuffer_create_handle,
1935 };
1936
1937 int intel_framebuffer_create(struct drm_device *dev,
1938                              struct drm_mode_fb_cmd *mode_cmd,
1939                              struct drm_framebuffer **fb,
1940                              struct drm_gem_object *obj)
1941 {
1942         struct intel_framebuffer *intel_fb;
1943         int ret;
1944
1945         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1946         if (!intel_fb)
1947                 return -ENOMEM;
1948
1949         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1950         if (ret) {
1951                 DRM_ERROR("framebuffer init failed %d\n", ret);
1952                 return ret;
1953         }
1954
1955         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1956
1957         intel_fb->obj = obj;
1958
1959         *fb = &intel_fb->base;
1960
1961         return 0;
1962 }
1963
1964
1965 static struct drm_framebuffer *
1966 intel_user_framebuffer_create(struct drm_device *dev,
1967                               struct drm_file *filp,
1968                               struct drm_mode_fb_cmd *mode_cmd)
1969 {
1970         struct drm_gem_object *obj;
1971         struct drm_framebuffer *fb;
1972         int ret;
1973
1974         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1975         if (!obj)
1976                 return NULL;
1977
1978         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1979         if (ret) {
1980                 mutex_lock(&dev->struct_mutex);
1981                 drm_gem_object_unreference(obj);
1982                 mutex_unlock(&dev->struct_mutex);
1983                 return NULL;
1984         }
1985
1986         return fb;
1987 }
1988
1989 static const struct drm_mode_config_funcs intel_mode_funcs = {
1990         .fb_create = intel_user_framebuffer_create,
1991         .fb_changed = intelfb_probe,
1992 };
1993
1994 void intel_modeset_init(struct drm_device *dev)
1995 {
1996         int num_pipe;
1997         int i;
1998
1999         drm_mode_config_init(dev);
2000
2001         dev->mode_config.min_width = 0;
2002         dev->mode_config.min_height = 0;
2003
2004         dev->mode_config.funcs = (void *)&intel_mode_funcs;
2005
2006         if (IS_I965G(dev)) {
2007                 dev->mode_config.max_width = 8192;
2008                 dev->mode_config.max_height = 8192;
2009         } else {
2010                 dev->mode_config.max_width = 2048;
2011                 dev->mode_config.max_height = 2048;
2012         }
2013
2014         /* set memory base */
2015         if (IS_I9XX(dev))
2016                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
2017         else
2018                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
2019
2020         if (IS_MOBILE(dev) || IS_I9XX(dev))
2021                 num_pipe = 2;
2022         else
2023                 num_pipe = 1;
2024         DRM_DEBUG("%d display pipe%s available.\n",
2025                   num_pipe, num_pipe > 1 ? "s" : "");
2026
2027         for (i = 0; i < num_pipe; i++) {
2028                 intel_crtc_init(dev, i);
2029         }
2030
2031         intel_setup_outputs(dev);
2032 }
2033
2034 void intel_modeset_cleanup(struct drm_device *dev)
2035 {
2036         drm_mode_config_cleanup(dev);
2037 }
2038
2039
2040 /* current intel driver doesn't take advantage of encoders
2041    always give back the encoder for the connector
2042 */
2043 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2044 {
2045         struct intel_output *intel_output = to_intel_output(connector);
2046
2047         return &intel_output->enc;
2048 }