drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125
 126 struct intel_limit {
 127         struct {
 128                 int min, max;
 129         } dot, vco, n, m, m1, m2, p, p1;
 130
 131         struct {
 132                 int dot_limit;
 133                 int p2_slow, p2_fast;
 134         } p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 152                       const char *name, u32 reg, int ref_freq)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         mutex_lock(&dev_priv->sb_lock);
 158         val = vlv_cck_read(dev_priv, reg);
 159         mutex_unlock(&dev_priv->sb_lock);
 160
 161         divider = val & CCK_FREQUENCY_VALUES;
 162
 163         WARN((val & CCK_FREQUENCY_STATUS) !=
 164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 165              "%s change in progress\n", name);
 166
 167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 168 }
 169
 170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 171                            const char *name, u32 reg)
 172 {
 173         if (dev_priv->hpll_freq == 0)
 174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 175
 176         return vlv_get_cck_clock(dev_priv, name, reg,
 177                                  dev_priv->hpll_freq);
 178 }
 179
 180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 181 {
 182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 183                 return;
 184
 185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 186                                                       CCK_CZ_CLOCK_CONTROL);
 187
 188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 189 }
 190
 191 static inline u32 /* units of 100MHz */
 192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 193                     const struct intel_crtc_state *pipe_config)
 194 {
 195         if (HAS_DDI(dev_priv))
 196                 return pipe_config->port_clock; /* SPLL */
 197         else if (IS_GEN5(dev_priv))
 198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 199         else
 200                 return 270000;
 201 }
 202
 203 static const struct intel_limit intel_limits_i8xx_dac = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 908000, .max = 1512000 },
 206         .n = { .min = 2, .max = 16 },
 207         .m = { .min = 96, .max = 140 },
 208         .m1 = { .min = 18, .max = 26 },
 209         .m2 = { .min = 6, .max = 16 },
 210         .p = { .min = 4, .max = 128 },
 211         .p1 = { .min = 2, .max = 33 },
 212         .p2 = { .dot_limit = 165000,
 213                 .p2_slow = 4, .p2_fast = 2 },
 214 };
 215
 216 static const struct intel_limit intel_limits_i8xx_dvo = {
 217         .dot = { .min = 25000, .max = 350000 },
 218         .vco = { .min = 908000, .max = 1512000 },
 219         .n = { .min = 2, .max = 16 },
 220         .m = { .min = 96, .max = 140 },
 221         .m1 = { .min = 18, .max = 26 },
 222         .m2 = { .min = 6, .max = 16 },
 223         .p = { .min = 4, .max = 128 },
 224         .p1 = { .min = 2, .max = 33 },
 225         .p2 = { .dot_limit = 165000,
 226                 .p2_slow = 4, .p2_fast = 4 },
 227 };
 228
 229 static const struct intel_limit intel_limits_i8xx_lvds = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 908000, .max = 1512000 },
 232         .n = { .min = 2, .max = 16 },
 233         .m = { .min = 96, .max = 140 },
 234         .m1 = { .min = 18, .max = 26 },
 235         .m2 = { .min = 6, .max = 16 },
 236         .p = { .min = 4, .max = 128 },
 237         .p1 = { .min = 1, .max = 6 },
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 14, .p2_fast = 7 },
 240 };
 241
 242 static const struct intel_limit intel_limits_i9xx_sdvo = {
 243         .dot = { .min = 20000, .max = 400000 },
 244         .vco = { .min = 1400000, .max = 2800000 },
 245         .n = { .min = 1, .max = 6 },
 246         .m = { .min = 70, .max = 120 },
 247         .m1 = { .min = 8, .max = 18 },
 248         .m2 = { .min = 3, .max = 7 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i9xx_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1400000, .max = 2800000 },
 258         .n = { .min = 1, .max = 6 },
 259         .m = { .min = 70, .max = 120 },
 260         .m1 = { .min = 8, .max = 18 },
 261         .m2 = { .min = 3, .max = 7 },
 262         .p = { .min = 7, .max = 98 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 7 },
 266 };
 267
 268
 269 static const struct intel_limit intel_limits_g4x_sdvo = {
 270         .dot = { .min = 25000, .max = 270000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 17, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 10, .max = 30 },
 277         .p1 = { .min = 1, .max = 3},
 278         .p2 = { .dot_limit = 270000,
 279                 .p2_slow = 10,
 280                 .p2_fast = 10
 281         },
 282 };
 283
 284 static const struct intel_limit intel_limits_g4x_hdmi = {
 285         .dot = { .min = 22000, .max = 400000 },
 286         .vco = { .min = 1750000, .max = 3500000},
 287         .n = { .min = 1, .max = 4 },
 288         .m = { .min = 104, .max = 138 },
 289         .m1 = { .min = 16, .max = 23 },
 290         .m2 = { .min = 5, .max = 11 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8},
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 298         .dot = { .min = 20000, .max = 115000 },
 299         .vco = { .min = 1750000, .max = 3500000 },
 300         .n = { .min = 1, .max = 3 },
 301         .m = { .min = 104, .max = 138 },
 302         .m1 = { .min = 17, .max = 23 },
 303         .m2 = { .min = 5, .max = 11 },
 304         .p = { .min = 28, .max = 112 },
 305         .p1 = { .min = 2, .max = 8 },
 306         .p2 = { .dot_limit = 0,
 307                 .p2_slow = 14, .p2_fast = 14
 308         },
 309 };
 310
 311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 312         .dot = { .min = 80000, .max = 224000 },
 313         .vco = { .min = 1750000, .max = 3500000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 104, .max = 138 },
 316         .m1 = { .min = 17, .max = 23 },
 317         .m2 = { .min = 5, .max = 11 },
 318         .p = { .min = 14, .max = 42 },
 319         .p1 = { .min = 2, .max = 6 },
 320         .p2 = { .dot_limit = 0,
 321                 .p2_slow = 7, .p2_fast = 7
 322         },
 323 };
 324
 325 static const struct intel_limit intel_limits_pineview_sdvo = {
 326         .dot = { .min = 20000, .max = 400000},
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         /* Pineview's Ncounter is a ring counter */
 329         .n = { .min = 3, .max = 6 },
 330         .m = { .min = 2, .max = 256 },
 331         /* Pineview only has one combined m divider, which we treat as m2. */
 332         .m1 = { .min = 0, .max = 0 },
 333         .m2 = { .min = 0, .max = 254 },
 334         .p = { .min = 5, .max = 80 },
 335         .p1 = { .min = 1, .max = 8 },
 336         .p2 = { .dot_limit = 200000,
 337                 .p2_slow = 10, .p2_fast = 5 },
 338 };
 339
 340 static const struct intel_limit intel_limits_pineview_lvds = {
 341         .dot = { .min = 20000, .max = 400000 },
 342         .vco = { .min = 1700000, .max = 3500000 },
 343         .n = { .min = 3, .max = 6 },
 344         .m = { .min = 2, .max = 256 },
 345         .m1 = { .min = 0, .max = 0 },
 346         .m2 = { .min = 0, .max = 254 },
 347         .p = { .min = 7, .max = 112 },
 348         .p1 = { .min = 1, .max = 8 },
 349         .p2 = { .dot_limit = 112000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 /* Ironlake / Sandybridge
 354  *
 355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 356  * the range value for them is (actual_value - 2).
 357  */
 358 static const struct intel_limit intel_limits_ironlake_dac = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 5 },
 362         .m = { .min = 79, .max = 127 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 5, .max = 80 },
 366         .p1 = { .min = 1, .max = 8 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 10, .p2_fast = 5 },
 369 };
 370
 371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 372         .dot = { .min = 25000, .max = 350000 },
 373         .vco = { .min = 1760000, .max = 3510000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 79, .max = 118 },
 376         .m1 = { .min = 12, .max = 22 },
 377         .m2 = { .min = 5, .max = 9 },
 378         .p = { .min = 28, .max = 112 },
 379         .p1 = { .min = 2, .max = 8 },
 380         .p2 = { .dot_limit = 225000,
 381                 .p2_slow = 14, .p2_fast = 14 },
 382 };
 383
 384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 385         .dot = { .min = 25000, .max = 350000 },
 386         .vco = { .min = 1760000, .max = 3510000 },
 387         .n = { .min = 1, .max = 3 },
 388         .m = { .min = 79, .max = 127 },
 389         .m1 = { .min = 12, .max = 22 },
 390         .m2 = { .min = 5, .max = 9 },
 391         .p = { .min = 14, .max = 56 },
 392         .p1 = { .min = 2, .max = 8 },
 393         .p2 = { .dot_limit = 225000,
 394                 .p2_slow = 7, .p2_fast = 7 },
 395 };
 396
 397 /* LVDS 100mhz refclk limits. */
 398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 2 },
 402         .m = { .min = 79, .max = 126 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 28, .max = 112 },
 406         .p1 = { .min = 2, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 14, .p2_fast = 14 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 126 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 14, .max = 42 },
 419         .p1 = { .min = 2, .max = 6 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 7, .p2_fast = 7 },
 422 };
 423
 424 static const struct intel_limit intel_limits_vlv = {
 425          /*
 426           * These are the data rate limits (measured in fast clocks)
 427           * since those are the strictest limits we have. The fast
 428           * clock and actual rate limits are more relaxed, so checking
 429           * them would make no difference.
 430           */
 431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 432         .vco = { .min = 4000000, .max = 6000000 },
 433         .n = { .min = 1, .max = 7 },
 434         .m1 = { .min = 2, .max = 3 },
 435         .m2 = { .min = 11, .max = 156 },
 436         .p1 = { .min = 2, .max = 3 },
 437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 438 };
 439
 440 static const struct intel_limit intel_limits_chv = {
 441         /*
 442          * These are the data rate limits (measured in fast clocks)
 443          * since those are the strictest limits we have.  The fast
 444          * clock and actual rate limits are more relaxed, so checking
 445          * them would make no difference.
 446          */
 447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 448         .vco = { .min = 4800000, .max = 6480000 },
 449         .n = { .min = 1, .max = 1 },
 450         .m1 = { .min = 2, .max = 2 },
 451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 452         .p1 = { .min = 2, .max = 4 },
 453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 454 };
 455
 456 static const struct intel_limit intel_limits_bxt = {
 457         /* FIXME: find real dot limits */
 458         .dot = { .min = 0, .max = INT_MAX },
 459         .vco = { .min = 4800000, .max = 6700000 },
 460         .n = { .min = 1, .max = 1 },
 461         .m1 = { .min = 2, .max = 2 },
 462         /* FIXME: find real m2 limits */
 463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 464         .p1 = { .min = 2, .max = 4 },
 465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 466 };
 467
 468 static bool
 469 needs_modeset(struct drm_crtc_state *state)
 470 {
 471         return drm_atomic_crtc_needs_modeset(state);
 472 }
 473
 474 /*
 475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 478  * The helpers' return value is the rate of the clock that is fed to the
 479  * display engine's pipe which can be the above fast dot clock rate or a
 480  * divided-down version of it.
 481  */
 482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 484 {
 485         clock->m = clock->m2 + 2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return 0;
 489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 491
 492         return clock->dot;
 493 }
 494
 495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 496 {
 497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 498 }
 499
 500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 501 {
 502         clock->m = i9xx_dpll_compute_m(clock);
 503         clock->p = clock->p1 * clock->p2;
 504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 505                 return 0;
 506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 508
 509         return clock->dot;
 510 }
 511
 512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 513 {
 514         clock->m = clock->m1 * clock->m2;
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n == 0 || clock->p == 0))
 517                 return 0;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520
 521         return clock->dot / 5;
 522 }
 523
 524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 525 {
 526         clock->m = clock->m1 * clock->m2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return 0;
 530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 531                         clock->n << 22);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 544                                const struct intel_limit *limit,
 545                                const struct dpll *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 558                 if (clock->m1 <= clock->m2)
 559                         INTELPllInvalid("m1 <= m2\n");
 560
 561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 562             !IS_GEN9_LP(dev_priv)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static int
 581 i9xx_select_p2_div(const struct intel_limit *limit,
 582                    const struct intel_crtc_state *crtc_state,
 583                    int target)
 584 {
 585         struct drm_device *dev = crtc_state->base.crtc->dev;
 586
 587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         return limit->p2.p2_fast;
 595                 else
 596                         return limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         return limit->p2.p2_slow;
 600                 else
 601                         return limit->p2.p2_fast;
 602         }
 603 }
 604
 605 /*
 606  * Returns a set of divisors for the desired target clock with the given
 607  * refclk, or FALSE.  The returned values represent the clock equation:
 608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 609  *
 610  * Target and reference clocks are specified in kHz.
 611  *
 612  * If match_clock is provided, then best_clock P divider must match the P
 613  * divider from @match_clock used for LVDS downclocking.
 614  */
 615 static bool
 616 i9xx_find_best_dpll(const struct intel_limit *limit,
 617                     struct intel_crtc_state *crtc_state,
 618                     int target, int refclk, struct dpll *match_clock,
 619                     struct dpll *best_clock)
 620 {
 621         struct drm_device *dev = crtc_state->base.crtc->dev;
 622         struct dpll clock;
 623         int err = target;
 624
 625         memset(best_clock, 0, sizeof(*best_clock));
 626
 627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_calc_dpll_params(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(to_i915(dev),
 643                                                                 limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 pnv_find_best_dpll(const struct intel_limit *limit,
 675                    struct intel_crtc_state *crtc_state,
 676                    int target, int refclk, struct dpll *match_clock,
 677                    struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pnv_calc_dpll_params(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(to_i915(dev),
 699                                                                 limit,
 700                                                                 &clock))
 701                                                 continue;
 702                                         if (match_clock &&
 703                                             clock.p != match_clock->p)
 704                                                 continue;
 705
 706                                         this_err = abs(clock.dot - target);
 707                                         if (this_err < err) {
 708                                                 *best_clock = clock;
 709                                                 err = this_err;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715
 716         return (err != target);
 717 }
 718
 719 /*
 720  * Returns a set of divisors for the desired target clock with the given
 721  * refclk, or FALSE.  The returned values represent the clock equation:
 722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 723  *
 724  * Target and reference clocks are specified in kHz.
 725  *
 726  * If match_clock is provided, then best_clock P divider must match the P
 727  * divider from @match_clock used for LVDS downclocking.
 728  */
 729 static bool
 730 g4x_find_best_dpll(const struct intel_limit *limit,
 731                    struct intel_crtc_state *crtc_state,
 732                    int target, int refclk, struct dpll *match_clock,
 733                    struct dpll *best_clock)
 734 {
 735         struct drm_device *dev = crtc_state->base.crtc->dev;
 736         struct dpll clock;
 737         int max_n;
 738         bool found = false;
 739         /* approximately equals target * 0.00585 */
 740         int err_most = (target >> 8) + (target >> 9);
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         max_n = limit->n.max;
 747         /* based on hardware requirement, prefer smaller n to precision */
 748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 749                 /* based on hardware requirement, prefere larger m1,m2 */
 750                 for (clock.m1 = limit->m1.max;
 751                      clock.m1 >= limit->m1.min; clock.m1--) {
 752                         for (clock.m2 = limit->m2.max;
 753                              clock.m2 >= limit->m2.min; clock.m2--) {
 754                                 for (clock.p1 = limit->p1.max;
 755                                      clock.p1 >= limit->p1.min; clock.p1--) {
 756                                         int this_err;
 757
 758                                         i9xx_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 /*
 779  * Check if the calculated PLL configuration is more optimal compared to the
 780  * best configuration and error found so far. Return the calculated error.
 781  */
 782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 783                                const struct dpll *calculated_clock,
 784                                const struct dpll *best_clock,
 785                                unsigned int best_error_ppm,
 786                                unsigned int *error_ppm)
 787 {
 788         /*
 789          * For CHV ignore the error and consider only the P value.
 790          * Prefer a bigger P value based on HW requirements.
 791          */
 792         if (IS_CHERRYVIEW(to_i915(dev))) {
 793                 *error_ppm = 0;
 794
 795                 return calculated_clock->p > best_clock->p;
 796         }
 797
 798         if (WARN_ON_ONCE(!target_freq))
 799                 return false;
 800
 801         *error_ppm = div_u64(1000000ULL *
 802                                 abs(target_freq - calculated_clock->dot),
 803                              target_freq);
 804         /*
 805          * Prefer a better P value over a better (smaller) error if the error
 806          * is small. Ensure this preference for future configurations too by
 807          * setting the error to 0.
 808          */
 809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 810                 *error_ppm = 0;
 811
 812                 return true;
 813         }
 814
 815         return *error_ppm + 10 < best_error_ppm;
 816 }
 817
 818 /*
 819  * Returns a set of divisors for the desired target clock with the given
 820  * refclk, or FALSE.  The returned values represent the clock equation:
 821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 822  */
 823 static bool
 824 vlv_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 830         struct drm_device *dev = crtc->base.dev;
 831         struct dpll clock;
 832         unsigned int bestppm = 1000000;
 833         /* min update 19.2 MHz */
 834         int max_n = min(limit->n.max, refclk / 19200);
 835         bool found = false;
 836
 837         target *= 5; /* fast clock */
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 846                                 clock.p = clock.p1 * clock.p2;
 847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 849                                         unsigned int ppm;
 850
 851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 852                                                                      refclk * clock.m1);
 853
 854                                         vlv_calc_dpll_params(refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(to_i915(dev),
 857                                                                 limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         if (!vlv_PLL_is_optimal(dev, target,
 862                                                                 &clock,
 863                                                                 best_clock,
 864                                                                 bestppm, &ppm))
 865                                                 continue;
 866
 867                                         *best_clock = clock;
 868                                         bestppm = ppm;
 869                                         found = true;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         return found;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 chv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         unsigned int best_error_ppm;
 892         struct dpll clock;
 893         uint64_t m2;
 894         int found = false;
 895
 896         memset(best_clock, 0, sizeof(*best_clock));
 897         best_error_ppm = 1000000;
 898
 899         /*
 900          * Based on hardware doc, the n always set to 1, and m1 always
 901          * set to 2.  If requires to support 200Mhz refclk, we need to
 902          * revisit this because n may not 1 anymore.
 903          */
 904         clock.n = 1, clock.m1 = 2;
 905         target *= 5;    /* fast clock */
 906
 907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 908                 for (clock.p2 = limit->p2.p2_fast;
 909                                 clock.p2 >= limit->p2.p2_slow;
 910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 911                         unsigned int error_ppm;
 912
 913                         clock.p = clock.p1 * clock.p2;
 914
 915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 916                                         clock.n) << 22, refclk * clock.m1);
 917
 918                         if (m2 > INT_MAX/clock.m1)
 919                                 continue;
 920
 921                         clock.m2 = m2;
 922
 923                         chv_calc_dpll_params(refclk, &clock);
 924
 925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 926                                 continue;
 927
 928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 929                                                 best_error_ppm, &error_ppm))
 930                                 continue;
 931
 932                         *best_clock = clock;
 933                         best_error_ppm = error_ppm;
 934                         found = true;
 935                 }
 936         }
 937
 938         return found;
 939 }
 940
 941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 942                         struct dpll *best_clock)
 943 {
 944         int refclk = 100000;
 945         const struct intel_limit *limit = &intel_limits_bxt;
 946
 947         return chv_find_best_dpll(limit, crtc_state,
 948                                   target_clock, refclk, NULL, best_clock);
 949 }
 950
 951 bool intel_crtc_active(struct intel_crtc *crtc)
 952 {
 953         /* Be paranoid as we can arrive here with only partial
 954          * state retrieved from the hardware during setup.
 955          *
 956          * We can ditch the adjusted_mode.crtc_clock check as soon
 957          * as Haswell has gained clock readout/fastboot support.
 958          *
 959          * We can ditch the crtc->primary->fb check as soon as we can
 960          * properly reconstruct framebuffers.
 961          *
 962          * FIXME: The intel_crtc->active here should be switched to
 963          * crtc->state->active once we have proper CRTC states wired up
 964          * for atomic.
 965          */
 966         return crtc->active && crtc->base.primary->state->fb &&
 967                 crtc->config->base.adjusted_mode.crtc_clock;
 968 }
 969
 970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 971                                              enum pipe pipe)
 972 {
 973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 974
 975         return crtc->config->cpu_transcoder;
 976 }
 977
 978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 979 {
 980         i915_reg_t reg = PIPEDSL(pipe);
 981         u32 line1, line2;
 982         u32 line_mask;
 983
 984         if (IS_GEN2(dev_priv))
 985                 line_mask = DSL_LINEMASK_GEN2;
 986         else
 987                 line_mask = DSL_LINEMASK_GEN3;
 988
 989         line1 = I915_READ(reg) & line_mask;
 990         msleep(5);
 991         line2 = I915_READ(reg) & line_mask;
 992
 993         return line1 == line2;
 994 }
 995
 996 /*
 997  * intel_wait_for_pipe_off - wait for pipe to turn off
 998  * @crtc: crtc whose pipe to wait for
 999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_LINEAR:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (IS_I830(dev_priv))
2090                 return 16 * 1024;
2091         else if (IS_I85X(dev_priv))
2092                 return 256;
2093         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2094                 return 32;
2095         else
2096                 return 4 * 1024;
2097 }
2098
2099 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2100 {
2101         if (INTEL_INFO(dev_priv)->gen >= 9)
2102                 return 256 * 1024;
2103         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2104                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2105                 return 128 * 1024;
2106         else if (INTEL_INFO(dev_priv)->gen >= 4)
2107                 return 4 * 1024;
2108         else
2109                 return 0;
2110 }
2111
2112 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2113                                          int plane)
2114 {
2115         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2116
2117         /* AUX_DIST needs only 4K alignment */
2118         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2119                 return 4096;
2120
2121         switch (fb->modifier) {
2122         case DRM_FORMAT_MOD_LINEAR:
2123                 return intel_linear_alignment(dev_priv);
2124         case I915_FORMAT_MOD_X_TILED:
2125                 if (INTEL_GEN(dev_priv) >= 9)
2126                         return 256 * 1024;
2127                 return 0;
2128         case I915_FORMAT_MOD_Y_TILED:
2129         case I915_FORMAT_MOD_Yf_TILED:
2130                 return 1 * 1024 * 1024;
2131         default:
2132                 MISSING_CASE(fb->modifier);
2133                 return 0;
2134         }
2135 }
2136
2137 struct i915_vma *
2138 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2139 {
2140         struct drm_device *dev = fb->dev;
2141         struct drm_i915_private *dev_priv = to_i915(dev);
2142         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2143         struct i915_ggtt_view view;
2144         struct i915_vma *vma;
2145         u32 alignment;
2146
2147         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2148
2149         alignment = intel_surf_alignment(fb, 0);
2150
2151         intel_fill_fb_ggtt_view(&view, fb, rotation);
2152
2153         /* Note that the w/a also requires 64 PTE of padding following the
2154          * bo. We currently fill all unused PTE with the shadow page and so
2155          * we should always have valid PTE following the scanout preventing
2156          * the VT-d warning.
2157          */
2158         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2159                 alignment = 256 * 1024;
2160
2161         /*
2162          * Global gtt pte registers are special registers which actually forward
2163          * writes to a chunk of system memory. Which means that there is no risk
2164          * that the register values disappear as soon as we call
2165          * intel_runtime_pm_put(), so it is correct to wrap only the
2166          * pin/unpin/fence and not more.
2167          */
2168         intel_runtime_pm_get(dev_priv);
2169
2170         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2171         if (IS_ERR(vma))
2172                 goto err;
2173
2174         if (i915_vma_is_map_and_fenceable(vma)) {
2175                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2176                  * fence, whereas 965+ only requires a fence if using
2177                  * framebuffer compression.  For simplicity, we always, when
2178                  * possible, install a fence as the cost is not that onerous.
2179                  *
2180                  * If we fail to fence the tiled scanout, then either the
2181                  * modeset will reject the change (which is highly unlikely as
2182                  * the affected systems, all but one, do not have unmappable
2183                  * space) or we will not be able to enable full powersaving
2184                  * techniques (also likely not to apply due to various limits
2185                  * FBC and the like impose on the size of the buffer, which
2186                  * presumably we violated anyway with this unmappable buffer).
2187                  * Anyway, it is presumably better to stumble onwards with
2188                  * something and try to run the system in a "less than optimal"
2189                  * mode that matches the user configuration.
2190                  */
2191                 if (i915_vma_get_fence(vma) == 0)
2192                         i915_vma_pin_fence(vma);
2193         }
2194
2195         i915_vma_get(vma);
2196 err:
2197         intel_runtime_pm_put(dev_priv);
2198         return vma;
2199 }
2200
2201 void intel_unpin_fb_vma(struct i915_vma *vma)
2202 {
2203         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2204
2205         i915_vma_unpin_fence(vma);
2206         i915_gem_object_unpin_from_display_plane(vma);
2207         i915_vma_put(vma);
2208 }
2209
2210 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2211                           unsigned int rotation)
2212 {
2213         if (drm_rotation_90_or_270(rotation))
2214                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2215         else
2216                 return fb->pitches[plane];
2217 }
2218
2219 /*
2220  * Convert the x/y offsets into a linear offset.
2221  * Only valid with 0/180 degree rotation, which is fine since linear
2222  * offset is only used with linear buffers on pre-hsw and tiled buffers
2223  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2224  */
2225 u32 intel_fb_xy_to_linear(int x, int y,
2226                           const struct intel_plane_state *state,
2227                           int plane)
2228 {
2229         const struct drm_framebuffer *fb = state->base.fb;
2230         unsigned int cpp = fb->format->cpp[plane];
2231         unsigned int pitch = fb->pitches[plane];
2232
2233         return y * pitch + x * cpp;
2234 }
2235
2236 /*
2237  * Add the x/y offsets derived from fb->offsets[] to the user
2238  * specified plane src x/y offsets. The resulting x/y offsets
2239  * specify the start of scanout from the beginning of the gtt mapping.
2240  */
2241 void intel_add_fb_offsets(int *x, int *y,
2242                           const struct intel_plane_state *state,
2243                           int plane)
2244
2245 {
2246         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2247         unsigned int rotation = state->base.rotation;
2248
2249         if (drm_rotation_90_or_270(rotation)) {
2250                 *x += intel_fb->rotated[plane].x;
2251                 *y += intel_fb->rotated[plane].y;
2252         } else {
2253                 *x += intel_fb->normal[plane].x;
2254                 *y += intel_fb->normal[plane].y;
2255         }
2256 }
2257
2258 /*
2259  * Input tile dimensions and pitch must already be
2260  * rotated to match x and y, and in pixel units.
2261  */
2262 static u32 _intel_adjust_tile_offset(int *x, int *y,
2263                                      unsigned int tile_width,
2264                                      unsigned int tile_height,
2265                                      unsigned int tile_size,
2266                                      unsigned int pitch_tiles,
2267                                      u32 old_offset,
2268                                      u32 new_offset)
2269 {
2270         unsigned int pitch_pixels = pitch_tiles * tile_width;
2271         unsigned int tiles;
2272
2273         WARN_ON(old_offset & (tile_size - 1));
2274         WARN_ON(new_offset & (tile_size - 1));
2275         WARN_ON(new_offset > old_offset);
2276
2277         tiles = (old_offset - new_offset) / tile_size;
2278
2279         *y += tiles / pitch_tiles * tile_height;
2280         *x += tiles % pitch_tiles * tile_width;
2281
2282         /* minimize x in case it got needlessly big */
2283         *y += *x / pitch_pixels * tile_height;
2284         *x %= pitch_pixels;
2285
2286         return new_offset;
2287 }
2288
2289 /*
2290  * Adjust the tile offset by moving the difference into
2291  * the x/y offsets.
2292  */
2293 static u32 intel_adjust_tile_offset(int *x, int *y,
2294                                     const struct intel_plane_state *state, int plane,
2295                                     u32 old_offset, u32 new_offset)
2296 {
2297         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2298         const struct drm_framebuffer *fb = state->base.fb;
2299         unsigned int cpp = fb->format->cpp[plane];
2300         unsigned int rotation = state->base.rotation;
2301         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2302
2303         WARN_ON(new_offset > old_offset);
2304
2305         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2306                 unsigned int tile_size, tile_width, tile_height;
2307                 unsigned int pitch_tiles;
2308
2309                 tile_size = intel_tile_size(dev_priv);
2310                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2311
2312                 if (drm_rotation_90_or_270(rotation)) {
2313                         pitch_tiles = pitch / tile_height;
2314                         swap(tile_width, tile_height);
2315                 } else {
2316                         pitch_tiles = pitch / (tile_width * cpp);
2317                 }
2318
2319                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2320                                           tile_size, pitch_tiles,
2321                                           old_offset, new_offset);
2322         } else {
2323                 old_offset += *y * pitch + *x * cpp;
2324
2325                 *y = (old_offset - new_offset) / pitch;
2326                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2327         }
2328
2329         return new_offset;
2330 }
2331
2332 /*
2333  * Computes the linear offset to the base tile and adjusts
2334  * x, y. bytes per pixel is assumed to be a power-of-two.
2335  *
2336  * In the 90/270 rotated case, x and y are assumed
2337  * to be already rotated to match the rotated GTT view, and
2338  * pitch is the tile_height aligned framebuffer height.
2339  *
2340  * This function is used when computing the derived information
2341  * under intel_framebuffer, so using any of that information
2342  * here is not allowed. Anything under drm_framebuffer can be
2343  * used. This is why the user has to pass in the pitch since it
2344  * is specified in the rotated orientation.
2345  */
2346 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2347                                       int *x, int *y,
2348                                       const struct drm_framebuffer *fb, int plane,
2349                                       unsigned int pitch,
2350                                       unsigned int rotation,
2351                                       u32 alignment)
2352 {
2353         uint64_t fb_modifier = fb->modifier;
2354         unsigned int cpp = fb->format->cpp[plane];
2355         u32 offset, offset_aligned;
2356
2357         if (alignment)
2358                 alignment--;
2359
2360         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2361                 unsigned int tile_size, tile_width, tile_height;
2362                 unsigned int tile_rows, tiles, pitch_tiles;
2363
2364                 tile_size = intel_tile_size(dev_priv);
2365                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2366
2367                 if (drm_rotation_90_or_270(rotation)) {
2368                         pitch_tiles = pitch / tile_height;
2369                         swap(tile_width, tile_height);
2370                 } else {
2371                         pitch_tiles = pitch / (tile_width * cpp);
2372                 }
2373
2374                 tile_rows = *y / tile_height;
2375                 *y %= tile_height;
2376
2377                 tiles = *x / tile_width;
2378                 *x %= tile_width;
2379
2380                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2381                 offset_aligned = offset & ~alignment;
2382
2383                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2384                                           tile_size, pitch_tiles,
2385                                           offset, offset_aligned);
2386         } else {
2387                 offset = *y * pitch + *x * cpp;
2388                 offset_aligned = offset & ~alignment;
2389
2390                 *y = (offset & alignment) / pitch;
2391                 *x = ((offset & alignment) - *y * pitch) / cpp;
2392         }
2393
2394         return offset_aligned;
2395 }
2396
2397 u32 intel_compute_tile_offset(int *x, int *y,
2398                               const struct intel_plane_state *state,
2399                               int plane)
2400 {
2401         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2402         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2403         const struct drm_framebuffer *fb = state->base.fb;
2404         unsigned int rotation = state->base.rotation;
2405         int pitch = intel_fb_pitch(fb, plane, rotation);
2406         u32 alignment;
2407
2408         if (intel_plane->id == PLANE_CURSOR)
2409                 alignment = intel_cursor_alignment(dev_priv);
2410         else
2411                 alignment = intel_surf_alignment(fb, plane);
2412
2413         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2414                                           rotation, alignment);
2415 }
2416
2417 /* Convert the fb->offset[] linear offset into x/y offsets */
2418 static void intel_fb_offset_to_xy(int *x, int *y,
2419                                   const struct drm_framebuffer *fb, int plane)
2420 {
2421         unsigned int cpp = fb->format->cpp[plane];
2422         unsigned int pitch = fb->pitches[plane];
2423         u32 linear_offset = fb->offsets[plane];
2424
2425         *y = linear_offset / pitch;
2426         *x = linear_offset % pitch / cpp;
2427 }
2428
2429 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2430 {
2431         switch (fb_modifier) {
2432         case I915_FORMAT_MOD_X_TILED:
2433                 return I915_TILING_X;
2434         case I915_FORMAT_MOD_Y_TILED:
2435                 return I915_TILING_Y;
2436         default:
2437                 return I915_TILING_NONE;
2438         }
2439 }
2440
2441 static int
2442 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2443                    struct drm_framebuffer *fb)
2444 {
2445         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2446         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2447         u32 gtt_offset_rotated = 0;
2448         unsigned int max_size = 0;
2449         int i, num_planes = fb->format->num_planes;
2450         unsigned int tile_size = intel_tile_size(dev_priv);
2451
2452         for (i = 0; i < num_planes; i++) {
2453                 unsigned int width, height;
2454                 unsigned int cpp, size;
2455                 u32 offset;
2456                 int x, y;
2457
2458                 cpp = fb->format->cpp[i];
2459                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2460                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2461
2462                 intel_fb_offset_to_xy(&x, &y, fb, i);
2463
2464                 /*
2465                  * The fence (if used) is aligned to the start of the object
2466                  * so having the framebuffer wrap around across the edge of the
2467                  * fenced region doesn't really work. We have no API to configure
2468                  * the fence start offset within the object (nor could we probably
2469                  * on gen2/3). So it's just easier if we just require that the
2470                  * fb layout agrees with the fence layout. We already check that the
2471                  * fb stride matches the fence stride elsewhere.
2472                  */
2473                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2474                     (x + width) * cpp > fb->pitches[i]) {
2475                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2476                                       i, fb->offsets[i]);
2477                         return -EINVAL;
2478                 }
2479
2480                 /*
2481                  * First pixel of the framebuffer from
2482                  * the start of the normal gtt mapping.
2483                  */
2484                 intel_fb->normal[i].x = x;
2485                 intel_fb->normal[i].y = y;
2486
2487                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2488                                                     fb, i, fb->pitches[i],
2489                                                     DRM_MODE_ROTATE_0, tile_size);
2490                 offset /= tile_size;
2491
2492                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2493                         unsigned int tile_width, tile_height;
2494                         unsigned int pitch_tiles;
2495                         struct drm_rect r;
2496
2497                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2498
2499                         rot_info->plane[i].offset = offset;
2500                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2501                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2502                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2503
2504                         intel_fb->rotated[i].pitch =
2505                                 rot_info->plane[i].height * tile_height;
2506
2507                         /* how many tiles does this plane need */
2508                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2509                         /*
2510                          * If the plane isn't horizontally tile aligned,
2511                          * we need one more tile.
2512                          */
2513                         if (x != 0)
2514                                 size++;
2515
2516                         /* rotate the x/y offsets to match the GTT view */
2517                         r.x1 = x;
2518                         r.y1 = y;
2519                         r.x2 = x + width;
2520                         r.y2 = y + height;
2521                         drm_rect_rotate(&r,
2522                                         rot_info->plane[i].width * tile_width,
2523                                         rot_info->plane[i].height * tile_height,
2524                                         DRM_MODE_ROTATE_270);
2525                         x = r.x1;
2526                         y = r.y1;
2527
2528                         /* rotate the tile dimensions to match the GTT view */
2529                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2530                         swap(tile_width, tile_height);
2531
2532                         /*
2533                          * We only keep the x/y offsets, so push all of the
2534                          * gtt offset into the x/y offsets.
2535                          */
2536                         _intel_adjust_tile_offset(&x, &y,
2537                                                   tile_width, tile_height,
2538                                                   tile_size, pitch_tiles,
2539                                                   gtt_offset_rotated * tile_size, 0);
2540
2541                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2542
2543                         /*
2544                          * First pixel of the framebuffer from
2545                          * the start of the rotated gtt mapping.
2546                          */
2547                         intel_fb->rotated[i].x = x;
2548                         intel_fb->rotated[i].y = y;
2549                 } else {
2550                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2551                                             x * cpp, tile_size);
2552                 }
2553
2554                 /* how many tiles in total needed in the bo */
2555                 max_size = max(max_size, offset + size);
2556         }
2557
2558         if (max_size * tile_size > intel_fb->obj->base.size) {
2559                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2560                               max_size * tile_size, intel_fb->obj->base.size);
2561                 return -EINVAL;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static int i9xx_format_to_fourcc(int format)
2568 {
2569         switch (format) {
2570         case DISPPLANE_8BPP:
2571                 return DRM_FORMAT_C8;
2572         case DISPPLANE_BGRX555:
2573                 return DRM_FORMAT_XRGB1555;
2574         case DISPPLANE_BGRX565:
2575                 return DRM_FORMAT_RGB565;
2576         default:
2577         case DISPPLANE_BGRX888:
2578                 return DRM_FORMAT_XRGB8888;
2579         case DISPPLANE_RGBX888:
2580                 return DRM_FORMAT_XBGR8888;
2581         case DISPPLANE_BGRX101010:
2582                 return DRM_FORMAT_XRGB2101010;
2583         case DISPPLANE_RGBX101010:
2584                 return DRM_FORMAT_XBGR2101010;
2585         }
2586 }
2587
2588 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2589 {
2590         switch (format) {
2591         case PLANE_CTL_FORMAT_RGB_565:
2592                 return DRM_FORMAT_RGB565;
2593         default:
2594         case PLANE_CTL_FORMAT_XRGB_8888:
2595                 if (rgb_order) {
2596                         if (alpha)
2597                                 return DRM_FORMAT_ABGR8888;
2598                         else
2599                                 return DRM_FORMAT_XBGR8888;
2600                 } else {
2601                         if (alpha)
2602                                 return DRM_FORMAT_ARGB8888;
2603                         else
2604                                 return DRM_FORMAT_XRGB8888;
2605                 }
2606         case PLANE_CTL_FORMAT_XRGB_2101010:
2607                 if (rgb_order)
2608                         return DRM_FORMAT_XBGR2101010;
2609                 else
2610                         return DRM_FORMAT_XRGB2101010;
2611         }
2612 }
2613
2614 static bool
2615 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2616                               struct intel_initial_plane_config *plane_config)
2617 {
2618         struct drm_device *dev = crtc->base.dev;
2619         struct drm_i915_private *dev_priv = to_i915(dev);
2620         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2621         struct drm_i915_gem_object *obj = NULL;
2622         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2623         struct drm_framebuffer *fb = &plane_config->fb->base;
2624         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2625         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2626                                     PAGE_SIZE);
2627
2628         size_aligned -= base_aligned;
2629
2630         if (plane_config->size == 0)
2631                 return false;
2632
2633         /* If the FB is too big, just don't use it since fbdev is not very
2634          * important and we should probably use that space with FBC or other
2635          * features. */
2636         if (size_aligned * 2 > ggtt->stolen_usable_size)
2637                 return false;
2638
2639         mutex_lock(&dev->struct_mutex);
2640         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2641                                                              base_aligned,
2642                                                              base_aligned,
2643                                                              size_aligned);
2644         mutex_unlock(&dev->struct_mutex);
2645         if (!obj)
2646                 return false;
2647
2648         if (plane_config->tiling == I915_TILING_X)
2649                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2650
2651         mode_cmd.pixel_format = fb->format->format;
2652         mode_cmd.width = fb->width;
2653         mode_cmd.height = fb->height;
2654         mode_cmd.pitches[0] = fb->pitches[0];
2655         mode_cmd.modifier[0] = fb->modifier;
2656         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2657
2658         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2659                 DRM_DEBUG_KMS("intel fb init failed\n");
2660                 goto out_unref_obj;
2661         }
2662
2663
2664         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2665         return true;
2666
2667 out_unref_obj:
2668         i915_gem_object_put(obj);
2669         return false;
2670 }
2671
2672 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2673 static void
2674 update_state_fb(struct drm_plane *plane)
2675 {
2676         if (plane->fb == plane->state->fb)
2677                 return;
2678
2679         if (plane->state->fb)
2680                 drm_framebuffer_unreference(plane->state->fb);
2681         plane->state->fb = plane->fb;
2682         if (plane->state->fb)
2683                 drm_framebuffer_reference(plane->state->fb);
2684 }
2685
2686 static void
2687 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2688                         struct intel_plane_state *plane_state,
2689                         bool visible)
2690 {
2691         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2692
2693         plane_state->base.visible = visible;
2694
2695         /* FIXME pre-g4x don't work like this */
2696         if (visible) {
2697                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2698                 crtc_state->active_planes |= BIT(plane->id);
2699         } else {
2700                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2701                 crtc_state->active_planes &= ~BIT(plane->id);
2702         }
2703
2704         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2705                       crtc_state->base.crtc->name,
2706                       crtc_state->active_planes);
2707 }
2708
2709 static void
2710 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2711                              struct intel_initial_plane_config *plane_config)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = to_i915(dev);
2715         struct drm_crtc *c;
2716         struct drm_i915_gem_object *obj;
2717         struct drm_plane *primary = intel_crtc->base.primary;
2718         struct drm_plane_state *plane_state = primary->state;
2719         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2720         struct intel_plane *intel_plane = to_intel_plane(primary);
2721         struct intel_plane_state *intel_state =
2722                 to_intel_plane_state(plane_state);
2723         struct drm_framebuffer *fb;
2724
2725         if (!plane_config->fb)
2726                 return;
2727
2728         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2729                 fb = &plane_config->fb->base;
2730                 goto valid_fb;
2731         }
2732
2733         kfree(plane_config->fb);
2734
2735         /*
2736          * Failed to alloc the obj, check to see if we should share
2737          * an fb with another CRTC instead
2738          */
2739         for_each_crtc(dev, c) {
2740                 struct intel_plane_state *state;
2741
2742                 if (c == &intel_crtc->base)
2743                         continue;
2744
2745                 if (!to_intel_crtc(c)->active)
2746                         continue;
2747
2748                 state = to_intel_plane_state(c->primary->state);
2749                 if (!state->vma)
2750                         continue;
2751
2752                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2753                         fb = c->primary->fb;
2754                         drm_framebuffer_reference(fb);
2755                         goto valid_fb;
2756                 }
2757         }
2758
2759         /*
2760          * We've failed to reconstruct the BIOS FB.  Current display state
2761          * indicates that the primary plane is visible, but has a NULL FB,
2762          * which will lead to problems later if we don't fix it up.  The
2763          * simplest solution is to just disable the primary plane now and
2764          * pretend the BIOS never had it enabled.
2765          */
2766         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2767                                 to_intel_plane_state(plane_state),
2768                                 false);
2769         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2770         trace_intel_disable_plane(primary, intel_crtc);
2771         intel_plane->disable_plane(intel_plane, intel_crtc);
2772
2773         return;
2774
2775 valid_fb:
2776         mutex_lock(&dev->struct_mutex);
2777         intel_state->vma =
2778                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2779         mutex_unlock(&dev->struct_mutex);
2780         if (IS_ERR(intel_state->vma)) {
2781                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2782                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2783
2784                 intel_state->vma = NULL;
2785                 drm_framebuffer_unreference(fb);
2786                 return;
2787         }
2788
2789         plane_state->src_x = 0;
2790         plane_state->src_y = 0;
2791         plane_state->src_w = fb->width << 16;
2792         plane_state->src_h = fb->height << 16;
2793
2794         plane_state->crtc_x = 0;
2795         plane_state->crtc_y = 0;
2796         plane_state->crtc_w = fb->width;
2797         plane_state->crtc_h = fb->height;
2798
2799         intel_state->base.src = drm_plane_state_src(plane_state);
2800         intel_state->base.dst = drm_plane_state_dest(plane_state);
2801
2802         obj = intel_fb_obj(fb);
2803         if (i915_gem_object_is_tiled(obj))
2804                 dev_priv->preserve_bios_swizzle = true;
2805
2806         drm_framebuffer_reference(fb);
2807         primary->fb = primary->state->fb = fb;
2808         primary->crtc = primary->state->crtc = &intel_crtc->base;
2809
2810         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2811                                 to_intel_plane_state(plane_state),
2812                                 true);
2813
2814         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2815                   &obj->frontbuffer_bits);
2816 }
2817
2818 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2819                                unsigned int rotation)
2820 {
2821         int cpp = fb->format->cpp[plane];
2822
2823         switch (fb->modifier) {
2824         case DRM_FORMAT_MOD_LINEAR:
2825         case I915_FORMAT_MOD_X_TILED:
2826                 switch (cpp) {
2827                 case 8:
2828                         return 4096;
2829                 case 4:
2830                 case 2:
2831                 case 1:
2832                         return 8192;
2833                 default:
2834                         MISSING_CASE(cpp);
2835                         break;
2836                 }
2837                 break;
2838         case I915_FORMAT_MOD_Y_TILED:
2839         case I915_FORMAT_MOD_Yf_TILED:
2840                 switch (cpp) {
2841                 case 8:
2842                         return 2048;
2843                 case 4:
2844                         return 4096;
2845                 case 2:
2846                 case 1:
2847                         return 8192;
2848                 default:
2849                         MISSING_CASE(cpp);
2850                         break;
2851                 }
2852                 break;
2853         default:
2854                 MISSING_CASE(fb->modifier);
2855         }
2856
2857         return 2048;
2858 }
2859
2860 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2861 {
2862         const struct drm_framebuffer *fb = plane_state->base.fb;
2863         unsigned int rotation = plane_state->base.rotation;
2864         int x = plane_state->base.src.x1 >> 16;
2865         int y = plane_state->base.src.y1 >> 16;
2866         int w = drm_rect_width(&plane_state->base.src) >> 16;
2867         int h = drm_rect_height(&plane_state->base.src) >> 16;
2868         int max_width = skl_max_plane_width(fb, 0, rotation);
2869         int max_height = 4096;
2870         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2871
2872         if (w > max_width || h > max_height) {
2873                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2874                               w, h, max_width, max_height);
2875                 return -EINVAL;
2876         }
2877
2878         intel_add_fb_offsets(&x, &y, plane_state, 0);
2879         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2880         alignment = intel_surf_alignment(fb, 0);
2881
2882         /*
2883          * AUX surface offset is specified as the distance from the
2884          * main surface offset, and it must be non-negative. Make
2885          * sure that is what we will get.
2886          */
2887         if (offset > aux_offset)
2888                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                   offset, aux_offset & ~(alignment - 1));
2890
2891         /*
2892          * When using an X-tiled surface, the plane blows up
2893          * if the x offset + width exceed the stride.
2894          *
2895          * TODO: linear and Y-tiled seem fine, Yf untested,
2896          */
2897         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2898                 int cpp = fb->format->cpp[0];
2899
2900                 while ((x + w) * cpp > fb->pitches[0]) {
2901                         if (offset == 0) {
2902                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2903                                 return -EINVAL;
2904                         }
2905
2906                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2907                                                           offset, offset - alignment);
2908                 }
2909         }
2910
2911         plane_state->main.offset = offset;
2912         plane_state->main.x = x;
2913         plane_state->main.y = y;
2914
2915         return 0;
2916 }
2917
2918 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2919 {
2920         const struct drm_framebuffer *fb = plane_state->base.fb;
2921         unsigned int rotation = plane_state->base.rotation;
2922         int max_width = skl_max_plane_width(fb, 1, rotation);
2923         int max_height = 4096;
2924         int x = plane_state->base.src.x1 >> 17;
2925         int y = plane_state->base.src.y1 >> 17;
2926         int w = drm_rect_width(&plane_state->base.src) >> 17;
2927         int h = drm_rect_height(&plane_state->base.src) >> 17;
2928         u32 offset;
2929
2930         intel_add_fb_offsets(&x, &y, plane_state, 1);
2931         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2932
2933         /* FIXME not quite sure how/if these apply to the chroma plane */
2934         if (w > max_width || h > max_height) {
2935                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2936                               w, h, max_width, max_height);
2937                 return -EINVAL;
2938         }
2939
2940         plane_state->aux.offset = offset;
2941         plane_state->aux.x = x;
2942         plane_state->aux.y = y;
2943
2944         return 0;
2945 }
2946
2947 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2948 {
2949         const struct drm_framebuffer *fb = plane_state->base.fb;
2950         unsigned int rotation = plane_state->base.rotation;
2951         int ret;
2952
2953         if (!plane_state->base.visible)
2954                 return 0;
2955
2956         /* Rotate src coordinates to match rotated GTT view */
2957         if (drm_rotation_90_or_270(rotation))
2958                 drm_rect_rotate(&plane_state->base.src,
2959                                 fb->width << 16, fb->height << 16,
2960                                 DRM_MODE_ROTATE_270);
2961
2962         /*
2963          * Handle the AUX surface first since
2964          * the main surface setup depends on it.
2965          */
2966         if (fb->format->format == DRM_FORMAT_NV12) {
2967                 ret = skl_check_nv12_aux_surface(plane_state);
2968                 if (ret)
2969                         return ret;
2970         } else {
2971                 plane_state->aux.offset = ~0xfff;
2972                 plane_state->aux.x = 0;
2973                 plane_state->aux.y = 0;
2974         }
2975
2976         ret = skl_check_main_surface(plane_state);
2977         if (ret)
2978                 return ret;
2979
2980         return 0;
2981 }
2982
2983 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2984                           const struct intel_plane_state *plane_state)
2985 {
2986         struct drm_i915_private *dev_priv =
2987                 to_i915(plane_state->base.plane->dev);
2988         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2989         const struct drm_framebuffer *fb = plane_state->base.fb;
2990         unsigned int rotation = plane_state->base.rotation;
2991         u32 dspcntr;
2992
2993         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2994
2995         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2996             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2997                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2998
2999         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3000                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3001
3002         if (INTEL_GEN(dev_priv) < 4)
3003                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3004
3005         switch (fb->format->format) {
3006         case DRM_FORMAT_C8:
3007                 dspcntr |= DISPPLANE_8BPP;
3008                 break;
3009         case DRM_FORMAT_XRGB1555:
3010                 dspcntr |= DISPPLANE_BGRX555;
3011                 break;
3012         case DRM_FORMAT_RGB565:
3013                 dspcntr |= DISPPLANE_BGRX565;
3014                 break;
3015         case DRM_FORMAT_XRGB8888:
3016                 dspcntr |= DISPPLANE_BGRX888;
3017                 break;
3018         case DRM_FORMAT_XBGR8888:
3019                 dspcntr |= DISPPLANE_RGBX888;
3020                 break;
3021         case DRM_FORMAT_XRGB2101010:
3022                 dspcntr |= DISPPLANE_BGRX101010;
3023                 break;
3024         case DRM_FORMAT_XBGR2101010:
3025                 dspcntr |= DISPPLANE_RGBX101010;
3026                 break;
3027         default:
3028                 MISSING_CASE(fb->format->format);
3029                 return 0;
3030         }
3031
3032         if (INTEL_GEN(dev_priv) >= 4 &&
3033             fb->modifier == I915_FORMAT_MOD_X_TILED)
3034                 dspcntr |= DISPPLANE_TILED;
3035
3036         if (rotation & DRM_MODE_ROTATE_180)
3037                 dspcntr |= DISPPLANE_ROTATE_180;
3038
3039         if (rotation & DRM_MODE_REFLECT_X)
3040                 dspcntr |= DISPPLANE_MIRROR;
3041
3042         return dspcntr;
3043 }
3044
3045 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3046 {
3047         struct drm_i915_private *dev_priv =
3048                 to_i915(plane_state->base.plane->dev);
3049         int src_x = plane_state->base.src.x1 >> 16;
3050         int src_y = plane_state->base.src.y1 >> 16;
3051         u32 offset;
3052
3053         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3054
3055         if (INTEL_GEN(dev_priv) >= 4)
3056                 offset = intel_compute_tile_offset(&src_x, &src_y,
3057                                                    plane_state, 0);
3058         else
3059                 offset = 0;
3060
3061         /* HSW/BDW do this automagically in hardware */
3062         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3063                 unsigned int rotation = plane_state->base.rotation;
3064                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3065                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3066
3067                 if (rotation & DRM_MODE_ROTATE_180) {
3068                         src_x += src_w - 1;
3069                         src_y += src_h - 1;
3070                 } else if (rotation & DRM_MODE_REFLECT_X) {
3071                         src_x += src_w - 1;
3072                 }
3073         }
3074
3075         plane_state->main.offset = offset;
3076         plane_state->main.x = src_x;
3077         plane_state->main.y = src_y;
3078
3079         return 0;
3080 }
3081
3082 static void i9xx_update_primary_plane(struct intel_plane *primary,
3083                                       const struct intel_crtc_state *crtc_state,
3084                                       const struct intel_plane_state *plane_state)
3085 {
3086         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3087         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3088         const struct drm_framebuffer *fb = plane_state->base.fb;
3089         enum plane plane = primary->plane;
3090         u32 linear_offset;
3091         u32 dspcntr = plane_state->ctl;
3092         i915_reg_t reg = DSPCNTR(plane);
3093         int x = plane_state->main.x;
3094         int y = plane_state->main.y;
3095         unsigned long irqflags;
3096
3097         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3098
3099         if (INTEL_GEN(dev_priv) >= 4)
3100                 crtc->dspaddr_offset = plane_state->main.offset;
3101         else
3102                 crtc->dspaddr_offset = linear_offset;
3103
3104         crtc->adjusted_x = x;
3105         crtc->adjusted_y = y;
3106
3107         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3108
3109         if (INTEL_GEN(dev_priv) < 4) {
3110                 /* pipesrc and dspsize control the size that is scaled from,
3111                  * which should always be the user's requested size.
3112                  */
3113                 I915_WRITE_FW(DSPSIZE(plane),
3114                               ((crtc_state->pipe_src_h - 1) << 16) |
3115                               (crtc_state->pipe_src_w - 1));
3116                 I915_WRITE_FW(DSPPOS(plane), 0);
3117         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3118                 I915_WRITE_FW(PRIMSIZE(plane),
3119                               ((crtc_state->pipe_src_h - 1) << 16) |
3120                               (crtc_state->pipe_src_w - 1));
3121                 I915_WRITE_FW(PRIMPOS(plane), 0);
3122                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3123         }
3124
3125         I915_WRITE_FW(reg, dspcntr);
3126
3127         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3128         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3129                 I915_WRITE_FW(DSPSURF(plane),
3130                               intel_plane_ggtt_offset(plane_state) +
3131                               crtc->dspaddr_offset);
3132                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3133         } else if (INTEL_GEN(dev_priv) >= 4) {
3134                 I915_WRITE_FW(DSPSURF(plane),
3135                               intel_plane_ggtt_offset(plane_state) +
3136                               crtc->dspaddr_offset);
3137                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3138                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3139         } else {
3140                 I915_WRITE_FW(DSPADDR(plane),
3141                               intel_plane_ggtt_offset(plane_state) +
3142                               crtc->dspaddr_offset);
3143         }
3144         POSTING_READ_FW(reg);
3145
3146         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3147 }
3148
3149 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3150                                        struct intel_crtc *crtc)
3151 {
3152         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3153         enum plane plane = primary->plane;
3154         unsigned long irqflags;
3155
3156         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3157
3158         I915_WRITE_FW(DSPCNTR(plane), 0);
3159         if (INTEL_INFO(dev_priv)->gen >= 4)
3160                 I915_WRITE_FW(DSPSURF(plane), 0);
3161         else
3162                 I915_WRITE_FW(DSPADDR(plane), 0);
3163         POSTING_READ_FW(DSPCNTR(plane));
3164
3165         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3166 }
3167
3168 static u32
3169 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3170 {
3171         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3172                 return 64;
3173         else
3174                 return intel_tile_width_bytes(fb, plane);
3175 }
3176
3177 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3178 {
3179         struct drm_device *dev = intel_crtc->base.dev;
3180         struct drm_i915_private *dev_priv = to_i915(dev);
3181
3182         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3183         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3184         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3185 }
3186
3187 /*
3188  * This function detaches (aka. unbinds) unused scalers in hardware
3189  */
3190 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3191 {
3192         struct intel_crtc_scaler_state *scaler_state;
3193         int i;
3194
3195         scaler_state = &intel_crtc->config->scaler_state;
3196
3197         /* loop through and disable scalers that aren't in use */
3198         for (i = 0; i < intel_crtc->num_scalers; i++) {
3199                 if (!scaler_state->scalers[i].in_use)
3200                         skl_detach_scaler(intel_crtc, i);
3201         }
3202 }
3203
3204 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3205                      unsigned int rotation)
3206 {
3207         u32 stride;
3208
3209         if (plane >= fb->format->num_planes)
3210                 return 0;
3211
3212         stride = intel_fb_pitch(fb, plane, rotation);
3213
3214         /*
3215          * The stride is either expressed as a multiple of 64 bytes chunks for
3216          * linear buffers or in number of tiles for tiled buffers.
3217          */
3218         if (drm_rotation_90_or_270(rotation))
3219                 stride /= intel_tile_height(fb, plane);
3220         else
3221                 stride /= intel_fb_stride_alignment(fb, plane);
3222
3223         return stride;
3224 }
3225
3226 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3227 {
3228         switch (pixel_format) {
3229         case DRM_FORMAT_C8:
3230                 return PLANE_CTL_FORMAT_INDEXED;
3231         case DRM_FORMAT_RGB565:
3232                 return PLANE_CTL_FORMAT_RGB_565;
3233         case DRM_FORMAT_XBGR8888:
3234                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3235         case DRM_FORMAT_XRGB8888:
3236                 return PLANE_CTL_FORMAT_XRGB_8888;
3237         /*
3238          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3239          * to be already pre-multiplied. We need to add a knob (or a different
3240          * DRM_FORMAT) for user-space to configure that.
3241          */
3242         case DRM_FORMAT_ABGR8888:
3243                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3244                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3245         case DRM_FORMAT_ARGB8888:
3246                 return PLANE_CTL_FORMAT_XRGB_8888 |
3247                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3248         case DRM_FORMAT_XRGB2101010:
3249                 return PLANE_CTL_FORMAT_XRGB_2101010;
3250         case DRM_FORMAT_XBGR2101010:
3251                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3252         case DRM_FORMAT_YUYV:
3253                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3254         case DRM_FORMAT_YVYU:
3255                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3256         case DRM_FORMAT_UYVY:
3257                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3258         case DRM_FORMAT_VYUY:
3259                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3260         default:
3261                 MISSING_CASE(pixel_format);
3262         }
3263
3264         return 0;
3265 }
3266
3267 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3268 {
3269         switch (fb_modifier) {
3270         case DRM_FORMAT_MOD_LINEAR:
3271                 break;
3272         case I915_FORMAT_MOD_X_TILED:
3273                 return PLANE_CTL_TILED_X;
3274         case I915_FORMAT_MOD_Y_TILED:
3275                 return PLANE_CTL_TILED_Y;
3276         case I915_FORMAT_MOD_Yf_TILED:
3277                 return PLANE_CTL_TILED_YF;
3278         default:
3279                 MISSING_CASE(fb_modifier);
3280         }
3281
3282         return 0;
3283 }
3284
3285 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3286 {
3287         switch (rotation) {
3288         case DRM_MODE_ROTATE_0:
3289                 break;
3290         /*
3291          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3292          * while i915 HW rotation is clockwise, thats why this swapping.
3293          */
3294         case DRM_MODE_ROTATE_90:
3295                 return PLANE_CTL_ROTATE_270;
3296         case DRM_MODE_ROTATE_180:
3297                 return PLANE_CTL_ROTATE_180;
3298         case DRM_MODE_ROTATE_270:
3299                 return PLANE_CTL_ROTATE_90;
3300         default:
3301                 MISSING_CASE(rotation);
3302         }
3303
3304         return 0;
3305 }
3306
3307 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3308                   const struct intel_plane_state *plane_state)
3309 {
3310         struct drm_i915_private *dev_priv =
3311                 to_i915(plane_state->base.plane->dev);
3312         const struct drm_framebuffer *fb = plane_state->base.fb;
3313         unsigned int rotation = plane_state->base.rotation;
3314         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3315         u32 plane_ctl;
3316
3317         plane_ctl = PLANE_CTL_ENABLE;
3318
3319         if (!IS_GEMINILAKE(dev_priv)) {
3320                 plane_ctl |=
3321                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3322                         PLANE_CTL_PIPE_CSC_ENABLE |
3323                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3324         }
3325
3326         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3327         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3328         plane_ctl |= skl_plane_ctl_rotation(rotation);
3329
3330         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3331                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3332         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3333                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3334
3335         return plane_ctl;
3336 }
3337
3338 static void skylake_update_primary_plane(struct intel_plane *plane,
3339                                          const struct intel_crtc_state *crtc_state,
3340                                          const struct intel_plane_state *plane_state)
3341 {
3342         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3343         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3344         const struct drm_framebuffer *fb = plane_state->base.fb;
3345         enum plane_id plane_id = plane->id;
3346         enum pipe pipe = plane->pipe;
3347         u32 plane_ctl = plane_state->ctl;
3348         unsigned int rotation = plane_state->base.rotation;
3349         u32 stride = skl_plane_stride(fb, 0, rotation);
3350         u32 surf_addr = plane_state->main.offset;
3351         int scaler_id = plane_state->scaler_id;
3352         int src_x = plane_state->main.x;
3353         int src_y = plane_state->main.y;
3354         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3355         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3356         int dst_x = plane_state->base.dst.x1;
3357         int dst_y = plane_state->base.dst.y1;
3358         int dst_w = drm_rect_width(&plane_state->base.dst);
3359         int dst_h = drm_rect_height(&plane_state->base.dst);
3360         unsigned long irqflags;
3361
3362         /* Sizes are 0 based */
3363         src_w--;
3364         src_h--;
3365         dst_w--;
3366         dst_h--;
3367
3368         crtc->dspaddr_offset = surf_addr;
3369
3370         crtc->adjusted_x = src_x;
3371         crtc->adjusted_y = src_y;
3372
3373         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3374
3375         if (IS_GEMINILAKE(dev_priv)) {
3376                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3377                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3378                               PLANE_COLOR_PIPE_CSC_ENABLE |
3379                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3380         }
3381
3382         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3383         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3384         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3385         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3386
3387         if (scaler_id >= 0) {
3388                 uint32_t ps_ctrl = 0;
3389
3390                 WARN_ON(!dst_w || !dst_h);
3391                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3392                         crtc_state->scaler_state.scalers[scaler_id].mode;
3393                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3394                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3395                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3396                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3397                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3398         } else {
3399                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3400         }
3401
3402         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3403                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3404
3405         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3406
3407         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3408 }
3409
3410 static void skylake_disable_primary_plane(struct intel_plane *primary,
3411                                           struct intel_crtc *crtc)
3412 {
3413         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3414         enum plane_id plane_id = primary->id;
3415         enum pipe pipe = primary->pipe;
3416         unsigned long irqflags;
3417
3418         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3419
3420         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3421         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3422         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3423
3424         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3425 }
3426
3427 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3428 {
3429         struct intel_crtc *crtc;
3430
3431         for_each_intel_crtc(&dev_priv->drm, crtc)
3432                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3433 }
3434
3435 static void intel_update_primary_planes(struct drm_device *dev)
3436 {
3437         struct drm_crtc *crtc;
3438
3439         for_each_crtc(dev, crtc) {
3440                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3441                 struct intel_plane_state *plane_state =
3442                         to_intel_plane_state(plane->base.state);
3443
3444                 if (plane_state->base.visible) {
3445                         trace_intel_update_plane(&plane->base,
3446                                                  to_intel_crtc(crtc));
3447
3448                         plane->update_plane(plane,
3449                                             to_intel_crtc_state(crtc->state),
3450                                             plane_state);
3451                 }
3452         }
3453 }
3454
3455 static int
3456 __intel_display_resume(struct drm_device *dev,
3457                        struct drm_atomic_state *state,
3458                        struct drm_modeset_acquire_ctx *ctx)
3459 {
3460         struct drm_crtc_state *crtc_state;
3461         struct drm_crtc *crtc;
3462         int i, ret;
3463
3464         intel_modeset_setup_hw_state(dev);
3465         i915_redisable_vga(to_i915(dev));
3466
3467         if (!state)
3468                 return 0;
3469
3470         /*
3471          * We've duplicated the state, pointers to the old state are invalid.
3472          *
3473          * Don't attempt to use the old state until we commit the duplicated state.
3474          */
3475         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3476                 /*
3477                  * Force recalculation even if we restore
3478                  * current state. With fast modeset this may not result
3479                  * in a modeset when the state is compatible.
3480                  */
3481                 crtc_state->mode_changed = true;
3482         }
3483
3484         /* ignore any reset values/BIOS leftovers in the WM registers */
3485         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3486                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3487
3488         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3489
3490         WARN_ON(ret == -EDEADLK);
3491         return ret;
3492 }
3493
3494 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3495 {
3496         return intel_has_gpu_reset(dev_priv) &&
3497                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3498 }
3499
3500 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3501 {
3502         struct drm_device *dev = &dev_priv->drm;
3503         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3504         struct drm_atomic_state *state;
3505         int ret;
3506
3507         /*
3508          * Need mode_config.mutex so that we don't
3509          * trample ongoing ->detect() and whatnot.
3510          */
3511         mutex_lock(&dev->mode_config.mutex);
3512         drm_modeset_acquire_init(ctx, 0);
3513         while (1) {
3514                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3515                 if (ret != -EDEADLK)
3516                         break;
3517
3518                 drm_modeset_backoff(ctx);
3519         }
3520
3521         /* reset doesn't touch the display, but flips might get nuked anyway, */
3522         if (!i915.force_reset_modeset_test &&
3523             !gpu_reset_clobbers_display(dev_priv))
3524                 return;
3525
3526         /*
3527          * Disabling the crtcs gracefully seems nicer. Also the
3528          * g33 docs say we should at least disable all the planes.
3529          */
3530         state = drm_atomic_helper_duplicate_state(dev, ctx);
3531         if (IS_ERR(state)) {
3532                 ret = PTR_ERR(state);
3533                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3534                 return;
3535         }
3536
3537         ret = drm_atomic_helper_disable_all(dev, ctx);
3538         if (ret) {
3539                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3540                 drm_atomic_state_put(state);
3541                 return;
3542         }
3543
3544         dev_priv->modeset_restore_state = state;
3545         state->acquire_ctx = ctx;
3546 }
3547
3548 void intel_finish_reset(struct drm_i915_private *dev_priv)
3549 {
3550         struct drm_device *dev = &dev_priv->drm;
3551         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3552         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3553         int ret;
3554
3555         /*
3556          * Flips in the rings will be nuked by the reset,
3557          * so complete all pending flips so that user space
3558          * will get its events and not get stuck.
3559          */
3560         intel_complete_page_flips(dev_priv);
3561
3562         dev_priv->modeset_restore_state = NULL;
3563
3564         /* reset doesn't touch the display */
3565         if (!gpu_reset_clobbers_display(dev_priv)) {
3566                 if (!state) {
3567                         /*
3568                          * Flips in the rings have been nuked by the reset,
3569                          * so update the base address of all primary
3570                          * planes to the the last fb to make sure we're
3571                          * showing the correct fb after a reset.
3572                          *
3573                          * FIXME: Atomic will make this obsolete since we won't schedule
3574                          * CS-based flips (which might get lost in gpu resets) any more.
3575                          */
3576                         intel_update_primary_planes(dev);
3577                 } else {
3578                         ret = __intel_display_resume(dev, state, ctx);
3579                         if (ret)
3580                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3581                 }
3582         } else {
3583                 /*
3584                  * The display has been reset as well,
3585                  * so need a full re-initialization.
3586                  */
3587                 intel_runtime_pm_disable_interrupts(dev_priv);
3588                 intel_runtime_pm_enable_interrupts(dev_priv);
3589
3590                 intel_pps_unlock_regs_wa(dev_priv);
3591                 intel_modeset_init_hw(dev);
3592
3593                 spin_lock_irq(&dev_priv->irq_lock);
3594                 if (dev_priv->display.hpd_irq_setup)
3595                         dev_priv->display.hpd_irq_setup(dev_priv);
3596                 spin_unlock_irq(&dev_priv->irq_lock);
3597
3598                 ret = __intel_display_resume(dev, state, ctx);
3599                 if (ret)
3600                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3601
3602                 intel_hpd_init(dev_priv);
3603         }
3604
3605         if (state)
3606                 drm_atomic_state_put(state);
3607         drm_modeset_drop_locks(ctx);
3608         drm_modeset_acquire_fini(ctx);
3609         mutex_unlock(&dev->mode_config.mutex);
3610 }
3611
3612 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3613 {
3614         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3615
3616         if (i915_reset_backoff(error))
3617                 return true;
3618
3619         if (crtc->reset_count != i915_reset_count(error))
3620                 return true;
3621
3622         return false;
3623 }
3624
3625 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629         bool pending;
3630
3631         if (abort_flip_on_reset(intel_crtc))
3632                 return false;
3633
3634         spin_lock_irq(&dev->event_lock);
3635         pending = to_intel_crtc(crtc)->flip_work != NULL;
3636         spin_unlock_irq(&dev->event_lock);
3637
3638         return pending;
3639 }
3640
3641 static void intel_update_pipe_config(struct intel_crtc *crtc,
3642                                      struct intel_crtc_state *old_crtc_state)
3643 {
3644         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3645         struct intel_crtc_state *pipe_config =
3646                 to_intel_crtc_state(crtc->base.state);
3647
3648         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3649         crtc->base.mode = crtc->base.state->mode;
3650
3651         /*
3652          * Update pipe size and adjust fitter if needed: the reason for this is
3653          * that in compute_mode_changes we check the native mode (not the pfit
3654          * mode) to see if we can flip rather than do a full mode set. In the
3655          * fastboot case, we'll flip, but if we don't update the pipesrc and
3656          * pfit state, we'll end up with a big fb scanned out into the wrong
3657          * sized surface.
3658          */
3659
3660         I915_WRITE(PIPESRC(crtc->pipe),
3661                    ((pipe_config->pipe_src_w - 1) << 16) |
3662                    (pipe_config->pipe_src_h - 1));
3663
3664         /* on skylake this is done by detaching scalers */
3665         if (INTEL_GEN(dev_priv) >= 9) {
3666                 skl_detach_scalers(crtc);
3667
3668                 if (pipe_config->pch_pfit.enabled)
3669                         skylake_pfit_enable(crtc);
3670         } else if (HAS_PCH_SPLIT(dev_priv)) {
3671                 if (pipe_config->pch_pfit.enabled)
3672                         ironlake_pfit_enable(crtc);
3673                 else if (old_crtc_state->pch_pfit.enabled)
3674                         ironlake_pfit_disable(crtc, true);
3675         }
3676 }
3677
3678 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3679 {
3680         struct drm_device *dev = crtc->base.dev;
3681         struct drm_i915_private *dev_priv = to_i915(dev);
3682         int pipe = crtc->pipe;
3683         i915_reg_t reg;
3684         u32 temp;
3685
3686         /* enable normal train */
3687         reg = FDI_TX_CTL(pipe);
3688         temp = I915_READ(reg);
3689         if (IS_IVYBRIDGE(dev_priv)) {
3690                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3691                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3692         } else {
3693                 temp &= ~FDI_LINK_TRAIN_NONE;
3694                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3695         }
3696         I915_WRITE(reg, temp);
3697
3698         reg = FDI_RX_CTL(pipe);
3699         temp = I915_READ(reg);
3700         if (HAS_PCH_CPT(dev_priv)) {
3701                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3702                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3703         } else {
3704                 temp &= ~FDI_LINK_TRAIN_NONE;
3705                 temp |= FDI_LINK_TRAIN_NONE;
3706         }
3707         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3708
3709         /* wait one idle pattern time */
3710         POSTING_READ(reg);
3711         udelay(1000);
3712
3713         /* IVB wants error correction enabled */
3714         if (IS_IVYBRIDGE(dev_priv))
3715                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3716                            FDI_FE_ERRC_ENABLE);
3717 }
3718
3719 /* The FDI link training functions for ILK/Ibexpeak. */
3720 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3721                                     const struct intel_crtc_state *crtc_state)
3722 {
3723         struct drm_device *dev = crtc->base.dev;
3724         struct drm_i915_private *dev_priv = to_i915(dev);
3725         int pipe = crtc->pipe;
3726         i915_reg_t reg;
3727         u32 temp, tries;
3728
3729         /* FDI needs bits from pipe first */
3730         assert_pipe_enabled(dev_priv, pipe);
3731
3732         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3733            for train result */
3734         reg = FDI_RX_IMR(pipe);
3735         temp = I915_READ(reg);
3736         temp &= ~FDI_RX_SYMBOL_LOCK;
3737         temp &= ~FDI_RX_BIT_LOCK;
3738         I915_WRITE(reg, temp);
3739         I915_READ(reg);
3740         udelay(150);
3741
3742         /* enable CPU FDI TX and PCH FDI RX */
3743         reg = FDI_TX_CTL(pipe);
3744         temp = I915_READ(reg);
3745         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3746         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3747         temp &= ~FDI_LINK_TRAIN_NONE;
3748         temp |= FDI_LINK_TRAIN_PATTERN_1;
3749         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3750
3751         reg = FDI_RX_CTL(pipe);
3752         temp = I915_READ(reg);
3753         temp &= ~FDI_LINK_TRAIN_NONE;
3754         temp |= FDI_LINK_TRAIN_PATTERN_1;
3755         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3756
3757         POSTING_READ(reg);
3758         udelay(150);
3759
3760         /* Ironlake workaround, enable clock pointer after FDI enable*/
3761         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3762         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3763                    FDI_RX_PHASE_SYNC_POINTER_EN);
3764
3765         reg = FDI_RX_IIR(pipe);
3766         for (tries = 0; tries < 5; tries++) {
3767                 temp = I915_READ(reg);
3768                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3769
3770                 if ((temp & FDI_RX_BIT_LOCK)) {
3771                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3772                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3773                         break;
3774                 }
3775         }
3776         if (tries == 5)
3777                 DRM_ERROR("FDI train 1 fail!\n");
3778
3779         /* Train 2 */
3780         reg = FDI_TX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         temp &= ~FDI_LINK_TRAIN_NONE;
3783         temp |= FDI_LINK_TRAIN_PATTERN_2;
3784         I915_WRITE(reg, temp);
3785
3786         reg = FDI_RX_CTL(pipe);
3787         temp = I915_READ(reg);
3788         temp &= ~FDI_LINK_TRAIN_NONE;
3789         temp |= FDI_LINK_TRAIN_PATTERN_2;
3790         I915_WRITE(reg, temp);
3791
3792         POSTING_READ(reg);
3793         udelay(150);
3794
3795         reg = FDI_RX_IIR(pipe);
3796         for (tries = 0; tries < 5; tries++) {
3797                 temp = I915_READ(reg);
3798                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3799
3800                 if (temp & FDI_RX_SYMBOL_LOCK) {
3801                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3802                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3803                         break;
3804                 }
3805         }
3806         if (tries == 5)
3807                 DRM_ERROR("FDI train 2 fail!\n");
3808
3809         DRM_DEBUG_KMS("FDI train done\n");
3810
3811 }
3812
3813 static const int snb_b_fdi_train_param[] = {
3814         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3815         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3816         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3817         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3818 };
3819
3820 /* The FDI link training functions for SNB/Cougarpoint. */
3821 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3822                                 const struct intel_crtc_state *crtc_state)
3823 {
3824         struct drm_device *dev = crtc->base.dev;
3825         struct drm_i915_private *dev_priv = to_i915(dev);
3826         int pipe = crtc->pipe;
3827         i915_reg_t reg;
3828         u32 temp, i, retry;
3829
3830         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3831            for train result */
3832         reg = FDI_RX_IMR(pipe);
3833         temp = I915_READ(reg);
3834         temp &= ~FDI_RX_SYMBOL_LOCK;
3835         temp &= ~FDI_RX_BIT_LOCK;
3836         I915_WRITE(reg, temp);
3837
3838         POSTING_READ(reg);
3839         udelay(150);
3840
3841         /* enable CPU FDI TX and PCH FDI RX */
3842         reg = FDI_TX_CTL(pipe);
3843         temp = I915_READ(reg);
3844         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3845         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3846         temp &= ~FDI_LINK_TRAIN_NONE;
3847         temp |= FDI_LINK_TRAIN_PATTERN_1;
3848         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3849         /* SNB-B */
3850         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3851         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3852
3853         I915_WRITE(FDI_RX_MISC(pipe),
3854                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3855
3856         reg = FDI_RX_CTL(pipe);
3857         temp = I915_READ(reg);
3858         if (HAS_PCH_CPT(dev_priv)) {
3859                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861         } else {
3862                 temp &= ~FDI_LINK_TRAIN_NONE;
3863                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864         }
3865         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3866
3867         POSTING_READ(reg);
3868         udelay(150);
3869
3870         for (i = 0; i < 4; i++) {
3871                 reg = FDI_TX_CTL(pipe);
3872                 temp = I915_READ(reg);
3873                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3874                 temp |= snb_b_fdi_train_param[i];
3875                 I915_WRITE(reg, temp);
3876
3877                 POSTING_READ(reg);
3878                 udelay(500);
3879
3880                 for (retry = 0; retry < 5; retry++) {
3881                         reg = FDI_RX_IIR(pipe);
3882                         temp = I915_READ(reg);
3883                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3884                         if (temp & FDI_RX_BIT_LOCK) {
3885                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3886                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3887                                 break;
3888                         }
3889                         udelay(50);
3890                 }
3891                 if (retry < 5)
3892                         break;
3893         }
3894         if (i == 4)
3895                 DRM_ERROR("FDI train 1 fail!\n");
3896
3897         /* Train 2 */
3898         reg = FDI_TX_CTL(pipe);
3899         temp = I915_READ(reg);
3900         temp &= ~FDI_LINK_TRAIN_NONE;
3901         temp |= FDI_LINK_TRAIN_PATTERN_2;
3902         if (IS_GEN6(dev_priv)) {
3903                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3904                 /* SNB-B */
3905                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3906         }
3907         I915_WRITE(reg, temp);
3908
3909         reg = FDI_RX_CTL(pipe);
3910         temp = I915_READ(reg);
3911         if (HAS_PCH_CPT(dev_priv)) {
3912                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3913                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3914         } else {
3915                 temp &= ~FDI_LINK_TRAIN_NONE;
3916                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3917         }
3918         I915_WRITE(reg, temp);
3919
3920         POSTING_READ(reg);
3921         udelay(150);
3922
3923         for (i = 0; i < 4; i++) {
3924                 reg = FDI_TX_CTL(pipe);
3925                 temp = I915_READ(reg);
3926                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3927                 temp |= snb_b_fdi_train_param[i];
3928                 I915_WRITE(reg, temp);
3929
3930                 POSTING_READ(reg);
3931                 udelay(500);
3932
3933                 for (retry = 0; retry < 5; retry++) {
3934                         reg = FDI_RX_IIR(pipe);
3935                         temp = I915_READ(reg);
3936                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3937                         if (temp & FDI_RX_SYMBOL_LOCK) {
3938                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3939                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3940                                 break;
3941                         }
3942                         udelay(50);
3943                 }
3944                 if (retry < 5)
3945                         break;
3946         }
3947         if (i == 4)
3948                 DRM_ERROR("FDI train 2 fail!\n");
3949
3950         DRM_DEBUG_KMS("FDI train done.\n");
3951 }
3952
3953 /* Manual link training for Ivy Bridge A0 parts */
3954 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3955                                       const struct intel_crtc_state *crtc_state)
3956 {
3957         struct drm_device *dev = crtc->base.dev;
3958         struct drm_i915_private *dev_priv = to_i915(dev);
3959         int pipe = crtc->pipe;
3960         i915_reg_t reg;
3961         u32 temp, i, j;
3962
3963         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3964            for train result */
3965         reg = FDI_RX_IMR(pipe);
3966         temp = I915_READ(reg);
3967         temp &= ~FDI_RX_SYMBOL_LOCK;
3968         temp &= ~FDI_RX_BIT_LOCK;
3969         I915_WRITE(reg, temp);
3970
3971         POSTING_READ(reg);
3972         udelay(150);
3973
3974         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3975                       I915_READ(FDI_RX_IIR(pipe)));
3976
3977         /* Try each vswing and preemphasis setting twice before moving on */
3978         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3979                 /* disable first in case we need to retry */
3980                 reg = FDI_TX_CTL(pipe);
3981                 temp = I915_READ(reg);
3982                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3983                 temp &= ~FDI_TX_ENABLE;
3984                 I915_WRITE(reg, temp);
3985
3986                 reg = FDI_RX_CTL(pipe);
3987                 temp = I915_READ(reg);
3988                 temp &= ~FDI_LINK_TRAIN_AUTO;
3989                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3990                 temp &= ~FDI_RX_ENABLE;
3991                 I915_WRITE(reg, temp);
3992
3993                 /* enable CPU FDI TX and PCH FDI RX */
3994                 reg = FDI_TX_CTL(pipe);
3995                 temp = I915_READ(reg);
3996                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3997                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3998                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3999                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4000                 temp |= snb_b_fdi_train_param[j/2];
4001                 temp |= FDI_COMPOSITE_SYNC;
4002                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4003
4004                 I915_WRITE(FDI_RX_MISC(pipe),
4005                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4006
4007                 reg = FDI_RX_CTL(pipe);
4008                 temp = I915_READ(reg);
4009                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4010                 temp |= FDI_COMPOSITE_SYNC;
4011                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4012
4013                 POSTING_READ(reg);
4014                 udelay(1); /* should be 0.5us */
4015
4016                 for (i = 0; i < 4; i++) {
4017                         reg = FDI_RX_IIR(pipe);
4018                         temp = I915_READ(reg);
4019                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4020
4021                         if (temp & FDI_RX_BIT_LOCK ||
4022                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4023                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4024                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4025                                               i);
4026                                 break;
4027                         }
4028                         udelay(1); /* should be 0.5us */
4029                 }
4030                 if (i == 4) {
4031                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4032                         continue;
4033                 }
4034
4035                 /* Train 2 */
4036                 reg = FDI_TX_CTL(pipe);
4037                 temp = I915_READ(reg);
4038                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4039                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4040                 I915_WRITE(reg, temp);
4041
4042                 reg = FDI_RX_CTL(pipe);
4043                 temp = I915_READ(reg);
4044                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4045                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4046                 I915_WRITE(reg, temp);
4047
4048                 POSTING_READ(reg);
4049                 udelay(2); /* should be 1.5us */
4050
4051                 for (i = 0; i < 4; i++) {
4052                         reg = FDI_RX_IIR(pipe);
4053                         temp = I915_READ(reg);
4054                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4055
4056                         if (temp & FDI_RX_SYMBOL_LOCK ||
4057                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4058                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4059                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4060                                               i);
4061                                 goto train_done;
4062                         }
4063                         udelay(2); /* should be 1.5us */
4064                 }
4065                 if (i == 4)
4066                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4067         }
4068
4069 train_done:
4070         DRM_DEBUG_KMS("FDI train done.\n");
4071 }
4072
4073 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4074 {
4075         struct drm_device *dev = intel_crtc->base.dev;
4076         struct drm_i915_private *dev_priv = to_i915(dev);
4077         int pipe = intel_crtc->pipe;
4078         i915_reg_t reg;
4079         u32 temp;
4080
4081         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4082         reg = FDI_RX_CTL(pipe);
4083         temp = I915_READ(reg);
4084         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4085         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4086         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4087         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4088
4089         POSTING_READ(reg);
4090         udelay(200);
4091
4092         /* Switch from Rawclk to PCDclk */
4093         temp = I915_READ(reg);
4094         I915_WRITE(reg, temp | FDI_PCDCLK);
4095
4096         POSTING_READ(reg);
4097         udelay(200);
4098
4099         /* Enable CPU FDI TX PLL, always on for Ironlake */
4100         reg = FDI_TX_CTL(pipe);
4101         temp = I915_READ(reg);
4102         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4103                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4104
4105                 POSTING_READ(reg);
4106                 udelay(100);
4107         }
4108 }
4109
4110 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4111 {
4112         struct drm_device *dev = intel_crtc->base.dev;
4113         struct drm_i915_private *dev_priv = to_i915(dev);
4114         int pipe = intel_crtc->pipe;
4115         i915_reg_t reg;
4116         u32 temp;
4117
4118         /* Switch from PCDclk to Rawclk */
4119         reg = FDI_RX_CTL(pipe);
4120         temp = I915_READ(reg);
4121         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4122
4123         /* Disable CPU FDI TX PLL */
4124         reg = FDI_TX_CTL(pipe);
4125         temp = I915_READ(reg);
4126         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4127
4128         POSTING_READ(reg);
4129         udelay(100);
4130
4131         reg = FDI_RX_CTL(pipe);
4132         temp = I915_READ(reg);
4133         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4134
4135         /* Wait for the clocks to turn off. */
4136         POSTING_READ(reg);
4137         udelay(100);
4138 }
4139
4140 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = to_i915(dev);
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         int pipe = intel_crtc->pipe;
4146         i915_reg_t reg;
4147         u32 temp;
4148
4149         /* disable CPU FDI tx and PCH FDI rx */
4150         reg = FDI_TX_CTL(pipe);
4151         temp = I915_READ(reg);
4152         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4153         POSTING_READ(reg);
4154
4155         reg = FDI_RX_CTL(pipe);
4156         temp = I915_READ(reg);
4157         temp &= ~(0x7 << 16);
4158         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4159         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4160
4161         POSTING_READ(reg);
4162         udelay(100);
4163
4164         /* Ironlake workaround, disable clock pointer after downing FDI */
4165         if (HAS_PCH_IBX(dev_priv))
4166                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4167
4168         /* still set train pattern 1 */
4169         reg = FDI_TX_CTL(pipe);
4170         temp = I915_READ(reg);
4171         temp &= ~FDI_LINK_TRAIN_NONE;
4172         temp |= FDI_LINK_TRAIN_PATTERN_1;
4173         I915_WRITE(reg, temp);
4174
4175         reg = FDI_RX_CTL(pipe);
4176         temp = I915_READ(reg);
4177         if (HAS_PCH_CPT(dev_priv)) {
4178                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4179                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4180         } else {
4181                 temp &= ~FDI_LINK_TRAIN_NONE;
4182                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4183         }
4184         /* BPC in FDI rx is consistent with that in PIPECONF */
4185         temp &= ~(0x07 << 16);
4186         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4187         I915_WRITE(reg, temp);
4188
4189         POSTING_READ(reg);
4190         udelay(100);
4191 }
4192
4193 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4194 {
4195         struct intel_crtc *crtc;
4196
4197         /* Note that we don't need to be called with mode_config.lock here
4198          * as our list of CRTC objects is static for the lifetime of the
4199          * device and so cannot disappear as we iterate. Similarly, we can
4200          * happily treat the predicates as racy, atomic checks as userspace
4201          * cannot claim and pin a new fb without at least acquring the
4202          * struct_mutex and so serialising with us.
4203          */
4204         for_each_intel_crtc(&dev_priv->drm, crtc) {
4205                 if (atomic_read(&crtc->unpin_work_count) == 0)
4206                         continue;
4207
4208                 if (crtc->flip_work)
4209                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4210
4211                 return true;
4212         }
4213
4214         return false;
4215 }
4216
4217 static void page_flip_completed(struct intel_crtc *intel_crtc)
4218 {
4219         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4220         struct intel_flip_work *work = intel_crtc->flip_work;
4221
4222         intel_crtc->flip_work = NULL;
4223
4224         if (work->event)
4225                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4226
4227         drm_crtc_vblank_put(&intel_crtc->base);
4228
4229         wake_up_all(&dev_priv->pending_flip_queue);
4230         trace_i915_flip_complete(intel_crtc->plane,
4231                                  work->pending_flip_obj);
4232
4233         queue_work(dev_priv->wq, &work->unpin_work);
4234 }
4235
4236 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4237 {
4238         struct drm_device *dev = crtc->dev;
4239         struct drm_i915_private *dev_priv = to_i915(dev);
4240         long ret;
4241
4242         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4243
4244         ret = wait_event_interruptible_timeout(
4245                                         dev_priv->pending_flip_queue,
4246                                         !intel_crtc_has_pending_flip(crtc),
4247                                         60*HZ);
4248
4249         if (ret < 0)
4250                 return ret;
4251
4252         if (ret == 0) {
4253                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4254                 struct intel_flip_work *work;
4255
4256                 spin_lock_irq(&dev->event_lock);
4257                 work = intel_crtc->flip_work;
4258                 if (work && !is_mmio_work(work)) {
4259                         WARN_ONCE(1, "Removing stuck page flip\n");
4260                         page_flip_completed(intel_crtc);
4261                 }
4262                 spin_unlock_irq(&dev->event_lock);
4263         }
4264
4265         return 0;
4266 }
4267
4268 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4269 {
4270         u32 temp;
4271
4272         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4273
4274         mutex_lock(&dev_priv->sb_lock);
4275
4276         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4277         temp |= SBI_SSCCTL_DISABLE;
4278         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4279
4280         mutex_unlock(&dev_priv->sb_lock);
4281 }
4282
4283 /* Program iCLKIP clock to the desired frequency */
4284 static void lpt_program_iclkip(struct intel_crtc *crtc)
4285 {
4286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4287         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4288         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4289         u32 temp;
4290
4291         lpt_disable_iclkip(dev_priv);
4292
4293         /* The iCLK virtual clock root frequency is in MHz,
4294          * but the adjusted_mode->crtc_clock in in KHz. To get the
4295          * divisors, it is necessary to divide one by another, so we
4296          * convert the virtual clock precision to KHz here for higher
4297          * precision.
4298          */
4299         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4300                 u32 iclk_virtual_root_freq = 172800 * 1000;
4301                 u32 iclk_pi_range = 64;
4302                 u32 desired_divisor;
4303
4304                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4305                                                     clock << auxdiv);
4306                 divsel = (desired_divisor / iclk_pi_range) - 2;
4307                 phaseinc = desired_divisor % iclk_pi_range;
4308
4309                 /*
4310                  * Near 20MHz is a corner case which is
4311                  * out of range for the 7-bit divisor
4312                  */
4313                 if (divsel <= 0x7f)
4314                         break;
4315         }
4316
4317         /* This should not happen with any sane values */
4318         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4319                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4320         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4321                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4322
4323         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4324                         clock,
4325                         auxdiv,
4326                         divsel,
4327                         phasedir,
4328                         phaseinc);
4329
4330         mutex_lock(&dev_priv->sb_lock);
4331
4332         /* Program SSCDIVINTPHASE6 */
4333         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4334         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4335         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4336         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4337         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4338         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4339         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4340         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4341
4342         /* Program SSCAUXDIV */
4343         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4344         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4345         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4346         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4347
4348         /* Enable modulator and associated divider */
4349         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4350         temp &= ~SBI_SSCCTL_DISABLE;
4351         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4352
4353         mutex_unlock(&dev_priv->sb_lock);
4354
4355         /* Wait for initialization time */
4356         udelay(24);
4357
4358         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4359 }
4360
4361 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4362 {
4363         u32 divsel, phaseinc, auxdiv;
4364         u32 iclk_virtual_root_freq = 172800 * 1000;
4365         u32 iclk_pi_range = 64;
4366         u32 desired_divisor;
4367         u32 temp;
4368
4369         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4370                 return 0;
4371
4372         mutex_lock(&dev_priv->sb_lock);
4373
4374         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4375         if (temp & SBI_SSCCTL_DISABLE) {
4376                 mutex_unlock(&dev_priv->sb_lock);
4377                 return 0;
4378         }
4379
4380         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4381         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4382                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4383         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4384                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4385
4386         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4387         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4388                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4389
4390         mutex_unlock(&dev_priv->sb_lock);
4391
4392         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4393
4394         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4395                                  desired_divisor << auxdiv);
4396 }
4397
4398 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4399                                                 enum pipe pch_transcoder)
4400 {
4401         struct drm_device *dev = crtc->base.dev;
4402         struct drm_i915_private *dev_priv = to_i915(dev);
4403         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4404
4405         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4406                    I915_READ(HTOTAL(cpu_transcoder)));
4407         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4408                    I915_READ(HBLANK(cpu_transcoder)));
4409         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4410                    I915_READ(HSYNC(cpu_transcoder)));
4411
4412         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4413                    I915_READ(VTOTAL(cpu_transcoder)));
4414         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4415                    I915_READ(VBLANK(cpu_transcoder)));
4416         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4417                    I915_READ(VSYNC(cpu_transcoder)));
4418         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4419                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4420 }
4421
4422 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4423 {
4424         struct drm_i915_private *dev_priv = to_i915(dev);
4425         uint32_t temp;
4426
4427         temp = I915_READ(SOUTH_CHICKEN1);
4428         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4429                 return;
4430
4431         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4432         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4433
4434         temp &= ~FDI_BC_BIFURCATION_SELECT;
4435         if (enable)
4436                 temp |= FDI_BC_BIFURCATION_SELECT;
4437
4438         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4439         I915_WRITE(SOUTH_CHICKEN1, temp);
4440         POSTING_READ(SOUTH_CHICKEN1);
4441 }
4442
4443 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4444 {
4445         struct drm_device *dev = intel_crtc->base.dev;
4446
4447         switch (intel_crtc->pipe) {
4448         case PIPE_A:
4449                 break;
4450         case PIPE_B:
4451                 if (intel_crtc->config->fdi_lanes > 2)
4452                         cpt_set_fdi_bc_bifurcation(dev, false);
4453                 else
4454                         cpt_set_fdi_bc_bifurcation(dev, true);
4455
4456                 break;
4457         case PIPE_C:
4458                 cpt_set_fdi_bc_bifurcation(dev, true);
4459
4460                 break;
4461         default:
4462                 BUG();
4463         }
4464 }
4465
4466 /* Return which DP Port should be selected for Transcoder DP control */
4467 static enum port
4468 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4469 {
4470         struct drm_device *dev = crtc->base.dev;
4471         struct intel_encoder *encoder;
4472
4473         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4474                 if (encoder->type == INTEL_OUTPUT_DP ||
4475                     encoder->type == INTEL_OUTPUT_EDP)
4476                         return enc_to_dig_port(&encoder->base)->port;
4477         }
4478
4479         return -1;
4480 }
4481
4482 /*
4483  * Enable PCH resources required for PCH ports:
4484  *   - PCH PLLs
4485  *   - FDI training & RX/TX
4486  *   - update transcoder timings
4487  *   - DP transcoding bits
4488  *   - transcoder
4489  */
4490 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4491 {
4492         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4493         struct drm_device *dev = crtc->base.dev;
4494         struct drm_i915_private *dev_priv = to_i915(dev);
4495         int pipe = crtc->pipe;
4496         u32 temp;
4497
4498         assert_pch_transcoder_disabled(dev_priv, pipe);
4499
4500         if (IS_IVYBRIDGE(dev_priv))
4501                 ivybridge_update_fdi_bc_bifurcation(crtc);
4502
4503         /* Write the TU size bits before fdi link training, so that error
4504          * detection works. */
4505         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4506                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4507
4508         /* For PCH output, training FDI link */
4509         dev_priv->display.fdi_link_train(crtc, crtc_state);
4510
4511         /* We need to program the right clock selection before writing the pixel
4512          * mutliplier into the DPLL. */
4513         if (HAS_PCH_CPT(dev_priv)) {
4514                 u32 sel;
4515
4516                 temp = I915_READ(PCH_DPLL_SEL);
4517                 temp |= TRANS_DPLL_ENABLE(pipe);
4518                 sel = TRANS_DPLLB_SEL(pipe);
4519                 if (crtc_state->shared_dpll ==
4520                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4521                         temp |= sel;
4522                 else
4523                         temp &= ~sel;
4524                 I915_WRITE(PCH_DPLL_SEL, temp);
4525         }
4526
4527         /* XXX: pch pll's can be enabled any time before we enable the PCH
4528          * transcoder, and we actually should do this to not upset any PCH
4529          * transcoder that already use the clock when we share it.
4530          *
4531          * Note that enable_shared_dpll tries to do the right thing, but
4532          * get_shared_dpll unconditionally resets the pll - we need that to have
4533          * the right LVDS enable sequence. */
4534         intel_enable_shared_dpll(crtc);
4535
4536         /* set transcoder timing, panel must allow it */
4537         assert_panel_unlocked(dev_priv, pipe);
4538         ironlake_pch_transcoder_set_timings(crtc, pipe);
4539
4540         intel_fdi_normal_train(crtc);
4541
4542         /* For PCH DP, enable TRANS_DP_CTL */
4543         if (HAS_PCH_CPT(dev_priv) &&
4544             intel_crtc_has_dp_encoder(crtc_state)) {
4545                 const struct drm_display_mode *adjusted_mode =
4546                         &crtc_state->base.adjusted_mode;
4547                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4548                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4549                 temp = I915_READ(reg);
4550                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4551                           TRANS_DP_SYNC_MASK |
4552                           TRANS_DP_BPC_MASK);
4553                 temp |= TRANS_DP_OUTPUT_ENABLE;
4554                 temp |= bpc << 9; /* same format but at 11:9 */
4555
4556                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4557                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4558                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4559                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4560
4561                 switch (intel_trans_dp_port_sel(crtc)) {
4562                 case PORT_B:
4563                         temp |= TRANS_DP_PORT_SEL_B;
4564                         break;
4565                 case PORT_C:
4566                         temp |= TRANS_DP_PORT_SEL_C;
4567                         break;
4568                 case PORT_D:
4569                         temp |= TRANS_DP_PORT_SEL_D;
4570                         break;
4571                 default:
4572                         BUG();
4573                 }
4574
4575                 I915_WRITE(reg, temp);
4576         }
4577
4578         ironlake_enable_pch_transcoder(dev_priv, pipe);
4579 }
4580
4581 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4582 {
4583         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4584         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4585         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4586
4587         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4588
4589         lpt_program_iclkip(crtc);
4590
4591         /* Set transcoder timing. */
4592         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4593
4594         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4595 }
4596
4597 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4598 {
4599         struct drm_i915_private *dev_priv = to_i915(dev);
4600         i915_reg_t dslreg = PIPEDSL(pipe);
4601         u32 temp;
4602
4603         temp = I915_READ(dslreg);
4604         udelay(500);
4605         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4606                 if (wait_for(I915_READ(dslreg) != temp, 5))
4607                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4608         }
4609 }
4610
4611 static int
4612 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4613                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4614                   int src_w, int src_h, int dst_w, int dst_h)
4615 {
4616         struct intel_crtc_scaler_state *scaler_state =
4617                 &crtc_state->scaler_state;
4618         struct intel_crtc *intel_crtc =
4619                 to_intel_crtc(crtc_state->base.crtc);
4620         int need_scaling;
4621
4622         need_scaling = drm_rotation_90_or_270(rotation) ?
4623                 (src_h != dst_w || src_w != dst_h):
4624                 (src_w != dst_w || src_h != dst_h);
4625
4626         /*
4627          * if plane is being disabled or scaler is no more required or force detach
4628          *  - free scaler binded to this plane/crtc
4629          *  - in order to do this, update crtc->scaler_usage
4630          *
4631          * Here scaler state in crtc_state is set free so that
4632          * scaler can be assigned to other user. Actual register
4633          * update to free the scaler is done in plane/panel-fit programming.
4634          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4635          */
4636         if (force_detach || !need_scaling) {
4637                 if (*scaler_id >= 0) {
4638                         scaler_state->scaler_users &= ~(1 << scaler_user);
4639                         scaler_state->scalers[*scaler_id].in_use = 0;
4640
4641                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4642                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4643                                 intel_crtc->pipe, scaler_user, *scaler_id,
4644                                 scaler_state->scaler_users);
4645                         *scaler_id = -1;
4646                 }
4647                 return 0;
4648         }
4649
4650         /* range checks */
4651         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4652                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4653
4654                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4655                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4656                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4657                         "size is out of scaler range\n",
4658                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4659                 return -EINVAL;
4660         }
4661
4662         /* mark this plane as a scaler user in crtc_state */
4663         scaler_state->scaler_users |= (1 << scaler_user);
4664         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4665                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4666                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4667                 scaler_state->scaler_users);
4668
4669         return 0;
4670 }
4671
4672 /**
4673  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4674  *
4675  * @state: crtc's scaler state
4676  *
4677  * Return
4678  *     0 - scaler_usage updated successfully
4679  *    error - requested scaling cannot be supported or other error condition
4680  */
4681 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4682 {
4683         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4684
4685         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4686                 &state->scaler_state.scaler_id, DRM_MODE_ROTATE_0,
4687                 state->pipe_src_w, state->pipe_src_h,
4688                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4689 }
4690
4691 /**
4692  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4693  *
4694  * @state: crtc's scaler state
4695  * @plane_state: atomic plane state to update
4696  *
4697  * Return
4698  *     0 - scaler_usage updated successfully
4699  *    error - requested scaling cannot be supported or other error condition
4700  */
4701 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4702                                    struct intel_plane_state *plane_state)
4703 {
4704
4705         struct intel_plane *intel_plane =
4706                 to_intel_plane(plane_state->base.plane);
4707         struct drm_framebuffer *fb = plane_state->base.fb;
4708         int ret;
4709
4710         bool force_detach = !fb || !plane_state->base.visible;
4711
4712         ret = skl_update_scaler(crtc_state, force_detach,
4713                                 drm_plane_index(&intel_plane->base),
4714                                 &plane_state->scaler_id,
4715                                 plane_state->base.rotation,
4716                                 drm_rect_width(&plane_state->base.src) >> 16,
4717                                 drm_rect_height(&plane_state->base.src) >> 16,
4718                                 drm_rect_width(&plane_state->base.dst),
4719                                 drm_rect_height(&plane_state->base.dst));
4720
4721         if (ret || plane_state->scaler_id < 0)
4722                 return ret;
4723
4724         /* check colorkey */
4725         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4726                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4727                               intel_plane->base.base.id,
4728                               intel_plane->base.name);
4729                 return -EINVAL;
4730         }
4731
4732         /* Check src format */
4733         switch (fb->format->format) {
4734         case DRM_FORMAT_RGB565:
4735         case DRM_FORMAT_XBGR8888:
4736         case DRM_FORMAT_XRGB8888:
4737         case DRM_FORMAT_ABGR8888:
4738         case DRM_FORMAT_ARGB8888:
4739         case DRM_FORMAT_XRGB2101010:
4740         case DRM_FORMAT_XBGR2101010:
4741         case DRM_FORMAT_YUYV:
4742         case DRM_FORMAT_YVYU:
4743         case DRM_FORMAT_UYVY:
4744         case DRM_FORMAT_VYUY:
4745                 break;
4746         default:
4747                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4748                               intel_plane->base.base.id, intel_plane->base.name,
4749                               fb->base.id, fb->format->format);
4750                 return -EINVAL;
4751         }
4752
4753         return 0;
4754 }
4755
4756 static void skylake_scaler_disable(struct intel_crtc *crtc)
4757 {
4758         int i;
4759
4760         for (i = 0; i < crtc->num_scalers; i++)
4761                 skl_detach_scaler(crtc, i);
4762 }
4763
4764 static void skylake_pfit_enable(struct intel_crtc *crtc)
4765 {
4766         struct drm_device *dev = crtc->base.dev;
4767         struct drm_i915_private *dev_priv = to_i915(dev);
4768         int pipe = crtc->pipe;
4769         struct intel_crtc_scaler_state *scaler_state =
4770                 &crtc->config->scaler_state;
4771
4772         if (crtc->config->pch_pfit.enabled) {
4773                 int id;
4774
4775                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4776                         return;
4777
4778                 id = scaler_state->scaler_id;
4779                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4780                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4781                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4782                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4783         }
4784 }
4785
4786 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4787 {
4788         struct drm_device *dev = crtc->base.dev;
4789         struct drm_i915_private *dev_priv = to_i915(dev);
4790         int pipe = crtc->pipe;
4791
4792         if (crtc->config->pch_pfit.enabled) {
4793                 /* Force use of hard-coded filter coefficients
4794                  * as some pre-programmed values are broken,
4795                  * e.g. x201.
4796                  */
4797                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4798                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4799                                                  PF_PIPE_SEL_IVB(pipe));
4800                 else
4801                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4802                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4803                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4804         }
4805 }
4806
4807 void hsw_enable_ips(struct intel_crtc *crtc)
4808 {
4809         struct drm_device *dev = crtc->base.dev;
4810         struct drm_i915_private *dev_priv = to_i915(dev);
4811
4812         if (!crtc->config->ips_enabled)
4813                 return;
4814
4815         /*
4816          * We can only enable IPS after we enable a plane and wait for a vblank
4817          * This function is called from post_plane_update, which is run after
4818          * a vblank wait.
4819          */
4820
4821         assert_plane_enabled(dev_priv, crtc->plane);
4822         if (IS_BROADWELL(dev_priv)) {
4823                 mutex_lock(&dev_priv->rps.hw_lock);
4824                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4825                 mutex_unlock(&dev_priv->rps.hw_lock);
4826                 /* Quoting Art Runyan: "its not safe to expect any particular
4827                  * value in IPS_CTL bit 31 after enabling IPS through the
4828                  * mailbox." Moreover, the mailbox may return a bogus state,
4829                  * so we need to just enable it and continue on.
4830                  */
4831         } else {
4832                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4833                 /* The bit only becomes 1 in the next vblank, so this wait here
4834                  * is essentially intel_wait_for_vblank. If we don't have this
4835                  * and don't wait for vblanks until the end of crtc_enable, then
4836                  * the HW state readout code will complain that the expected
4837                  * IPS_CTL value is not the one we read. */
4838                 if (intel_wait_for_register(dev_priv,
4839                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4840                                             50))
4841                         DRM_ERROR("Timed out waiting for IPS enable\n");
4842         }
4843 }
4844
4845 void hsw_disable_ips(struct intel_crtc *crtc)
4846 {
4847         struct drm_device *dev = crtc->base.dev;
4848         struct drm_i915_private *dev_priv = to_i915(dev);
4849
4850         if (!crtc->config->ips_enabled)
4851                 return;
4852
4853         assert_plane_enabled(dev_priv, crtc->plane);
4854         if (IS_BROADWELL(dev_priv)) {
4855                 mutex_lock(&dev_priv->rps.hw_lock);
4856                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4857                 mutex_unlock(&dev_priv->rps.hw_lock);
4858                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4859                 if (intel_wait_for_register(dev_priv,
4860                                             IPS_CTL, IPS_ENABLE, 0,
4861                                             42))
4862                         DRM_ERROR("Timed out waiting for IPS disable\n");
4863         } else {
4864                 I915_WRITE(IPS_CTL, 0);
4865                 POSTING_READ(IPS_CTL);
4866         }
4867
4868         /* We need to wait for a vblank before we can disable the plane. */
4869         intel_wait_for_vblank(dev_priv, crtc->pipe);
4870 }
4871
4872 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4873 {
4874         if (intel_crtc->overlay) {
4875                 struct drm_device *dev = intel_crtc->base.dev;
4876
4877                 mutex_lock(&dev->struct_mutex);
4878                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4879                 mutex_unlock(&dev->struct_mutex);
4880         }
4881
4882         /* Let userspace switch the overlay on again. In most cases userspace
4883          * has to recompute where to put it anyway.
4884          */
4885 }
4886
4887 /**
4888  * intel_post_enable_primary - Perform operations after enabling primary plane
4889  * @crtc: the CRTC whose primary plane was just enabled
4890  *
4891  * Performs potentially sleeping operations that must be done after the primary
4892  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4893  * called due to an explicit primary plane update, or due to an implicit
4894  * re-enable that is caused when a sprite plane is updated to no longer
4895  * completely hide the primary plane.
4896  */
4897 static void
4898 intel_post_enable_primary(struct drm_crtc *crtc)
4899 {
4900         struct drm_device *dev = crtc->dev;
4901         struct drm_i915_private *dev_priv = to_i915(dev);
4902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4903         int pipe = intel_crtc->pipe;
4904
4905         /*
4906          * FIXME IPS should be fine as long as one plane is
4907          * enabled, but in practice it seems to have problems
4908          * when going from primary only to sprite only and vice
4909          * versa.
4910          */
4911         hsw_enable_ips(intel_crtc);
4912
4913         /*
4914          * Gen2 reports pipe underruns whenever all planes are disabled.
4915          * So don't enable underrun reporting before at least some planes
4916          * are enabled.
4917          * FIXME: Need to fix the logic to work when we turn off all planes
4918          * but leave the pipe running.
4919          */
4920         if (IS_GEN2(dev_priv))
4921                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4922
4923         /* Underruns don't always raise interrupts, so check manually. */
4924         intel_check_cpu_fifo_underruns(dev_priv);
4925         intel_check_pch_fifo_underruns(dev_priv);
4926 }
4927
4928 /* FIXME move all this to pre_plane_update() with proper state tracking */
4929 static void
4930 intel_pre_disable_primary(struct drm_crtc *crtc)
4931 {
4932         struct drm_device *dev = crtc->dev;
4933         struct drm_i915_private *dev_priv = to_i915(dev);
4934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4935         int pipe = intel_crtc->pipe;
4936
4937         /*
4938          * Gen2 reports pipe underruns whenever all planes are disabled.
4939          * So diasble underrun reporting before all the planes get disabled.
4940          * FIXME: Need to fix the logic to work when we turn off all planes
4941          * but leave the pipe running.
4942          */
4943         if (IS_GEN2(dev_priv))
4944                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4945
4946         /*
4947          * FIXME IPS should be fine as long as one plane is
4948          * enabled, but in practice it seems to have problems
4949          * when going from primary only to sprite only and vice
4950          * versa.
4951          */
4952         hsw_disable_ips(intel_crtc);
4953 }
4954
4955 /* FIXME get rid of this and use pre_plane_update */
4956 static void
4957 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4958 {
4959         struct drm_device *dev = crtc->dev;
4960         struct drm_i915_private *dev_priv = to_i915(dev);
4961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962         int pipe = intel_crtc->pipe;
4963
4964         intel_pre_disable_primary(crtc);
4965
4966         /*
4967          * Vblank time updates from the shadow to live plane control register
4968          * are blocked if the memory self-refresh mode is active at that
4969          * moment. So to make sure the plane gets truly disabled, disable
4970          * first the self-refresh mode. The self-refresh enable bit in turn
4971          * will be checked/applied by the HW only at the next frame start
4972          * event which is after the vblank start event, so we need to have a
4973          * wait-for-vblank between disabling the plane and the pipe.
4974          */
4975         if (HAS_GMCH_DISPLAY(dev_priv) &&
4976             intel_set_memory_cxsr(dev_priv, false))
4977                 intel_wait_for_vblank(dev_priv, pipe);
4978 }
4979
4980 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4981 {
4982         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4983         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4984         struct intel_crtc_state *pipe_config =
4985                 to_intel_crtc_state(crtc->base.state);
4986         struct drm_plane *primary = crtc->base.primary;
4987         struct drm_plane_state *old_pri_state =
4988                 drm_atomic_get_existing_plane_state(old_state, primary);
4989
4990         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4991
4992         if (pipe_config->update_wm_post && pipe_config->base.active)
4993                 intel_update_watermarks(crtc);
4994
4995         if (old_pri_state) {
4996                 struct intel_plane_state *primary_state =
4997                         to_intel_plane_state(primary->state);
4998                 struct intel_plane_state *old_primary_state =
4999                         to_intel_plane_state(old_pri_state);
5000
5001                 intel_fbc_post_update(crtc);
5002
5003                 if (primary_state->base.visible &&
5004                     (needs_modeset(&pipe_config->base) ||
5005                      !old_primary_state->base.visible))
5006                         intel_post_enable_primary(&crtc->base);
5007         }
5008 }
5009
5010 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5011                                    struct intel_crtc_state *pipe_config)
5012 {
5013         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5014         struct drm_device *dev = crtc->base.dev;
5015         struct drm_i915_private *dev_priv = to_i915(dev);
5016         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5017         struct drm_plane *primary = crtc->base.primary;
5018         struct drm_plane_state *old_pri_state =
5019                 drm_atomic_get_existing_plane_state(old_state, primary);
5020         bool modeset = needs_modeset(&pipe_config->base);
5021         struct intel_atomic_state *old_intel_state =
5022                 to_intel_atomic_state(old_state);
5023
5024         if (old_pri_state) {
5025                 struct intel_plane_state *primary_state =
5026                         to_intel_plane_state(primary->state);
5027                 struct intel_plane_state *old_primary_state =
5028                         to_intel_plane_state(old_pri_state);
5029
5030                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5031
5032                 if (old_primary_state->base.visible &&
5033                     (modeset || !primary_state->base.visible))
5034                         intel_pre_disable_primary(&crtc->base);
5035         }
5036
5037         /*
5038          * Vblank time updates from the shadow to live plane control register
5039          * are blocked if the memory self-refresh mode is active at that
5040          * moment. So to make sure the plane gets truly disabled, disable
5041          * first the self-refresh mode. The self-refresh enable bit in turn
5042          * will be checked/applied by the HW only at the next frame start
5043          * event which is after the vblank start event, so we need to have a
5044          * wait-for-vblank between disabling the plane and the pipe.
5045          */
5046         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5047             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5048                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5049
5050         /*
5051          * IVB workaround: must disable low power watermarks for at least
5052          * one frame before enabling scaling.  LP watermarks can be re-enabled
5053          * when scaling is disabled.
5054          *
5055          * WaCxSRDisabledForSpriteScaling:ivb
5056          */
5057         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5058                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5059
5060         /*
5061          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5062          * watermark programming here.
5063          */
5064         if (needs_modeset(&pipe_config->base))
5065                 return;
5066
5067         /*
5068          * For platforms that support atomic watermarks, program the
5069          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5070          * will be the intermediate values that are safe for both pre- and
5071          * post- vblank; when vblank happens, the 'active' values will be set
5072          * to the final 'target' values and we'll do this again to get the
5073          * optimal watermarks.  For gen9+ platforms, the values we program here
5074          * will be the final target values which will get automatically latched
5075          * at vblank time; no further programming will be necessary.
5076          *
5077          * If a platform hasn't been transitioned to atomic watermarks yet,
5078          * we'll continue to update watermarks the old way, if flags tell
5079          * us to.
5080          */
5081         if (dev_priv->display.initial_watermarks != NULL)
5082                 dev_priv->display.initial_watermarks(old_intel_state,
5083                                                      pipe_config);
5084         else if (pipe_config->update_wm_pre)
5085                 intel_update_watermarks(crtc);
5086 }
5087
5088 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5089 {
5090         struct drm_device *dev = crtc->dev;
5091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5092         struct drm_plane *p;
5093         int pipe = intel_crtc->pipe;
5094
5095         intel_crtc_dpms_overlay_disable(intel_crtc);
5096
5097         drm_for_each_plane_mask(p, dev, plane_mask)
5098                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5099
5100         /*
5101          * FIXME: Once we grow proper nuclear flip support out of this we need
5102          * to compute the mask of flip planes precisely. For the time being
5103          * consider this a flip to a NULL plane.
5104          */
5105         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5106 }
5107
5108 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5109                                           struct intel_crtc_state *crtc_state,
5110                                           struct drm_atomic_state *old_state)
5111 {
5112         struct drm_connector_state *conn_state;
5113         struct drm_connector *conn;
5114         int i;
5115
5116         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5117                 struct intel_encoder *encoder =
5118                         to_intel_encoder(conn_state->best_encoder);
5119
5120                 if (conn_state->crtc != crtc)
5121                         continue;
5122
5123                 if (encoder->pre_pll_enable)
5124                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5125         }
5126 }
5127
5128 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5129                                       struct intel_crtc_state *crtc_state,
5130                                       struct drm_atomic_state *old_state)
5131 {
5132         struct drm_connector_state *conn_state;
5133         struct drm_connector *conn;
5134         int i;
5135
5136         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5137                 struct intel_encoder *encoder =
5138                         to_intel_encoder(conn_state->best_encoder);
5139
5140                 if (conn_state->crtc != crtc)
5141                         continue;
5142
5143                 if (encoder->pre_enable)
5144                         encoder->pre_enable(encoder, crtc_state, conn_state);
5145         }
5146 }
5147
5148 static void intel_encoders_enable(struct drm_crtc *crtc,
5149                                   struct intel_crtc_state *crtc_state,
5150                                   struct drm_atomic_state *old_state)
5151 {
5152         struct drm_connector_state *conn_state;
5153         struct drm_connector *conn;
5154         int i;
5155
5156         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5157                 struct intel_encoder *encoder =
5158                         to_intel_encoder(conn_state->best_encoder);
5159
5160                 if (conn_state->crtc != crtc)
5161                         continue;
5162
5163                 encoder->enable(encoder, crtc_state, conn_state);
5164                 intel_opregion_notify_encoder(encoder, true);
5165         }
5166 }
5167
5168 static void intel_encoders_disable(struct drm_crtc *crtc,
5169                                    struct intel_crtc_state *old_crtc_state,
5170                                    struct drm_atomic_state *old_state)
5171 {
5172         struct drm_connector_state *old_conn_state;
5173         struct drm_connector *conn;
5174         int i;
5175
5176         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5177                 struct intel_encoder *encoder =
5178                         to_intel_encoder(old_conn_state->best_encoder);
5179
5180                 if (old_conn_state->crtc != crtc)
5181                         continue;
5182
5183                 intel_opregion_notify_encoder(encoder, false);
5184                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5185         }
5186 }
5187
5188 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5189                                         struct intel_crtc_state *old_crtc_state,
5190                                         struct drm_atomic_state *old_state)
5191 {
5192         struct drm_connector_state *old_conn_state;
5193         struct drm_connector *conn;
5194         int i;
5195
5196         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5197                 struct intel_encoder *encoder =
5198                         to_intel_encoder(old_conn_state->best_encoder);
5199
5200                 if (old_conn_state->crtc != crtc)
5201                         continue;
5202
5203                 if (encoder->post_disable)
5204                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5205         }
5206 }
5207
5208 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5209                                             struct intel_crtc_state *old_crtc_state,
5210                                             struct drm_atomic_state *old_state)
5211 {
5212         struct drm_connector_state *old_conn_state;
5213         struct drm_connector *conn;
5214         int i;
5215
5216         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5217                 struct intel_encoder *encoder =
5218                         to_intel_encoder(old_conn_state->best_encoder);
5219
5220                 if (old_conn_state->crtc != crtc)
5221                         continue;
5222
5223                 if (encoder->post_pll_disable)
5224                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5225         }
5226 }
5227
5228 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5229                                  struct drm_atomic_state *old_state)
5230 {
5231         struct drm_crtc *crtc = pipe_config->base.crtc;
5232         struct drm_device *dev = crtc->dev;
5233         struct drm_i915_private *dev_priv = to_i915(dev);
5234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5235         int pipe = intel_crtc->pipe;
5236         struct intel_atomic_state *old_intel_state =
5237                 to_intel_atomic_state(old_state);
5238
5239         if (WARN_ON(intel_crtc->active))
5240                 return;
5241
5242         /*
5243          * Sometimes spurious CPU pipe underruns happen during FDI
5244          * training, at least with VGA+HDMI cloning. Suppress them.
5245          *
5246          * On ILK we get an occasional spurious CPU pipe underruns
5247          * between eDP port A enable and vdd enable. Also PCH port
5248          * enable seems to result in the occasional CPU pipe underrun.
5249          *
5250          * Spurious PCH underruns also occur during PCH enabling.
5251          */
5252         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5253                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5254         if (intel_crtc->config->has_pch_encoder)
5255                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5256
5257         if (intel_crtc->config->has_pch_encoder)
5258                 intel_prepare_shared_dpll(intel_crtc);
5259
5260         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5261                 intel_dp_set_m_n(intel_crtc, M1_N1);
5262
5263         intel_set_pipe_timings(intel_crtc);
5264         intel_set_pipe_src_size(intel_crtc);
5265
5266         if (intel_crtc->config->has_pch_encoder) {
5267                 intel_cpu_transcoder_set_m_n(intel_crtc,
5268                                      &intel_crtc->config->fdi_m_n, NULL);
5269         }
5270
5271         ironlake_set_pipeconf(crtc);
5272
5273         intel_crtc->active = true;
5274
5275         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5276
5277         if (intel_crtc->config->has_pch_encoder) {
5278                 /* Note: FDI PLL enabling _must_ be done before we enable the
5279                  * cpu pipes, hence this is separate from all the other fdi/pch
5280                  * enabling. */
5281                 ironlake_fdi_pll_enable(intel_crtc);
5282         } else {
5283                 assert_fdi_tx_disabled(dev_priv, pipe);
5284                 assert_fdi_rx_disabled(dev_priv, pipe);
5285         }
5286
5287         ironlake_pfit_enable(intel_crtc);
5288
5289         /*
5290          * On ILK+ LUT must be loaded before the pipe is running but with
5291          * clocks enabled
5292          */
5293         intel_color_load_luts(&pipe_config->base);
5294
5295         if (dev_priv->display.initial_watermarks != NULL)
5296                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5297         intel_enable_pipe(intel_crtc);
5298
5299         if (intel_crtc->config->has_pch_encoder)
5300                 ironlake_pch_enable(pipe_config);
5301
5302         assert_vblank_disabled(crtc);
5303         drm_crtc_vblank_on(crtc);
5304
5305         intel_encoders_enable(crtc, pipe_config, old_state);
5306
5307         if (HAS_PCH_CPT(dev_priv))
5308                 cpt_verify_modeset(dev, intel_crtc->pipe);
5309
5310         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5311         if (intel_crtc->config->has_pch_encoder)
5312                 intel_wait_for_vblank(dev_priv, pipe);
5313         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5314         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5315 }
5316
5317 /* IPS only exists on ULT machines and is tied to pipe A. */
5318 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5319 {
5320         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5321 }
5322
5323 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5324                                 struct drm_atomic_state *old_state)
5325 {
5326         struct drm_crtc *crtc = pipe_config->base.crtc;
5327         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5329         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5330         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5331         struct intel_atomic_state *old_intel_state =
5332                 to_intel_atomic_state(old_state);
5333
5334         if (WARN_ON(intel_crtc->active))
5335                 return;
5336
5337         if (intel_crtc->config->has_pch_encoder)
5338                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5339                                                       false);
5340
5341         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5342
5343         if (intel_crtc->config->shared_dpll)
5344                 intel_enable_shared_dpll(intel_crtc);
5345
5346         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5347                 intel_dp_set_m_n(intel_crtc, M1_N1);
5348
5349         if (!transcoder_is_dsi(cpu_transcoder))
5350                 intel_set_pipe_timings(intel_crtc);
5351
5352         intel_set_pipe_src_size(intel_crtc);
5353
5354         if (cpu_transcoder != TRANSCODER_EDP &&
5355             !transcoder_is_dsi(cpu_transcoder)) {
5356                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5357                            intel_crtc->config->pixel_multiplier - 1);
5358         }
5359
5360         if (intel_crtc->config->has_pch_encoder) {
5361                 intel_cpu_transcoder_set_m_n(intel_crtc,
5362                                      &intel_crtc->config->fdi_m_n, NULL);
5363         }
5364
5365         if (!transcoder_is_dsi(cpu_transcoder))
5366                 haswell_set_pipeconf(crtc);
5367
5368         haswell_set_pipemisc(crtc);
5369
5370         intel_color_set_csc(&pipe_config->base);
5371
5372         intel_crtc->active = true;
5373
5374         if (intel_crtc->config->has_pch_encoder)
5375                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5376         else
5377                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5378
5379         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5380
5381         if (intel_crtc->config->has_pch_encoder)
5382                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5383
5384         if (!transcoder_is_dsi(cpu_transcoder))
5385                 intel_ddi_enable_pipe_clock(pipe_config);
5386
5387         if (INTEL_GEN(dev_priv) >= 9)
5388                 skylake_pfit_enable(intel_crtc);
5389         else
5390                 ironlake_pfit_enable(intel_crtc);
5391
5392         /*
5393          * On ILK+ LUT must be loaded before the pipe is running but with
5394          * clocks enabled
5395          */
5396         intel_color_load_luts(&pipe_config->base);
5397
5398         intel_ddi_set_pipe_settings(pipe_config);
5399         if (!transcoder_is_dsi(cpu_transcoder))
5400                 intel_ddi_enable_transcoder_func(pipe_config);
5401
5402         if (dev_priv->display.initial_watermarks != NULL)
5403                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5404
5405         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5406         if (!transcoder_is_dsi(cpu_transcoder))
5407                 intel_enable_pipe(intel_crtc);
5408
5409         if (intel_crtc->config->has_pch_encoder)
5410                 lpt_pch_enable(pipe_config);
5411
5412         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5413                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5414
5415         assert_vblank_disabled(crtc);
5416         drm_crtc_vblank_on(crtc);
5417
5418         intel_encoders_enable(crtc, pipe_config, old_state);
5419
5420         if (intel_crtc->config->has_pch_encoder) {
5421                 intel_wait_for_vblank(dev_priv, pipe);
5422                 intel_wait_for_vblank(dev_priv, pipe);
5423                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5424                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5425                                                       true);
5426         }
5427
5428         /* If we change the relative order between pipe/planes enabling, we need
5429          * to change the workaround. */
5430         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5431         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5432                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5433                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5434         }
5435 }
5436
5437 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5438 {
5439         struct drm_device *dev = crtc->base.dev;
5440         struct drm_i915_private *dev_priv = to_i915(dev);
5441         int pipe = crtc->pipe;
5442
5443         /* To avoid upsetting the power well on haswell only disable the pfit if
5444          * it's in use. The hw state code will make sure we get this right. */
5445         if (force || crtc->config->pch_pfit.enabled) {
5446                 I915_WRITE(PF_CTL(pipe), 0);
5447                 I915_WRITE(PF_WIN_POS(pipe), 0);
5448                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5449         }
5450 }
5451
5452 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5453                                   struct drm_atomic_state *old_state)
5454 {
5455         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5456         struct drm_device *dev = crtc->dev;
5457         struct drm_i915_private *dev_priv = to_i915(dev);
5458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5459         int pipe = intel_crtc->pipe;
5460
5461         /*
5462          * Sometimes spurious CPU pipe underruns happen when the
5463          * pipe is already disabled, but FDI RX/TX is still enabled.
5464          * Happens at least with VGA+HDMI cloning. Suppress them.
5465          */
5466         if (intel_crtc->config->has_pch_encoder) {
5467                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5468                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5469         }
5470
5471         intel_encoders_disable(crtc, old_crtc_state, old_state);
5472
5473         drm_crtc_vblank_off(crtc);
5474         assert_vblank_disabled(crtc);
5475
5476         intel_disable_pipe(intel_crtc);
5477
5478         ironlake_pfit_disable(intel_crtc, false);
5479
5480         if (intel_crtc->config->has_pch_encoder)
5481                 ironlake_fdi_disable(crtc);
5482
5483         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5484
5485         if (intel_crtc->config->has_pch_encoder) {
5486                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5487
5488                 if (HAS_PCH_CPT(dev_priv)) {
5489                         i915_reg_t reg;
5490                         u32 temp;
5491
5492                         /* disable TRANS_DP_CTL */
5493                         reg = TRANS_DP_CTL(pipe);
5494                         temp = I915_READ(reg);
5495                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5496                                   TRANS_DP_PORT_SEL_MASK);
5497                         temp |= TRANS_DP_PORT_SEL_NONE;
5498                         I915_WRITE(reg, temp);
5499
5500                         /* disable DPLL_SEL */
5501                         temp = I915_READ(PCH_DPLL_SEL);
5502                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5503                         I915_WRITE(PCH_DPLL_SEL, temp);
5504                 }
5505
5506                 ironlake_fdi_pll_disable(intel_crtc);
5507         }
5508
5509         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5510         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5511 }
5512
5513 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5514                                  struct drm_atomic_state *old_state)
5515 {
5516         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5517         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5519         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5520
5521         if (intel_crtc->config->has_pch_encoder)
5522                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5523                                                       false);
5524
5525         intel_encoders_disable(crtc, old_crtc_state, old_state);
5526
5527         drm_crtc_vblank_off(crtc);
5528         assert_vblank_disabled(crtc);
5529
5530         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5531         if (!transcoder_is_dsi(cpu_transcoder))
5532                 intel_disable_pipe(intel_crtc);
5533
5534         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5535                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5536
5537         if (!transcoder_is_dsi(cpu_transcoder))
5538                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5539
5540         if (INTEL_GEN(dev_priv) >= 9)
5541                 skylake_scaler_disable(intel_crtc);
5542         else
5543                 ironlake_pfit_disable(intel_crtc, false);
5544
5545         if (!transcoder_is_dsi(cpu_transcoder))
5546                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5547
5548         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5549
5550         if (old_crtc_state->has_pch_encoder)
5551                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5552                                                       true);
5553 }
5554
5555 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5556 {
5557         struct drm_device *dev = crtc->base.dev;
5558         struct drm_i915_private *dev_priv = to_i915(dev);
5559         struct intel_crtc_state *pipe_config = crtc->config;
5560
5561         if (!pipe_config->gmch_pfit.control)
5562                 return;
5563
5564         /*
5565          * The panel fitter should only be adjusted whilst the pipe is disabled,
5566          * according to register description and PRM.
5567          */
5568         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5569         assert_pipe_disabled(dev_priv, crtc->pipe);
5570
5571         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5572         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5573
5574         /* Border color in case we don't scale up to the full screen. Black by
5575          * default, change to something else for debugging. */
5576         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5577 }
5578
5579 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5580 {
5581         switch (port) {
5582         case PORT_A:
5583                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5584         case PORT_B:
5585                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5586         case PORT_C:
5587                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5588         case PORT_D:
5589                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5590         case PORT_E:
5591                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5592         default:
5593                 MISSING_CASE(port);
5594                 return POWER_DOMAIN_PORT_OTHER;
5595         }
5596 }
5597
5598 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5599                                   struct intel_crtc_state *crtc_state)
5600 {
5601         struct drm_device *dev = crtc->dev;
5602         struct drm_i915_private *dev_priv = to_i915(dev);
5603         struct drm_encoder *encoder;
5604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5605         enum pipe pipe = intel_crtc->pipe;
5606         u64 mask;
5607         enum transcoder transcoder = crtc_state->cpu_transcoder;
5608
5609         if (!crtc_state->base.active)
5610                 return 0;
5611
5612         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5613         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5614         if (crtc_state->pch_pfit.enabled ||
5615             crtc_state->pch_pfit.force_thru)
5616                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5617
5618         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5619                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5620
5621                 mask |= BIT_ULL(intel_encoder->power_domain);
5622         }
5623
5624         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5625                 mask |= BIT(POWER_DOMAIN_AUDIO);
5626
5627         if (crtc_state->shared_dpll)
5628                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5629
5630         return mask;
5631 }
5632
5633 static u64
5634 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5635                                struct intel_crtc_state *crtc_state)
5636 {
5637         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5639         enum intel_display_power_domain domain;
5640         u64 domains, new_domains, old_domains;
5641
5642         old_domains = intel_crtc->enabled_power_domains;
5643         intel_crtc->enabled_power_domains = new_domains =
5644                 get_crtc_power_domains(crtc, crtc_state);
5645
5646         domains = new_domains & ~old_domains;
5647
5648         for_each_power_domain(domain, domains)
5649                 intel_display_power_get(dev_priv, domain);
5650
5651         return old_domains & ~new_domains;
5652 }
5653
5654 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5655                                       u64 domains)
5656 {
5657         enum intel_display_power_domain domain;
5658
5659         for_each_power_domain(domain, domains)
5660                 intel_display_power_put(dev_priv, domain);
5661 }
5662
5663 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5664                                    struct drm_atomic_state *old_state)
5665 {
5666         struct intel_atomic_state *old_intel_state =
5667                 to_intel_atomic_state(old_state);
5668         struct drm_crtc *crtc = pipe_config->base.crtc;
5669         struct drm_device *dev = crtc->dev;
5670         struct drm_i915_private *dev_priv = to_i915(dev);
5671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5672         int pipe = intel_crtc->pipe;
5673
5674         if (WARN_ON(intel_crtc->active))
5675                 return;
5676
5677         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5678                 intel_dp_set_m_n(intel_crtc, M1_N1);
5679
5680         intel_set_pipe_timings(intel_crtc);
5681         intel_set_pipe_src_size(intel_crtc);
5682
5683         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5684                 struct drm_i915_private *dev_priv = to_i915(dev);
5685
5686                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5687                 I915_WRITE(CHV_CANVAS(pipe), 0);
5688         }
5689
5690         i9xx_set_pipeconf(intel_crtc);
5691
5692         intel_crtc->active = true;
5693
5694         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5695
5696         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5697
5698         if (IS_CHERRYVIEW(dev_priv)) {
5699                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5700                 chv_enable_pll(intel_crtc, intel_crtc->config);
5701         } else {
5702                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5703                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5704         }
5705
5706         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5707
5708         i9xx_pfit_enable(intel_crtc);
5709
5710         intel_color_load_luts(&pipe_config->base);
5711
5712         dev_priv->display.initial_watermarks(old_intel_state,
5713                                              pipe_config);
5714         intel_enable_pipe(intel_crtc);
5715
5716         assert_vblank_disabled(crtc);
5717         drm_crtc_vblank_on(crtc);
5718
5719         intel_encoders_enable(crtc, pipe_config, old_state);
5720 }
5721
5722 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5723 {
5724         struct drm_device *dev = crtc->base.dev;
5725         struct drm_i915_private *dev_priv = to_i915(dev);
5726
5727         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5728         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5729 }
5730
5731 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5732                              struct drm_atomic_state *old_state)
5733 {
5734         struct intel_atomic_state *old_intel_state =
5735                 to_intel_atomic_state(old_state);
5736         struct drm_crtc *crtc = pipe_config->base.crtc;
5737         struct drm_device *dev = crtc->dev;
5738         struct drm_i915_private *dev_priv = to_i915(dev);
5739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5740         enum pipe pipe = intel_crtc->pipe;
5741
5742         if (WARN_ON(intel_crtc->active))
5743                 return;
5744
5745         i9xx_set_pll_dividers(intel_crtc);
5746
5747         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5748                 intel_dp_set_m_n(intel_crtc, M1_N1);
5749
5750         intel_set_pipe_timings(intel_crtc);
5751         intel_set_pipe_src_size(intel_crtc);
5752
5753         i9xx_set_pipeconf(intel_crtc);
5754
5755         intel_crtc->active = true;
5756
5757         if (!IS_GEN2(dev_priv))
5758                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5759
5760         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5761
5762         i9xx_enable_pll(intel_crtc);
5763
5764         i9xx_pfit_enable(intel_crtc);
5765
5766         intel_color_load_luts(&pipe_config->base);
5767
5768         if (dev_priv->display.initial_watermarks != NULL)
5769                 dev_priv->display.initial_watermarks(old_intel_state,
5770                                                      intel_crtc->config);
5771         else
5772                 intel_update_watermarks(intel_crtc);
5773         intel_enable_pipe(intel_crtc);
5774
5775         assert_vblank_disabled(crtc);
5776         drm_crtc_vblank_on(crtc);
5777
5778         intel_encoders_enable(crtc, pipe_config, old_state);
5779 }
5780
5781 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5782 {
5783         struct drm_device *dev = crtc->base.dev;
5784         struct drm_i915_private *dev_priv = to_i915(dev);
5785
5786         if (!crtc->config->gmch_pfit.control)
5787                 return;
5788
5789         assert_pipe_disabled(dev_priv, crtc->pipe);
5790
5791         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5792                          I915_READ(PFIT_CONTROL));
5793         I915_WRITE(PFIT_CONTROL, 0);
5794 }
5795
5796 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5797                               struct drm_atomic_state *old_state)
5798 {
5799         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5800         struct drm_device *dev = crtc->dev;
5801         struct drm_i915_private *dev_priv = to_i915(dev);
5802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5803         int pipe = intel_crtc->pipe;
5804
5805         /*
5806          * On gen2 planes are double buffered but the pipe isn't, so we must
5807          * wait for planes to fully turn off before disabling the pipe.
5808          */
5809         if (IS_GEN2(dev_priv))
5810                 intel_wait_for_vblank(dev_priv, pipe);
5811
5812         intel_encoders_disable(crtc, old_crtc_state, old_state);
5813
5814         drm_crtc_vblank_off(crtc);
5815         assert_vblank_disabled(crtc);
5816
5817         intel_disable_pipe(intel_crtc);
5818
5819         i9xx_pfit_disable(intel_crtc);
5820
5821         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5822
5823         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5824                 if (IS_CHERRYVIEW(dev_priv))
5825                         chv_disable_pll(dev_priv, pipe);
5826                 else if (IS_VALLEYVIEW(dev_priv))
5827                         vlv_disable_pll(dev_priv, pipe);
5828                 else
5829                         i9xx_disable_pll(intel_crtc);
5830         }
5831
5832         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5833
5834         if (!IS_GEN2(dev_priv))
5835                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5836
5837         if (!dev_priv->display.initial_watermarks)
5838                 intel_update_watermarks(intel_crtc);
5839 }
5840
5841 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5842 {
5843         struct intel_encoder *encoder;
5844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5845         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5846         enum intel_display_power_domain domain;
5847         u64 domains;
5848         struct drm_atomic_state *state;
5849         struct intel_crtc_state *crtc_state;
5850         int ret;
5851
5852         if (!intel_crtc->active)
5853                 return;
5854
5855         if (crtc->primary->state->visible) {
5856                 WARN_ON(intel_crtc->flip_work);
5857
5858                 intel_pre_disable_primary_noatomic(crtc);
5859
5860                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5861                 crtc->primary->state->visible = false;
5862         }
5863
5864         state = drm_atomic_state_alloc(crtc->dev);
5865         if (!state) {
5866                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5867                               crtc->base.id, crtc->name);
5868                 return;
5869         }
5870
5871         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5872
5873         /* Everything's already locked, -EDEADLK can't happen. */
5874         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5875         ret = drm_atomic_add_affected_connectors(state, crtc);
5876
5877         WARN_ON(IS_ERR(crtc_state) || ret);
5878
5879         dev_priv->display.crtc_disable(crtc_state, state);
5880
5881         drm_atomic_state_put(state);
5882
5883         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5884                       crtc->base.id, crtc->name);
5885
5886         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5887         crtc->state->active = false;
5888         intel_crtc->active = false;
5889         crtc->enabled = false;
5890         crtc->state->connector_mask = 0;
5891         crtc->state->encoder_mask = 0;
5892
5893         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5894                 encoder->base.crtc = NULL;
5895
5896         intel_fbc_disable(intel_crtc);
5897         intel_update_watermarks(intel_crtc);
5898         intel_disable_shared_dpll(intel_crtc);
5899
5900         domains = intel_crtc->enabled_power_domains;
5901         for_each_power_domain(domain, domains)
5902                 intel_display_power_put(dev_priv, domain);
5903         intel_crtc->enabled_power_domains = 0;
5904
5905         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5906         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5907 }
5908
5909 /*
5910  * turn all crtc's off, but do not adjust state
5911  * This has to be paired with a call to intel_modeset_setup_hw_state.
5912  */
5913 int intel_display_suspend(struct drm_device *dev)
5914 {
5915         struct drm_i915_private *dev_priv = to_i915(dev);
5916         struct drm_atomic_state *state;
5917         int ret;
5918
5919         state = drm_atomic_helper_suspend(dev);
5920         ret = PTR_ERR_OR_ZERO(state);
5921         if (ret)
5922                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5923         else
5924                 dev_priv->modeset_restore_state = state;
5925         return ret;
5926 }
5927
5928 void intel_encoder_destroy(struct drm_encoder *encoder)
5929 {
5930         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5931
5932         drm_encoder_cleanup(encoder);
5933         kfree(intel_encoder);
5934 }
5935
5936 /* Cross check the actual hw state with our own modeset state tracking (and it's
5937  * internal consistency). */
5938 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5939                                          struct drm_connector_state *conn_state)
5940 {
5941         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5942
5943         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5944                       connector->base.base.id,
5945                       connector->base.name);
5946
5947         if (connector->get_hw_state(connector)) {
5948                 struct intel_encoder *encoder = connector->encoder;
5949
5950                 I915_STATE_WARN(!crtc_state,
5951                          "connector enabled without attached crtc\n");
5952
5953                 if (!crtc_state)
5954                         return;
5955
5956                 I915_STATE_WARN(!crtc_state->active,
5957                       "connector is active, but attached crtc isn't\n");
5958
5959                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5960                         return;
5961
5962                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5963                         "atomic encoder doesn't match attached encoder\n");
5964
5965                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5966                         "attached encoder crtc differs from connector crtc\n");
5967         } else {
5968                 I915_STATE_WARN(crtc_state && crtc_state->active,
5969                         "attached crtc is active, but connector isn't\n");
5970                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5971                         "best encoder set without crtc!\n");
5972         }
5973 }
5974
5975 int intel_connector_init(struct intel_connector *connector)
5976 {
5977         drm_atomic_helper_connector_reset(&connector->base);
5978
5979         if (!connector->base.state)
5980                 return -ENOMEM;
5981
5982         return 0;
5983 }
5984
5985 struct intel_connector *intel_connector_alloc(void)
5986 {
5987         struct intel_connector *connector;
5988
5989         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5990         if (!connector)
5991                 return NULL;
5992
5993         if (intel_connector_init(connector) < 0) {
5994                 kfree(connector);
5995                 return NULL;
5996         }
5997
5998         return connector;
5999 }
6000
6001 /* Simple connector->get_hw_state implementation for encoders that support only
6002  * one connector and no cloning and hence the encoder state determines the state
6003  * of the connector. */
6004 bool intel_connector_get_hw_state(struct intel_connector *connector)
6005 {
6006         enum pipe pipe = 0;
6007         struct intel_encoder *encoder = connector->encoder;
6008
6009         return encoder->get_hw_state(encoder, &pipe);
6010 }
6011
6012 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6013 {
6014         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6015                 return crtc_state->fdi_lanes;
6016
6017         return 0;
6018 }
6019
6020 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6021                                      struct intel_crtc_state *pipe_config)
6022 {
6023         struct drm_i915_private *dev_priv = to_i915(dev);
6024         struct drm_atomic_state *state = pipe_config->base.state;
6025         struct intel_crtc *other_crtc;
6026         struct intel_crtc_state *other_crtc_state;
6027
6028         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6029                       pipe_name(pipe), pipe_config->fdi_lanes);
6030         if (pipe_config->fdi_lanes > 4) {
6031                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6032                               pipe_name(pipe), pipe_config->fdi_lanes);
6033                 return -EINVAL;
6034         }
6035
6036         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6037                 if (pipe_config->fdi_lanes > 2) {
6038                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6039                                       pipe_config->fdi_lanes);
6040                         return -EINVAL;
6041                 } else {
6042                         return 0;
6043                 }
6044         }
6045
6046         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6047                 return 0;
6048
6049         /* Ivybridge 3 pipe is really complicated */
6050         switch (pipe) {
6051         case PIPE_A:
6052                 return 0;
6053         case PIPE_B:
6054                 if (pipe_config->fdi_lanes <= 2)
6055                         return 0;
6056
6057                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6058                 other_crtc_state =
6059                         intel_atomic_get_crtc_state(state, other_crtc);
6060                 if (IS_ERR(other_crtc_state))
6061                         return PTR_ERR(other_crtc_state);
6062
6063                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6064                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6065                                       pipe_name(pipe), pipe_config->fdi_lanes);
6066                         return -EINVAL;
6067                 }
6068                 return 0;
6069         case PIPE_C:
6070                 if (pipe_config->fdi_lanes > 2) {
6071                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6072                                       pipe_name(pipe), pipe_config->fdi_lanes);
6073                         return -EINVAL;
6074                 }
6075
6076                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6077                 other_crtc_state =
6078                         intel_atomic_get_crtc_state(state, other_crtc);
6079                 if (IS_ERR(other_crtc_state))
6080                         return PTR_ERR(other_crtc_state);
6081
6082                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6083                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6084                         return -EINVAL;
6085                 }
6086                 return 0;
6087         default:
6088                 BUG();
6089         }
6090 }
6091
6092 #define RETRY 1
6093 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6094                                        struct intel_crtc_state *pipe_config)
6095 {
6096         struct drm_device *dev = intel_crtc->base.dev;
6097         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6098         int lane, link_bw, fdi_dotclock, ret;
6099         bool needs_recompute = false;
6100
6101 retry:
6102         /* FDI is a binary signal running at ~2.7GHz, encoding
6103          * each output octet as 10 bits. The actual frequency
6104          * is stored as a divider into a 100MHz clock, and the
6105          * mode pixel clock is stored in units of 1KHz.
6106          * Hence the bw of each lane in terms of the mode signal
6107          * is:
6108          */
6109         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6110
6111         fdi_dotclock = adjusted_mode->crtc_clock;
6112
6113         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6114                                            pipe_config->pipe_bpp);
6115
6116         pipe_config->fdi_lanes = lane;
6117
6118         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6119                                link_bw, &pipe_config->fdi_m_n);
6120
6121         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6122         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6123                 pipe_config->pipe_bpp -= 2*3;
6124                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6125                               pipe_config->pipe_bpp);
6126                 needs_recompute = true;
6127                 pipe_config->bw_constrained = true;
6128
6129                 goto retry;
6130         }
6131
6132         if (needs_recompute)
6133                 return RETRY;
6134
6135         return ret;
6136 }
6137
6138 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6139                                      struct intel_crtc_state *pipe_config)
6140 {
6141         if (pipe_config->pipe_bpp > 24)
6142                 return false;
6143
6144         /* HSW can handle pixel rate up to cdclk? */
6145         if (IS_HASWELL(dev_priv))
6146                 return true;
6147
6148         /*
6149          * We compare against max which means we must take
6150          * the increased cdclk requirement into account when
6151          * calculating the new cdclk.
6152          *
6153          * Should measure whether using a lower cdclk w/o IPS
6154          */
6155         return pipe_config->pixel_rate <=
6156                 dev_priv->max_cdclk_freq * 95 / 100;
6157 }
6158
6159 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6160                                    struct intel_crtc_state *pipe_config)
6161 {
6162         struct drm_device *dev = crtc->base.dev;
6163         struct drm_i915_private *dev_priv = to_i915(dev);
6164
6165         pipe_config->ips_enabled = i915.enable_ips &&
6166                 hsw_crtc_supports_ips(crtc) &&
6167                 pipe_config_supports_ips(dev_priv, pipe_config);
6168 }
6169
6170 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6171 {
6172         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6173
6174         /* GDG double wide on either pipe, otherwise pipe A only */
6175         return INTEL_INFO(dev_priv)->gen < 4 &&
6176                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6177 }
6178
6179 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6180 {
6181         uint32_t pixel_rate;
6182
6183         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6184
6185         /*
6186          * We only use IF-ID interlacing. If we ever use
6187          * PF-ID we'll need to adjust the pixel_rate here.
6188          */
6189
6190         if (pipe_config->pch_pfit.enabled) {
6191                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6192                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6193
6194                 pipe_w = pipe_config->pipe_src_w;
6195                 pipe_h = pipe_config->pipe_src_h;
6196
6197                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6198                 pfit_h = pfit_size & 0xFFFF;
6199                 if (pipe_w < pfit_w)
6200                         pipe_w = pfit_w;
6201                 if (pipe_h < pfit_h)
6202                         pipe_h = pfit_h;
6203
6204                 if (WARN_ON(!pfit_w || !pfit_h))
6205                         return pixel_rate;
6206
6207                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6208                                      pfit_w * pfit_h);
6209         }
6210
6211         return pixel_rate;
6212 }
6213
6214 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6215 {
6216         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6217
6218         if (HAS_GMCH_DISPLAY(dev_priv))
6219                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6220                 crtc_state->pixel_rate =
6221                         crtc_state->base.adjusted_mode.crtc_clock;
6222         else
6223                 crtc_state->pixel_rate =
6224                         ilk_pipe_pixel_rate(crtc_state);
6225 }
6226
6227 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6228                                      struct intel_crtc_state *pipe_config)
6229 {
6230         struct drm_device *dev = crtc->base.dev;
6231         struct drm_i915_private *dev_priv = to_i915(dev);
6232         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6233         int clock_limit = dev_priv->max_dotclk_freq;
6234
6235         if (INTEL_GEN(dev_priv) < 4) {
6236                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6237
6238                 /*
6239                  * Enable double wide mode when the dot clock
6240                  * is > 90% of the (display) core speed.
6241                  */
6242                 if (intel_crtc_supports_double_wide(crtc) &&
6243                     adjusted_mode->crtc_clock > clock_limit) {
6244                         clock_limit = dev_priv->max_dotclk_freq;
6245                         pipe_config->double_wide = true;
6246                 }
6247         }
6248
6249         if (adjusted_mode->crtc_clock > clock_limit) {
6250                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6251                               adjusted_mode->crtc_clock, clock_limit,
6252                               yesno(pipe_config->double_wide));
6253                 return -EINVAL;
6254         }
6255
6256         /*
6257          * Pipe horizontal size must be even in:
6258          * - DVO ganged mode
6259          * - LVDS dual channel mode
6260          * - Double wide pipe
6261          */
6262         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6263              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6264                 pipe_config->pipe_src_w &= ~1;
6265
6266         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6267          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6268          */
6269         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6270                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6271                 return -EINVAL;
6272
6273         intel_crtc_compute_pixel_rate(pipe_config);
6274
6275         if (HAS_IPS(dev_priv))
6276                 hsw_compute_ips_config(crtc, pipe_config);
6277
6278         if (pipe_config->has_pch_encoder)
6279                 return ironlake_fdi_compute_config(crtc, pipe_config);
6280
6281         return 0;
6282 }
6283
6284 static void
6285 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6286 {
6287         while (*num > DATA_LINK_M_N_MASK ||
6288                *den > DATA_LINK_M_N_MASK) {
6289                 *num >>= 1;
6290                 *den >>= 1;
6291         }
6292 }
6293
6294 static void compute_m_n(unsigned int m, unsigned int n,
6295                         uint32_t *ret_m, uint32_t *ret_n)
6296 {
6297         /*
6298          * Reduce M/N as much as possible without loss in precision. Several DP
6299          * dongles in particular seem to be fussy about too large *link* M/N
6300          * values. The passed in values are more likely to have the least
6301          * significant bits zero than M after rounding below, so do this first.
6302          */
6303         while ((m & 1) == 0 && (n & 1) == 0) {
6304                 m >>= 1;
6305                 n >>= 1;
6306         }
6307
6308         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6309         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6310         intel_reduce_m_n_ratio(ret_m, ret_n);
6311 }
6312
6313 void
6314 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6315                        int pixel_clock, int link_clock,
6316                        struct intel_link_m_n *m_n)
6317 {
6318         m_n->tu = 64;
6319
6320         compute_m_n(bits_per_pixel * pixel_clock,
6321                     link_clock * nlanes * 8,
6322                     &m_n->gmch_m, &m_n->gmch_n);
6323
6324         compute_m_n(pixel_clock, link_clock,
6325                     &m_n->link_m, &m_n->link_n);
6326 }
6327
6328 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6329 {
6330         if (i915.panel_use_ssc >= 0)
6331                 return i915.panel_use_ssc != 0;
6332         return dev_priv->vbt.lvds_use_ssc
6333                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6334 }
6335
6336 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6337 {
6338         return (1 << dpll->n) << 16 | dpll->m2;
6339 }
6340
6341 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6342 {
6343         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6344 }
6345
6346 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6347                                      struct intel_crtc_state *crtc_state,
6348                                      struct dpll *reduced_clock)
6349 {
6350         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6351         u32 fp, fp2 = 0;
6352
6353         if (IS_PINEVIEW(dev_priv)) {
6354                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6355                 if (reduced_clock)
6356                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6357         } else {
6358                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6359                 if (reduced_clock)
6360                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6361         }
6362
6363         crtc_state->dpll_hw_state.fp0 = fp;
6364
6365         crtc->lowfreq_avail = false;
6366         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6367             reduced_clock) {
6368                 crtc_state->dpll_hw_state.fp1 = fp2;
6369                 crtc->lowfreq_avail = true;
6370         } else {
6371                 crtc_state->dpll_hw_state.fp1 = fp;
6372         }
6373 }
6374
6375 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6376                 pipe)
6377 {
6378         u32 reg_val;
6379
6380         /*
6381          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6382          * and set it to a reasonable value instead.
6383          */
6384         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6385         reg_val &= 0xffffff00;
6386         reg_val |= 0x00000030;
6387         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6388
6389         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6390         reg_val &= 0x00ffffff;
6391         reg_val |= 0x8c000000;
6392         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6393
6394         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6395         reg_val &= 0xffffff00;
6396         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6397
6398         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6399         reg_val &= 0x00ffffff;
6400         reg_val |= 0xb0000000;
6401         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6402 }
6403
6404 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6405                                          struct intel_link_m_n *m_n)
6406 {
6407         struct drm_device *dev = crtc->base.dev;
6408         struct drm_i915_private *dev_priv = to_i915(dev);
6409         int pipe = crtc->pipe;
6410
6411         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6412         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6413         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6414         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6415 }
6416
6417 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6418                                          struct intel_link_m_n *m_n,
6419                                          struct intel_link_m_n *m2_n2)
6420 {
6421         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6422         int pipe = crtc->pipe;
6423         enum transcoder transcoder = crtc->config->cpu_transcoder;
6424
6425         if (INTEL_GEN(dev_priv) >= 5) {
6426                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6427                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6428                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6429                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6430                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6431                  * for gen < 8) and if DRRS is supported (to make sure the
6432                  * registers are not unnecessarily accessed).
6433                  */
6434                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6435                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6436                         I915_WRITE(PIPE_DATA_M2(transcoder),
6437                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6438                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6439                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6440                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6441                 }
6442         } else {
6443                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6444                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6445                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6446                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6447         }
6448 }
6449
6450 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6451 {
6452         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6453
6454         if (m_n == M1_N1) {
6455                 dp_m_n = &crtc->config->dp_m_n;
6456                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6457         } else if (m_n == M2_N2) {
6458
6459                 /*
6460                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6461                  * needs to be programmed into M1_N1.
6462                  */
6463                 dp_m_n = &crtc->config->dp_m2_n2;
6464         } else {
6465                 DRM_ERROR("Unsupported divider value\n");
6466                 return;
6467         }
6468
6469         if (crtc->config->has_pch_encoder)
6470                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6471         else
6472                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6473 }
6474
6475 static void vlv_compute_dpll(struct intel_crtc *crtc,
6476                              struct intel_crtc_state *pipe_config)
6477 {
6478         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6479                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6480         if (crtc->pipe != PIPE_A)
6481                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6482
6483         /* DPLL not used with DSI, but still need the rest set up */
6484         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6485                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6486                         DPLL_EXT_BUFFER_ENABLE_VLV;
6487
6488         pipe_config->dpll_hw_state.dpll_md =
6489                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6490 }
6491
6492 static void chv_compute_dpll(struct intel_crtc *crtc,
6493                              struct intel_crtc_state *pipe_config)
6494 {
6495         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6496                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6497         if (crtc->pipe != PIPE_A)
6498                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6499
6500         /* DPLL not used with DSI, but still need the rest set up */
6501         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6502                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6503
6504         pipe_config->dpll_hw_state.dpll_md =
6505                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6506 }
6507
6508 static void vlv_prepare_pll(struct intel_crtc *crtc,
6509                             const struct intel_crtc_state *pipe_config)
6510 {
6511         struct drm_device *dev = crtc->base.dev;
6512         struct drm_i915_private *dev_priv = to_i915(dev);
6513         enum pipe pipe = crtc->pipe;
6514         u32 mdiv;
6515         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6516         u32 coreclk, reg_val;
6517
6518         /* Enable Refclk */
6519         I915_WRITE(DPLL(pipe),
6520                    pipe_config->dpll_hw_state.dpll &
6521                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6522
6523         /* No need to actually set up the DPLL with DSI */
6524         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6525                 return;
6526
6527         mutex_lock(&dev_priv->sb_lock);
6528
6529         bestn = pipe_config->dpll.n;
6530         bestm1 = pipe_config->dpll.m1;
6531         bestm2 = pipe_config->dpll.m2;
6532         bestp1 = pipe_config->dpll.p1;
6533         bestp2 = pipe_config->dpll.p2;
6534
6535         /* See eDP HDMI DPIO driver vbios notes doc */
6536
6537         /* PLL B needs special handling */
6538         if (pipe == PIPE_B)
6539                 vlv_pllb_recal_opamp(dev_priv, pipe);
6540
6541         /* Set up Tx target for periodic Rcomp update */
6542         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6543
6544         /* Disable target IRef on PLL */
6545         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6546         reg_val &= 0x00ffffff;
6547         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6548
6549         /* Disable fast lock */
6550         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6551
6552         /* Set idtafcrecal before PLL is enabled */
6553         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6554         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6555         mdiv |= ((bestn << DPIO_N_SHIFT));
6556         mdiv |= (1 << DPIO_K_SHIFT);
6557
6558         /*
6559          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6560          * but we don't support that).
6561          * Note: don't use the DAC post divider as it seems unstable.
6562          */
6563         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6564         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6565
6566         mdiv |= DPIO_ENABLE_CALIBRATION;
6567         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6568
6569         /* Set HBR and RBR LPF coefficients */
6570         if (pipe_config->port_clock == 162000 ||
6571             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6572             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6573                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6574                                  0x009f0003);
6575         else
6576                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6577                                  0x00d0000f);
6578
6579         if (intel_crtc_has_dp_encoder(pipe_config)) {
6580                 /* Use SSC source */
6581                 if (pipe == PIPE_A)
6582                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6583                                          0x0df40000);
6584                 else
6585                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6586                                          0x0df70000);
6587         } else { /* HDMI or VGA */
6588                 /* Use bend source */
6589                 if (pipe == PIPE_A)
6590                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6591                                          0x0df70000);
6592                 else
6593                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6594                                          0x0df40000);
6595         }
6596
6597         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6598         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6599         if (intel_crtc_has_dp_encoder(crtc->config))
6600                 coreclk |= 0x01000000;
6601         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6602
6603         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6604         mutex_unlock(&dev_priv->sb_lock);
6605 }
6606
6607 static void chv_prepare_pll(struct intel_crtc *crtc,
6608                             const struct intel_crtc_state *pipe_config)
6609 {
6610         struct drm_device *dev = crtc->base.dev;
6611         struct drm_i915_private *dev_priv = to_i915(dev);
6612         enum pipe pipe = crtc->pipe;
6613         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6614         u32 loopfilter, tribuf_calcntr;
6615         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6616         u32 dpio_val;
6617         int vco;
6618
6619         /* Enable Refclk and SSC */
6620         I915_WRITE(DPLL(pipe),
6621                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6622
6623         /* No need to actually set up the DPLL with DSI */
6624         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6625                 return;
6626
6627         bestn = pipe_config->dpll.n;
6628         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6629         bestm1 = pipe_config->dpll.m1;
6630         bestm2 = pipe_config->dpll.m2 >> 22;
6631         bestp1 = pipe_config->dpll.p1;
6632         bestp2 = pipe_config->dpll.p2;
6633         vco = pipe_config->dpll.vco;
6634         dpio_val = 0;
6635         loopfilter = 0;
6636
6637         mutex_lock(&dev_priv->sb_lock);
6638
6639         /* p1 and p2 divider */
6640         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6641                         5 << DPIO_CHV_S1_DIV_SHIFT |
6642                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6643                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6644                         1 << DPIO_CHV_K_DIV_SHIFT);
6645
6646         /* Feedback post-divider - m2 */
6647         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6648
6649         /* Feedback refclk divider - n and m1 */
6650         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6651                         DPIO_CHV_M1_DIV_BY_2 |
6652                         1 << DPIO_CHV_N_DIV_SHIFT);
6653
6654         /* M2 fraction division */
6655         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6656
6657         /* M2 fraction division enable */
6658         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6659         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6660         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6661         if (bestm2_frac)
6662                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6663         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6664
6665         /* Program digital lock detect threshold */
6666         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6667         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6668                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6669         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6670         if (!bestm2_frac)
6671                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6672         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6673
6674         /* Loop filter */
6675         if (vco == 5400000) {
6676                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6677                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6678                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6679                 tribuf_calcntr = 0x9;
6680         } else if (vco <= 6200000) {
6681                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6682                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6683                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6684                 tribuf_calcntr = 0x9;
6685         } else if (vco <= 6480000) {
6686                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6687                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6688                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6689                 tribuf_calcntr = 0x8;
6690         } else {
6691                 /* Not supported. Apply the same limits as in the max case */
6692                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6693                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6694                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6695                 tribuf_calcntr = 0;
6696         }
6697         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6698
6699         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6700         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6701         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6702         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6703
6704         /* AFC Recal */
6705         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6706                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6707                         DPIO_AFC_RECAL);
6708
6709         mutex_unlock(&dev_priv->sb_lock);
6710 }
6711
6712 /**
6713  * vlv_force_pll_on - forcibly enable just the PLL
6714  * @dev_priv: i915 private structure
6715  * @pipe: pipe PLL to enable
6716  * @dpll: PLL configuration
6717  *
6718  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6719  * in cases where we need the PLL enabled even when @pipe is not going to
6720  * be enabled.
6721  */
6722 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6723                      const struct dpll *dpll)
6724 {
6725         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6726         struct intel_crtc_state *pipe_config;
6727
6728         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6729         if (!pipe_config)
6730                 return -ENOMEM;
6731
6732         pipe_config->base.crtc = &crtc->base;
6733         pipe_config->pixel_multiplier = 1;
6734         pipe_config->dpll = *dpll;
6735
6736         if (IS_CHERRYVIEW(dev_priv)) {
6737                 chv_compute_dpll(crtc, pipe_config);
6738                 chv_prepare_pll(crtc, pipe_config);
6739                 chv_enable_pll(crtc, pipe_config);
6740         } else {
6741                 vlv_compute_dpll(crtc, pipe_config);
6742                 vlv_prepare_pll(crtc, pipe_config);
6743                 vlv_enable_pll(crtc, pipe_config);
6744         }
6745
6746         kfree(pipe_config);
6747
6748         return 0;
6749 }
6750
6751 /**
6752  * vlv_force_pll_off - forcibly disable just the PLL
6753  * @dev_priv: i915 private structure
6754  * @pipe: pipe PLL to disable
6755  *
6756  * Disable the PLL for @pipe. To be used in cases where we need
6757  * the PLL enabled even when @pipe is not going to be enabled.
6758  */
6759 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6760 {
6761         if (IS_CHERRYVIEW(dev_priv))
6762                 chv_disable_pll(dev_priv, pipe);
6763         else
6764                 vlv_disable_pll(dev_priv, pipe);
6765 }
6766
6767 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6768                               struct intel_crtc_state *crtc_state,
6769                               struct dpll *reduced_clock)
6770 {
6771         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6772         u32 dpll;
6773         struct dpll *clock = &crtc_state->dpll;
6774
6775         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6776
6777         dpll = DPLL_VGA_MODE_DIS;
6778
6779         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6780                 dpll |= DPLLB_MODE_LVDS;
6781         else
6782                 dpll |= DPLLB_MODE_DAC_SERIAL;
6783
6784         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6785             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6786                 dpll |= (crtc_state->pixel_multiplier - 1)
6787                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6788         }
6789
6790         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6791             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6792                 dpll |= DPLL_SDVO_HIGH_SPEED;
6793
6794         if (intel_crtc_has_dp_encoder(crtc_state))
6795                 dpll |= DPLL_SDVO_HIGH_SPEED;
6796
6797         /* compute bitmask from p1 value */
6798         if (IS_PINEVIEW(dev_priv))
6799                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6800         else {
6801                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6802                 if (IS_G4X(dev_priv) && reduced_clock)
6803                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6804         }
6805         switch (clock->p2) {
6806         case 5:
6807                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6808                 break;
6809         case 7:
6810                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6811                 break;
6812         case 10:
6813                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6814                 break;
6815         case 14:
6816                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6817                 break;
6818         }
6819         if (INTEL_GEN(dev_priv) >= 4)
6820                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6821
6822         if (crtc_state->sdvo_tv_clock)
6823                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6824         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6825                  intel_panel_use_ssc(dev_priv))
6826                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6827         else
6828                 dpll |= PLL_REF_INPUT_DREFCLK;
6829
6830         dpll |= DPLL_VCO_ENABLE;
6831         crtc_state->dpll_hw_state.dpll = dpll;
6832
6833         if (INTEL_GEN(dev_priv) >= 4) {
6834                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6835                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6836                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6837         }
6838 }
6839
6840 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6841                               struct intel_crtc_state *crtc_state,
6842                               struct dpll *reduced_clock)
6843 {
6844         struct drm_device *dev = crtc->base.dev;
6845         struct drm_i915_private *dev_priv = to_i915(dev);
6846         u32 dpll;
6847         struct dpll *clock = &crtc_state->dpll;
6848
6849         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6850
6851         dpll = DPLL_VGA_MODE_DIS;
6852
6853         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6854                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6855         } else {
6856                 if (clock->p1 == 2)
6857                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6858                 else
6859                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6860                 if (clock->p2 == 4)
6861                         dpll |= PLL_P2_DIVIDE_BY_4;
6862         }
6863
6864         if (!IS_I830(dev_priv) &&
6865             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6866                 dpll |= DPLL_DVO_2X_MODE;
6867
6868         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6869             intel_panel_use_ssc(dev_priv))
6870                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6871         else
6872                 dpll |= PLL_REF_INPUT_DREFCLK;
6873
6874         dpll |= DPLL_VCO_ENABLE;
6875         crtc_state->dpll_hw_state.dpll = dpll;
6876 }
6877
6878 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6879 {
6880         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6881         enum pipe pipe = intel_crtc->pipe;
6882         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6883         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6884         uint32_t crtc_vtotal, crtc_vblank_end;
6885         int vsyncshift = 0;
6886
6887         /* We need to be careful not to changed the adjusted mode, for otherwise
6888          * the hw state checker will get angry at the mismatch. */
6889         crtc_vtotal = adjusted_mode->crtc_vtotal;
6890         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6891
6892         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6893                 /* the chip adds 2 halflines automatically */
6894                 crtc_vtotal -= 1;
6895                 crtc_vblank_end -= 1;
6896
6897                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6898                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6899                 else
6900                         vsyncshift = adjusted_mode->crtc_hsync_start -
6901                                 adjusted_mode->crtc_htotal / 2;
6902                 if (vsyncshift < 0)
6903                         vsyncshift += adjusted_mode->crtc_htotal;
6904         }
6905
6906         if (INTEL_GEN(dev_priv) > 3)
6907                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6908
6909         I915_WRITE(HTOTAL(cpu_transcoder),
6910                    (adjusted_mode->crtc_hdisplay - 1) |
6911                    ((adjusted_mode->crtc_htotal - 1) << 16));
6912         I915_WRITE(HBLANK(cpu_transcoder),
6913                    (adjusted_mode->crtc_hblank_start - 1) |
6914                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6915         I915_WRITE(HSYNC(cpu_transcoder),
6916                    (adjusted_mode->crtc_hsync_start - 1) |
6917                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6918
6919         I915_WRITE(VTOTAL(cpu_transcoder),
6920                    (adjusted_mode->crtc_vdisplay - 1) |
6921                    ((crtc_vtotal - 1) << 16));
6922         I915_WRITE(VBLANK(cpu_transcoder),
6923                    (adjusted_mode->crtc_vblank_start - 1) |
6924                    ((crtc_vblank_end - 1) << 16));
6925         I915_WRITE(VSYNC(cpu_transcoder),
6926                    (adjusted_mode->crtc_vsync_start - 1) |
6927                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6928
6929         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6930          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6931          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6932          * bits. */
6933         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6934             (pipe == PIPE_B || pipe == PIPE_C))
6935                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6936
6937 }
6938
6939 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6940 {
6941         struct drm_device *dev = intel_crtc->base.dev;
6942         struct drm_i915_private *dev_priv = to_i915(dev);
6943         enum pipe pipe = intel_crtc->pipe;
6944
6945         /* pipesrc controls the size that is scaled from, which should
6946          * always be the user's requested size.
6947          */
6948         I915_WRITE(PIPESRC(pipe),
6949                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6950                    (intel_crtc->config->pipe_src_h - 1));
6951 }
6952
6953 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6954                                    struct intel_crtc_state *pipe_config)
6955 {
6956         struct drm_device *dev = crtc->base.dev;
6957         struct drm_i915_private *dev_priv = to_i915(dev);
6958         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6959         uint32_t tmp;
6960
6961         tmp = I915_READ(HTOTAL(cpu_transcoder));
6962         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6963         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6964         tmp = I915_READ(HBLANK(cpu_transcoder));
6965         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6966         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6967         tmp = I915_READ(HSYNC(cpu_transcoder));
6968         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6969         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6970
6971         tmp = I915_READ(VTOTAL(cpu_transcoder));
6972         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6973         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6974         tmp = I915_READ(VBLANK(cpu_transcoder));
6975         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6976         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6977         tmp = I915_READ(VSYNC(cpu_transcoder));
6978         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6979         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6980
6981         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6982                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6983                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6984                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6985         }
6986 }
6987
6988 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6989                                     struct intel_crtc_state *pipe_config)
6990 {
6991         struct drm_device *dev = crtc->base.dev;
6992         struct drm_i915_private *dev_priv = to_i915(dev);
6993         u32 tmp;
6994
6995         tmp = I915_READ(PIPESRC(crtc->pipe));
6996         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6997         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6998
6999         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7000         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7001 }
7002
7003 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7004                                  struct intel_crtc_state *pipe_config)
7005 {
7006         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7007         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7008         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7009         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7010
7011         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7012         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7013         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7014         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7015
7016         mode->flags = pipe_config->base.adjusted_mode.flags;
7017         mode->type = DRM_MODE_TYPE_DRIVER;
7018
7019         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7020
7021         mode->hsync = drm_mode_hsync(mode);
7022         mode->vrefresh = drm_mode_vrefresh(mode);
7023         drm_mode_set_name(mode);
7024 }
7025
7026 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7027 {
7028         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7029         uint32_t pipeconf;
7030
7031         pipeconf = 0;
7032
7033         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7034             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7035                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7036
7037         if (intel_crtc->config->double_wide)
7038                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7039
7040         /* only g4x and later have fancy bpc/dither controls */
7041         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7042             IS_CHERRYVIEW(dev_priv)) {
7043                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7044                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7045                         pipeconf |= PIPECONF_DITHER_EN |
7046                                     PIPECONF_DITHER_TYPE_SP;
7047
7048                 switch (intel_crtc->config->pipe_bpp) {
7049                 case 18:
7050                         pipeconf |= PIPECONF_6BPC;
7051                         break;
7052                 case 24:
7053                         pipeconf |= PIPECONF_8BPC;
7054                         break;
7055                 case 30:
7056                         pipeconf |= PIPECONF_10BPC;
7057                         break;
7058                 default:
7059                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7060                         BUG();
7061                 }
7062         }
7063
7064         if (HAS_PIPE_CXSR(dev_priv)) {
7065                 if (intel_crtc->lowfreq_avail) {
7066                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7067                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7068                 } else {
7069                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7070                 }
7071         }
7072
7073         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7074                 if (INTEL_GEN(dev_priv) < 4 ||
7075                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7076                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7077                 else
7078                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7079         } else
7080                 pipeconf |= PIPECONF_PROGRESSIVE;
7081
7082         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7083              intel_crtc->config->limited_color_range)
7084                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7085
7086         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7087         POSTING_READ(PIPECONF(intel_crtc->pipe));
7088 }
7089
7090 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7091                                    struct intel_crtc_state *crtc_state)
7092 {
7093         struct drm_device *dev = crtc->base.dev;
7094         struct drm_i915_private *dev_priv = to_i915(dev);
7095         const struct intel_limit *limit;
7096         int refclk = 48000;
7097
7098         memset(&crtc_state->dpll_hw_state, 0,
7099                sizeof(crtc_state->dpll_hw_state));
7100
7101         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7102                 if (intel_panel_use_ssc(dev_priv)) {
7103                         refclk = dev_priv->vbt.lvds_ssc_freq;
7104                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7105                 }
7106
7107                 limit = &intel_limits_i8xx_lvds;
7108         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7109                 limit = &intel_limits_i8xx_dvo;
7110         } else {
7111                 limit = &intel_limits_i8xx_dac;
7112         }
7113
7114         if (!crtc_state->clock_set &&
7115             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7116                                  refclk, NULL, &crtc_state->dpll)) {
7117                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7118                 return -EINVAL;
7119         }
7120
7121         i8xx_compute_dpll(crtc, crtc_state, NULL);
7122
7123         return 0;
7124 }
7125
7126 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7127                                   struct intel_crtc_state *crtc_state)
7128 {
7129         struct drm_device *dev = crtc->base.dev;
7130         struct drm_i915_private *dev_priv = to_i915(dev);
7131         const struct intel_limit *limit;
7132         int refclk = 96000;
7133
7134         memset(&crtc_state->dpll_hw_state, 0,
7135                sizeof(crtc_state->dpll_hw_state));
7136
7137         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7138                 if (intel_panel_use_ssc(dev_priv)) {
7139                         refclk = dev_priv->vbt.lvds_ssc_freq;
7140                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7141                 }
7142
7143                 if (intel_is_dual_link_lvds(dev))
7144                         limit = &intel_limits_g4x_dual_channel_lvds;
7145                 else
7146                         limit = &intel_limits_g4x_single_channel_lvds;
7147         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7148                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7149                 limit = &intel_limits_g4x_hdmi;
7150         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7151                 limit = &intel_limits_g4x_sdvo;
7152         } else {
7153                 /* The option is for other outputs */
7154                 limit = &intel_limits_i9xx_sdvo;
7155         }
7156
7157         if (!crtc_state->clock_set &&
7158             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7159                                 refclk, NULL, &crtc_state->dpll)) {
7160                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7161                 return -EINVAL;
7162         }
7163
7164         i9xx_compute_dpll(crtc, crtc_state, NULL);
7165
7166         return 0;
7167 }
7168
7169 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7170                                   struct intel_crtc_state *crtc_state)
7171 {
7172         struct drm_device *dev = crtc->base.dev;
7173         struct drm_i915_private *dev_priv = to_i915(dev);
7174         const struct intel_limit *limit;
7175         int refclk = 96000;
7176
7177         memset(&crtc_state->dpll_hw_state, 0,
7178                sizeof(crtc_state->dpll_hw_state));
7179
7180         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7181                 if (intel_panel_use_ssc(dev_priv)) {
7182                         refclk = dev_priv->vbt.lvds_ssc_freq;
7183                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7184                 }
7185
7186                 limit = &intel_limits_pineview_lvds;
7187         } else {
7188                 limit = &intel_limits_pineview_sdvo;
7189         }
7190
7191         if (!crtc_state->clock_set &&
7192             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7193                                 refclk, NULL, &crtc_state->dpll)) {
7194                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7195                 return -EINVAL;
7196         }
7197
7198         i9xx_compute_dpll(crtc, crtc_state, NULL);
7199
7200         return 0;
7201 }
7202
7203 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7204                                    struct intel_crtc_state *crtc_state)
7205 {
7206         struct drm_device *dev = crtc->base.dev;
7207         struct drm_i915_private *dev_priv = to_i915(dev);
7208         const struct intel_limit *limit;
7209         int refclk = 96000;
7210
7211         memset(&crtc_state->dpll_hw_state, 0,
7212                sizeof(crtc_state->dpll_hw_state));
7213
7214         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7215                 if (intel_panel_use_ssc(dev_priv)) {
7216                         refclk = dev_priv->vbt.lvds_ssc_freq;
7217                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7218                 }
7219
7220                 limit = &intel_limits_i9xx_lvds;
7221         } else {
7222                 limit = &intel_limits_i9xx_sdvo;
7223         }
7224
7225         if (!crtc_state->clock_set &&
7226             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7227                                  refclk, NULL, &crtc_state->dpll)) {
7228                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7229                 return -EINVAL;
7230         }
7231
7232         i9xx_compute_dpll(crtc, crtc_state, NULL);
7233
7234         return 0;
7235 }
7236
7237 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7238                                   struct intel_crtc_state *crtc_state)
7239 {
7240         int refclk = 100000;
7241         const struct intel_limit *limit = &intel_limits_chv;
7242
7243         memset(&crtc_state->dpll_hw_state, 0,
7244                sizeof(crtc_state->dpll_hw_state));
7245
7246         if (!crtc_state->clock_set &&
7247             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7248                                 refclk, NULL, &crtc_state->dpll)) {
7249                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7250                 return -EINVAL;
7251         }
7252
7253         chv_compute_dpll(crtc, crtc_state);
7254
7255         return 0;
7256 }
7257
7258 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7259                                   struct intel_crtc_state *crtc_state)
7260 {
7261         int refclk = 100000;
7262         const struct intel_limit *limit = &intel_limits_vlv;
7263
7264         memset(&crtc_state->dpll_hw_state, 0,
7265                sizeof(crtc_state->dpll_hw_state));
7266
7267         if (!crtc_state->clock_set &&
7268             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7269                                 refclk, NULL, &crtc_state->dpll)) {
7270                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7271                 return -EINVAL;
7272         }
7273
7274         vlv_compute_dpll(crtc, crtc_state);
7275
7276         return 0;
7277 }
7278
7279 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7280                                  struct intel_crtc_state *pipe_config)
7281 {
7282         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7283         uint32_t tmp;
7284
7285         if (INTEL_GEN(dev_priv) <= 3 &&
7286             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7287                 return;
7288
7289         tmp = I915_READ(PFIT_CONTROL);
7290         if (!(tmp & PFIT_ENABLE))
7291                 return;
7292
7293         /* Check whether the pfit is attached to our pipe. */
7294         if (INTEL_GEN(dev_priv) < 4) {
7295                 if (crtc->pipe != PIPE_B)
7296                         return;
7297         } else {
7298                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7299                         return;
7300         }
7301
7302         pipe_config->gmch_pfit.control = tmp;
7303         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7304 }
7305
7306 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7307                                struct intel_crtc_state *pipe_config)
7308 {
7309         struct drm_device *dev = crtc->base.dev;
7310         struct drm_i915_private *dev_priv = to_i915(dev);
7311         int pipe = pipe_config->cpu_transcoder;
7312         struct dpll clock;
7313         u32 mdiv;
7314         int refclk = 100000;
7315
7316         /* In case of DSI, DPLL will not be used */
7317         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7318                 return;
7319
7320         mutex_lock(&dev_priv->sb_lock);
7321         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7322         mutex_unlock(&dev_priv->sb_lock);
7323
7324         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7325         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7326         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7327         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7328         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7329
7330         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7331 }
7332
7333 static void
7334 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7335                               struct intel_initial_plane_config *plane_config)
7336 {
7337         struct drm_device *dev = crtc->base.dev;
7338         struct drm_i915_private *dev_priv = to_i915(dev);
7339         u32 val, base, offset;
7340         int pipe = crtc->pipe, plane = crtc->plane;
7341         int fourcc, pixel_format;
7342         unsigned int aligned_height;
7343         struct drm_framebuffer *fb;
7344         struct intel_framebuffer *intel_fb;
7345
7346         val = I915_READ(DSPCNTR(plane));
7347         if (!(val & DISPLAY_PLANE_ENABLE))
7348                 return;
7349
7350         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7351         if (!intel_fb) {
7352                 DRM_DEBUG_KMS("failed to alloc fb\n");
7353                 return;
7354         }
7355
7356         fb = &intel_fb->base;
7357
7358         fb->dev = dev;
7359
7360         if (INTEL_GEN(dev_priv) >= 4) {
7361                 if (val & DISPPLANE_TILED) {
7362                         plane_config->tiling = I915_TILING_X;
7363                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7364                 }
7365         }
7366
7367         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7368         fourcc = i9xx_format_to_fourcc(pixel_format);
7369         fb->format = drm_format_info(fourcc);
7370
7371         if (INTEL_GEN(dev_priv) >= 4) {
7372                 if (plane_config->tiling)
7373                         offset = I915_READ(DSPTILEOFF(plane));
7374                 else
7375                         offset = I915_READ(DSPLINOFF(plane));
7376                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7377         } else {
7378                 base = I915_READ(DSPADDR(plane));
7379         }
7380         plane_config->base = base;
7381
7382         val = I915_READ(PIPESRC(pipe));
7383         fb->width = ((val >> 16) & 0xfff) + 1;
7384         fb->height = ((val >> 0) & 0xfff) + 1;
7385
7386         val = I915_READ(DSPSTRIDE(pipe));
7387         fb->pitches[0] = val & 0xffffffc0;
7388
7389         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7390
7391         plane_config->size = fb->pitches[0] * aligned_height;
7392
7393         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7394                       pipe_name(pipe), plane, fb->width, fb->height,
7395                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7396                       plane_config->size);
7397
7398         plane_config->fb = intel_fb;
7399 }
7400
7401 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7402                                struct intel_crtc_state *pipe_config)
7403 {
7404         struct drm_device *dev = crtc->base.dev;
7405         struct drm_i915_private *dev_priv = to_i915(dev);
7406         int pipe = pipe_config->cpu_transcoder;
7407         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7408         struct dpll clock;
7409         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7410         int refclk = 100000;
7411
7412         /* In case of DSI, DPLL will not be used */
7413         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7414                 return;
7415
7416         mutex_lock(&dev_priv->sb_lock);
7417         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7418         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7419         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7420         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7421         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7422         mutex_unlock(&dev_priv->sb_lock);
7423
7424         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7425         clock.m2 = (pll_dw0 & 0xff) << 22;
7426         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7427                 clock.m2 |= pll_dw2 & 0x3fffff;
7428         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7429         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7430         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7431
7432         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7433 }
7434
7435 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7436                                  struct intel_crtc_state *pipe_config)
7437 {
7438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7439         enum intel_display_power_domain power_domain;
7440         uint32_t tmp;
7441         bool ret;
7442
7443         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7444         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7445                 return false;
7446
7447         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7448         pipe_config->shared_dpll = NULL;
7449
7450         ret = false;
7451
7452         tmp = I915_READ(PIPECONF(crtc->pipe));
7453         if (!(tmp & PIPECONF_ENABLE))
7454                 goto out;
7455
7456         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7457             IS_CHERRYVIEW(dev_priv)) {
7458                 switch (tmp & PIPECONF_BPC_MASK) {
7459                 case PIPECONF_6BPC:
7460                         pipe_config->pipe_bpp = 18;
7461                         break;
7462                 case PIPECONF_8BPC:
7463                         pipe_config->pipe_bpp = 24;
7464                         break;
7465                 case PIPECONF_10BPC:
7466                         pipe_config->pipe_bpp = 30;
7467                         break;
7468                 default:
7469                         break;
7470                 }
7471         }
7472
7473         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7474             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7475                 pipe_config->limited_color_range = true;
7476
7477         if (INTEL_GEN(dev_priv) < 4)
7478                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7479
7480         intel_get_pipe_timings(crtc, pipe_config);
7481         intel_get_pipe_src_size(crtc, pipe_config);
7482
7483         i9xx_get_pfit_config(crtc, pipe_config);
7484
7485         if (INTEL_GEN(dev_priv) >= 4) {
7486                 /* No way to read it out on pipes B and C */
7487                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7488                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7489                 else
7490                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7491                 pipe_config->pixel_multiplier =
7492                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7493                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7494                 pipe_config->dpll_hw_state.dpll_md = tmp;
7495         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7496                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7497                 tmp = I915_READ(DPLL(crtc->pipe));
7498                 pipe_config->pixel_multiplier =
7499                         ((tmp & SDVO_MULTIPLIER_MASK)
7500                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7501         } else {
7502                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7503                  * port and will be fixed up in the encoder->get_config
7504                  * function. */
7505                 pipe_config->pixel_multiplier = 1;
7506         }
7507         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7508         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7509                 /*
7510                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7511                  * on 830. Filter it out here so that we don't
7512                  * report errors due to that.
7513                  */
7514                 if (IS_I830(dev_priv))
7515                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7516
7517                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7518                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7519         } else {
7520                 /* Mask out read-only status bits. */
7521                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7522                                                      DPLL_PORTC_READY_MASK |
7523                                                      DPLL_PORTB_READY_MASK);
7524         }
7525
7526         if (IS_CHERRYVIEW(dev_priv))
7527                 chv_crtc_clock_get(crtc, pipe_config);
7528         else if (IS_VALLEYVIEW(dev_priv))
7529                 vlv_crtc_clock_get(crtc, pipe_config);
7530         else
7531                 i9xx_crtc_clock_get(crtc, pipe_config);
7532
7533         /*
7534          * Normally the dotclock is filled in by the encoder .get_config()
7535          * but in case the pipe is enabled w/o any ports we need a sane
7536          * default.
7537          */
7538         pipe_config->base.adjusted_mode.crtc_clock =
7539                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7540
7541         ret = true;
7542
7543 out:
7544         intel_display_power_put(dev_priv, power_domain);
7545
7546         return ret;
7547 }
7548
7549 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7550 {
7551         struct intel_encoder *encoder;
7552         int i;
7553         u32 val, final;
7554         bool has_lvds = false;
7555         bool has_cpu_edp = false;
7556         bool has_panel = false;
7557         bool has_ck505 = false;
7558         bool can_ssc = false;
7559         bool using_ssc_source = false;
7560
7561         /* We need to take the global config into account */
7562         for_each_intel_encoder(&dev_priv->drm, encoder) {
7563                 switch (encoder->type) {
7564                 case INTEL_OUTPUT_LVDS:
7565                         has_panel = true;
7566                         has_lvds = true;
7567                         break;
7568                 case INTEL_OUTPUT_EDP:
7569                         has_panel = true;
7570                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7571                                 has_cpu_edp = true;
7572                         break;
7573                 default:
7574                         break;
7575                 }
7576         }
7577
7578         if (HAS_PCH_IBX(dev_priv)) {
7579                 has_ck505 = dev_priv->vbt.display_clock_mode;
7580                 can_ssc = has_ck505;
7581         } else {
7582                 has_ck505 = false;
7583                 can_ssc = true;
7584         }
7585
7586         /* Check if any DPLLs are using the SSC source */
7587         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7588                 u32 temp = I915_READ(PCH_DPLL(i));
7589
7590                 if (!(temp & DPLL_VCO_ENABLE))
7591                         continue;
7592
7593                 if ((temp & PLL_REF_INPUT_MASK) ==
7594                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7595                         using_ssc_source = true;
7596                         break;
7597                 }
7598         }
7599
7600         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7601                       has_panel, has_lvds, has_ck505, using_ssc_source);
7602
7603         /* Ironlake: try to setup display ref clock before DPLL
7604          * enabling. This is only under driver's control after
7605          * PCH B stepping, previous chipset stepping should be
7606          * ignoring this setting.
7607          */
7608         val = I915_READ(PCH_DREF_CONTROL);
7609
7610         /* As we must carefully and slowly disable/enable each source in turn,
7611          * compute the final state we want first and check if we need to
7612          * make any changes at all.
7613          */
7614         final = val;
7615         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7616         if (has_ck505)
7617                 final |= DREF_NONSPREAD_CK505_ENABLE;
7618         else
7619                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7620
7621         final &= ~DREF_SSC_SOURCE_MASK;
7622         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7623         final &= ~DREF_SSC1_ENABLE;
7624
7625         if (has_panel) {
7626                 final |= DREF_SSC_SOURCE_ENABLE;
7627
7628                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7629                         final |= DREF_SSC1_ENABLE;
7630
7631                 if (has_cpu_edp) {
7632                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7633                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7634                         else
7635                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7636                 } else
7637                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7638         } else if (using_ssc_source) {
7639                 final |= DREF_SSC_SOURCE_ENABLE;
7640                 final |= DREF_SSC1_ENABLE;
7641         }
7642
7643         if (final == val)
7644                 return;
7645
7646         /* Always enable nonspread source */
7647         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7648
7649         if (has_ck505)
7650                 val |= DREF_NONSPREAD_CK505_ENABLE;
7651         else
7652                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7653
7654         if (has_panel) {
7655                 val &= ~DREF_SSC_SOURCE_MASK;
7656                 val |= DREF_SSC_SOURCE_ENABLE;
7657
7658                 /* SSC must be turned on before enabling the CPU output  */
7659                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7660                         DRM_DEBUG_KMS("Using SSC on panel\n");
7661                         val |= DREF_SSC1_ENABLE;
7662                 } else
7663                         val &= ~DREF_SSC1_ENABLE;
7664
7665                 /* Get SSC going before enabling the outputs */
7666                 I915_WRITE(PCH_DREF_CONTROL, val);
7667                 POSTING_READ(PCH_DREF_CONTROL);
7668                 udelay(200);
7669
7670                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7671
7672                 /* Enable CPU source on CPU attached eDP */
7673                 if (has_cpu_edp) {
7674                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7675                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7676                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7677                         } else
7678                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7679                 } else
7680                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7681
7682                 I915_WRITE(PCH_DREF_CONTROL, val);
7683                 POSTING_READ(PCH_DREF_CONTROL);
7684                 udelay(200);
7685         } else {
7686                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7687
7688                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7689
7690                 /* Turn off CPU output */
7691                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7692
7693                 I915_WRITE(PCH_DREF_CONTROL, val);
7694                 POSTING_READ(PCH_DREF_CONTROL);
7695                 udelay(200);
7696
7697                 if (!using_ssc_source) {
7698                         DRM_DEBUG_KMS("Disabling SSC source\n");
7699
7700                         /* Turn off the SSC source */
7701                         val &= ~DREF_SSC_SOURCE_MASK;
7702                         val |= DREF_SSC_SOURCE_DISABLE;
7703
7704                         /* Turn off SSC1 */
7705                         val &= ~DREF_SSC1_ENABLE;
7706
7707                         I915_WRITE(PCH_DREF_CONTROL, val);
7708                         POSTING_READ(PCH_DREF_CONTROL);
7709                         udelay(200);
7710                 }
7711         }
7712
7713         BUG_ON(val != final);
7714 }
7715
7716 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7717 {
7718         uint32_t tmp;
7719
7720         tmp = I915_READ(SOUTH_CHICKEN2);
7721         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7722         I915_WRITE(SOUTH_CHICKEN2, tmp);
7723
7724         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7725                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7726                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7727
7728         tmp = I915_READ(SOUTH_CHICKEN2);
7729         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7730         I915_WRITE(SOUTH_CHICKEN2, tmp);
7731
7732         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7733                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7734                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7735 }
7736
7737 /* WaMPhyProgramming:hsw */
7738 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7739 {
7740         uint32_t tmp;
7741
7742         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7743         tmp &= ~(0xFF << 24);
7744         tmp |= (0x12 << 24);
7745         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7746
7747         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7748         tmp |= (1 << 11);
7749         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7750
7751         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7752         tmp |= (1 << 11);
7753         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7754
7755         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7756         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7757         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7758
7759         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7760         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7761         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7762
7763         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7764         tmp &= ~(7 << 13);
7765         tmp |= (5 << 13);
7766         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7767
7768         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7769         tmp &= ~(7 << 13);
7770         tmp |= (5 << 13);
7771         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7772
7773         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7774         tmp &= ~0xFF;
7775         tmp |= 0x1C;
7776         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7777
7778         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7779         tmp &= ~0xFF;
7780         tmp |= 0x1C;
7781         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7782
7783         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7784         tmp &= ~(0xFF << 16);
7785         tmp |= (0x1C << 16);
7786         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7787
7788         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7789         tmp &= ~(0xFF << 16);
7790         tmp |= (0x1C << 16);
7791         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7792
7793         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7794         tmp |= (1 << 27);
7795         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7796
7797         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7798         tmp |= (1 << 27);
7799         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7800
7801         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7802         tmp &= ~(0xF << 28);
7803         tmp |= (4 << 28);
7804         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7805
7806         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7807         tmp &= ~(0xF << 28);
7808         tmp |= (4 << 28);
7809         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7810 }
7811
7812 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7813  * Programming" based on the parameters passed:
7814  * - Sequence to enable CLKOUT_DP
7815  * - Sequence to enable CLKOUT_DP without spread
7816  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7817  */
7818 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7819                                  bool with_spread, bool with_fdi)
7820 {
7821         uint32_t reg, tmp;
7822
7823         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7824                 with_spread = true;
7825         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7826             with_fdi, "LP PCH doesn't have FDI\n"))
7827                 with_fdi = false;
7828
7829         mutex_lock(&dev_priv->sb_lock);
7830
7831         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7832         tmp &= ~SBI_SSCCTL_DISABLE;
7833         tmp |= SBI_SSCCTL_PATHALT;
7834         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7835
7836         udelay(24);
7837
7838         if (with_spread) {
7839                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7840                 tmp &= ~SBI_SSCCTL_PATHALT;
7841                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7842
7843                 if (with_fdi) {
7844                         lpt_reset_fdi_mphy(dev_priv);
7845                         lpt_program_fdi_mphy(dev_priv);
7846                 }
7847         }
7848
7849         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7850         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7851         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7852         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7853
7854         mutex_unlock(&dev_priv->sb_lock);
7855 }
7856
7857 /* Sequence to disable CLKOUT_DP */
7858 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7859 {
7860         uint32_t reg, tmp;
7861
7862         mutex_lock(&dev_priv->sb_lock);
7863
7864         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7865         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7866         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7867         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7868
7869         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7870         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7871                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7872                         tmp |= SBI_SSCCTL_PATHALT;
7873                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7874                         udelay(32);
7875                 }
7876                 tmp |= SBI_SSCCTL_DISABLE;
7877                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7878         }
7879
7880         mutex_unlock(&dev_priv->sb_lock);
7881 }
7882
7883 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7884
7885 static const uint16_t sscdivintphase[] = {
7886         [BEND_IDX( 50)] = 0x3B23,
7887         [BEND_IDX( 45)] = 0x3B23,
7888         [BEND_IDX( 40)] = 0x3C23,
7889         [BEND_IDX( 35)] = 0x3C23,
7890         [BEND_IDX( 30)] = 0x3D23,
7891         [BEND_IDX( 25)] = 0x3D23,
7892         [BEND_IDX( 20)] = 0x3E23,
7893         [BEND_IDX( 15)] = 0x3E23,
7894         [BEND_IDX( 10)] = 0x3F23,
7895         [BEND_IDX(  5)] = 0x3F23,
7896         [BEND_IDX(  0)] = 0x0025,
7897         [BEND_IDX( -5)] = 0x0025,
7898         [BEND_IDX(-10)] = 0x0125,
7899         [BEND_IDX(-15)] = 0x0125,
7900         [BEND_IDX(-20)] = 0x0225,
7901         [BEND_IDX(-25)] = 0x0225,
7902         [BEND_IDX(-30)] = 0x0325,
7903         [BEND_IDX(-35)] = 0x0325,
7904         [BEND_IDX(-40)] = 0x0425,
7905         [BEND_IDX(-45)] = 0x0425,
7906         [BEND_IDX(-50)] = 0x0525,
7907 };
7908
7909 /*
7910  * Bend CLKOUT_DP
7911  * steps -50 to 50 inclusive, in steps of 5
7912  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7913  * change in clock period = -(steps / 10) * 5.787 ps
7914  */
7915 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7916 {
7917         uint32_t tmp;
7918         int idx = BEND_IDX(steps);
7919
7920         if (WARN_ON(steps % 5 != 0))
7921                 return;
7922
7923         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7924                 return;
7925
7926         mutex_lock(&dev_priv->sb_lock);
7927
7928         if (steps % 10 != 0)
7929                 tmp = 0xAAAAAAAB;
7930         else
7931                 tmp = 0x00000000;
7932         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7933
7934         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7935         tmp &= 0xffff0000;
7936         tmp |= sscdivintphase[idx];
7937         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7938
7939         mutex_unlock(&dev_priv->sb_lock);
7940 }
7941
7942 #undef BEND_IDX
7943
7944 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7945 {
7946         struct intel_encoder *encoder;
7947         bool has_vga = false;
7948
7949         for_each_intel_encoder(&dev_priv->drm, encoder) {
7950                 switch (encoder->type) {
7951                 case INTEL_OUTPUT_ANALOG:
7952                         has_vga = true;
7953                         break;
7954                 default:
7955                         break;
7956                 }
7957         }
7958
7959         if (has_vga) {
7960                 lpt_bend_clkout_dp(dev_priv, 0);
7961                 lpt_enable_clkout_dp(dev_priv, true, true);
7962         } else {
7963                 lpt_disable_clkout_dp(dev_priv);
7964         }
7965 }
7966
7967 /*
7968  * Initialize reference clocks when the driver loads
7969  */
7970 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7971 {
7972         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7973                 ironlake_init_pch_refclk(dev_priv);
7974         else if (HAS_PCH_LPT(dev_priv))
7975                 lpt_init_pch_refclk(dev_priv);
7976 }
7977
7978 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7979 {
7980         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7982         int pipe = intel_crtc->pipe;
7983         uint32_t val;
7984
7985         val = 0;
7986
7987         switch (intel_crtc->config->pipe_bpp) {
7988         case 18:
7989                 val |= PIPECONF_6BPC;
7990                 break;
7991         case 24:
7992                 val |= PIPECONF_8BPC;
7993                 break;
7994         case 30:
7995                 val |= PIPECONF_10BPC;
7996                 break;
7997         case 36:
7998                 val |= PIPECONF_12BPC;
7999                 break;
8000         default:
8001                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8002                 BUG();
8003         }
8004
8005         if (intel_crtc->config->dither)
8006                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8007
8008         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8009                 val |= PIPECONF_INTERLACED_ILK;
8010         else
8011                 val |= PIPECONF_PROGRESSIVE;
8012
8013         if (intel_crtc->config->limited_color_range)
8014                 val |= PIPECONF_COLOR_RANGE_SELECT;
8015
8016         I915_WRITE(PIPECONF(pipe), val);
8017         POSTING_READ(PIPECONF(pipe));
8018 }
8019
8020 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8021 {
8022         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8024         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8025         u32 val = 0;
8026
8027         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8028                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8029
8030         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8031                 val |= PIPECONF_INTERLACED_ILK;
8032         else
8033                 val |= PIPECONF_PROGRESSIVE;
8034
8035         I915_WRITE(PIPECONF(cpu_transcoder), val);
8036         POSTING_READ(PIPECONF(cpu_transcoder));
8037 }
8038
8039 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8040 {
8041         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8043
8044         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8045                 u32 val = 0;
8046
8047                 switch (intel_crtc->config->pipe_bpp) {
8048                 case 18:
8049                         val |= PIPEMISC_DITHER_6_BPC;
8050                         break;
8051                 case 24:
8052                         val |= PIPEMISC_DITHER_8_BPC;
8053                         break;
8054                 case 30:
8055                         val |= PIPEMISC_DITHER_10_BPC;
8056                         break;
8057                 case 36:
8058                         val |= PIPEMISC_DITHER_12_BPC;
8059                         break;
8060                 default:
8061                         /* Case prevented by pipe_config_set_bpp. */
8062                         BUG();
8063                 }
8064
8065                 if (intel_crtc->config->dither)
8066                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8067
8068                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8069         }
8070 }
8071
8072 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8073 {
8074         /*
8075          * Account for spread spectrum to avoid
8076          * oversubscribing the link. Max center spread
8077          * is 2.5%; use 5% for safety's sake.
8078          */
8079         u32 bps = target_clock * bpp * 21 / 20;
8080         return DIV_ROUND_UP(bps, link_bw * 8);
8081 }
8082
8083 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8084 {
8085         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8086 }
8087
8088 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8089                                   struct intel_crtc_state *crtc_state,
8090                                   struct dpll *reduced_clock)
8091 {
8092         struct drm_crtc *crtc = &intel_crtc->base;
8093         struct drm_device *dev = crtc->dev;
8094         struct drm_i915_private *dev_priv = to_i915(dev);
8095         u32 dpll, fp, fp2;
8096         int factor;
8097
8098         /* Enable autotuning of the PLL clock (if permissible) */
8099         factor = 21;
8100         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8101                 if ((intel_panel_use_ssc(dev_priv) &&
8102                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8103                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8104                         factor = 25;
8105         } else if (crtc_state->sdvo_tv_clock)
8106                 factor = 20;
8107
8108         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8109
8110         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8111                 fp |= FP_CB_TUNE;
8112
8113         if (reduced_clock) {
8114                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8115
8116                 if (reduced_clock->m < factor * reduced_clock->n)
8117                         fp2 |= FP_CB_TUNE;
8118         } else {
8119                 fp2 = fp;
8120         }
8121
8122         dpll = 0;
8123
8124         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8125                 dpll |= DPLLB_MODE_LVDS;
8126         else
8127                 dpll |= DPLLB_MODE_DAC_SERIAL;
8128
8129         dpll |= (crtc_state->pixel_multiplier - 1)
8130                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8131
8132         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8133             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8134                 dpll |= DPLL_SDVO_HIGH_SPEED;
8135
8136         if (intel_crtc_has_dp_encoder(crtc_state))
8137                 dpll |= DPLL_SDVO_HIGH_SPEED;
8138
8139         /*
8140          * The high speed IO clock is only really required for
8141          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8142          * possible to share the DPLL between CRT and HDMI. Enabling
8143          * the clock needlessly does no real harm, except use up a
8144          * bit of power potentially.
8145          *
8146          * We'll limit this to IVB with 3 pipes, since it has only two
8147          * DPLLs and so DPLL sharing is the only way to get three pipes
8148          * driving PCH ports at the same time. On SNB we could do this,
8149          * and potentially avoid enabling the second DPLL, but it's not
8150          * clear if it''s a win or loss power wise. No point in doing
8151          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8152          */
8153         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8154             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8155                 dpll |= DPLL_SDVO_HIGH_SPEED;
8156
8157         /* compute bitmask from p1 value */
8158         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8159         /* also FPA1 */
8160         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8161
8162         switch (crtc_state->dpll.p2) {
8163         case 5:
8164                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8165                 break;
8166         case 7:
8167                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8168                 break;
8169         case 10:
8170                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8171                 break;
8172         case 14:
8173                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8174                 break;
8175         }
8176
8177         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8178             intel_panel_use_ssc(dev_priv))
8179                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8180         else
8181                 dpll |= PLL_REF_INPUT_DREFCLK;
8182
8183         dpll |= DPLL_VCO_ENABLE;
8184
8185         crtc_state->dpll_hw_state.dpll = dpll;
8186         crtc_state->dpll_hw_state.fp0 = fp;
8187         crtc_state->dpll_hw_state.fp1 = fp2;
8188 }
8189
8190 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8191                                        struct intel_crtc_state *crtc_state)
8192 {
8193         struct drm_device *dev = crtc->base.dev;
8194         struct drm_i915_private *dev_priv = to_i915(dev);
8195         const struct intel_limit *limit;
8196         int refclk = 120000;
8197
8198         memset(&crtc_state->dpll_hw_state, 0,
8199                sizeof(crtc_state->dpll_hw_state));
8200
8201         crtc->lowfreq_avail = false;
8202
8203         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8204         if (!crtc_state->has_pch_encoder)
8205                 return 0;
8206
8207         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8208                 if (intel_panel_use_ssc(dev_priv)) {
8209                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8210                                       dev_priv->vbt.lvds_ssc_freq);
8211                         refclk = dev_priv->vbt.lvds_ssc_freq;
8212                 }
8213
8214                 if (intel_is_dual_link_lvds(dev)) {
8215                         if (refclk == 100000)
8216                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8217                         else
8218                                 limit = &intel_limits_ironlake_dual_lvds;
8219                 } else {
8220                         if (refclk == 100000)
8221                                 limit = &intel_limits_ironlake_single_lvds_100m;
8222                         else
8223                                 limit = &intel_limits_ironlake_single_lvds;
8224                 }
8225         } else {
8226                 limit = &intel_limits_ironlake_dac;
8227         }
8228
8229         if (!crtc_state->clock_set &&
8230             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8231                                 refclk, NULL, &crtc_state->dpll)) {
8232                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8233                 return -EINVAL;
8234         }
8235
8236         ironlake_compute_dpll(crtc, crtc_state, NULL);
8237
8238         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8239                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8240                                  pipe_name(crtc->pipe));
8241                 return -EINVAL;
8242         }
8243
8244         return 0;
8245 }
8246
8247 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8248                                          struct intel_link_m_n *m_n)
8249 {
8250         struct drm_device *dev = crtc->base.dev;
8251         struct drm_i915_private *dev_priv = to_i915(dev);
8252         enum pipe pipe = crtc->pipe;
8253
8254         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8255         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8256         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8257                 & ~TU_SIZE_MASK;
8258         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8259         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8260                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8261 }
8262
8263 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8264                                          enum transcoder transcoder,
8265                                          struct intel_link_m_n *m_n,
8266                                          struct intel_link_m_n *m2_n2)
8267 {
8268         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8269         enum pipe pipe = crtc->pipe;
8270
8271         if (INTEL_GEN(dev_priv) >= 5) {
8272                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8273                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8274                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8275                         & ~TU_SIZE_MASK;
8276                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8277                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8278                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8279                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8280                  * gen < 8) and if DRRS is supported (to make sure the
8281                  * registers are not unnecessarily read).
8282                  */
8283                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8284                         crtc->config->has_drrs) {
8285                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8286                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8287                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8288                                         & ~TU_SIZE_MASK;
8289                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8290                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8291                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8292                 }
8293         } else {
8294                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8295                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8296                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8297                         & ~TU_SIZE_MASK;
8298                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8299                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8300                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8301         }
8302 }
8303
8304 void intel_dp_get_m_n(struct intel_crtc *crtc,
8305                       struct intel_crtc_state *pipe_config)
8306 {
8307         if (pipe_config->has_pch_encoder)
8308                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8309         else
8310                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8311                                              &pipe_config->dp_m_n,
8312                                              &pipe_config->dp_m2_n2);
8313 }
8314
8315 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8316                                         struct intel_crtc_state *pipe_config)
8317 {
8318         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8319                                      &pipe_config->fdi_m_n, NULL);
8320 }
8321
8322 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8323                                     struct intel_crtc_state *pipe_config)
8324 {
8325         struct drm_device *dev = crtc->base.dev;
8326         struct drm_i915_private *dev_priv = to_i915(dev);
8327         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8328         uint32_t ps_ctrl = 0;
8329         int id = -1;
8330         int i;
8331
8332         /* find scaler attached to this pipe */
8333         for (i = 0; i < crtc->num_scalers; i++) {
8334                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8335                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8336                         id = i;
8337                         pipe_config->pch_pfit.enabled = true;
8338                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8339                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8340                         break;
8341                 }
8342         }
8343
8344         scaler_state->scaler_id = id;
8345         if (id >= 0) {
8346                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8347         } else {
8348                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8349         }
8350 }
8351
8352 static void
8353 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8354                                  struct intel_initial_plane_config *plane_config)
8355 {
8356         struct drm_device *dev = crtc->base.dev;
8357         struct drm_i915_private *dev_priv = to_i915(dev);
8358         u32 val, base, offset, stride_mult, tiling;
8359         int pipe = crtc->pipe;
8360         int fourcc, pixel_format;
8361         unsigned int aligned_height;
8362         struct drm_framebuffer *fb;
8363         struct intel_framebuffer *intel_fb;
8364
8365         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8366         if (!intel_fb) {
8367                 DRM_DEBUG_KMS("failed to alloc fb\n");
8368                 return;
8369         }
8370
8371         fb = &intel_fb->base;
8372
8373         fb->dev = dev;
8374
8375         val = I915_READ(PLANE_CTL(pipe, 0));
8376         if (!(val & PLANE_CTL_ENABLE))
8377                 goto error;
8378
8379         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8380         fourcc = skl_format_to_fourcc(pixel_format,
8381                                       val & PLANE_CTL_ORDER_RGBX,
8382                                       val & PLANE_CTL_ALPHA_MASK);
8383         fb->format = drm_format_info(fourcc);
8384
8385         tiling = val & PLANE_CTL_TILED_MASK;
8386         switch (tiling) {
8387         case PLANE_CTL_TILED_LINEAR:
8388                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8389                 break;
8390         case PLANE_CTL_TILED_X:
8391                 plane_config->tiling = I915_TILING_X;
8392                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8393                 break;
8394         case PLANE_CTL_TILED_Y:
8395                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8396                 break;
8397         case PLANE_CTL_TILED_YF:
8398                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8399                 break;
8400         default:
8401                 MISSING_CASE(tiling);
8402                 goto error;
8403         }
8404
8405         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8406         plane_config->base = base;
8407
8408         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8409
8410         val = I915_READ(PLANE_SIZE(pipe, 0));
8411         fb->height = ((val >> 16) & 0xfff) + 1;
8412         fb->width = ((val >> 0) & 0x1fff) + 1;
8413
8414         val = I915_READ(PLANE_STRIDE(pipe, 0));
8415         stride_mult = intel_fb_stride_alignment(fb, 0);
8416         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8417
8418         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8419
8420         plane_config->size = fb->pitches[0] * aligned_height;
8421
8422         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8423                       pipe_name(pipe), fb->width, fb->height,
8424                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8425                       plane_config->size);
8426
8427         plane_config->fb = intel_fb;
8428         return;
8429
8430 error:
8431         kfree(intel_fb);
8432 }
8433
8434 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8435                                      struct intel_crtc_state *pipe_config)
8436 {
8437         struct drm_device *dev = crtc->base.dev;
8438         struct drm_i915_private *dev_priv = to_i915(dev);
8439         uint32_t tmp;
8440
8441         tmp = I915_READ(PF_CTL(crtc->pipe));
8442
8443         if (tmp & PF_ENABLE) {
8444                 pipe_config->pch_pfit.enabled = true;
8445                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8446                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8447
8448                 /* We currently do not free assignements of panel fitters on
8449                  * ivb/hsw (since we don't use the higher upscaling modes which
8450                  * differentiates them) so just WARN about this case for now. */
8451                 if (IS_GEN7(dev_priv)) {
8452                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8453                                 PF_PIPE_SEL_IVB(crtc->pipe));
8454                 }
8455         }
8456 }
8457
8458 static void
8459 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8460                                   struct intel_initial_plane_config *plane_config)
8461 {
8462         struct drm_device *dev = crtc->base.dev;
8463         struct drm_i915_private *dev_priv = to_i915(dev);
8464         u32 val, base, offset;
8465         int pipe = crtc->pipe;
8466         int fourcc, pixel_format;
8467         unsigned int aligned_height;
8468         struct drm_framebuffer *fb;
8469         struct intel_framebuffer *intel_fb;
8470
8471         val = I915_READ(DSPCNTR(pipe));
8472         if (!(val & DISPLAY_PLANE_ENABLE))
8473                 return;
8474
8475         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8476         if (!intel_fb) {
8477                 DRM_DEBUG_KMS("failed to alloc fb\n");
8478                 return;
8479         }
8480
8481         fb = &intel_fb->base;
8482
8483         fb->dev = dev;
8484
8485         if (INTEL_GEN(dev_priv) >= 4) {
8486                 if (val & DISPPLANE_TILED) {
8487                         plane_config->tiling = I915_TILING_X;
8488                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8489                 }
8490         }
8491
8492         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8493         fourcc = i9xx_format_to_fourcc(pixel_format);
8494         fb->format = drm_format_info(fourcc);
8495
8496         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8497         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8498                 offset = I915_READ(DSPOFFSET(pipe));
8499         } else {
8500                 if (plane_config->tiling)
8501                         offset = I915_READ(DSPTILEOFF(pipe));
8502                 else
8503                         offset = I915_READ(DSPLINOFF(pipe));
8504         }
8505         plane_config->base = base;
8506
8507         val = I915_READ(PIPESRC(pipe));
8508         fb->width = ((val >> 16) & 0xfff) + 1;
8509         fb->height = ((val >> 0) & 0xfff) + 1;
8510
8511         val = I915_READ(DSPSTRIDE(pipe));
8512         fb->pitches[0] = val & 0xffffffc0;
8513
8514         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8515
8516         plane_config->size = fb->pitches[0] * aligned_height;
8517
8518         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8519                       pipe_name(pipe), fb->width, fb->height,
8520                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8521                       plane_config->size);
8522
8523         plane_config->fb = intel_fb;
8524 }
8525
8526 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8527                                      struct intel_crtc_state *pipe_config)
8528 {
8529         struct drm_device *dev = crtc->base.dev;
8530         struct drm_i915_private *dev_priv = to_i915(dev);
8531         enum intel_display_power_domain power_domain;
8532         uint32_t tmp;
8533         bool ret;
8534
8535         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8536         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8537                 return false;
8538
8539         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8540         pipe_config->shared_dpll = NULL;
8541
8542         ret = false;
8543         tmp = I915_READ(PIPECONF(crtc->pipe));
8544         if (!(tmp & PIPECONF_ENABLE))
8545                 goto out;
8546
8547         switch (tmp & PIPECONF_BPC_MASK) {
8548         case PIPECONF_6BPC:
8549                 pipe_config->pipe_bpp = 18;
8550                 break;
8551         case PIPECONF_8BPC:
8552                 pipe_config->pipe_bpp = 24;
8553                 break;
8554         case PIPECONF_10BPC:
8555                 pipe_config->pipe_bpp = 30;
8556                 break;
8557         case PIPECONF_12BPC:
8558                 pipe_config->pipe_bpp = 36;
8559                 break;
8560         default:
8561                 break;
8562         }
8563
8564         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8565                 pipe_config->limited_color_range = true;
8566
8567         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8568                 struct intel_shared_dpll *pll;
8569                 enum intel_dpll_id pll_id;
8570
8571                 pipe_config->has_pch_encoder = true;
8572
8573                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8574                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8575                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8576
8577                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8578
8579                 if (HAS_PCH_IBX(dev_priv)) {
8580                         /*
8581                          * The pipe->pch transcoder and pch transcoder->pll
8582                          * mapping is fixed.
8583                          */
8584                         pll_id = (enum intel_dpll_id) crtc->pipe;
8585                 } else {
8586                         tmp = I915_READ(PCH_DPLL_SEL);
8587                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8588                                 pll_id = DPLL_ID_PCH_PLL_B;
8589                         else
8590                                 pll_id= DPLL_ID_PCH_PLL_A;
8591                 }
8592
8593                 pipe_config->shared_dpll =
8594                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8595                 pll = pipe_config->shared_dpll;
8596
8597                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8598                                                  &pipe_config->dpll_hw_state));
8599
8600                 tmp = pipe_config->dpll_hw_state.dpll;
8601                 pipe_config->pixel_multiplier =
8602                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8603                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8604
8605                 ironlake_pch_clock_get(crtc, pipe_config);
8606         } else {
8607                 pipe_config->pixel_multiplier = 1;
8608         }
8609
8610         intel_get_pipe_timings(crtc, pipe_config);
8611         intel_get_pipe_src_size(crtc, pipe_config);
8612
8613         ironlake_get_pfit_config(crtc, pipe_config);
8614
8615         ret = true;
8616
8617 out:
8618         intel_display_power_put(dev_priv, power_domain);
8619
8620         return ret;
8621 }
8622
8623 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8624 {
8625         struct drm_device *dev = &dev_priv->drm;
8626         struct intel_crtc *crtc;
8627
8628         for_each_intel_crtc(dev, crtc)
8629                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8630                      pipe_name(crtc->pipe));
8631
8632         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8633         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8634         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8635         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8636         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8637         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8638              "CPU PWM1 enabled\n");
8639         if (IS_HASWELL(dev_priv))
8640                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8641                      "CPU PWM2 enabled\n");
8642         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8643              "PCH PWM1 enabled\n");
8644         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8645              "Utility pin enabled\n");
8646         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8647
8648         /*
8649          * In theory we can still leave IRQs enabled, as long as only the HPD
8650          * interrupts remain enabled. We used to check for that, but since it's
8651          * gen-specific and since we only disable LCPLL after we fully disable
8652          * the interrupts, the check below should be enough.
8653          */
8654         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8655 }
8656
8657 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8658 {
8659         if (IS_HASWELL(dev_priv))
8660                 return I915_READ(D_COMP_HSW);
8661         else
8662                 return I915_READ(D_COMP_BDW);
8663 }
8664
8665 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8666 {
8667         if (IS_HASWELL(dev_priv)) {
8668                 mutex_lock(&dev_priv->rps.hw_lock);
8669                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8670                                             val))
8671                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8672                 mutex_unlock(&dev_priv->rps.hw_lock);
8673         } else {
8674                 I915_WRITE(D_COMP_BDW, val);
8675                 POSTING_READ(D_COMP_BDW);
8676         }
8677 }
8678
8679 /*
8680  * This function implements pieces of two sequences from BSpec:
8681  * - Sequence for display software to disable LCPLL
8682  * - Sequence for display software to allow package C8+
8683  * The steps implemented here are just the steps that actually touch the LCPLL
8684  * register. Callers should take care of disabling all the display engine
8685  * functions, doing the mode unset, fixing interrupts, etc.
8686  */
8687 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8688                               bool switch_to_fclk, bool allow_power_down)
8689 {
8690         uint32_t val;
8691
8692         assert_can_disable_lcpll(dev_priv);
8693
8694         val = I915_READ(LCPLL_CTL);
8695
8696         if (switch_to_fclk) {
8697                 val |= LCPLL_CD_SOURCE_FCLK;
8698                 I915_WRITE(LCPLL_CTL, val);
8699
8700                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8701                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8702                         DRM_ERROR("Switching to FCLK failed\n");
8703
8704                 val = I915_READ(LCPLL_CTL);
8705         }
8706
8707         val |= LCPLL_PLL_DISABLE;
8708         I915_WRITE(LCPLL_CTL, val);
8709         POSTING_READ(LCPLL_CTL);
8710
8711         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8712                 DRM_ERROR("LCPLL still locked\n");
8713
8714         val = hsw_read_dcomp(dev_priv);
8715         val |= D_COMP_COMP_DISABLE;
8716         hsw_write_dcomp(dev_priv, val);
8717         ndelay(100);
8718
8719         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8720                      1))
8721                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8722
8723         if (allow_power_down) {
8724                 val = I915_READ(LCPLL_CTL);
8725                 val |= LCPLL_POWER_DOWN_ALLOW;
8726                 I915_WRITE(LCPLL_CTL, val);
8727                 POSTING_READ(LCPLL_CTL);
8728         }
8729 }
8730
8731 /*
8732  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8733  * source.
8734  */
8735 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8736 {
8737         uint32_t val;
8738
8739         val = I915_READ(LCPLL_CTL);
8740
8741         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8742                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8743                 return;
8744
8745         /*
8746          * Make sure we're not on PC8 state before disabling PC8, otherwise
8747          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8748          */
8749         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8750
8751         if (val & LCPLL_POWER_DOWN_ALLOW) {
8752                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8753                 I915_WRITE(LCPLL_CTL, val);
8754                 POSTING_READ(LCPLL_CTL);
8755         }
8756
8757         val = hsw_read_dcomp(dev_priv);
8758         val |= D_COMP_COMP_FORCE;
8759         val &= ~D_COMP_COMP_DISABLE;
8760         hsw_write_dcomp(dev_priv, val);
8761
8762         val = I915_READ(LCPLL_CTL);
8763         val &= ~LCPLL_PLL_DISABLE;
8764         I915_WRITE(LCPLL_CTL, val);
8765
8766         if (intel_wait_for_register(dev_priv,
8767                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8768                                     5))
8769                 DRM_ERROR("LCPLL not locked yet\n");
8770
8771         if (val & LCPLL_CD_SOURCE_FCLK) {
8772                 val = I915_READ(LCPLL_CTL);
8773                 val &= ~LCPLL_CD_SOURCE_FCLK;
8774                 I915_WRITE(LCPLL_CTL, val);
8775
8776                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8777                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8778                         DRM_ERROR("Switching back to LCPLL failed\n");
8779         }
8780
8781         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8782         intel_update_cdclk(dev_priv);
8783 }
8784
8785 /*
8786  * Package states C8 and deeper are really deep PC states that can only be
8787  * reached when all the devices on the system allow it, so even if the graphics
8788  * device allows PC8+, it doesn't mean the system will actually get to these
8789  * states. Our driver only allows PC8+ when going into runtime PM.
8790  *
8791  * The requirements for PC8+ are that all the outputs are disabled, the power
8792  * well is disabled and most interrupts are disabled, and these are also
8793  * requirements for runtime PM. When these conditions are met, we manually do
8794  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8795  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8796  * hang the machine.
8797  *
8798  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8799  * the state of some registers, so when we come back from PC8+ we need to
8800  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8801  * need to take care of the registers kept by RC6. Notice that this happens even
8802  * if we don't put the device in PCI D3 state (which is what currently happens
8803  * because of the runtime PM support).
8804  *
8805  * For more, read "Display Sequences for Package C8" on the hardware
8806  * documentation.
8807  */
8808 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8809 {
8810         uint32_t val;
8811
8812         DRM_DEBUG_KMS("Enabling package C8+\n");
8813
8814         if (HAS_PCH_LPT_LP(dev_priv)) {
8815                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8816                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8817                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8818         }
8819
8820         lpt_disable_clkout_dp(dev_priv);
8821         hsw_disable_lcpll(dev_priv, true, true);
8822 }
8823
8824 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8825 {
8826         uint32_t val;
8827
8828         DRM_DEBUG_KMS("Disabling package C8+\n");
8829
8830         hsw_restore_lcpll(dev_priv);
8831         lpt_init_pch_refclk(dev_priv);
8832
8833         if (HAS_PCH_LPT_LP(dev_priv)) {
8834                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8835                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8836                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8837         }
8838 }
8839
8840 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8841                                       struct intel_crtc_state *crtc_state)
8842 {
8843         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8844                 struct intel_encoder *encoder =
8845                         intel_ddi_get_crtc_new_encoder(crtc_state);
8846
8847                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8848                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8849                                          pipe_name(crtc->pipe));
8850                         return -EINVAL;
8851                 }
8852         }
8853
8854         crtc->lowfreq_avail = false;
8855
8856         return 0;
8857 }
8858
8859 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8860                                 enum port port,
8861                                 struct intel_crtc_state *pipe_config)
8862 {
8863         enum intel_dpll_id id;
8864
8865         switch (port) {
8866         case PORT_A:
8867                 id = DPLL_ID_SKL_DPLL0;
8868                 break;
8869         case PORT_B:
8870                 id = DPLL_ID_SKL_DPLL1;
8871                 break;
8872         case PORT_C:
8873                 id = DPLL_ID_SKL_DPLL2;
8874                 break;
8875         default:
8876                 DRM_ERROR("Incorrect port type\n");
8877                 return;
8878         }
8879
8880         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8881 }
8882
8883 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8884                                 enum port port,
8885                                 struct intel_crtc_state *pipe_config)
8886 {
8887         enum intel_dpll_id id;
8888         u32 temp;
8889
8890         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8891         id = temp >> (port * 3 + 1);
8892
8893         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8894                 return;
8895
8896         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8897 }
8898
8899 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8900                                 enum port port,
8901                                 struct intel_crtc_state *pipe_config)
8902 {
8903         enum intel_dpll_id id;
8904         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8905
8906         switch (ddi_pll_sel) {
8907         case PORT_CLK_SEL_WRPLL1:
8908                 id = DPLL_ID_WRPLL1;
8909                 break;
8910         case PORT_CLK_SEL_WRPLL2:
8911                 id = DPLL_ID_WRPLL2;
8912                 break;
8913         case PORT_CLK_SEL_SPLL:
8914                 id = DPLL_ID_SPLL;
8915                 break;
8916         case PORT_CLK_SEL_LCPLL_810:
8917                 id = DPLL_ID_LCPLL_810;
8918                 break;
8919         case PORT_CLK_SEL_LCPLL_1350:
8920                 id = DPLL_ID_LCPLL_1350;
8921                 break;
8922         case PORT_CLK_SEL_LCPLL_2700:
8923                 id = DPLL_ID_LCPLL_2700;
8924                 break;
8925         default:
8926                 MISSING_CASE(ddi_pll_sel);
8927                 /* fall through */
8928         case PORT_CLK_SEL_NONE:
8929                 return;
8930         }
8931
8932         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8933 }
8934
8935 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8936                                      struct intel_crtc_state *pipe_config,
8937                                      u64 *power_domain_mask)
8938 {
8939         struct drm_device *dev = crtc->base.dev;
8940         struct drm_i915_private *dev_priv = to_i915(dev);
8941         enum intel_display_power_domain power_domain;
8942         u32 tmp;
8943
8944         /*
8945          * The pipe->transcoder mapping is fixed with the exception of the eDP
8946          * transcoder handled below.
8947          */
8948         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8949
8950         /*
8951          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8952          * consistency and less surprising code; it's in always on power).
8953          */
8954         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8955         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8956                 enum pipe trans_edp_pipe;
8957                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8958                 default:
8959                         WARN(1, "unknown pipe linked to edp transcoder\n");
8960                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8961                 case TRANS_DDI_EDP_INPUT_A_ON:
8962                         trans_edp_pipe = PIPE_A;
8963                         break;
8964                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8965                         trans_edp_pipe = PIPE_B;
8966                         break;
8967                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8968                         trans_edp_pipe = PIPE_C;
8969                         break;
8970                 }
8971
8972                 if (trans_edp_pipe == crtc->pipe)
8973                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8974         }
8975
8976         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8977         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8978                 return false;
8979         *power_domain_mask |= BIT_ULL(power_domain);
8980
8981         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8982
8983         return tmp & PIPECONF_ENABLE;
8984 }
8985
8986 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8987                                          struct intel_crtc_state *pipe_config,
8988                                          u64 *power_domain_mask)
8989 {
8990         struct drm_device *dev = crtc->base.dev;
8991         struct drm_i915_private *dev_priv = to_i915(dev);
8992         enum intel_display_power_domain power_domain;
8993         enum port port;
8994         enum transcoder cpu_transcoder;
8995         u32 tmp;
8996
8997         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8998                 if (port == PORT_A)
8999                         cpu_transcoder = TRANSCODER_DSI_A;
9000                 else
9001                         cpu_transcoder = TRANSCODER_DSI_C;
9002
9003                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9004                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9005                         continue;
9006                 *power_domain_mask |= BIT_ULL(power_domain);
9007
9008                 /*
9009                  * The PLL needs to be enabled with a valid divider
9010                  * configuration, otherwise accessing DSI registers will hang
9011                  * the machine. See BSpec North Display Engine
9012                  * registers/MIPI[BXT]. We can break out here early, since we
9013                  * need the same DSI PLL to be enabled for both DSI ports.
9014                  */
9015                 if (!intel_dsi_pll_is_enabled(dev_priv))
9016                         break;
9017
9018                 /* XXX: this works for video mode only */
9019                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9020                 if (!(tmp & DPI_ENABLE))
9021                         continue;
9022
9023                 tmp = I915_READ(MIPI_CTRL(port));
9024                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9025                         continue;
9026
9027                 pipe_config->cpu_transcoder = cpu_transcoder;
9028                 break;
9029         }
9030
9031         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9032 }
9033
9034 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9035                                        struct intel_crtc_state *pipe_config)
9036 {
9037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9038         struct intel_shared_dpll *pll;
9039         enum port port;
9040         uint32_t tmp;
9041
9042         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9043
9044         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9045
9046         if (IS_GEN9_BC(dev_priv))
9047                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9048         else if (IS_GEN9_LP(dev_priv))
9049                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9050         else
9051                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9052
9053         pll = pipe_config->shared_dpll;
9054         if (pll) {
9055                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9056                                                  &pipe_config->dpll_hw_state));
9057         }
9058
9059         /*
9060          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9061          * DDI E. So just check whether this pipe is wired to DDI E and whether
9062          * the PCH transcoder is on.
9063          */
9064         if (INTEL_GEN(dev_priv) < 9 &&
9065             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9066                 pipe_config->has_pch_encoder = true;
9067
9068                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9069                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9070                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9071
9072                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9073         }
9074 }
9075
9076 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9077                                     struct intel_crtc_state *pipe_config)
9078 {
9079         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9080         enum intel_display_power_domain power_domain;
9081         u64 power_domain_mask;
9082         bool active;
9083
9084         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9085         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9086                 return false;
9087         power_domain_mask = BIT_ULL(power_domain);
9088
9089         pipe_config->shared_dpll = NULL;
9090
9091         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9092
9093         if (IS_GEN9_LP(dev_priv) &&
9094             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9095                 WARN_ON(active);
9096                 active = true;
9097         }
9098
9099         if (!active)
9100                 goto out;
9101
9102         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9103                 haswell_get_ddi_port_state(crtc, pipe_config);
9104                 intel_get_pipe_timings(crtc, pipe_config);
9105         }
9106
9107         intel_get_pipe_src_size(crtc, pipe_config);
9108
9109         pipe_config->gamma_mode =
9110                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9111
9112         if (INTEL_GEN(dev_priv) >= 9) {
9113                 intel_crtc_init_scalers(crtc, pipe_config);
9114
9115                 pipe_config->scaler_state.scaler_id = -1;
9116                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9117         }
9118
9119         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9120         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9121                 power_domain_mask |= BIT_ULL(power_domain);
9122                 if (INTEL_GEN(dev_priv) >= 9)
9123                         skylake_get_pfit_config(crtc, pipe_config);
9124                 else
9125                         ironlake_get_pfit_config(crtc, pipe_config);
9126         }
9127
9128         if (IS_HASWELL(dev_priv))
9129                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9130                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9131
9132         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9133             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9134                 pipe_config->pixel_multiplier =
9135                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9136         } else {
9137                 pipe_config->pixel_multiplier = 1;
9138         }
9139
9140 out:
9141         for_each_power_domain(power_domain, power_domain_mask)
9142                 intel_display_power_put(dev_priv, power_domain);
9143
9144         return active;
9145 }
9146
9147 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9148 {
9149         struct drm_i915_private *dev_priv =
9150                 to_i915(plane_state->base.plane->dev);
9151         const struct drm_framebuffer *fb = plane_state->base.fb;
9152         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9153         u32 base;
9154
9155         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9156                 base = obj->phys_handle->busaddr;
9157         else
9158                 base = intel_plane_ggtt_offset(plane_state);
9159
9160         base += plane_state->main.offset;
9161
9162         /* ILK+ do this automagically */
9163         if (HAS_GMCH_DISPLAY(dev_priv) &&
9164             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9165                 base += (plane_state->base.crtc_h *
9166                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9167
9168         return base;
9169 }
9170
9171 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9172 {
9173         int x = plane_state->base.crtc_x;
9174         int y = plane_state->base.crtc_y;
9175         u32 pos = 0;
9176
9177         if (x < 0) {
9178                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9179                 x = -x;
9180         }
9181         pos |= x << CURSOR_X_SHIFT;
9182
9183         if (y < 0) {
9184                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9185                 y = -y;
9186         }
9187         pos |= y << CURSOR_Y_SHIFT;
9188
9189         return pos;
9190 }
9191
9192 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9193 {
9194         const struct drm_mode_config *config =
9195                 &plane_state->base.plane->dev->mode_config;
9196         int width = plane_state->base.crtc_w;
9197         int height = plane_state->base.crtc_h;
9198
9199         return width > 0 && width <= config->cursor_width &&
9200                 height > 0 && height <= config->cursor_height;
9201 }
9202
9203 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9204                               struct intel_plane_state *plane_state)
9205 {
9206         const struct drm_framebuffer *fb = plane_state->base.fb;
9207         int src_x, src_y;
9208         u32 offset;
9209         int ret;
9210
9211         ret = drm_plane_helper_check_state(&plane_state->base,
9212                                            &plane_state->clip,
9213                                            DRM_PLANE_HELPER_NO_SCALING,
9214                                            DRM_PLANE_HELPER_NO_SCALING,
9215                                            true, true);
9216         if (ret)
9217                 return ret;
9218
9219         if (!fb)
9220                 return 0;
9221
9222         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9223                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9224                 return -EINVAL;
9225         }
9226
9227         src_x = plane_state->base.src_x >> 16;
9228         src_y = plane_state->base.src_y >> 16;
9229
9230         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9231         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9232
9233         if (src_x != 0 || src_y != 0) {
9234                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9235                 return -EINVAL;
9236         }
9237
9238         plane_state->main.offset = offset;
9239
9240         return 0;
9241 }
9242
9243 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9244                            const struct intel_plane_state *plane_state)
9245 {
9246         const struct drm_framebuffer *fb = plane_state->base.fb;
9247
9248         return CURSOR_ENABLE |
9249                 CURSOR_GAMMA_ENABLE |
9250                 CURSOR_FORMAT_ARGB |
9251                 CURSOR_STRIDE(fb->pitches[0]);
9252 }
9253
9254 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9255 {
9256         int width = plane_state->base.crtc_w;
9257
9258         /*
9259          * 845g/865g are only limited by the width of their cursors,
9260          * the height is arbitrary up to the precision of the register.
9261          */
9262         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9263 }
9264
9265 static int i845_check_cursor(struct intel_plane *plane,
9266                              struct intel_crtc_state *crtc_state,
9267                              struct intel_plane_state *plane_state)
9268 {
9269         const struct drm_framebuffer *fb = plane_state->base.fb;
9270         int ret;
9271
9272         ret = intel_check_cursor(crtc_state, plane_state);
9273         if (ret)
9274                 return ret;
9275
9276         /* if we want to turn off the cursor ignore width and height */
9277         if (!fb)
9278                 return 0;
9279
9280         /* Check for which cursor types we support */
9281         if (!i845_cursor_size_ok(plane_state)) {
9282                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9283                           plane_state->base.crtc_w,
9284                           plane_state->base.crtc_h);
9285                 return -EINVAL;
9286         }
9287
9288         switch (fb->pitches[0]) {
9289         case 256:
9290         case 512:
9291         case 1024:
9292         case 2048:
9293                 break;
9294         default:
9295                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9296                               fb->pitches[0]);
9297                 return -EINVAL;
9298         }
9299
9300         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9301
9302         return 0;
9303 }
9304
9305 static void i845_update_cursor(struct intel_plane *plane,
9306                                const struct intel_crtc_state *crtc_state,
9307                                const struct intel_plane_state *plane_state)
9308 {
9309         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9310         u32 cntl = 0, base = 0, pos = 0, size = 0;
9311         unsigned long irqflags;
9312
9313         if (plane_state && plane_state->base.visible) {
9314                 unsigned int width = plane_state->base.crtc_w;
9315                 unsigned int height = plane_state->base.crtc_h;
9316
9317                 cntl = plane_state->ctl;
9318                 size = (height << 12) | width;
9319
9320                 base = intel_cursor_base(plane_state);
9321                 pos = intel_cursor_position(plane_state);
9322         }
9323
9324         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9325
9326         /* On these chipsets we can only modify the base/size/stride
9327          * whilst the cursor is disabled.
9328          */
9329         if (plane->cursor.base != base ||
9330             plane->cursor.size != size ||
9331             plane->cursor.cntl != cntl) {
9332                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9333                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9334                 I915_WRITE_FW(CURSIZE, size);
9335                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9336                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9337
9338                 plane->cursor.base = base;
9339                 plane->cursor.size = size;
9340                 plane->cursor.cntl = cntl;
9341         } else {
9342                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9343         }
9344
9345         POSTING_READ_FW(CURCNTR(PIPE_A));
9346
9347         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9348 }
9349
9350 static void i845_disable_cursor(struct intel_plane *plane,
9351                                 struct intel_crtc *crtc)
9352 {
9353         i845_update_cursor(plane, NULL, NULL);
9354 }
9355
9356 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9357                            const struct intel_plane_state *plane_state)
9358 {
9359         struct drm_i915_private *dev_priv =
9360                 to_i915(plane_state->base.plane->dev);
9361         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9362         u32 cntl;
9363
9364         cntl = MCURSOR_GAMMA_ENABLE;
9365
9366         if (HAS_DDI(dev_priv))
9367                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9368
9369         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9370
9371         switch (plane_state->base.crtc_w) {
9372         case 64:
9373                 cntl |= CURSOR_MODE_64_ARGB_AX;
9374                 break;
9375         case 128:
9376                 cntl |= CURSOR_MODE_128_ARGB_AX;
9377                 break;
9378         case 256:
9379                 cntl |= CURSOR_MODE_256_ARGB_AX;
9380                 break;
9381         default:
9382                 MISSING_CASE(plane_state->base.crtc_w);
9383                 return 0;
9384         }
9385
9386         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9387                 cntl |= CURSOR_ROTATE_180;
9388
9389         return cntl;
9390 }
9391
9392 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9393 {
9394         struct drm_i915_private *dev_priv =
9395                 to_i915(plane_state->base.plane->dev);
9396         int width = plane_state->base.crtc_w;
9397         int height = plane_state->base.crtc_h;
9398
9399         if (!intel_cursor_size_ok(plane_state))
9400                 return false;
9401
9402         /* Cursor width is limited to a few power-of-two sizes */
9403         switch (width) {
9404         case 256:
9405         case 128:
9406         case 64:
9407                 break;
9408         default:
9409                 return false;
9410         }
9411
9412         /*
9413          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9414          * height from 8 lines up to the cursor width, when the
9415          * cursor is not rotated. Everything else requires square
9416          * cursors.
9417          */
9418         if (HAS_CUR_FBC(dev_priv) &&
9419             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9420                 if (height < 8 || height > width)
9421                         return false;
9422         } else {
9423                 if (height != width)
9424                         return false;
9425         }
9426
9427         return true;
9428 }
9429
9430 static int i9xx_check_cursor(struct intel_plane *plane,
9431                              struct intel_crtc_state *crtc_state,
9432                              struct intel_plane_state *plane_state)
9433 {
9434         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9435         const struct drm_framebuffer *fb = plane_state->base.fb;
9436         enum pipe pipe = plane->pipe;
9437         int ret;
9438
9439         ret = intel_check_cursor(crtc_state, plane_state);
9440         if (ret)
9441                 return ret;
9442
9443         /* if we want to turn off the cursor ignore width and height */
9444         if (!fb)
9445                 return 0;
9446
9447         /* Check for which cursor types we support */
9448         if (!i9xx_cursor_size_ok(plane_state)) {
9449                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9450                           plane_state->base.crtc_w,
9451                           plane_state->base.crtc_h);
9452                 return -EINVAL;
9453         }
9454
9455         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9456                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9457                               fb->pitches[0], plane_state->base.crtc_w);
9458                 return -EINVAL;
9459         }
9460
9461         /*
9462          * There's something wrong with the cursor on CHV pipe C.
9463          * If it straddles the left edge of the screen then
9464          * moving it away from the edge or disabling it often
9465          * results in a pipe underrun, and often that can lead to
9466          * dead pipe (constant underrun reported, and it scans
9467          * out just a solid color). To recover from that, the
9468          * display power well must be turned off and on again.
9469          * Refuse the put the cursor into that compromised position.
9470          */
9471         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9472             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9473                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9474                 return -EINVAL;
9475         }
9476
9477         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9478
9479         return 0;
9480 }
9481
9482 static void i9xx_update_cursor(struct intel_plane *plane,
9483                                const struct intel_crtc_state *crtc_state,
9484                                const struct intel_plane_state *plane_state)
9485 {
9486         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9487         enum pipe pipe = plane->pipe;
9488         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9489         unsigned long irqflags;
9490
9491         if (plane_state && plane_state->base.visible) {
9492                 cntl = plane_state->ctl;
9493
9494                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9495                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9496
9497                 base = intel_cursor_base(plane_state);
9498                 pos = intel_cursor_position(plane_state);
9499         }
9500
9501         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9502
9503         /*
9504          * On some platforms writing CURCNTR first will also
9505          * cause CURPOS to be armed by the CURBASE write.
9506          * Without the CURCNTR write the CURPOS write would
9507          * arm itself.
9508          *
9509          * CURCNTR and CUR_FBC_CTL are always
9510          * armed by the CURBASE write only.
9511          */
9512         if (plane->cursor.base != base ||
9513             plane->cursor.size != fbc_ctl ||
9514             plane->cursor.cntl != cntl) {
9515                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9516                 if (HAS_CUR_FBC(dev_priv))
9517                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9518                 I915_WRITE_FW(CURPOS(pipe), pos);
9519                 I915_WRITE_FW(CURBASE(pipe), base);
9520
9521                 plane->cursor.base = base;
9522                 plane->cursor.size = fbc_ctl;
9523                 plane->cursor.cntl = cntl;
9524         } else {
9525                 I915_WRITE_FW(CURPOS(pipe), pos);
9526         }
9527
9528         POSTING_READ_FW(CURBASE(pipe));
9529
9530         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9531 }
9532
9533 static void i9xx_disable_cursor(struct intel_plane *plane,
9534                                 struct intel_crtc *crtc)
9535 {
9536         i9xx_update_cursor(plane, NULL, NULL);
9537 }
9538
9539
9540 /* VESA 640x480x72Hz mode to set on the pipe */
9541 static struct drm_display_mode load_detect_mode = {
9542         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9543                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9544 };
9545
9546 struct drm_framebuffer *
9547 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9548                          struct drm_mode_fb_cmd2 *mode_cmd)
9549 {
9550         struct intel_framebuffer *intel_fb;
9551         int ret;
9552
9553         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9554         if (!intel_fb)
9555                 return ERR_PTR(-ENOMEM);
9556
9557         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9558         if (ret)
9559                 goto err;
9560
9561         return &intel_fb->base;
9562
9563 err:
9564         kfree(intel_fb);
9565         return ERR_PTR(ret);
9566 }
9567
9568 static u32
9569 intel_framebuffer_pitch_for_width(int width, int bpp)
9570 {
9571         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9572         return ALIGN(pitch, 64);
9573 }
9574
9575 static u32
9576 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9577 {
9578         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9579         return PAGE_ALIGN(pitch * mode->vdisplay);
9580 }
9581
9582 static struct drm_framebuffer *
9583 intel_framebuffer_create_for_mode(struct drm_device *dev,
9584                                   struct drm_display_mode *mode,
9585                                   int depth, int bpp)
9586 {
9587         struct drm_framebuffer *fb;
9588         struct drm_i915_gem_object *obj;
9589         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9590
9591         obj = i915_gem_object_create(to_i915(dev),
9592                                     intel_framebuffer_size_for_mode(mode, bpp));
9593         if (IS_ERR(obj))
9594                 return ERR_CAST(obj);
9595
9596         mode_cmd.width = mode->hdisplay;
9597         mode_cmd.height = mode->vdisplay;
9598         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9599                                                                 bpp);
9600         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9601
9602         fb = intel_framebuffer_create(obj, &mode_cmd);
9603         if (IS_ERR(fb))
9604                 i915_gem_object_put(obj);
9605
9606         return fb;
9607 }
9608
9609 static struct drm_framebuffer *
9610 mode_fits_in_fbdev(struct drm_device *dev,
9611                    struct drm_display_mode *mode)
9612 {
9613 #ifdef CONFIG_DRM_FBDEV_EMULATION
9614         struct drm_i915_private *dev_priv = to_i915(dev);
9615         struct drm_i915_gem_object *obj;
9616         struct drm_framebuffer *fb;
9617
9618         if (!dev_priv->fbdev)
9619                 return NULL;
9620
9621         if (!dev_priv->fbdev->fb)
9622                 return NULL;
9623
9624         obj = dev_priv->fbdev->fb->obj;
9625         BUG_ON(!obj);
9626
9627         fb = &dev_priv->fbdev->fb->base;
9628         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9629                                                                fb->format->cpp[0] * 8))
9630                 return NULL;
9631
9632         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9633                 return NULL;
9634
9635         drm_framebuffer_reference(fb);
9636         return fb;
9637 #else
9638         return NULL;
9639 #endif
9640 }
9641
9642 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9643                                            struct drm_crtc *crtc,
9644                                            struct drm_display_mode *mode,
9645                                            struct drm_framebuffer *fb,
9646                                            int x, int y)
9647 {
9648         struct drm_plane_state *plane_state;
9649         int hdisplay, vdisplay;
9650         int ret;
9651
9652         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9653         if (IS_ERR(plane_state))
9654                 return PTR_ERR(plane_state);
9655
9656         if (mode)
9657                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9658         else
9659                 hdisplay = vdisplay = 0;
9660
9661         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9662         if (ret)
9663                 return ret;
9664         drm_atomic_set_fb_for_plane(plane_state, fb);
9665         plane_state->crtc_x = 0;
9666         plane_state->crtc_y = 0;
9667         plane_state->crtc_w = hdisplay;
9668         plane_state->crtc_h = vdisplay;
9669         plane_state->src_x = x << 16;
9670         plane_state->src_y = y << 16;
9671         plane_state->src_w = hdisplay << 16;
9672         plane_state->src_h = vdisplay << 16;
9673
9674         return 0;
9675 }
9676
9677 int intel_get_load_detect_pipe(struct drm_connector *connector,
9678                                struct drm_display_mode *mode,
9679                                struct intel_load_detect_pipe *old,
9680                                struct drm_modeset_acquire_ctx *ctx)
9681 {
9682         struct intel_crtc *intel_crtc;
9683         struct intel_encoder *intel_encoder =
9684                 intel_attached_encoder(connector);
9685         struct drm_crtc *possible_crtc;
9686         struct drm_encoder *encoder = &intel_encoder->base;
9687         struct drm_crtc *crtc = NULL;
9688         struct drm_device *dev = encoder->dev;
9689         struct drm_i915_private *dev_priv = to_i915(dev);
9690         struct drm_framebuffer *fb;
9691         struct drm_mode_config *config = &dev->mode_config;
9692         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9693         struct drm_connector_state *connector_state;
9694         struct intel_crtc_state *crtc_state;
9695         int ret, i = -1;
9696
9697         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9698                       connector->base.id, connector->name,
9699                       encoder->base.id, encoder->name);
9700
9701         old->restore_state = NULL;
9702
9703         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9704
9705         /*
9706          * Algorithm gets a little messy:
9707          *
9708          *   - if the connector already has an assigned crtc, use it (but make
9709          *     sure it's on first)
9710          *
9711          *   - try to find the first unused crtc that can drive this connector,
9712          *     and use that if we find one
9713          */
9714
9715         /* See if we already have a CRTC for this connector */
9716         if (connector->state->crtc) {
9717                 crtc = connector->state->crtc;
9718
9719                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9720                 if (ret)
9721                         goto fail;
9722
9723                 /* Make sure the crtc and connector are running */
9724                 goto found;
9725         }
9726
9727         /* Find an unused one (if possible) */
9728         for_each_crtc(dev, possible_crtc) {
9729                 i++;
9730                 if (!(encoder->possible_crtcs & (1 << i)))
9731                         continue;
9732
9733                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9734                 if (ret)
9735                         goto fail;
9736
9737                 if (possible_crtc->state->enable) {
9738                         drm_modeset_unlock(&possible_crtc->mutex);
9739                         continue;
9740                 }
9741
9742                 crtc = possible_crtc;
9743                 break;
9744         }
9745
9746         /*
9747          * If we didn't find an unused CRTC, don't use any.
9748          */
9749         if (!crtc) {
9750                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9751                 ret = -ENODEV;
9752                 goto fail;
9753         }
9754
9755 found:
9756         intel_crtc = to_intel_crtc(crtc);
9757
9758         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9759         if (ret)
9760                 goto fail;
9761
9762         state = drm_atomic_state_alloc(dev);
9763         restore_state = drm_atomic_state_alloc(dev);
9764         if (!state || !restore_state) {
9765                 ret = -ENOMEM;
9766                 goto fail;
9767         }
9768
9769         state->acquire_ctx = ctx;
9770         restore_state->acquire_ctx = ctx;
9771
9772         connector_state = drm_atomic_get_connector_state(state, connector);
9773         if (IS_ERR(connector_state)) {
9774                 ret = PTR_ERR(connector_state);
9775                 goto fail;
9776         }
9777
9778         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9779         if (ret)
9780                 goto fail;
9781
9782         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9783         if (IS_ERR(crtc_state)) {
9784                 ret = PTR_ERR(crtc_state);
9785                 goto fail;
9786         }
9787
9788         crtc_state->base.active = crtc_state->base.enable = true;
9789
9790         if (!mode)
9791                 mode = &load_detect_mode;
9792
9793         /* We need a framebuffer large enough to accommodate all accesses
9794          * that the plane may generate whilst we perform load detection.
9795          * We can not rely on the fbcon either being present (we get called
9796          * during its initialisation to detect all boot displays, or it may
9797          * not even exist) or that it is large enough to satisfy the
9798          * requested mode.
9799          */
9800         fb = mode_fits_in_fbdev(dev, mode);
9801         if (fb == NULL) {
9802                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9803                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9804         } else
9805                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9806         if (IS_ERR(fb)) {
9807                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9808                 ret = PTR_ERR(fb);
9809                 goto fail;
9810         }
9811
9812         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9813         if (ret)
9814                 goto fail;
9815
9816         drm_framebuffer_unreference(fb);
9817
9818         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9819         if (ret)
9820                 goto fail;
9821
9822         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9823         if (!ret)
9824                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9825         if (!ret)
9826                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9827         if (ret) {
9828                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9829                 goto fail;
9830         }
9831
9832         ret = drm_atomic_commit(state);
9833         if (ret) {
9834                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9835                 goto fail;
9836         }
9837
9838         old->restore_state = restore_state;
9839         drm_atomic_state_put(state);
9840
9841         /* let the connector get through one full cycle before testing */
9842         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9843         return true;
9844
9845 fail:
9846         if (state) {
9847                 drm_atomic_state_put(state);
9848                 state = NULL;
9849         }
9850         if (restore_state) {
9851                 drm_atomic_state_put(restore_state);
9852                 restore_state = NULL;
9853         }
9854
9855         if (ret == -EDEADLK)
9856                 return ret;
9857
9858         return false;
9859 }
9860
9861 void intel_release_load_detect_pipe(struct drm_connector *connector,
9862                                     struct intel_load_detect_pipe *old,
9863                                     struct drm_modeset_acquire_ctx *ctx)
9864 {
9865         struct intel_encoder *intel_encoder =
9866                 intel_attached_encoder(connector);
9867         struct drm_encoder *encoder = &intel_encoder->base;
9868         struct drm_atomic_state *state = old->restore_state;
9869         int ret;
9870
9871         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9872                       connector->base.id, connector->name,
9873                       encoder->base.id, encoder->name);
9874
9875         if (!state)
9876                 return;
9877
9878         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9879         if (ret)
9880                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9881         drm_atomic_state_put(state);
9882 }
9883
9884 static int i9xx_pll_refclk(struct drm_device *dev,
9885                            const struct intel_crtc_state *pipe_config)
9886 {
9887         struct drm_i915_private *dev_priv = to_i915(dev);
9888         u32 dpll = pipe_config->dpll_hw_state.dpll;
9889
9890         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9891                 return dev_priv->vbt.lvds_ssc_freq;
9892         else if (HAS_PCH_SPLIT(dev_priv))
9893                 return 120000;
9894         else if (!IS_GEN2(dev_priv))
9895                 return 96000;
9896         else
9897                 return 48000;
9898 }
9899
9900 /* Returns the clock of the currently programmed mode of the given pipe. */
9901 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9902                                 struct intel_crtc_state *pipe_config)
9903 {
9904         struct drm_device *dev = crtc->base.dev;
9905         struct drm_i915_private *dev_priv = to_i915(dev);
9906         int pipe = pipe_config->cpu_transcoder;
9907         u32 dpll = pipe_config->dpll_hw_state.dpll;
9908         u32 fp;
9909         struct dpll clock;
9910         int port_clock;
9911         int refclk = i9xx_pll_refclk(dev, pipe_config);
9912
9913         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9914                 fp = pipe_config->dpll_hw_state.fp0;
9915         else
9916                 fp = pipe_config->dpll_hw_state.fp1;
9917
9918         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9919         if (IS_PINEVIEW(dev_priv)) {
9920                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9921                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9922         } else {
9923                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9924                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9925         }
9926
9927         if (!IS_GEN2(dev_priv)) {
9928                 if (IS_PINEVIEW(dev_priv))
9929                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9930                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9931                 else
9932                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9933                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9934
9935                 switch (dpll & DPLL_MODE_MASK) {
9936                 case DPLLB_MODE_DAC_SERIAL:
9937                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9938                                 5 : 10;
9939                         break;
9940                 case DPLLB_MODE_LVDS:
9941                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9942                                 7 : 14;
9943                         break;
9944                 default:
9945                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9946                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9947                         return;
9948                 }
9949
9950                 if (IS_PINEVIEW(dev_priv))
9951                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9952                 else
9953                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9954         } else {
9955                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9956                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9957
9958                 if (is_lvds) {
9959                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9960                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9961
9962                         if (lvds & LVDS_CLKB_POWER_UP)
9963                                 clock.p2 = 7;
9964                         else
9965                                 clock.p2 = 14;
9966                 } else {
9967                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9968                                 clock.p1 = 2;
9969                         else {
9970                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9971                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9972                         }
9973                         if (dpll & PLL_P2_DIVIDE_BY_4)
9974                                 clock.p2 = 4;
9975                         else
9976                                 clock.p2 = 2;
9977                 }
9978
9979                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9980         }
9981
9982         /*
9983          * This value includes pixel_multiplier. We will use
9984          * port_clock to compute adjusted_mode.crtc_clock in the
9985          * encoder's get_config() function.
9986          */
9987         pipe_config->port_clock = port_clock;
9988 }
9989
9990 int intel_dotclock_calculate(int link_freq,
9991                              const struct intel_link_m_n *m_n)
9992 {
9993         /*
9994          * The calculation for the data clock is:
9995          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9996          * But we want to avoid losing precison if possible, so:
9997          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9998          *
9999          * and the link clock is simpler:
10000          * link_clock = (m * link_clock) / n
10001          */
10002
10003         if (!m_n->link_n)
10004                 return 0;
10005
10006         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10007 }
10008
10009 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10010                                    struct intel_crtc_state *pipe_config)
10011 {
10012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10013
10014         /* read out port_clock from the DPLL */
10015         i9xx_crtc_clock_get(crtc, pipe_config);
10016
10017         /*
10018          * In case there is an active pipe without active ports,
10019          * we may need some idea for the dotclock anyway.
10020          * Calculate one based on the FDI configuration.
10021          */
10022         pipe_config->base.adjusted_mode.crtc_clock =
10023                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10024                                          &pipe_config->fdi_m_n);
10025 }
10026
10027 /** Returns the currently programmed mode of the given pipe. */
10028 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10029                                              struct drm_crtc *crtc)
10030 {
10031         struct drm_i915_private *dev_priv = to_i915(dev);
10032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10033         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10034         struct drm_display_mode *mode;
10035         struct intel_crtc_state *pipe_config;
10036         int htot = I915_READ(HTOTAL(cpu_transcoder));
10037         int hsync = I915_READ(HSYNC(cpu_transcoder));
10038         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10039         int vsync = I915_READ(VSYNC(cpu_transcoder));
10040         enum pipe pipe = intel_crtc->pipe;
10041
10042         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10043         if (!mode)
10044                 return NULL;
10045
10046         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10047         if (!pipe_config) {
10048                 kfree(mode);
10049                 return NULL;
10050         }
10051
10052         /*
10053          * Construct a pipe_config sufficient for getting the clock info
10054          * back out of crtc_clock_get.
10055          *
10056          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10057          * to use a real value here instead.
10058          */
10059         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10060         pipe_config->pixel_multiplier = 1;
10061         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10062         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10063         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10064         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10065
10066         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10067         mode->hdisplay = (htot & 0xffff) + 1;
10068         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10069         mode->hsync_start = (hsync & 0xffff) + 1;
10070         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10071         mode->vdisplay = (vtot & 0xffff) + 1;
10072         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10073         mode->vsync_start = (vsync & 0xffff) + 1;
10074         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10075
10076         drm_mode_set_name(mode);
10077
10078         kfree(pipe_config);
10079
10080         return mode;
10081 }
10082
10083 static void intel_crtc_destroy(struct drm_crtc *crtc)
10084 {
10085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10086         struct drm_device *dev = crtc->dev;
10087         struct intel_flip_work *work;
10088
10089         spin_lock_irq(&dev->event_lock);
10090         work = intel_crtc->flip_work;
10091         intel_crtc->flip_work = NULL;
10092         spin_unlock_irq(&dev->event_lock);
10093
10094         if (work) {
10095                 cancel_work_sync(&work->mmio_work);
10096                 cancel_work_sync(&work->unpin_work);
10097                 kfree(work);
10098         }
10099
10100         drm_crtc_cleanup(crtc);
10101
10102         kfree(intel_crtc);
10103 }
10104
10105 static void intel_unpin_work_fn(struct work_struct *__work)
10106 {
10107         struct intel_flip_work *work =
10108                 container_of(__work, struct intel_flip_work, unpin_work);
10109         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10110         struct drm_device *dev = crtc->base.dev;
10111         struct drm_plane *primary = crtc->base.primary;
10112
10113         if (is_mmio_work(work))
10114                 flush_work(&work->mmio_work);
10115
10116         mutex_lock(&dev->struct_mutex);
10117         intel_unpin_fb_vma(work->old_vma);
10118         i915_gem_object_put(work->pending_flip_obj);
10119         mutex_unlock(&dev->struct_mutex);
10120
10121         i915_gem_request_put(work->flip_queued_req);
10122
10123         intel_frontbuffer_flip_complete(to_i915(dev),
10124                                         to_intel_plane(primary)->frontbuffer_bit);
10125         intel_fbc_post_update(crtc);
10126         drm_framebuffer_unreference(work->old_fb);
10127
10128         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10129         atomic_dec(&crtc->unpin_work_count);
10130
10131         kfree(work);
10132 }
10133
10134 /* Is 'a' after or equal to 'b'? */
10135 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10136 {
10137         return !((a - b) & 0x80000000);
10138 }
10139
10140 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10141                                    struct intel_flip_work *work)
10142 {
10143         struct drm_device *dev = crtc->base.dev;
10144         struct drm_i915_private *dev_priv = to_i915(dev);
10145
10146         if (abort_flip_on_reset(crtc))
10147                 return true;
10148
10149         /*
10150          * The relevant registers doen't exist on pre-ctg.
10151          * As the flip done interrupt doesn't trigger for mmio
10152          * flips on gmch platforms, a flip count check isn't
10153          * really needed there. But since ctg has the registers,
10154          * include it in the check anyway.
10155          */
10156         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10157                 return true;
10158
10159         /*
10160          * BDW signals flip done immediately if the plane
10161          * is disabled, even if the plane enable is already
10162          * armed to occur at the next vblank :(
10163          */
10164
10165         /*
10166          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10167          * used the same base address. In that case the mmio flip might
10168          * have completed, but the CS hasn't even executed the flip yet.
10169          *
10170          * A flip count check isn't enough as the CS might have updated
10171          * the base address just after start of vblank, but before we
10172          * managed to process the interrupt. This means we'd complete the
10173          * CS flip too soon.
10174          *
10175          * Combining both checks should get us a good enough result. It may
10176          * still happen that the CS flip has been executed, but has not
10177          * yet actually completed. But in case the base address is the same
10178          * anyway, we don't really care.
10179          */
10180         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10181                 crtc->flip_work->gtt_offset &&
10182                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10183                                     crtc->flip_work->flip_count);
10184 }
10185
10186 static bool
10187 __pageflip_finished_mmio(struct intel_crtc *crtc,
10188                                struct intel_flip_work *work)
10189 {
10190         /*
10191          * MMIO work completes when vblank is different from
10192          * flip_queued_vblank.
10193          *
10194          * Reset counter value doesn't matter, this is handled by
10195          * i915_wait_request finishing early, so no need to handle
10196          * reset here.
10197          */
10198         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10199 }
10200
10201
10202 static bool pageflip_finished(struct intel_crtc *crtc,
10203                               struct intel_flip_work *work)
10204 {
10205         if (!atomic_read(&work->pending))
10206                 return false;
10207
10208         smp_rmb();
10209
10210         if (is_mmio_work(work))
10211                 return __pageflip_finished_mmio(crtc, work);
10212         else
10213                 return __pageflip_finished_cs(crtc, work);
10214 }
10215
10216 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10217 {
10218         struct drm_device *dev = &dev_priv->drm;
10219         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10220         struct intel_flip_work *work;
10221         unsigned long flags;
10222
10223         /* Ignore early vblank irqs */
10224         if (!crtc)
10225                 return;
10226
10227         /*
10228          * This is called both by irq handlers and the reset code (to complete
10229          * lost pageflips) so needs the full irqsave spinlocks.
10230          */
10231         spin_lock_irqsave(&dev->event_lock, flags);
10232         work = crtc->flip_work;
10233
10234         if (work != NULL &&
10235             !is_mmio_work(work) &&
10236             pageflip_finished(crtc, work))
10237                 page_flip_completed(crtc);
10238
10239         spin_unlock_irqrestore(&dev->event_lock, flags);
10240 }
10241
10242 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10243 {
10244         struct drm_device *dev = &dev_priv->drm;
10245         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10246         struct intel_flip_work *work;
10247         unsigned long flags;
10248
10249         /* Ignore early vblank irqs */
10250         if (!crtc)
10251                 return;
10252
10253         /*
10254          * This is called both by irq handlers and the reset code (to complete
10255          * lost pageflips) so needs the full irqsave spinlocks.
10256          */
10257         spin_lock_irqsave(&dev->event_lock, flags);
10258         work = crtc->flip_work;
10259
10260         if (work != NULL &&
10261             is_mmio_work(work) &&
10262             pageflip_finished(crtc, work))
10263                 page_flip_completed(crtc);
10264
10265         spin_unlock_irqrestore(&dev->event_lock, flags);
10266 }
10267
10268 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10269                                                struct intel_flip_work *work)
10270 {
10271         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10272
10273         /* Ensure that the work item is consistent when activating it ... */
10274         smp_mb__before_atomic();
10275         atomic_set(&work->pending, 1);
10276 }
10277
10278 static int intel_gen2_queue_flip(struct drm_device *dev,
10279                                  struct drm_crtc *crtc,
10280                                  struct drm_framebuffer *fb,
10281                                  struct drm_i915_gem_object *obj,
10282                                  struct drm_i915_gem_request *req,
10283                                  uint32_t flags)
10284 {
10285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10286         u32 flip_mask, *cs;
10287
10288         cs = intel_ring_begin(req, 6);
10289         if (IS_ERR(cs))
10290                 return PTR_ERR(cs);
10291
10292         /* Can't queue multiple flips, so wait for the previous
10293          * one to finish before executing the next.
10294          */
10295         if (intel_crtc->plane)
10296                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10297         else
10298                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10299         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10300         *cs++ = MI_NOOP;
10301         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10302         *cs++ = fb->pitches[0];
10303         *cs++ = intel_crtc->flip_work->gtt_offset;
10304         *cs++ = 0; /* aux display base address, unused */
10305
10306         return 0;
10307 }
10308
10309 static int intel_gen3_queue_flip(struct drm_device *dev,
10310                                  struct drm_crtc *crtc,
10311                                  struct drm_framebuffer *fb,
10312                                  struct drm_i915_gem_object *obj,
10313                                  struct drm_i915_gem_request *req,
10314                                  uint32_t flags)
10315 {
10316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10317         u32 flip_mask, *cs;
10318
10319         cs = intel_ring_begin(req, 6);
10320         if (IS_ERR(cs))
10321                 return PTR_ERR(cs);
10322
10323         if (intel_crtc->plane)
10324                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10325         else
10326                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10327         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10328         *cs++ = MI_NOOP;
10329         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10330         *cs++ = fb->pitches[0];
10331         *cs++ = intel_crtc->flip_work->gtt_offset;
10332         *cs++ = MI_NOOP;
10333
10334         return 0;
10335 }
10336
10337 static int intel_gen4_queue_flip(struct drm_device *dev,
10338                                  struct drm_crtc *crtc,
10339                                  struct drm_framebuffer *fb,
10340                                  struct drm_i915_gem_object *obj,
10341                                  struct drm_i915_gem_request *req,
10342                                  uint32_t flags)
10343 {
10344         struct drm_i915_private *dev_priv = to_i915(dev);
10345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10346         u32 pf, pipesrc, *cs;
10347
10348         cs = intel_ring_begin(req, 4);
10349         if (IS_ERR(cs))
10350                 return PTR_ERR(cs);
10351
10352         /* i965+ uses the linear or tiled offsets from the
10353          * Display Registers (which do not change across a page-flip)
10354          * so we need only reprogram the base address.
10355          */
10356         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10357         *cs++ = fb->pitches[0];
10358         *cs++ = intel_crtc->flip_work->gtt_offset |
10359                 intel_fb_modifier_to_tiling(fb->modifier);
10360
10361         /* XXX Enabling the panel-fitter across page-flip is so far
10362          * untested on non-native modes, so ignore it for now.
10363          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10364          */
10365         pf = 0;
10366         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10367         *cs++ = pf | pipesrc;
10368
10369         return 0;
10370 }
10371
10372 static int intel_gen6_queue_flip(struct drm_device *dev,
10373                                  struct drm_crtc *crtc,
10374                                  struct drm_framebuffer *fb,
10375                                  struct drm_i915_gem_object *obj,
10376                                  struct drm_i915_gem_request *req,
10377                                  uint32_t flags)
10378 {
10379         struct drm_i915_private *dev_priv = to_i915(dev);
10380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10381         u32 pf, pipesrc, *cs;
10382
10383         cs = intel_ring_begin(req, 4);
10384         if (IS_ERR(cs))
10385                 return PTR_ERR(cs);
10386
10387         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10388         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10389         *cs++ = intel_crtc->flip_work->gtt_offset;
10390
10391         /* Contrary to the suggestions in the documentation,
10392          * "Enable Panel Fitter" does not seem to be required when page
10393          * flipping with a non-native mode, and worse causes a normal
10394          * modeset to fail.
10395          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10396          */
10397         pf = 0;
10398         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10399         *cs++ = pf | pipesrc;
10400
10401         return 0;
10402 }
10403
10404 static int intel_gen7_queue_flip(struct drm_device *dev,
10405                                  struct drm_crtc *crtc,
10406                                  struct drm_framebuffer *fb,
10407                                  struct drm_i915_gem_object *obj,
10408                                  struct drm_i915_gem_request *req,
10409                                  uint32_t flags)
10410 {
10411         struct drm_i915_private *dev_priv = to_i915(dev);
10412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10413         u32 *cs, plane_bit = 0;
10414         int len, ret;
10415
10416         switch (intel_crtc->plane) {
10417         case PLANE_A:
10418                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10419                 break;
10420         case PLANE_B:
10421                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10422                 break;
10423         case PLANE_C:
10424                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10425                 break;
10426         default:
10427                 WARN_ONCE(1, "unknown plane in flip command\n");
10428                 return -ENODEV;
10429         }
10430
10431         len = 4;
10432         if (req->engine->id == RCS) {
10433                 len += 6;
10434                 /*
10435                  * On Gen 8, SRM is now taking an extra dword to accommodate
10436                  * 48bits addresses, and we need a NOOP for the batch size to
10437                  * stay even.
10438                  */
10439                 if (IS_GEN8(dev_priv))
10440                         len += 2;
10441         }
10442
10443         /*
10444          * BSpec MI_DISPLAY_FLIP for IVB:
10445          * "The full packet must be contained within the same cache line."
10446          *
10447          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10448          * cacheline, if we ever start emitting more commands before
10449          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10450          * then do the cacheline alignment, and finally emit the
10451          * MI_DISPLAY_FLIP.
10452          */
10453         ret = intel_ring_cacheline_align(req);
10454         if (ret)
10455                 return ret;
10456
10457         cs = intel_ring_begin(req, len);
10458         if (IS_ERR(cs))
10459                 return PTR_ERR(cs);
10460
10461         /* Unmask the flip-done completion message. Note that the bspec says that
10462          * we should do this for both the BCS and RCS, and that we must not unmask
10463          * more than one flip event at any time (or ensure that one flip message
10464          * can be sent by waiting for flip-done prior to queueing new flips).
10465          * Experimentation says that BCS works despite DERRMR masking all
10466          * flip-done completion events and that unmasking all planes at once
10467          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10468          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10469          */
10470         if (req->engine->id == RCS) {
10471                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10472                 *cs++ = i915_mmio_reg_offset(DERRMR);
10473                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10474                           DERRMR_PIPEB_PRI_FLIP_DONE |
10475                           DERRMR_PIPEC_PRI_FLIP_DONE);
10476                 if (IS_GEN8(dev_priv))
10477                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10478                                 MI_SRM_LRM_GLOBAL_GTT;
10479                 else
10480                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10481                 *cs++ = i915_mmio_reg_offset(DERRMR);
10482                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10483                 if (IS_GEN8(dev_priv)) {
10484                         *cs++ = 0;
10485                         *cs++ = MI_NOOP;
10486                 }
10487         }
10488
10489         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10490         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10491         *cs++ = intel_crtc->flip_work->gtt_offset;
10492         *cs++ = MI_NOOP;
10493
10494         return 0;
10495 }
10496
10497 static bool use_mmio_flip(struct intel_engine_cs *engine,
10498                           struct drm_i915_gem_object *obj)
10499 {
10500         /*
10501          * This is not being used for older platforms, because
10502          * non-availability of flip done interrupt forces us to use
10503          * CS flips. Older platforms derive flip done using some clever
10504          * tricks involving the flip_pending status bits and vblank irqs.
10505          * So using MMIO flips there would disrupt this mechanism.
10506          */
10507
10508         if (engine == NULL)
10509                 return true;
10510
10511         if (INTEL_GEN(engine->i915) < 5)
10512                 return false;
10513
10514         if (i915.use_mmio_flip < 0)
10515                 return false;
10516         else if (i915.use_mmio_flip > 0)
10517                 return true;
10518         else if (i915.enable_execlists)
10519                 return true;
10520
10521         return engine != i915_gem_object_last_write_engine(obj);
10522 }
10523
10524 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10525                              unsigned int rotation,
10526                              struct intel_flip_work *work)
10527 {
10528         struct drm_device *dev = intel_crtc->base.dev;
10529         struct drm_i915_private *dev_priv = to_i915(dev);
10530         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10531         const enum pipe pipe = intel_crtc->pipe;
10532         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10533
10534         ctl = I915_READ(PLANE_CTL(pipe, 0));
10535         ctl &= ~PLANE_CTL_TILED_MASK;
10536         switch (fb->modifier) {
10537         case DRM_FORMAT_MOD_LINEAR:
10538                 break;
10539         case I915_FORMAT_MOD_X_TILED:
10540                 ctl |= PLANE_CTL_TILED_X;
10541                 break;
10542         case I915_FORMAT_MOD_Y_TILED:
10543                 ctl |= PLANE_CTL_TILED_Y;
10544                 break;
10545         case I915_FORMAT_MOD_Yf_TILED:
10546                 ctl |= PLANE_CTL_TILED_YF;
10547                 break;
10548         default:
10549                 MISSING_CASE(fb->modifier);
10550         }
10551
10552         /*
10553          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10554          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10555          */
10556         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10557         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10558
10559         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10560         POSTING_READ(PLANE_SURF(pipe, 0));
10561 }
10562
10563 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10564                              struct intel_flip_work *work)
10565 {
10566         struct drm_device *dev = intel_crtc->base.dev;
10567         struct drm_i915_private *dev_priv = to_i915(dev);
10568         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10569         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10570         u32 dspcntr;
10571
10572         dspcntr = I915_READ(reg);
10573
10574         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10575                 dspcntr |= DISPPLANE_TILED;
10576         else
10577                 dspcntr &= ~DISPPLANE_TILED;
10578
10579         I915_WRITE(reg, dspcntr);
10580
10581         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10582         POSTING_READ(DSPSURF(intel_crtc->plane));
10583 }
10584
10585 static void intel_mmio_flip_work_func(struct work_struct *w)
10586 {
10587         struct intel_flip_work *work =
10588                 container_of(w, struct intel_flip_work, mmio_work);
10589         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10590         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10591         struct intel_framebuffer *intel_fb =
10592                 to_intel_framebuffer(crtc->base.primary->fb);
10593         struct drm_i915_gem_object *obj = intel_fb->obj;
10594
10595         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10596
10597         intel_pipe_update_start(crtc);
10598
10599         if (INTEL_GEN(dev_priv) >= 9)
10600                 skl_do_mmio_flip(crtc, work->rotation, work);
10601         else
10602                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10603                 ilk_do_mmio_flip(crtc, work);
10604
10605         intel_pipe_update_end(crtc, work);
10606 }
10607
10608 static int intel_default_queue_flip(struct drm_device *dev,
10609                                     struct drm_crtc *crtc,
10610                                     struct drm_framebuffer *fb,
10611                                     struct drm_i915_gem_object *obj,
10612                                     struct drm_i915_gem_request *req,
10613                                     uint32_t flags)
10614 {
10615         return -ENODEV;
10616 }
10617
10618 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10619                                       struct intel_crtc *intel_crtc,
10620                                       struct intel_flip_work *work)
10621 {
10622         u32 addr, vblank;
10623
10624         if (!atomic_read(&work->pending))
10625                 return false;
10626
10627         smp_rmb();
10628
10629         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10630         if (work->flip_ready_vblank == 0) {
10631                 if (work->flip_queued_req &&
10632                     !i915_gem_request_completed(work->flip_queued_req))
10633                         return false;
10634
10635                 work->flip_ready_vblank = vblank;
10636         }
10637
10638         if (vblank - work->flip_ready_vblank < 3)
10639                 return false;
10640
10641         /* Potential stall - if we see that the flip has happened,
10642          * assume a missed interrupt. */
10643         if (INTEL_GEN(dev_priv) >= 4)
10644                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10645         else
10646                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10647
10648         /* There is a potential issue here with a false positive after a flip
10649          * to the same address. We could address this by checking for a
10650          * non-incrementing frame counter.
10651          */
10652         return addr == work->gtt_offset;
10653 }
10654
10655 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10656 {
10657         struct drm_device *dev = &dev_priv->drm;
10658         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10659         struct intel_flip_work *work;
10660
10661         WARN_ON(!in_interrupt());
10662
10663         if (crtc == NULL)
10664                 return;
10665
10666         spin_lock(&dev->event_lock);
10667         work = crtc->flip_work;
10668
10669         if (work != NULL && !is_mmio_work(work) &&
10670             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10671                 WARN_ONCE(1,
10672                           "Kicking stuck page flip: queued at %d, now %d\n",
10673                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10674                 page_flip_completed(crtc);
10675                 work = NULL;
10676         }
10677
10678         if (work != NULL && !is_mmio_work(work) &&
10679             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10680                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10681         spin_unlock(&dev->event_lock);
10682 }
10683
10684 __maybe_unused
10685 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10686                                 struct drm_framebuffer *fb,
10687                                 struct drm_pending_vblank_event *event,
10688                                 uint32_t page_flip_flags)
10689 {
10690         struct drm_device *dev = crtc->dev;
10691         struct drm_i915_private *dev_priv = to_i915(dev);
10692         struct drm_framebuffer *old_fb = crtc->primary->fb;
10693         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10695         struct drm_plane *primary = crtc->primary;
10696         enum pipe pipe = intel_crtc->pipe;
10697         struct intel_flip_work *work;
10698         struct intel_engine_cs *engine;
10699         bool mmio_flip;
10700         struct drm_i915_gem_request *request;
10701         struct i915_vma *vma;
10702         int ret;
10703
10704         /*
10705          * drm_mode_page_flip_ioctl() should already catch this, but double
10706          * check to be safe.  In the future we may enable pageflipping from
10707          * a disabled primary plane.
10708          */
10709         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10710                 return -EBUSY;
10711
10712         /* Can't change pixel format via MI display flips. */
10713         if (fb->format != crtc->primary->fb->format)
10714                 return -EINVAL;
10715
10716         /*
10717          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10718          * Note that pitch changes could also affect these register.
10719          */
10720         if (INTEL_GEN(dev_priv) > 3 &&
10721             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10722              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10723                 return -EINVAL;
10724
10725         if (i915_terminally_wedged(&dev_priv->gpu_error))
10726                 goto out_hang;
10727
10728         work = kzalloc(sizeof(*work), GFP_KERNEL);
10729         if (work == NULL)
10730                 return -ENOMEM;
10731
10732         work->event = event;
10733         work->crtc = crtc;
10734         work->old_fb = old_fb;
10735         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10736
10737         ret = drm_crtc_vblank_get(crtc);
10738         if (ret)
10739                 goto free_work;
10740
10741         /* We borrow the event spin lock for protecting flip_work */
10742         spin_lock_irq(&dev->event_lock);
10743         if (intel_crtc->flip_work) {
10744                 /* Before declaring the flip queue wedged, check if
10745                  * the hardware completed the operation behind our backs.
10746                  */
10747                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10748                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10749                         page_flip_completed(intel_crtc);
10750                 } else {
10751                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10752                         spin_unlock_irq(&dev->event_lock);
10753
10754                         drm_crtc_vblank_put(crtc);
10755                         kfree(work);
10756                         return -EBUSY;
10757                 }
10758         }
10759         intel_crtc->flip_work = work;
10760         spin_unlock_irq(&dev->event_lock);
10761
10762         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10763                 flush_workqueue(dev_priv->wq);
10764
10765         /* Reference the objects for the scheduled work. */
10766         drm_framebuffer_reference(work->old_fb);
10767
10768         crtc->primary->fb = fb;
10769         update_state_fb(crtc->primary);
10770
10771         work->pending_flip_obj = i915_gem_object_get(obj);
10772
10773         ret = i915_mutex_lock_interruptible(dev);
10774         if (ret)
10775                 goto cleanup;
10776
10777         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10778         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10779                 ret = -EIO;
10780                 goto unlock;
10781         }
10782
10783         atomic_inc(&intel_crtc->unpin_work_count);
10784
10785         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10786                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10787
10788         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10789                 engine = dev_priv->engine[BCS];
10790                 if (fb->modifier != old_fb->modifier)
10791                         /* vlv: DISPLAY_FLIP fails to change tiling */
10792                         engine = NULL;
10793         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10794                 engine = dev_priv->engine[BCS];
10795         } else if (INTEL_GEN(dev_priv) >= 7) {
10796                 engine = i915_gem_object_last_write_engine(obj);
10797                 if (engine == NULL || engine->id != RCS)
10798                         engine = dev_priv->engine[BCS];
10799         } else {
10800                 engine = dev_priv->engine[RCS];
10801         }
10802
10803         mmio_flip = use_mmio_flip(engine, obj);
10804
10805         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10806         if (IS_ERR(vma)) {
10807                 ret = PTR_ERR(vma);
10808                 goto cleanup_pending;
10809         }
10810
10811         work->old_vma = to_intel_plane_state(primary->state)->vma;
10812         to_intel_plane_state(primary->state)->vma = vma;
10813
10814         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10815         work->rotation = crtc->primary->state->rotation;
10816
10817         /*
10818          * There's the potential that the next frame will not be compatible with
10819          * FBC, so we want to call pre_update() before the actual page flip.
10820          * The problem is that pre_update() caches some information about the fb
10821          * object, so we want to do this only after the object is pinned. Let's
10822          * be on the safe side and do this immediately before scheduling the
10823          * flip.
10824          */
10825         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10826                              to_intel_plane_state(primary->state));
10827
10828         if (mmio_flip) {
10829                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10830                 queue_work(system_unbound_wq, &work->mmio_work);
10831         } else {
10832                 request = i915_gem_request_alloc(engine,
10833                                                  dev_priv->kernel_context);
10834                 if (IS_ERR(request)) {
10835                         ret = PTR_ERR(request);
10836                         goto cleanup_unpin;
10837                 }
10838
10839                 ret = i915_gem_request_await_object(request, obj, false);
10840                 if (ret)
10841                         goto cleanup_request;
10842
10843                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10844                                                    page_flip_flags);
10845                 if (ret)
10846                         goto cleanup_request;
10847
10848                 intel_mark_page_flip_active(intel_crtc, work);
10849
10850                 work->flip_queued_req = i915_gem_request_get(request);
10851                 i915_add_request(request);
10852         }
10853
10854         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10855         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10856                           to_intel_plane(primary)->frontbuffer_bit);
10857         mutex_unlock(&dev->struct_mutex);
10858
10859         intel_frontbuffer_flip_prepare(to_i915(dev),
10860                                        to_intel_plane(primary)->frontbuffer_bit);
10861
10862         trace_i915_flip_request(intel_crtc->plane, obj);
10863
10864         return 0;
10865
10866 cleanup_request:
10867         i915_add_request(request);
10868 cleanup_unpin:
10869         to_intel_plane_state(primary->state)->vma = work->old_vma;
10870         intel_unpin_fb_vma(vma);
10871 cleanup_pending:
10872         atomic_dec(&intel_crtc->unpin_work_count);
10873 unlock:
10874         mutex_unlock(&dev->struct_mutex);
10875 cleanup:
10876         crtc->primary->fb = old_fb;
10877         update_state_fb(crtc->primary);
10878
10879         i915_gem_object_put(obj);
10880         drm_framebuffer_unreference(work->old_fb);
10881
10882         spin_lock_irq(&dev->event_lock);
10883         intel_crtc->flip_work = NULL;
10884         spin_unlock_irq(&dev->event_lock);
10885
10886         drm_crtc_vblank_put(crtc);
10887 free_work:
10888         kfree(work);
10889
10890         if (ret == -EIO) {
10891                 struct drm_atomic_state *state;
10892                 struct drm_plane_state *plane_state;
10893
10894 out_hang:
10895                 state = drm_atomic_state_alloc(dev);
10896                 if (!state)
10897                         return -ENOMEM;
10898                 state->acquire_ctx = dev->mode_config.acquire_ctx;
10899
10900 retry:
10901                 plane_state = drm_atomic_get_plane_state(state, primary);
10902                 ret = PTR_ERR_OR_ZERO(plane_state);
10903                 if (!ret) {
10904                         drm_atomic_set_fb_for_plane(plane_state, fb);
10905
10906                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10907                         if (!ret)
10908                                 ret = drm_atomic_commit(state);
10909                 }
10910
10911                 if (ret == -EDEADLK) {
10912                         drm_modeset_backoff(state->acquire_ctx);
10913                         drm_atomic_state_clear(state);
10914                         goto retry;
10915                 }
10916
10917                 drm_atomic_state_put(state);
10918
10919                 if (ret == 0 && event) {
10920                         spin_lock_irq(&dev->event_lock);
10921                         drm_crtc_send_vblank_event(crtc, event);
10922                         spin_unlock_irq(&dev->event_lock);
10923                 }
10924         }
10925         return ret;
10926 }
10927
10928
10929 /**
10930  * intel_wm_need_update - Check whether watermarks need updating
10931  * @plane: drm plane
10932  * @state: new plane state
10933  *
10934  * Check current plane state versus the new one to determine whether
10935  * watermarks need to be recalculated.
10936  *
10937  * Returns true or false.
10938  */
10939 static bool intel_wm_need_update(struct drm_plane *plane,
10940                                  struct drm_plane_state *state)
10941 {
10942         struct intel_plane_state *new = to_intel_plane_state(state);
10943         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10944
10945         /* Update watermarks on tiling or size changes. */
10946         if (new->base.visible != cur->base.visible)
10947                 return true;
10948
10949         if (!cur->base.fb || !new->base.fb)
10950                 return false;
10951
10952         if (cur->base.fb->modifier != new->base.fb->modifier ||
10953             cur->base.rotation != new->base.rotation ||
10954             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10955             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10956             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10957             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10958                 return true;
10959
10960         return false;
10961 }
10962
10963 static bool needs_scaling(struct intel_plane_state *state)
10964 {
10965         int src_w = drm_rect_width(&state->base.src) >> 16;
10966         int src_h = drm_rect_height(&state->base.src) >> 16;
10967         int dst_w = drm_rect_width(&state->base.dst);
10968         int dst_h = drm_rect_height(&state->base.dst);
10969
10970         return (src_w != dst_w || src_h != dst_h);
10971 }
10972
10973 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10974                                     struct drm_plane_state *plane_state)
10975 {
10976         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10977         struct drm_crtc *crtc = crtc_state->crtc;
10978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10979         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10980         struct drm_device *dev = crtc->dev;
10981         struct drm_i915_private *dev_priv = to_i915(dev);
10982         struct intel_plane_state *old_plane_state =
10983                 to_intel_plane_state(plane->base.state);
10984         bool mode_changed = needs_modeset(crtc_state);
10985         bool was_crtc_enabled = crtc->state->active;
10986         bool is_crtc_enabled = crtc_state->active;
10987         bool turn_off, turn_on, visible, was_visible;
10988         struct drm_framebuffer *fb = plane_state->fb;
10989         int ret;
10990
10991         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10992                 ret = skl_update_scaler_plane(
10993                         to_intel_crtc_state(crtc_state),
10994                         to_intel_plane_state(plane_state));
10995                 if (ret)
10996                         return ret;
10997         }
10998
10999         was_visible = old_plane_state->base.visible;
11000         visible = plane_state->visible;
11001
11002         if (!was_crtc_enabled && WARN_ON(was_visible))
11003                 was_visible = false;
11004
11005         /*
11006          * Visibility is calculated as if the crtc was on, but
11007          * after scaler setup everything depends on it being off
11008          * when the crtc isn't active.
11009          *
11010          * FIXME this is wrong for watermarks. Watermarks should also
11011          * be computed as if the pipe would be active. Perhaps move
11012          * per-plane wm computation to the .check_plane() hook, and
11013          * only combine the results from all planes in the current place?
11014          */
11015         if (!is_crtc_enabled) {
11016                 plane_state->visible = visible = false;
11017                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11018         }
11019
11020         if (!was_visible && !visible)
11021                 return 0;
11022
11023         if (fb != old_plane_state->base.fb)
11024                 pipe_config->fb_changed = true;
11025
11026         turn_off = was_visible && (!visible || mode_changed);
11027         turn_on = visible && (!was_visible || mode_changed);
11028
11029         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11030                          intel_crtc->base.base.id, intel_crtc->base.name,
11031                          plane->base.base.id, plane->base.name,
11032                          fb ? fb->base.id : -1);
11033
11034         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11035                          plane->base.base.id, plane->base.name,
11036                          was_visible, visible,
11037                          turn_off, turn_on, mode_changed);
11038
11039         if (turn_on) {
11040                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11041                         pipe_config->update_wm_pre = true;
11042
11043                 /* must disable cxsr around plane enable/disable */
11044                 if (plane->id != PLANE_CURSOR)
11045                         pipe_config->disable_cxsr = true;
11046         } else if (turn_off) {
11047                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11048                         pipe_config->update_wm_post = true;
11049
11050                 /* must disable cxsr around plane enable/disable */
11051                 if (plane->id != PLANE_CURSOR)
11052                         pipe_config->disable_cxsr = true;
11053         } else if (intel_wm_need_update(&plane->base, plane_state)) {
11054                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11055                         /* FIXME bollocks */
11056                         pipe_config->update_wm_pre = true;
11057                         pipe_config->update_wm_post = true;
11058                 }
11059         }
11060
11061         if (visible || was_visible)
11062                 pipe_config->fb_bits |= plane->frontbuffer_bit;
11063
11064         /*
11065          * WaCxSRDisabledForSpriteScaling:ivb
11066          *
11067          * cstate->update_wm was already set above, so this flag will
11068          * take effect when we commit and program watermarks.
11069          */
11070         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
11071             needs_scaling(to_intel_plane_state(plane_state)) &&
11072             !needs_scaling(old_plane_state))
11073                 pipe_config->disable_lp_wm = true;
11074
11075         return 0;
11076 }
11077
11078 static bool encoders_cloneable(const struct intel_encoder *a,
11079                                const struct intel_encoder *b)
11080 {
11081         /* masks could be asymmetric, so check both ways */
11082         return a == b || (a->cloneable & (1 << b->type) &&
11083                           b->cloneable & (1 << a->type));
11084 }
11085
11086 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11087                                          struct intel_crtc *crtc,
11088                                          struct intel_encoder *encoder)
11089 {
11090         struct intel_encoder *source_encoder;
11091         struct drm_connector *connector;
11092         struct drm_connector_state *connector_state;
11093         int i;
11094
11095         for_each_new_connector_in_state(state, connector, connector_state, i) {
11096                 if (connector_state->crtc != &crtc->base)
11097                         continue;
11098
11099                 source_encoder =
11100                         to_intel_encoder(connector_state->best_encoder);
11101                 if (!encoders_cloneable(encoder, source_encoder))
11102                         return false;
11103         }
11104
11105         return true;
11106 }
11107
11108 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11109                                    struct drm_crtc_state *crtc_state)
11110 {
11111         struct drm_device *dev = crtc->dev;
11112         struct drm_i915_private *dev_priv = to_i915(dev);
11113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11114         struct intel_crtc_state *pipe_config =
11115                 to_intel_crtc_state(crtc_state);
11116         struct drm_atomic_state *state = crtc_state->state;
11117         int ret;
11118         bool mode_changed = needs_modeset(crtc_state);
11119
11120         if (mode_changed && !crtc_state->active)
11121                 pipe_config->update_wm_post = true;
11122
11123         if (mode_changed && crtc_state->enable &&
11124             dev_priv->display.crtc_compute_clock &&
11125             !WARN_ON(pipe_config->shared_dpll)) {
11126                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11127                                                            pipe_config);
11128                 if (ret)
11129                         return ret;
11130         }
11131
11132         if (crtc_state->color_mgmt_changed) {
11133                 ret = intel_color_check(crtc, crtc_state);
11134                 if (ret)
11135                         return ret;
11136
11137                 /*
11138                  * Changing color management on Intel hardware is
11139                  * handled as part of planes update.
11140                  */
11141                 crtc_state->planes_changed = true;
11142         }
11143
11144         ret = 0;
11145         if (dev_priv->display.compute_pipe_wm) {
11146                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11147                 if (ret) {
11148                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11149                         return ret;
11150                 }
11151         }
11152
11153         if (dev_priv->display.compute_intermediate_wm &&
11154             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11155                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11156                         return 0;
11157
11158                 /*
11159                  * Calculate 'intermediate' watermarks that satisfy both the
11160                  * old state and the new state.  We can program these
11161                  * immediately.
11162                  */
11163                 ret = dev_priv->display.compute_intermediate_wm(dev,
11164                                                                 intel_crtc,
11165                                                                 pipe_config);
11166                 if (ret) {
11167                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11168                         return ret;
11169                 }
11170         } else if (dev_priv->display.compute_intermediate_wm) {
11171                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11172                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11173         }
11174
11175         if (INTEL_GEN(dev_priv) >= 9) {
11176                 if (mode_changed)
11177                         ret = skl_update_scaler_crtc(pipe_config);
11178
11179                 if (!ret)
11180                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11181                                                          pipe_config);
11182         }
11183
11184         return ret;
11185 }
11186
11187 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11188         .atomic_begin = intel_begin_crtc_commit,
11189         .atomic_flush = intel_finish_crtc_commit,
11190         .atomic_check = intel_crtc_atomic_check,
11191 };
11192
11193 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11194 {
11195         struct intel_connector *connector;
11196         struct drm_connector_list_iter conn_iter;
11197
11198         drm_connector_list_iter_begin(dev, &conn_iter);
11199         for_each_intel_connector_iter(connector, &conn_iter) {
11200                 if (connector->base.state->crtc)
11201                         drm_connector_unreference(&connector->base);
11202
11203                 if (connector->base.encoder) {
11204                         connector->base.state->best_encoder =
11205                                 connector->base.encoder;
11206                         connector->base.state->crtc =
11207                                 connector->base.encoder->crtc;
11208
11209                         drm_connector_reference(&connector->base);
11210                 } else {
11211                         connector->base.state->best_encoder = NULL;
11212                         connector->base.state->crtc = NULL;
11213                 }
11214         }
11215         drm_connector_list_iter_end(&conn_iter);
11216 }
11217
11218 static void
11219 connected_sink_compute_bpp(struct intel_connector *connector,
11220                            struct intel_crtc_state *pipe_config)
11221 {
11222         const struct drm_display_info *info = &connector->base.display_info;
11223         int bpp = pipe_config->pipe_bpp;
11224
11225         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11226                       connector->base.base.id,
11227                       connector->base.name);
11228
11229         /* Don't use an invalid EDID bpc value */
11230         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11231                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11232                               bpp, info->bpc * 3);
11233                 pipe_config->pipe_bpp = info->bpc * 3;
11234         }
11235
11236         /* Clamp bpp to 8 on screens without EDID 1.4 */
11237         if (info->bpc == 0 && bpp > 24) {
11238                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11239                               bpp);
11240                 pipe_config->pipe_bpp = 24;
11241         }
11242 }
11243
11244 static int
11245 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11246                           struct intel_crtc_state *pipe_config)
11247 {
11248         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11249         struct drm_atomic_state *state;
11250         struct drm_connector *connector;
11251         struct drm_connector_state *connector_state;
11252         int bpp, i;
11253
11254         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11255             IS_CHERRYVIEW(dev_priv)))
11256                 bpp = 10*3;
11257         else if (INTEL_GEN(dev_priv) >= 5)
11258                 bpp = 12*3;
11259         else
11260                 bpp = 8*3;
11261
11262
11263         pipe_config->pipe_bpp = bpp;
11264
11265         state = pipe_config->base.state;
11266
11267         /* Clamp display bpp to EDID value */
11268         for_each_new_connector_in_state(state, connector, connector_state, i) {
11269                 if (connector_state->crtc != &crtc->base)
11270                         continue;
11271
11272                 connected_sink_compute_bpp(to_intel_connector(connector),
11273                                            pipe_config);
11274         }
11275
11276         return bpp;
11277 }
11278
11279 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11280 {
11281         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11282                         "type: 0x%x flags: 0x%x\n",
11283                 mode->crtc_clock,
11284                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11285                 mode->crtc_hsync_end, mode->crtc_htotal,
11286                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11287                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11288 }
11289
11290 static inline void
11291 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11292                       unsigned int lane_count, struct intel_link_m_n *m_n)
11293 {
11294         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11295                       id, lane_count,
11296                       m_n->gmch_m, m_n->gmch_n,
11297                       m_n->link_m, m_n->link_n, m_n->tu);
11298 }
11299
11300 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11301                                    struct intel_crtc_state *pipe_config,
11302                                    const char *context)
11303 {
11304         struct drm_device *dev = crtc->base.dev;
11305         struct drm_i915_private *dev_priv = to_i915(dev);
11306         struct drm_plane *plane;
11307         struct intel_plane *intel_plane;
11308         struct intel_plane_state *state;
11309         struct drm_framebuffer *fb;
11310
11311         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11312                       crtc->base.base.id, crtc->base.name, context);
11313
11314         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11315                       transcoder_name(pipe_config->cpu_transcoder),
11316                       pipe_config->pipe_bpp, pipe_config->dither);
11317
11318         if (pipe_config->has_pch_encoder)
11319                 intel_dump_m_n_config(pipe_config, "fdi",
11320                                       pipe_config->fdi_lanes,
11321                                       &pipe_config->fdi_m_n);
11322
11323         if (intel_crtc_has_dp_encoder(pipe_config)) {
11324                 intel_dump_m_n_config(pipe_config, "dp m_n",
11325                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11326                 if (pipe_config->has_drrs)
11327                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11328                                               pipe_config->lane_count,
11329                                               &pipe_config->dp_m2_n2);
11330         }
11331
11332         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11333                       pipe_config->has_audio, pipe_config->has_infoframe);
11334
11335         DRM_DEBUG_KMS("requested mode:\n");
11336         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11337         DRM_DEBUG_KMS("adjusted mode:\n");
11338         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11339         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11340         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11341                       pipe_config->port_clock,
11342                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11343                       pipe_config->pixel_rate);
11344
11345         if (INTEL_GEN(dev_priv) >= 9)
11346                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11347                               crtc->num_scalers,
11348                               pipe_config->scaler_state.scaler_users,
11349                               pipe_config->scaler_state.scaler_id);
11350
11351         if (HAS_GMCH_DISPLAY(dev_priv))
11352                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11353                               pipe_config->gmch_pfit.control,
11354                               pipe_config->gmch_pfit.pgm_ratios,
11355                               pipe_config->gmch_pfit.lvds_border_bits);
11356         else
11357                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11358                               pipe_config->pch_pfit.pos,
11359                               pipe_config->pch_pfit.size,
11360                               enableddisabled(pipe_config->pch_pfit.enabled));
11361
11362         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11363                       pipe_config->ips_enabled, pipe_config->double_wide);
11364
11365         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11366
11367         DRM_DEBUG_KMS("planes on this crtc\n");
11368         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11369                 struct drm_format_name_buf format_name;
11370                 intel_plane = to_intel_plane(plane);
11371                 if (intel_plane->pipe != crtc->pipe)
11372                         continue;
11373
11374                 state = to_intel_plane_state(plane->state);
11375                 fb = state->base.fb;
11376                 if (!fb) {
11377                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11378                                       plane->base.id, plane->name, state->scaler_id);
11379                         continue;
11380                 }
11381
11382                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11383                               plane->base.id, plane->name,
11384                               fb->base.id, fb->width, fb->height,
11385                               drm_get_format_name(fb->format->format, &format_name));
11386                 if (INTEL_GEN(dev_priv) >= 9)
11387                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11388                                       state->scaler_id,
11389                                       state->base.src.x1 >> 16,
11390                                       state->base.src.y1 >> 16,
11391                                       drm_rect_width(&state->base.src) >> 16,
11392                                       drm_rect_height(&state->base.src) >> 16,
11393                                       state->base.dst.x1, state->base.dst.y1,
11394                                       drm_rect_width(&state->base.dst),
11395                                       drm_rect_height(&state->base.dst));
11396         }
11397 }
11398
11399 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11400 {
11401         struct drm_device *dev = state->dev;
11402         struct drm_connector *connector;
11403         unsigned int used_ports = 0;
11404         unsigned int used_mst_ports = 0;
11405
11406         /*
11407          * Walk the connector list instead of the encoder
11408          * list to detect the problem on ddi platforms
11409          * where there's just one encoder per digital port.
11410          */
11411         drm_for_each_connector(connector, dev) {
11412                 struct drm_connector_state *connector_state;
11413                 struct intel_encoder *encoder;
11414
11415                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11416                 if (!connector_state)
11417                         connector_state = connector->state;
11418
11419                 if (!connector_state->best_encoder)
11420                         continue;
11421
11422                 encoder = to_intel_encoder(connector_state->best_encoder);
11423
11424                 WARN_ON(!connector_state->crtc);
11425
11426                 switch (encoder->type) {
11427                         unsigned int port_mask;
11428                 case INTEL_OUTPUT_UNKNOWN:
11429                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11430                                 break;
11431                 case INTEL_OUTPUT_DP:
11432                 case INTEL_OUTPUT_HDMI:
11433                 case INTEL_OUTPUT_EDP:
11434                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11435
11436                         /* the same port mustn't appear more than once */
11437                         if (used_ports & port_mask)
11438                                 return false;
11439
11440                         used_ports |= port_mask;
11441                         break;
11442                 case INTEL_OUTPUT_DP_MST:
11443                         used_mst_ports |=
11444                                 1 << enc_to_mst(&encoder->base)->primary->port;
11445                         break;
11446                 default:
11447                         break;
11448                 }
11449         }
11450
11451         /* can't mix MST and SST/HDMI on the same port */
11452         if (used_ports & used_mst_ports)
11453                 return false;
11454
11455         return true;
11456 }
11457
11458 static void
11459 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11460 {
11461         struct drm_i915_private *dev_priv =
11462                 to_i915(crtc_state->base.crtc->dev);
11463         struct intel_crtc_scaler_state scaler_state;
11464         struct intel_dpll_hw_state dpll_hw_state;
11465         struct intel_shared_dpll *shared_dpll;
11466         struct intel_crtc_wm_state wm_state;
11467         bool force_thru;
11468
11469         /* FIXME: before the switch to atomic started, a new pipe_config was
11470          * kzalloc'd. Code that depends on any field being zero should be
11471          * fixed, so that the crtc_state can be safely duplicated. For now,
11472          * only fields that are know to not cause problems are preserved. */
11473
11474         scaler_state = crtc_state->scaler_state;
11475         shared_dpll = crtc_state->shared_dpll;
11476         dpll_hw_state = crtc_state->dpll_hw_state;
11477         force_thru = crtc_state->pch_pfit.force_thru;
11478         if (IS_G4X(dev_priv) ||
11479             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11480                 wm_state = crtc_state->wm;
11481
11482         /* Keep base drm_crtc_state intact, only clear our extended struct */
11483         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11484         memset(&crtc_state->base + 1, 0,
11485                sizeof(*crtc_state) - sizeof(crtc_state->base));
11486
11487         crtc_state->scaler_state = scaler_state;
11488         crtc_state->shared_dpll = shared_dpll;
11489         crtc_state->dpll_hw_state = dpll_hw_state;
11490         crtc_state->pch_pfit.force_thru = force_thru;
11491         if (IS_G4X(dev_priv) ||
11492             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11493                 crtc_state->wm = wm_state;
11494 }
11495
11496 static int
11497 intel_modeset_pipe_config(struct drm_crtc *crtc,
11498                           struct intel_crtc_state *pipe_config)
11499 {
11500         struct drm_atomic_state *state = pipe_config->base.state;
11501         struct intel_encoder *encoder;
11502         struct drm_connector *connector;
11503         struct drm_connector_state *connector_state;
11504         int base_bpp, ret = -EINVAL;
11505         int i;
11506         bool retry = true;
11507
11508         clear_intel_crtc_state(pipe_config);
11509
11510         pipe_config->cpu_transcoder =
11511                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11512
11513         /*
11514          * Sanitize sync polarity flags based on requested ones. If neither
11515          * positive or negative polarity is requested, treat this as meaning
11516          * negative polarity.
11517          */
11518         if (!(pipe_config->base.adjusted_mode.flags &
11519               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11520                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11521
11522         if (!(pipe_config->base.adjusted_mode.flags &
11523               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11524                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11525
11526         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11527                                              pipe_config);
11528         if (base_bpp < 0)
11529                 goto fail;
11530
11531         /*
11532          * Determine the real pipe dimensions. Note that stereo modes can
11533          * increase the actual pipe size due to the frame doubling and
11534          * insertion of additional space for blanks between the frame. This
11535          * is stored in the crtc timings. We use the requested mode to do this
11536          * computation to clearly distinguish it from the adjusted mode, which
11537          * can be changed by the connectors in the below retry loop.
11538          */
11539         drm_mode_get_hv_timing(&pipe_config->base.mode,
11540                                &pipe_config->pipe_src_w,
11541                                &pipe_config->pipe_src_h);
11542
11543         for_each_new_connector_in_state(state, connector, connector_state, i) {
11544                 if (connector_state->crtc != crtc)
11545                         continue;
11546
11547                 encoder = to_intel_encoder(connector_state->best_encoder);
11548
11549                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11550                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11551                         goto fail;
11552                 }
11553
11554                 /*
11555                  * Determine output_types before calling the .compute_config()
11556                  * hooks so that the hooks can use this information safely.
11557                  */
11558                 pipe_config->output_types |= 1 << encoder->type;
11559         }
11560
11561 encoder_retry:
11562         /* Ensure the port clock defaults are reset when retrying. */
11563         pipe_config->port_clock = 0;
11564         pipe_config->pixel_multiplier = 1;
11565
11566         /* Fill in default crtc timings, allow encoders to overwrite them. */
11567         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11568                               CRTC_STEREO_DOUBLE);
11569
11570         /* Pass our mode to the connectors and the CRTC to give them a chance to
11571          * adjust it according to limitations or connector properties, and also
11572          * a chance to reject the mode entirely.
11573          */
11574         for_each_new_connector_in_state(state, connector, connector_state, i) {
11575                 if (connector_state->crtc != crtc)
11576                         continue;
11577
11578                 encoder = to_intel_encoder(connector_state->best_encoder);
11579
11580                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11581                         DRM_DEBUG_KMS("Encoder config failure\n");
11582                         goto fail;
11583                 }
11584         }
11585
11586         /* Set default port clock if not overwritten by the encoder. Needs to be
11587          * done afterwards in case the encoder adjusts the mode. */
11588         if (!pipe_config->port_clock)
11589                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11590                         * pipe_config->pixel_multiplier;
11591
11592         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11593         if (ret < 0) {
11594                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11595                 goto fail;
11596         }
11597
11598         if (ret == RETRY) {
11599                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11600                         ret = -EINVAL;
11601                         goto fail;
11602                 }
11603
11604                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11605                 retry = false;
11606                 goto encoder_retry;
11607         }
11608
11609         /* Dithering seems to not pass-through bits correctly when it should, so
11610          * only enable it on 6bpc panels and when its not a compliance
11611          * test requesting 6bpc video pattern.
11612          */
11613         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11614                 !pipe_config->dither_force_disable;
11615         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11616                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11617
11618 fail:
11619         return ret;
11620 }
11621
11622 static void
11623 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11624 {
11625         struct drm_crtc *crtc;
11626         struct drm_crtc_state *new_crtc_state;
11627         int i;
11628
11629         /* Double check state. */
11630         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11631                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11632
11633                 /*
11634                  * Update legacy state to satisfy fbc code. This can
11635                  * be removed when fbc uses the atomic state.
11636                  */
11637                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11638                         struct drm_plane_state *plane_state = crtc->primary->state;
11639
11640                         crtc->primary->fb = plane_state->fb;
11641                         crtc->x = plane_state->src_x >> 16;
11642                         crtc->y = plane_state->src_y >> 16;
11643                 }
11644         }
11645 }
11646
11647 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11648 {
11649         int diff;
11650
11651         if (clock1 == clock2)
11652                 return true;
11653
11654         if (!clock1 || !clock2)
11655                 return false;
11656
11657         diff = abs(clock1 - clock2);
11658
11659         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11660                 return true;
11661
11662         return false;
11663 }
11664
11665 static bool
11666 intel_compare_m_n(unsigned int m, unsigned int n,
11667                   unsigned int m2, unsigned int n2,
11668                   bool exact)
11669 {
11670         if (m == m2 && n == n2)
11671                 return true;
11672
11673         if (exact || !m || !n || !m2 || !n2)
11674                 return false;
11675
11676         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11677
11678         if (n > n2) {
11679                 while (n > n2) {
11680                         m2 <<= 1;
11681                         n2 <<= 1;
11682                 }
11683         } else if (n < n2) {
11684                 while (n < n2) {
11685                         m <<= 1;
11686                         n <<= 1;
11687                 }
11688         }
11689
11690         if (n != n2)
11691                 return false;
11692
11693         return intel_fuzzy_clock_check(m, m2);
11694 }
11695
11696 static bool
11697 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11698                        struct intel_link_m_n *m2_n2,
11699                        bool adjust)
11700 {
11701         if (m_n->tu == m2_n2->tu &&
11702             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11703                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11704             intel_compare_m_n(m_n->link_m, m_n->link_n,
11705                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11706                 if (adjust)
11707                         *m2_n2 = *m_n;
11708
11709                 return true;
11710         }
11711
11712         return false;
11713 }
11714
11715 static void __printf(3, 4)
11716 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11717 {
11718         char *level;
11719         unsigned int category;
11720         struct va_format vaf;
11721         va_list args;
11722
11723         if (adjust) {
11724                 level = KERN_DEBUG;
11725                 category = DRM_UT_KMS;
11726         } else {
11727                 level = KERN_ERR;
11728                 category = DRM_UT_NONE;
11729         }
11730
11731         va_start(args, format);
11732         vaf.fmt = format;
11733         vaf.va = &args;
11734
11735         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11736
11737         va_end(args);
11738 }
11739
11740 static bool
11741 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11742                           struct intel_crtc_state *current_config,
11743                           struct intel_crtc_state *pipe_config,
11744                           bool adjust)
11745 {
11746         bool ret = true;
11747
11748 #define PIPE_CONF_CHECK_X(name) \
11749         if (current_config->name != pipe_config->name) { \
11750                 pipe_config_err(adjust, __stringify(name), \
11751                           "(expected 0x%08x, found 0x%08x)\n", \
11752                           current_config->name, \
11753                           pipe_config->name); \
11754                 ret = false; \
11755         }
11756
11757 #define PIPE_CONF_CHECK_I(name) \
11758         if (current_config->name != pipe_config->name) { \
11759                 pipe_config_err(adjust, __stringify(name), \
11760                           "(expected %i, found %i)\n", \
11761                           current_config->name, \
11762                           pipe_config->name); \
11763                 ret = false; \
11764         }
11765
11766 #define PIPE_CONF_CHECK_P(name) \
11767         if (current_config->name != pipe_config->name) { \
11768                 pipe_config_err(adjust, __stringify(name), \
11769                           "(expected %p, found %p)\n", \
11770                           current_config->name, \
11771                           pipe_config->name); \
11772                 ret = false; \
11773         }
11774
11775 #define PIPE_CONF_CHECK_M_N(name) \
11776         if (!intel_compare_link_m_n(&current_config->name, \
11777                                     &pipe_config->name,\
11778                                     adjust)) { \
11779                 pipe_config_err(adjust, __stringify(name), \
11780                           "(expected tu %i gmch %i/%i link %i/%i, " \
11781                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11782                           current_config->name.tu, \
11783                           current_config->name.gmch_m, \
11784                           current_config->name.gmch_n, \
11785                           current_config->name.link_m, \
11786                           current_config->name.link_n, \
11787                           pipe_config->name.tu, \
11788                           pipe_config->name.gmch_m, \
11789                           pipe_config->name.gmch_n, \
11790                           pipe_config->name.link_m, \
11791                           pipe_config->name.link_n); \
11792                 ret = false; \
11793         }
11794
11795 /* This is required for BDW+ where there is only one set of registers for
11796  * switching between high and low RR.
11797  * This macro can be used whenever a comparison has to be made between one
11798  * hw state and multiple sw state variables.
11799  */
11800 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11801         if (!intel_compare_link_m_n(&current_config->name, \
11802                                     &pipe_config->name, adjust) && \
11803             !intel_compare_link_m_n(&current_config->alt_name, \
11804                                     &pipe_config->name, adjust)) { \
11805                 pipe_config_err(adjust, __stringify(name), \
11806                           "(expected tu %i gmch %i/%i link %i/%i, " \
11807                           "or tu %i gmch %i/%i link %i/%i, " \
11808                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11809                           current_config->name.tu, \
11810                           current_config->name.gmch_m, \
11811                           current_config->name.gmch_n, \
11812                           current_config->name.link_m, \
11813                           current_config->name.link_n, \
11814                           current_config->alt_name.tu, \
11815                           current_config->alt_name.gmch_m, \
11816                           current_config->alt_name.gmch_n, \
11817                           current_config->alt_name.link_m, \
11818                           current_config->alt_name.link_n, \
11819                           pipe_config->name.tu, \
11820                           pipe_config->name.gmch_m, \
11821                           pipe_config->name.gmch_n, \
11822                           pipe_config->name.link_m, \
11823                           pipe_config->name.link_n); \
11824                 ret = false; \
11825         }
11826
11827 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11828         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11829                 pipe_config_err(adjust, __stringify(name), \
11830                           "(%x) (expected %i, found %i)\n", \
11831                           (mask), \
11832                           current_config->name & (mask), \
11833                           pipe_config->name & (mask)); \
11834                 ret = false; \
11835         }
11836
11837 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11838         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11839                 pipe_config_err(adjust, __stringify(name), \
11840                           "(expected %i, found %i)\n", \
11841                           current_config->name, \
11842                           pipe_config->name); \
11843                 ret = false; \
11844         }
11845
11846 #define PIPE_CONF_QUIRK(quirk)  \
11847         ((current_config->quirks | pipe_config->quirks) & (quirk))
11848
11849         PIPE_CONF_CHECK_I(cpu_transcoder);
11850
11851         PIPE_CONF_CHECK_I(has_pch_encoder);
11852         PIPE_CONF_CHECK_I(fdi_lanes);
11853         PIPE_CONF_CHECK_M_N(fdi_m_n);
11854
11855         PIPE_CONF_CHECK_I(lane_count);
11856         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11857
11858         if (INTEL_GEN(dev_priv) < 8) {
11859                 PIPE_CONF_CHECK_M_N(dp_m_n);
11860
11861                 if (current_config->has_drrs)
11862                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11863         } else
11864                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11865
11866         PIPE_CONF_CHECK_X(output_types);
11867
11868         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11869         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11870         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11871         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11872         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11873         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11874
11875         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11876         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11877         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11878         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11879         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11880         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11881
11882         PIPE_CONF_CHECK_I(pixel_multiplier);
11883         PIPE_CONF_CHECK_I(has_hdmi_sink);
11884         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11885             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11886                 PIPE_CONF_CHECK_I(limited_color_range);
11887
11888         PIPE_CONF_CHECK_I(hdmi_scrambling);
11889         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11890         PIPE_CONF_CHECK_I(has_infoframe);
11891
11892         PIPE_CONF_CHECK_I(has_audio);
11893
11894         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11895                               DRM_MODE_FLAG_INTERLACE);
11896
11897         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11898                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11899                                       DRM_MODE_FLAG_PHSYNC);
11900                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11901                                       DRM_MODE_FLAG_NHSYNC);
11902                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11903                                       DRM_MODE_FLAG_PVSYNC);
11904                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11905                                       DRM_MODE_FLAG_NVSYNC);
11906         }
11907
11908         PIPE_CONF_CHECK_X(gmch_pfit.control);
11909         /* pfit ratios are autocomputed by the hw on gen4+ */
11910         if (INTEL_GEN(dev_priv) < 4)
11911                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11912         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11913
11914         if (!adjust) {
11915                 PIPE_CONF_CHECK_I(pipe_src_w);
11916                 PIPE_CONF_CHECK_I(pipe_src_h);
11917
11918                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11919                 if (current_config->pch_pfit.enabled) {
11920                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11921                         PIPE_CONF_CHECK_X(pch_pfit.size);
11922                 }
11923
11924                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11925                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11926         }
11927
11928         /* BDW+ don't expose a synchronous way to read the state */
11929         if (IS_HASWELL(dev_priv))
11930                 PIPE_CONF_CHECK_I(ips_enabled);
11931
11932         PIPE_CONF_CHECK_I(double_wide);
11933
11934         PIPE_CONF_CHECK_P(shared_dpll);
11935         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11936         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11937         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11938         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11939         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11940         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11941         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11942         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11943         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11944
11945         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11946         PIPE_CONF_CHECK_X(dsi_pll.div);
11947
11948         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11949                 PIPE_CONF_CHECK_I(pipe_bpp);
11950
11951         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11952         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11953
11954 #undef PIPE_CONF_CHECK_X
11955 #undef PIPE_CONF_CHECK_I
11956 #undef PIPE_CONF_CHECK_P
11957 #undef PIPE_CONF_CHECK_FLAGS
11958 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11959 #undef PIPE_CONF_QUIRK
11960
11961         return ret;
11962 }
11963
11964 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11965                                            const struct intel_crtc_state *pipe_config)
11966 {
11967         if (pipe_config->has_pch_encoder) {
11968                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11969                                                             &pipe_config->fdi_m_n);
11970                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11971
11972                 /*
11973                  * FDI already provided one idea for the dotclock.
11974                  * Yell if the encoder disagrees.
11975                  */
11976                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11977                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11978                      fdi_dotclock, dotclock);
11979         }
11980 }
11981
11982 static void verify_wm_state(struct drm_crtc *crtc,
11983                             struct drm_crtc_state *new_state)
11984 {
11985         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11986         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11987         struct skl_pipe_wm hw_wm, *sw_wm;
11988         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11989         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11991         const enum pipe pipe = intel_crtc->pipe;
11992         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11993
11994         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11995                 return;
11996
11997         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11998         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11999
12000         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12001         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12002
12003         /* planes */
12004         for_each_universal_plane(dev_priv, pipe, plane) {
12005                 hw_plane_wm = &hw_wm.planes[plane];
12006                 sw_plane_wm = &sw_wm->planes[plane];
12007
12008                 /* Watermarks */
12009                 for (level = 0; level <= max_level; level++) {
12010                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12011                                                 &sw_plane_wm->wm[level]))
12012                                 continue;
12013
12014                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12015                                   pipe_name(pipe), plane + 1, level,
12016                                   sw_plane_wm->wm[level].plane_en,
12017                                   sw_plane_wm->wm[level].plane_res_b,
12018                                   sw_plane_wm->wm[level].plane_res_l,
12019                                   hw_plane_wm->wm[level].plane_en,
12020                                   hw_plane_wm->wm[level].plane_res_b,
12021                                   hw_plane_wm->wm[level].plane_res_l);
12022                 }
12023
12024                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12025                                          &sw_plane_wm->trans_wm)) {
12026                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12027                                   pipe_name(pipe), plane + 1,
12028                                   sw_plane_wm->trans_wm.plane_en,
12029                                   sw_plane_wm->trans_wm.plane_res_b,
12030                                   sw_plane_wm->trans_wm.plane_res_l,
12031                                   hw_plane_wm->trans_wm.plane_en,
12032                                   hw_plane_wm->trans_wm.plane_res_b,
12033                                   hw_plane_wm->trans_wm.plane_res_l);
12034                 }
12035
12036                 /* DDB */
12037                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
12038                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
12039
12040                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12041                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12042                                   pipe_name(pipe), plane + 1,
12043                                   sw_ddb_entry->start, sw_ddb_entry->end,
12044                                   hw_ddb_entry->start, hw_ddb_entry->end);
12045                 }
12046         }
12047
12048         /*
12049          * cursor
12050          * If the cursor plane isn't active, we may not have updated it's ddb
12051          * allocation. In that case since the ddb allocation will be updated
12052          * once the plane becomes visible, we can skip this check
12053          */
12054         if (1) {
12055                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
12056                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12057
12058                 /* Watermarks */
12059                 for (level = 0; level <= max_level; level++) {
12060                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12061                                                 &sw_plane_wm->wm[level]))
12062                                 continue;
12063
12064                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12065                                   pipe_name(pipe), level,
12066                                   sw_plane_wm->wm[level].plane_en,
12067                                   sw_plane_wm->wm[level].plane_res_b,
12068                                   sw_plane_wm->wm[level].plane_res_l,
12069                                   hw_plane_wm->wm[level].plane_en,
12070                                   hw_plane_wm->wm[level].plane_res_b,
12071                                   hw_plane_wm->wm[level].plane_res_l);
12072                 }
12073
12074                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12075                                          &sw_plane_wm->trans_wm)) {
12076                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12077                                   pipe_name(pipe),
12078                                   sw_plane_wm->trans_wm.plane_en,
12079                                   sw_plane_wm->trans_wm.plane_res_b,
12080                                   sw_plane_wm->trans_wm.plane_res_l,
12081                                   hw_plane_wm->trans_wm.plane_en,
12082                                   hw_plane_wm->trans_wm.plane_res_b,
12083                                   hw_plane_wm->trans_wm.plane_res_l);
12084                 }
12085
12086                 /* DDB */
12087                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12088                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12089
12090                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12091                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12092                                   pipe_name(pipe),
12093                                   sw_ddb_entry->start, sw_ddb_entry->end,
12094                                   hw_ddb_entry->start, hw_ddb_entry->end);
12095                 }
12096         }
12097 }
12098
12099 static void
12100 verify_connector_state(struct drm_device *dev,
12101                        struct drm_atomic_state *state,
12102                        struct drm_crtc *crtc)
12103 {
12104         struct drm_connector *connector;
12105         struct drm_connector_state *new_conn_state;
12106         int i;
12107
12108         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12109                 struct drm_encoder *encoder = connector->encoder;
12110                 struct drm_crtc_state *crtc_state = NULL;
12111
12112                 if (new_conn_state->crtc != crtc)
12113                         continue;
12114
12115                 if (crtc)
12116                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12117
12118                 intel_connector_verify_state(crtc_state, new_conn_state);
12119
12120                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12121                      "connector's atomic encoder doesn't match legacy encoder\n");
12122         }
12123 }
12124
12125 static void
12126 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12127 {
12128         struct intel_encoder *encoder;
12129         struct drm_connector *connector;
12130         struct drm_connector_state *old_conn_state, *new_conn_state;
12131         int i;
12132
12133         for_each_intel_encoder(dev, encoder) {
12134                 bool enabled = false, found = false;
12135                 enum pipe pipe;
12136
12137                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12138                               encoder->base.base.id,
12139                               encoder->base.name);
12140
12141                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12142                                                    new_conn_state, i) {
12143                         if (old_conn_state->best_encoder == &encoder->base)
12144                                 found = true;
12145
12146                         if (new_conn_state->best_encoder != &encoder->base)
12147                                 continue;
12148                         found = enabled = true;
12149
12150                         I915_STATE_WARN(new_conn_state->crtc !=
12151                                         encoder->base.crtc,
12152                              "connector's crtc doesn't match encoder crtc\n");
12153                 }
12154
12155                 if (!found)
12156                         continue;
12157
12158                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12159                      "encoder's enabled state mismatch "
12160                      "(expected %i, found %i)\n",
12161                      !!encoder->base.crtc, enabled);
12162
12163                 if (!encoder->base.crtc) {
12164                         bool active;
12165
12166                         active = encoder->get_hw_state(encoder, &pipe);
12167                         I915_STATE_WARN(active,
12168                              "encoder detached but still enabled on pipe %c.\n",
12169                              pipe_name(pipe));
12170                 }
12171         }
12172 }
12173
12174 static void
12175 verify_crtc_state(struct drm_crtc *crtc,
12176                   struct drm_crtc_state *old_crtc_state,
12177                   struct drm_crtc_state *new_crtc_state)
12178 {
12179         struct drm_device *dev = crtc->dev;
12180         struct drm_i915_private *dev_priv = to_i915(dev);
12181         struct intel_encoder *encoder;
12182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12183         struct intel_crtc_state *pipe_config, *sw_config;
12184         struct drm_atomic_state *old_state;
12185         bool active;
12186
12187         old_state = old_crtc_state->state;
12188         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12189         pipe_config = to_intel_crtc_state(old_crtc_state);
12190         memset(pipe_config, 0, sizeof(*pipe_config));
12191         pipe_config->base.crtc = crtc;
12192         pipe_config->base.state = old_state;
12193
12194         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12195
12196         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12197
12198         /* hw state is inconsistent with the pipe quirk */
12199         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12200             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12201                 active = new_crtc_state->active;
12202
12203         I915_STATE_WARN(new_crtc_state->active != active,
12204              "crtc active state doesn't match with hw state "
12205              "(expected %i, found %i)\n", new_crtc_state->active, active);
12206
12207         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12208              "transitional active state does not match atomic hw state "
12209              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12210
12211         for_each_encoder_on_crtc(dev, crtc, encoder) {
12212                 enum pipe pipe;
12213
12214                 active = encoder->get_hw_state(encoder, &pipe);
12215                 I915_STATE_WARN(active != new_crtc_state->active,
12216                         "[ENCODER:%i] active %i with crtc active %i\n",
12217                         encoder->base.base.id, active, new_crtc_state->active);
12218
12219                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12220                                 "Encoder connected to wrong pipe %c\n",
12221                                 pipe_name(pipe));
12222
12223                 if (active) {
12224                         pipe_config->output_types |= 1 << encoder->type;
12225                         encoder->get_config(encoder, pipe_config);
12226                 }
12227         }
12228
12229         intel_crtc_compute_pixel_rate(pipe_config);
12230
12231         if (!new_crtc_state->active)
12232                 return;
12233
12234         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12235
12236         sw_config = to_intel_crtc_state(new_crtc_state);
12237         if (!intel_pipe_config_compare(dev_priv, sw_config,
12238                                        pipe_config, false)) {
12239                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12240                 intel_dump_pipe_config(intel_crtc, pipe_config,
12241                                        "[hw state]");
12242                 intel_dump_pipe_config(intel_crtc, sw_config,
12243                                        "[sw state]");
12244         }
12245 }
12246
12247 static void
12248 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12249                          struct intel_shared_dpll *pll,
12250                          struct drm_crtc *crtc,
12251                          struct drm_crtc_state *new_state)
12252 {
12253         struct intel_dpll_hw_state dpll_hw_state;
12254         unsigned crtc_mask;
12255         bool active;
12256
12257         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12258
12259         DRM_DEBUG_KMS("%s\n", pll->name);
12260
12261         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12262
12263         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12264                 I915_STATE_WARN(!pll->on && pll->active_mask,
12265                      "pll in active use but not on in sw tracking\n");
12266                 I915_STATE_WARN(pll->on && !pll->active_mask,
12267                      "pll is on but not used by any active crtc\n");
12268                 I915_STATE_WARN(pll->on != active,
12269                      "pll on state mismatch (expected %i, found %i)\n",
12270                      pll->on, active);
12271         }
12272
12273         if (!crtc) {
12274                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12275                                 "more active pll users than references: %x vs %x\n",
12276                                 pll->active_mask, pll->state.crtc_mask);
12277
12278                 return;
12279         }
12280
12281         crtc_mask = 1 << drm_crtc_index(crtc);
12282
12283         if (new_state->active)
12284                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12285                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12286                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12287         else
12288                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12289                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12290                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12291
12292         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12293                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12294                         crtc_mask, pll->state.crtc_mask);
12295
12296         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12297                                           &dpll_hw_state,
12298                                           sizeof(dpll_hw_state)),
12299                         "pll hw state mismatch\n");
12300 }
12301
12302 static void
12303 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12304                          struct drm_crtc_state *old_crtc_state,
12305                          struct drm_crtc_state *new_crtc_state)
12306 {
12307         struct drm_i915_private *dev_priv = to_i915(dev);
12308         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12309         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12310
12311         if (new_state->shared_dpll)
12312                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12313
12314         if (old_state->shared_dpll &&
12315             old_state->shared_dpll != new_state->shared_dpll) {
12316                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12317                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12318
12319                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12320                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12321                                 pipe_name(drm_crtc_index(crtc)));
12322                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12323                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12324                                 pipe_name(drm_crtc_index(crtc)));
12325         }
12326 }
12327
12328 static void
12329 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12330                           struct drm_atomic_state *state,
12331                           struct drm_crtc_state *old_state,
12332                           struct drm_crtc_state *new_state)
12333 {
12334         if (!needs_modeset(new_state) &&
12335             !to_intel_crtc_state(new_state)->update_pipe)
12336                 return;
12337
12338         verify_wm_state(crtc, new_state);
12339         verify_connector_state(crtc->dev, state, crtc);
12340         verify_crtc_state(crtc, old_state, new_state);
12341         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12342 }
12343
12344 static void
12345 verify_disabled_dpll_state(struct drm_device *dev)
12346 {
12347         struct drm_i915_private *dev_priv = to_i915(dev);
12348         int i;
12349
12350         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12351                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12352 }
12353
12354 static void
12355 intel_modeset_verify_disabled(struct drm_device *dev,
12356                               struct drm_atomic_state *state)
12357 {
12358         verify_encoder_state(dev, state);
12359         verify_connector_state(dev, state, NULL);
12360         verify_disabled_dpll_state(dev);
12361 }
12362
12363 static void update_scanline_offset(struct intel_crtc *crtc)
12364 {
12365         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12366
12367         /*
12368          * The scanline counter increments at the leading edge of hsync.
12369          *
12370          * On most platforms it starts counting from vtotal-1 on the
12371          * first active line. That means the scanline counter value is
12372          * always one less than what we would expect. Ie. just after
12373          * start of vblank, which also occurs at start of hsync (on the
12374          * last active line), the scanline counter will read vblank_start-1.
12375          *
12376          * On gen2 the scanline counter starts counting from 1 instead
12377          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12378          * to keep the value positive), instead of adding one.
12379          *
12380          * On HSW+ the behaviour of the scanline counter depends on the output
12381          * type. For DP ports it behaves like most other platforms, but on HDMI
12382          * there's an extra 1 line difference. So we need to add two instead of
12383          * one to the value.
12384          */
12385         if (IS_GEN2(dev_priv)) {
12386                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12387                 int vtotal;
12388
12389                 vtotal = adjusted_mode->crtc_vtotal;
12390                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12391                         vtotal /= 2;
12392
12393                 crtc->scanline_offset = vtotal - 1;
12394         } else if (HAS_DDI(dev_priv) &&
12395                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12396                 crtc->scanline_offset = 2;
12397         } else
12398                 crtc->scanline_offset = 1;
12399 }
12400
12401 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12402 {
12403         struct drm_device *dev = state->dev;
12404         struct drm_i915_private *dev_priv = to_i915(dev);
12405         struct drm_crtc *crtc;
12406         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12407         int i;
12408
12409         if (!dev_priv->display.crtc_compute_clock)
12410                 return;
12411
12412         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12413                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12414                 struct intel_shared_dpll *old_dpll =
12415                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12416
12417                 if (!needs_modeset(new_crtc_state))
12418                         continue;
12419
12420                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12421
12422                 if (!old_dpll)
12423                         continue;
12424
12425                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12426         }
12427 }
12428
12429 /*
12430  * This implements the workaround described in the "notes" section of the mode
12431  * set sequence documentation. When going from no pipes or single pipe to
12432  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12433  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12434  */
12435 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12436 {
12437         struct drm_crtc_state *crtc_state;
12438         struct intel_crtc *intel_crtc;
12439         struct drm_crtc *crtc;
12440         struct intel_crtc_state *first_crtc_state = NULL;
12441         struct intel_crtc_state *other_crtc_state = NULL;
12442         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12443         int i;
12444
12445         /* look at all crtc's that are going to be enabled in during modeset */
12446         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12447                 intel_crtc = to_intel_crtc(crtc);
12448
12449                 if (!crtc_state->active || !needs_modeset(crtc_state))
12450                         continue;
12451
12452                 if (first_crtc_state) {
12453                         other_crtc_state = to_intel_crtc_state(crtc_state);
12454                         break;
12455                 } else {
12456                         first_crtc_state = to_intel_crtc_state(crtc_state);
12457                         first_pipe = intel_crtc->pipe;
12458                 }
12459         }
12460
12461         /* No workaround needed? */
12462         if (!first_crtc_state)
12463                 return 0;
12464
12465         /* w/a possibly needed, check how many crtc's are already enabled. */
12466         for_each_intel_crtc(state->dev, intel_crtc) {
12467                 struct intel_crtc_state *pipe_config;
12468
12469                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12470                 if (IS_ERR(pipe_config))
12471                         return PTR_ERR(pipe_config);
12472
12473                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12474
12475                 if (!pipe_config->base.active ||
12476                     needs_modeset(&pipe_config->base))
12477                         continue;
12478
12479                 /* 2 or more enabled crtcs means no need for w/a */
12480                 if (enabled_pipe != INVALID_PIPE)
12481                         return 0;
12482
12483                 enabled_pipe = intel_crtc->pipe;
12484         }
12485
12486         if (enabled_pipe != INVALID_PIPE)
12487                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12488         else if (other_crtc_state)
12489                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12490
12491         return 0;
12492 }
12493
12494 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12495 {
12496         struct drm_crtc *crtc;
12497
12498         /* Add all pipes to the state */
12499         for_each_crtc(state->dev, crtc) {
12500                 struct drm_crtc_state *crtc_state;
12501
12502                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12503                 if (IS_ERR(crtc_state))
12504                         return PTR_ERR(crtc_state);
12505         }
12506
12507         return 0;
12508 }
12509
12510 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12511 {
12512         struct drm_crtc *crtc;
12513
12514         /*
12515          * Add all pipes to the state, and force
12516          * a modeset on all the active ones.
12517          */
12518         for_each_crtc(state->dev, crtc) {
12519                 struct drm_crtc_state *crtc_state;
12520                 int ret;
12521
12522                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12523                 if (IS_ERR(crtc_state))
12524                         return PTR_ERR(crtc_state);
12525
12526                 if (!crtc_state->active || needs_modeset(crtc_state))
12527                         continue;
12528
12529                 crtc_state->mode_changed = true;
12530
12531                 ret = drm_atomic_add_affected_connectors(state, crtc);
12532                 if (ret)
12533                         return ret;
12534
12535                 ret = drm_atomic_add_affected_planes(state, crtc);
12536                 if (ret)
12537                         return ret;
12538         }
12539
12540         return 0;
12541 }
12542
12543 static int intel_modeset_checks(struct drm_atomic_state *state)
12544 {
12545         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12546         struct drm_i915_private *dev_priv = to_i915(state->dev);
12547         struct drm_crtc *crtc;
12548         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12549         int ret = 0, i;
12550
12551         if (!check_digital_port_conflicts(state)) {
12552                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12553                 return -EINVAL;
12554         }
12555
12556         intel_state->modeset = true;
12557         intel_state->active_crtcs = dev_priv->active_crtcs;
12558         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12559         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12560
12561         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12562                 if (new_crtc_state->active)
12563                         intel_state->active_crtcs |= 1 << i;
12564                 else
12565                         intel_state->active_crtcs &= ~(1 << i);
12566
12567                 if (old_crtc_state->active != new_crtc_state->active)
12568                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12569         }
12570
12571         /*
12572          * See if the config requires any additional preparation, e.g.
12573          * to adjust global state with pipes off.  We need to do this
12574          * here so we can get the modeset_pipe updated config for the new
12575          * mode set on this crtc.  For other crtcs we need to use the
12576          * adjusted_mode bits in the crtc directly.
12577          */
12578         if (dev_priv->display.modeset_calc_cdclk) {
12579                 ret = dev_priv->display.modeset_calc_cdclk(state);
12580                 if (ret < 0)
12581                         return ret;
12582
12583                 /*
12584                  * Writes to dev_priv->cdclk.logical must protected by
12585                  * holding all the crtc locks, even if we don't end up
12586                  * touching the hardware
12587                  */
12588                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12589                                                &intel_state->cdclk.logical)) {
12590                         ret = intel_lock_all_pipes(state);
12591                         if (ret < 0)
12592                                 return ret;
12593                 }
12594
12595                 /* All pipes must be switched off while we change the cdclk. */
12596                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12597                                                &intel_state->cdclk.actual)) {
12598                         ret = intel_modeset_all_pipes(state);
12599                         if (ret < 0)
12600                                 return ret;
12601                 }
12602
12603                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12604                               intel_state->cdclk.logical.cdclk,
12605                               intel_state->cdclk.actual.cdclk);
12606         } else {
12607                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12608         }
12609
12610         intel_modeset_clear_plls(state);
12611
12612         if (IS_HASWELL(dev_priv))
12613                 return haswell_mode_set_planes_workaround(state);
12614
12615         return 0;
12616 }
12617
12618 /*
12619  * Handle calculation of various watermark data at the end of the atomic check
12620  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12621  * handlers to ensure that all derived state has been updated.
12622  */
12623 static int calc_watermark_data(struct drm_atomic_state *state)
12624 {
12625         struct drm_device *dev = state->dev;
12626         struct drm_i915_private *dev_priv = to_i915(dev);
12627
12628         /* Is there platform-specific watermark information to calculate? */
12629         if (dev_priv->display.compute_global_watermarks)
12630                 return dev_priv->display.compute_global_watermarks(state);
12631
12632         return 0;
12633 }
12634
12635 /**
12636  * intel_atomic_check - validate state object
12637  * @dev: drm device
12638  * @state: state to validate
12639  */
12640 static int intel_atomic_check(struct drm_device *dev,
12641                               struct drm_atomic_state *state)
12642 {
12643         struct drm_i915_private *dev_priv = to_i915(dev);
12644         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12645         struct drm_crtc *crtc;
12646         struct drm_crtc_state *old_crtc_state, *crtc_state;
12647         int ret, i;
12648         bool any_ms = false;
12649
12650         ret = drm_atomic_helper_check_modeset(dev, state);
12651         if (ret)
12652                 return ret;
12653
12654         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12655                 struct intel_crtc_state *pipe_config =
12656                         to_intel_crtc_state(crtc_state);
12657
12658                 /* Catch I915_MODE_FLAG_INHERITED */
12659                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12660                         crtc_state->mode_changed = true;
12661
12662                 if (!needs_modeset(crtc_state))
12663                         continue;
12664
12665                 if (!crtc_state->enable) {
12666                         any_ms = true;
12667                         continue;
12668                 }
12669
12670                 /* FIXME: For only active_changed we shouldn't need to do any
12671                  * state recomputation at all. */
12672
12673                 ret = drm_atomic_add_affected_connectors(state, crtc);
12674                 if (ret)
12675                         return ret;
12676
12677                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12678                 if (ret) {
12679                         intel_dump_pipe_config(to_intel_crtc(crtc),
12680                                                pipe_config, "[failed]");
12681                         return ret;
12682                 }
12683
12684                 if (i915.fastboot &&
12685                     intel_pipe_config_compare(dev_priv,
12686                                         to_intel_crtc_state(old_crtc_state),
12687                                         pipe_config, true)) {
12688                         crtc_state->mode_changed = false;
12689                         pipe_config->update_pipe = true;
12690                 }
12691
12692                 if (needs_modeset(crtc_state))
12693                         any_ms = true;
12694
12695                 ret = drm_atomic_add_affected_planes(state, crtc);
12696                 if (ret)
12697                         return ret;
12698
12699                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12700                                        needs_modeset(crtc_state) ?
12701                                        "[modeset]" : "[fastset]");
12702         }
12703
12704         if (any_ms) {
12705                 ret = intel_modeset_checks(state);
12706
12707                 if (ret)
12708                         return ret;
12709         } else {
12710                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12711         }
12712
12713         ret = drm_atomic_helper_check_planes(dev, state);
12714         if (ret)
12715                 return ret;
12716
12717         intel_fbc_choose_crtc(dev_priv, state);
12718         return calc_watermark_data(state);
12719 }
12720
12721 static int intel_atomic_prepare_commit(struct drm_device *dev,
12722                                        struct drm_atomic_state *state)
12723 {
12724         struct drm_i915_private *dev_priv = to_i915(dev);
12725         struct drm_crtc_state *crtc_state;
12726         struct drm_crtc *crtc;
12727         int i, ret;
12728
12729         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12730                 if (state->legacy_cursor_update)
12731                         continue;
12732
12733                 ret = intel_crtc_wait_for_pending_flips(crtc);
12734                 if (ret)
12735                         return ret;
12736
12737                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12738                         flush_workqueue(dev_priv->wq);
12739         }
12740
12741         ret = mutex_lock_interruptible(&dev->struct_mutex);
12742         if (ret)
12743                 return ret;
12744
12745         ret = drm_atomic_helper_prepare_planes(dev, state);
12746         mutex_unlock(&dev->struct_mutex);
12747
12748         return ret;
12749 }
12750
12751 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12752 {
12753         struct drm_device *dev = crtc->base.dev;
12754
12755         if (!dev->max_vblank_count)
12756                 return drm_accurate_vblank_count(&crtc->base);
12757
12758         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12759 }
12760
12761 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12762                                           struct drm_i915_private *dev_priv,
12763                                           unsigned crtc_mask)
12764 {
12765         unsigned last_vblank_count[I915_MAX_PIPES];
12766         enum pipe pipe;
12767         int ret;
12768
12769         if (!crtc_mask)
12770                 return;
12771
12772         for_each_pipe(dev_priv, pipe) {
12773                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12774                                                                   pipe);
12775
12776                 if (!((1 << pipe) & crtc_mask))
12777                         continue;
12778
12779                 ret = drm_crtc_vblank_get(&crtc->base);
12780                 if (WARN_ON(ret != 0)) {
12781                         crtc_mask &= ~(1 << pipe);
12782                         continue;
12783                 }
12784
12785                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12786         }
12787
12788         for_each_pipe(dev_priv, pipe) {
12789                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12790                                                                   pipe);
12791                 long lret;
12792
12793                 if (!((1 << pipe) & crtc_mask))
12794                         continue;
12795
12796                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12797                                 last_vblank_count[pipe] !=
12798                                         drm_crtc_vblank_count(&crtc->base),
12799                                 msecs_to_jiffies(50));
12800
12801                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12802
12803                 drm_crtc_vblank_put(&crtc->base);
12804         }
12805 }
12806
12807 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12808 {
12809         /* fb updated, need to unpin old fb */
12810         if (crtc_state->fb_changed)
12811                 return true;
12812
12813         /* wm changes, need vblank before final wm's */
12814         if (crtc_state->update_wm_post)
12815                 return true;
12816
12817         if (crtc_state->wm.need_postvbl_update)
12818                 return true;
12819
12820         return false;
12821 }
12822
12823 static void intel_update_crtc(struct drm_crtc *crtc,
12824                               struct drm_atomic_state *state,
12825                               struct drm_crtc_state *old_crtc_state,
12826                               struct drm_crtc_state *new_crtc_state,
12827                               unsigned int *crtc_vblank_mask)
12828 {
12829         struct drm_device *dev = crtc->dev;
12830         struct drm_i915_private *dev_priv = to_i915(dev);
12831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12832         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12833         bool modeset = needs_modeset(new_crtc_state);
12834
12835         if (modeset) {
12836                 update_scanline_offset(intel_crtc);
12837                 dev_priv->display.crtc_enable(pipe_config, state);
12838         } else {
12839                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12840                                        pipe_config);
12841         }
12842
12843         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12844                 intel_fbc_enable(
12845                     intel_crtc, pipe_config,
12846                     to_intel_plane_state(crtc->primary->state));
12847         }
12848
12849         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12850
12851         if (needs_vblank_wait(pipe_config))
12852                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12853 }
12854
12855 static void intel_update_crtcs(struct drm_atomic_state *state,
12856                                unsigned int *crtc_vblank_mask)
12857 {
12858         struct drm_crtc *crtc;
12859         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12860         int i;
12861
12862         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12863                 if (!new_crtc_state->active)
12864                         continue;
12865
12866                 intel_update_crtc(crtc, state, old_crtc_state,
12867                                   new_crtc_state, crtc_vblank_mask);
12868         }
12869 }
12870
12871 static void skl_update_crtcs(struct drm_atomic_state *state,
12872                              unsigned int *crtc_vblank_mask)
12873 {
12874         struct drm_i915_private *dev_priv = to_i915(state->dev);
12875         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12876         struct drm_crtc *crtc;
12877         struct intel_crtc *intel_crtc;
12878         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12879         struct intel_crtc_state *cstate;
12880         unsigned int updated = 0;
12881         bool progress;
12882         enum pipe pipe;
12883         int i;
12884
12885         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12886
12887         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12888                 /* ignore allocations for crtc's that have been turned off. */
12889                 if (new_crtc_state->active)
12890                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12891
12892         /*
12893          * Whenever the number of active pipes changes, we need to make sure we
12894          * update the pipes in the right order so that their ddb allocations
12895          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12896          * cause pipe underruns and other bad stuff.
12897          */
12898         do {
12899                 progress = false;
12900
12901                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12902                         bool vbl_wait = false;
12903                         unsigned int cmask = drm_crtc_mask(crtc);
12904
12905                         intel_crtc = to_intel_crtc(crtc);
12906                         cstate = to_intel_crtc_state(crtc->state);
12907                         pipe = intel_crtc->pipe;
12908
12909                         if (updated & cmask || !cstate->base.active)
12910                                 continue;
12911
12912                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12913                                 continue;
12914
12915                         updated |= cmask;
12916                         entries[i] = &cstate->wm.skl.ddb;
12917
12918                         /*
12919                          * If this is an already active pipe, it's DDB changed,
12920                          * and this isn't the last pipe that needs updating
12921                          * then we need to wait for a vblank to pass for the
12922                          * new ddb allocation to take effect.
12923                          */
12924                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12925                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12926                             !new_crtc_state->active_changed &&
12927                             intel_state->wm_results.dirty_pipes != updated)
12928                                 vbl_wait = true;
12929
12930                         intel_update_crtc(crtc, state, old_crtc_state,
12931                                           new_crtc_state, crtc_vblank_mask);
12932
12933                         if (vbl_wait)
12934                                 intel_wait_for_vblank(dev_priv, pipe);
12935
12936                         progress = true;
12937                 }
12938         } while (progress);
12939 }
12940
12941 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12942 {
12943         struct intel_atomic_state *state, *next;
12944         struct llist_node *freed;
12945
12946         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12947         llist_for_each_entry_safe(state, next, freed, freed)
12948                 drm_atomic_state_put(&state->base);
12949 }
12950
12951 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12952 {
12953         struct drm_i915_private *dev_priv =
12954                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12955
12956         intel_atomic_helper_free_state(dev_priv);
12957 }
12958
12959 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12960 {
12961         struct drm_device *dev = state->dev;
12962         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12963         struct drm_i915_private *dev_priv = to_i915(dev);
12964         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12965         struct drm_crtc *crtc;
12966         struct intel_crtc_state *intel_cstate;
12967         bool hw_check = intel_state->modeset;
12968         u64 put_domains[I915_MAX_PIPES] = {};
12969         unsigned crtc_vblank_mask = 0;
12970         int i;
12971
12972         drm_atomic_helper_wait_for_dependencies(state);
12973
12974         if (intel_state->modeset)
12975                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12976
12977         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12978                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12979
12980                 if (needs_modeset(new_crtc_state) ||
12981                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12982                         hw_check = true;
12983
12984                         put_domains[to_intel_crtc(crtc)->pipe] =
12985                                 modeset_get_crtc_power_domains(crtc,
12986                                         to_intel_crtc_state(new_crtc_state));
12987                 }
12988
12989                 if (!needs_modeset(new_crtc_state))
12990                         continue;
12991
12992                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12993                                        to_intel_crtc_state(new_crtc_state));
12994
12995                 if (old_crtc_state->active) {
12996                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12997                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12998                         intel_crtc->active = false;
12999                         intel_fbc_disable(intel_crtc);
13000                         intel_disable_shared_dpll(intel_crtc);
13001
13002                         /*
13003                          * Underruns don't always raise
13004                          * interrupts, so check manually.
13005                          */
13006                         intel_check_cpu_fifo_underruns(dev_priv);
13007                         intel_check_pch_fifo_underruns(dev_priv);
13008
13009                         if (!crtc->state->active) {
13010                                 /*
13011                                  * Make sure we don't call initial_watermarks
13012                                  * for ILK-style watermark updates.
13013                                  *
13014                                  * No clue what this is supposed to achieve.
13015                                  */
13016                                 if (INTEL_GEN(dev_priv) >= 9)
13017                                         dev_priv->display.initial_watermarks(intel_state,
13018                                                                              to_intel_crtc_state(crtc->state));
13019                         }
13020                 }
13021         }
13022
13023         /* Only after disabling all output pipelines that will be changed can we
13024          * update the the output configuration. */
13025         intel_modeset_update_crtc_state(state);
13026
13027         if (intel_state->modeset) {
13028                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13029
13030                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13031
13032                 /*
13033                  * SKL workaround: bspec recommends we disable the SAGV when we
13034                  * have more then one pipe enabled
13035                  */
13036                 if (!intel_can_enable_sagv(state))
13037                         intel_disable_sagv(dev_priv);
13038
13039                 intel_modeset_verify_disabled(dev, state);
13040         }
13041
13042         /* Complete the events for pipes that have now been disabled */
13043         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13044                 bool modeset = needs_modeset(new_crtc_state);
13045
13046                 /* Complete events for now disable pipes here. */
13047                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13048                         spin_lock_irq(&dev->event_lock);
13049                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13050                         spin_unlock_irq(&dev->event_lock);
13051
13052                         new_crtc_state->event = NULL;
13053                 }
13054         }
13055
13056         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13057         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
13058
13059         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13060          * already, but still need the state for the delayed optimization. To
13061          * fix this:
13062          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13063          * - schedule that vblank worker _before_ calling hw_done
13064          * - at the start of commit_tail, cancel it _synchrously
13065          * - switch over to the vblank wait helper in the core after that since
13066          *   we don't need out special handling any more.
13067          */
13068         if (!state->legacy_cursor_update)
13069                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13070
13071         /*
13072          * Now that the vblank has passed, we can go ahead and program the
13073          * optimal watermarks on platforms that need two-step watermark
13074          * programming.
13075          *
13076          * TODO: Move this (and other cleanup) to an async worker eventually.
13077          */
13078         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13079                 intel_cstate = to_intel_crtc_state(new_crtc_state);
13080
13081                 if (dev_priv->display.optimize_watermarks)
13082                         dev_priv->display.optimize_watermarks(intel_state,
13083                                                               intel_cstate);
13084         }
13085
13086         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13087                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13088
13089                 if (put_domains[i])
13090                         modeset_put_power_domains(dev_priv, put_domains[i]);
13091
13092                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13093         }
13094
13095         if (intel_state->modeset && intel_can_enable_sagv(state))
13096                 intel_enable_sagv(dev_priv);
13097
13098         drm_atomic_helper_commit_hw_done(state);
13099
13100         if (intel_state->modeset)
13101                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13102
13103         mutex_lock(&dev->struct_mutex);
13104         drm_atomic_helper_cleanup_planes(dev, state);
13105         mutex_unlock(&dev->struct_mutex);
13106
13107         drm_atomic_helper_commit_cleanup_done(state);
13108
13109         drm_atomic_state_put(state);
13110
13111         /* As one of the primary mmio accessors, KMS has a high likelihood
13112          * of triggering bugs in unclaimed access. After we finish
13113          * modesetting, see if an error has been flagged, and if so
13114          * enable debugging for the next modeset - and hope we catch
13115          * the culprit.
13116          *
13117          * XXX note that we assume display power is on at this point.
13118          * This might hold true now but we need to add pm helper to check
13119          * unclaimed only when the hardware is on, as atomic commits
13120          * can happen also when the device is completely off.
13121          */
13122         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13123
13124         intel_atomic_helper_free_state(dev_priv);
13125 }
13126
13127 static void intel_atomic_commit_work(struct work_struct *work)
13128 {
13129         struct drm_atomic_state *state =
13130                 container_of(work, struct drm_atomic_state, commit_work);
13131
13132         intel_atomic_commit_tail(state);
13133 }
13134
13135 static int __i915_sw_fence_call
13136 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13137                           enum i915_sw_fence_notify notify)
13138 {
13139         struct intel_atomic_state *state =
13140                 container_of(fence, struct intel_atomic_state, commit_ready);
13141
13142         switch (notify) {
13143         case FENCE_COMPLETE:
13144                 if (state->base.commit_work.func)
13145                         queue_work(system_unbound_wq, &state->base.commit_work);
13146                 break;
13147
13148         case FENCE_FREE:
13149                 {
13150                         struct intel_atomic_helper *helper =
13151                                 &to_i915(state->base.dev)->atomic_helper;
13152
13153                         if (llist_add(&state->freed, &helper->free_list))
13154                                 schedule_work(&helper->free_work);
13155                         break;
13156                 }
13157         }
13158
13159         return NOTIFY_DONE;
13160 }
13161
13162 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13163 {
13164         struct drm_plane_state *old_plane_state, *new_plane_state;
13165         struct drm_plane *plane;
13166         int i;
13167
13168         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13169                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13170                                   intel_fb_obj(new_plane_state->fb),
13171                                   to_intel_plane(plane)->frontbuffer_bit);
13172 }
13173
13174 /**
13175  * intel_atomic_commit - commit validated state object
13176  * @dev: DRM device
13177  * @state: the top-level driver state object
13178  * @nonblock: nonblocking commit
13179  *
13180  * This function commits a top-level state object that has been validated
13181  * with drm_atomic_helper_check().
13182  *
13183  * RETURNS
13184  * Zero for success or -errno.
13185  */
13186 static int intel_atomic_commit(struct drm_device *dev,
13187                                struct drm_atomic_state *state,
13188                                bool nonblock)
13189 {
13190         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13191         struct drm_i915_private *dev_priv = to_i915(dev);
13192         int ret = 0;
13193
13194         ret = drm_atomic_helper_setup_commit(state, nonblock);
13195         if (ret)
13196                 return ret;
13197
13198         drm_atomic_state_get(state);
13199         i915_sw_fence_init(&intel_state->commit_ready,
13200                            intel_atomic_commit_ready);
13201
13202         ret = intel_atomic_prepare_commit(dev, state);
13203         if (ret) {
13204                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13205                 i915_sw_fence_commit(&intel_state->commit_ready);
13206                 return ret;
13207         }
13208
13209         /*
13210          * The intel_legacy_cursor_update() fast path takes care
13211          * of avoiding the vblank waits for simple cursor
13212          * movement and flips. For cursor on/off and size changes,
13213          * we want to perform the vblank waits so that watermark
13214          * updates happen during the correct frames. Gen9+ have
13215          * double buffered watermarks and so shouldn't need this.
13216          *
13217          * Do this after drm_atomic_helper_setup_commit() and
13218          * intel_atomic_prepare_commit() because we still want
13219          * to skip the flip and fb cleanup waits. Although that
13220          * does risk yanking the mapping from under the display
13221          * engine.
13222          *
13223          * FIXME doing watermarks and fb cleanup from a vblank worker
13224          * (assuming we had any) would solve these problems.
13225          */
13226         if (INTEL_GEN(dev_priv) < 9)
13227                 state->legacy_cursor_update = false;
13228
13229         drm_atomic_helper_swap_state(state, true);
13230         dev_priv->wm.distrust_bios_wm = false;
13231         intel_shared_dpll_swap_state(state);
13232         intel_atomic_track_fbs(state);
13233
13234         if (intel_state->modeset) {
13235                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13236                        sizeof(intel_state->min_pixclk));
13237                 dev_priv->active_crtcs = intel_state->active_crtcs;
13238                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13239                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13240         }
13241
13242         drm_atomic_state_get(state);
13243         INIT_WORK(&state->commit_work,
13244                   nonblock ? intel_atomic_commit_work : NULL);
13245
13246         i915_sw_fence_commit(&intel_state->commit_ready);
13247         if (!nonblock) {
13248                 i915_sw_fence_wait(&intel_state->commit_ready);
13249                 intel_atomic_commit_tail(state);
13250         }
13251
13252         return 0;
13253 }
13254
13255 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13256 {
13257         struct drm_device *dev = crtc->dev;
13258         struct drm_atomic_state *state;
13259         struct drm_crtc_state *crtc_state;
13260         int ret;
13261
13262         state = drm_atomic_state_alloc(dev);
13263         if (!state) {
13264                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13265                               crtc->base.id, crtc->name);
13266                 return;
13267         }
13268
13269         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
13270
13271 retry:
13272         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13273         ret = PTR_ERR_OR_ZERO(crtc_state);
13274         if (!ret) {
13275                 if (!crtc_state->active)
13276                         goto out;
13277
13278                 crtc_state->mode_changed = true;
13279                 ret = drm_atomic_commit(state);
13280         }
13281
13282         if (ret == -EDEADLK) {
13283                 drm_atomic_state_clear(state);
13284                 drm_modeset_backoff(state->acquire_ctx);
13285                 goto retry;
13286         }
13287
13288 out:
13289         drm_atomic_state_put(state);
13290 }
13291
13292 static const struct drm_crtc_funcs intel_crtc_funcs = {
13293         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13294         .set_config = drm_atomic_helper_set_config,
13295         .set_property = drm_atomic_helper_crtc_set_property,
13296         .destroy = intel_crtc_destroy,
13297         .page_flip = drm_atomic_helper_page_flip,
13298         .atomic_duplicate_state = intel_crtc_duplicate_state,
13299         .atomic_destroy_state = intel_crtc_destroy_state,
13300         .set_crc_source = intel_crtc_set_crc_source,
13301 };
13302
13303 /**
13304  * intel_prepare_plane_fb - Prepare fb for usage on plane
13305  * @plane: drm plane to prepare for
13306  * @fb: framebuffer to prepare for presentation
13307  *
13308  * Prepares a framebuffer for usage on a display plane.  Generally this
13309  * involves pinning the underlying object and updating the frontbuffer tracking
13310  * bits.  Some older platforms need special physical address handling for
13311  * cursor planes.
13312  *
13313  * Must be called with struct_mutex held.
13314  *
13315  * Returns 0 on success, negative error code on failure.
13316  */
13317 int
13318 intel_prepare_plane_fb(struct drm_plane *plane,
13319                        struct drm_plane_state *new_state)
13320 {
13321         struct intel_atomic_state *intel_state =
13322                 to_intel_atomic_state(new_state->state);
13323         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13324         struct drm_framebuffer *fb = new_state->fb;
13325         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13326         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13327         int ret;
13328
13329         if (obj) {
13330                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13331                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13332                         const int align = intel_cursor_alignment(dev_priv);
13333
13334                         ret = i915_gem_object_attach_phys(obj, align);
13335                         if (ret) {
13336                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13337                                 return ret;
13338                         }
13339                 } else {
13340                         struct i915_vma *vma;
13341
13342                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13343                         if (IS_ERR(vma)) {
13344                                 DRM_DEBUG_KMS("failed to pin object\n");
13345                                 return PTR_ERR(vma);
13346                         }
13347
13348                         to_intel_plane_state(new_state)->vma = vma;
13349                 }
13350         }
13351
13352         if (!obj && !old_obj)
13353                 return 0;
13354
13355         if (old_obj) {
13356                 struct drm_crtc_state *crtc_state =
13357                         drm_atomic_get_existing_crtc_state(new_state->state,
13358                                                            plane->state->crtc);
13359
13360                 /* Big Hammer, we also need to ensure that any pending
13361                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13362                  * current scanout is retired before unpinning the old
13363                  * framebuffer. Note that we rely on userspace rendering
13364                  * into the buffer attached to the pipe they are waiting
13365                  * on. If not, userspace generates a GPU hang with IPEHR
13366                  * point to the MI_WAIT_FOR_EVENT.
13367                  *
13368                  * This should only fail upon a hung GPU, in which case we
13369                  * can safely continue.
13370                  */
13371                 if (needs_modeset(crtc_state)) {
13372                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13373                                                               old_obj->resv, NULL,
13374                                                               false, 0,
13375                                                               GFP_KERNEL);
13376                         if (ret < 0)
13377                                 return ret;
13378                 }
13379         }
13380
13381         if (new_state->fence) { /* explicit fencing */
13382                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13383                                                     new_state->fence,
13384                                                     I915_FENCE_TIMEOUT,
13385                                                     GFP_KERNEL);
13386                 if (ret < 0)
13387                         return ret;
13388         }
13389
13390         if (!obj)
13391                 return 0;
13392
13393         if (!new_state->fence) { /* implicit fencing */
13394                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13395                                                       obj->resv, NULL,
13396                                                       false, I915_FENCE_TIMEOUT,
13397                                                       GFP_KERNEL);
13398                 if (ret < 0)
13399                         return ret;
13400
13401                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13402         }
13403
13404         return 0;
13405 }
13406
13407 /**
13408  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13409  * @plane: drm plane to clean up for
13410  * @fb: old framebuffer that was on plane
13411  *
13412  * Cleans up a framebuffer that has just been removed from a plane.
13413  *
13414  * Must be called with struct_mutex held.
13415  */
13416 void
13417 intel_cleanup_plane_fb(struct drm_plane *plane,
13418                        struct drm_plane_state *old_state)
13419 {
13420         struct i915_vma *vma;
13421
13422         /* Should only be called after a successful intel_prepare_plane_fb()! */
13423         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13424         if (vma)
13425                 intel_unpin_fb_vma(vma);
13426 }
13427
13428 int
13429 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13430 {
13431         struct drm_i915_private *dev_priv;
13432         int max_scale;
13433         int crtc_clock, max_dotclk;
13434
13435         if (!intel_crtc || !crtc_state->base.enable)
13436                 return DRM_PLANE_HELPER_NO_SCALING;
13437
13438         dev_priv = to_i915(intel_crtc->base.dev);
13439
13440         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13441         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13442
13443         if (IS_GEMINILAKE(dev_priv))
13444                 max_dotclk *= 2;
13445
13446         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13447                 return DRM_PLANE_HELPER_NO_SCALING;
13448
13449         /*
13450          * skl max scale is lower of:
13451          *    close to 3 but not 3, -1 is for that purpose
13452          *            or
13453          *    cdclk/crtc_clock
13454          */
13455         max_scale = min((1 << 16) * 3 - 1,
13456                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13457
13458         return max_scale;
13459 }
13460
13461 static int
13462 intel_check_primary_plane(struct intel_plane *plane,
13463                           struct intel_crtc_state *crtc_state,
13464                           struct intel_plane_state *state)
13465 {
13466         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13467         struct drm_crtc *crtc = state->base.crtc;
13468         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13469         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13470         bool can_position = false;
13471         int ret;
13472
13473         if (INTEL_GEN(dev_priv) >= 9) {
13474                 /* use scaler when colorkey is not required */
13475                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13476                         min_scale = 1;
13477                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13478                 }
13479                 can_position = true;
13480         }
13481
13482         ret = drm_plane_helper_check_state(&state->base,
13483                                            &state->clip,
13484                                            min_scale, max_scale,
13485                                            can_position, true);
13486         if (ret)
13487                 return ret;
13488
13489         if (!state->base.fb)
13490                 return 0;
13491
13492         if (INTEL_GEN(dev_priv) >= 9) {
13493                 ret = skl_check_plane_surface(state);
13494                 if (ret)
13495                         return ret;
13496
13497                 state->ctl = skl_plane_ctl(crtc_state, state);
13498         } else {
13499                 ret = i9xx_check_plane_surface(state);
13500                 if (ret)
13501                         return ret;
13502
13503                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13504         }
13505
13506         return 0;
13507 }
13508
13509 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13510                                     struct drm_crtc_state *old_crtc_state)
13511 {
13512         struct drm_device *dev = crtc->dev;
13513         struct drm_i915_private *dev_priv = to_i915(dev);
13514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13515         struct intel_crtc_state *intel_cstate =
13516                 to_intel_crtc_state(crtc->state);
13517         struct intel_crtc_state *old_intel_cstate =
13518                 to_intel_crtc_state(old_crtc_state);
13519         struct intel_atomic_state *old_intel_state =
13520                 to_intel_atomic_state(old_crtc_state->state);
13521         bool modeset = needs_modeset(crtc->state);
13522
13523         if (!modeset &&
13524             (intel_cstate->base.color_mgmt_changed ||
13525              intel_cstate->update_pipe)) {
13526                 intel_color_set_csc(crtc->state);
13527                 intel_color_load_luts(crtc->state);
13528         }
13529
13530         /* Perform vblank evasion around commit operation */
13531         intel_pipe_update_start(intel_crtc);
13532
13533         if (modeset)
13534                 goto out;
13535
13536         if (intel_cstate->update_pipe)
13537                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13538         else if (INTEL_GEN(dev_priv) >= 9)
13539                 skl_detach_scalers(intel_crtc);
13540
13541 out:
13542         if (dev_priv->display.atomic_update_watermarks)
13543                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13544                                                            intel_cstate);
13545 }
13546
13547 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13548                                      struct drm_crtc_state *old_crtc_state)
13549 {
13550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13551
13552         intel_pipe_update_end(intel_crtc, NULL);
13553 }
13554
13555 /**
13556  * intel_plane_destroy - destroy a plane
13557  * @plane: plane to destroy
13558  *
13559  * Common destruction function for all types of planes (primary, cursor,
13560  * sprite).
13561  */
13562 void intel_plane_destroy(struct drm_plane *plane)
13563 {
13564         drm_plane_cleanup(plane);
13565         kfree(to_intel_plane(plane));
13566 }
13567
13568 const struct drm_plane_funcs intel_plane_funcs = {
13569         .update_plane = drm_atomic_helper_update_plane,
13570         .disable_plane = drm_atomic_helper_disable_plane,
13571         .destroy = intel_plane_destroy,
13572         .set_property = drm_atomic_helper_plane_set_property,
13573         .atomic_get_property = intel_plane_atomic_get_property,
13574         .atomic_set_property = intel_plane_atomic_set_property,
13575         .atomic_duplicate_state = intel_plane_duplicate_state,
13576         .atomic_destroy_state = intel_plane_destroy_state,
13577 };
13578
13579 static int
13580 intel_legacy_cursor_update(struct drm_plane *plane,
13581                            struct drm_crtc *crtc,
13582                            struct drm_framebuffer *fb,
13583                            int crtc_x, int crtc_y,
13584                            unsigned int crtc_w, unsigned int crtc_h,
13585                            uint32_t src_x, uint32_t src_y,
13586                            uint32_t src_w, uint32_t src_h,
13587                            struct drm_modeset_acquire_ctx *ctx)
13588 {
13589         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13590         int ret;
13591         struct drm_plane_state *old_plane_state, *new_plane_state;
13592         struct intel_plane *intel_plane = to_intel_plane(plane);
13593         struct drm_framebuffer *old_fb;
13594         struct drm_crtc_state *crtc_state = crtc->state;
13595         struct i915_vma *old_vma;
13596
13597         /*
13598          * When crtc is inactive or there is a modeset pending,
13599          * wait for it to complete in the slowpath
13600          */
13601         if (!crtc_state->active || needs_modeset(crtc_state) ||
13602             to_intel_crtc_state(crtc_state)->update_pipe)
13603                 goto slow;
13604
13605         old_plane_state = plane->state;
13606
13607         /*
13608          * If any parameters change that may affect watermarks,
13609          * take the slowpath. Only changing fb or position should be
13610          * in the fastpath.
13611          */
13612         if (old_plane_state->crtc != crtc ||
13613             old_plane_state->src_w != src_w ||
13614             old_plane_state->src_h != src_h ||
13615             old_plane_state->crtc_w != crtc_w ||
13616             old_plane_state->crtc_h != crtc_h ||
13617             !old_plane_state->fb != !fb)
13618                 goto slow;
13619
13620         new_plane_state = intel_plane_duplicate_state(plane);
13621         if (!new_plane_state)
13622                 return -ENOMEM;
13623
13624         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13625
13626         new_plane_state->src_x = src_x;
13627         new_plane_state->src_y = src_y;
13628         new_plane_state->src_w = src_w;
13629         new_plane_state->src_h = src_h;
13630         new_plane_state->crtc_x = crtc_x;
13631         new_plane_state->crtc_y = crtc_y;
13632         new_plane_state->crtc_w = crtc_w;
13633         new_plane_state->crtc_h = crtc_h;
13634
13635         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13636                                                   to_intel_plane_state(new_plane_state));
13637         if (ret)
13638                 goto out_free;
13639
13640         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13641         if (ret)
13642                 goto out_free;
13643
13644         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13645                 int align = intel_cursor_alignment(dev_priv);
13646
13647                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13648                 if (ret) {
13649                         DRM_DEBUG_KMS("failed to attach phys object\n");
13650                         goto out_unlock;
13651                 }
13652         } else {
13653                 struct i915_vma *vma;
13654
13655                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13656                 if (IS_ERR(vma)) {
13657                         DRM_DEBUG_KMS("failed to pin object\n");
13658
13659                         ret = PTR_ERR(vma);
13660                         goto out_unlock;
13661                 }
13662
13663                 to_intel_plane_state(new_plane_state)->vma = vma;
13664         }
13665
13666         old_fb = old_plane_state->fb;
13667         old_vma = to_intel_plane_state(old_plane_state)->vma;
13668
13669         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13670                           intel_plane->frontbuffer_bit);
13671
13672         /* Swap plane state */
13673         new_plane_state->fence = old_plane_state->fence;
13674         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13675         new_plane_state->fence = NULL;
13676         new_plane_state->fb = old_fb;
13677         to_intel_plane_state(new_plane_state)->vma = old_vma;
13678
13679         if (plane->state->visible) {
13680                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13681                 intel_plane->update_plane(intel_plane,
13682                                           to_intel_crtc_state(crtc->state),
13683                                           to_intel_plane_state(plane->state));
13684         } else {
13685                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13686                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13687         }
13688
13689         intel_cleanup_plane_fb(plane, new_plane_state);
13690
13691 out_unlock:
13692         mutex_unlock(&dev_priv->drm.struct_mutex);
13693 out_free:
13694         intel_plane_destroy_state(plane, new_plane_state);
13695         return ret;
13696
13697 slow:
13698         return drm_atomic_helper_update_plane(plane, crtc, fb,
13699                                               crtc_x, crtc_y, crtc_w, crtc_h,
13700                                               src_x, src_y, src_w, src_h, ctx);
13701 }
13702
13703 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13704         .update_plane = intel_legacy_cursor_update,
13705         .disable_plane = drm_atomic_helper_disable_plane,
13706         .destroy = intel_plane_destroy,
13707         .set_property = drm_atomic_helper_plane_set_property,
13708         .atomic_get_property = intel_plane_atomic_get_property,
13709         .atomic_set_property = intel_plane_atomic_set_property,
13710         .atomic_duplicate_state = intel_plane_duplicate_state,
13711         .atomic_destroy_state = intel_plane_destroy_state,
13712 };
13713
13714 static struct intel_plane *
13715 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13716 {
13717         struct intel_plane *primary = NULL;
13718         struct intel_plane_state *state = NULL;
13719         const uint32_t *intel_primary_formats;
13720         unsigned int supported_rotations;
13721         unsigned int num_formats;
13722         int ret;
13723
13724         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13725         if (!primary) {
13726                 ret = -ENOMEM;
13727                 goto fail;
13728         }
13729
13730         state = intel_create_plane_state(&primary->base);
13731         if (!state) {
13732                 ret = -ENOMEM;
13733                 goto fail;
13734         }
13735
13736         primary->base.state = &state->base;
13737
13738         primary->can_scale = false;
13739         primary->max_downscale = 1;
13740         if (INTEL_GEN(dev_priv) >= 9) {
13741                 primary->can_scale = true;
13742                 state->scaler_id = -1;
13743         }
13744         primary->pipe = pipe;
13745         /*
13746          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13747          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13748          */
13749         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13750                 primary->plane = (enum plane) !pipe;
13751         else
13752                 primary->plane = (enum plane) pipe;
13753         primary->id = PLANE_PRIMARY;
13754         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13755         primary->check_plane = intel_check_primary_plane;
13756
13757         if (INTEL_GEN(dev_priv) >= 9) {
13758                 intel_primary_formats = skl_primary_formats;
13759                 num_formats = ARRAY_SIZE(skl_primary_formats);
13760
13761                 primary->update_plane = skylake_update_primary_plane;
13762                 primary->disable_plane = skylake_disable_primary_plane;
13763         } else if (INTEL_GEN(dev_priv) >= 4) {
13764                 intel_primary_formats = i965_primary_formats;
13765                 num_formats = ARRAY_SIZE(i965_primary_formats);
13766
13767                 primary->update_plane = i9xx_update_primary_plane;
13768                 primary->disable_plane = i9xx_disable_primary_plane;
13769         } else {
13770                 intel_primary_formats = i8xx_primary_formats;
13771                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13772
13773                 primary->update_plane = i9xx_update_primary_plane;
13774                 primary->disable_plane = i9xx_disable_primary_plane;
13775         }
13776
13777         if (INTEL_GEN(dev_priv) >= 9)
13778                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13779                                                0, &intel_plane_funcs,
13780                                                intel_primary_formats, num_formats,
13781                                                DRM_PLANE_TYPE_PRIMARY,
13782                                                "plane 1%c", pipe_name(pipe));
13783         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13784                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13785                                                0, &intel_plane_funcs,
13786                                                intel_primary_formats, num_formats,
13787                                                DRM_PLANE_TYPE_PRIMARY,
13788                                                "primary %c", pipe_name(pipe));
13789         else
13790                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13791                                                0, &intel_plane_funcs,
13792                                                intel_primary_formats, num_formats,
13793                                                DRM_PLANE_TYPE_PRIMARY,
13794                                                "plane %c", plane_name(primary->plane));
13795         if (ret)
13796                 goto fail;
13797
13798         if (INTEL_GEN(dev_priv) >= 9) {
13799                 supported_rotations =
13800                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13801                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13802         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13803                 supported_rotations =
13804                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13805                         DRM_MODE_REFLECT_X;
13806         } else if (INTEL_GEN(dev_priv) >= 4) {
13807                 supported_rotations =
13808                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13809         } else {
13810                 supported_rotations = DRM_MODE_ROTATE_0;
13811         }
13812
13813         if (INTEL_GEN(dev_priv) >= 4)
13814                 drm_plane_create_rotation_property(&primary->base,
13815                                                    DRM_MODE_ROTATE_0,
13816                                                    supported_rotations);
13817
13818         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13819
13820         return primary;
13821
13822 fail:
13823         kfree(state);
13824         kfree(primary);
13825
13826         return ERR_PTR(ret);
13827 }
13828
13829 static struct intel_plane *
13830 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13831                           enum pipe pipe)
13832 {
13833         struct intel_plane *cursor = NULL;
13834         struct intel_plane_state *state = NULL;
13835         int ret;
13836
13837         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13838         if (!cursor) {
13839                 ret = -ENOMEM;
13840                 goto fail;
13841         }
13842
13843         state = intel_create_plane_state(&cursor->base);
13844         if (!state) {
13845                 ret = -ENOMEM;
13846                 goto fail;
13847         }
13848
13849         cursor->base.state = &state->base;
13850
13851         cursor->can_scale = false;
13852         cursor->max_downscale = 1;
13853         cursor->pipe = pipe;
13854         cursor->plane = pipe;
13855         cursor->id = PLANE_CURSOR;
13856         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13857
13858         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13859                 cursor->update_plane = i845_update_cursor;
13860                 cursor->disable_plane = i845_disable_cursor;
13861                 cursor->check_plane = i845_check_cursor;
13862         } else {
13863                 cursor->update_plane = i9xx_update_cursor;
13864                 cursor->disable_plane = i9xx_disable_cursor;
13865                 cursor->check_plane = i9xx_check_cursor;
13866         }
13867
13868         cursor->cursor.base = ~0;
13869         cursor->cursor.cntl = ~0;
13870
13871         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13872                 cursor->cursor.size = ~0;
13873
13874         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13875                                        0, &intel_cursor_plane_funcs,
13876                                        intel_cursor_formats,
13877                                        ARRAY_SIZE(intel_cursor_formats),
13878                                        DRM_PLANE_TYPE_CURSOR,
13879                                        "cursor %c", pipe_name(pipe));
13880         if (ret)
13881                 goto fail;
13882
13883         if (INTEL_GEN(dev_priv) >= 4)
13884                 drm_plane_create_rotation_property(&cursor->base,
13885                                                    DRM_MODE_ROTATE_0,
13886                                                    DRM_MODE_ROTATE_0 |
13887                                                    DRM_MODE_ROTATE_180);
13888
13889         if (INTEL_GEN(dev_priv) >= 9)
13890                 state->scaler_id = -1;
13891
13892         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13893
13894         return cursor;
13895
13896 fail:
13897         kfree(state);
13898         kfree(cursor);
13899
13900         return ERR_PTR(ret);
13901 }
13902
13903 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13904                                     struct intel_crtc_state *crtc_state)
13905 {
13906         struct intel_crtc_scaler_state *scaler_state =
13907                 &crtc_state->scaler_state;
13908         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13909         int i;
13910
13911         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13912         if (!crtc->num_scalers)
13913                 return;
13914
13915         for (i = 0; i < crtc->num_scalers; i++) {
13916                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13917
13918                 scaler->in_use = 0;
13919                 scaler->mode = PS_SCALER_MODE_DYN;
13920         }
13921
13922         scaler_state->scaler_id = -1;
13923 }
13924
13925 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13926 {
13927         struct intel_crtc *intel_crtc;
13928         struct intel_crtc_state *crtc_state = NULL;
13929         struct intel_plane *primary = NULL;
13930         struct intel_plane *cursor = NULL;
13931         int sprite, ret;
13932
13933         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13934         if (!intel_crtc)
13935                 return -ENOMEM;
13936
13937         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13938         if (!crtc_state) {
13939                 ret = -ENOMEM;
13940                 goto fail;
13941         }
13942         intel_crtc->config = crtc_state;
13943         intel_crtc->base.state = &crtc_state->base;
13944         crtc_state->base.crtc = &intel_crtc->base;
13945
13946         primary = intel_primary_plane_create(dev_priv, pipe);
13947         if (IS_ERR(primary)) {
13948                 ret = PTR_ERR(primary);
13949                 goto fail;
13950         }
13951         intel_crtc->plane_ids_mask |= BIT(primary->id);
13952
13953         for_each_sprite(dev_priv, pipe, sprite) {
13954                 struct intel_plane *plane;
13955
13956                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13957                 if (IS_ERR(plane)) {
13958                         ret = PTR_ERR(plane);
13959                         goto fail;
13960                 }
13961                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13962         }
13963
13964         cursor = intel_cursor_plane_create(dev_priv, pipe);
13965         if (IS_ERR(cursor)) {
13966                 ret = PTR_ERR(cursor);
13967                 goto fail;
13968         }
13969         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13970
13971         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13972                                         &primary->base, &cursor->base,
13973                                         &intel_crtc_funcs,
13974                                         "pipe %c", pipe_name(pipe));
13975         if (ret)
13976                 goto fail;
13977
13978         intel_crtc->pipe = pipe;
13979         intel_crtc->plane = primary->plane;
13980
13981         /* initialize shared scalers */
13982         intel_crtc_init_scalers(intel_crtc, crtc_state);
13983
13984         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13985                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13986         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13987         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13988
13989         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13990
13991         intel_color_init(&intel_crtc->base);
13992
13993         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13994
13995         return 0;
13996
13997 fail:
13998         /*
13999          * drm_mode_config_cleanup() will free up any
14000          * crtcs/planes already initialized.
14001          */
14002         kfree(crtc_state);
14003         kfree(intel_crtc);
14004
14005         return ret;
14006 }
14007
14008 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14009 {
14010         struct drm_device *dev = connector->base.dev;
14011
14012         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14013
14014         if (!connector->base.state->crtc)
14015                 return INVALID_PIPE;
14016
14017         return to_intel_crtc(connector->base.state->crtc)->pipe;
14018 }
14019
14020 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14021                                 struct drm_file *file)
14022 {
14023         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14024         struct drm_crtc *drmmode_crtc;
14025         struct intel_crtc *crtc;
14026
14027         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14028         if (!drmmode_crtc)
14029                 return -ENOENT;
14030
14031         crtc = to_intel_crtc(drmmode_crtc);
14032         pipe_from_crtc_id->pipe = crtc->pipe;
14033
14034         return 0;
14035 }
14036
14037 static int intel_encoder_clones(struct intel_encoder *encoder)
14038 {
14039         struct drm_device *dev = encoder->base.dev;
14040         struct intel_encoder *source_encoder;
14041         int index_mask = 0;
14042         int entry = 0;
14043
14044         for_each_intel_encoder(dev, source_encoder) {
14045                 if (encoders_cloneable(encoder, source_encoder))
14046                         index_mask |= (1 << entry);
14047
14048                 entry++;
14049         }
14050
14051         return index_mask;
14052 }
14053
14054 static bool has_edp_a(struct drm_i915_private *dev_priv)
14055 {
14056         if (!IS_MOBILE(dev_priv))
14057                 return false;
14058
14059         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14060                 return false;
14061
14062         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14063                 return false;
14064
14065         return true;
14066 }
14067
14068 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14069 {
14070         if (INTEL_GEN(dev_priv) >= 9)
14071                 return false;
14072
14073         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14074                 return false;
14075
14076         if (IS_CHERRYVIEW(dev_priv))
14077                 return false;
14078
14079         if (HAS_PCH_LPT_H(dev_priv) &&
14080             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14081                 return false;
14082
14083         /* DDI E can't be used if DDI A requires 4 lanes */
14084         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14085                 return false;
14086
14087         if (!dev_priv->vbt.int_crt_support)
14088                 return false;
14089
14090         return true;
14091 }
14092
14093 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14094 {
14095         int pps_num;
14096         int pps_idx;
14097
14098         if (HAS_DDI(dev_priv))
14099                 return;
14100         /*
14101          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14102          * everywhere where registers can be write protected.
14103          */
14104         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14105                 pps_num = 2;
14106         else
14107                 pps_num = 1;
14108
14109         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14110                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14111
14112                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14113                 I915_WRITE(PP_CONTROL(pps_idx), val);
14114         }
14115 }
14116
14117 static void intel_pps_init(struct drm_i915_private *dev_priv)
14118 {
14119         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14120                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14121         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14122                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14123         else
14124                 dev_priv->pps_mmio_base = PPS_BASE;
14125
14126         intel_pps_unlock_regs_wa(dev_priv);
14127 }
14128
14129 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14130 {
14131         struct intel_encoder *encoder;
14132         bool dpd_is_edp = false;
14133
14134         intel_pps_init(dev_priv);
14135
14136         /*
14137          * intel_edp_init_connector() depends on this completing first, to
14138          * prevent the registeration of both eDP and LVDS and the incorrect
14139          * sharing of the PPS.
14140          */
14141         intel_lvds_init(dev_priv);
14142
14143         if (intel_crt_present(dev_priv))
14144                 intel_crt_init(dev_priv);
14145
14146         if (IS_GEN9_LP(dev_priv)) {
14147                 /*
14148                  * FIXME: Broxton doesn't support port detection via the
14149                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14150                  * detect the ports.
14151                  */
14152                 intel_ddi_init(dev_priv, PORT_A);
14153                 intel_ddi_init(dev_priv, PORT_B);
14154                 intel_ddi_init(dev_priv, PORT_C);
14155
14156                 intel_dsi_init(dev_priv);
14157         } else if (HAS_DDI(dev_priv)) {
14158                 int found;
14159
14160                 /*
14161                  * Haswell uses DDI functions to detect digital outputs.
14162                  * On SKL pre-D0 the strap isn't connected, so we assume
14163                  * it's there.
14164                  */
14165                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14166                 /* WaIgnoreDDIAStrap: skl */
14167                 if (found || IS_GEN9_BC(dev_priv))
14168                         intel_ddi_init(dev_priv, PORT_A);
14169
14170                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14171                  * register */
14172                 found = I915_READ(SFUSE_STRAP);
14173
14174                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14175                         intel_ddi_init(dev_priv, PORT_B);
14176                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14177                         intel_ddi_init(dev_priv, PORT_C);
14178                 if (found & SFUSE_STRAP_DDID_DETECTED)
14179                         intel_ddi_init(dev_priv, PORT_D);
14180                 /*
14181                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14182                  */
14183                 if (IS_GEN9_BC(dev_priv) &&
14184                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14185                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14186                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14187                         intel_ddi_init(dev_priv, PORT_E);
14188
14189         } else if (HAS_PCH_SPLIT(dev_priv)) {
14190                 int found;
14191                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14192
14193                 if (has_edp_a(dev_priv))
14194                         intel_dp_init(dev_priv, DP_A, PORT_A);
14195
14196                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14197                         /* PCH SDVOB multiplex with HDMIB */
14198                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14199                         if (!found)
14200                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14201                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14202                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14203                 }
14204
14205                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14206                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14207
14208                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14209                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14210
14211                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14212                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14213
14214                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14215                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14216         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14217                 bool has_edp, has_port;
14218
14219                 /*
14220                  * The DP_DETECTED bit is the latched state of the DDC
14221                  * SDA pin at boot. However since eDP doesn't require DDC
14222                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14223                  * eDP ports may have been muxed to an alternate function.
14224                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14225                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14226                  * detect eDP ports.
14227                  *
14228                  * Sadly the straps seem to be missing sometimes even for HDMI
14229                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14230                  * and VBT for the presence of the port. Additionally we can't
14231                  * trust the port type the VBT declares as we've seen at least
14232                  * HDMI ports that the VBT claim are DP or eDP.
14233                  */
14234                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14235                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14236                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14237                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14238                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14239                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14240
14241                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14242                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14243                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14244                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14245                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14246                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14247
14248                 if (IS_CHERRYVIEW(dev_priv)) {
14249                         /*
14250                          * eDP not supported on port D,
14251                          * so no need to worry about it
14252                          */
14253                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14254                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14255                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14256                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14257                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14258                 }
14259
14260                 intel_dsi_init(dev_priv);
14261         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14262                 bool found = false;
14263
14264                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14265                         DRM_DEBUG_KMS("probing SDVOB\n");
14266                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14267                         if (!found && IS_G4X(dev_priv)) {
14268                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14269                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14270                         }
14271
14272                         if (!found && IS_G4X(dev_priv))
14273                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14274                 }
14275
14276                 /* Before G4X SDVOC doesn't have its own detect register */
14277
14278                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14279                         DRM_DEBUG_KMS("probing SDVOC\n");
14280                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14281                 }
14282
14283                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14284
14285                         if (IS_G4X(dev_priv)) {
14286                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14287                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14288                         }
14289                         if (IS_G4X(dev_priv))
14290                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14291                 }
14292
14293                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14294                         intel_dp_init(dev_priv, DP_D, PORT_D);
14295         } else if (IS_GEN2(dev_priv))
14296                 intel_dvo_init(dev_priv);
14297
14298         if (SUPPORTS_TV(dev_priv))
14299                 intel_tv_init(dev_priv);
14300
14301         intel_psr_init(dev_priv);
14302
14303         for_each_intel_encoder(&dev_priv->drm, encoder) {
14304                 encoder->base.possible_crtcs = encoder->crtc_mask;
14305                 encoder->base.possible_clones =
14306                         intel_encoder_clones(encoder);
14307         }
14308
14309         intel_init_pch_refclk(dev_priv);
14310
14311         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14312 }
14313
14314 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14315 {
14316         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14317
14318         drm_framebuffer_cleanup(fb);
14319
14320         i915_gem_object_lock(intel_fb->obj);
14321         WARN_ON(!intel_fb->obj->framebuffer_references--);
14322         i915_gem_object_unlock(intel_fb->obj);
14323
14324         i915_gem_object_put(intel_fb->obj);
14325
14326         kfree(intel_fb);
14327 }
14328
14329 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14330                                                 struct drm_file *file,
14331                                                 unsigned int *handle)
14332 {
14333         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14334         struct drm_i915_gem_object *obj = intel_fb->obj;
14335
14336         if (obj->userptr.mm) {
14337                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14338                 return -EINVAL;
14339         }
14340
14341         return drm_gem_handle_create(file, &obj->base, handle);
14342 }
14343
14344 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14345                                         struct drm_file *file,
14346                                         unsigned flags, unsigned color,
14347                                         struct drm_clip_rect *clips,
14348                                         unsigned num_clips)
14349 {
14350         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14351
14352         i915_gem_object_flush_if_display(obj);
14353         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14354
14355         return 0;
14356 }
14357
14358 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14359         .destroy = intel_user_framebuffer_destroy,
14360         .create_handle = intel_user_framebuffer_create_handle,
14361         .dirty = intel_user_framebuffer_dirty,
14362 };
14363
14364 static
14365 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14366                          uint64_t fb_modifier, uint32_t pixel_format)
14367 {
14368         u32 gen = INTEL_GEN(dev_priv);
14369
14370         if (gen >= 9) {
14371                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14372
14373                 /* "The stride in bytes must not exceed the of the size of 8K
14374                  *  pixels and 32K bytes."
14375                  */
14376                 return min(8192 * cpp, 32768);
14377         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14378                 return 32*1024;
14379         } else if (gen >= 4) {
14380                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14381                         return 16*1024;
14382                 else
14383                         return 32*1024;
14384         } else if (gen >= 3) {
14385                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14386                         return 8*1024;
14387                 else
14388                         return 16*1024;
14389         } else {
14390                 /* XXX DSPC is limited to 4k tiled */
14391                 return 8*1024;
14392         }
14393 }
14394
14395 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14396                                   struct drm_i915_gem_object *obj,
14397                                   struct drm_mode_fb_cmd2 *mode_cmd)
14398 {
14399         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14400         struct drm_format_name_buf format_name;
14401         u32 pitch_limit, stride_alignment;
14402         unsigned int tiling, stride;
14403         int ret = -EINVAL;
14404
14405         i915_gem_object_lock(obj);
14406         obj->framebuffer_references++;
14407         tiling = i915_gem_object_get_tiling(obj);
14408         stride = i915_gem_object_get_stride(obj);
14409         i915_gem_object_unlock(obj);
14410
14411         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14412                 /*
14413                  * If there's a fence, enforce that
14414                  * the fb modifier and tiling mode match.
14415                  */
14416                 if (tiling != I915_TILING_NONE &&
14417                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14418                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14419                         goto err;
14420                 }
14421         } else {
14422                 if (tiling == I915_TILING_X) {
14423                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14424                 } else if (tiling == I915_TILING_Y) {
14425                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14426                         goto err;
14427                 }
14428         }
14429
14430         /* Passed in modifier sanity checking. */
14431         switch (mode_cmd->modifier[0]) {
14432         case I915_FORMAT_MOD_Y_TILED:
14433         case I915_FORMAT_MOD_Yf_TILED:
14434                 if (INTEL_GEN(dev_priv) < 9) {
14435                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14436                                       mode_cmd->modifier[0]);
14437                         goto err;
14438                 }
14439         case DRM_FORMAT_MOD_LINEAR:
14440         case I915_FORMAT_MOD_X_TILED:
14441                 break;
14442         default:
14443                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14444                               mode_cmd->modifier[0]);
14445                 goto err;
14446         }
14447
14448         /*
14449          * gen2/3 display engine uses the fence if present,
14450          * so the tiling mode must match the fb modifier exactly.
14451          */
14452         if (INTEL_INFO(dev_priv)->gen < 4 &&
14453             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14454                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14455                 goto err;
14456         }
14457
14458         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14459                                            mode_cmd->pixel_format);
14460         if (mode_cmd->pitches[0] > pitch_limit) {
14461                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14462                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14463                               "tiled" : "linear",
14464                               mode_cmd->pitches[0], pitch_limit);
14465                 goto err;
14466         }
14467
14468         /*
14469          * If there's a fence, enforce that
14470          * the fb pitch and fence stride match.
14471          */
14472         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14473                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14474                               mode_cmd->pitches[0], stride);
14475                 goto err;
14476         }
14477
14478         /* Reject formats not supported by any plane early. */
14479         switch (mode_cmd->pixel_format) {
14480         case DRM_FORMAT_C8:
14481         case DRM_FORMAT_RGB565:
14482         case DRM_FORMAT_XRGB8888:
14483         case DRM_FORMAT_ARGB8888:
14484                 break;
14485         case DRM_FORMAT_XRGB1555:
14486                 if (INTEL_GEN(dev_priv) > 3) {
14487                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14488                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14489                         goto err;
14490                 }
14491                 break;
14492         case DRM_FORMAT_ABGR8888:
14493                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14494                     INTEL_GEN(dev_priv) < 9) {
14495                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14496                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14497                         goto err;
14498                 }
14499                 break;
14500         case DRM_FORMAT_XBGR8888:
14501         case DRM_FORMAT_XRGB2101010:
14502         case DRM_FORMAT_XBGR2101010:
14503                 if (INTEL_GEN(dev_priv) < 4) {
14504                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14505                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14506                         goto err;
14507                 }
14508                 break;
14509         case DRM_FORMAT_ABGR2101010:
14510                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14511                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14512                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14513                         goto err;
14514                 }
14515                 break;
14516         case DRM_FORMAT_YUYV:
14517         case DRM_FORMAT_UYVY:
14518         case DRM_FORMAT_YVYU:
14519         case DRM_FORMAT_VYUY:
14520                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14521                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14522                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14523                         goto err;
14524                 }
14525                 break;
14526         default:
14527                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14528                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14529                 goto err;
14530         }
14531
14532         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14533         if (mode_cmd->offsets[0] != 0)
14534                 goto err;
14535
14536         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14537                                        &intel_fb->base, mode_cmd);
14538
14539         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14540         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14541                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14542                               mode_cmd->pitches[0], stride_alignment);
14543                 goto err;
14544         }
14545
14546         intel_fb->obj = obj;
14547
14548         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14549         if (ret)
14550                 goto err;
14551
14552         ret = drm_framebuffer_init(obj->base.dev,
14553                                    &intel_fb->base,
14554                                    &intel_fb_funcs);
14555         if (ret) {
14556                 DRM_ERROR("framebuffer init failed %d\n", ret);
14557                 goto err;
14558         }
14559
14560         return 0;
14561
14562 err:
14563         i915_gem_object_lock(obj);
14564         obj->framebuffer_references--;
14565         i915_gem_object_unlock(obj);
14566         return ret;
14567 }
14568
14569 static struct drm_framebuffer *
14570 intel_user_framebuffer_create(struct drm_device *dev,
14571                               struct drm_file *filp,
14572                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14573 {
14574         struct drm_framebuffer *fb;
14575         struct drm_i915_gem_object *obj;
14576         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14577
14578         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14579         if (!obj)
14580                 return ERR_PTR(-ENOENT);
14581
14582         fb = intel_framebuffer_create(obj, &mode_cmd);
14583         if (IS_ERR(fb))
14584                 i915_gem_object_put(obj);
14585
14586         return fb;
14587 }
14588
14589 static void intel_atomic_state_free(struct drm_atomic_state *state)
14590 {
14591         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14592
14593         drm_atomic_state_default_release(state);
14594
14595         i915_sw_fence_fini(&intel_state->commit_ready);
14596
14597         kfree(state);
14598 }
14599
14600 static const struct drm_mode_config_funcs intel_mode_funcs = {
14601         .fb_create = intel_user_framebuffer_create,
14602         .output_poll_changed = intel_fbdev_output_poll_changed,
14603         .atomic_check = intel_atomic_check,
14604         .atomic_commit = intel_atomic_commit,
14605         .atomic_state_alloc = intel_atomic_state_alloc,
14606         .atomic_state_clear = intel_atomic_state_clear,
14607         .atomic_state_free = intel_atomic_state_free,
14608 };
14609
14610 /**
14611  * intel_init_display_hooks - initialize the display modesetting hooks
14612  * @dev_priv: device private
14613  */
14614 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14615 {
14616         intel_init_cdclk_hooks(dev_priv);
14617
14618         if (INTEL_INFO(dev_priv)->gen >= 9) {
14619                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14620                 dev_priv->display.get_initial_plane_config =
14621                         skylake_get_initial_plane_config;
14622                 dev_priv->display.crtc_compute_clock =
14623                         haswell_crtc_compute_clock;
14624                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14625                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14626         } else if (HAS_DDI(dev_priv)) {
14627                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14628                 dev_priv->display.get_initial_plane_config =
14629                         ironlake_get_initial_plane_config;
14630                 dev_priv->display.crtc_compute_clock =
14631                         haswell_crtc_compute_clock;
14632                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14633                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14634         } else if (HAS_PCH_SPLIT(dev_priv)) {
14635                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14636                 dev_priv->display.get_initial_plane_config =
14637                         ironlake_get_initial_plane_config;
14638                 dev_priv->display.crtc_compute_clock =
14639                         ironlake_crtc_compute_clock;
14640                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14641                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14642         } else if (IS_CHERRYVIEW(dev_priv)) {
14643                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14644                 dev_priv->display.get_initial_plane_config =
14645                         i9xx_get_initial_plane_config;
14646                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14647                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14648                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14649         } else if (IS_VALLEYVIEW(dev_priv)) {
14650                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14651                 dev_priv->display.get_initial_plane_config =
14652                         i9xx_get_initial_plane_config;
14653                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14654                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14655                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14656         } else if (IS_G4X(dev_priv)) {
14657                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14658                 dev_priv->display.get_initial_plane_config =
14659                         i9xx_get_initial_plane_config;
14660                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14661                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14662                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14663         } else if (IS_PINEVIEW(dev_priv)) {
14664                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14665                 dev_priv->display.get_initial_plane_config =
14666                         i9xx_get_initial_plane_config;
14667                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14668                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14669                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14670         } else if (!IS_GEN2(dev_priv)) {
14671                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14672                 dev_priv->display.get_initial_plane_config =
14673                         i9xx_get_initial_plane_config;
14674                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14675                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14676                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14677         } else {
14678                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14679                 dev_priv->display.get_initial_plane_config =
14680                         i9xx_get_initial_plane_config;
14681                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14682                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14683                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14684         }
14685
14686         if (IS_GEN5(dev_priv)) {
14687                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14688         } else if (IS_GEN6(dev_priv)) {
14689                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14690         } else if (IS_IVYBRIDGE(dev_priv)) {
14691                 /* FIXME: detect B0+ stepping and use auto training */
14692                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14693         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14694                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14695         }
14696
14697         if (dev_priv->info.gen >= 9)
14698                 dev_priv->display.update_crtcs = skl_update_crtcs;
14699         else
14700                 dev_priv->display.update_crtcs = intel_update_crtcs;
14701
14702         switch (INTEL_INFO(dev_priv)->gen) {
14703         case 2:
14704                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14705                 break;
14706
14707         case 3:
14708                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14709                 break;
14710
14711         case 4:
14712         case 5:
14713                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14714                 break;
14715
14716         case 6:
14717                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14718                 break;
14719         case 7:
14720         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14721                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14722                 break;
14723         case 9:
14724                 /* Drop through - unsupported since execlist only. */
14725         default:
14726                 /* Default just returns -ENODEV to indicate unsupported */
14727                 dev_priv->display.queue_flip = intel_default_queue_flip;
14728         }
14729 }
14730
14731 /*
14732  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14733  * resume, or other times.  This quirk makes sure that's the case for
14734  * affected systems.
14735  */
14736 static void quirk_pipea_force(struct drm_device *dev)
14737 {
14738         struct drm_i915_private *dev_priv = to_i915(dev);
14739
14740         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14741         DRM_INFO("applying pipe a force quirk\n");
14742 }
14743
14744 static void quirk_pipeb_force(struct drm_device *dev)
14745 {
14746         struct drm_i915_private *dev_priv = to_i915(dev);
14747
14748         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14749         DRM_INFO("applying pipe b force quirk\n");
14750 }
14751
14752 /*
14753  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14754  */
14755 static void quirk_ssc_force_disable(struct drm_device *dev)
14756 {
14757         struct drm_i915_private *dev_priv = to_i915(dev);
14758         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14759         DRM_INFO("applying lvds SSC disable quirk\n");
14760 }
14761
14762 /*
14763  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14764  * brightness value
14765  */
14766 static void quirk_invert_brightness(struct drm_device *dev)
14767 {
14768         struct drm_i915_private *dev_priv = to_i915(dev);
14769         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14770         DRM_INFO("applying inverted panel brightness quirk\n");
14771 }
14772
14773 /* Some VBT's incorrectly indicate no backlight is present */
14774 static void quirk_backlight_present(struct drm_device *dev)
14775 {
14776         struct drm_i915_private *dev_priv = to_i915(dev);
14777         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14778         DRM_INFO("applying backlight present quirk\n");
14779 }
14780
14781 struct intel_quirk {
14782         int device;
14783         int subsystem_vendor;
14784         int subsystem_device;
14785         void (*hook)(struct drm_device *dev);
14786 };
14787
14788 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14789 struct intel_dmi_quirk {
14790         void (*hook)(struct drm_device *dev);
14791         const struct dmi_system_id (*dmi_id_list)[];
14792 };
14793
14794 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14795 {
14796         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14797         return 1;
14798 }
14799
14800 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14801         {
14802                 .dmi_id_list = &(const struct dmi_system_id[]) {
14803                         {
14804                                 .callback = intel_dmi_reverse_brightness,
14805                                 .ident = "NCR Corporation",
14806                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14807                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14808                                 },
14809                         },
14810                         { }  /* terminating entry */
14811                 },
14812                 .hook = quirk_invert_brightness,
14813         },
14814 };
14815
14816 static struct intel_quirk intel_quirks[] = {
14817         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14818         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14819
14820         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14821         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14822
14823         /* 830 needs to leave pipe A & dpll A up */
14824         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14825
14826         /* 830 needs to leave pipe B & dpll B up */
14827         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14828
14829         /* Lenovo U160 cannot use SSC on LVDS */
14830         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14831
14832         /* Sony Vaio Y cannot use SSC on LVDS */
14833         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14834
14835         /* Acer Aspire 5734Z must invert backlight brightness */
14836         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14837
14838         /* Acer/eMachines G725 */
14839         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14840
14841         /* Acer/eMachines e725 */
14842         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14843
14844         /* Acer/Packard Bell NCL20 */
14845         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14846
14847         /* Acer Aspire 4736Z */
14848         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14849
14850         /* Acer Aspire 5336 */
14851         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14852
14853         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14854         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14855
14856         /* Acer C720 Chromebook (Core i3 4005U) */
14857         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14858
14859         /* Apple Macbook 2,1 (Core 2 T7400) */
14860         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14861
14862         /* Apple Macbook 4,1 */
14863         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14864
14865         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14866         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14867
14868         /* HP Chromebook 14 (Celeron 2955U) */
14869         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14870
14871         /* Dell Chromebook 11 */
14872         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14873
14874         /* Dell Chromebook 11 (2015 version) */
14875         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14876 };
14877
14878 static void intel_init_quirks(struct drm_device *dev)
14879 {
14880         struct pci_dev *d = dev->pdev;
14881         int i;
14882
14883         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14884                 struct intel_quirk *q = &intel_quirks[i];
14885
14886                 if (d->device == q->device &&
14887                     (d->subsystem_vendor == q->subsystem_vendor ||
14888                      q->subsystem_vendor == PCI_ANY_ID) &&
14889                     (d->subsystem_device == q->subsystem_device ||
14890                      q->subsystem_device == PCI_ANY_ID))
14891                         q->hook(dev);
14892         }
14893         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14894                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14895                         intel_dmi_quirks[i].hook(dev);
14896         }
14897 }
14898
14899 /* Disable the VGA plane that we never use */
14900 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14901 {
14902         struct pci_dev *pdev = dev_priv->drm.pdev;
14903         u8 sr1;
14904         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14905
14906         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14907         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14908         outb(SR01, VGA_SR_INDEX);
14909         sr1 = inb(VGA_SR_DATA);
14910         outb(sr1 | 1<<5, VGA_SR_DATA);
14911         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14912         udelay(300);
14913
14914         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14915         POSTING_READ(vga_reg);
14916 }
14917
14918 void intel_modeset_init_hw(struct drm_device *dev)
14919 {
14920         struct drm_i915_private *dev_priv = to_i915(dev);
14921
14922         intel_update_cdclk(dev_priv);
14923         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14924
14925         intel_init_clock_gating(dev_priv);
14926 }
14927
14928 /*
14929  * Calculate what we think the watermarks should be for the state we've read
14930  * out of the hardware and then immediately program those watermarks so that
14931  * we ensure the hardware settings match our internal state.
14932  *
14933  * We can calculate what we think WM's should be by creating a duplicate of the
14934  * current state (which was constructed during hardware readout) and running it
14935  * through the atomic check code to calculate new watermark values in the
14936  * state object.
14937  */
14938 static void sanitize_watermarks(struct drm_device *dev)
14939 {
14940         struct drm_i915_private *dev_priv = to_i915(dev);
14941         struct drm_atomic_state *state;
14942         struct intel_atomic_state *intel_state;
14943         struct drm_crtc *crtc;
14944         struct drm_crtc_state *cstate;
14945         struct drm_modeset_acquire_ctx ctx;
14946         int ret;
14947         int i;
14948
14949         /* Only supported on platforms that use atomic watermark design */
14950         if (!dev_priv->display.optimize_watermarks)
14951                 return;
14952
14953         /*
14954          * We need to hold connection_mutex before calling duplicate_state so
14955          * that the connector loop is protected.
14956          */
14957         drm_modeset_acquire_init(&ctx, 0);
14958 retry:
14959         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14960         if (ret == -EDEADLK) {
14961                 drm_modeset_backoff(&ctx);
14962                 goto retry;
14963         } else if (WARN_ON(ret)) {
14964                 goto fail;
14965         }
14966
14967         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14968         if (WARN_ON(IS_ERR(state)))
14969                 goto fail;
14970
14971         intel_state = to_intel_atomic_state(state);
14972
14973         /*
14974          * Hardware readout is the only time we don't want to calculate
14975          * intermediate watermarks (since we don't trust the current
14976          * watermarks).
14977          */
14978         if (!HAS_GMCH_DISPLAY(dev_priv))
14979                 intel_state->skip_intermediate_wm = true;
14980
14981         ret = intel_atomic_check(dev, state);
14982         if (ret) {
14983                 /*
14984                  * If we fail here, it means that the hardware appears to be
14985                  * programmed in a way that shouldn't be possible, given our
14986                  * understanding of watermark requirements.  This might mean a
14987                  * mistake in the hardware readout code or a mistake in the
14988                  * watermark calculations for a given platform.  Raise a WARN
14989                  * so that this is noticeable.
14990                  *
14991                  * If this actually happens, we'll have to just leave the
14992                  * BIOS-programmed watermarks untouched and hope for the best.
14993                  */
14994                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14995                 goto put_state;
14996         }
14997
14998         /* Write calculated watermark values back */
14999         for_each_new_crtc_in_state(state, crtc, cstate, i) {
15000                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15001
15002                 cs->wm.need_postvbl_update = true;
15003                 dev_priv->display.optimize_watermarks(intel_state, cs);
15004         }
15005
15006 put_state:
15007         drm_atomic_state_put(state);
15008 fail:
15009         drm_modeset_drop_locks(&ctx);
15010         drm_modeset_acquire_fini(&ctx);
15011 }
15012
15013 int intel_modeset_init(struct drm_device *dev)
15014 {
15015         struct drm_i915_private *dev_priv = to_i915(dev);
15016         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15017         enum pipe pipe;
15018         struct intel_crtc *crtc;
15019
15020         drm_mode_config_init(dev);
15021
15022         dev->mode_config.min_width = 0;
15023         dev->mode_config.min_height = 0;
15024
15025         dev->mode_config.preferred_depth = 24;
15026         dev->mode_config.prefer_shadow = 1;
15027
15028         dev->mode_config.allow_fb_modifiers = true;
15029
15030         dev->mode_config.funcs = &intel_mode_funcs;
15031
15032         init_llist_head(&dev_priv->atomic_helper.free_list);
15033         INIT_WORK(&dev_priv->atomic_helper.free_work,
15034                   intel_atomic_helper_free_state_worker);
15035
15036         intel_init_quirks(dev);
15037
15038         intel_init_pm(dev_priv);
15039
15040         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15041                 return 0;
15042
15043         /*
15044          * There may be no VBT; and if the BIOS enabled SSC we can
15045          * just keep using it to avoid unnecessary flicker.  Whereas if the
15046          * BIOS isn't using it, don't assume it will work even if the VBT
15047          * indicates as much.
15048          */
15049         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15050                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15051                                             DREF_SSC1_ENABLE);
15052
15053                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15054                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15055                                      bios_lvds_use_ssc ? "en" : "dis",
15056                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15057                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15058                 }
15059         }
15060
15061         if (IS_GEN2(dev_priv)) {
15062                 dev->mode_config.max_width = 2048;
15063                 dev->mode_config.max_height = 2048;
15064         } else if (IS_GEN3(dev_priv)) {
15065                 dev->mode_config.max_width = 4096;
15066                 dev->mode_config.max_height = 4096;
15067         } else {
15068                 dev->mode_config.max_width = 8192;
15069                 dev->mode_config.max_height = 8192;
15070         }
15071
15072         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15073                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15074                 dev->mode_config.cursor_height = 1023;
15075         } else if (IS_GEN2(dev_priv)) {
15076                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15077                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15078         } else {
15079                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15080                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15081         }
15082
15083         dev->mode_config.fb_base = ggtt->mappable_base;
15084
15085         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15086                       INTEL_INFO(dev_priv)->num_pipes,
15087                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15088
15089         for_each_pipe(dev_priv, pipe) {
15090                 int ret;
15091
15092                 ret = intel_crtc_init(dev_priv, pipe);
15093                 if (ret) {
15094                         drm_mode_config_cleanup(dev);
15095                         return ret;
15096                 }
15097         }
15098
15099         intel_shared_dpll_init(dev);
15100
15101         intel_update_czclk(dev_priv);
15102         intel_modeset_init_hw(dev);
15103
15104         if (dev_priv->max_cdclk_freq == 0)
15105                 intel_update_max_cdclk(dev_priv);
15106
15107         /* Just disable it once at startup */
15108         i915_disable_vga(dev_priv);
15109         intel_setup_outputs(dev_priv);
15110
15111         drm_modeset_lock_all(dev);
15112         intel_modeset_setup_hw_state(dev);
15113         drm_modeset_unlock_all(dev);
15114
15115         for_each_intel_crtc(dev, crtc) {
15116                 struct intel_initial_plane_config plane_config = {};
15117
15118                 if (!crtc->active)
15119                         continue;
15120
15121                 /*
15122                  * Note that reserving the BIOS fb up front prevents us
15123                  * from stuffing other stolen allocations like the ring
15124                  * on top.  This prevents some ugliness at boot time, and
15125                  * can even allow for smooth boot transitions if the BIOS
15126                  * fb is large enough for the active pipe configuration.
15127                  */
15128                 dev_priv->display.get_initial_plane_config(crtc,
15129                                                            &plane_config);
15130
15131                 /*
15132                  * If the fb is shared between multiple heads, we'll
15133                  * just get the first one.
15134                  */
15135                 intel_find_initial_plane_obj(crtc, &plane_config);
15136         }
15137
15138         /*
15139          * Make sure hardware watermarks really match the state we read out.
15140          * Note that we need to do this after reconstructing the BIOS fb's
15141          * since the watermark calculation done here will use pstate->fb.
15142          */
15143         if (!HAS_GMCH_DISPLAY(dev_priv))
15144                 sanitize_watermarks(dev);
15145
15146         return 0;
15147 }
15148
15149 static void intel_enable_pipe_a(struct drm_device *dev)
15150 {
15151         struct intel_connector *connector;
15152         struct drm_connector_list_iter conn_iter;
15153         struct drm_connector *crt = NULL;
15154         struct intel_load_detect_pipe load_detect_temp;
15155         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15156         int ret;
15157
15158         /* We can't just switch on the pipe A, we need to set things up with a
15159          * proper mode and output configuration. As a gross hack, enable pipe A
15160          * by enabling the load detect pipe once. */
15161         drm_connector_list_iter_begin(dev, &conn_iter);
15162         for_each_intel_connector_iter(connector, &conn_iter) {
15163                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15164                         crt = &connector->base;
15165                         break;
15166                 }
15167         }
15168         drm_connector_list_iter_end(&conn_iter);
15169
15170         if (!crt)
15171                 return;
15172
15173         ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
15174         WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
15175
15176         if (ret > 0)
15177                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15178 }
15179
15180 static bool
15181 intel_check_plane_mapping(struct intel_crtc *crtc)
15182 {
15183         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15184         u32 val;
15185
15186         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15187                 return true;
15188
15189         val = I915_READ(DSPCNTR(!crtc->plane));
15190
15191         if ((val & DISPLAY_PLANE_ENABLE) &&
15192             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15193                 return false;
15194
15195         return true;
15196 }
15197
15198 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15199 {
15200         struct drm_device *dev = crtc->base.dev;
15201         struct intel_encoder *encoder;
15202
15203         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15204                 return true;
15205
15206         return false;
15207 }
15208
15209 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15210 {
15211         struct drm_device *dev = encoder->base.dev;
15212         struct intel_connector *connector;
15213
15214         for_each_connector_on_encoder(dev, &encoder->base, connector)
15215                 return connector;
15216
15217         return NULL;
15218 }
15219
15220 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15221                               enum transcoder pch_transcoder)
15222 {
15223         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15224                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15225 }
15226
15227 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15228 {
15229         struct drm_device *dev = crtc->base.dev;
15230         struct drm_i915_private *dev_priv = to_i915(dev);
15231         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15232
15233         /* Clear any frame start delays used for debugging left by the BIOS */
15234         if (!transcoder_is_dsi(cpu_transcoder)) {
15235                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15236
15237                 I915_WRITE(reg,
15238                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15239         }
15240
15241         /* restore vblank interrupts to correct state */
15242         drm_crtc_vblank_reset(&crtc->base);
15243         if (crtc->active) {
15244                 struct intel_plane *plane;
15245
15246                 drm_crtc_vblank_on(&crtc->base);
15247
15248                 /* Disable everything but the primary plane */
15249                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15250                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15251                                 continue;
15252
15253                         trace_intel_disable_plane(&plane->base, crtc);
15254                         plane->disable_plane(plane, crtc);
15255                 }
15256         }
15257
15258         /* We need to sanitize the plane -> pipe mapping first because this will
15259          * disable the crtc (and hence change the state) if it is wrong. Note
15260          * that gen4+ has a fixed plane -> pipe mapping.  */
15261         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15262                 bool plane;
15263
15264                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15265                               crtc->base.base.id, crtc->base.name);
15266
15267                 /* Pipe has the wrong plane attached and the plane is active.
15268                  * Temporarily change the plane mapping and disable everything
15269                  * ...  */
15270                 plane = crtc->plane;
15271                 crtc->base.primary->state->visible = true;
15272                 crtc->plane = !plane;
15273                 intel_crtc_disable_noatomic(&crtc->base);
15274                 crtc->plane = plane;
15275         }
15276
15277         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15278             crtc->pipe == PIPE_A && !crtc->active) {
15279                 /* BIOS forgot to enable pipe A, this mostly happens after
15280                  * resume. Force-enable the pipe to fix this, the update_dpms
15281                  * call below we restore the pipe to the right state, but leave
15282                  * the required bits on. */
15283                 intel_enable_pipe_a(dev);
15284         }
15285
15286         /* Adjust the state of the output pipe according to whether we
15287          * have active connectors/encoders. */
15288         if (crtc->active && !intel_crtc_has_encoders(crtc))
15289                 intel_crtc_disable_noatomic(&crtc->base);
15290
15291         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15292                 /*
15293                  * We start out with underrun reporting disabled to avoid races.
15294                  * For correct bookkeeping mark this on active crtcs.
15295                  *
15296                  * Also on gmch platforms we dont have any hardware bits to
15297                  * disable the underrun reporting. Which means we need to start
15298                  * out with underrun reporting disabled also on inactive pipes,
15299                  * since otherwise we'll complain about the garbage we read when
15300                  * e.g. coming up after runtime pm.
15301                  *
15302                  * No protection against concurrent access is required - at
15303                  * worst a fifo underrun happens which also sets this to false.
15304                  */
15305                 crtc->cpu_fifo_underrun_disabled = true;
15306                 /*
15307                  * We track the PCH trancoder underrun reporting state
15308                  * within the crtc. With crtc for pipe A housing the underrun
15309                  * reporting state for PCH transcoder A, crtc for pipe B housing
15310                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15311                  * and marking underrun reporting as disabled for the non-existing
15312                  * PCH transcoders B and C would prevent enabling the south
15313                  * error interrupt (see cpt_can_enable_serr_int()).
15314                  */
15315                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15316                         crtc->pch_fifo_underrun_disabled = true;
15317         }
15318 }
15319
15320 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15321 {
15322         struct intel_connector *connector;
15323
15324         /* We need to check both for a crtc link (meaning that the
15325          * encoder is active and trying to read from a pipe) and the
15326          * pipe itself being active. */
15327         bool has_active_crtc = encoder->base.crtc &&
15328                 to_intel_crtc(encoder->base.crtc)->active;
15329
15330         connector = intel_encoder_find_connector(encoder);
15331         if (connector && !has_active_crtc) {
15332                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15333                               encoder->base.base.id,
15334                               encoder->base.name);
15335
15336                 /* Connector is active, but has no active pipe. This is
15337                  * fallout from our resume register restoring. Disable
15338                  * the encoder manually again. */
15339                 if (encoder->base.crtc) {
15340                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15341
15342                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15343                                       encoder->base.base.id,
15344                                       encoder->base.name);
15345                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15346                         if (encoder->post_disable)
15347                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15348                 }
15349                 encoder->base.crtc = NULL;
15350
15351                 /* Inconsistent output/port/pipe state happens presumably due to
15352                  * a bug in one of the get_hw_state functions. Or someplace else
15353                  * in our code, like the register restore mess on resume. Clamp
15354                  * things to off as a safer default. */
15355
15356                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15357                 connector->base.encoder = NULL;
15358         }
15359         /* Enabled encoders without active connectors will be fixed in
15360          * the crtc fixup. */
15361 }
15362
15363 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15364 {
15365         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15366
15367         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15368                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15369                 i915_disable_vga(dev_priv);
15370         }
15371 }
15372
15373 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15374 {
15375         /* This function can be called both from intel_modeset_setup_hw_state or
15376          * at a very early point in our resume sequence, where the power well
15377          * structures are not yet restored. Since this function is at a very
15378          * paranoid "someone might have enabled VGA while we were not looking"
15379          * level, just check if the power well is enabled instead of trying to
15380          * follow the "don't touch the power well if we don't need it" policy
15381          * the rest of the driver uses. */
15382         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15383                 return;
15384
15385         i915_redisable_vga_power_on(dev_priv);
15386
15387         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15388 }
15389
15390 static bool primary_get_hw_state(struct intel_plane *plane)
15391 {
15392         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15393
15394         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15395 }
15396
15397 /* FIXME read out full plane state for all planes */
15398 static void readout_plane_state(struct intel_crtc *crtc)
15399 {
15400         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15401         bool visible;
15402
15403         visible = crtc->active && primary_get_hw_state(primary);
15404
15405         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15406                                 to_intel_plane_state(primary->base.state),
15407                                 visible);
15408 }
15409
15410 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15411 {
15412         struct drm_i915_private *dev_priv = to_i915(dev);
15413         enum pipe pipe;
15414         struct intel_crtc *crtc;
15415         struct intel_encoder *encoder;
15416         struct intel_connector *connector;
15417         struct drm_connector_list_iter conn_iter;
15418         int i;
15419
15420         dev_priv->active_crtcs = 0;
15421
15422         for_each_intel_crtc(dev, crtc) {
15423                 struct intel_crtc_state *crtc_state =
15424                         to_intel_crtc_state(crtc->base.state);
15425
15426                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15427                 memset(crtc_state, 0, sizeof(*crtc_state));
15428                 crtc_state->base.crtc = &crtc->base;
15429
15430                 crtc_state->base.active = crtc_state->base.enable =
15431                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15432
15433                 crtc->base.enabled = crtc_state->base.enable;
15434                 crtc->active = crtc_state->base.active;
15435
15436                 if (crtc_state->base.active)
15437                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15438
15439                 readout_plane_state(crtc);
15440
15441                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15442                               crtc->base.base.id, crtc->base.name,
15443                               enableddisabled(crtc_state->base.active));
15444         }
15445
15446         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15447                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15448
15449                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15450                                                   &pll->state.hw_state);
15451                 pll->state.crtc_mask = 0;
15452                 for_each_intel_crtc(dev, crtc) {
15453                         struct intel_crtc_state *crtc_state =
15454                                 to_intel_crtc_state(crtc->base.state);
15455
15456                         if (crtc_state->base.active &&
15457                             crtc_state->shared_dpll == pll)
15458                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15459                 }
15460                 pll->active_mask = pll->state.crtc_mask;
15461
15462                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15463                               pll->name, pll->state.crtc_mask, pll->on);
15464         }
15465
15466         for_each_intel_encoder(dev, encoder) {
15467                 pipe = 0;
15468
15469                 if (encoder->get_hw_state(encoder, &pipe)) {
15470                         struct intel_crtc_state *crtc_state;
15471
15472                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15473                         crtc_state = to_intel_crtc_state(crtc->base.state);
15474
15475                         encoder->base.crtc = &crtc->base;
15476                         crtc_state->output_types |= 1 << encoder->type;
15477                         encoder->get_config(encoder, crtc_state);
15478                 } else {
15479                         encoder->base.crtc = NULL;
15480                 }
15481
15482                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15483                               encoder->base.base.id, encoder->base.name,
15484                               enableddisabled(encoder->base.crtc),
15485                               pipe_name(pipe));
15486         }
15487
15488         drm_connector_list_iter_begin(dev, &conn_iter);
15489         for_each_intel_connector_iter(connector, &conn_iter) {
15490                 if (connector->get_hw_state(connector)) {
15491                         connector->base.dpms = DRM_MODE_DPMS_ON;
15492
15493                         encoder = connector->encoder;
15494                         connector->base.encoder = &encoder->base;
15495
15496                         if (encoder->base.crtc &&
15497                             encoder->base.crtc->state->active) {
15498                                 /*
15499                                  * This has to be done during hardware readout
15500                                  * because anything calling .crtc_disable may
15501                                  * rely on the connector_mask being accurate.
15502                                  */
15503                                 encoder->base.crtc->state->connector_mask |=
15504                                         1 << drm_connector_index(&connector->base);
15505                                 encoder->base.crtc->state->encoder_mask |=
15506                                         1 << drm_encoder_index(&encoder->base);
15507                         }
15508
15509                 } else {
15510                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15511                         connector->base.encoder = NULL;
15512                 }
15513                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15514                               connector->base.base.id, connector->base.name,
15515                               enableddisabled(connector->base.encoder));
15516         }
15517         drm_connector_list_iter_end(&conn_iter);
15518
15519         for_each_intel_crtc(dev, crtc) {
15520                 struct intel_crtc_state *crtc_state =
15521                         to_intel_crtc_state(crtc->base.state);
15522                 int pixclk = 0;
15523
15524                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15525                 if (crtc_state->base.active) {
15526                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15527                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15528                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15529
15530                         /*
15531                          * The initial mode needs to be set in order to keep
15532                          * the atomic core happy. It wants a valid mode if the
15533                          * crtc's enabled, so we do the above call.
15534                          *
15535                          * But we don't set all the derived state fully, hence
15536                          * set a flag to indicate that a full recalculation is
15537                          * needed on the next commit.
15538                          */
15539                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15540
15541                         intel_crtc_compute_pixel_rate(crtc_state);
15542
15543                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15544                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15545                                 pixclk = crtc_state->pixel_rate;
15546                         else
15547                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15548
15549                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15550                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15551                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15552
15553                         drm_calc_timestamping_constants(&crtc->base,
15554                                                         &crtc_state->base.adjusted_mode);
15555                         update_scanline_offset(crtc);
15556                 }
15557
15558                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15559
15560                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15561         }
15562 }
15563
15564 static void
15565 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15566 {
15567         struct intel_encoder *encoder;
15568
15569         for_each_intel_encoder(&dev_priv->drm, encoder) {
15570                 u64 get_domains;
15571                 enum intel_display_power_domain domain;
15572
15573                 if (!encoder->get_power_domains)
15574                         continue;
15575
15576                 get_domains = encoder->get_power_domains(encoder);
15577                 for_each_power_domain(domain, get_domains)
15578                         intel_display_power_get(dev_priv, domain);
15579         }
15580 }
15581
15582 /* Scan out the current hw modeset state,
15583  * and sanitizes it to the current state
15584  */
15585 static void
15586 intel_modeset_setup_hw_state(struct drm_device *dev)
15587 {
15588         struct drm_i915_private *dev_priv = to_i915(dev);
15589         enum pipe pipe;
15590         struct intel_crtc *crtc;
15591         struct intel_encoder *encoder;
15592         int i;
15593
15594         intel_modeset_readout_hw_state(dev);
15595
15596         /* HW state is read out, now we need to sanitize this mess. */
15597         get_encoder_power_domains(dev_priv);
15598
15599         for_each_intel_encoder(dev, encoder) {
15600                 intel_sanitize_encoder(encoder);
15601         }
15602
15603         for_each_pipe(dev_priv, pipe) {
15604                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15605
15606                 intel_sanitize_crtc(crtc);
15607                 intel_dump_pipe_config(crtc, crtc->config,
15608                                        "[setup_hw_state]");
15609         }
15610
15611         intel_modeset_update_connector_atomic_state(dev);
15612
15613         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15614                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15615
15616                 if (!pll->on || pll->active_mask)
15617                         continue;
15618
15619                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15620
15621                 pll->funcs.disable(dev_priv, pll);
15622                 pll->on = false;
15623         }
15624
15625         if (IS_G4X(dev_priv)) {
15626                 g4x_wm_get_hw_state(dev);
15627                 g4x_wm_sanitize(dev_priv);
15628         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15629                 vlv_wm_get_hw_state(dev);
15630                 vlv_wm_sanitize(dev_priv);
15631         } else if (IS_GEN9(dev_priv)) {
15632                 skl_wm_get_hw_state(dev);
15633         } else if (HAS_PCH_SPLIT(dev_priv)) {
15634                 ilk_wm_get_hw_state(dev);
15635         }
15636
15637         for_each_intel_crtc(dev, crtc) {
15638                 u64 put_domains;
15639
15640                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15641                 if (WARN_ON(put_domains))
15642                         modeset_put_power_domains(dev_priv, put_domains);
15643         }
15644         intel_display_set_init_power(dev_priv, false);
15645
15646         intel_power_domains_verify_state(dev_priv);
15647
15648         intel_fbc_init_pipe_state(dev_priv);
15649 }
15650
15651 void intel_display_resume(struct drm_device *dev)
15652 {
15653         struct drm_i915_private *dev_priv = to_i915(dev);
15654         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15655         struct drm_modeset_acquire_ctx ctx;
15656         int ret;
15657
15658         dev_priv->modeset_restore_state = NULL;
15659         if (state)
15660                 state->acquire_ctx = &ctx;
15661
15662         drm_modeset_acquire_init(&ctx, 0);
15663
15664         while (1) {
15665                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15666                 if (ret != -EDEADLK)
15667                         break;
15668
15669                 drm_modeset_backoff(&ctx);
15670         }
15671
15672         if (!ret)
15673                 ret = __intel_display_resume(dev, state, &ctx);
15674
15675         drm_modeset_drop_locks(&ctx);
15676         drm_modeset_acquire_fini(&ctx);
15677
15678         if (ret)
15679                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15680         if (state)
15681                 drm_atomic_state_put(state);
15682 }
15683
15684 void intel_modeset_gem_init(struct drm_device *dev)
15685 {
15686         struct drm_i915_private *dev_priv = to_i915(dev);
15687
15688         intel_init_gt_powersave(dev_priv);
15689
15690         intel_setup_overlay(dev_priv);
15691 }
15692
15693 int intel_connector_register(struct drm_connector *connector)
15694 {
15695         struct intel_connector *intel_connector = to_intel_connector(connector);
15696         int ret;
15697
15698         ret = intel_backlight_device_register(intel_connector);
15699         if (ret)
15700                 goto err;
15701
15702         return 0;
15703
15704 err:
15705         return ret;
15706 }
15707
15708 void intel_connector_unregister(struct drm_connector *connector)
15709 {
15710         struct intel_connector *intel_connector = to_intel_connector(connector);
15711
15712         intel_backlight_device_unregister(intel_connector);
15713         intel_panel_destroy_backlight(connector);
15714 }
15715
15716 void intel_modeset_cleanup(struct drm_device *dev)
15717 {
15718         struct drm_i915_private *dev_priv = to_i915(dev);
15719
15720         flush_work(&dev_priv->atomic_helper.free_work);
15721         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15722
15723         intel_disable_gt_powersave(dev_priv);
15724
15725         /*
15726          * Interrupts and polling as the first thing to avoid creating havoc.
15727          * Too much stuff here (turning of connectors, ...) would
15728          * experience fancy races otherwise.
15729          */
15730         intel_irq_uninstall(dev_priv);
15731
15732         /*
15733          * Due to the hpd irq storm handling the hotplug work can re-arm the
15734          * poll handlers. Hence disable polling after hpd handling is shut down.
15735          */
15736         drm_kms_helper_poll_fini(dev);
15737
15738         intel_unregister_dsm_handler();
15739
15740         intel_fbc_global_disable(dev_priv);
15741
15742         /* flush any delayed tasks or pending work */
15743         flush_scheduled_work();
15744
15745         drm_mode_config_cleanup(dev);
15746
15747         intel_cleanup_overlay(dev_priv);
15748
15749         intel_cleanup_gt_powersave(dev_priv);
15750
15751         intel_teardown_gmbus(dev_priv);
15752 }
15753
15754 void intel_connector_attach_encoder(struct intel_connector *connector,
15755                                     struct intel_encoder *encoder)
15756 {
15757         connector->encoder = encoder;
15758         drm_mode_connector_attach_encoder(&connector->base,
15759                                           &encoder->base);
15760 }
15761
15762 /*
15763  * set vga decode state - true == enable VGA decode
15764  */
15765 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15766 {
15767         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15768         u16 gmch_ctrl;
15769
15770         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15771                 DRM_ERROR("failed to read control word\n");
15772                 return -EIO;
15773         }
15774
15775         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15776                 return 0;
15777
15778         if (state)
15779                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15780         else
15781                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15782
15783         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15784                 DRM_ERROR("failed to write control word\n");
15785                 return -EIO;
15786         }
15787
15788         return 0;
15789 }
15790
15791 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15792
15793 struct intel_display_error_state {
15794
15795         u32 power_well_driver;
15796
15797         int num_transcoders;
15798
15799         struct intel_cursor_error_state {
15800                 u32 control;
15801                 u32 position;
15802                 u32 base;
15803                 u32 size;
15804         } cursor[I915_MAX_PIPES];
15805
15806         struct intel_pipe_error_state {
15807                 bool power_domain_on;
15808                 u32 source;
15809                 u32 stat;
15810         } pipe[I915_MAX_PIPES];
15811
15812         struct intel_plane_error_state {
15813                 u32 control;
15814                 u32 stride;
15815                 u32 size;
15816                 u32 pos;
15817                 u32 addr;
15818                 u32 surface;
15819                 u32 tile_offset;
15820         } plane[I915_MAX_PIPES];
15821
15822         struct intel_transcoder_error_state {
15823                 bool power_domain_on;
15824                 enum transcoder cpu_transcoder;
15825
15826                 u32 conf;
15827
15828                 u32 htotal;
15829                 u32 hblank;
15830                 u32 hsync;
15831                 u32 vtotal;
15832                 u32 vblank;
15833                 u32 vsync;
15834         } transcoder[4];
15835 };
15836
15837 struct intel_display_error_state *
15838 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15839 {
15840         struct intel_display_error_state *error;
15841         int transcoders[] = {
15842                 TRANSCODER_A,
15843                 TRANSCODER_B,
15844                 TRANSCODER_C,
15845                 TRANSCODER_EDP,
15846         };
15847         int i;
15848
15849         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15850                 return NULL;
15851
15852         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15853         if (error == NULL)
15854                 return NULL;
15855
15856         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15857                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15858
15859         for_each_pipe(dev_priv, i) {
15860                 error->pipe[i].power_domain_on =
15861                         __intel_display_power_is_enabled(dev_priv,
15862                                                          POWER_DOMAIN_PIPE(i));
15863                 if (!error->pipe[i].power_domain_on)
15864                         continue;
15865
15866                 error->cursor[i].control = I915_READ(CURCNTR(i));
15867                 error->cursor[i].position = I915_READ(CURPOS(i));
15868                 error->cursor[i].base = I915_READ(CURBASE(i));
15869
15870                 error->plane[i].control = I915_READ(DSPCNTR(i));
15871                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15872                 if (INTEL_GEN(dev_priv) <= 3) {
15873                         error->plane[i].size = I915_READ(DSPSIZE(i));
15874                         error->plane[i].pos = I915_READ(DSPPOS(i));
15875                 }
15876                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15877                         error->plane[i].addr = I915_READ(DSPADDR(i));
15878                 if (INTEL_GEN(dev_priv) >= 4) {
15879                         error->plane[i].surface = I915_READ(DSPSURF(i));
15880                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15881                 }
15882
15883                 error->pipe[i].source = I915_READ(PIPESRC(i));
15884
15885                 if (HAS_GMCH_DISPLAY(dev_priv))
15886                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15887         }
15888
15889         /* Note: this does not include DSI transcoders. */
15890         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15891         if (HAS_DDI(dev_priv))
15892                 error->num_transcoders++; /* Account for eDP. */
15893
15894         for (i = 0; i < error->num_transcoders; i++) {
15895                 enum transcoder cpu_transcoder = transcoders[i];
15896
15897                 error->transcoder[i].power_domain_on =
15898                         __intel_display_power_is_enabled(dev_priv,
15899                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15900                 if (!error->transcoder[i].power_domain_on)
15901                         continue;
15902
15903                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15904
15905                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15906                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15907                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15908                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15909                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15910                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15911                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15912         }
15913
15914         return error;
15915 }
15916
15917 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15918
15919 void
15920 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15921                                 struct intel_display_error_state *error)
15922 {
15923         struct drm_i915_private *dev_priv = m->i915;
15924         int i;
15925
15926         if (!error)
15927                 return;
15928
15929         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15930         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15931                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15932                            error->power_well_driver);
15933         for_each_pipe(dev_priv, i) {
15934                 err_printf(m, "Pipe [%d]:\n", i);
15935                 err_printf(m, "  Power: %s\n",
15936                            onoff(error->pipe[i].power_domain_on));
15937                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15938                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15939
15940                 err_printf(m, "Plane [%d]:\n", i);
15941                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15942                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15943                 if (INTEL_GEN(dev_priv) <= 3) {
15944                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15945                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15946                 }
15947                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15948                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15949                 if (INTEL_GEN(dev_priv) >= 4) {
15950                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15951                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15952                 }
15953
15954                 err_printf(m, "Cursor [%d]:\n", i);
15955                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15956                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15957                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15958         }
15959
15960         for (i = 0; i < error->num_transcoders; i++) {
15961                 err_printf(m, "CPU transcoder: %s\n",
15962                            transcoder_name(error->transcoder[i].cpu_transcoder));
15963                 err_printf(m, "  Power: %s\n",
15964                            onoff(error->transcoder[i].power_domain_on));
15965                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15966                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15967                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15968                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15969                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15970                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15971                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15972         }
15973 }
15974
15975 #endif