drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 struct icl_combo_phy_ddi_buf_trans {
 497         u32 dw2_swing_select;
 498         u32 dw2_swing_scalar;
 499         u32 dw4_scaling;
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 0.85V for DP */
 503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 504                                 /* Voltage mV  db    */
 505         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 506         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 507         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 508         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 509         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 510         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 511         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 512         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 513         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 514         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 515 };
 516
 517 /* FIXME - After table is updated in Bspec */
 518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 520                                 /* Voltage mV  db    */
 521         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 522         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 523         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 524         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 525         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 527         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 528         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 530         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 531 };
 532
 533 /* Voltage Swing Programming for VccIO 0.95V for DP */
 534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 535                                 /* Voltage mV  db    */
 536         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 537         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 538         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 539         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 540         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 541         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 542         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 543         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 544         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 545         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 546 };
 547
 548 /* FIXME - After table is updated in Bspec */
 549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 551                                 /* Voltage mV  db    */
 552         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 553         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 554         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 555         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 556         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 558         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 559         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 561         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 562 };
 563
 564 /* Voltage Swing Programming for VccIO 1.05V for DP */
 565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 566                                 /* Voltage mV  db    */
 567         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 568         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 569         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 570         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 571         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 572         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 573         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 574         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 575         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 576         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 577 };
 578
 579 /* FIXME - After table is updated in Bspec */
 580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 582                                 /* Voltage mV  db    */
 583         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 584         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 585         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 586         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 587         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 589         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 590         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 592         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 593 };
 594
 595 struct icl_mg_phy_ddi_buf_trans {
 596         u32 cri_txdeemph_override_5_0;
 597         u32 cri_txdeemph_override_11_6;
 598         u32 cri_txdeemph_override_17_12;
 599 };
 600
 601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 602                                 /* Voltage swing  pre-emphasis */
 603         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 604         { 0x0, 0x23, 0x08 },    /* 0              1   */
 605         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 606         { 0x0, 0x00, 0x00 },    /* 0              3   */
 607         { 0x0, 0x23, 0x00 },    /* 1              0   */
 608         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 609         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 610         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 611         { 0x0, 0x33, 0x0C },    /* 2              1   */
 612         { 0x0, 0x00, 0x00 },    /* 3              0   */
 613 };
 614
 615 static const struct ddi_buf_trans *
 616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (dev_priv->vbt.edp.low_vswing) {
 619                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 620                 return bdw_ddi_translations_edp;
 621         } else {
 622                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 623                 return bdw_ddi_translations_dp;
 624         }
 625 }
 626
 627 static const struct ddi_buf_trans *
 628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 629 {
 630         if (IS_SKL_ULX(dev_priv)) {
 631                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 632                 return skl_y_ddi_translations_dp;
 633         } else if (IS_SKL_ULT(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 635                 return skl_u_ddi_translations_dp;
 636         } else {
 637                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 638                 return skl_ddi_translations_dp;
 639         }
 640 }
 641
 642 static const struct ddi_buf_trans *
 643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 644 {
 645         if (IS_KBL_ULX(dev_priv)) {
 646                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 647                 return kbl_y_ddi_translations_dp;
 648         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 649                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 650                 return kbl_u_ddi_translations_dp;
 651         } else {
 652                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 653                 return kbl_ddi_translations_dp;
 654         }
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 659 {
 660         if (dev_priv->vbt.edp.low_vswing) {
 661                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 663                         return skl_y_ddi_translations_edp;
 664                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 665                            IS_CFL_ULT(dev_priv)) {
 666                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 667                         return skl_u_ddi_translations_edp;
 668                 } else {
 669                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 670                         return skl_ddi_translations_edp;
 671                 }
 672         }
 673
 674         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 675                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 676         else
 677                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct ddi_buf_trans *
 681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 684                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 685                 return skl_y_ddi_translations_hdmi;
 686         } else {
 687                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 688                 return skl_ddi_translations_hdmi;
 689         }
 690 }
 691
 692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 693 {
 694         /* Only DDIA and DDIE can select the 10th register with DP */
 695         if (port == PORT_A || port == PORT_E)
 696                 return min(n_entries, 10);
 697         else
 698                 return min(n_entries, 9);
 699 }
 700
 701 static const struct ddi_buf_trans *
 702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 703                            enum port port, int *n_entries)
 704 {
 705         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 706                 const struct ddi_buf_trans *ddi_translations =
 707                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 708                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 709                 return ddi_translations;
 710         } else if (IS_SKYLAKE(dev_priv)) {
 711                 const struct ddi_buf_trans *ddi_translations =
 712                         skl_get_buf_trans_dp(dev_priv, n_entries);
 713                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 714                 return ddi_translations;
 715         } else if (IS_BROADWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 717                 return  bdw_ddi_translations_dp;
 718         } else if (IS_HASWELL(dev_priv)) {
 719                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 720                 return hsw_ddi_translations_dp;
 721         }
 722
 723         *n_entries = 0;
 724         return NULL;
 725 }
 726
 727 static const struct ddi_buf_trans *
 728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 729                             enum port port, int *n_entries)
 730 {
 731         if (IS_GEN9_BC(dev_priv)) {
 732                 const struct ddi_buf_trans *ddi_translations =
 733                         skl_get_buf_trans_edp(dev_priv, n_entries);
 734                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 735                 return ddi_translations;
 736         } else if (IS_BROADWELL(dev_priv)) {
 737                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 740                 return hsw_ddi_translations_dp;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct ddi_buf_trans *
 748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 749                             int *n_entries)
 750 {
 751         if (IS_BROADWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 753                 return bdw_ddi_translations_fdi;
 754         } else if (IS_HASWELL(dev_priv)) {
 755                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 756                 return hsw_ddi_translations_fdi;
 757         }
 758
 759         *n_entries = 0;
 760         return NULL;
 761 }
 762
 763 static const struct ddi_buf_trans *
 764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 765                              int *n_entries)
 766 {
 767         if (IS_GEN9_BC(dev_priv)) {
 768                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 771                 return bdw_ddi_translations_hdmi;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 774                 return hsw_ddi_translations_hdmi;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct bxt_ddi_buf_trans *
 782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 785         return bxt_ddi_translations_dp;
 786 }
 787
 788 static const struct bxt_ddi_buf_trans *
 789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 790 {
 791         if (dev_priv->vbt.edp.low_vswing) {
 792                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 793                 return bxt_ddi_translations_edp;
 794         }
 795
 796         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 803         return bxt_ddi_translations_hdmi;
 804 }
 805
 806 static const struct cnl_ddi_buf_trans *
 807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 808 {
 809         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 810
 811         if (voltage == VOLTAGE_INFO_0_85V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 813                 return cnl_ddi_translations_hdmi_0_85V;
 814         } else if (voltage == VOLTAGE_INFO_0_95V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 816                 return cnl_ddi_translations_hdmi_0_95V;
 817         } else if (voltage == VOLTAGE_INFO_1_05V) {
 818                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 819                 return cnl_ddi_translations_hdmi_1_05V;
 820         } else {
 821                 *n_entries = 1; /* shut up gcc */
 822                 MISSING_CASE(voltage);
 823         }
 824         return NULL;
 825 }
 826
 827 static const struct cnl_ddi_buf_trans *
 828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 829 {
 830         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 831
 832         if (voltage == VOLTAGE_INFO_0_85V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 834                 return cnl_ddi_translations_dp_0_85V;
 835         } else if (voltage == VOLTAGE_INFO_0_95V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 837                 return cnl_ddi_translations_dp_0_95V;
 838         } else if (voltage == VOLTAGE_INFO_1_05V) {
 839                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 840                 return cnl_ddi_translations_dp_1_05V;
 841         } else {
 842                 *n_entries = 1; /* shut up gcc */
 843                 MISSING_CASE(voltage);
 844         }
 845         return NULL;
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 850 {
 851         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 852
 853         if (dev_priv->vbt.edp.low_vswing) {
 854                 if (voltage == VOLTAGE_INFO_0_85V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 856                         return cnl_ddi_translations_edp_0_85V;
 857                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 859                         return cnl_ddi_translations_edp_0_95V;
 860                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 861                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 862                         return cnl_ddi_translations_edp_1_05V;
 863                 } else {
 864                         *n_entries = 1; /* shut up gcc */
 865                         MISSING_CASE(voltage);
 866                 }
 867                 return NULL;
 868         } else {
 869                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 870         }
 871 }
 872
 873 static const struct icl_combo_phy_ddi_buf_trans *
 874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 875                         int type, int *n_entries)
 876 {
 877         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 878
 879         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 880                 switch (voltage) {
 881                 case VOLTAGE_INFO_0_85V:
 882                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 883                         return icl_combo_phy_ddi_translations_edp_0_85V;
 884                 case VOLTAGE_INFO_0_95V:
 885                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 886                         return icl_combo_phy_ddi_translations_edp_0_95V;
 887                 case VOLTAGE_INFO_1_05V:
 888                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 889                         return icl_combo_phy_ddi_translations_edp_1_05V;
 890                 default:
 891                         MISSING_CASE(voltage);
 892                         return NULL;
 893                 }
 894         } else {
 895                 switch (voltage) {
 896                 case VOLTAGE_INFO_0_85V:
 897                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 898                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 899                 case VOLTAGE_INFO_0_95V:
 900                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 901                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 902                 case VOLTAGE_INFO_1_05V:
 903                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 904                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 905                 default:
 906                         MISSING_CASE(voltage);
 907                         return NULL;
 908                 }
 909         }
 910 }
 911
 912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 913 {
 914         int n_entries, level, default_entry;
 915
 916         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 917
 918         if (IS_CANNONLAKE(dev_priv)) {
 919                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 920                 default_entry = n_entries - 1;
 921         } else if (IS_GEN9_LP(dev_priv)) {
 922                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 923                 default_entry = n_entries - 1;
 924         } else if (IS_GEN9_BC(dev_priv)) {
 925                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 926                 default_entry = 8;
 927         } else if (IS_BROADWELL(dev_priv)) {
 928                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 929                 default_entry = 7;
 930         } else if (IS_HASWELL(dev_priv)) {
 931                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 932                 default_entry = 6;
 933         } else {
 934                 WARN(1, "ddi translation table missing\n");
 935                 return 0;
 936         }
 937
 938         /* Choose a good default if VBT is badly populated */
 939         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 940                 level = default_entry;
 941
 942         if (WARN_ON_ONCE(n_entries == 0))
 943                 return 0;
 944         if (WARN_ON_ONCE(level >= n_entries))
 945                 level = n_entries - 1;
 946
 947         return level;
 948 }
 949
 950 /*
 951  * Starting with Haswell, DDI port buffers must be programmed with correct
 952  * values in advance. This function programs the correct values for
 953  * DP/eDP/FDI use cases.
 954  */
 955 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 956                                          const struct intel_crtc_state *crtc_state)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 959         u32 iboost_bit = 0;
 960         int i, n_entries;
 961         enum port port = encoder->port;
 962         const struct ddi_buf_trans *ddi_translations;
 963
 964         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 965                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 966                                                                &n_entries);
 967         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 968                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 969                                                                &n_entries);
 970         else
 971                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 972                                                               &n_entries);
 973
 974         /* If we're boosting the current, set bit 31 of trans1 */
 975         if (IS_GEN9_BC(dev_priv) &&
 976             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 977                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 978
 979         for (i = 0; i < n_entries; i++) {
 980                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 981                            ddi_translations[i].trans1 | iboost_bit);
 982                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 983                            ddi_translations[i].trans2);
 984         }
 985 }
 986
 987 /*
 988  * Starting with Haswell, DDI port buffers must be programmed with correct
 989  * values in advance. This function programs the correct values for
 990  * HDMI/DVI use cases.
 991  */
 992 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 993                                            int level)
 994 {
 995         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 996         u32 iboost_bit = 0;
 997         int n_entries;
 998         enum port port = encoder->port;
 999         const struct ddi_buf_trans *ddi_translations;
1000
1001         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1002
1003         if (WARN_ON_ONCE(!ddi_translations))
1004                 return;
1005         if (WARN_ON_ONCE(level >= n_entries))
1006                 level = n_entries - 1;
1007
1008         /* If we're boosting the current, set bit 31 of trans1 */
1009         if (IS_GEN9_BC(dev_priv) &&
1010             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1011                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1012
1013         /* Entry 9 is for HDMI: */
1014         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1015                    ddi_translations[level].trans1 | iboost_bit);
1016         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1017                    ddi_translations[level].trans2);
1018 }
1019
1020 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1021                                     enum port port)
1022 {
1023         i915_reg_t reg = DDI_BUF_CTL(port);
1024         int i;
1025
1026         for (i = 0; i < 16; i++) {
1027                 udelay(1);
1028                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1029                         return;
1030         }
1031         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1032 }
1033
1034 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1035 {
1036         switch (pll->info->id) {
1037         case DPLL_ID_WRPLL1:
1038                 return PORT_CLK_SEL_WRPLL1;
1039         case DPLL_ID_WRPLL2:
1040                 return PORT_CLK_SEL_WRPLL2;
1041         case DPLL_ID_SPLL:
1042                 return PORT_CLK_SEL_SPLL;
1043         case DPLL_ID_LCPLL_810:
1044                 return PORT_CLK_SEL_LCPLL_810;
1045         case DPLL_ID_LCPLL_1350:
1046                 return PORT_CLK_SEL_LCPLL_1350;
1047         case DPLL_ID_LCPLL_2700:
1048                 return PORT_CLK_SEL_LCPLL_2700;
1049         default:
1050                 MISSING_CASE(pll->info->id);
1051                 return PORT_CLK_SEL_NONE;
1052         }
1053 }
1054
1055 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1056                                        const struct intel_shared_dpll *pll)
1057 {
1058         const enum intel_dpll_id id = pll->info->id;
1059
1060         switch (id) {
1061         default:
1062                 MISSING_CASE(id);
1063         case DPLL_ID_ICL_DPLL0:
1064         case DPLL_ID_ICL_DPLL1:
1065                 return DDI_CLK_SEL_NONE;
1066         case DPLL_ID_ICL_MGPLL1:
1067         case DPLL_ID_ICL_MGPLL2:
1068         case DPLL_ID_ICL_MGPLL3:
1069         case DPLL_ID_ICL_MGPLL4:
1070                 return DDI_CLK_SEL_MG;
1071         }
1072 }
1073
1074 /* Starting with Haswell, different DDI ports can work in FDI mode for
1075  * connection to the PCH-located connectors. For this, it is necessary to train
1076  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1077  *
1078  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1079  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1080  * DDI A (which is used for eDP)
1081  */
1082
1083 void hsw_fdi_link_train(struct intel_crtc *crtc,
1084                         const struct intel_crtc_state *crtc_state)
1085 {
1086         struct drm_device *dev = crtc->base.dev;
1087         struct drm_i915_private *dev_priv = to_i915(dev);
1088         struct intel_encoder *encoder;
1089         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1090
1091         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1092                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1093                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1094         }
1095
1096         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1097          * mode set "sequence for CRT port" document:
1098          * - TP1 to TP2 time with the default value
1099          * - FDI delay to 90h
1100          *
1101          * WaFDIAutoLinkSetTimingOverrride:hsw
1102          */
1103         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1104                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1105                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1106
1107         /* Enable the PCH Receiver FDI PLL */
1108         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1109                      FDI_RX_PLL_ENABLE |
1110                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1111         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1112         POSTING_READ(FDI_RX_CTL(PIPE_A));
1113         udelay(220);
1114
1115         /* Switch from Rawclk to PCDclk */
1116         rx_ctl_val |= FDI_PCDCLK;
1117         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1118
1119         /* Configure Port Clock Select */
1120         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1121         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1122         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1123
1124         /* Start the training iterating through available voltages and emphasis,
1125          * testing each value twice. */
1126         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1127                 /* Configure DP_TP_CTL with auto-training */
1128                 I915_WRITE(DP_TP_CTL(PORT_E),
1129                                         DP_TP_CTL_FDI_AUTOTRAIN |
1130                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1131                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1132                                         DP_TP_CTL_ENABLE);
1133
1134                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1135                  * DDI E does not support port reversal, the functionality is
1136                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1137                  * port reversal bit */
1138                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1139                            DDI_BUF_CTL_ENABLE |
1140                            ((crtc_state->fdi_lanes - 1) << 1) |
1141                            DDI_BUF_TRANS_SELECT(i / 2));
1142                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1143
1144                 udelay(600);
1145
1146                 /* Program PCH FDI Receiver TU */
1147                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1148
1149                 /* Enable PCH FDI Receiver with auto-training */
1150                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1151                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1152                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1153
1154                 /* Wait for FDI receiver lane calibration */
1155                 udelay(30);
1156
1157                 /* Unset FDI_RX_MISC pwrdn lanes */
1158                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1159                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1160                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1161                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1162
1163                 /* Wait for FDI auto training time */
1164                 udelay(5);
1165
1166                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1167                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1168                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1169                         break;
1170                 }
1171
1172                 /*
1173                  * Leave things enabled even if we failed to train FDI.
1174                  * Results in less fireworks from the state checker.
1175                  */
1176                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1177                         DRM_ERROR("FDI link training failed!\n");
1178                         break;
1179                 }
1180
1181                 rx_ctl_val &= ~FDI_RX_ENABLE;
1182                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1183                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1184
1185                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1186                 temp &= ~DDI_BUF_CTL_ENABLE;
1187                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1188                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1189
1190                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1191                 temp = I915_READ(DP_TP_CTL(PORT_E));
1192                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1193                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1194                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1195                 POSTING_READ(DP_TP_CTL(PORT_E));
1196
1197                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1198
1199                 /* Reset FDI_RX_MISC pwrdn lanes */
1200                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1201                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1202                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1203                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1204                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1205         }
1206
1207         /* Enable normal pixel sending for FDI */
1208         I915_WRITE(DP_TP_CTL(PORT_E),
1209                    DP_TP_CTL_FDI_AUTOTRAIN |
1210                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1211                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1212                    DP_TP_CTL_ENABLE);
1213 }
1214
1215 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1216 {
1217         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1218         struct intel_digital_port *intel_dig_port =
1219                 enc_to_dig_port(&encoder->base);
1220
1221         intel_dp->DP = intel_dig_port->saved_port_bits |
1222                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1223         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1224 }
1225
1226 static struct intel_encoder *
1227 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1228 {
1229         struct drm_device *dev = crtc->base.dev;
1230         struct intel_encoder *encoder, *ret = NULL;
1231         int num_encoders = 0;
1232
1233         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1234                 ret = encoder;
1235                 num_encoders++;
1236         }
1237
1238         if (num_encoders != 1)
1239                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1240                      pipe_name(crtc->pipe));
1241
1242         BUG_ON(ret == NULL);
1243         return ret;
1244 }
1245
1246 /* Finds the only possible encoder associated with the given CRTC. */
1247 struct intel_encoder *
1248 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
1249 {
1250         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1251         struct intel_encoder *ret = NULL;
1252         struct drm_atomic_state *state;
1253         struct drm_connector *connector;
1254         struct drm_connector_state *connector_state;
1255         int num_encoders = 0;
1256         int i;
1257
1258         state = crtc_state->base.state;
1259
1260         for_each_new_connector_in_state(state, connector, connector_state, i) {
1261                 if (connector_state->crtc != crtc_state->base.crtc)
1262                         continue;
1263
1264                 ret = to_intel_encoder(connector_state->best_encoder);
1265                 num_encoders++;
1266         }
1267
1268         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1269              pipe_name(crtc->pipe));
1270
1271         BUG_ON(ret == NULL);
1272         return ret;
1273 }
1274
1275 #define LC_FREQ 2700
1276
1277 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1278                                    i915_reg_t reg)
1279 {
1280         int refclk = LC_FREQ;
1281         int n, p, r;
1282         u32 wrpll;
1283
1284         wrpll = I915_READ(reg);
1285         switch (wrpll & WRPLL_PLL_REF_MASK) {
1286         case WRPLL_PLL_SSC:
1287         case WRPLL_PLL_NON_SSC:
1288                 /*
1289                  * We could calculate spread here, but our checking
1290                  * code only cares about 5% accuracy, and spread is a max of
1291                  * 0.5% downspread.
1292                  */
1293                 refclk = 135;
1294                 break;
1295         case WRPLL_PLL_LCPLL:
1296                 refclk = LC_FREQ;
1297                 break;
1298         default:
1299                 WARN(1, "bad wrpll refclk\n");
1300                 return 0;
1301         }
1302
1303         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1304         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1305         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1306
1307         /* Convert to KHz, p & r have a fixed point portion */
1308         return (refclk * n * 100) / (p * r);
1309 }
1310
1311 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1312                                enum intel_dpll_id pll_id)
1313 {
1314         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1315         uint32_t cfgcr1_val, cfgcr2_val;
1316         uint32_t p0, p1, p2, dco_freq;
1317
1318         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1319         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1320
1321         cfgcr1_val = I915_READ(cfgcr1_reg);
1322         cfgcr2_val = I915_READ(cfgcr2_reg);
1323
1324         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1325         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1326
1327         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1328                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1329         else
1330                 p1 = 1;
1331
1332
1333         switch (p0) {
1334         case DPLL_CFGCR2_PDIV_1:
1335                 p0 = 1;
1336                 break;
1337         case DPLL_CFGCR2_PDIV_2:
1338                 p0 = 2;
1339                 break;
1340         case DPLL_CFGCR2_PDIV_3:
1341                 p0 = 3;
1342                 break;
1343         case DPLL_CFGCR2_PDIV_7:
1344                 p0 = 7;
1345                 break;
1346         }
1347
1348         switch (p2) {
1349         case DPLL_CFGCR2_KDIV_5:
1350                 p2 = 5;
1351                 break;
1352         case DPLL_CFGCR2_KDIV_2:
1353                 p2 = 2;
1354                 break;
1355         case DPLL_CFGCR2_KDIV_3:
1356                 p2 = 3;
1357                 break;
1358         case DPLL_CFGCR2_KDIV_1:
1359                 p2 = 1;
1360                 break;
1361         }
1362
1363         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1364
1365         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1366                 1000) / 0x8000;
1367
1368         return dco_freq / (p0 * p1 * p2 * 5);
1369 }
1370
1371 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1372                                enum intel_dpll_id pll_id)
1373 {
1374         uint32_t cfgcr0, cfgcr1;
1375         uint32_t p0, p1, p2, dco_freq, ref_clock;
1376
1377         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1378         cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1379
1380         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386         else
1387                 p1 = 1;
1388
1389
1390         switch (p0) {
1391         case DPLL_CFGCR1_PDIV_2:
1392                 p0 = 2;
1393                 break;
1394         case DPLL_CFGCR1_PDIV_3:
1395                 p0 = 3;
1396                 break;
1397         case DPLL_CFGCR1_PDIV_5:
1398                 p0 = 5;
1399                 break;
1400         case DPLL_CFGCR1_PDIV_7:
1401                 p0 = 7;
1402                 break;
1403         }
1404
1405         switch (p2) {
1406         case DPLL_CFGCR1_KDIV_1:
1407                 p2 = 1;
1408                 break;
1409         case DPLL_CFGCR1_KDIV_2:
1410                 p2 = 2;
1411                 break;
1412         case DPLL_CFGCR1_KDIV_4:
1413                 p2 = 4;
1414                 break;
1415         }
1416
1417         ref_clock = dev_priv->cdclk.hw.ref;
1418
1419         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1423
1424         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425                 return 0;
1426
1427         return dco_freq / (p0 * p1 * p2 * 5);
1428 }
1429
1430 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1431 {
1432         int dotclock;
1433
1434         if (pipe_config->has_pch_encoder)
1435                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1436                                                     &pipe_config->fdi_m_n);
1437         else if (intel_crtc_has_dp_encoder(pipe_config))
1438                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1439                                                     &pipe_config->dp_m_n);
1440         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1441                 dotclock = pipe_config->port_clock * 2 / 3;
1442         else
1443                 dotclock = pipe_config->port_clock;
1444
1445         if (pipe_config->ycbcr420)
1446                 dotclock *= 2;
1447
1448         if (pipe_config->pixel_multiplier)
1449                 dotclock /= pipe_config->pixel_multiplier;
1450
1451         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1452 }
1453
1454 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1455                               struct intel_crtc_state *pipe_config)
1456 {
1457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1458         int link_clock = 0;
1459         uint32_t cfgcr0;
1460         enum intel_dpll_id pll_id;
1461
1462         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1463
1464         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1465
1466         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1467                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1468         } else {
1469                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1470
1471                 switch (link_clock) {
1472                 case DPLL_CFGCR0_LINK_RATE_810:
1473                         link_clock = 81000;
1474                         break;
1475                 case DPLL_CFGCR0_LINK_RATE_1080:
1476                         link_clock = 108000;
1477                         break;
1478                 case DPLL_CFGCR0_LINK_RATE_1350:
1479                         link_clock = 135000;
1480                         break;
1481                 case DPLL_CFGCR0_LINK_RATE_1620:
1482                         link_clock = 162000;
1483                         break;
1484                 case DPLL_CFGCR0_LINK_RATE_2160:
1485                         link_clock = 216000;
1486                         break;
1487                 case DPLL_CFGCR0_LINK_RATE_2700:
1488                         link_clock = 270000;
1489                         break;
1490                 case DPLL_CFGCR0_LINK_RATE_3240:
1491                         link_clock = 324000;
1492                         break;
1493                 case DPLL_CFGCR0_LINK_RATE_4050:
1494                         link_clock = 405000;
1495                         break;
1496                 default:
1497                         WARN(1, "Unsupported link rate\n");
1498                         break;
1499                 }
1500                 link_clock *= 2;
1501         }
1502
1503         pipe_config->port_clock = link_clock;
1504
1505         ddi_dotclock_get(pipe_config);
1506 }
1507
1508 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1509                                 struct intel_crtc_state *pipe_config)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1512         int link_clock = 0;
1513         uint32_t dpll_ctl1;
1514         enum intel_dpll_id pll_id;
1515
1516         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1517
1518         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1519
1520         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1521                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1522         } else {
1523                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1524                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1525
1526                 switch (link_clock) {
1527                 case DPLL_CTRL1_LINK_RATE_810:
1528                         link_clock = 81000;
1529                         break;
1530                 case DPLL_CTRL1_LINK_RATE_1080:
1531                         link_clock = 108000;
1532                         break;
1533                 case DPLL_CTRL1_LINK_RATE_1350:
1534                         link_clock = 135000;
1535                         break;
1536                 case DPLL_CTRL1_LINK_RATE_1620:
1537                         link_clock = 162000;
1538                         break;
1539                 case DPLL_CTRL1_LINK_RATE_2160:
1540                         link_clock = 216000;
1541                         break;
1542                 case DPLL_CTRL1_LINK_RATE_2700:
1543                         link_clock = 270000;
1544                         break;
1545                 default:
1546                         WARN(1, "Unsupported link rate\n");
1547                         break;
1548                 }
1549                 link_clock *= 2;
1550         }
1551
1552         pipe_config->port_clock = link_clock;
1553
1554         ddi_dotclock_get(pipe_config);
1555 }
1556
1557 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1558                               struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1561         int link_clock = 0;
1562         u32 val, pll;
1563
1564         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1565         switch (val & PORT_CLK_SEL_MASK) {
1566         case PORT_CLK_SEL_LCPLL_810:
1567                 link_clock = 81000;
1568                 break;
1569         case PORT_CLK_SEL_LCPLL_1350:
1570                 link_clock = 135000;
1571                 break;
1572         case PORT_CLK_SEL_LCPLL_2700:
1573                 link_clock = 270000;
1574                 break;
1575         case PORT_CLK_SEL_WRPLL1:
1576                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1577                 break;
1578         case PORT_CLK_SEL_WRPLL2:
1579                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1580                 break;
1581         case PORT_CLK_SEL_SPLL:
1582                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1583                 if (pll == SPLL_PLL_FREQ_810MHz)
1584                         link_clock = 81000;
1585                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1586                         link_clock = 135000;
1587                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1588                         link_clock = 270000;
1589                 else {
1590                         WARN(1, "bad spll freq\n");
1591                         return;
1592                 }
1593                 break;
1594         default:
1595                 WARN(1, "bad port clock sel\n");
1596                 return;
1597         }
1598
1599         pipe_config->port_clock = link_clock * 2;
1600
1601         ddi_dotclock_get(pipe_config);
1602 }
1603
1604 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1605 {
1606         struct intel_dpll_hw_state *state;
1607         struct dpll clock;
1608
1609         /* For DDI ports we always use a shared PLL. */
1610         if (WARN_ON(!crtc_state->shared_dpll))
1611                 return 0;
1612
1613         state = &crtc_state->dpll_hw_state;
1614
1615         clock.m1 = 2;
1616         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1617         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1618                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1619         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1620         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1621         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1622
1623         return chv_calc_dpll_params(100000, &clock);
1624 }
1625
1626 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1627                               struct intel_crtc_state *pipe_config)
1628 {
1629         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1630
1631         ddi_dotclock_get(pipe_config);
1632 }
1633
1634 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1635                                 struct intel_crtc_state *pipe_config)
1636 {
1637         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1638
1639         if (INTEL_GEN(dev_priv) <= 8)
1640                 hsw_ddi_clock_get(encoder, pipe_config);
1641         else if (IS_GEN9_BC(dev_priv))
1642                 skl_ddi_clock_get(encoder, pipe_config);
1643         else if (IS_GEN9_LP(dev_priv))
1644                 bxt_ddi_clock_get(encoder, pipe_config);
1645         else if (IS_CANNONLAKE(dev_priv))
1646                 cnl_ddi_clock_get(encoder, pipe_config);
1647 }
1648
1649 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1650 {
1651         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1652         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1653         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1654         u32 temp;
1655
1656         if (!intel_crtc_has_dp_encoder(crtc_state))
1657                 return;
1658
1659         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1660
1661         temp = TRANS_MSA_SYNC_CLK;
1662         switch (crtc_state->pipe_bpp) {
1663         case 18:
1664                 temp |= TRANS_MSA_6_BPC;
1665                 break;
1666         case 24:
1667                 temp |= TRANS_MSA_8_BPC;
1668                 break;
1669         case 30:
1670                 temp |= TRANS_MSA_10_BPC;
1671                 break;
1672         case 36:
1673                 temp |= TRANS_MSA_12_BPC;
1674                 break;
1675         default:
1676                 MISSING_CASE(crtc_state->pipe_bpp);
1677                 break;
1678         }
1679
1680         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1681 }
1682
1683 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1684                                     bool state)
1685 {
1686         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1687         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1688         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1689         uint32_t temp;
1690
1691         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1692         if (state == true)
1693                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1694         else
1695                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1696         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1697 }
1698
1699 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1700 {
1701         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1702         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1704         enum pipe pipe = crtc->pipe;
1705         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1706         enum port port = encoder->port;
1707         uint32_t temp;
1708
1709         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1710         temp = TRANS_DDI_FUNC_ENABLE;
1711         temp |= TRANS_DDI_SELECT_PORT(port);
1712
1713         switch (crtc_state->pipe_bpp) {
1714         case 18:
1715                 temp |= TRANS_DDI_BPC_6;
1716                 break;
1717         case 24:
1718                 temp |= TRANS_DDI_BPC_8;
1719                 break;
1720         case 30:
1721                 temp |= TRANS_DDI_BPC_10;
1722                 break;
1723         case 36:
1724                 temp |= TRANS_DDI_BPC_12;
1725                 break;
1726         default:
1727                 BUG();
1728         }
1729
1730         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1731                 temp |= TRANS_DDI_PVSYNC;
1732         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1733                 temp |= TRANS_DDI_PHSYNC;
1734
1735         if (cpu_transcoder == TRANSCODER_EDP) {
1736                 switch (pipe) {
1737                 case PIPE_A:
1738                         /* On Haswell, can only use the always-on power well for
1739                          * eDP when not using the panel fitter, and when not
1740                          * using motion blur mitigation (which we don't
1741                          * support). */
1742                         if (IS_HASWELL(dev_priv) &&
1743                             (crtc_state->pch_pfit.enabled ||
1744                              crtc_state->pch_pfit.force_thru))
1745                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1746                         else
1747                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1748                         break;
1749                 case PIPE_B:
1750                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1751                         break;
1752                 case PIPE_C:
1753                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1754                         break;
1755                 default:
1756                         BUG();
1757                         break;
1758                 }
1759         }
1760
1761         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1762                 if (crtc_state->has_hdmi_sink)
1763                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1764                 else
1765                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1766
1767                 if (crtc_state->hdmi_scrambling)
1768                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1769                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1770                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1771         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1772                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1773                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1774         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1775                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1776                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1777         } else {
1778                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1779                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1780         }
1781
1782         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1783 }
1784
1785 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1786 {
1787         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1788         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1789         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1790         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1791         uint32_t val = I915_READ(reg);
1792
1793         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1794         val |= TRANS_DDI_PORT_NONE;
1795         I915_WRITE(reg, val);
1796
1797         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1798             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1799                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1800                 /* Quirk time at 100ms for reliable operation */
1801                 msleep(100);
1802         }
1803 }
1804
1805 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1806                                      bool enable)
1807 {
1808         struct drm_device *dev = intel_encoder->base.dev;
1809         struct drm_i915_private *dev_priv = to_i915(dev);
1810         enum pipe pipe = 0;
1811         int ret = 0;
1812         uint32_t tmp;
1813
1814         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1815                                                 intel_encoder->power_domain)))
1816                 return -ENXIO;
1817
1818         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1819                 ret = -EIO;
1820                 goto out;
1821         }
1822
1823         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1824         if (enable)
1825                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1826         else
1827                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1828         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1829 out:
1830         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1831         return ret;
1832 }
1833
1834 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1835 {
1836         struct drm_device *dev = intel_connector->base.dev;
1837         struct drm_i915_private *dev_priv = to_i915(dev);
1838         struct intel_encoder *encoder = intel_connector->encoder;
1839         int type = intel_connector->base.connector_type;
1840         enum port port = encoder->port;
1841         enum pipe pipe = 0;
1842         enum transcoder cpu_transcoder;
1843         uint32_t tmp;
1844         bool ret;
1845
1846         if (!intel_display_power_get_if_enabled(dev_priv,
1847                                                 encoder->power_domain))
1848                 return false;
1849
1850         if (!encoder->get_hw_state(encoder, &pipe)) {
1851                 ret = false;
1852                 goto out;
1853         }
1854
1855         if (port == PORT_A)
1856                 cpu_transcoder = TRANSCODER_EDP;
1857         else
1858                 cpu_transcoder = (enum transcoder) pipe;
1859
1860         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1861
1862         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1863         case TRANS_DDI_MODE_SELECT_HDMI:
1864         case TRANS_DDI_MODE_SELECT_DVI:
1865                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1866                 break;
1867
1868         case TRANS_DDI_MODE_SELECT_DP_SST:
1869                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1870                       type == DRM_MODE_CONNECTOR_DisplayPort;
1871                 break;
1872
1873         case TRANS_DDI_MODE_SELECT_DP_MST:
1874                 /* if the transcoder is in MST state then
1875                  * connector isn't connected */
1876                 ret = false;
1877                 break;
1878
1879         case TRANS_DDI_MODE_SELECT_FDI:
1880                 ret = type == DRM_MODE_CONNECTOR_VGA;
1881                 break;
1882
1883         default:
1884                 ret = false;
1885                 break;
1886         }
1887
1888 out:
1889         intel_display_power_put(dev_priv, encoder->power_domain);
1890
1891         return ret;
1892 }
1893
1894 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1895                             enum pipe *pipe)
1896 {
1897         struct drm_device *dev = encoder->base.dev;
1898         struct drm_i915_private *dev_priv = to_i915(dev);
1899         enum port port = encoder->port;
1900         enum pipe p;
1901         u32 tmp;
1902         bool ret;
1903
1904         if (!intel_display_power_get_if_enabled(dev_priv,
1905                                                 encoder->power_domain))
1906                 return false;
1907
1908         ret = false;
1909
1910         tmp = I915_READ(DDI_BUF_CTL(port));
1911
1912         if (!(tmp & DDI_BUF_CTL_ENABLE))
1913                 goto out;
1914
1915         if (port == PORT_A) {
1916                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1917
1918                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1919                 case TRANS_DDI_EDP_INPUT_A_ON:
1920                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1921                         *pipe = PIPE_A;
1922                         break;
1923                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1924                         *pipe = PIPE_B;
1925                         break;
1926                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1927                         *pipe = PIPE_C;
1928                         break;
1929                 }
1930
1931                 ret = true;
1932
1933                 goto out;
1934         }
1935
1936         for_each_pipe(dev_priv, p) {
1937                 enum transcoder cpu_transcoder = (enum transcoder) p;
1938
1939                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1940
1941                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1942                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1943                             TRANS_DDI_MODE_SELECT_DP_MST)
1944                                 goto out;
1945
1946                         *pipe = p;
1947                         ret = true;
1948
1949                         goto out;
1950                 }
1951         }
1952
1953         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1954
1955 out:
1956         if (ret && IS_GEN9_LP(dev_priv)) {
1957                 tmp = I915_READ(BXT_PHY_CTL(port));
1958                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1959                             BXT_PHY_LANE_POWERDOWN_ACK |
1960                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1961                         DRM_ERROR("Port %c enabled but PHY powered down? "
1962                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1963         }
1964
1965         intel_display_power_put(dev_priv, encoder->power_domain);
1966
1967         return ret;
1968 }
1969
1970 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1971 {
1972         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1973         enum pipe pipe;
1974
1975         if (intel_ddi_get_hw_state(encoder, &pipe))
1976                 return BIT_ULL(dig_port->ddi_io_power_domain);
1977
1978         return 0;
1979 }
1980
1981 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1982 {
1983         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1984         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1985         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1986         enum port port = encoder->port;
1987         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1988
1989         if (cpu_transcoder != TRANSCODER_EDP)
1990                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1991                            TRANS_CLK_SEL_PORT(port));
1992 }
1993
1994 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1997         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1998
1999         if (cpu_transcoder != TRANSCODER_EDP)
2000                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2001                            TRANS_CLK_SEL_DISABLED);
2002 }
2003
2004 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2005                                 enum port port, uint8_t iboost)
2006 {
2007         u32 tmp;
2008
2009         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2010         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2011         if (iboost)
2012                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2013         else
2014                 tmp |= BALANCE_LEG_DISABLE(port);
2015         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2016 }
2017
2018 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2019                                int level, enum intel_output_type type)
2020 {
2021         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2022         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2023         enum port port = encoder->port;
2024         uint8_t iboost;
2025
2026         if (type == INTEL_OUTPUT_HDMI)
2027                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2028         else
2029                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2030
2031         if (iboost == 0) {
2032                 const struct ddi_buf_trans *ddi_translations;
2033                 int n_entries;
2034
2035                 if (type == INTEL_OUTPUT_HDMI)
2036                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2037                 else if (type == INTEL_OUTPUT_EDP)
2038                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2039                 else
2040                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2041
2042                 if (WARN_ON_ONCE(!ddi_translations))
2043                         return;
2044                 if (WARN_ON_ONCE(level >= n_entries))
2045                         level = n_entries - 1;
2046
2047                 iboost = ddi_translations[level].i_boost;
2048         }
2049
2050         /* Make sure that the requested I_boost is valid */
2051         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2052                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2053                 return;
2054         }
2055
2056         _skl_ddi_set_iboost(dev_priv, port, iboost);
2057
2058         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2059                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2060 }
2061
2062 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2063                                     int level, enum intel_output_type type)
2064 {
2065         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2066         const struct bxt_ddi_buf_trans *ddi_translations;
2067         enum port port = encoder->port;
2068         int n_entries;
2069
2070         if (type == INTEL_OUTPUT_HDMI)
2071                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2072         else if (type == INTEL_OUTPUT_EDP)
2073                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2074         else
2075                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2076
2077         if (WARN_ON_ONCE(!ddi_translations))
2078                 return;
2079         if (WARN_ON_ONCE(level >= n_entries))
2080                 level = n_entries - 1;
2081
2082         bxt_ddi_phy_set_signal_level(dev_priv, port,
2083                                      ddi_translations[level].margin,
2084                                      ddi_translations[level].scale,
2085                                      ddi_translations[level].enable,
2086                                      ddi_translations[level].deemphasis);
2087 }
2088
2089 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2090 {
2091         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2092         enum port port = encoder->port;
2093         int n_entries;
2094
2095         if (IS_ICELAKE(dev_priv)) {
2096                 if (port == PORT_A || port == PORT_B)
2097                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2098                                                 &n_entries);
2099                 else
2100                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2101         } else if (IS_CANNONLAKE(dev_priv)) {
2102                 if (encoder->type == INTEL_OUTPUT_EDP)
2103                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2104                 else
2105                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2106         } else if (IS_GEN9_LP(dev_priv)) {
2107                 if (encoder->type == INTEL_OUTPUT_EDP)
2108                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2109                 else
2110                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2111         } else {
2112                 if (encoder->type == INTEL_OUTPUT_EDP)
2113                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2114                 else
2115                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2116         }
2117
2118         if (WARN_ON(n_entries < 1))
2119                 n_entries = 1;
2120         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2121                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2122
2123         return index_to_dp_signal_levels[n_entries - 1] &
2124                 DP_TRAIN_VOLTAGE_SWING_MASK;
2125 }
2126
2127 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2128                                    int level, enum intel_output_type type)
2129 {
2130         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2131         const struct cnl_ddi_buf_trans *ddi_translations;
2132         enum port port = encoder->port;
2133         int n_entries, ln;
2134         u32 val;
2135
2136         if (type == INTEL_OUTPUT_HDMI)
2137                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2138         else if (type == INTEL_OUTPUT_EDP)
2139                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2140         else
2141                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2142
2143         if (WARN_ON_ONCE(!ddi_translations))
2144                 return;
2145         if (WARN_ON_ONCE(level >= n_entries))
2146                 level = n_entries - 1;
2147
2148         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2149         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2150         val &= ~SCALING_MODE_SEL_MASK;
2151         val |= SCALING_MODE_SEL(2);
2152         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2153
2154         /* Program PORT_TX_DW2 */
2155         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2156         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2157                  RCOMP_SCALAR_MASK);
2158         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2159         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2160         /* Rcomp scalar is fixed as 0x98 for every table entry */
2161         val |= RCOMP_SCALAR(0x98);
2162         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2163
2164         /* Program PORT_TX_DW4 */
2165         /* We cannot write to GRP. It would overrite individual loadgen */
2166         for (ln = 0; ln < 4; ln++) {
2167                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2168                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2169                          CURSOR_COEFF_MASK);
2170                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2171                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2172                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2173                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2174         }
2175
2176         /* Program PORT_TX_DW5 */
2177         /* All DW5 values are fixed for every table entry */
2178         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2179         val &= ~RTERM_SELECT_MASK;
2180         val |= RTERM_SELECT(6);
2181         val |= TAP3_DISABLE;
2182         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2183
2184         /* Program PORT_TX_DW7 */
2185         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2186         val &= ~N_SCALAR_MASK;
2187         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2188         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2189 }
2190
2191 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2192                                     int level, enum intel_output_type type)
2193 {
2194         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2195         enum port port = encoder->port;
2196         int width, rate, ln;
2197         u32 val;
2198
2199         if (type == INTEL_OUTPUT_HDMI) {
2200                 width = 4;
2201                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2202         } else {
2203                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2204
2205                 width = intel_dp->lane_count;
2206                 rate = intel_dp->link_rate;
2207         }
2208
2209         /*
2210          * 1. If port type is eDP or DP,
2211          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2212          * else clear to 0b.
2213          */
2214         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2215         if (type != INTEL_OUTPUT_HDMI)
2216                 val |= COMMON_KEEPER_EN;
2217         else
2218                 val &= ~COMMON_KEEPER_EN;
2219         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2220
2221         /* 2. Program loadgen select */
2222         /*
2223          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2224          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2225          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2226          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2227          */
2228         for (ln = 0; ln <= 3; ln++) {
2229                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2230                 val &= ~LOADGEN_SELECT;
2231
2232                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2233                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2234                         val |= LOADGEN_SELECT;
2235                 }
2236                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2237         }
2238
2239         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2240         val = I915_READ(CNL_PORT_CL1CM_DW5);
2241         val |= SUS_CLOCK_CONFIG;
2242         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2243
2244         /* 4. Clear training enable to change swing values */
2245         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2246         val &= ~TX_TRAINING_EN;
2247         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2248
2249         /* 5. Program swing and de-emphasis */
2250         cnl_ddi_vswing_program(encoder, level, type);
2251
2252         /* 6. Set training enable to trigger update */
2253         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2254         val |= TX_TRAINING_EN;
2255         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2256 }
2257
2258 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2259                                          u32 level, enum port port, int type)
2260 {
2261         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2262         u32 n_entries, val;
2263         int ln;
2264
2265         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2266                                                    &n_entries);
2267         if (!ddi_translations)
2268                 return;
2269
2270         if (level >= n_entries) {
2271                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2272                 level = n_entries - 1;
2273         }
2274
2275         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2276         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2277         val &= ~RTERM_SELECT_MASK;
2278         val |= RTERM_SELECT(0x6);
2279         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2280
2281         /* Program PORT_TX_DW5 */
2282         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2283         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2284          * Clear DisableTap2 and DisableTap3 for all other Ports
2285          */
2286         if (type == INTEL_OUTPUT_DSI) {
2287                 val |= TAP2_DISABLE;
2288                 val |= TAP3_DISABLE;
2289         } else {
2290                 val &= ~TAP2_DISABLE;
2291                 val &= ~TAP3_DISABLE;
2292         }
2293         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2294
2295         /* Program PORT_TX_DW2 */
2296         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2297         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2298                  RCOMP_SCALAR_MASK);
2299         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2300         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2301         /* Program Rcomp scalar for every table entry */
2302         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2303         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2304
2305         /* Program PORT_TX_DW4 */
2306         /* We cannot write to GRP. It would overwrite individual loadgen. */
2307         for (ln = 0; ln <= 3; ln++) {
2308                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2309                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2310                          CURSOR_COEFF_MASK);
2311                 val |= ddi_translations[level].dw4_scaling;
2312                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2313         }
2314 }
2315
2316 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2317                                               u32 level,
2318                                               enum intel_output_type type)
2319 {
2320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2321         enum port port = encoder->port;
2322         int width = 0;
2323         int rate = 0;
2324         u32 val;
2325         int ln = 0;
2326
2327         if (type == INTEL_OUTPUT_HDMI) {
2328                 width = 4;
2329                 /* Rate is always < than 6GHz for HDMI */
2330         } else {
2331                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332
2333                 width = intel_dp->lane_count;
2334                 rate = intel_dp->link_rate;
2335         }
2336
2337         /*
2338          * 1. If port type is eDP or DP,
2339          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2340          * else clear to 0b.
2341          */
2342         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2343         if (type == INTEL_OUTPUT_HDMI)
2344                 val &= ~COMMON_KEEPER_EN;
2345         else
2346                 val |= COMMON_KEEPER_EN;
2347         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2348
2349         /* 2. Program loadgen select */
2350         /*
2351          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2352          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2353          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2354          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2355          */
2356         for (ln = 0; ln <= 3; ln++) {
2357                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2358                 val &= ~LOADGEN_SELECT;
2359
2360                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2361                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2362                         val |= LOADGEN_SELECT;
2363                 }
2364                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2365         }
2366
2367         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2368         val = I915_READ(ICL_PORT_CL_DW5(port));
2369         val |= SUS_CLOCK_CONFIG;
2370         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2371
2372         /* 4. Clear training enable to change swing values */
2373         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2374         val &= ~TX_TRAINING_EN;
2375         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2376
2377         /* 5. Program swing and de-emphasis */
2378         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2379
2380         /* 6. Set training enable to trigger update */
2381         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2382         val |= TX_TRAINING_EN;
2383         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2384 }
2385
2386 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
2387                                     enum intel_output_type type)
2388 {
2389         enum port port = encoder->port;
2390
2391         if (port == PORT_A || port == PORT_B)
2392                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2393         else
2394                 /* Not Implemented Yet */
2395                 WARN_ON(1);
2396 }
2397
2398 static uint32_t translate_signal_level(int signal_levels)
2399 {
2400         int i;
2401
2402         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2403                 if (index_to_dp_signal_levels[i] == signal_levels)
2404                         return i;
2405         }
2406
2407         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2408              signal_levels);
2409
2410         return 0;
2411 }
2412
2413 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2414 {
2415         uint8_t train_set = intel_dp->train_set[0];
2416         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2417                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2418
2419         return translate_signal_level(signal_levels);
2420 }
2421
2422 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2423 {
2424         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2425         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2426         struct intel_encoder *encoder = &dport->base;
2427         int level = intel_ddi_dp_level(intel_dp);
2428
2429         if (IS_ICELAKE(dev_priv))
2430                 icl_ddi_vswing_sequence(encoder, level, encoder->type);
2431         else if (IS_CANNONLAKE(dev_priv))
2432                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2433         else
2434                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2435
2436         return 0;
2437 }
2438
2439 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2440 {
2441         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2442         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2443         struct intel_encoder *encoder = &dport->base;
2444         int level = intel_ddi_dp_level(intel_dp);
2445
2446         if (IS_GEN9_BC(dev_priv))
2447                 skl_ddi_set_iboost(encoder, level, encoder->type);
2448
2449         return DDI_BUF_TRANS_SELECT(level);
2450 }
2451
2452 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2453                            struct intel_crtc_state *crtc_state,
2454                            struct drm_atomic_state *old_state)
2455 {
2456         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2457         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2458         struct drm_connector_state *conn_state;
2459         struct drm_connector *conn;
2460         int i;
2461
2462         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2463                 struct intel_encoder *encoder =
2464                         to_intel_encoder(conn_state->best_encoder);
2465                 enum port port;
2466                 uint32_t val;
2467
2468                 if (conn_state->crtc != crtc)
2469                         continue;
2470
2471                 port = encoder->port;
2472                 mutex_lock(&dev_priv->dpll_lock);
2473
2474                 val = I915_READ(DPCLKA_CFGCR0_ICL);
2475                 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2476
2477                 if (port == PORT_A || port == PORT_B) {
2478                         val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2479                         val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2480                         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2481                         POSTING_READ(DPCLKA_CFGCR0_ICL);
2482                 }
2483
2484                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2485                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2486
2487                 mutex_unlock(&dev_priv->dpll_lock);
2488         }
2489 }
2490
2491 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2492                              struct intel_crtc_state *crtc_state,
2493                              struct drm_atomic_state *old_state)
2494 {
2495         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2496         struct drm_connector_state *old_conn_state;
2497         struct drm_connector *conn;
2498         int i;
2499
2500         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2501                 struct intel_encoder *encoder =
2502                         to_intel_encoder(old_conn_state->best_encoder);
2503                 enum port port;
2504
2505                 if (old_conn_state->crtc != crtc)
2506                         continue;
2507
2508                 port = encoder->port;
2509                 mutex_lock(&dev_priv->dpll_lock);
2510                 I915_WRITE(DPCLKA_CFGCR0_ICL,
2511                            I915_READ(DPCLKA_CFGCR0_ICL) |
2512                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2513                 mutex_unlock(&dev_priv->dpll_lock);
2514         }
2515 }
2516
2517 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2518                                  const struct intel_shared_dpll *pll)
2519 {
2520         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2521         enum port port = encoder->port;
2522         uint32_t val;
2523
2524         if (WARN_ON(!pll))
2525                 return;
2526
2527         mutex_lock(&dev_priv->dpll_lock);
2528
2529         if (IS_ICELAKE(dev_priv)) {
2530                 if (port >= PORT_C)
2531                         I915_WRITE(DDI_CLK_SEL(port),
2532                                    icl_pll_to_ddi_pll_sel(encoder, pll));
2533         } else if (IS_CANNONLAKE(dev_priv)) {
2534                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2535                 val = I915_READ(DPCLKA_CFGCR0);
2536                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2537                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2538                 I915_WRITE(DPCLKA_CFGCR0, val);
2539
2540                 /*
2541                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2542                  * This step and the step before must be done with separate
2543                  * register writes.
2544                  */
2545                 val = I915_READ(DPCLKA_CFGCR0);
2546                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2547                 I915_WRITE(DPCLKA_CFGCR0, val);
2548         } else if (IS_GEN9_BC(dev_priv)) {
2549                 /* DDI -> PLL mapping  */
2550                 val = I915_READ(DPLL_CTRL2);
2551
2552                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2553                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2554                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2555                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2556
2557                 I915_WRITE(DPLL_CTRL2, val);
2558
2559         } else if (INTEL_GEN(dev_priv) < 9) {
2560                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2561         }
2562
2563         mutex_unlock(&dev_priv->dpll_lock);
2564 }
2565
2566 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2567 {
2568         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2569         enum port port = encoder->port;
2570
2571         if (IS_ICELAKE(dev_priv)) {
2572                 if (port >= PORT_C)
2573                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2574         } else if (IS_CANNONLAKE(dev_priv)) {
2575                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2576                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2577         } else if (IS_GEN9_BC(dev_priv)) {
2578                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2579                            DPLL_CTRL2_DDI_CLK_OFF(port));
2580         } else if (INTEL_GEN(dev_priv) < 9) {
2581                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2582         }
2583 }
2584
2585 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2586                                     const struct intel_crtc_state *crtc_state,
2587                                     const struct drm_connector_state *conn_state)
2588 {
2589         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2590         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2591         enum port port = encoder->port;
2592         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2593         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2594         int level = intel_ddi_dp_level(intel_dp);
2595
2596         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2597
2598         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2599                                  crtc_state->lane_count, is_mst);
2600
2601         intel_edp_panel_on(intel_dp);
2602
2603         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2604
2605         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2606
2607         if (IS_ICELAKE(dev_priv))
2608                 icl_ddi_vswing_sequence(encoder, level, encoder->type);
2609         else if (IS_CANNONLAKE(dev_priv))
2610                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2611         else if (IS_GEN9_LP(dev_priv))
2612                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2613         else
2614                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2615
2616         intel_ddi_init_dp_buf_reg(encoder);
2617         if (!is_mst)
2618                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2619         intel_dp_start_link_train(intel_dp);
2620         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2621                 intel_dp_stop_link_train(intel_dp);
2622 }
2623
2624 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2625                                       const struct intel_crtc_state *crtc_state,
2626                                       const struct drm_connector_state *conn_state)
2627 {
2628         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2629         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2630         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2631         enum port port = encoder->port;
2632         int level = intel_ddi_hdmi_level(dev_priv, port);
2633         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2634
2635         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2636         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2637
2638         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2639
2640         if (IS_ICELAKE(dev_priv))
2641                 icl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2642         else if (IS_CANNONLAKE(dev_priv))
2643                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2644         else if (IS_GEN9_LP(dev_priv))
2645                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2646         else
2647                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2648
2649         if (IS_GEN9_BC(dev_priv))
2650                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2651
2652         intel_dig_port->set_infoframes(&encoder->base,
2653                                        crtc_state->has_infoframe,
2654                                        crtc_state, conn_state);
2655 }
2656
2657 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2658                                  const struct intel_crtc_state *crtc_state,
2659                                  const struct drm_connector_state *conn_state)
2660 {
2661         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2662         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2663         enum pipe pipe = crtc->pipe;
2664
2665         /*
2666          * When called from DP MST code:
2667          * - conn_state will be NULL
2668          * - encoder will be the main encoder (ie. mst->primary)
2669          * - the main connector associated with this port
2670          *   won't be active or linked to a crtc
2671          * - crtc_state will be the state of the first stream to
2672          *   be activated on this port, and it may not be the same
2673          *   stream that will be deactivated last, but each stream
2674          *   should have a state that is identical when it comes to
2675          *   the DP link parameteres
2676          */
2677
2678         WARN_ON(crtc_state->has_pch_encoder);
2679
2680         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2681
2682         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2683                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2684         else
2685                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2686 }
2687
2688 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2689 {
2690         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2691         enum port port = encoder->port;
2692         bool wait = false;
2693         u32 val;
2694
2695         val = I915_READ(DDI_BUF_CTL(port));
2696         if (val & DDI_BUF_CTL_ENABLE) {
2697                 val &= ~DDI_BUF_CTL_ENABLE;
2698                 I915_WRITE(DDI_BUF_CTL(port), val);
2699                 wait = true;
2700         }
2701
2702         val = I915_READ(DP_TP_CTL(port));
2703         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2704         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2705         I915_WRITE(DP_TP_CTL(port), val);
2706
2707         if (wait)
2708                 intel_wait_ddi_buf_idle(dev_priv, port);
2709 }
2710
2711 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2712                                       const struct intel_crtc_state *old_crtc_state,
2713                                       const struct drm_connector_state *old_conn_state)
2714 {
2715         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2716         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2717         struct intel_dp *intel_dp = &dig_port->dp;
2718         bool is_mst = intel_crtc_has_type(old_crtc_state,
2719                                           INTEL_OUTPUT_DP_MST);
2720
2721         /*
2722          * Power down sink before disabling the port, otherwise we end
2723          * up getting interrupts from the sink on detecting link loss.
2724          */
2725         if (!is_mst)
2726                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2727
2728         intel_disable_ddi_buf(encoder);
2729
2730         intel_edp_panel_vdd_on(intel_dp);
2731         intel_edp_panel_off(intel_dp);
2732
2733         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2734
2735         intel_ddi_clk_disable(encoder);
2736 }
2737
2738 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2739                                         const struct intel_crtc_state *old_crtc_state,
2740                                         const struct drm_connector_state *old_conn_state)
2741 {
2742         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2743         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2744         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2745
2746         intel_disable_ddi_buf(encoder);
2747
2748         dig_port->set_infoframes(&encoder->base, false,
2749                                  old_crtc_state, old_conn_state);
2750
2751         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2752
2753         intel_ddi_clk_disable(encoder);
2754
2755         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2756 }
2757
2758 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2759                                    const struct intel_crtc_state *old_crtc_state,
2760                                    const struct drm_connector_state *old_conn_state)
2761 {
2762         /*
2763          * When called from DP MST code:
2764          * - old_conn_state will be NULL
2765          * - encoder will be the main encoder (ie. mst->primary)
2766          * - the main connector associated with this port
2767          *   won't be active or linked to a crtc
2768          * - old_crtc_state will be the state of the last stream to
2769          *   be deactivated on this port, and it may not be the same
2770          *   stream that was activated last, but each stream
2771          *   should have a state that is identical when it comes to
2772          *   the DP link parameteres
2773          */
2774
2775         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2776                 intel_ddi_post_disable_hdmi(encoder,
2777                                             old_crtc_state, old_conn_state);
2778         else
2779                 intel_ddi_post_disable_dp(encoder,
2780                                           old_crtc_state, old_conn_state);
2781 }
2782
2783 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2784                                 const struct intel_crtc_state *old_crtc_state,
2785                                 const struct drm_connector_state *old_conn_state)
2786 {
2787         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2788         uint32_t val;
2789
2790         /*
2791          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2792          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2793          * step 13 is the correct place for it. Step 18 is where it was
2794          * originally before the BUN.
2795          */
2796         val = I915_READ(FDI_RX_CTL(PIPE_A));
2797         val &= ~FDI_RX_ENABLE;
2798         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2799
2800         intel_disable_ddi_buf(encoder);
2801         intel_ddi_clk_disable(encoder);
2802
2803         val = I915_READ(FDI_RX_MISC(PIPE_A));
2804         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2805         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2806         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2807
2808         val = I915_READ(FDI_RX_CTL(PIPE_A));
2809         val &= ~FDI_PCDCLK;
2810         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2811
2812         val = I915_READ(FDI_RX_CTL(PIPE_A));
2813         val &= ~FDI_RX_PLL_ENABLE;
2814         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2815 }
2816
2817 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2818                                 const struct intel_crtc_state *crtc_state,
2819                                 const struct drm_connector_state *conn_state)
2820 {
2821         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2822         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2823         enum port port = encoder->port;
2824
2825         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2826                 intel_dp_stop_link_train(intel_dp);
2827
2828         intel_edp_backlight_on(crtc_state, conn_state);
2829         intel_psr_enable(intel_dp, crtc_state);
2830         intel_edp_drrs_enable(intel_dp, crtc_state);
2831
2832         if (crtc_state->has_audio)
2833                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2834 }
2835
2836 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2837                                   const struct intel_crtc_state *crtc_state,
2838                                   const struct drm_connector_state *conn_state)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2841         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2842         struct drm_connector *connector = conn_state->connector;
2843         enum port port = encoder->port;
2844
2845         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2846                                                crtc_state->hdmi_high_tmds_clock_ratio,
2847                                                crtc_state->hdmi_scrambling))
2848                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2849                           connector->base.id, connector->name);
2850
2851         /* Display WA #1143: skl,kbl,cfl */
2852         if (IS_GEN9_BC(dev_priv)) {
2853                 /*
2854                  * For some reason these chicken bits have been
2855                  * stuffed into a transcoder register, event though
2856                  * the bits affect a specific DDI port rather than
2857                  * a specific transcoder.
2858                  */
2859                 static const enum transcoder port_to_transcoder[] = {
2860                         [PORT_A] = TRANSCODER_EDP,
2861                         [PORT_B] = TRANSCODER_A,
2862                         [PORT_C] = TRANSCODER_B,
2863                         [PORT_D] = TRANSCODER_C,
2864                         [PORT_E] = TRANSCODER_A,
2865                 };
2866                 enum transcoder transcoder = port_to_transcoder[port];
2867                 u32 val;
2868
2869                 val = I915_READ(CHICKEN_TRANS(transcoder));
2870
2871                 if (port == PORT_E)
2872                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2873                                 DDIE_TRAINING_OVERRIDE_VALUE;
2874                 else
2875                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
2876                                 DDI_TRAINING_OVERRIDE_VALUE;
2877
2878                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2879                 POSTING_READ(CHICKEN_TRANS(transcoder));
2880
2881                 udelay(1);
2882
2883                 if (port == PORT_E)
2884                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2885                                  DDIE_TRAINING_OVERRIDE_VALUE);
2886                 else
2887                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2888                                  DDI_TRAINING_OVERRIDE_VALUE);
2889
2890                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2891         }
2892
2893         /* In HDMI/DVI mode, the port width, and swing/emphasis values
2894          * are ignored so nothing special needs to be done besides
2895          * enabling the port.
2896          */
2897         I915_WRITE(DDI_BUF_CTL(port),
2898                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2899
2900         if (crtc_state->has_audio)
2901                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2902 }
2903
2904 static void intel_enable_ddi(struct intel_encoder *encoder,
2905                              const struct intel_crtc_state *crtc_state,
2906                              const struct drm_connector_state *conn_state)
2907 {
2908         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2909                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2910         else
2911                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2912
2913         /* Enable hdcp if it's desired */
2914         if (conn_state->content_protection ==
2915             DRM_MODE_CONTENT_PROTECTION_DESIRED)
2916                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
2917 }
2918
2919 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2920                                  const struct intel_crtc_state *old_crtc_state,
2921                                  const struct drm_connector_state *old_conn_state)
2922 {
2923         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2924
2925         intel_dp->link_trained = false;
2926
2927         if (old_crtc_state->has_audio)
2928                 intel_audio_codec_disable(encoder,
2929                                           old_crtc_state, old_conn_state);
2930
2931         intel_edp_drrs_disable(intel_dp, old_crtc_state);
2932         intel_psr_disable(intel_dp, old_crtc_state);
2933         intel_edp_backlight_off(old_conn_state);
2934 }
2935
2936 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2937                                    const struct intel_crtc_state *old_crtc_state,
2938                                    const struct drm_connector_state *old_conn_state)
2939 {
2940         struct drm_connector *connector = old_conn_state->connector;
2941
2942         if (old_crtc_state->has_audio)
2943                 intel_audio_codec_disable(encoder,
2944                                           old_crtc_state, old_conn_state);
2945
2946         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2947                                                false, false))
2948                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
2949                               connector->base.id, connector->name);
2950 }
2951
2952 static void intel_disable_ddi(struct intel_encoder *encoder,
2953                               const struct intel_crtc_state *old_crtc_state,
2954                               const struct drm_connector_state *old_conn_state)
2955 {
2956         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2957
2958         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2959                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2960         else
2961                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
2962 }
2963
2964 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2965                                    const struct intel_crtc_state *pipe_config,
2966                                    const struct drm_connector_state *conn_state)
2967 {
2968         uint8_t mask = pipe_config->lane_lat_optim_mask;
2969
2970         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2971 }
2972
2973 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2974 {
2975         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2976         struct drm_i915_private *dev_priv =
2977                 to_i915(intel_dig_port->base.base.dev);
2978         enum port port = intel_dig_port->base.port;
2979         uint32_t val;
2980         bool wait = false;
2981
2982         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2983                 val = I915_READ(DDI_BUF_CTL(port));
2984                 if (val & DDI_BUF_CTL_ENABLE) {
2985                         val &= ~DDI_BUF_CTL_ENABLE;
2986                         I915_WRITE(DDI_BUF_CTL(port), val);
2987                         wait = true;
2988                 }
2989
2990                 val = I915_READ(DP_TP_CTL(port));
2991                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2992                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2993                 I915_WRITE(DP_TP_CTL(port), val);
2994                 POSTING_READ(DP_TP_CTL(port));
2995
2996                 if (wait)
2997                         intel_wait_ddi_buf_idle(dev_priv, port);
2998         }
2999
3000         val = DP_TP_CTL_ENABLE |
3001               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3002         if (intel_dp->link_mst)
3003                 val |= DP_TP_CTL_MODE_MST;
3004         else {
3005                 val |= DP_TP_CTL_MODE_SST;
3006                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3007                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3008         }
3009         I915_WRITE(DP_TP_CTL(port), val);
3010         POSTING_READ(DP_TP_CTL(port));
3011
3012         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3013         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3014         POSTING_READ(DDI_BUF_CTL(port));
3015
3016         udelay(600);
3017 }
3018
3019 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3020                                        enum transcoder cpu_transcoder)
3021 {
3022         if (cpu_transcoder == TRANSCODER_EDP)
3023                 return false;
3024
3025         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3026                 return false;
3027
3028         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3029                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3030 }
3031
3032 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3033                                          struct intel_crtc_state *crtc_state)
3034 {
3035         if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3036                 crtc_state->min_voltage_level = 2;
3037 }
3038
3039 void intel_ddi_get_config(struct intel_encoder *encoder,
3040                           struct intel_crtc_state *pipe_config)
3041 {
3042         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3043         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3044         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3045         struct intel_digital_port *intel_dig_port;
3046         u32 temp, flags = 0;
3047
3048         /* XXX: DSI transcoder paranoia */
3049         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3050                 return;
3051
3052         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3053         if (temp & TRANS_DDI_PHSYNC)
3054                 flags |= DRM_MODE_FLAG_PHSYNC;
3055         else
3056                 flags |= DRM_MODE_FLAG_NHSYNC;
3057         if (temp & TRANS_DDI_PVSYNC)
3058                 flags |= DRM_MODE_FLAG_PVSYNC;
3059         else
3060                 flags |= DRM_MODE_FLAG_NVSYNC;
3061
3062         pipe_config->base.adjusted_mode.flags |= flags;
3063
3064         switch (temp & TRANS_DDI_BPC_MASK) {
3065         case TRANS_DDI_BPC_6:
3066                 pipe_config->pipe_bpp = 18;
3067                 break;
3068         case TRANS_DDI_BPC_8:
3069                 pipe_config->pipe_bpp = 24;
3070                 break;
3071         case TRANS_DDI_BPC_10:
3072                 pipe_config->pipe_bpp = 30;
3073                 break;
3074         case TRANS_DDI_BPC_12:
3075                 pipe_config->pipe_bpp = 36;
3076                 break;
3077         default:
3078                 break;
3079         }
3080
3081         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3082         case TRANS_DDI_MODE_SELECT_HDMI:
3083                 pipe_config->has_hdmi_sink = true;
3084                 intel_dig_port = enc_to_dig_port(&encoder->base);
3085
3086                 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
3087                         pipe_config->has_infoframe = true;
3088
3089                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3090                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3091                         pipe_config->hdmi_scrambling = true;
3092                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3093                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3094                 /* fall through */
3095         case TRANS_DDI_MODE_SELECT_DVI:
3096                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3097                 pipe_config->lane_count = 4;
3098                 break;
3099         case TRANS_DDI_MODE_SELECT_FDI:
3100                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3101                 break;
3102         case TRANS_DDI_MODE_SELECT_DP_SST:
3103                 if (encoder->type == INTEL_OUTPUT_EDP)
3104                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3105                 else
3106                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3107                 pipe_config->lane_count =
3108                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3109                 intel_dp_get_m_n(intel_crtc, pipe_config);
3110                 break;
3111         case TRANS_DDI_MODE_SELECT_DP_MST:
3112                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3113                 pipe_config->lane_count =
3114                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3115                 intel_dp_get_m_n(intel_crtc, pipe_config);
3116                 break;
3117         default:
3118                 break;
3119         }
3120
3121         pipe_config->has_audio =
3122                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3123
3124         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3125             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3126                 /*
3127                  * This is a big fat ugly hack.
3128                  *
3129                  * Some machines in UEFI boot mode provide us a VBT that has 18
3130                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3131                  * unknown we fail to light up. Yet the same BIOS boots up with
3132                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3133                  * max, not what it tells us to use.
3134                  *
3135                  * Note: This will still be broken if the eDP panel is not lit
3136                  * up by the BIOS, and thus we can't get the mode at module
3137                  * load.
3138                  */
3139                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3140                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3141                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3142         }
3143
3144         intel_ddi_clock_get(encoder, pipe_config);
3145
3146         if (IS_GEN9_LP(dev_priv))
3147                 pipe_config->lane_lat_optim_mask =
3148                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3149
3150         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3151 }
3152
3153 static enum intel_output_type
3154 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3155                               struct intel_crtc_state *crtc_state,
3156                               struct drm_connector_state *conn_state)
3157 {
3158         switch (conn_state->connector->connector_type) {
3159         case DRM_MODE_CONNECTOR_HDMIA:
3160                 return INTEL_OUTPUT_HDMI;
3161         case DRM_MODE_CONNECTOR_eDP:
3162                 return INTEL_OUTPUT_EDP;
3163         case DRM_MODE_CONNECTOR_DisplayPort:
3164                 return INTEL_OUTPUT_DP;
3165         default:
3166                 MISSING_CASE(conn_state->connector->connector_type);
3167                 return INTEL_OUTPUT_UNUSED;
3168         }
3169 }
3170
3171 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3172                                      struct intel_crtc_state *pipe_config,
3173                                      struct drm_connector_state *conn_state)
3174 {
3175         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3176         enum port port = encoder->port;
3177         int ret;
3178
3179         if (port == PORT_A)
3180                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3181
3182         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3183                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3184         else
3185                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3186
3187         if (IS_GEN9_LP(dev_priv) && ret)
3188                 pipe_config->lane_lat_optim_mask =
3189                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3190
3191         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3192
3193         return ret;
3194
3195 }
3196
3197 static const struct drm_encoder_funcs intel_ddi_funcs = {
3198         .reset = intel_dp_encoder_reset,
3199         .destroy = intel_dp_encoder_destroy,
3200 };
3201
3202 static struct intel_connector *
3203 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3204 {
3205         struct intel_connector *connector;
3206         enum port port = intel_dig_port->base.port;
3207
3208         connector = intel_connector_alloc();
3209         if (!connector)
3210                 return NULL;
3211
3212         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3213         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3214                 kfree(connector);
3215                 return NULL;
3216         }
3217
3218         return connector;
3219 }
3220
3221 static int modeset_pipe(struct drm_crtc *crtc,
3222                         struct drm_modeset_acquire_ctx *ctx)
3223 {
3224         struct drm_atomic_state *state;
3225         struct drm_crtc_state *crtc_state;
3226         int ret;
3227
3228         state = drm_atomic_state_alloc(crtc->dev);
3229         if (!state)
3230                 return -ENOMEM;
3231
3232         state->acquire_ctx = ctx;
3233
3234         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3235         if (IS_ERR(crtc_state)) {
3236                 ret = PTR_ERR(crtc_state);
3237                 goto out;
3238         }
3239
3240         crtc_state->mode_changed = true;
3241
3242         ret = drm_atomic_add_affected_connectors(state, crtc);
3243         if (ret)
3244                 goto out;
3245
3246         ret = drm_atomic_add_affected_planes(state, crtc);
3247         if (ret)
3248                 goto out;
3249
3250         ret = drm_atomic_commit(state);
3251         if (ret)
3252                 goto out;
3253
3254         return 0;
3255
3256  out:
3257         drm_atomic_state_put(state);
3258
3259         return ret;
3260 }
3261
3262 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3263                                  struct drm_modeset_acquire_ctx *ctx)
3264 {
3265         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3266         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3267         struct intel_connector *connector = hdmi->attached_connector;
3268         struct i2c_adapter *adapter =
3269                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3270         struct drm_connector_state *conn_state;
3271         struct intel_crtc_state *crtc_state;
3272         struct intel_crtc *crtc;
3273         u8 config;
3274         int ret;
3275
3276         if (!connector || connector->base.status != connector_status_connected)
3277                 return 0;
3278
3279         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3280                                ctx);
3281         if (ret)
3282                 return ret;
3283
3284         conn_state = connector->base.state;
3285
3286         crtc = to_intel_crtc(conn_state->crtc);
3287         if (!crtc)
3288                 return 0;
3289
3290         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3291         if (ret)
3292                 return ret;
3293
3294         crtc_state = to_intel_crtc_state(crtc->base.state);
3295
3296         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3297
3298         if (!crtc_state->base.active)
3299                 return 0;
3300
3301         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3302             !crtc_state->hdmi_scrambling)
3303                 return 0;
3304
3305         if (conn_state->commit &&
3306             !try_wait_for_completion(&conn_state->commit->hw_done))
3307                 return 0;
3308
3309         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3310         if (ret < 0) {
3311                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3312                 return 0;
3313         }
3314
3315         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3316             crtc_state->hdmi_high_tmds_clock_ratio &&
3317             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3318             crtc_state->hdmi_scrambling)
3319                 return 0;
3320
3321         /*
3322          * HDMI 2.0 says that one should not send scrambled data
3323          * prior to configuring the sink scrambling, and that
3324          * TMDS clock/data transmission should be suspended when
3325          * changing the TMDS clock rate in the sink. So let's
3326          * just do a full modeset here, even though some sinks
3327          * would be perfectly happy if were to just reconfigure
3328          * the SCDC settings on the fly.
3329          */
3330         return modeset_pipe(&crtc->base, ctx);
3331 }
3332
3333 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3334                               struct intel_connector *connector)
3335 {
3336         struct drm_modeset_acquire_ctx ctx;
3337         bool changed;
3338         int ret;
3339
3340         changed = intel_encoder_hotplug(encoder, connector);
3341
3342         drm_modeset_acquire_init(&ctx, 0);
3343
3344         for (;;) {
3345                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3346                         ret = intel_hdmi_reset_link(encoder, &ctx);
3347                 else
3348                         ret = intel_dp_retrain_link(encoder, &ctx);
3349
3350                 if (ret == -EDEADLK) {
3351                         drm_modeset_backoff(&ctx);
3352                         continue;
3353                 }
3354
3355                 break;
3356         }
3357
3358         drm_modeset_drop_locks(&ctx);
3359         drm_modeset_acquire_fini(&ctx);
3360         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3361
3362         return changed;
3363 }
3364
3365 static struct intel_connector *
3366 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3367 {
3368         struct intel_connector *connector;
3369         enum port port = intel_dig_port->base.port;
3370
3371         connector = intel_connector_alloc();
3372         if (!connector)
3373                 return NULL;
3374
3375         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3376         intel_hdmi_init_connector(intel_dig_port, connector);
3377
3378         return connector;
3379 }
3380
3381 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3382 {
3383         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3384
3385         if (dport->base.port != PORT_A)
3386                 return false;
3387
3388         if (dport->saved_port_bits & DDI_A_4_LANES)
3389                 return false;
3390
3391         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3392          *                     supported configuration
3393          */
3394         if (IS_GEN9_LP(dev_priv))
3395                 return true;
3396
3397         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3398          *             one who does also have a full A/E split called
3399          *             DDI_F what makes DDI_E useless. However for this
3400          *             case let's trust VBT info.
3401          */
3402         if (IS_CANNONLAKE(dev_priv) &&
3403             !intel_bios_is_port_present(dev_priv, PORT_E))
3404                 return true;
3405
3406         return false;
3407 }
3408
3409 static int
3410 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3411 {
3412         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3413         enum port port = intel_dport->base.port;
3414         int max_lanes = 4;
3415
3416         if (INTEL_GEN(dev_priv) >= 11)
3417                 return max_lanes;
3418
3419         if (port == PORT_A || port == PORT_E) {
3420                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3421                         max_lanes = port == PORT_A ? 4 : 0;
3422                 else
3423                         /* Both A and E share 2 lanes */
3424                         max_lanes = 2;
3425         }
3426
3427         /*
3428          * Some BIOS might fail to set this bit on port A if eDP
3429          * wasn't lit up at boot.  Force this bit set when needed
3430          * so we use the proper lane count for our calculations.
3431          */
3432         if (intel_ddi_a_force_4_lanes(intel_dport)) {
3433                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3434                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3435                 max_lanes = 4;
3436         }
3437
3438         return max_lanes;
3439 }
3440
3441 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3442 {
3443         struct intel_digital_port *intel_dig_port;
3444         struct intel_encoder *intel_encoder;
3445         struct drm_encoder *encoder;
3446         bool init_hdmi, init_dp, init_lspcon = false;
3447
3448
3449         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3450                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3451         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3452
3453         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3454                 /*
3455                  * Lspcon device needs to be driven with DP connector
3456                  * with special detection sequence. So make sure DP
3457                  * is initialized before lspcon.
3458                  */
3459                 init_dp = true;
3460                 init_lspcon = true;
3461                 init_hdmi = false;
3462                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3463         }
3464
3465         if (!init_dp && !init_hdmi) {
3466                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3467                               port_name(port));
3468                 return;
3469         }
3470
3471         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3472         if (!intel_dig_port)
3473                 return;
3474
3475         intel_encoder = &intel_dig_port->base;
3476         encoder = &intel_encoder->base;
3477
3478         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3479                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3480
3481         intel_encoder->hotplug = intel_ddi_hotplug;
3482         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3483         intel_encoder->compute_config = intel_ddi_compute_config;
3484         intel_encoder->enable = intel_enable_ddi;
3485         if (IS_GEN9_LP(dev_priv))
3486                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3487         intel_encoder->pre_enable = intel_ddi_pre_enable;
3488         intel_encoder->disable = intel_disable_ddi;
3489         intel_encoder->post_disable = intel_ddi_post_disable;
3490         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3491         intel_encoder->get_config = intel_ddi_get_config;
3492         intel_encoder->suspend = intel_dp_encoder_suspend;
3493         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3494         intel_encoder->type = INTEL_OUTPUT_DDI;
3495         intel_encoder->power_domain = intel_port_to_power_domain(port);
3496         intel_encoder->port = port;
3497         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3498         intel_encoder->cloneable = 0;
3499
3500         if (INTEL_GEN(dev_priv) >= 11)
3501                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3502                         DDI_BUF_PORT_REVERSAL;
3503         else
3504                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3505                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3506         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3507         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3508
3509         switch (port) {
3510         case PORT_A:
3511                 intel_dig_port->ddi_io_power_domain =
3512                         POWER_DOMAIN_PORT_DDI_A_IO;
3513                 break;
3514         case PORT_B:
3515                 intel_dig_port->ddi_io_power_domain =
3516                         POWER_DOMAIN_PORT_DDI_B_IO;
3517                 break;
3518         case PORT_C:
3519                 intel_dig_port->ddi_io_power_domain =
3520                         POWER_DOMAIN_PORT_DDI_C_IO;
3521                 break;
3522         case PORT_D:
3523                 intel_dig_port->ddi_io_power_domain =
3524                         POWER_DOMAIN_PORT_DDI_D_IO;
3525                 break;
3526         case PORT_E:
3527                 intel_dig_port->ddi_io_power_domain =
3528                         POWER_DOMAIN_PORT_DDI_E_IO;
3529                 break;
3530         case PORT_F:
3531                 intel_dig_port->ddi_io_power_domain =
3532                         POWER_DOMAIN_PORT_DDI_F_IO;
3533                 break;
3534         default:
3535                 MISSING_CASE(port);
3536         }
3537
3538         intel_infoframe_init(intel_dig_port);
3539
3540         if (init_dp) {
3541                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3542                         goto err;
3543
3544                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3545                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3546         }
3547
3548         /* In theory we don't need the encoder->type check, but leave it just in
3549          * case we have some really bad VBTs... */
3550         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3551                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3552                         goto err;
3553         }
3554
3555         if (init_lspcon) {
3556                 if (lspcon_init(intel_dig_port))
3557                         /* TODO: handle hdmi info frame part */
3558                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3559                                 port_name(port));
3560                 else
3561                         /*
3562                          * LSPCON init faied, but DP init was success, so
3563                          * lets try to drive as DP++ port.
3564                          */
3565                         DRM_ERROR("LSPCON init failed on port %c\n",
3566                                 port_name(port));
3567         }
3568
3569         return;
3570
3571 err:
3572         drm_encoder_cleanup(encoder);
3573         kfree(intel_dig_port);
3574 }