drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 struct icl_combo_phy_ddi_buf_trans {
 497         u32 dw2_swing_select;
 498         u32 dw2_swing_scalar;
 499         u32 dw4_scaling;
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 0.85V for DP */
 503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 504                                 /* Voltage mV  db    */
 505         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 506         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 507         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 508         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 509         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 510         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 511         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 512         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 513         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 514         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 515 };
 516
 517 /* FIXME - After table is updated in Bspec */
 518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 520                                 /* Voltage mV  db    */
 521         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 522         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 523         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 524         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 525         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 527         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 528         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 530         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 531 };
 532
 533 /* Voltage Swing Programming for VccIO 0.95V for DP */
 534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 535                                 /* Voltage mV  db    */
 536         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 537         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 538         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 539         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 540         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 541         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 542         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 543         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 544         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 545         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 546 };
 547
 548 /* FIXME - After table is updated in Bspec */
 549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 551                                 /* Voltage mV  db    */
 552         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 553         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 554         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 555         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 556         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 558         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 559         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 561         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 562 };
 563
 564 /* Voltage Swing Programming for VccIO 1.05V for DP */
 565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 566                                 /* Voltage mV  db    */
 567         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 568         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 569         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 570         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 571         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 572         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 573         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 574         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 575         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 576         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 577 };
 578
 579 /* FIXME - After table is updated in Bspec */
 580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 582                                 /* Voltage mV  db    */
 583         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 584         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 585         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 586         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 587         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 589         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 590         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 592         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 593 };
 594
 595 struct icl_mg_phy_ddi_buf_trans {
 596         u32 cri_txdeemph_override_5_0;
 597         u32 cri_txdeemph_override_11_6;
 598         u32 cri_txdeemph_override_17_12;
 599 };
 600
 601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 602                                 /* Voltage swing  pre-emphasis */
 603         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 604         { 0x0, 0x23, 0x08 },    /* 0              1   */
 605         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 606         { 0x0, 0x00, 0x00 },    /* 0              3   */
 607         { 0x0, 0x23, 0x00 },    /* 1              0   */
 608         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 609         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 610         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 611         { 0x0, 0x33, 0x0C },    /* 2              1   */
 612         { 0x0, 0x00, 0x00 },    /* 3              0   */
 613 };
 614
 615 static const struct ddi_buf_trans *
 616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (dev_priv->vbt.edp.low_vswing) {
 619                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 620                 return bdw_ddi_translations_edp;
 621         } else {
 622                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 623                 return bdw_ddi_translations_dp;
 624         }
 625 }
 626
 627 static const struct ddi_buf_trans *
 628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 629 {
 630         if (IS_SKL_ULX(dev_priv)) {
 631                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 632                 return skl_y_ddi_translations_dp;
 633         } else if (IS_SKL_ULT(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 635                 return skl_u_ddi_translations_dp;
 636         } else {
 637                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 638                 return skl_ddi_translations_dp;
 639         }
 640 }
 641
 642 static const struct ddi_buf_trans *
 643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 644 {
 645         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 646                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 647                 return kbl_y_ddi_translations_dp;
 648         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 649                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 650                 return kbl_u_ddi_translations_dp;
 651         } else {
 652                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 653                 return kbl_ddi_translations_dp;
 654         }
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 659 {
 660         if (dev_priv->vbt.edp.low_vswing) {
 661                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 663                         return skl_y_ddi_translations_edp;
 664                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 665                            IS_CFL_ULT(dev_priv)) {
 666                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 667                         return skl_u_ddi_translations_edp;
 668                 } else {
 669                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 670                         return skl_ddi_translations_edp;
 671                 }
 672         }
 673
 674         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 675                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 676         else
 677                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct ddi_buf_trans *
 681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 684                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 685                 return skl_y_ddi_translations_hdmi;
 686         } else {
 687                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 688                 return skl_ddi_translations_hdmi;
 689         }
 690 }
 691
 692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 693 {
 694         /* Only DDIA and DDIE can select the 10th register with DP */
 695         if (port == PORT_A || port == PORT_E)
 696                 return min(n_entries, 10);
 697         else
 698                 return min(n_entries, 9);
 699 }
 700
 701 static const struct ddi_buf_trans *
 702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 703                            enum port port, int *n_entries)
 704 {
 705         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 706                 const struct ddi_buf_trans *ddi_translations =
 707                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 708                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 709                 return ddi_translations;
 710         } else if (IS_SKYLAKE(dev_priv)) {
 711                 const struct ddi_buf_trans *ddi_translations =
 712                         skl_get_buf_trans_dp(dev_priv, n_entries);
 713                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 714                 return ddi_translations;
 715         } else if (IS_BROADWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 717                 return  bdw_ddi_translations_dp;
 718         } else if (IS_HASWELL(dev_priv)) {
 719                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 720                 return hsw_ddi_translations_dp;
 721         }
 722
 723         *n_entries = 0;
 724         return NULL;
 725 }
 726
 727 static const struct ddi_buf_trans *
 728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 729                             enum port port, int *n_entries)
 730 {
 731         if (IS_GEN9_BC(dev_priv)) {
 732                 const struct ddi_buf_trans *ddi_translations =
 733                         skl_get_buf_trans_edp(dev_priv, n_entries);
 734                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 735                 return ddi_translations;
 736         } else if (IS_BROADWELL(dev_priv)) {
 737                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 740                 return hsw_ddi_translations_dp;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct ddi_buf_trans *
 748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 749                             int *n_entries)
 750 {
 751         if (IS_BROADWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 753                 return bdw_ddi_translations_fdi;
 754         } else if (IS_HASWELL(dev_priv)) {
 755                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 756                 return hsw_ddi_translations_fdi;
 757         }
 758
 759         *n_entries = 0;
 760         return NULL;
 761 }
 762
 763 static const struct ddi_buf_trans *
 764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 765                              int *n_entries)
 766 {
 767         if (IS_GEN9_BC(dev_priv)) {
 768                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 771                 return bdw_ddi_translations_hdmi;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 774                 return hsw_ddi_translations_hdmi;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct bxt_ddi_buf_trans *
 782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 785         return bxt_ddi_translations_dp;
 786 }
 787
 788 static const struct bxt_ddi_buf_trans *
 789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 790 {
 791         if (dev_priv->vbt.edp.low_vswing) {
 792                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 793                 return bxt_ddi_translations_edp;
 794         }
 795
 796         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 803         return bxt_ddi_translations_hdmi;
 804 }
 805
 806 static const struct cnl_ddi_buf_trans *
 807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 808 {
 809         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 810
 811         if (voltage == VOLTAGE_INFO_0_85V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 813                 return cnl_ddi_translations_hdmi_0_85V;
 814         } else if (voltage == VOLTAGE_INFO_0_95V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 816                 return cnl_ddi_translations_hdmi_0_95V;
 817         } else if (voltage == VOLTAGE_INFO_1_05V) {
 818                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 819                 return cnl_ddi_translations_hdmi_1_05V;
 820         } else {
 821                 *n_entries = 1; /* shut up gcc */
 822                 MISSING_CASE(voltage);
 823         }
 824         return NULL;
 825 }
 826
 827 static const struct cnl_ddi_buf_trans *
 828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 829 {
 830         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 831
 832         if (voltage == VOLTAGE_INFO_0_85V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 834                 return cnl_ddi_translations_dp_0_85V;
 835         } else if (voltage == VOLTAGE_INFO_0_95V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 837                 return cnl_ddi_translations_dp_0_95V;
 838         } else if (voltage == VOLTAGE_INFO_1_05V) {
 839                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 840                 return cnl_ddi_translations_dp_1_05V;
 841         } else {
 842                 *n_entries = 1; /* shut up gcc */
 843                 MISSING_CASE(voltage);
 844         }
 845         return NULL;
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 850 {
 851         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 852
 853         if (dev_priv->vbt.edp.low_vswing) {
 854                 if (voltage == VOLTAGE_INFO_0_85V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 856                         return cnl_ddi_translations_edp_0_85V;
 857                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 859                         return cnl_ddi_translations_edp_0_95V;
 860                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 861                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 862                         return cnl_ddi_translations_edp_1_05V;
 863                 } else {
 864                         *n_entries = 1; /* shut up gcc */
 865                         MISSING_CASE(voltage);
 866                 }
 867                 return NULL;
 868         } else {
 869                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 870         }
 871 }
 872
 873 static const struct icl_combo_phy_ddi_buf_trans *
 874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 875                         int type, int *n_entries)
 876 {
 877         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 878
 879         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 880                 switch (voltage) {
 881                 case VOLTAGE_INFO_0_85V:
 882                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 883                         return icl_combo_phy_ddi_translations_edp_0_85V;
 884                 case VOLTAGE_INFO_0_95V:
 885                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 886                         return icl_combo_phy_ddi_translations_edp_0_95V;
 887                 case VOLTAGE_INFO_1_05V:
 888                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 889                         return icl_combo_phy_ddi_translations_edp_1_05V;
 890                 default:
 891                         MISSING_CASE(voltage);
 892                         return NULL;
 893                 }
 894         } else {
 895                 switch (voltage) {
 896                 case VOLTAGE_INFO_0_85V:
 897                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 898                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 899                 case VOLTAGE_INFO_0_95V:
 900                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 901                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 902                 case VOLTAGE_INFO_1_05V:
 903                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 904                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 905                 default:
 906                         MISSING_CASE(voltage);
 907                         return NULL;
 908                 }
 909         }
 910 }
 911
 912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 913 {
 914         int n_entries, level, default_entry;
 915
 916         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 917
 918         if (IS_ICELAKE(dev_priv)) {
 919                 if (intel_port_is_combophy(dev_priv, port))
 920                         icl_get_combo_buf_trans(dev_priv, port,
 921                                                 INTEL_OUTPUT_HDMI, &n_entries);
 922                 else
 923                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 924                 default_entry = n_entries - 1;
 925         } else if (IS_CANNONLAKE(dev_priv)) {
 926                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 927                 default_entry = n_entries - 1;
 928         } else if (IS_GEN9_LP(dev_priv)) {
 929                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 930                 default_entry = n_entries - 1;
 931         } else if (IS_GEN9_BC(dev_priv)) {
 932                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 933                 default_entry = 8;
 934         } else if (IS_BROADWELL(dev_priv)) {
 935                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 936                 default_entry = 7;
 937         } else if (IS_HASWELL(dev_priv)) {
 938                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 939                 default_entry = 6;
 940         } else {
 941                 WARN(1, "ddi translation table missing\n");
 942                 return 0;
 943         }
 944
 945         /* Choose a good default if VBT is badly populated */
 946         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 947                 level = default_entry;
 948
 949         if (WARN_ON_ONCE(n_entries == 0))
 950                 return 0;
 951         if (WARN_ON_ONCE(level >= n_entries))
 952                 level = n_entries - 1;
 953
 954         return level;
 955 }
 956
 957 /*
 958  * Starting with Haswell, DDI port buffers must be programmed with correct
 959  * values in advance. This function programs the correct values for
 960  * DP/eDP/FDI use cases.
 961  */
 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 966         u32 iboost_bit = 0;
 967         int i, n_entries;
 968         enum port port = encoder->port;
 969         const struct ddi_buf_trans *ddi_translations;
 970
 971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 972                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 973                                                                &n_entries);
 974         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 975                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 976                                                                &n_entries);
 977         else
 978                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 979                                                               &n_entries);
 980
 981         /* If we're boosting the current, set bit 31 of trans1 */
 982         if (IS_GEN9_BC(dev_priv) &&
 983             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 984                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 985
 986         for (i = 0; i < n_entries; i++) {
 987                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 988                            ddi_translations[i].trans1 | iboost_bit);
 989                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 990                            ddi_translations[i].trans2);
 991         }
 992 }
 993
 994 /*
 995  * Starting with Haswell, DDI port buffers must be programmed with correct
 996  * values in advance. This function programs the correct values for
 997  * HDMI/DVI use cases.
 998  */
 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000                                            int level)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003         u32 iboost_bit = 0;
1004         int n_entries;
1005         enum port port = encoder->port;
1006         const struct ddi_buf_trans *ddi_translations;
1007
1008         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010         if (WARN_ON_ONCE(!ddi_translations))
1011                 return;
1012         if (WARN_ON_ONCE(level >= n_entries))
1013                 level = n_entries - 1;
1014
1015         /* If we're boosting the current, set bit 31 of trans1 */
1016         if (IS_GEN9_BC(dev_priv) &&
1017             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020         /* Entry 9 is for HDMI: */
1021         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022                    ddi_translations[level].trans1 | iboost_bit);
1023         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024                    ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028                                     enum port port)
1029 {
1030         i915_reg_t reg = DDI_BUF_CTL(port);
1031         int i;
1032
1033         for (i = 0; i < 16; i++) {
1034                 udelay(1);
1035                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036                         return;
1037         }
1038         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043         switch (pll->info->id) {
1044         case DPLL_ID_WRPLL1:
1045                 return PORT_CLK_SEL_WRPLL1;
1046         case DPLL_ID_WRPLL2:
1047                 return PORT_CLK_SEL_WRPLL2;
1048         case DPLL_ID_SPLL:
1049                 return PORT_CLK_SEL_SPLL;
1050         case DPLL_ID_LCPLL_810:
1051                 return PORT_CLK_SEL_LCPLL_810;
1052         case DPLL_ID_LCPLL_1350:
1053                 return PORT_CLK_SEL_LCPLL_1350;
1054         case DPLL_ID_LCPLL_2700:
1055                 return PORT_CLK_SEL_LCPLL_2700;
1056         default:
1057                 MISSING_CASE(pll->info->id);
1058                 return PORT_CLK_SEL_NONE;
1059         }
1060 }
1061
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063                                        const struct intel_crtc_state *crtc_state)
1064 {
1065         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1066         int clock = crtc_state->port_clock;
1067         const enum intel_dpll_id id = pll->info->id;
1068
1069         switch (id) {
1070         default:
1071                 MISSING_CASE(id);
1072                 /* fall through */
1073         case DPLL_ID_ICL_DPLL0:
1074         case DPLL_ID_ICL_DPLL1:
1075                 return DDI_CLK_SEL_NONE;
1076         case DPLL_ID_ICL_TBTPLL:
1077                 switch (clock) {
1078                 case 162000:
1079                         return DDI_CLK_SEL_TBT_162;
1080                 case 270000:
1081                         return DDI_CLK_SEL_TBT_270;
1082                 case 540000:
1083                         return DDI_CLK_SEL_TBT_540;
1084                 case 810000:
1085                         return DDI_CLK_SEL_TBT_810;
1086                 default:
1087                         MISSING_CASE(clock);
1088                         break;
1089                 }
1090         case DPLL_ID_ICL_MGPLL1:
1091         case DPLL_ID_ICL_MGPLL2:
1092         case DPLL_ID_ICL_MGPLL3:
1093         case DPLL_ID_ICL_MGPLL4:
1094                 return DDI_CLK_SEL_MG;
1095         }
1096 }
1097
1098 /* Starting with Haswell, different DDI ports can work in FDI mode for
1099  * connection to the PCH-located connectors. For this, it is necessary to train
1100  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101  *
1102  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104  * DDI A (which is used for eDP)
1105  */
1106
1107 void hsw_fdi_link_train(struct intel_crtc *crtc,
1108                         const struct intel_crtc_state *crtc_state)
1109 {
1110         struct drm_device *dev = crtc->base.dev;
1111         struct drm_i915_private *dev_priv = to_i915(dev);
1112         struct intel_encoder *encoder;
1113         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1114
1115         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1116                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1117                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1118         }
1119
1120         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121          * mode set "sequence for CRT port" document:
1122          * - TP1 to TP2 time with the default value
1123          * - FDI delay to 90h
1124          *
1125          * WaFDIAutoLinkSetTimingOverrride:hsw
1126          */
1127         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1128                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1129                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131         /* Enable the PCH Receiver FDI PLL */
1132         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1133                      FDI_RX_PLL_ENABLE |
1134                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1135         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136         POSTING_READ(FDI_RX_CTL(PIPE_A));
1137         udelay(220);
1138
1139         /* Switch from Rawclk to PCDclk */
1140         rx_ctl_val |= FDI_PCDCLK;
1141         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1142
1143         /* Configure Port Clock Select */
1144         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1145         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1147
1148         /* Start the training iterating through available voltages and emphasis,
1149          * testing each value twice. */
1150         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1151                 /* Configure DP_TP_CTL with auto-training */
1152                 I915_WRITE(DP_TP_CTL(PORT_E),
1153                                         DP_TP_CTL_FDI_AUTOTRAIN |
1154                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1156                                         DP_TP_CTL_ENABLE);
1157
1158                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159                  * DDI E does not support port reversal, the functionality is
1160                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161                  * port reversal bit */
1162                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1163                            DDI_BUF_CTL_ENABLE |
1164                            ((crtc_state->fdi_lanes - 1) << 1) |
1165                            DDI_BUF_TRANS_SELECT(i / 2));
1166                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
1168                 udelay(600);
1169
1170                 /* Program PCH FDI Receiver TU */
1171                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1172
1173                 /* Enable PCH FDI Receiver with auto-training */
1174                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1175                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1177
1178                 /* Wait for FDI receiver lane calibration */
1179                 udelay(30);
1180
1181                 /* Unset FDI_RX_MISC pwrdn lanes */
1182                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1186
1187                 /* Wait for FDI auto training time */
1188                 udelay(5);
1189
1190                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1192                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1193                         break;
1194                 }
1195
1196                 /*
1197                  * Leave things enabled even if we failed to train FDI.
1198                  * Results in less fireworks from the state checker.
1199                  */
1200                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201                         DRM_ERROR("FDI link training failed!\n");
1202                         break;
1203                 }
1204
1205                 rx_ctl_val &= ~FDI_RX_ENABLE;
1206                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
1209                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210                 temp &= ~DDI_BUF_CTL_ENABLE;
1211                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
1214                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1215                 temp = I915_READ(DP_TP_CTL(PORT_E));
1216                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219                 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1222
1223                 /* Reset FDI_RX_MISC pwrdn lanes */
1224                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1225                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1227                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1229         }
1230
1231         /* Enable normal pixel sending for FDI */
1232         I915_WRITE(DP_TP_CTL(PORT_E),
1233                    DP_TP_CTL_FDI_AUTOTRAIN |
1234                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1235                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236                    DP_TP_CTL_ENABLE);
1237 }
1238
1239 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1240 {
1241         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242         struct intel_digital_port *intel_dig_port =
1243                 enc_to_dig_port(&encoder->base);
1244
1245         intel_dp->DP = intel_dig_port->saved_port_bits |
1246                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1247         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1248 }
1249
1250 static struct intel_encoder *
1251 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1252 {
1253         struct drm_device *dev = crtc->base.dev;
1254         struct intel_encoder *encoder, *ret = NULL;
1255         int num_encoders = 0;
1256
1257         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258                 ret = encoder;
1259                 num_encoders++;
1260         }
1261
1262         if (num_encoders != 1)
1263                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1264                      pipe_name(crtc->pipe));
1265
1266         BUG_ON(ret == NULL);
1267         return ret;
1268 }
1269
1270 #define LC_FREQ 2700
1271
1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273                                    i915_reg_t reg)
1274 {
1275         int refclk = LC_FREQ;
1276         int n, p, r;
1277         u32 wrpll;
1278
1279         wrpll = I915_READ(reg);
1280         switch (wrpll & WRPLL_PLL_REF_MASK) {
1281         case WRPLL_PLL_SSC:
1282         case WRPLL_PLL_NON_SSC:
1283                 /*
1284                  * We could calculate spread here, but our checking
1285                  * code only cares about 5% accuracy, and spread is a max of
1286                  * 0.5% downspread.
1287                  */
1288                 refclk = 135;
1289                 break;
1290         case WRPLL_PLL_LCPLL:
1291                 refclk = LC_FREQ;
1292                 break;
1293         default:
1294                 WARN(1, "bad wrpll refclk\n");
1295                 return 0;
1296         }
1297
1298         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
1302         /* Convert to KHz, p & r have a fixed point portion */
1303         return (refclk * n * 100) / (p * r);
1304 }
1305
1306 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307                                enum intel_dpll_id pll_id)
1308 {
1309         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1310         uint32_t cfgcr1_val, cfgcr2_val;
1311         uint32_t p0, p1, p2, dco_freq;
1312
1313         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1315
1316         cfgcr1_val = I915_READ(cfgcr1_reg);
1317         cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1323                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324         else
1325                 p1 = 1;
1326
1327
1328         switch (p0) {
1329         case DPLL_CFGCR2_PDIV_1:
1330                 p0 = 1;
1331                 break;
1332         case DPLL_CFGCR2_PDIV_2:
1333                 p0 = 2;
1334                 break;
1335         case DPLL_CFGCR2_PDIV_3:
1336                 p0 = 3;
1337                 break;
1338         case DPLL_CFGCR2_PDIV_7:
1339                 p0 = 7;
1340                 break;
1341         }
1342
1343         switch (p2) {
1344         case DPLL_CFGCR2_KDIV_5:
1345                 p2 = 5;
1346                 break;
1347         case DPLL_CFGCR2_KDIV_2:
1348                 p2 = 2;
1349                 break;
1350         case DPLL_CFGCR2_KDIV_3:
1351                 p2 = 3;
1352                 break;
1353         case DPLL_CFGCR2_KDIV_1:
1354                 p2 = 1;
1355                 break;
1356         }
1357
1358         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361                 1000) / 0x8000;
1362
1363         return dco_freq / (p0 * p1 * p2 * 5);
1364 }
1365
1366 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1367                                enum intel_dpll_id pll_id)
1368 {
1369         uint32_t cfgcr0, cfgcr1;
1370         uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
1372         if (INTEL_GEN(dev_priv) >= 11) {
1373                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375         } else {
1376                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378         }
1379
1380         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386         else
1387                 p1 = 1;
1388
1389
1390         switch (p0) {
1391         case DPLL_CFGCR1_PDIV_2:
1392                 p0 = 2;
1393                 break;
1394         case DPLL_CFGCR1_PDIV_3:
1395                 p0 = 3;
1396                 break;
1397         case DPLL_CFGCR1_PDIV_5:
1398                 p0 = 5;
1399                 break;
1400         case DPLL_CFGCR1_PDIV_7:
1401                 p0 = 7;
1402                 break;
1403         }
1404
1405         switch (p2) {
1406         case DPLL_CFGCR1_KDIV_1:
1407                 p2 = 1;
1408                 break;
1409         case DPLL_CFGCR1_KDIV_2:
1410                 p2 = 2;
1411                 break;
1412         case DPLL_CFGCR1_KDIV_4:
1413                 p2 = 4;
1414                 break;
1415         }
1416
1417         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1418
1419         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1423
1424         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425                 return 0;
1426
1427         return dco_freq / (p0 * p1 * p2 * 5);
1428 }
1429
1430 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1431                                  enum port port)
1432 {
1433         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1434
1435         switch (val) {
1436         case DDI_CLK_SEL_NONE:
1437                 return 0;
1438         case DDI_CLK_SEL_TBT_162:
1439                 return 162000;
1440         case DDI_CLK_SEL_TBT_270:
1441                 return 270000;
1442         case DDI_CLK_SEL_TBT_540:
1443                 return 540000;
1444         case DDI_CLK_SEL_TBT_810:
1445                 return 810000;
1446         default:
1447                 MISSING_CASE(val);
1448                 return 0;
1449         }
1450 }
1451
1452 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1453                                 enum port port)
1454 {
1455         u32 mg_pll_div0, mg_clktop_hsclkctl;
1456         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1457         u64 tmp;
1458
1459         refclk = dev_priv->cdclk.hw.ref;
1460
1461         mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1463
1464         m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1469
1470         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1472                 div1 = 2;
1473                 break;
1474         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1475                 div1 = 3;
1476                 break;
1477         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1478                 div1 = 5;
1479                 break;
1480         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1481                 div1 = 7;
1482                 break;
1483         default:
1484                 MISSING_CASE(mg_clktop_hsclkctl);
1485                 return 0;
1486         }
1487
1488         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490         /* div2 value of 0 is same as 1 means no div */
1491         if (div2 == 0)
1492                 div2 = 1;
1493
1494         /*
1495          * Adjust the original formula to delay the division by 2^22 in order to
1496          * minimize possible rounding errors.
1497          */
1498         tmp = (u64)m1 * m2_int * refclk +
1499               (((u64)m1 * m2_frac * refclk) >> 22);
1500         tmp = div_u64(tmp, 5 * div1 * div2);
1501
1502         return tmp;
1503 }
1504
1505 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1506 {
1507         int dotclock;
1508
1509         if (pipe_config->has_pch_encoder)
1510                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1511                                                     &pipe_config->fdi_m_n);
1512         else if (intel_crtc_has_dp_encoder(pipe_config))
1513                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514                                                     &pipe_config->dp_m_n);
1515         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1516                 dotclock = pipe_config->port_clock * 2 / 3;
1517         else
1518                 dotclock = pipe_config->port_clock;
1519
1520         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1521                 dotclock *= 2;
1522
1523         if (pipe_config->pixel_multiplier)
1524                 dotclock /= pipe_config->pixel_multiplier;
1525
1526         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1527 }
1528
1529 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1530                               struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533         enum port port = encoder->port;
1534         int link_clock = 0;
1535         uint32_t pll_id;
1536
1537         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538         if (intel_port_is_combophy(dev_priv, port)) {
1539                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1541                 else
1542                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1543                                                                 pll_id);
1544         } else {
1545                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1546                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1547                 else
1548                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1549         }
1550
1551         pipe_config->port_clock = link_clock;
1552         ddi_dotclock_get(pipe_config);
1553 }
1554
1555 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1556                               struct intel_crtc_state *pipe_config)
1557 {
1558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1559         int link_clock = 0;
1560         uint32_t cfgcr0;
1561         enum intel_dpll_id pll_id;
1562
1563         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1564
1565         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1566
1567         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1569         } else {
1570                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572                 switch (link_clock) {
1573                 case DPLL_CFGCR0_LINK_RATE_810:
1574                         link_clock = 81000;
1575                         break;
1576                 case DPLL_CFGCR0_LINK_RATE_1080:
1577                         link_clock = 108000;
1578                         break;
1579                 case DPLL_CFGCR0_LINK_RATE_1350:
1580                         link_clock = 135000;
1581                         break;
1582                 case DPLL_CFGCR0_LINK_RATE_1620:
1583                         link_clock = 162000;
1584                         break;
1585                 case DPLL_CFGCR0_LINK_RATE_2160:
1586                         link_clock = 216000;
1587                         break;
1588                 case DPLL_CFGCR0_LINK_RATE_2700:
1589                         link_clock = 270000;
1590                         break;
1591                 case DPLL_CFGCR0_LINK_RATE_3240:
1592                         link_clock = 324000;
1593                         break;
1594                 case DPLL_CFGCR0_LINK_RATE_4050:
1595                         link_clock = 405000;
1596                         break;
1597                 default:
1598                         WARN(1, "Unsupported link rate\n");
1599                         break;
1600                 }
1601                 link_clock *= 2;
1602         }
1603
1604         pipe_config->port_clock = link_clock;
1605
1606         ddi_dotclock_get(pipe_config);
1607 }
1608
1609 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1610                                 struct intel_crtc_state *pipe_config)
1611 {
1612         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1613         int link_clock = 0;
1614         uint32_t dpll_ctl1;
1615         enum intel_dpll_id pll_id;
1616
1617         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1618
1619         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1620
1621         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1622                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1623         } else {
1624                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1625                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1626
1627                 switch (link_clock) {
1628                 case DPLL_CTRL1_LINK_RATE_810:
1629                         link_clock = 81000;
1630                         break;
1631                 case DPLL_CTRL1_LINK_RATE_1080:
1632                         link_clock = 108000;
1633                         break;
1634                 case DPLL_CTRL1_LINK_RATE_1350:
1635                         link_clock = 135000;
1636                         break;
1637                 case DPLL_CTRL1_LINK_RATE_1620:
1638                         link_clock = 162000;
1639                         break;
1640                 case DPLL_CTRL1_LINK_RATE_2160:
1641                         link_clock = 216000;
1642                         break;
1643                 case DPLL_CTRL1_LINK_RATE_2700:
1644                         link_clock = 270000;
1645                         break;
1646                 default:
1647                         WARN(1, "Unsupported link rate\n");
1648                         break;
1649                 }
1650                 link_clock *= 2;
1651         }
1652
1653         pipe_config->port_clock = link_clock;
1654
1655         ddi_dotclock_get(pipe_config);
1656 }
1657
1658 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1659                               struct intel_crtc_state *pipe_config)
1660 {
1661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1662         int link_clock = 0;
1663         u32 val, pll;
1664
1665         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1666         switch (val & PORT_CLK_SEL_MASK) {
1667         case PORT_CLK_SEL_LCPLL_810:
1668                 link_clock = 81000;
1669                 break;
1670         case PORT_CLK_SEL_LCPLL_1350:
1671                 link_clock = 135000;
1672                 break;
1673         case PORT_CLK_SEL_LCPLL_2700:
1674                 link_clock = 270000;
1675                 break;
1676         case PORT_CLK_SEL_WRPLL1:
1677                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1678                 break;
1679         case PORT_CLK_SEL_WRPLL2:
1680                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1681                 break;
1682         case PORT_CLK_SEL_SPLL:
1683                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1684                 if (pll == SPLL_PLL_FREQ_810MHz)
1685                         link_clock = 81000;
1686                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1687                         link_clock = 135000;
1688                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1689                         link_clock = 270000;
1690                 else {
1691                         WARN(1, "bad spll freq\n");
1692                         return;
1693                 }
1694                 break;
1695         default:
1696                 WARN(1, "bad port clock sel\n");
1697                 return;
1698         }
1699
1700         pipe_config->port_clock = link_clock * 2;
1701
1702         ddi_dotclock_get(pipe_config);
1703 }
1704
1705 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1706 {
1707         struct intel_dpll_hw_state *state;
1708         struct dpll clock;
1709
1710         /* For DDI ports we always use a shared PLL. */
1711         if (WARN_ON(!crtc_state->shared_dpll))
1712                 return 0;
1713
1714         state = &crtc_state->dpll_hw_state;
1715
1716         clock.m1 = 2;
1717         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1718         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1719                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1720         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1721         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1722         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1723
1724         return chv_calc_dpll_params(100000, &clock);
1725 }
1726
1727 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1728                               struct intel_crtc_state *pipe_config)
1729 {
1730         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1731
1732         ddi_dotclock_get(pipe_config);
1733 }
1734
1735 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1736                                 struct intel_crtc_state *pipe_config)
1737 {
1738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1739
1740         if (IS_ICELAKE(dev_priv))
1741                 icl_ddi_clock_get(encoder, pipe_config);
1742         else if (IS_CANNONLAKE(dev_priv))
1743                 cnl_ddi_clock_get(encoder, pipe_config);
1744         else if (IS_GEN9_LP(dev_priv))
1745                 bxt_ddi_clock_get(encoder, pipe_config);
1746         else if (IS_GEN9_BC(dev_priv))
1747                 skl_ddi_clock_get(encoder, pipe_config);
1748         else if (INTEL_GEN(dev_priv) <= 8)
1749                 hsw_ddi_clock_get(encoder, pipe_config);
1750 }
1751
1752 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1753 {
1754         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1755         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1756         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1757         u32 temp;
1758
1759         if (!intel_crtc_has_dp_encoder(crtc_state))
1760                 return;
1761
1762         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1763
1764         temp = TRANS_MSA_SYNC_CLK;
1765
1766         if (crtc_state->limited_color_range)
1767                 temp |= TRANS_MSA_CEA_RANGE;
1768
1769         switch (crtc_state->pipe_bpp) {
1770         case 18:
1771                 temp |= TRANS_MSA_6_BPC;
1772                 break;
1773         case 24:
1774                 temp |= TRANS_MSA_8_BPC;
1775                 break;
1776         case 30:
1777                 temp |= TRANS_MSA_10_BPC;
1778                 break;
1779         case 36:
1780                 temp |= TRANS_MSA_12_BPC;
1781                 break;
1782         default:
1783                 MISSING_CASE(crtc_state->pipe_bpp);
1784                 break;
1785         }
1786
1787         /*
1788          * As per DP 1.2 spec section 2.3.4.3 while sending
1789          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1790          * colorspace information. The output colorspace encoding is BT601.
1791          */
1792         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1793                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1794         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1795 }
1796
1797 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1798                                     bool state)
1799 {
1800         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1801         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1803         uint32_t temp;
1804
1805         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1806         if (state == true)
1807                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1808         else
1809                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1810         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1811 }
1812
1813 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1814 {
1815         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1816         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1818         enum pipe pipe = crtc->pipe;
1819         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1820         enum port port = encoder->port;
1821         uint32_t temp;
1822
1823         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1824         temp = TRANS_DDI_FUNC_ENABLE;
1825         temp |= TRANS_DDI_SELECT_PORT(port);
1826
1827         switch (crtc_state->pipe_bpp) {
1828         case 18:
1829                 temp |= TRANS_DDI_BPC_6;
1830                 break;
1831         case 24:
1832                 temp |= TRANS_DDI_BPC_8;
1833                 break;
1834         case 30:
1835                 temp |= TRANS_DDI_BPC_10;
1836                 break;
1837         case 36:
1838                 temp |= TRANS_DDI_BPC_12;
1839                 break;
1840         default:
1841                 BUG();
1842         }
1843
1844         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1845                 temp |= TRANS_DDI_PVSYNC;
1846         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1847                 temp |= TRANS_DDI_PHSYNC;
1848
1849         if (cpu_transcoder == TRANSCODER_EDP) {
1850                 switch (pipe) {
1851                 case PIPE_A:
1852                         /* On Haswell, can only use the always-on power well for
1853                          * eDP when not using the panel fitter, and when not
1854                          * using motion blur mitigation (which we don't
1855                          * support). */
1856                         if (IS_HASWELL(dev_priv) &&
1857                             (crtc_state->pch_pfit.enabled ||
1858                              crtc_state->pch_pfit.force_thru))
1859                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1860                         else
1861                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1862                         break;
1863                 case PIPE_B:
1864                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1865                         break;
1866                 case PIPE_C:
1867                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1868                         break;
1869                 default:
1870                         BUG();
1871                         break;
1872                 }
1873         }
1874
1875         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1876                 if (crtc_state->has_hdmi_sink)
1877                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1878                 else
1879                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1880
1881                 if (crtc_state->hdmi_scrambling)
1882                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1883                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1884                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1885         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1886                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1887                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1888         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1889                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1890                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1891         } else {
1892                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1893                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1894         }
1895
1896         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1897 }
1898
1899 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1900 {
1901         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1902         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1903         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1904         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1905         uint32_t val = I915_READ(reg);
1906
1907         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1908         val |= TRANS_DDI_PORT_NONE;
1909         I915_WRITE(reg, val);
1910
1911         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1912             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1913                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1914                 /* Quirk time at 100ms for reliable operation */
1915                 msleep(100);
1916         }
1917 }
1918
1919 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1920                                      bool enable)
1921 {
1922         struct drm_device *dev = intel_encoder->base.dev;
1923         struct drm_i915_private *dev_priv = to_i915(dev);
1924         enum pipe pipe = 0;
1925         int ret = 0;
1926         uint32_t tmp;
1927
1928         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1929                                                 intel_encoder->power_domain)))
1930                 return -ENXIO;
1931
1932         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1933                 ret = -EIO;
1934                 goto out;
1935         }
1936
1937         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1938         if (enable)
1939                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1940         else
1941                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1942         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1943 out:
1944         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1945         return ret;
1946 }
1947
1948 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1949 {
1950         struct drm_device *dev = intel_connector->base.dev;
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         struct intel_encoder *encoder = intel_connector->encoder;
1953         int type = intel_connector->base.connector_type;
1954         enum port port = encoder->port;
1955         enum pipe pipe = 0;
1956         enum transcoder cpu_transcoder;
1957         uint32_t tmp;
1958         bool ret;
1959
1960         if (!intel_display_power_get_if_enabled(dev_priv,
1961                                                 encoder->power_domain))
1962                 return false;
1963
1964         if (!encoder->get_hw_state(encoder, &pipe)) {
1965                 ret = false;
1966                 goto out;
1967         }
1968
1969         if (port == PORT_A)
1970                 cpu_transcoder = TRANSCODER_EDP;
1971         else
1972                 cpu_transcoder = (enum transcoder) pipe;
1973
1974         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1975
1976         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1977         case TRANS_DDI_MODE_SELECT_HDMI:
1978         case TRANS_DDI_MODE_SELECT_DVI:
1979                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1980                 break;
1981
1982         case TRANS_DDI_MODE_SELECT_DP_SST:
1983                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1984                       type == DRM_MODE_CONNECTOR_DisplayPort;
1985                 break;
1986
1987         case TRANS_DDI_MODE_SELECT_DP_MST:
1988                 /* if the transcoder is in MST state then
1989                  * connector isn't connected */
1990                 ret = false;
1991                 break;
1992
1993         case TRANS_DDI_MODE_SELECT_FDI:
1994                 ret = type == DRM_MODE_CONNECTOR_VGA;
1995                 break;
1996
1997         default:
1998                 ret = false;
1999                 break;
2000         }
2001
2002 out:
2003         intel_display_power_put(dev_priv, encoder->power_domain);
2004
2005         return ret;
2006 }
2007
2008 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2009                             enum pipe *pipe)
2010 {
2011         struct drm_device *dev = encoder->base.dev;
2012         struct drm_i915_private *dev_priv = to_i915(dev);
2013         enum port port = encoder->port;
2014         enum pipe p;
2015         u32 tmp;
2016         bool ret;
2017
2018         if (!intel_display_power_get_if_enabled(dev_priv,
2019                                                 encoder->power_domain))
2020                 return false;
2021
2022         ret = false;
2023
2024         tmp = I915_READ(DDI_BUF_CTL(port));
2025
2026         if (!(tmp & DDI_BUF_CTL_ENABLE))
2027                 goto out;
2028
2029         if (port == PORT_A) {
2030                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2031
2032                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2033                 case TRANS_DDI_EDP_INPUT_A_ON:
2034                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2035                         *pipe = PIPE_A;
2036                         break;
2037                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2038                         *pipe = PIPE_B;
2039                         break;
2040                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2041                         *pipe = PIPE_C;
2042                         break;
2043                 }
2044
2045                 ret = true;
2046
2047                 goto out;
2048         }
2049
2050         for_each_pipe(dev_priv, p) {
2051                 enum transcoder cpu_transcoder = (enum transcoder) p;
2052
2053                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2054
2055                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2056                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2057                             TRANS_DDI_MODE_SELECT_DP_MST)
2058                                 goto out;
2059
2060                         *pipe = p;
2061                         ret = true;
2062
2063                         goto out;
2064                 }
2065         }
2066
2067         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2068
2069 out:
2070         if (ret && IS_GEN9_LP(dev_priv)) {
2071                 tmp = I915_READ(BXT_PHY_CTL(port));
2072                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2073                             BXT_PHY_LANE_POWERDOWN_ACK |
2074                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2075                         DRM_ERROR("Port %c enabled but PHY powered down? "
2076                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2077         }
2078
2079         intel_display_power_put(dev_priv, encoder->power_domain);
2080
2081         return ret;
2082 }
2083
2084 static inline enum intel_display_power_domain
2085 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2086 {
2087         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2088          * DC states enabled at the same time, while for driver initiated AUX
2089          * transfers we need the same AUX IOs to be powered but with DC states
2090          * disabled. Accordingly use the AUX power domain here which leaves DC
2091          * states enabled.
2092          * However, for non-A AUX ports the corresponding non-EDP transcoders
2093          * would have already enabled power well 2 and DC_OFF. This means we can
2094          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2095          * specific AUX_IO reference without powering up any extra wells.
2096          * Note that PSR is enabled only on Port A even though this function
2097          * returns the correct domain for other ports too.
2098          */
2099         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2100                                               intel_aux_power_domain(dig_port);
2101 }
2102
2103 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2104                                        struct intel_crtc_state *crtc_state)
2105 {
2106         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2107         struct intel_digital_port *dig_port;
2108         u64 domains;
2109
2110         /*
2111          * TODO: Add support for MST encoders. Atm, the following should never
2112          * happen since fake-MST encoders don't set their get_power_domains()
2113          * hook.
2114          */
2115         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2116                 return 0;
2117
2118         dig_port = enc_to_dig_port(&encoder->base);
2119         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2120
2121         /*
2122          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2123          * ports.
2124          */
2125         if (intel_crtc_has_dp_encoder(crtc_state) ||
2126             intel_port_is_tc(dev_priv, encoder->port))
2127                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2128
2129         return domains;
2130 }
2131
2132 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2133 {
2134         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2135         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2136         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2137         enum port port = encoder->port;
2138         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2139
2140         if (cpu_transcoder != TRANSCODER_EDP)
2141                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2142                            TRANS_CLK_SEL_PORT(port));
2143 }
2144
2145 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2146 {
2147         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2148         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2149
2150         if (cpu_transcoder != TRANSCODER_EDP)
2151                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2152                            TRANS_CLK_SEL_DISABLED);
2153 }
2154
2155 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2156                                 enum port port, uint8_t iboost)
2157 {
2158         u32 tmp;
2159
2160         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2161         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2162         if (iboost)
2163                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2164         else
2165                 tmp |= BALANCE_LEG_DISABLE(port);
2166         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2167 }
2168
2169 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2170                                int level, enum intel_output_type type)
2171 {
2172         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2173         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2174         enum port port = encoder->port;
2175         uint8_t iboost;
2176
2177         if (type == INTEL_OUTPUT_HDMI)
2178                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2179         else
2180                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2181
2182         if (iboost == 0) {
2183                 const struct ddi_buf_trans *ddi_translations;
2184                 int n_entries;
2185
2186                 if (type == INTEL_OUTPUT_HDMI)
2187                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2188                 else if (type == INTEL_OUTPUT_EDP)
2189                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2190                 else
2191                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2192
2193                 if (WARN_ON_ONCE(!ddi_translations))
2194                         return;
2195                 if (WARN_ON_ONCE(level >= n_entries))
2196                         level = n_entries - 1;
2197
2198                 iboost = ddi_translations[level].i_boost;
2199         }
2200
2201         /* Make sure that the requested I_boost is valid */
2202         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2203                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2204                 return;
2205         }
2206
2207         _skl_ddi_set_iboost(dev_priv, port, iboost);
2208
2209         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2210                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2211 }
2212
2213 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2214                                     int level, enum intel_output_type type)
2215 {
2216         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2217         const struct bxt_ddi_buf_trans *ddi_translations;
2218         enum port port = encoder->port;
2219         int n_entries;
2220
2221         if (type == INTEL_OUTPUT_HDMI)
2222                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2223         else if (type == INTEL_OUTPUT_EDP)
2224                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2225         else
2226                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2227
2228         if (WARN_ON_ONCE(!ddi_translations))
2229                 return;
2230         if (WARN_ON_ONCE(level >= n_entries))
2231                 level = n_entries - 1;
2232
2233         bxt_ddi_phy_set_signal_level(dev_priv, port,
2234                                      ddi_translations[level].margin,
2235                                      ddi_translations[level].scale,
2236                                      ddi_translations[level].enable,
2237                                      ddi_translations[level].deemphasis);
2238 }
2239
2240 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2241 {
2242         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2243         enum port port = encoder->port;
2244         int n_entries;
2245
2246         if (IS_ICELAKE(dev_priv)) {
2247                 if (intel_port_is_combophy(dev_priv, port))
2248                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2249                                                 &n_entries);
2250                 else
2251                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2252         } else if (IS_CANNONLAKE(dev_priv)) {
2253                 if (encoder->type == INTEL_OUTPUT_EDP)
2254                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2255                 else
2256                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2257         } else if (IS_GEN9_LP(dev_priv)) {
2258                 if (encoder->type == INTEL_OUTPUT_EDP)
2259                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2260                 else
2261                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2262         } else {
2263                 if (encoder->type == INTEL_OUTPUT_EDP)
2264                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2265                 else
2266                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2267         }
2268
2269         if (WARN_ON(n_entries < 1))
2270                 n_entries = 1;
2271         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2272                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2273
2274         return index_to_dp_signal_levels[n_entries - 1] &
2275                 DP_TRAIN_VOLTAGE_SWING_MASK;
2276 }
2277
2278 /*
2279  * We assume that the full set of pre-emphasis values can be
2280  * used on all DDI platforms. Should that change we need to
2281  * rethink this code.
2282  */
2283 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2284 {
2285         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2286         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2287                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2288         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2289                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2290         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2291                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2292         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2293         default:
2294                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2295         }
2296 }
2297
2298 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2299                                    int level, enum intel_output_type type)
2300 {
2301         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2302         const struct cnl_ddi_buf_trans *ddi_translations;
2303         enum port port = encoder->port;
2304         int n_entries, ln;
2305         u32 val;
2306
2307         if (type == INTEL_OUTPUT_HDMI)
2308                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2309         else if (type == INTEL_OUTPUT_EDP)
2310                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2311         else
2312                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2313
2314         if (WARN_ON_ONCE(!ddi_translations))
2315                 return;
2316         if (WARN_ON_ONCE(level >= n_entries))
2317                 level = n_entries - 1;
2318
2319         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2320         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2321         val &= ~SCALING_MODE_SEL_MASK;
2322         val |= SCALING_MODE_SEL(2);
2323         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2324
2325         /* Program PORT_TX_DW2 */
2326         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2327         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2328                  RCOMP_SCALAR_MASK);
2329         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2330         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2331         /* Rcomp scalar is fixed as 0x98 for every table entry */
2332         val |= RCOMP_SCALAR(0x98);
2333         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2334
2335         /* Program PORT_TX_DW4 */
2336         /* We cannot write to GRP. It would overrite individual loadgen */
2337         for (ln = 0; ln < 4; ln++) {
2338                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2339                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2340                          CURSOR_COEFF_MASK);
2341                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2342                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2343                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2344                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2345         }
2346
2347         /* Program PORT_TX_DW5 */
2348         /* All DW5 values are fixed for every table entry */
2349         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2350         val &= ~RTERM_SELECT_MASK;
2351         val |= RTERM_SELECT(6);
2352         val |= TAP3_DISABLE;
2353         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2354
2355         /* Program PORT_TX_DW7 */
2356         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2357         val &= ~N_SCALAR_MASK;
2358         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2359         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2360 }
2361
2362 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2363                                     int level, enum intel_output_type type)
2364 {
2365         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2366         enum port port = encoder->port;
2367         int width, rate, ln;
2368         u32 val;
2369
2370         if (type == INTEL_OUTPUT_HDMI) {
2371                 width = 4;
2372                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2373         } else {
2374                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2375
2376                 width = intel_dp->lane_count;
2377                 rate = intel_dp->link_rate;
2378         }
2379
2380         /*
2381          * 1. If port type is eDP or DP,
2382          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2383          * else clear to 0b.
2384          */
2385         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2386         if (type != INTEL_OUTPUT_HDMI)
2387                 val |= COMMON_KEEPER_EN;
2388         else
2389                 val &= ~COMMON_KEEPER_EN;
2390         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2391
2392         /* 2. Program loadgen select */
2393         /*
2394          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2395          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2396          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2397          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2398          */
2399         for (ln = 0; ln <= 3; ln++) {
2400                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2401                 val &= ~LOADGEN_SELECT;
2402
2403                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2404                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2405                         val |= LOADGEN_SELECT;
2406                 }
2407                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2408         }
2409
2410         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2411         val = I915_READ(CNL_PORT_CL1CM_DW5);
2412         val |= SUS_CLOCK_CONFIG;
2413         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2414
2415         /* 4. Clear training enable to change swing values */
2416         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2417         val &= ~TX_TRAINING_EN;
2418         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2419
2420         /* 5. Program swing and de-emphasis */
2421         cnl_ddi_vswing_program(encoder, level, type);
2422
2423         /* 6. Set training enable to trigger update */
2424         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2425         val |= TX_TRAINING_EN;
2426         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2427 }
2428
2429 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2430                                          u32 level, enum port port, int type)
2431 {
2432         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2433         u32 n_entries, val;
2434         int ln;
2435
2436         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2437                                                    &n_entries);
2438         if (!ddi_translations)
2439                 return;
2440
2441         if (level >= n_entries) {
2442                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2443                 level = n_entries - 1;
2444         }
2445
2446         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2447         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2448         val &= ~RTERM_SELECT_MASK;
2449         val |= RTERM_SELECT(0x6);
2450         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2451
2452         /* Program PORT_TX_DW5 */
2453         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2454         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2455          * Clear DisableTap2 and DisableTap3 for all other Ports
2456          */
2457         if (type == INTEL_OUTPUT_DSI) {
2458                 val |= TAP2_DISABLE;
2459                 val |= TAP3_DISABLE;
2460         } else {
2461                 val &= ~TAP2_DISABLE;
2462                 val &= ~TAP3_DISABLE;
2463         }
2464         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2465
2466         /* Program PORT_TX_DW2 */
2467         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2468         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2469                  RCOMP_SCALAR_MASK);
2470         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2471         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2472         /* Program Rcomp scalar for every table entry */
2473         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2474         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2475
2476         /* Program PORT_TX_DW4 */
2477         /* We cannot write to GRP. It would overwrite individual loadgen. */
2478         for (ln = 0; ln <= 3; ln++) {
2479                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2480                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2481                          CURSOR_COEFF_MASK);
2482                 val |= ddi_translations[level].dw4_scaling;
2483                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2484         }
2485 }
2486
2487 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2488                                               u32 level,
2489                                               enum intel_output_type type)
2490 {
2491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2492         enum port port = encoder->port;
2493         int width = 0;
2494         int rate = 0;
2495         u32 val;
2496         int ln = 0;
2497
2498         if (type == INTEL_OUTPUT_HDMI) {
2499                 width = 4;
2500                 /* Rate is always < than 6GHz for HDMI */
2501         } else {
2502                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2503
2504                 width = intel_dp->lane_count;
2505                 rate = intel_dp->link_rate;
2506         }
2507
2508         /*
2509          * 1. If port type is eDP or DP,
2510          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2511          * else clear to 0b.
2512          */
2513         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2514         if (type == INTEL_OUTPUT_HDMI)
2515                 val &= ~COMMON_KEEPER_EN;
2516         else
2517                 val |= COMMON_KEEPER_EN;
2518         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2519
2520         /* 2. Program loadgen select */
2521         /*
2522          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2523          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2524          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2525          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2526          */
2527         for (ln = 0; ln <= 3; ln++) {
2528                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2529                 val &= ~LOADGEN_SELECT;
2530
2531                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2532                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2533                         val |= LOADGEN_SELECT;
2534                 }
2535                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2536         }
2537
2538         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2539         val = I915_READ(ICL_PORT_CL_DW5(port));
2540         val |= SUS_CLOCK_CONFIG;
2541         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2542
2543         /* 4. Clear training enable to change swing values */
2544         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2545         val &= ~TX_TRAINING_EN;
2546         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2547
2548         /* 5. Program swing and de-emphasis */
2549         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2550
2551         /* 6. Set training enable to trigger update */
2552         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2553         val |= TX_TRAINING_EN;
2554         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2555 }
2556
2557 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2558                                            int link_clock,
2559                                            u32 level)
2560 {
2561         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2562         enum port port = encoder->port;
2563         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2564         u32 n_entries, val;
2565         int ln;
2566
2567         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2568         ddi_translations = icl_mg_phy_ddi_translations;
2569         /* The table does not have values for level 3 and level 9. */
2570         if (level >= n_entries || level == 3 || level == 9) {
2571                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2572                               level, n_entries - 2);
2573                 level = n_entries - 2;
2574         }
2575
2576         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2577         for (ln = 0; ln < 2; ln++) {
2578                 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2579                 val &= ~CRI_USE_FS32;
2580                 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2581
2582                 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2583                 val &= ~CRI_USE_FS32;
2584                 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2585         }
2586
2587         /* Program MG_TX_SWINGCTRL with values from vswing table */
2588         for (ln = 0; ln < 2; ln++) {
2589                 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2590                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2591                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2592                         ddi_translations[level].cri_txdeemph_override_17_12);
2593                 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2594
2595                 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2596                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2597                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2598                         ddi_translations[level].cri_txdeemph_override_17_12);
2599                 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2600         }
2601
2602         /* Program MG_TX_DRVCTRL with values from vswing table */
2603         for (ln = 0; ln < 2; ln++) {
2604                 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2605                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2606                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2607                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2608                         ddi_translations[level].cri_txdeemph_override_5_0) |
2609                         CRI_TXDEEMPH_OVERRIDE_11_6(
2610                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2611                         CRI_TXDEEMPH_OVERRIDE_EN;
2612                 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2613
2614                 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2615                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2616                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2617                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2618                         ddi_translations[level].cri_txdeemph_override_5_0) |
2619                         CRI_TXDEEMPH_OVERRIDE_11_6(
2620                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2621                         CRI_TXDEEMPH_OVERRIDE_EN;
2622                 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2623
2624                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2625         }
2626
2627         /*
2628          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2629          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2630          * values from table for which TX1 and TX2 enabled.
2631          */
2632         for (ln = 0; ln < 2; ln++) {
2633                 val = I915_READ(MG_CLKHUB(port, ln));
2634                 if (link_clock < 300000)
2635                         val |= CFG_LOW_RATE_LKREN_EN;
2636                 else
2637                         val &= ~CFG_LOW_RATE_LKREN_EN;
2638                 I915_WRITE(MG_CLKHUB(port, ln), val);
2639         }
2640
2641         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2642         for (ln = 0; ln < 2; ln++) {
2643                 val = I915_READ(MG_TX1_DCC(port, ln));
2644                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2645                 if (link_clock <= 500000) {
2646                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2647                 } else {
2648                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2649                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2650                 }
2651                 I915_WRITE(MG_TX1_DCC(port, ln), val);
2652
2653                 val = I915_READ(MG_TX2_DCC(port, ln));
2654                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2655                 if (link_clock <= 500000) {
2656                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2657                 } else {
2658                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2659                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2660                 }
2661                 I915_WRITE(MG_TX2_DCC(port, ln), val);
2662         }
2663
2664         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2665         for (ln = 0; ln < 2; ln++) {
2666                 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2667                 val |= CRI_CALCINIT;
2668                 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2669
2670                 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2671                 val |= CRI_CALCINIT;
2672                 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2673         }
2674 }
2675
2676 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2677                                     int link_clock,
2678                                     u32 level,
2679                                     enum intel_output_type type)
2680 {
2681         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2682         enum port port = encoder->port;
2683
2684         if (intel_port_is_combophy(dev_priv, port))
2685                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2686         else
2687                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2688 }
2689
2690 static uint32_t translate_signal_level(int signal_levels)
2691 {
2692         int i;
2693
2694         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2695                 if (index_to_dp_signal_levels[i] == signal_levels)
2696                         return i;
2697         }
2698
2699         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2700              signal_levels);
2701
2702         return 0;
2703 }
2704
2705 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2706 {
2707         uint8_t train_set = intel_dp->train_set[0];
2708         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2709                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2710
2711         return translate_signal_level(signal_levels);
2712 }
2713
2714 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2715 {
2716         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2717         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2718         struct intel_encoder *encoder = &dport->base;
2719         int level = intel_ddi_dp_level(intel_dp);
2720
2721         if (IS_ICELAKE(dev_priv))
2722                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2723                                         level, encoder->type);
2724         else if (IS_CANNONLAKE(dev_priv))
2725                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2726         else
2727                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2728
2729         return 0;
2730 }
2731
2732 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2733 {
2734         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2735         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2736         struct intel_encoder *encoder = &dport->base;
2737         int level = intel_ddi_dp_level(intel_dp);
2738
2739         if (IS_GEN9_BC(dev_priv))
2740                 skl_ddi_set_iboost(encoder, level, encoder->type);
2741
2742         return DDI_BUF_TRANS_SELECT(level);
2743 }
2744
2745 static inline
2746 uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2747                                    enum port port)
2748 {
2749         if (intel_port_is_combophy(dev_priv, port)) {
2750                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2751         } else if (intel_port_is_tc(dev_priv, port)) {
2752                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2753
2754                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2755         }
2756
2757         return 0;
2758 }
2759
2760 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2761                            struct intel_crtc_state *crtc_state,
2762                            struct drm_atomic_state *old_state)
2763 {
2764         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2765         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2766         struct drm_connector_state *conn_state;
2767         struct drm_connector *conn;
2768         int i;
2769
2770         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2771                 struct intel_encoder *encoder =
2772                         to_intel_encoder(conn_state->best_encoder);
2773                 enum port port;
2774                 uint32_t val;
2775
2776                 if (conn_state->crtc != crtc)
2777                         continue;
2778
2779                 port = encoder->port;
2780                 mutex_lock(&dev_priv->dpll_lock);
2781
2782                 val = I915_READ(DPCLKA_CFGCR0_ICL);
2783                 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2784
2785                 if (intel_port_is_combophy(dev_priv, port)) {
2786                         val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2787                         val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2788                         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2789                         POSTING_READ(DPCLKA_CFGCR0_ICL);
2790                 }
2791
2792                 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2793                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2794
2795                 mutex_unlock(&dev_priv->dpll_lock);
2796         }
2797 }
2798
2799 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2800                              struct intel_crtc_state *crtc_state,
2801                              struct drm_atomic_state *old_state)
2802 {
2803         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2804         struct drm_connector_state *old_conn_state;
2805         struct drm_connector *conn;
2806         int i;
2807
2808         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2809                 struct intel_encoder *encoder =
2810                         to_intel_encoder(old_conn_state->best_encoder);
2811                 enum port port;
2812
2813                 if (old_conn_state->crtc != crtc)
2814                         continue;
2815
2816                 port = encoder->port;
2817                 mutex_lock(&dev_priv->dpll_lock);
2818                 I915_WRITE(DPCLKA_CFGCR0_ICL,
2819                            I915_READ(DPCLKA_CFGCR0_ICL) |
2820                            icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2821                 mutex_unlock(&dev_priv->dpll_lock);
2822         }
2823 }
2824
2825 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2826 {
2827         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2828         u32 val = I915_READ(DPCLKA_CFGCR0_ICL);
2829         enum port port = encoder->port;
2830         bool clk_enabled = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2831
2832         if (clk_enabled == !!encoder->base.crtc)
2833                 return;
2834
2835         /*
2836          * Punt on the case now where clock is disabled, but the encoder is
2837          * enabled, something else is really broken then.
2838          */
2839         if (WARN_ON(!clk_enabled))
2840                 return;
2841
2842         DRM_NOTE("Port %c is disabled but it has a mapped PLL, unmap it\n",
2843                  port_name(port));
2844         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2845         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2846 }
2847
2848 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2849                                  const struct intel_crtc_state *crtc_state)
2850 {
2851         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2852         enum port port = encoder->port;
2853         uint32_t val;
2854         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2855
2856         if (WARN_ON(!pll))
2857                 return;
2858
2859         mutex_lock(&dev_priv->dpll_lock);
2860
2861         if (IS_ICELAKE(dev_priv)) {
2862                 if (!intel_port_is_combophy(dev_priv, port))
2863                         I915_WRITE(DDI_CLK_SEL(port),
2864                                    icl_pll_to_ddi_pll_sel(encoder, crtc_state));
2865         } else if (IS_CANNONLAKE(dev_priv)) {
2866                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2867                 val = I915_READ(DPCLKA_CFGCR0);
2868                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2869                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2870                 I915_WRITE(DPCLKA_CFGCR0, val);
2871
2872                 /*
2873                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2874                  * This step and the step before must be done with separate
2875                  * register writes.
2876                  */
2877                 val = I915_READ(DPCLKA_CFGCR0);
2878                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2879                 I915_WRITE(DPCLKA_CFGCR0, val);
2880         } else if (IS_GEN9_BC(dev_priv)) {
2881                 /* DDI -> PLL mapping  */
2882                 val = I915_READ(DPLL_CTRL2);
2883
2884                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2885                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2886                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2887                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2888
2889                 I915_WRITE(DPLL_CTRL2, val);
2890
2891         } else if (INTEL_GEN(dev_priv) < 9) {
2892                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2893         }
2894
2895         mutex_unlock(&dev_priv->dpll_lock);
2896 }
2897
2898 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2899 {
2900         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2901         enum port port = encoder->port;
2902
2903         if (IS_ICELAKE(dev_priv)) {
2904                 if (!intel_port_is_combophy(dev_priv, port))
2905                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2906         } else if (IS_CANNONLAKE(dev_priv)) {
2907                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2908                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2909         } else if (IS_GEN9_BC(dev_priv)) {
2910                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2911                            DPLL_CTRL2_DDI_CLK_OFF(port));
2912         } else if (INTEL_GEN(dev_priv) < 9) {
2913                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2914         }
2915 }
2916
2917 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2918                                     const struct intel_crtc_state *crtc_state,
2919                                     const struct drm_connector_state *conn_state)
2920 {
2921         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2922         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2923         enum port port = encoder->port;
2924         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2925         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2926         int level = intel_ddi_dp_level(intel_dp);
2927
2928         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2929
2930         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2931                                  crtc_state->lane_count, is_mst);
2932
2933         intel_edp_panel_on(intel_dp);
2934
2935         intel_ddi_clk_select(encoder, crtc_state);
2936
2937         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2938
2939         icl_program_mg_dp_mode(intel_dp);
2940         icl_disable_phy_clock_gating(dig_port);
2941
2942         if (IS_ICELAKE(dev_priv))
2943                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2944                                         level, encoder->type);
2945         else if (IS_CANNONLAKE(dev_priv))
2946                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2947         else if (IS_GEN9_LP(dev_priv))
2948                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2949         else
2950                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2951
2952         intel_ddi_init_dp_buf_reg(encoder);
2953         if (!is_mst)
2954                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2955         intel_dp_start_link_train(intel_dp);
2956         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2957                 intel_dp_stop_link_train(intel_dp);
2958
2959         icl_enable_phy_clock_gating(dig_port);
2960
2961         if (!is_mst)
2962                 intel_ddi_enable_pipe_clock(crtc_state);
2963 }
2964
2965 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2966                                       const struct intel_crtc_state *crtc_state,
2967                                       const struct drm_connector_state *conn_state)
2968 {
2969         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2970         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2971         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2972         enum port port = encoder->port;
2973         int level = intel_ddi_hdmi_level(dev_priv, port);
2974         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2975
2976         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2977         intel_ddi_clk_select(encoder, crtc_state);
2978
2979         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2980
2981         if (IS_ICELAKE(dev_priv))
2982                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2983                                         level, INTEL_OUTPUT_HDMI);
2984         else if (IS_CANNONLAKE(dev_priv))
2985                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2986         else if (IS_GEN9_LP(dev_priv))
2987                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2988         else
2989                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2990
2991         if (IS_GEN9_BC(dev_priv))
2992                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2993
2994         intel_ddi_enable_pipe_clock(crtc_state);
2995
2996         intel_dig_port->set_infoframes(encoder,
2997                                        crtc_state->has_infoframe,
2998                                        crtc_state, conn_state);
2999 }
3000
3001 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3002                                  const struct intel_crtc_state *crtc_state,
3003                                  const struct drm_connector_state *conn_state)
3004 {
3005         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3006         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3007         enum pipe pipe = crtc->pipe;
3008
3009         /*
3010          * When called from DP MST code:
3011          * - conn_state will be NULL
3012          * - encoder will be the main encoder (ie. mst->primary)
3013          * - the main connector associated with this port
3014          *   won't be active or linked to a crtc
3015          * - crtc_state will be the state of the first stream to
3016          *   be activated on this port, and it may not be the same
3017          *   stream that will be deactivated last, but each stream
3018          *   should have a state that is identical when it comes to
3019          *   the DP link parameteres
3020          */
3021
3022         WARN_ON(crtc_state->has_pch_encoder);
3023
3024         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3025
3026         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3027                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3028         } else {
3029                 struct intel_lspcon *lspcon =
3030                                 enc_to_intel_lspcon(&encoder->base);
3031
3032                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3033                 if (lspcon->active) {
3034                         struct intel_digital_port *dig_port =
3035                                         enc_to_dig_port(&encoder->base);
3036
3037                         dig_port->set_infoframes(encoder,
3038                                                  crtc_state->has_infoframe,
3039                                                  crtc_state, conn_state);
3040                 }
3041         }
3042 }
3043
3044 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
3045 {
3046         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3047         enum port port = encoder->port;
3048         bool wait = false;
3049         u32 val;
3050
3051         val = I915_READ(DDI_BUF_CTL(port));
3052         if (val & DDI_BUF_CTL_ENABLE) {
3053                 val &= ~DDI_BUF_CTL_ENABLE;
3054                 I915_WRITE(DDI_BUF_CTL(port), val);
3055                 wait = true;
3056         }
3057
3058         val = I915_READ(DP_TP_CTL(port));
3059         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3060         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3061         I915_WRITE(DP_TP_CTL(port), val);
3062
3063         if (wait)
3064                 intel_wait_ddi_buf_idle(dev_priv, port);
3065 }
3066
3067 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3068                                       const struct intel_crtc_state *old_crtc_state,
3069                                       const struct drm_connector_state *old_conn_state)
3070 {
3071         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3072         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3073         struct intel_dp *intel_dp = &dig_port->dp;
3074         bool is_mst = intel_crtc_has_type(old_crtc_state,
3075                                           INTEL_OUTPUT_DP_MST);
3076
3077         if (!is_mst) {
3078                 intel_ddi_disable_pipe_clock(old_crtc_state);
3079                 /*
3080                  * Power down sink before disabling the port, otherwise we end
3081                  * up getting interrupts from the sink on detecting link loss.
3082                  */
3083                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3084         }
3085
3086         intel_disable_ddi_buf(encoder);
3087
3088         intel_edp_panel_vdd_on(intel_dp);
3089         intel_edp_panel_off(intel_dp);
3090
3091         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3092
3093         intel_ddi_clk_disable(encoder);
3094 }
3095
3096 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3097                                         const struct intel_crtc_state *old_crtc_state,
3098                                         const struct drm_connector_state *old_conn_state)
3099 {
3100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3101         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3102         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3103
3104         dig_port->set_infoframes(encoder, false,
3105                                  old_crtc_state, old_conn_state);
3106
3107         intel_ddi_disable_pipe_clock(old_crtc_state);
3108
3109         intel_disable_ddi_buf(encoder);
3110
3111         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3112
3113         intel_ddi_clk_disable(encoder);
3114
3115         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3116 }
3117
3118 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3119                                    const struct intel_crtc_state *old_crtc_state,
3120                                    const struct drm_connector_state *old_conn_state)
3121 {
3122         /*
3123          * When called from DP MST code:
3124          * - old_conn_state will be NULL
3125          * - encoder will be the main encoder (ie. mst->primary)
3126          * - the main connector associated with this port
3127          *   won't be active or linked to a crtc
3128          * - old_crtc_state will be the state of the last stream to
3129          *   be deactivated on this port, and it may not be the same
3130          *   stream that was activated last, but each stream
3131          *   should have a state that is identical when it comes to
3132          *   the DP link parameteres
3133          */
3134
3135         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3136                 intel_ddi_post_disable_hdmi(encoder,
3137                                             old_crtc_state, old_conn_state);
3138         else
3139                 intel_ddi_post_disable_dp(encoder,
3140                                           old_crtc_state, old_conn_state);
3141 }
3142
3143 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3144                                 const struct intel_crtc_state *old_crtc_state,
3145                                 const struct drm_connector_state *old_conn_state)
3146 {
3147         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3148         uint32_t val;
3149
3150         /*
3151          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3152          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3153          * step 13 is the correct place for it. Step 18 is where it was
3154          * originally before the BUN.
3155          */
3156         val = I915_READ(FDI_RX_CTL(PIPE_A));
3157         val &= ~FDI_RX_ENABLE;
3158         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3159
3160         intel_disable_ddi_buf(encoder);
3161         intel_ddi_clk_disable(encoder);
3162
3163         val = I915_READ(FDI_RX_MISC(PIPE_A));
3164         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3165         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3166         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3167
3168         val = I915_READ(FDI_RX_CTL(PIPE_A));
3169         val &= ~FDI_PCDCLK;
3170         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3171
3172         val = I915_READ(FDI_RX_CTL(PIPE_A));
3173         val &= ~FDI_RX_PLL_ENABLE;
3174         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3175 }
3176
3177 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3178                                 const struct intel_crtc_state *crtc_state,
3179                                 const struct drm_connector_state *conn_state)
3180 {
3181         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3182         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3183         enum port port = encoder->port;
3184
3185         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3186                 intel_dp_stop_link_train(intel_dp);
3187
3188         intel_edp_backlight_on(crtc_state, conn_state);
3189         intel_psr_enable(intel_dp, crtc_state);
3190         intel_edp_drrs_enable(intel_dp, crtc_state);
3191
3192         if (crtc_state->has_audio)
3193                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3194 }
3195
3196 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3197                                   const struct intel_crtc_state *crtc_state,
3198                                   const struct drm_connector_state *conn_state)
3199 {
3200         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3201         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3202         struct drm_connector *connector = conn_state->connector;
3203         enum port port = encoder->port;
3204
3205         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3206                                                crtc_state->hdmi_high_tmds_clock_ratio,
3207                                                crtc_state->hdmi_scrambling))
3208                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3209                           connector->base.id, connector->name);
3210
3211         /* Display WA #1143: skl,kbl,cfl */
3212         if (IS_GEN9_BC(dev_priv)) {
3213                 /*
3214                  * For some reason these chicken bits have been
3215                  * stuffed into a transcoder register, event though
3216                  * the bits affect a specific DDI port rather than
3217                  * a specific transcoder.
3218                  */
3219                 static const enum transcoder port_to_transcoder[] = {
3220                         [PORT_A] = TRANSCODER_EDP,
3221                         [PORT_B] = TRANSCODER_A,
3222                         [PORT_C] = TRANSCODER_B,
3223                         [PORT_D] = TRANSCODER_C,
3224                         [PORT_E] = TRANSCODER_A,
3225                 };
3226                 enum transcoder transcoder = port_to_transcoder[port];
3227                 u32 val;
3228
3229                 val = I915_READ(CHICKEN_TRANS(transcoder));
3230
3231                 if (port == PORT_E)
3232                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3233                                 DDIE_TRAINING_OVERRIDE_VALUE;
3234                 else
3235                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3236                                 DDI_TRAINING_OVERRIDE_VALUE;
3237
3238                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3239                 POSTING_READ(CHICKEN_TRANS(transcoder));
3240
3241                 udelay(1);
3242
3243                 if (port == PORT_E)
3244                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3245                                  DDIE_TRAINING_OVERRIDE_VALUE);
3246                 else
3247                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3248                                  DDI_TRAINING_OVERRIDE_VALUE);
3249
3250                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3251         }
3252
3253         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3254          * are ignored so nothing special needs to be done besides
3255          * enabling the port.
3256          */
3257         I915_WRITE(DDI_BUF_CTL(port),
3258                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3259
3260         if (crtc_state->has_audio)
3261                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3262 }
3263
3264 static void intel_enable_ddi(struct intel_encoder *encoder,
3265                              const struct intel_crtc_state *crtc_state,
3266                              const struct drm_connector_state *conn_state)
3267 {
3268         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3269                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3270         else
3271                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3272
3273         /* Enable hdcp if it's desired */
3274         if (conn_state->content_protection ==
3275             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3276                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3277 }
3278
3279 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3280                                  const struct intel_crtc_state *old_crtc_state,
3281                                  const struct drm_connector_state *old_conn_state)
3282 {
3283         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3284
3285         intel_dp->link_trained = false;
3286
3287         if (old_crtc_state->has_audio)
3288                 intel_audio_codec_disable(encoder,
3289                                           old_crtc_state, old_conn_state);
3290
3291         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3292         intel_psr_disable(intel_dp, old_crtc_state);
3293         intel_edp_backlight_off(old_conn_state);
3294 }
3295
3296 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3297                                    const struct intel_crtc_state *old_crtc_state,
3298                                    const struct drm_connector_state *old_conn_state)
3299 {
3300         struct drm_connector *connector = old_conn_state->connector;
3301
3302         if (old_crtc_state->has_audio)
3303                 intel_audio_codec_disable(encoder,
3304                                           old_crtc_state, old_conn_state);
3305
3306         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3307                                                false, false))
3308                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3309                               connector->base.id, connector->name);
3310 }
3311
3312 static void intel_disable_ddi(struct intel_encoder *encoder,
3313                               const struct intel_crtc_state *old_crtc_state,
3314                               const struct drm_connector_state *old_conn_state)
3315 {
3316         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3317
3318         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3319                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3320         else
3321                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3322 }
3323
3324 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3325                                          const struct intel_crtc_state *pipe_config,
3326                                          enum port port)
3327 {
3328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3329         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3330         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3331         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3332         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3333
3334         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3335         switch (pipe_config->lane_count) {
3336         case 1:
3337                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3338                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3339                 break;
3340         case 2:
3341                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3342                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3343                 break;
3344         case 4:
3345                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3346                 break;
3347         default:
3348                 MISSING_CASE(pipe_config->lane_count);
3349         }
3350         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3351 }
3352
3353 static void
3354 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3355                          const struct intel_crtc_state *crtc_state,
3356                          const struct drm_connector_state *conn_state)
3357 {
3358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3359         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3360         enum port port = encoder->port;
3361
3362         if (intel_crtc_has_dp_encoder(crtc_state) ||
3363             intel_port_is_tc(dev_priv, encoder->port))
3364                 intel_display_power_get(dev_priv,
3365                                         intel_ddi_main_link_aux_domain(dig_port));
3366
3367         if (IS_GEN9_LP(dev_priv))
3368                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3369                                                 crtc_state->lane_lat_optim_mask);
3370
3371         /*
3372          * Program the lane count for static/dynamic connections on Type-C ports.
3373          * Skip this step for TBT.
3374          */
3375         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3376             dig_port->tc_type == TC_PORT_TBT)
3377                 return;
3378
3379         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3380 }
3381
3382 static void
3383 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3384                            const struct intel_crtc_state *crtc_state,
3385                            const struct drm_connector_state *conn_state)
3386 {
3387         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3388         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3389
3390         if (intel_crtc_has_dp_encoder(crtc_state) ||
3391             intel_port_is_tc(dev_priv, encoder->port))
3392                 intel_display_power_put(dev_priv,
3393                                         intel_ddi_main_link_aux_domain(dig_port));
3394 }
3395
3396 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3397 {
3398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3399         struct drm_i915_private *dev_priv =
3400                 to_i915(intel_dig_port->base.base.dev);
3401         enum port port = intel_dig_port->base.port;
3402         uint32_t val;
3403         bool wait = false;
3404
3405         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3406                 val = I915_READ(DDI_BUF_CTL(port));
3407                 if (val & DDI_BUF_CTL_ENABLE) {
3408                         val &= ~DDI_BUF_CTL_ENABLE;
3409                         I915_WRITE(DDI_BUF_CTL(port), val);
3410                         wait = true;
3411                 }
3412
3413                 val = I915_READ(DP_TP_CTL(port));
3414                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3415                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3416                 I915_WRITE(DP_TP_CTL(port), val);
3417                 POSTING_READ(DP_TP_CTL(port));
3418
3419                 if (wait)
3420                         intel_wait_ddi_buf_idle(dev_priv, port);
3421         }
3422
3423         val = DP_TP_CTL_ENABLE |
3424               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3425         if (intel_dp->link_mst)
3426                 val |= DP_TP_CTL_MODE_MST;
3427         else {
3428                 val |= DP_TP_CTL_MODE_SST;
3429                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3430                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3431         }
3432         I915_WRITE(DP_TP_CTL(port), val);
3433         POSTING_READ(DP_TP_CTL(port));
3434
3435         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3436         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3437         POSTING_READ(DDI_BUF_CTL(port));
3438
3439         udelay(600);
3440 }
3441
3442 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3443                                        enum transcoder cpu_transcoder)
3444 {
3445         if (cpu_transcoder == TRANSCODER_EDP)
3446                 return false;
3447
3448         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3449                 return false;
3450
3451         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3452                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3453 }
3454
3455 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3456                                          struct intel_crtc_state *crtc_state)
3457 {
3458         if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3459                 crtc_state->min_voltage_level = 1;
3460         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3461                 crtc_state->min_voltage_level = 2;
3462 }
3463
3464 void intel_ddi_get_config(struct intel_encoder *encoder,
3465                           struct intel_crtc_state *pipe_config)
3466 {
3467         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3468         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3469         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3470         struct intel_digital_port *intel_dig_port;
3471         u32 temp, flags = 0;
3472
3473         /* XXX: DSI transcoder paranoia */
3474         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3475                 return;
3476
3477         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3478         if (temp & TRANS_DDI_PHSYNC)
3479                 flags |= DRM_MODE_FLAG_PHSYNC;
3480         else
3481                 flags |= DRM_MODE_FLAG_NHSYNC;
3482         if (temp & TRANS_DDI_PVSYNC)
3483                 flags |= DRM_MODE_FLAG_PVSYNC;
3484         else
3485                 flags |= DRM_MODE_FLAG_NVSYNC;
3486
3487         pipe_config->base.adjusted_mode.flags |= flags;
3488
3489         switch (temp & TRANS_DDI_BPC_MASK) {
3490         case TRANS_DDI_BPC_6:
3491                 pipe_config->pipe_bpp = 18;
3492                 break;
3493         case TRANS_DDI_BPC_8:
3494                 pipe_config->pipe_bpp = 24;
3495                 break;
3496         case TRANS_DDI_BPC_10:
3497                 pipe_config->pipe_bpp = 30;
3498                 break;
3499         case TRANS_DDI_BPC_12:
3500                 pipe_config->pipe_bpp = 36;
3501                 break;
3502         default:
3503                 break;
3504         }
3505
3506         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3507         case TRANS_DDI_MODE_SELECT_HDMI:
3508                 pipe_config->has_hdmi_sink = true;
3509                 intel_dig_port = enc_to_dig_port(&encoder->base);
3510
3511                 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
3512                         pipe_config->has_infoframe = true;
3513
3514                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3515                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3516                         pipe_config->hdmi_scrambling = true;
3517                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3518                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3519                 /* fall through */
3520         case TRANS_DDI_MODE_SELECT_DVI:
3521                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3522                 pipe_config->lane_count = 4;
3523                 break;
3524         case TRANS_DDI_MODE_SELECT_FDI:
3525                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3526                 break;
3527         case TRANS_DDI_MODE_SELECT_DP_SST:
3528                 if (encoder->type == INTEL_OUTPUT_EDP)
3529                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3530                 else
3531                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3532                 pipe_config->lane_count =
3533                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3534                 intel_dp_get_m_n(intel_crtc, pipe_config);
3535                 break;
3536         case TRANS_DDI_MODE_SELECT_DP_MST:
3537                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3538                 pipe_config->lane_count =
3539                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3540                 intel_dp_get_m_n(intel_crtc, pipe_config);
3541                 break;
3542         default:
3543                 break;
3544         }
3545
3546         pipe_config->has_audio =
3547                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3548
3549         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3550             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3551                 /*
3552                  * This is a big fat ugly hack.
3553                  *
3554                  * Some machines in UEFI boot mode provide us a VBT that has 18
3555                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3556                  * unknown we fail to light up. Yet the same BIOS boots up with
3557                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3558                  * max, not what it tells us to use.
3559                  *
3560                  * Note: This will still be broken if the eDP panel is not lit
3561                  * up by the BIOS, and thus we can't get the mode at module
3562                  * load.
3563                  */
3564                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3565                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3566                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3567         }
3568
3569         intel_ddi_clock_get(encoder, pipe_config);
3570
3571         if (IS_GEN9_LP(dev_priv))
3572                 pipe_config->lane_lat_optim_mask =
3573                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3574
3575         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3576 }
3577
3578 static enum intel_output_type
3579 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3580                               struct intel_crtc_state *crtc_state,
3581                               struct drm_connector_state *conn_state)
3582 {
3583         switch (conn_state->connector->connector_type) {
3584         case DRM_MODE_CONNECTOR_HDMIA:
3585                 return INTEL_OUTPUT_HDMI;
3586         case DRM_MODE_CONNECTOR_eDP:
3587                 return INTEL_OUTPUT_EDP;
3588         case DRM_MODE_CONNECTOR_DisplayPort:
3589                 return INTEL_OUTPUT_DP;
3590         default:
3591                 MISSING_CASE(conn_state->connector->connector_type);
3592                 return INTEL_OUTPUT_UNUSED;
3593         }
3594 }
3595
3596 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3597                                      struct intel_crtc_state *pipe_config,
3598                                      struct drm_connector_state *conn_state)
3599 {
3600         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3601         enum port port = encoder->port;
3602         int ret;
3603
3604         if (port == PORT_A)
3605                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3606
3607         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3608                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3609         else
3610                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3611
3612         if (IS_GEN9_LP(dev_priv) && ret)
3613                 pipe_config->lane_lat_optim_mask =
3614                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3615
3616         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3617
3618         return ret;
3619
3620 }
3621
3622 static const struct drm_encoder_funcs intel_ddi_funcs = {
3623         .reset = intel_dp_encoder_reset,
3624         .destroy = intel_dp_encoder_destroy,
3625 };
3626
3627 static struct intel_connector *
3628 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3629 {
3630         struct intel_connector *connector;
3631         enum port port = intel_dig_port->base.port;
3632
3633         connector = intel_connector_alloc();
3634         if (!connector)
3635                 return NULL;
3636
3637         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3638         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3639                 kfree(connector);
3640                 return NULL;
3641         }
3642
3643         return connector;
3644 }
3645
3646 static int modeset_pipe(struct drm_crtc *crtc,
3647                         struct drm_modeset_acquire_ctx *ctx)
3648 {
3649         struct drm_atomic_state *state;
3650         struct drm_crtc_state *crtc_state;
3651         int ret;
3652
3653         state = drm_atomic_state_alloc(crtc->dev);
3654         if (!state)
3655                 return -ENOMEM;
3656
3657         state->acquire_ctx = ctx;
3658
3659         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3660         if (IS_ERR(crtc_state)) {
3661                 ret = PTR_ERR(crtc_state);
3662                 goto out;
3663         }
3664
3665         crtc_state->mode_changed = true;
3666
3667         ret = drm_atomic_add_affected_connectors(state, crtc);
3668         if (ret)
3669                 goto out;
3670
3671         ret = drm_atomic_add_affected_planes(state, crtc);
3672         if (ret)
3673                 goto out;
3674
3675         ret = drm_atomic_commit(state);
3676         if (ret)
3677                 goto out;
3678
3679         return 0;
3680
3681  out:
3682         drm_atomic_state_put(state);
3683
3684         return ret;
3685 }
3686
3687 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3688                                  struct drm_modeset_acquire_ctx *ctx)
3689 {
3690         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3691         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3692         struct intel_connector *connector = hdmi->attached_connector;
3693         struct i2c_adapter *adapter =
3694                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3695         struct drm_connector_state *conn_state;
3696         struct intel_crtc_state *crtc_state;
3697         struct intel_crtc *crtc;
3698         u8 config;
3699         int ret;
3700
3701         if (!connector || connector->base.status != connector_status_connected)
3702                 return 0;
3703
3704         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3705                                ctx);
3706         if (ret)
3707                 return ret;
3708
3709         conn_state = connector->base.state;
3710
3711         crtc = to_intel_crtc(conn_state->crtc);
3712         if (!crtc)
3713                 return 0;
3714
3715         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3716         if (ret)
3717                 return ret;
3718
3719         crtc_state = to_intel_crtc_state(crtc->base.state);
3720
3721         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3722
3723         if (!crtc_state->base.active)
3724                 return 0;
3725
3726         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3727             !crtc_state->hdmi_scrambling)
3728                 return 0;
3729
3730         if (conn_state->commit &&
3731             !try_wait_for_completion(&conn_state->commit->hw_done))
3732                 return 0;
3733
3734         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3735         if (ret < 0) {
3736                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3737                 return 0;
3738         }
3739
3740         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3741             crtc_state->hdmi_high_tmds_clock_ratio &&
3742             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3743             crtc_state->hdmi_scrambling)
3744                 return 0;
3745
3746         /*
3747          * HDMI 2.0 says that one should not send scrambled data
3748          * prior to configuring the sink scrambling, and that
3749          * TMDS clock/data transmission should be suspended when
3750          * changing the TMDS clock rate in the sink. So let's
3751          * just do a full modeset here, even though some sinks
3752          * would be perfectly happy if were to just reconfigure
3753          * the SCDC settings on the fly.
3754          */
3755         return modeset_pipe(&crtc->base, ctx);
3756 }
3757
3758 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3759                               struct intel_connector *connector)
3760 {
3761         struct drm_modeset_acquire_ctx ctx;
3762         bool changed;
3763         int ret;
3764
3765         changed = intel_encoder_hotplug(encoder, connector);
3766
3767         drm_modeset_acquire_init(&ctx, 0);
3768
3769         for (;;) {
3770                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3771                         ret = intel_hdmi_reset_link(encoder, &ctx);
3772                 else
3773                         ret = intel_dp_retrain_link(encoder, &ctx);
3774
3775                 if (ret == -EDEADLK) {
3776                         drm_modeset_backoff(&ctx);
3777                         continue;
3778                 }
3779
3780                 break;
3781         }
3782
3783         drm_modeset_drop_locks(&ctx);
3784         drm_modeset_acquire_fini(&ctx);
3785         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3786
3787         return changed;
3788 }
3789
3790 static struct intel_connector *
3791 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3792 {
3793         struct intel_connector *connector;
3794         enum port port = intel_dig_port->base.port;
3795
3796         connector = intel_connector_alloc();
3797         if (!connector)
3798                 return NULL;
3799
3800         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3801         intel_hdmi_init_connector(intel_dig_port, connector);
3802
3803         return connector;
3804 }
3805
3806 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3807 {
3808         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3809
3810         if (dport->base.port != PORT_A)
3811                 return false;
3812
3813         if (dport->saved_port_bits & DDI_A_4_LANES)
3814                 return false;
3815
3816         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3817          *                     supported configuration
3818          */
3819         if (IS_GEN9_LP(dev_priv))
3820                 return true;
3821
3822         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3823          *             one who does also have a full A/E split called
3824          *             DDI_F what makes DDI_E useless. However for this
3825          *             case let's trust VBT info.
3826          */
3827         if (IS_CANNONLAKE(dev_priv) &&
3828             !intel_bios_is_port_present(dev_priv, PORT_E))
3829                 return true;
3830
3831         return false;
3832 }
3833
3834 static int
3835 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3836 {
3837         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3838         enum port port = intel_dport->base.port;
3839         int max_lanes = 4;
3840
3841         if (INTEL_GEN(dev_priv) >= 11)
3842                 return max_lanes;
3843
3844         if (port == PORT_A || port == PORT_E) {
3845                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3846                         max_lanes = port == PORT_A ? 4 : 0;
3847                 else
3848                         /* Both A and E share 2 lanes */
3849                         max_lanes = 2;
3850         }
3851
3852         /*
3853          * Some BIOS might fail to set this bit on port A if eDP
3854          * wasn't lit up at boot.  Force this bit set when needed
3855          * so we use the proper lane count for our calculations.
3856          */
3857         if (intel_ddi_a_force_4_lanes(intel_dport)) {
3858                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3859                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3860                 max_lanes = 4;
3861         }
3862
3863         return max_lanes;
3864 }
3865
3866 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3867 {
3868         struct intel_digital_port *intel_dig_port;
3869         struct intel_encoder *intel_encoder;
3870         struct drm_encoder *encoder;
3871         bool init_hdmi, init_dp, init_lspcon = false;
3872         enum pipe pipe;
3873
3874
3875         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3876                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3877         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3878
3879         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3880                 /*
3881                  * Lspcon device needs to be driven with DP connector
3882                  * with special detection sequence. So make sure DP
3883                  * is initialized before lspcon.
3884                  */
3885                 init_dp = true;
3886                 init_lspcon = true;
3887                 init_hdmi = false;
3888                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3889         }
3890
3891         if (!init_dp && !init_hdmi) {
3892                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3893                               port_name(port));
3894                 return;
3895         }
3896
3897         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3898         if (!intel_dig_port)
3899                 return;
3900
3901         intel_encoder = &intel_dig_port->base;
3902         encoder = &intel_encoder->base;
3903
3904         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3905                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3906
3907         intel_encoder->hotplug = intel_ddi_hotplug;
3908         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3909         intel_encoder->compute_config = intel_ddi_compute_config;
3910         intel_encoder->enable = intel_enable_ddi;
3911         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
3912         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
3913         intel_encoder->pre_enable = intel_ddi_pre_enable;
3914         intel_encoder->disable = intel_disable_ddi;
3915         intel_encoder->post_disable = intel_ddi_post_disable;
3916         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3917         intel_encoder->get_config = intel_ddi_get_config;
3918         intel_encoder->suspend = intel_dp_encoder_suspend;
3919         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3920         intel_encoder->type = INTEL_OUTPUT_DDI;
3921         intel_encoder->power_domain = intel_port_to_power_domain(port);
3922         intel_encoder->port = port;
3923         intel_encoder->cloneable = 0;
3924         for_each_pipe(dev_priv, pipe)
3925                 intel_encoder->crtc_mask |= BIT(pipe);
3926
3927         if (INTEL_GEN(dev_priv) >= 11)
3928                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3929                         DDI_BUF_PORT_REVERSAL;
3930         else
3931                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3932                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3933         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3934         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3935         intel_dig_port->aux_ch = intel_aux_ch(dev_priv, port);
3936
3937         switch (port) {
3938         case PORT_A:
3939                 intel_dig_port->ddi_io_power_domain =
3940                         POWER_DOMAIN_PORT_DDI_A_IO;
3941                 break;
3942         case PORT_B:
3943                 intel_dig_port->ddi_io_power_domain =
3944                         POWER_DOMAIN_PORT_DDI_B_IO;
3945                 break;
3946         case PORT_C:
3947                 intel_dig_port->ddi_io_power_domain =
3948                         POWER_DOMAIN_PORT_DDI_C_IO;
3949                 break;
3950         case PORT_D:
3951                 intel_dig_port->ddi_io_power_domain =
3952                         POWER_DOMAIN_PORT_DDI_D_IO;
3953                 break;
3954         case PORT_E:
3955                 intel_dig_port->ddi_io_power_domain =
3956                         POWER_DOMAIN_PORT_DDI_E_IO;
3957                 break;
3958         case PORT_F:
3959                 intel_dig_port->ddi_io_power_domain =
3960                         POWER_DOMAIN_PORT_DDI_F_IO;
3961                 break;
3962         default:
3963                 MISSING_CASE(port);
3964         }
3965
3966         if (init_dp) {
3967                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3968                         goto err;
3969
3970                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3971         }
3972
3973         /* In theory we don't need the encoder->type check, but leave it just in
3974          * case we have some really bad VBTs... */
3975         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3976                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3977                         goto err;
3978         }
3979
3980         if (init_lspcon) {
3981                 if (lspcon_init(intel_dig_port))
3982                         /* TODO: handle hdmi info frame part */
3983                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3984                                 port_name(port));
3985                 else
3986                         /*
3987                          * LSPCON init faied, but DP init was success, so
3988                          * lets try to drive as DP++ port.
3989                          */
3990                         DRM_ERROR("LSPCON init failed on port %c\n",
3991                                 port_name(port));
3992         }
3993
3994         intel_infoframe_init(intel_dig_port);
3995         return;
3996
3997 err:
3998         drm_encoder_cleanup(encoder);
3999         kfree(intel_dig_port);
4000 }