drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
  38 MODULE_FIRMWARE(I915_CSR_GLK);
  39 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  40
  41 #define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
  42 MODULE_FIRMWARE(I915_CSR_CNL);
  43 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  44
  45 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
  46 MODULE_FIRMWARE(I915_CSR_KBL);
  47 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  48
  49 #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin"
  50 MODULE_FIRMWARE(I915_CSR_SKL);
  51 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  52
  53 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
  54 MODULE_FIRMWARE(I915_CSR_BXT);
  55 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  56
  57
  58 #define BXT_CSR_MAX_FW_SIZE             0x3000
  59 #define GLK_CSR_MAX_FW_SIZE             0x4000
  60 #define ICL_CSR_MAX_FW_SIZE             0x6000
  61 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  62
  63 struct intel_css_header {
  64         /* 0x09 for DMC */
  65         uint32_t module_type;
  66
  67         /* Includes the DMC specific header in dwords */
  68         uint32_t header_len;
  69
  70         /* always value would be 0x10000 */
  71         uint32_t header_ver;
  72
  73         /* Not used */
  74         uint32_t module_id;
  75
  76         /* Not used */
  77         uint32_t module_vendor;
  78
  79         /* in YYYYMMDD format */
  80         uint32_t date;
  81
  82         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  83         uint32_t size;
  84
  85         /* Not used */
  86         uint32_t key_size;
  87
  88         /* Not used */
  89         uint32_t modulus_size;
  90
  91         /* Not used */
  92         uint32_t exponent_size;
  93
  94         /* Not used */
  95         uint32_t reserved1[12];
  96
  97         /* Major Minor */
  98         uint32_t version;
  99
 100         /* Not used */
 101         uint32_t reserved2[8];
 102
 103         /* Not used */
 104         uint32_t kernel_header_info;
 105 } __packed;
 106
 107 struct intel_fw_info {
 108         uint16_t reserved1;
 109
 110         /* Stepping (A, B, C, ..., *). * is a wildcard */
 111         char stepping;
 112
 113         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 114         char substepping;
 115
 116         uint32_t offset;
 117         uint32_t reserved2;
 118 } __packed;
 119
 120 struct intel_package_header {
 121         /* DMC container header length in dwords */
 122         unsigned char header_len;
 123
 124         /* always value would be 0x01 */
 125         unsigned char header_ver;
 126
 127         unsigned char reserved[10];
 128
 129         /* Number of valid entries in the FWInfo array below */
 130         uint32_t num_entries;
 131
 132         struct intel_fw_info fw_info[20];
 133 } __packed;
 134
 135 struct intel_dmc_header {
 136         /* always value would be 0x40403E3E */
 137         uint32_t signature;
 138
 139         /* DMC binary header length */
 140         unsigned char header_len;
 141
 142         /* 0x01 */
 143         unsigned char header_ver;
 144
 145         /* Reserved */
 146         uint16_t dmcc_ver;
 147
 148         /* Major, Minor */
 149         uint32_t        project;
 150
 151         /* Firmware program size (excluding header) in dwords */
 152         uint32_t        fw_size;
 153
 154         /* Major Minor version */
 155         uint32_t fw_version;
 156
 157         /* Number of valid MMIO cycles present. */
 158         uint32_t mmio_count;
 159
 160         /* MMIO address */
 161         uint32_t mmioaddr[8];
 162
 163         /* MMIO data */
 164         uint32_t mmiodata[8];
 165
 166         /* FW filename  */
 167         unsigned char dfile[32];
 168
 169         uint32_t reserved1[2];
 170 } __packed;
 171
 172 struct stepping_info {
 173         char stepping;
 174         char substepping;
 175 };
 176
 177 static const struct stepping_info skl_stepping_info[] = {
 178         {'A', '0'}, {'B', '0'}, {'C', '0'},
 179         {'D', '0'}, {'E', '0'}, {'F', '0'},
 180         {'G', '0'}, {'H', '0'}, {'I', '0'},
 181         {'J', '0'}, {'K', '0'}
 182 };
 183
 184 static const struct stepping_info bxt_stepping_info[] = {
 185         {'A', '0'}, {'A', '1'}, {'A', '2'},
 186         {'B', '0'}, {'B', '1'}, {'B', '2'}
 187 };
 188
 189 static const struct stepping_info no_stepping_info = { '*', '*' };
 190
 191 static const struct stepping_info *
 192 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 193 {
 194         const struct stepping_info *si;
 195         unsigned int size;
 196
 197         if (IS_SKYLAKE(dev_priv)) {
 198                 size = ARRAY_SIZE(skl_stepping_info);
 199                 si = skl_stepping_info;
 200         } else if (IS_BROXTON(dev_priv)) {
 201                 size = ARRAY_SIZE(bxt_stepping_info);
 202                 si = bxt_stepping_info;
 203         } else {
 204                 size = 0;
 205                 si = NULL;
 206         }
 207
 208         if (INTEL_REVID(dev_priv) < size)
 209                 return si + INTEL_REVID(dev_priv);
 210
 211         return &no_stepping_info;
 212 }
 213
 214 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 215 {
 216         uint32_t val, mask;
 217
 218         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 219
 220         if (IS_GEN9_LP(dev_priv))
 221                 mask |= DC_STATE_DEBUG_MASK_CORES;
 222
 223         /* The below bit doesn't need to be cleared ever afterwards */
 224         val = I915_READ(DC_STATE_DEBUG);
 225         if ((val & mask) != mask) {
 226                 val |= mask;
 227                 I915_WRITE(DC_STATE_DEBUG, val);
 228                 POSTING_READ(DC_STATE_DEBUG);
 229         }
 230 }
 231
 232 /**
 233  * intel_csr_load_program() - write the firmware from memory to register.
 234  * @dev_priv: i915 drm device.
 235  *
 236  * CSR firmware is read from a .bin file and kept in internal memory one time.
 237  * Everytime display comes back from low power state this function is called to
 238  * copy the firmware from internal memory to registers.
 239  */
 240 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 241 {
 242         u32 *payload = dev_priv->csr.dmc_payload;
 243         uint32_t i, fw_size;
 244
 245         if (!HAS_CSR(dev_priv)) {
 246                 DRM_ERROR("No CSR support available for this platform\n");
 247                 return;
 248         }
 249
 250         if (!dev_priv->csr.dmc_payload) {
 251                 DRM_ERROR("Tried to program CSR with empty payload\n");
 252                 return;
 253         }
 254
 255         fw_size = dev_priv->csr.dmc_fw_size;
 256         assert_rpm_wakelock_held(dev_priv);
 257
 258         preempt_disable();
 259
 260         for (i = 0; i < fw_size; i++)
 261                 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
 262
 263         preempt_enable();
 264
 265         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 266                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 267                            dev_priv->csr.mmiodata[i]);
 268         }
 269
 270         dev_priv->csr.dc_state = 0;
 271
 272         gen9_set_dc_state_debugmask(dev_priv);
 273 }
 274
 275 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 276                               const struct firmware *fw)
 277 {
 278         struct intel_css_header *css_header;
 279         struct intel_package_header *package_header;
 280         struct intel_dmc_header *dmc_header;
 281         struct intel_csr *csr = &dev_priv->csr;
 282         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 283         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 284         uint32_t max_fw_size = 0;
 285         uint32_t i;
 286         uint32_t *dmc_payload;
 287         uint32_t required_version;
 288
 289         if (!fw)
 290                 return NULL;
 291
 292         /* Extract CSS Header information*/
 293         css_header = (struct intel_css_header *)fw->data;
 294         if (sizeof(struct intel_css_header) !=
 295             (css_header->header_len * 4)) {
 296                 DRM_ERROR("DMC firmware has wrong CSS header length "
 297                           "(%u bytes)\n",
 298                           (css_header->header_len * 4));
 299                 return NULL;
 300         }
 301
 302         csr->version = css_header->version;
 303
 304         if (csr->fw_path == i915_modparams.dmc_firmware_path) {
 305                 /* Bypass version check for firmware override. */
 306                 required_version = csr->version;
 307         } else if (IS_CANNONLAKE(dev_priv)) {
 308                 required_version = CNL_CSR_VERSION_REQUIRED;
 309         } else if (IS_GEMINILAKE(dev_priv)) {
 310                 required_version = GLK_CSR_VERSION_REQUIRED;
 311         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 312                 required_version = KBL_CSR_VERSION_REQUIRED;
 313         } else if (IS_SKYLAKE(dev_priv)) {
 314                 required_version = SKL_CSR_VERSION_REQUIRED;
 315         } else if (IS_BROXTON(dev_priv)) {
 316                 required_version = BXT_CSR_VERSION_REQUIRED;
 317         } else {
 318                 MISSING_CASE(INTEL_REVID(dev_priv));
 319                 required_version = 0;
 320         }
 321
 322         if (csr->version != required_version) {
 323                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 324                          " please use v%u.%u\n",
 325                          CSR_VERSION_MAJOR(csr->version),
 326                          CSR_VERSION_MINOR(csr->version),
 327                          CSR_VERSION_MAJOR(required_version),
 328                          CSR_VERSION_MINOR(required_version));
 329                 return NULL;
 330         }
 331
 332         readcount += sizeof(struct intel_css_header);
 333
 334         /* Extract Package Header information*/
 335         package_header = (struct intel_package_header *)
 336                 &fw->data[readcount];
 337         if (sizeof(struct intel_package_header) !=
 338             (package_header->header_len * 4)) {
 339                 DRM_ERROR("DMC firmware has wrong package header length "
 340                           "(%u bytes)\n",
 341                           (package_header->header_len * 4));
 342                 return NULL;
 343         }
 344         readcount += sizeof(struct intel_package_header);
 345
 346         /* Search for dmc_offset to find firware binary. */
 347         for (i = 0; i < package_header->num_entries; i++) {
 348                 if (package_header->fw_info[i].substepping == '*' &&
 349                     si->stepping == package_header->fw_info[i].stepping) {
 350                         dmc_offset = package_header->fw_info[i].offset;
 351                         break;
 352                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 353                            si->substepping == package_header->fw_info[i].substepping) {
 354                         dmc_offset = package_header->fw_info[i].offset;
 355                         break;
 356                 } else if (package_header->fw_info[i].stepping == '*' &&
 357                            package_header->fw_info[i].substepping == '*')
 358                         dmc_offset = package_header->fw_info[i].offset;
 359         }
 360         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 361                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 362                           si->stepping);
 363                 return NULL;
 364         }
 365         /* Convert dmc_offset into number of bytes. By default it is in dwords*/
 366         dmc_offset *= 4;
 367         readcount += dmc_offset;
 368
 369         /* Extract dmc_header information. */
 370         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 371         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 372                 DRM_ERROR("DMC firmware has wrong dmc header length "
 373                           "(%u bytes)\n",
 374                           (dmc_header->header_len));
 375                 return NULL;
 376         }
 377         readcount += sizeof(struct intel_dmc_header);
 378
 379         /* Cache the dmc header info. */
 380         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 381                 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
 382                           dmc_header->mmio_count);
 383                 return NULL;
 384         }
 385         csr->mmio_count = dmc_header->mmio_count;
 386         for (i = 0; i < dmc_header->mmio_count; i++) {
 387                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 388                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 389                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 390                                   dmc_header->mmioaddr[i]);
 391                         return NULL;
 392                 }
 393                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 394                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 395         }
 396
 397         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 398         nbytes = dmc_header->fw_size * 4;
 399         if (INTEL_GEN(dev_priv) >= 11)
 400                 max_fw_size = ICL_CSR_MAX_FW_SIZE;
 401         else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 402                 max_fw_size = GLK_CSR_MAX_FW_SIZE;
 403         else if (IS_GEN9(dev_priv))
 404                 max_fw_size = BXT_CSR_MAX_FW_SIZE;
 405         else
 406                 MISSING_CASE(INTEL_REVID(dev_priv));
 407         if (nbytes > max_fw_size) {
 408                 DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
 409                 return NULL;
 410         }
 411         csr->dmc_fw_size = dmc_header->fw_size;
 412
 413         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 414         if (!dmc_payload) {
 415                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 416                 return NULL;
 417         }
 418
 419         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 420 }
 421
 422 static void csr_load_work_fn(struct work_struct *work)
 423 {
 424         struct drm_i915_private *dev_priv;
 425         struct intel_csr *csr;
 426         const struct firmware *fw = NULL;
 427
 428         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 429         csr = &dev_priv->csr;
 430
 431         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 432         if (fw)
 433                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 434
 435         if (dev_priv->csr.dmc_payload) {
 436                 intel_csr_load_program(dev_priv);
 437
 438                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 439
 440                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 441                          dev_priv->csr.fw_path,
 442                          CSR_VERSION_MAJOR(csr->version),
 443                          CSR_VERSION_MINOR(csr->version));
 444         } else {
 445                 dev_notice(dev_priv->drm.dev,
 446                            "Failed to load DMC firmware %s."
 447                            " Disabling runtime power management.\n",
 448                            csr->fw_path);
 449                 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
 450                            INTEL_UC_FIRMWARE_URL);
 451         }
 452
 453         release_firmware(fw);
 454 }
 455
 456 /**
 457  * intel_csr_ucode_init() - initialize the firmware loading.
 458  * @dev_priv: i915 drm device.
 459  *
 460  * This function is called at the time of loading the display driver to read
 461  * firmware from a .bin file and copied into a internal memory.
 462  */
 463 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 464 {
 465         struct intel_csr *csr = &dev_priv->csr;
 466
 467         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 468
 469         if (!HAS_CSR(dev_priv))
 470                 return;
 471
 472         if (i915_modparams.dmc_firmware_path)
 473                 csr->fw_path = i915_modparams.dmc_firmware_path;
 474         else if (IS_CANNONLAKE(dev_priv))
 475                 csr->fw_path = I915_CSR_CNL;
 476         else if (IS_GEMINILAKE(dev_priv))
 477                 csr->fw_path = I915_CSR_GLK;
 478         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 479                 csr->fw_path = I915_CSR_KBL;
 480         else if (IS_SKYLAKE(dev_priv))
 481                 csr->fw_path = I915_CSR_SKL;
 482         else if (IS_BROXTON(dev_priv))
 483                 csr->fw_path = I915_CSR_BXT;
 484
 485         /*
 486          * Obtain a runtime pm reference, until CSR is loaded,
 487          * to avoid entering runtime-suspend.
 488          */
 489         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 490
 491         if (csr->fw_path == NULL) {
 492                 DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
 493                 WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv)));
 494
 495                 return;
 496         }
 497
 498         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 499         schedule_work(&dev_priv->csr.work);
 500 }
 501
 502 /**
 503  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 504  * @dev_priv: i915 drm device
 505  *
 506  * Prepare the DMC firmware before entering system suspend. This includes
 507  * flushing pending work items and releasing any resources acquired during
 508  * init.
 509  */
 510 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 511 {
 512         if (!HAS_CSR(dev_priv))
 513                 return;
 514
 515         flush_work(&dev_priv->csr.work);
 516
 517         /* Drop the reference held in case DMC isn't loaded. */
 518         if (!dev_priv->csr.dmc_payload)
 519                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 520 }
 521
 522 /**
 523  * intel_csr_ucode_resume() - init CSR firmware during system resume
 524  * @dev_priv: i915 drm device
 525  *
 526  * Reinitialize the DMC firmware during system resume, reacquiring any
 527  * resources released in intel_csr_ucode_suspend().
 528  */
 529 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 530 {
 531         if (!HAS_CSR(dev_priv))
 532                 return;
 533
 534         /*
 535          * Reacquire the reference to keep RPM disabled in case DMC isn't
 536          * loaded.
 537          */
 538         if (!dev_priv->csr.dmc_payload)
 539                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 540 }
 541
 542 /**
 543  * intel_csr_ucode_fini() - unload the CSR firmware.
 544  * @dev_priv: i915 drm device.
 545  *
 546  * Firmmware unloading includes freeing the internal memory and reset the
 547  * firmware loading status.
 548  */
 549 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 550 {
 551         if (!HAS_CSR(dev_priv))
 552                 return;
 553
 554         intel_csr_ucode_suspend(dev_priv);
 555
 556         kfree(dev_priv->csr.dmc_payload);
 557 }