drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30
  31 #define GEN_DEFAULT_PIPEOFFSETS \
  32         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  33                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  34         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  35                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  36         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  37
  38 #define GEN_CHV_PIPEOFFSETS \
  39         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  40                           CHV_PIPE_C_OFFSET }, \
  41         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  42                            CHV_TRANSCODER_C_OFFSET, }, \
  43         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  44                              CHV_PALETTE_C_OFFSET }
  45
  46 #define CURSOR_OFFSETS \
  47         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  48
  49 #define IVB_CURSOR_OFFSETS \
  50         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  51
  52 #define BDW_COLORS \
  53         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  54 #define CHV_COLORS \
  55         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  56
  57 /* Keep in gen based order, and chronological order within a gen */
  58 #define GEN2_FEATURES \
  59         .gen = 2, .num_pipes = 1, \
  60         .has_overlay = 1, .overlay_needs_physical = 1, \
  61         .has_gmch_display = 1, \
  62         .hws_needs_physical = 1, \
  63         .unfenced_needs_alignment = 1, \
  64         .ring_mask = RENDER_RING, \
  65         GEN_DEFAULT_PIPEOFFSETS, \
  66         CURSOR_OFFSETS
  67
  68 static const struct intel_device_info intel_i830_info = {
  69         GEN2_FEATURES,
  70         .platform = INTEL_I830,
  71         .is_mobile = 1, .cursor_needs_physical = 1,
  72         .num_pipes = 2, /* legal, last one wins */
  73 };
  74
  75 static const struct intel_device_info intel_i845g_info = {
  76         GEN2_FEATURES,
  77         .platform = INTEL_I845G,
  78 };
  79
  80 static const struct intel_device_info intel_i85x_info = {
  81         GEN2_FEATURES,
  82         .platform = INTEL_I85X, .is_mobile = 1,
  83         .num_pipes = 2, /* legal, last one wins */
  84         .cursor_needs_physical = 1,
  85         .has_fbc = 1,
  86 };
  87
  88 static const struct intel_device_info intel_i865g_info = {
  89         GEN2_FEATURES,
  90         .platform = INTEL_I865G,
  91 };
  92
  93 #define GEN3_FEATURES \
  94         .gen = 3, .num_pipes = 2, \
  95         .has_gmch_display = 1, \
  96         .ring_mask = RENDER_RING, \
  97         GEN_DEFAULT_PIPEOFFSETS, \
  98         CURSOR_OFFSETS
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         GEN3_FEATURES,
 102         .platform = INTEL_I915G, .cursor_needs_physical = 1,
 103         .has_overlay = 1, .overlay_needs_physical = 1,
 104         .hws_needs_physical = 1,
 105         .unfenced_needs_alignment = 1,
 106 };
 107
 108 static const struct intel_device_info intel_i915gm_info = {
 109         GEN3_FEATURES,
 110         .platform = INTEL_I915GM,
 111         .is_mobile = 1,
 112         .cursor_needs_physical = 1,
 113         .has_overlay = 1, .overlay_needs_physical = 1,
 114         .supports_tv = 1,
 115         .has_fbc = 1,
 116         .hws_needs_physical = 1,
 117         .unfenced_needs_alignment = 1,
 118 };
 119
 120 static const struct intel_device_info intel_i945g_info = {
 121         GEN3_FEATURES,
 122         .platform = INTEL_I945G,
 123         .has_hotplug = 1, .cursor_needs_physical = 1,
 124         .has_overlay = 1, .overlay_needs_physical = 1,
 125         .hws_needs_physical = 1,
 126         .unfenced_needs_alignment = 1,
 127 };
 128
 129 static const struct intel_device_info intel_i945gm_info = {
 130         GEN3_FEATURES,
 131         .platform = INTEL_I945GM, .is_mobile = 1,
 132         .has_hotplug = 1, .cursor_needs_physical = 1,
 133         .has_overlay = 1, .overlay_needs_physical = 1,
 134         .supports_tv = 1,
 135         .has_fbc = 1,
 136         .hws_needs_physical = 1,
 137         .unfenced_needs_alignment = 1,
 138 };
 139
 140 static const struct intel_device_info intel_g33_info = {
 141         GEN3_FEATURES,
 142         .platform = INTEL_G33,
 143         .has_hotplug = 1,
 144         .has_overlay = 1,
 145 };
 146
 147 static const struct intel_device_info intel_pineview_info = {
 148         GEN3_FEATURES,
 149         .platform = INTEL_PINEVIEW, .is_mobile = 1,
 150         .has_hotplug = 1,
 151         .has_overlay = 1,
 152 };
 153
 154 #define GEN4_FEATURES \
 155         .gen = 4, .num_pipes = 2, \
 156         .has_hotplug = 1, \
 157         .has_gmch_display = 1, \
 158         .ring_mask = RENDER_RING, \
 159         GEN_DEFAULT_PIPEOFFSETS, \
 160         CURSOR_OFFSETS
 161
 162 static const struct intel_device_info intel_i965g_info = {
 163         GEN4_FEATURES,
 164         .platform = INTEL_I965G,
 165         .has_overlay = 1,
 166         .hws_needs_physical = 1,
 167 };
 168
 169 static const struct intel_device_info intel_i965gm_info = {
 170         GEN4_FEATURES,
 171         .platform = INTEL_I965GM,
 172         .is_mobile = 1, .has_fbc = 1,
 173         .has_overlay = 1,
 174         .supports_tv = 1,
 175         .hws_needs_physical = 1,
 176 };
 177
 178 static const struct intel_device_info intel_g45_info = {
 179         GEN4_FEATURES,
 180         .platform = INTEL_G45,
 181         .has_pipe_cxsr = 1,
 182         .ring_mask = RENDER_RING | BSD_RING,
 183 };
 184
 185 static const struct intel_device_info intel_gm45_info = {
 186         GEN4_FEATURES,
 187         .platform = INTEL_GM45,
 188         .is_mobile = 1, .has_fbc = 1,
 189         .has_pipe_cxsr = 1,
 190         .supports_tv = 1,
 191         .ring_mask = RENDER_RING | BSD_RING,
 192 };
 193
 194 #define GEN5_FEATURES \
 195         .gen = 5, .num_pipes = 2, \
 196         .has_hotplug = 1, \
 197         .has_gmbus_irq = 1, \
 198         .ring_mask = RENDER_RING | BSD_RING, \
 199         GEN_DEFAULT_PIPEOFFSETS, \
 200         CURSOR_OFFSETS
 201
 202 static const struct intel_device_info intel_ironlake_d_info = {
 203         GEN5_FEATURES,
 204         .platform = INTEL_IRONLAKE,
 205 };
 206
 207 static const struct intel_device_info intel_ironlake_m_info = {
 208         GEN5_FEATURES,
 209         .platform = INTEL_IRONLAKE,
 210         .is_mobile = 1,
 211 };
 212
 213 #define GEN6_FEATURES \
 214         .gen = 6, .num_pipes = 2, \
 215         .has_hotplug = 1, \
 216         .has_fbc = 1, \
 217         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 218         .has_llc = 1, \
 219         .has_rc6 = 1, \
 220         .has_rc6p = 1, \
 221         .has_gmbus_irq = 1, \
 222         .has_hw_contexts = 1, \
 223         .has_aliasing_ppgtt = 1, \
 224         GEN_DEFAULT_PIPEOFFSETS, \
 225         CURSOR_OFFSETS
 226
 227 static const struct intel_device_info intel_sandybridge_d_info = {
 228         GEN6_FEATURES,
 229         .platform = INTEL_SANDYBRIDGE,
 230 };
 231
 232 static const struct intel_device_info intel_sandybridge_m_info = {
 233         GEN6_FEATURES,
 234         .platform = INTEL_SANDYBRIDGE,
 235         .is_mobile = 1,
 236 };
 237
 238 #define GEN7_FEATURES  \
 239         .gen = 7, .num_pipes = 3, \
 240         .has_hotplug = 1, \
 241         .has_fbc = 1, \
 242         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 243         .has_llc = 1, \
 244         .has_rc6 = 1, \
 245         .has_rc6p = 1, \
 246         .has_gmbus_irq = 1, \
 247         .has_hw_contexts = 1, \
 248         .has_aliasing_ppgtt = 1, \
 249         .has_full_ppgtt = 1, \
 250         GEN_DEFAULT_PIPEOFFSETS, \
 251         IVB_CURSOR_OFFSETS
 252
 253 static const struct intel_device_info intel_ivybridge_d_info = {
 254         GEN7_FEATURES,
 255         .platform = INTEL_IVYBRIDGE,
 256         .has_l3_dpf = 1,
 257 };
 258
 259 static const struct intel_device_info intel_ivybridge_m_info = {
 260         GEN7_FEATURES,
 261         .platform = INTEL_IVYBRIDGE,
 262         .is_mobile = 1,
 263         .has_l3_dpf = 1,
 264 };
 265
 266 static const struct intel_device_info intel_ivybridge_q_info = {
 267         GEN7_FEATURES,
 268         .platform = INTEL_IVYBRIDGE,
 269         .num_pipes = 0, /* legal, last one wins */
 270         .has_l3_dpf = 1,
 271 };
 272
 273 static const struct intel_device_info intel_valleyview_info = {
 274         .platform = INTEL_VALLEYVIEW,
 275         .gen = 7,
 276         .is_lp = 1,
 277         .num_pipes = 2,
 278         .has_psr = 1,
 279         .has_runtime_pm = 1,
 280         .has_rc6 = 1,
 281         .has_gmbus_irq = 1,
 282         .has_hw_contexts = 1,
 283         .has_gmch_display = 1,
 284         .has_hotplug = 1,
 285         .has_aliasing_ppgtt = 1,
 286         .has_full_ppgtt = 1,
 287         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 288         .display_mmio_offset = VLV_DISPLAY_BASE,
 289         GEN_DEFAULT_PIPEOFFSETS,
 290         CURSOR_OFFSETS
 291 };
 292
 293 #define HSW_FEATURES  \
 294         GEN7_FEATURES, \
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 296         .has_ddi = 1, \
 297         .has_fpga_dbg = 1, \
 298         .has_psr = 1, \
 299         .has_resource_streamer = 1, \
 300         .has_dp_mst = 1, \
 301         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 302         .has_runtime_pm = 1
 303
 304 static const struct intel_device_info intel_haswell_info = {
 305         HSW_FEATURES,
 306         .platform = INTEL_HASWELL,
 307         .has_l3_dpf = 1,
 308 };
 309
 310 #define BDW_FEATURES \
 311         HSW_FEATURES, \
 312         BDW_COLORS, \
 313         .has_logical_ring_contexts = 1, \
 314         .has_full_48bit_ppgtt = 1, \
 315         .has_64bit_reloc = 1
 316
 317 static const struct intel_device_info intel_broadwell_info = {
 318         BDW_FEATURES,
 319         .gen = 8,
 320         .platform = INTEL_BROADWELL,
 321 };
 322
 323 static const struct intel_device_info intel_broadwell_gt3_info = {
 324         BDW_FEATURES,
 325         .gen = 8,
 326         .platform = INTEL_BROADWELL,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328 };
 329
 330 static const struct intel_device_info intel_cherryview_info = {
 331         .gen = 8, .num_pipes = 3,
 332         .has_hotplug = 1,
 333         .is_lp = 1,
 334         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 335         .platform = INTEL_CHERRYVIEW,
 336         .has_64bit_reloc = 1,
 337         .has_psr = 1,
 338         .has_runtime_pm = 1,
 339         .has_resource_streamer = 1,
 340         .has_rc6 = 1,
 341         .has_gmbus_irq = 1,
 342         .has_hw_contexts = 1,
 343         .has_logical_ring_contexts = 1,
 344         .has_gmch_display = 1,
 345         .has_aliasing_ppgtt = 1,
 346         .has_full_ppgtt = 1,
 347         .display_mmio_offset = VLV_DISPLAY_BASE,
 348         GEN_CHV_PIPEOFFSETS,
 349         CURSOR_OFFSETS,
 350         CHV_COLORS,
 351 };
 352
 353 static const struct intel_device_info intel_skylake_info = {
 354         BDW_FEATURES,
 355         .platform = INTEL_SKYLAKE,
 356         .gen = 9,
 357         .has_csr = 1,
 358         .has_guc = 1,
 359         .ddb_size = 896,
 360 };
 361
 362 static const struct intel_device_info intel_skylake_gt3_info = {
 363         BDW_FEATURES,
 364         .platform = INTEL_SKYLAKE,
 365         .gen = 9,
 366         .has_csr = 1,
 367         .has_guc = 1,
 368         .ddb_size = 896,
 369         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 370 };
 371
 372 #define GEN9_LP_FEATURES \
 373         .gen = 9, \
 374         .is_lp = 1, \
 375         .has_hotplug = 1, \
 376         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 377         .num_pipes = 3, \
 378         .has_64bit_reloc = 1, \
 379         .has_ddi = 1, \
 380         .has_fpga_dbg = 1, \
 381         .has_fbc = 1, \
 382         .has_runtime_pm = 1, \
 383         .has_pooled_eu = 0, \
 384         .has_csr = 1, \
 385         .has_resource_streamer = 1, \
 386         .has_rc6 = 1, \
 387         .has_dp_mst = 1, \
 388         .has_gmbus_irq = 1, \
 389         .has_hw_contexts = 1, \
 390         .has_logical_ring_contexts = 1, \
 391         .has_guc = 1, \
 392         .has_decoupled_mmio = 1, \
 393         .has_aliasing_ppgtt = 1, \
 394         .has_full_ppgtt = 1, \
 395         .has_full_48bit_ppgtt = 1, \
 396         GEN_DEFAULT_PIPEOFFSETS, \
 397         IVB_CURSOR_OFFSETS, \
 398         BDW_COLORS
 399
 400 static const struct intel_device_info intel_broxton_info = {
 401         GEN9_LP_FEATURES,
 402         .platform = INTEL_BROXTON,
 403         .ddb_size = 512,
 404 };
 405
 406 static const struct intel_device_info intel_geminilake_info = {
 407         GEN9_LP_FEATURES,
 408         .platform = INTEL_GEMINILAKE,
 409         .is_alpha_support = 1,
 410         .ddb_size = 1024,
 411 };
 412
 413 static const struct intel_device_info intel_kabylake_info = {
 414         BDW_FEATURES,
 415         .platform = INTEL_KABYLAKE,
 416         .gen = 9,
 417         .has_csr = 1,
 418         .has_guc = 1,
 419         .ddb_size = 896,
 420 };
 421
 422 static const struct intel_device_info intel_kabylake_gt3_info = {
 423         BDW_FEATURES,
 424         .platform = INTEL_KABYLAKE,
 425         .gen = 9,
 426         .has_csr = 1,
 427         .has_guc = 1,
 428         .ddb_size = 896,
 429         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 430 };
 431
 432 /*
 433  * Make sure any device matches here are from most specific to most
 434  * general.  For example, since the Quanta match is based on the subsystem
 435  * and subvendor IDs, we need it to come before the more general IVB
 436  * PCI ID matches, otherwise we'll use the wrong info struct above.
 437  */
 438 static const struct pci_device_id pciidlist[] = {
 439         INTEL_I830_IDS(&intel_i830_info),
 440         INTEL_I845G_IDS(&intel_i845g_info),
 441         INTEL_I85X_IDS(&intel_i85x_info),
 442         INTEL_I865G_IDS(&intel_i865g_info),
 443         INTEL_I915G_IDS(&intel_i915g_info),
 444         INTEL_I915GM_IDS(&intel_i915gm_info),
 445         INTEL_I945G_IDS(&intel_i945g_info),
 446         INTEL_I945GM_IDS(&intel_i945gm_info),
 447         INTEL_I965G_IDS(&intel_i965g_info),
 448         INTEL_G33_IDS(&intel_g33_info),
 449         INTEL_I965GM_IDS(&intel_i965gm_info),
 450         INTEL_GM45_IDS(&intel_gm45_info),
 451         INTEL_G45_IDS(&intel_g45_info),
 452         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 453         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 454         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 455         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 456         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 457         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 458         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 459         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 460         INTEL_HSW_IDS(&intel_haswell_info),
 461         INTEL_VLV_IDS(&intel_valleyview_info),
 462         INTEL_BDW_GT12_IDS(&intel_broadwell_info),
 463         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 464         INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
 465         INTEL_CHV_IDS(&intel_cherryview_info),
 466         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 467         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 468         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 469         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 470         INTEL_BXT_IDS(&intel_broxton_info),
 471         INTEL_GLK_IDS(&intel_geminilake_info),
 472         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 473         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 474         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 475         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 476         {0, 0, 0}
 477 };
 478 MODULE_DEVICE_TABLE(pci, pciidlist);
 479
 480 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 481 {
 482         struct intel_device_info *intel_info =
 483                 (struct intel_device_info *) ent->driver_data;
 484
 485         if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
 486                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 487                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 488                          "to enable support in this kernel version, or check for kernel updates.\n");
 489                 return -ENODEV;
 490         }
 491
 492         /* Only bind to function 0 of the device. Early generations
 493          * used function 1 as a placeholder for multi-head. This causes
 494          * us confusion instead, especially on the systems where both
 495          * functions have the same PCI-ID!
 496          */
 497         if (PCI_FUNC(pdev->devfn))
 498                 return -ENODEV;
 499
 500         /*
 501          * apple-gmux is needed on dual GPU MacBook Pro
 502          * to probe the panel if we're the inactive GPU.
 503          */
 504         if (vga_switcheroo_client_probe_defer(pdev))
 505                 return -EPROBE_DEFER;
 506
 507         return i915_driver_load(pdev, ent);
 508 }
 509
 510 static void i915_pci_remove(struct pci_dev *pdev)
 511 {
 512         struct drm_device *dev = pci_get_drvdata(pdev);
 513
 514         i915_driver_unload(dev);
 515         drm_dev_unref(dev);
 516 }
 517
 518 static struct pci_driver i915_pci_driver = {
 519         .name = DRIVER_NAME,
 520         .id_table = pciidlist,
 521         .probe = i915_pci_probe,
 522         .remove = i915_pci_remove,
 523         .driver.pm = &i915_pm_ops,
 524 };
 525
 526 static int __init i915_init(void)
 527 {
 528         bool use_kms = true;
 529
 530         /*
 531          * Enable KMS by default, unless explicitly overriden by
 532          * either the i915.modeset prarameter or by the
 533          * vga_text_mode_force boot option.
 534          */
 535
 536         if (i915.modeset == 0)
 537                 use_kms = false;
 538
 539         if (vgacon_text_force() && i915.modeset == -1)
 540                 use_kms = false;
 541
 542         if (!use_kms) {
 543                 /* Silently fail loading to not upset userspace. */
 544                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 545                 return 0;
 546         }
 547
 548         return pci_register_driver(&i915_pci_driver);
 549 }
 550
 551 static void __exit i915_exit(void)
 552 {
 553         if (!i915_pci_driver.driver.owner)
 554                 return;
 555
 556         pci_unregister_driver(&i915_pci_driver);
 557 }
 558
 559 module_init(i915_init);
 560 module_exit(i915_exit);
 561
 562 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 563 MODULE_AUTHOR("Intel Corporation");
 564
 565 MODULE_DESCRIPTION(DRIVER_DESC);
 566 MODULE_LICENSE("GPL and additional rights");