2 * Autogenerated file by GPU Top : https://github.com/rib/gputop
3 * DO NOT EDIT manually!
6 * Copyright (c) 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include <linux/sysfs.h>
32 #include "i915_oa_sklgt3.h"
35 METRIC_SET_ID_RENDER_BASIC = 1,
36 METRIC_SET_ID_COMPUTE_BASIC,
37 METRIC_SET_ID_RENDER_PIPE_PROFILE,
38 METRIC_SET_ID_MEMORY_READS,
39 METRIC_SET_ID_MEMORY_WRITES,
40 METRIC_SET_ID_COMPUTE_EXTENDED,
41 METRIC_SET_ID_COMPUTE_L3_CACHE,
42 METRIC_SET_ID_HDC_AND_SF,
46 METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
47 METRIC_SET_ID_SAMPLER,
50 METRIC_SET_ID_COMPUTE_EXTRA,
51 METRIC_SET_ID_VME_PIPE,
52 METRIC_SET_ID_TEST_OA,
55 int i915_oa_n_builtin_metric_sets_sklgt3 = 18;
57 static const struct i915_oa_reg b_counter_config_render_basic[] = {
58 { _MMIO(0x2710), 0x00000000 },
59 { _MMIO(0x2714), 0x00800000 },
60 { _MMIO(0x2720), 0x00000000 },
61 { _MMIO(0x2724), 0x00800000 },
62 { _MMIO(0x2740), 0x00000000 },
65 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
66 { _MMIO(0xe458), 0x00005004 },
67 { _MMIO(0xe558), 0x00010003 },
68 { _MMIO(0xe658), 0x00012011 },
69 { _MMIO(0xe758), 0x00015014 },
70 { _MMIO(0xe45c), 0x00051050 },
71 { _MMIO(0xe55c), 0x00053052 },
72 { _MMIO(0xe65c), 0x00055054 },
75 static const struct i915_oa_reg mux_config_render_basic[] = {
76 { _MMIO(0x9888), 0x166c01e0 },
77 { _MMIO(0x9888), 0x12170280 },
78 { _MMIO(0x9888), 0x12370280 },
79 { _MMIO(0x9888), 0x16ec01e0 },
80 { _MMIO(0x9888), 0x11930317 },
81 { _MMIO(0x9888), 0x159303df },
82 { _MMIO(0x9888), 0x3f900003 },
83 { _MMIO(0x9888), 0x1a4e0380 },
84 { _MMIO(0x9888), 0x0a6c0053 },
85 { _MMIO(0x9888), 0x106c0000 },
86 { _MMIO(0x9888), 0x1c6c0000 },
87 { _MMIO(0x9888), 0x0a1b4000 },
88 { _MMIO(0x9888), 0x1c1c0001 },
89 { _MMIO(0x9888), 0x002f1000 },
90 { _MMIO(0x9888), 0x042f1000 },
91 { _MMIO(0x9888), 0x004c4000 },
92 { _MMIO(0x9888), 0x0a4c8400 },
93 { _MMIO(0x9888), 0x0c4c0002 },
94 { _MMIO(0x9888), 0x000d2000 },
95 { _MMIO(0x9888), 0x060d8000 },
96 { _MMIO(0x9888), 0x080da000 },
97 { _MMIO(0x9888), 0x0a0da000 },
98 { _MMIO(0x9888), 0x0c0f0400 },
99 { _MMIO(0x9888), 0x0e0f6600 },
100 { _MMIO(0x9888), 0x100f0001 },
101 { _MMIO(0x9888), 0x002c8000 },
102 { _MMIO(0x9888), 0x162ca200 },
103 { _MMIO(0x9888), 0x062d8000 },
104 { _MMIO(0x9888), 0x082d8000 },
105 { _MMIO(0x9888), 0x00133000 },
106 { _MMIO(0x9888), 0x08133000 },
107 { _MMIO(0x9888), 0x00170020 },
108 { _MMIO(0x9888), 0x08170021 },
109 { _MMIO(0x9888), 0x10170000 },
110 { _MMIO(0x9888), 0x0633c000 },
111 { _MMIO(0x9888), 0x0833c000 },
112 { _MMIO(0x9888), 0x06370800 },
113 { _MMIO(0x9888), 0x08370840 },
114 { _MMIO(0x9888), 0x10370000 },
115 { _MMIO(0x9888), 0x1ace0200 },
116 { _MMIO(0x9888), 0x0aec5300 },
117 { _MMIO(0x9888), 0x10ec0000 },
118 { _MMIO(0x9888), 0x1cec0000 },
119 { _MMIO(0x9888), 0x0a9b8000 },
120 { _MMIO(0x9888), 0x1c9c0002 },
121 { _MMIO(0x9888), 0x0ccc0002 },
122 { _MMIO(0x9888), 0x0a8d8000 },
123 { _MMIO(0x9888), 0x108f0001 },
124 { _MMIO(0x9888), 0x16ac8000 },
125 { _MMIO(0x9888), 0x0d933031 },
126 { _MMIO(0x9888), 0x0f933e3f },
127 { _MMIO(0x9888), 0x01933d00 },
128 { _MMIO(0x9888), 0x0393073c },
129 { _MMIO(0x9888), 0x0593000e },
130 { _MMIO(0x9888), 0x1d930000 },
131 { _MMIO(0x9888), 0x19930000 },
132 { _MMIO(0x9888), 0x1b930000 },
133 { _MMIO(0x9888), 0x1d900157 },
134 { _MMIO(0x9888), 0x1f900158 },
135 { _MMIO(0x9888), 0x35900000 },
136 { _MMIO(0x9888), 0x2b908000 },
137 { _MMIO(0x9888), 0x2d908000 },
138 { _MMIO(0x9888), 0x2f908000 },
139 { _MMIO(0x9888), 0x31908000 },
140 { _MMIO(0x9888), 0x15908000 },
141 { _MMIO(0x9888), 0x17908000 },
142 { _MMIO(0x9888), 0x19908000 },
143 { _MMIO(0x9888), 0x1b908000 },
144 { _MMIO(0x9888), 0x1190003f },
145 { _MMIO(0x9888), 0x51907710 },
146 { _MMIO(0x9888), 0x419020a0 },
147 { _MMIO(0x9888), 0x55901515 },
148 { _MMIO(0x9888), 0x45900529 },
149 { _MMIO(0x9888), 0x47901025 },
150 { _MMIO(0x9888), 0x57907770 },
151 { _MMIO(0x9888), 0x49902100 },
152 { _MMIO(0x9888), 0x37900000 },
153 { _MMIO(0x9888), 0x33900000 },
154 { _MMIO(0x9888), 0x4b900108 },
155 { _MMIO(0x9888), 0x59900007 },
156 { _MMIO(0x9888), 0x43902108 },
157 { _MMIO(0x9888), 0x53907777 },
161 get_render_basic_mux_config(struct drm_i915_private *dev_priv,
162 const struct i915_oa_reg **regs,
167 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
168 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
170 regs[n] = mux_config_render_basic;
171 lens[n] = ARRAY_SIZE(mux_config_render_basic);
177 static const struct i915_oa_reg b_counter_config_compute_basic[] = {
178 { _MMIO(0x2710), 0x00000000 },
179 { _MMIO(0x2714), 0x00800000 },
180 { _MMIO(0x2720), 0x00000000 },
181 { _MMIO(0x2724), 0x00800000 },
182 { _MMIO(0x2740), 0x00000000 },
185 static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
186 { _MMIO(0xe458), 0x00005004 },
187 { _MMIO(0xe558), 0x00000003 },
188 { _MMIO(0xe658), 0x00002001 },
189 { _MMIO(0xe758), 0x00778008 },
190 { _MMIO(0xe45c), 0x00088078 },
191 { _MMIO(0xe55c), 0x00808708 },
192 { _MMIO(0xe65c), 0x00a08908 },
195 static const struct i915_oa_reg mux_config_compute_basic[] = {
196 { _MMIO(0x9888), 0x104f00e0 },
197 { _MMIO(0x9888), 0x124f1c00 },
198 { _MMIO(0x9888), 0x106c00e0 },
199 { _MMIO(0x9888), 0x37906800 },
200 { _MMIO(0x9888), 0x3f900003 },
201 { _MMIO(0x9888), 0x004e8000 },
202 { _MMIO(0x9888), 0x1a4e0820 },
203 { _MMIO(0x9888), 0x1c4e0002 },
204 { _MMIO(0x9888), 0x064f0900 },
205 { _MMIO(0x9888), 0x084f0032 },
206 { _MMIO(0x9888), 0x0a4f1891 },
207 { _MMIO(0x9888), 0x0c4f0e00 },
208 { _MMIO(0x9888), 0x0e4f003c },
209 { _MMIO(0x9888), 0x004f0d80 },
210 { _MMIO(0x9888), 0x024f003b },
211 { _MMIO(0x9888), 0x006c0002 },
212 { _MMIO(0x9888), 0x086c0100 },
213 { _MMIO(0x9888), 0x0c6c000c },
214 { _MMIO(0x9888), 0x0e6c0b00 },
215 { _MMIO(0x9888), 0x186c0000 },
216 { _MMIO(0x9888), 0x1c6c0000 },
217 { _MMIO(0x9888), 0x1e6c0000 },
218 { _MMIO(0x9888), 0x001b4000 },
219 { _MMIO(0x9888), 0x081b8000 },
220 { _MMIO(0x9888), 0x0c1b4000 },
221 { _MMIO(0x9888), 0x0e1b8000 },
222 { _MMIO(0x9888), 0x101c8000 },
223 { _MMIO(0x9888), 0x1a1c8000 },
224 { _MMIO(0x9888), 0x1c1c0024 },
225 { _MMIO(0x9888), 0x065b8000 },
226 { _MMIO(0x9888), 0x085b4000 },
227 { _MMIO(0x9888), 0x0a5bc000 },
228 { _MMIO(0x9888), 0x0c5b8000 },
229 { _MMIO(0x9888), 0x0e5b4000 },
230 { _MMIO(0x9888), 0x005b8000 },
231 { _MMIO(0x9888), 0x025b4000 },
232 { _MMIO(0x9888), 0x1a5c6000 },
233 { _MMIO(0x9888), 0x1c5c001b },
234 { _MMIO(0x9888), 0x125c8000 },
235 { _MMIO(0x9888), 0x145c8000 },
236 { _MMIO(0x9888), 0x004c8000 },
237 { _MMIO(0x9888), 0x0a4c2000 },
238 { _MMIO(0x9888), 0x0c4c0208 },
239 { _MMIO(0x9888), 0x000da000 },
240 { _MMIO(0x9888), 0x060d8000 },
241 { _MMIO(0x9888), 0x080da000 },
242 { _MMIO(0x9888), 0x0a0da000 },
243 { _MMIO(0x9888), 0x0c0da000 },
244 { _MMIO(0x9888), 0x0e0da000 },
245 { _MMIO(0x9888), 0x020d2000 },
246 { _MMIO(0x9888), 0x0c0f5400 },
247 { _MMIO(0x9888), 0x0e0f5500 },
248 { _MMIO(0x9888), 0x100f0155 },
249 { _MMIO(0x9888), 0x002c8000 },
250 { _MMIO(0x9888), 0x0e2cc000 },
251 { _MMIO(0x9888), 0x162cfb00 },
252 { _MMIO(0x9888), 0x182c00be },
253 { _MMIO(0x9888), 0x022cc000 },
254 { _MMIO(0x9888), 0x042cc000 },
255 { _MMIO(0x9888), 0x19900157 },
256 { _MMIO(0x9888), 0x1b900158 },
257 { _MMIO(0x9888), 0x1d900105 },
258 { _MMIO(0x9888), 0x1f900103 },
259 { _MMIO(0x9888), 0x35900000 },
260 { _MMIO(0x9888), 0x11900fff },
261 { _MMIO(0x9888), 0x51900000 },
262 { _MMIO(0x9888), 0x41900800 },
263 { _MMIO(0x9888), 0x55900000 },
264 { _MMIO(0x9888), 0x45900863 },
265 { _MMIO(0x9888), 0x47900802 },
266 { _MMIO(0x9888), 0x57900000 },
267 { _MMIO(0x9888), 0x49900802 },
268 { _MMIO(0x9888), 0x33900000 },
269 { _MMIO(0x9888), 0x4b900002 },
270 { _MMIO(0x9888), 0x59900000 },
271 { _MMIO(0x9888), 0x43900c62 },
272 { _MMIO(0x9888), 0x53903333 },
276 get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
277 const struct i915_oa_reg **regs,
282 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
283 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
285 regs[n] = mux_config_compute_basic;
286 lens[n] = ARRAY_SIZE(mux_config_compute_basic);
292 static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
293 { _MMIO(0x2724), 0xf0800000 },
294 { _MMIO(0x2720), 0x00000000 },
295 { _MMIO(0x2714), 0xf0800000 },
296 { _MMIO(0x2710), 0x00000000 },
297 { _MMIO(0x2740), 0x00000000 },
298 { _MMIO(0x2770), 0x0007ffea },
299 { _MMIO(0x2774), 0x00007ffc },
300 { _MMIO(0x2778), 0x0007affa },
301 { _MMIO(0x277c), 0x0000f5fd },
302 { _MMIO(0x2780), 0x00079ffa },
303 { _MMIO(0x2784), 0x0000f3fb },
304 { _MMIO(0x2788), 0x0007bf7a },
305 { _MMIO(0x278c), 0x0000f7e7 },
306 { _MMIO(0x2790), 0x0007fefa },
307 { _MMIO(0x2794), 0x0000f7cf },
308 { _MMIO(0x2798), 0x00077ffa },
309 { _MMIO(0x279c), 0x0000efdf },
310 { _MMIO(0x27a0), 0x0006fffa },
311 { _MMIO(0x27a4), 0x0000cfbf },
312 { _MMIO(0x27a8), 0x0003fffa },
313 { _MMIO(0x27ac), 0x00005f7f },
316 static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
317 { _MMIO(0xe458), 0x00005004 },
318 { _MMIO(0xe558), 0x00015014 },
319 { _MMIO(0xe658), 0x00025024 },
320 { _MMIO(0xe758), 0x00035034 },
321 { _MMIO(0xe45c), 0x00045044 },
322 { _MMIO(0xe55c), 0x00055054 },
323 { _MMIO(0xe65c), 0x00065064 },
326 static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
327 { _MMIO(0x9888), 0x0c0e001f },
328 { _MMIO(0x9888), 0x0a0f0000 },
329 { _MMIO(0x9888), 0x10116800 },
330 { _MMIO(0x9888), 0x178a03e0 },
331 { _MMIO(0x9888), 0x11824c00 },
332 { _MMIO(0x9888), 0x11830020 },
333 { _MMIO(0x9888), 0x13840020 },
334 { _MMIO(0x9888), 0x11850019 },
335 { _MMIO(0x9888), 0x11860007 },
336 { _MMIO(0x9888), 0x01870c40 },
337 { _MMIO(0x9888), 0x17880000 },
338 { _MMIO(0x9888), 0x022f4000 },
339 { _MMIO(0x9888), 0x0a4c0040 },
340 { _MMIO(0x9888), 0x0c0d8000 },
341 { _MMIO(0x9888), 0x040d4000 },
342 { _MMIO(0x9888), 0x060d2000 },
343 { _MMIO(0x9888), 0x020e5400 },
344 { _MMIO(0x9888), 0x000e0000 },
345 { _MMIO(0x9888), 0x080f0040 },
346 { _MMIO(0x9888), 0x000f0000 },
347 { _MMIO(0x9888), 0x100f0000 },
348 { _MMIO(0x9888), 0x0e0f0040 },
349 { _MMIO(0x9888), 0x0c2c8000 },
350 { _MMIO(0x9888), 0x06104000 },
351 { _MMIO(0x9888), 0x06110012 },
352 { _MMIO(0x9888), 0x06131000 },
353 { _MMIO(0x9888), 0x01898000 },
354 { _MMIO(0x9888), 0x0d890100 },
355 { _MMIO(0x9888), 0x03898000 },
356 { _MMIO(0x9888), 0x09808000 },
357 { _MMIO(0x9888), 0x0b808000 },
358 { _MMIO(0x9888), 0x0380c000 },
359 { _MMIO(0x9888), 0x0f8a0075 },
360 { _MMIO(0x9888), 0x1d8a0000 },
361 { _MMIO(0x9888), 0x118a8000 },
362 { _MMIO(0x9888), 0x1b8a4000 },
363 { _MMIO(0x9888), 0x138a8000 },
364 { _MMIO(0x9888), 0x1d81a000 },
365 { _MMIO(0x9888), 0x15818000 },
366 { _MMIO(0x9888), 0x17818000 },
367 { _MMIO(0x9888), 0x0b820030 },
368 { _MMIO(0x9888), 0x07828000 },
369 { _MMIO(0x9888), 0x0d824000 },
370 { _MMIO(0x9888), 0x0f828000 },
371 { _MMIO(0x9888), 0x05824000 },
372 { _MMIO(0x9888), 0x0d830003 },
373 { _MMIO(0x9888), 0x0583000c },
374 { _MMIO(0x9888), 0x09830000 },
375 { _MMIO(0x9888), 0x03838000 },
376 { _MMIO(0x9888), 0x07838000 },
377 { _MMIO(0x9888), 0x0b840980 },
378 { _MMIO(0x9888), 0x03844d80 },
379 { _MMIO(0x9888), 0x11840000 },
380 { _MMIO(0x9888), 0x09848000 },
381 { _MMIO(0x9888), 0x09850080 },
382 { _MMIO(0x9888), 0x03850003 },
383 { _MMIO(0x9888), 0x01850000 },
384 { _MMIO(0x9888), 0x07860000 },
385 { _MMIO(0x9888), 0x0f860400 },
386 { _MMIO(0x9888), 0x09870032 },
387 { _MMIO(0x9888), 0x01888052 },
388 { _MMIO(0x9888), 0x11880000 },
389 { _MMIO(0x9888), 0x09884000 },
390 { _MMIO(0x9888), 0x1b931001 },
391 { _MMIO(0x9888), 0x1d930001 },
392 { _MMIO(0x9888), 0x19934000 },
393 { _MMIO(0x9888), 0x1b958000 },
394 { _MMIO(0x9888), 0x1d950094 },
395 { _MMIO(0x9888), 0x19958000 },
396 { _MMIO(0x9888), 0x09e58000 },
397 { _MMIO(0x9888), 0x0be58000 },
398 { _MMIO(0x9888), 0x03e5c000 },
399 { _MMIO(0x9888), 0x0592c000 },
400 { _MMIO(0x9888), 0x0b928000 },
401 { _MMIO(0x9888), 0x0d924000 },
402 { _MMIO(0x9888), 0x0f924000 },
403 { _MMIO(0x9888), 0x11928000 },
404 { _MMIO(0x9888), 0x1392c000 },
405 { _MMIO(0x9888), 0x09924000 },
406 { _MMIO(0x9888), 0x01985000 },
407 { _MMIO(0x9888), 0x07988000 },
408 { _MMIO(0x9888), 0x09981000 },
409 { _MMIO(0x9888), 0x0b982000 },
410 { _MMIO(0x9888), 0x0d982000 },
411 { _MMIO(0x9888), 0x0f989000 },
412 { _MMIO(0x9888), 0x05982000 },
413 { _MMIO(0x9888), 0x13904000 },
414 { _MMIO(0x9888), 0x21904000 },
415 { _MMIO(0x9888), 0x23904000 },
416 { _MMIO(0x9888), 0x25908000 },
417 { _MMIO(0x9888), 0x27904000 },
418 { _MMIO(0x9888), 0x29908000 },
419 { _MMIO(0x9888), 0x2b904000 },
420 { _MMIO(0x9888), 0x2f904000 },
421 { _MMIO(0x9888), 0x31904000 },
422 { _MMIO(0x9888), 0x15904000 },
423 { _MMIO(0x9888), 0x17908000 },
424 { _MMIO(0x9888), 0x19908000 },
425 { _MMIO(0x9888), 0x1b904000 },
426 { _MMIO(0x9888), 0x1190c080 },
427 { _MMIO(0x9888), 0x51901150 },
428 { _MMIO(0x9888), 0x41901400 },
429 { _MMIO(0x9888), 0x55905111 },
430 { _MMIO(0x9888), 0x45901400 },
431 { _MMIO(0x9888), 0x479004a5 },
432 { _MMIO(0x9888), 0x57903455 },
433 { _MMIO(0x9888), 0x49900000 },
434 { _MMIO(0x9888), 0x37900000 },
435 { _MMIO(0x9888), 0x33900000 },
436 { _MMIO(0x9888), 0x4b9000a0 },
437 { _MMIO(0x9888), 0x59900001 },
438 { _MMIO(0x9888), 0x43900005 },
439 { _MMIO(0x9888), 0x53900455 },
443 get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
444 const struct i915_oa_reg **regs,
449 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
450 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
452 regs[n] = mux_config_render_pipe_profile;
453 lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
459 static const struct i915_oa_reg b_counter_config_memory_reads[] = {
460 { _MMIO(0x272c), 0xffffffff },
461 { _MMIO(0x2728), 0xffffffff },
462 { _MMIO(0x2724), 0xf0800000 },
463 { _MMIO(0x2720), 0x00000000 },
464 { _MMIO(0x271c), 0xffffffff },
465 { _MMIO(0x2718), 0xffffffff },
466 { _MMIO(0x2714), 0xf0800000 },
467 { _MMIO(0x2710), 0x00000000 },
468 { _MMIO(0x274c), 0x86543210 },
469 { _MMIO(0x2748), 0x86543210 },
470 { _MMIO(0x2744), 0x00006667 },
471 { _MMIO(0x2740), 0x00000000 },
472 { _MMIO(0x275c), 0x86543210 },
473 { _MMIO(0x2758), 0x86543210 },
474 { _MMIO(0x2754), 0x00006465 },
475 { _MMIO(0x2750), 0x00000000 },
476 { _MMIO(0x2770), 0x0007f81a },
477 { _MMIO(0x2774), 0x0000fe00 },
478 { _MMIO(0x2778), 0x0007f82a },
479 { _MMIO(0x277c), 0x0000fe00 },
480 { _MMIO(0x2780), 0x0007f872 },
481 { _MMIO(0x2784), 0x0000fe00 },
482 { _MMIO(0x2788), 0x0007f8ba },
483 { _MMIO(0x278c), 0x0000fe00 },
484 { _MMIO(0x2790), 0x0007f87a },
485 { _MMIO(0x2794), 0x0000fe00 },
486 { _MMIO(0x2798), 0x0007f8ea },
487 { _MMIO(0x279c), 0x0000fe00 },
488 { _MMIO(0x27a0), 0x0007f8e2 },
489 { _MMIO(0x27a4), 0x0000fe00 },
490 { _MMIO(0x27a8), 0x0007f8f2 },
491 { _MMIO(0x27ac), 0x0000fe00 },
494 static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
495 { _MMIO(0xe458), 0x00005004 },
496 { _MMIO(0xe558), 0x00015014 },
497 { _MMIO(0xe658), 0x00025024 },
498 { _MMIO(0xe758), 0x00035034 },
499 { _MMIO(0xe45c), 0x00045044 },
500 { _MMIO(0xe55c), 0x00055054 },
501 { _MMIO(0xe65c), 0x00065064 },
504 static const struct i915_oa_reg mux_config_memory_reads[] = {
505 { _MMIO(0x9888), 0x11810c00 },
506 { _MMIO(0x9888), 0x1381001a },
507 { _MMIO(0x9888), 0x37906800 },
508 { _MMIO(0x9888), 0x3f900064 },
509 { _MMIO(0x9888), 0x03811300 },
510 { _MMIO(0x9888), 0x05811b12 },
511 { _MMIO(0x9888), 0x0781001a },
512 { _MMIO(0x9888), 0x1f810000 },
513 { _MMIO(0x9888), 0x17810000 },
514 { _MMIO(0x9888), 0x19810000 },
515 { _MMIO(0x9888), 0x1b810000 },
516 { _MMIO(0x9888), 0x1d810000 },
517 { _MMIO(0x9888), 0x1b930055 },
518 { _MMIO(0x9888), 0x03e58000 },
519 { _MMIO(0x9888), 0x05e5c000 },
520 { _MMIO(0x9888), 0x07e54000 },
521 { _MMIO(0x9888), 0x13900150 },
522 { _MMIO(0x9888), 0x21900151 },
523 { _MMIO(0x9888), 0x23900152 },
524 { _MMIO(0x9888), 0x25900153 },
525 { _MMIO(0x9888), 0x27900154 },
526 { _MMIO(0x9888), 0x29900155 },
527 { _MMIO(0x9888), 0x2b900156 },
528 { _MMIO(0x9888), 0x2d900157 },
529 { _MMIO(0x9888), 0x2f90015f },
530 { _MMIO(0x9888), 0x31900105 },
531 { _MMIO(0x9888), 0x15900103 },
532 { _MMIO(0x9888), 0x17900101 },
533 { _MMIO(0x9888), 0x35900000 },
534 { _MMIO(0x9888), 0x19908000 },
535 { _MMIO(0x9888), 0x1b908000 },
536 { _MMIO(0x9888), 0x1d908000 },
537 { _MMIO(0x9888), 0x1f908000 },
538 { _MMIO(0x9888), 0x11900000 },
539 { _MMIO(0x9888), 0x51900000 },
540 { _MMIO(0x9888), 0x41900c60 },
541 { _MMIO(0x9888), 0x55900000 },
542 { _MMIO(0x9888), 0x45900c00 },
543 { _MMIO(0x9888), 0x47900c63 },
544 { _MMIO(0x9888), 0x57900000 },
545 { _MMIO(0x9888), 0x49900c63 },
546 { _MMIO(0x9888), 0x33900000 },
547 { _MMIO(0x9888), 0x4b900063 },
548 { _MMIO(0x9888), 0x59900000 },
549 { _MMIO(0x9888), 0x43900003 },
550 { _MMIO(0x9888), 0x53900000 },
554 get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
555 const struct i915_oa_reg **regs,
560 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
561 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
563 regs[n] = mux_config_memory_reads;
564 lens[n] = ARRAY_SIZE(mux_config_memory_reads);
570 static const struct i915_oa_reg b_counter_config_memory_writes[] = {
571 { _MMIO(0x272c), 0xffffffff },
572 { _MMIO(0x2728), 0xffffffff },
573 { _MMIO(0x2724), 0xf0800000 },
574 { _MMIO(0x2720), 0x00000000 },
575 { _MMIO(0x271c), 0xffffffff },
576 { _MMIO(0x2718), 0xffffffff },
577 { _MMIO(0x2714), 0xf0800000 },
578 { _MMIO(0x2710), 0x00000000 },
579 { _MMIO(0x274c), 0x86543210 },
580 { _MMIO(0x2748), 0x86543210 },
581 { _MMIO(0x2744), 0x00006667 },
582 { _MMIO(0x2740), 0x00000000 },
583 { _MMIO(0x275c), 0x86543210 },
584 { _MMIO(0x2758), 0x86543210 },
585 { _MMIO(0x2754), 0x00006465 },
586 { _MMIO(0x2750), 0x00000000 },
587 { _MMIO(0x2770), 0x0007f81a },
588 { _MMIO(0x2774), 0x0000fe00 },
589 { _MMIO(0x2778), 0x0007f82a },
590 { _MMIO(0x277c), 0x0000fe00 },
591 { _MMIO(0x2780), 0x0007f822 },
592 { _MMIO(0x2784), 0x0000fe00 },
593 { _MMIO(0x2788), 0x0007f8ba },
594 { _MMIO(0x278c), 0x0000fe00 },
595 { _MMIO(0x2790), 0x0007f87a },
596 { _MMIO(0x2794), 0x0000fe00 },
597 { _MMIO(0x2798), 0x0007f8ea },
598 { _MMIO(0x279c), 0x0000fe00 },
599 { _MMIO(0x27a0), 0x0007f8e2 },
600 { _MMIO(0x27a4), 0x0000fe00 },
601 { _MMIO(0x27a8), 0x0007f8f2 },
602 { _MMIO(0x27ac), 0x0000fe00 },
605 static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
606 { _MMIO(0xe458), 0x00005004 },
607 { _MMIO(0xe558), 0x00015014 },
608 { _MMIO(0xe658), 0x00025024 },
609 { _MMIO(0xe758), 0x00035034 },
610 { _MMIO(0xe45c), 0x00045044 },
611 { _MMIO(0xe55c), 0x00055054 },
612 { _MMIO(0xe65c), 0x00065064 },
615 static const struct i915_oa_reg mux_config_memory_writes[] = {
616 { _MMIO(0x9888), 0x11810c00 },
617 { _MMIO(0x9888), 0x1381001a },
618 { _MMIO(0x9888), 0x37906800 },
619 { _MMIO(0x9888), 0x3f901000 },
620 { _MMIO(0x9888), 0x03811300 },
621 { _MMIO(0x9888), 0x05811b12 },
622 { _MMIO(0x9888), 0x0781001a },
623 { _MMIO(0x9888), 0x1f810000 },
624 { _MMIO(0x9888), 0x17810000 },
625 { _MMIO(0x9888), 0x19810000 },
626 { _MMIO(0x9888), 0x1b810000 },
627 { _MMIO(0x9888), 0x1d810000 },
628 { _MMIO(0x9888), 0x1b930055 },
629 { _MMIO(0x9888), 0x03e58000 },
630 { _MMIO(0x9888), 0x05e5c000 },
631 { _MMIO(0x9888), 0x07e54000 },
632 { _MMIO(0x9888), 0x13900160 },
633 { _MMIO(0x9888), 0x21900161 },
634 { _MMIO(0x9888), 0x23900162 },
635 { _MMIO(0x9888), 0x25900163 },
636 { _MMIO(0x9888), 0x27900164 },
637 { _MMIO(0x9888), 0x29900165 },
638 { _MMIO(0x9888), 0x2b900166 },
639 { _MMIO(0x9888), 0x2d900167 },
640 { _MMIO(0x9888), 0x2f900150 },
641 { _MMIO(0x9888), 0x31900105 },
642 { _MMIO(0x9888), 0x15900103 },
643 { _MMIO(0x9888), 0x17900101 },
644 { _MMIO(0x9888), 0x35900000 },
645 { _MMIO(0x9888), 0x19908000 },
646 { _MMIO(0x9888), 0x1b908000 },
647 { _MMIO(0x9888), 0x1d908000 },
648 { _MMIO(0x9888), 0x1f908000 },
649 { _MMIO(0x9888), 0x11900000 },
650 { _MMIO(0x9888), 0x51900000 },
651 { _MMIO(0x9888), 0x41900c60 },
652 { _MMIO(0x9888), 0x55900000 },
653 { _MMIO(0x9888), 0x45900c00 },
654 { _MMIO(0x9888), 0x47900c63 },
655 { _MMIO(0x9888), 0x57900000 },
656 { _MMIO(0x9888), 0x49900c63 },
657 { _MMIO(0x9888), 0x33900000 },
658 { _MMIO(0x9888), 0x4b900063 },
659 { _MMIO(0x9888), 0x59900000 },
660 { _MMIO(0x9888), 0x43900003 },
661 { _MMIO(0x9888), 0x53900000 },
665 get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
666 const struct i915_oa_reg **regs,
671 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
672 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
674 regs[n] = mux_config_memory_writes;
675 lens[n] = ARRAY_SIZE(mux_config_memory_writes);
681 static const struct i915_oa_reg b_counter_config_compute_extended[] = {
682 { _MMIO(0x2724), 0xf0800000 },
683 { _MMIO(0x2720), 0x00000000 },
684 { _MMIO(0x2714), 0xf0800000 },
685 { _MMIO(0x2710), 0x00000000 },
686 { _MMIO(0x2740), 0x00000000 },
687 { _MMIO(0x2770), 0x0007fc2a },
688 { _MMIO(0x2774), 0x0000bf00 },
689 { _MMIO(0x2778), 0x0007fc6a },
690 { _MMIO(0x277c), 0x0000bf00 },
691 { _MMIO(0x2780), 0x0007fc92 },
692 { _MMIO(0x2784), 0x0000bf00 },
693 { _MMIO(0x2788), 0x0007fca2 },
694 { _MMIO(0x278c), 0x0000bf00 },
695 { _MMIO(0x2790), 0x0007fc32 },
696 { _MMIO(0x2794), 0x0000bf00 },
697 { _MMIO(0x2798), 0x0007fc9a },
698 { _MMIO(0x279c), 0x0000bf00 },
699 { _MMIO(0x27a0), 0x0007fe6a },
700 { _MMIO(0x27a4), 0x0000bf00 },
701 { _MMIO(0x27a8), 0x0007fe7a },
702 { _MMIO(0x27ac), 0x0000bf00 },
705 static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
706 { _MMIO(0xe458), 0x00005004 },
707 { _MMIO(0xe558), 0x00000003 },
708 { _MMIO(0xe658), 0x00002001 },
709 { _MMIO(0xe758), 0x00778008 },
710 { _MMIO(0xe45c), 0x00088078 },
711 { _MMIO(0xe55c), 0x00808708 },
712 { _MMIO(0xe65c), 0x00a08908 },
715 static const struct i915_oa_reg mux_config_compute_extended[] = {
716 { _MMIO(0x9888), 0x106c00e0 },
717 { _MMIO(0x9888), 0x141c8160 },
718 { _MMIO(0x9888), 0x161c8015 },
719 { _MMIO(0x9888), 0x181c0120 },
720 { _MMIO(0x9888), 0x004e8000 },
721 { _MMIO(0x9888), 0x0e4e8000 },
722 { _MMIO(0x9888), 0x184e8000 },
723 { _MMIO(0x9888), 0x1a4eaaa0 },
724 { _MMIO(0x9888), 0x1c4e0002 },
725 { _MMIO(0x9888), 0x024e8000 },
726 { _MMIO(0x9888), 0x044e8000 },
727 { _MMIO(0x9888), 0x064e8000 },
728 { _MMIO(0x9888), 0x084e8000 },
729 { _MMIO(0x9888), 0x0a4e8000 },
730 { _MMIO(0x9888), 0x0e6c0b01 },
731 { _MMIO(0x9888), 0x006c0200 },
732 { _MMIO(0x9888), 0x026c000c },
733 { _MMIO(0x9888), 0x1c6c0000 },
734 { _MMIO(0x9888), 0x1e6c0000 },
735 { _MMIO(0x9888), 0x1a6c0000 },
736 { _MMIO(0x9888), 0x0e1bc000 },
737 { _MMIO(0x9888), 0x001b8000 },
738 { _MMIO(0x9888), 0x021bc000 },
739 { _MMIO(0x9888), 0x001c0041 },
740 { _MMIO(0x9888), 0x061c4200 },
741 { _MMIO(0x9888), 0x081c4443 },
742 { _MMIO(0x9888), 0x0a1c4645 },
743 { _MMIO(0x9888), 0x0c1c7647 },
744 { _MMIO(0x9888), 0x041c7357 },
745 { _MMIO(0x9888), 0x1c1c0030 },
746 { _MMIO(0x9888), 0x101c0000 },
747 { _MMIO(0x9888), 0x1a1c0000 },
748 { _MMIO(0x9888), 0x121c8000 },
749 { _MMIO(0x9888), 0x004c8000 },
750 { _MMIO(0x9888), 0x0a4caa2a },
751 { _MMIO(0x9888), 0x0c4c02aa },
752 { _MMIO(0x9888), 0x084ca000 },
753 { _MMIO(0x9888), 0x000da000 },
754 { _MMIO(0x9888), 0x060d8000 },
755 { _MMIO(0x9888), 0x080da000 },
756 { _MMIO(0x9888), 0x0a0da000 },
757 { _MMIO(0x9888), 0x0c0da000 },
758 { _MMIO(0x9888), 0x0e0da000 },
759 { _MMIO(0x9888), 0x020da000 },
760 { _MMIO(0x9888), 0x040da000 },
761 { _MMIO(0x9888), 0x0c0f5400 },
762 { _MMIO(0x9888), 0x0e0f5515 },
763 { _MMIO(0x9888), 0x100f0155 },
764 { _MMIO(0x9888), 0x002c8000 },
765 { _MMIO(0x9888), 0x0e2c8000 },
766 { _MMIO(0x9888), 0x162caa00 },
767 { _MMIO(0x9888), 0x182c00aa },
768 { _MMIO(0x9888), 0x022c8000 },
769 { _MMIO(0x9888), 0x042c8000 },
770 { _MMIO(0x9888), 0x062c8000 },
771 { _MMIO(0x9888), 0x082c8000 },
772 { _MMIO(0x9888), 0x0a2c8000 },
773 { _MMIO(0x9888), 0x11907fff },
774 { _MMIO(0x9888), 0x51900000 },
775 { _MMIO(0x9888), 0x41900040 },
776 { _MMIO(0x9888), 0x55900000 },
777 { _MMIO(0x9888), 0x45900802 },
778 { _MMIO(0x9888), 0x47900842 },
779 { _MMIO(0x9888), 0x57900000 },
780 { _MMIO(0x9888), 0x49900842 },
781 { _MMIO(0x9888), 0x37900000 },
782 { _MMIO(0x9888), 0x33900000 },
783 { _MMIO(0x9888), 0x4b900000 },
784 { _MMIO(0x9888), 0x59900000 },
785 { _MMIO(0x9888), 0x43900800 },
786 { _MMIO(0x9888), 0x53900000 },
790 get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
791 const struct i915_oa_reg **regs,
796 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
797 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
799 regs[n] = mux_config_compute_extended;
800 lens[n] = ARRAY_SIZE(mux_config_compute_extended);
806 static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
807 { _MMIO(0x2710), 0x00000000 },
808 { _MMIO(0x2714), 0x30800000 },
809 { _MMIO(0x2720), 0x00000000 },
810 { _MMIO(0x2724), 0x30800000 },
811 { _MMIO(0x2740), 0x00000000 },
812 { _MMIO(0x2770), 0x0007fffa },
813 { _MMIO(0x2774), 0x0000fefe },
814 { _MMIO(0x2778), 0x0007fffa },
815 { _MMIO(0x277c), 0x0000fefd },
816 { _MMIO(0x2790), 0x0007fffa },
817 { _MMIO(0x2794), 0x0000fbef },
818 { _MMIO(0x2798), 0x0007fffa },
819 { _MMIO(0x279c), 0x0000fbdf },
822 static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
823 { _MMIO(0xe458), 0x00005004 },
824 { _MMIO(0xe558), 0x00000003 },
825 { _MMIO(0xe658), 0x00002001 },
826 { _MMIO(0xe758), 0x00101100 },
827 { _MMIO(0xe45c), 0x00201200 },
828 { _MMIO(0xe55c), 0x00301300 },
829 { _MMIO(0xe65c), 0x00401400 },
832 static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
833 { _MMIO(0x9888), 0x166c0760 },
834 { _MMIO(0x9888), 0x1593001e },
835 { _MMIO(0x9888), 0x3f900003 },
836 { _MMIO(0x9888), 0x004e8000 },
837 { _MMIO(0x9888), 0x0e4e8000 },
838 { _MMIO(0x9888), 0x184e8000 },
839 { _MMIO(0x9888), 0x1a4e8020 },
840 { _MMIO(0x9888), 0x1c4e0002 },
841 { _MMIO(0x9888), 0x006c0051 },
842 { _MMIO(0x9888), 0x066c5000 },
843 { _MMIO(0x9888), 0x086c5c5d },
844 { _MMIO(0x9888), 0x0e6c5e5f },
845 { _MMIO(0x9888), 0x106c0000 },
846 { _MMIO(0x9888), 0x186c0000 },
847 { _MMIO(0x9888), 0x1c6c0000 },
848 { _MMIO(0x9888), 0x1e6c0000 },
849 { _MMIO(0x9888), 0x001b4000 },
850 { _MMIO(0x9888), 0x061b8000 },
851 { _MMIO(0x9888), 0x081bc000 },
852 { _MMIO(0x9888), 0x0e1bc000 },
853 { _MMIO(0x9888), 0x101c8000 },
854 { _MMIO(0x9888), 0x1a1ce000 },
855 { _MMIO(0x9888), 0x1c1c0030 },
856 { _MMIO(0x9888), 0x004c8000 },
857 { _MMIO(0x9888), 0x0a4c2a00 },
858 { _MMIO(0x9888), 0x0c4c0280 },
859 { _MMIO(0x9888), 0x000d2000 },
860 { _MMIO(0x9888), 0x060d8000 },
861 { _MMIO(0x9888), 0x080da000 },
862 { _MMIO(0x9888), 0x0e0da000 },
863 { _MMIO(0x9888), 0x0c0f0400 },
864 { _MMIO(0x9888), 0x0e0f1500 },
865 { _MMIO(0x9888), 0x100f0140 },
866 { _MMIO(0x9888), 0x002c8000 },
867 { _MMIO(0x9888), 0x0e2c8000 },
868 { _MMIO(0x9888), 0x162c0a00 },
869 { _MMIO(0x9888), 0x182c00a0 },
870 { _MMIO(0x9888), 0x03933300 },
871 { _MMIO(0x9888), 0x05930032 },
872 { _MMIO(0x9888), 0x11930000 },
873 { _MMIO(0x9888), 0x1b930000 },
874 { _MMIO(0x9888), 0x1d900157 },
875 { _MMIO(0x9888), 0x1f900158 },
876 { _MMIO(0x9888), 0x35900000 },
877 { _MMIO(0x9888), 0x19908000 },
878 { _MMIO(0x9888), 0x1b908000 },
879 { _MMIO(0x9888), 0x1190030f },
880 { _MMIO(0x9888), 0x51900000 },
881 { _MMIO(0x9888), 0x41900000 },
882 { _MMIO(0x9888), 0x55900000 },
883 { _MMIO(0x9888), 0x45900063 },
884 { _MMIO(0x9888), 0x47900000 },
885 { _MMIO(0x9888), 0x37900000 },
886 { _MMIO(0x9888), 0x33900000 },
887 { _MMIO(0x9888), 0x57900000 },
888 { _MMIO(0x9888), 0x4b900000 },
889 { _MMIO(0x9888), 0x59900000 },
890 { _MMIO(0x9888), 0x53903333 },
891 { _MMIO(0x9888), 0x43900840 },
895 get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
896 const struct i915_oa_reg **regs,
901 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
902 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
904 regs[n] = mux_config_compute_l3_cache;
905 lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
911 static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
912 { _MMIO(0x2740), 0x00000000 },
913 { _MMIO(0x2744), 0x00800000 },
914 { _MMIO(0x2710), 0x00000000 },
915 { _MMIO(0x2714), 0x10800000 },
916 { _MMIO(0x2720), 0x00000000 },
917 { _MMIO(0x2724), 0x00800000 },
918 { _MMIO(0x2770), 0x00000002 },
919 { _MMIO(0x2774), 0x0000fdff },
922 static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
923 { _MMIO(0xe458), 0x00005004 },
924 { _MMIO(0xe558), 0x00010003 },
925 { _MMIO(0xe658), 0x00012011 },
926 { _MMIO(0xe758), 0x00015014 },
927 { _MMIO(0xe45c), 0x00051050 },
928 { _MMIO(0xe55c), 0x00053052 },
929 { _MMIO(0xe65c), 0x00055054 },
932 static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
933 { _MMIO(0x9888), 0x104f0232 },
934 { _MMIO(0x9888), 0x124f4640 },
935 { _MMIO(0x9888), 0x106c0232 },
936 { _MMIO(0x9888), 0x11834400 },
937 { _MMIO(0x9888), 0x0a4e8000 },
938 { _MMIO(0x9888), 0x0c4e8000 },
939 { _MMIO(0x9888), 0x004f1880 },
940 { _MMIO(0x9888), 0x024f08bb },
941 { _MMIO(0x9888), 0x044f001b },
942 { _MMIO(0x9888), 0x046c0100 },
943 { _MMIO(0x9888), 0x066c000b },
944 { _MMIO(0x9888), 0x1a6c0000 },
945 { _MMIO(0x9888), 0x041b8000 },
946 { _MMIO(0x9888), 0x061b4000 },
947 { _MMIO(0x9888), 0x1a1c1800 },
948 { _MMIO(0x9888), 0x005b8000 },
949 { _MMIO(0x9888), 0x025bc000 },
950 { _MMIO(0x9888), 0x045b4000 },
951 { _MMIO(0x9888), 0x125c8000 },
952 { _MMIO(0x9888), 0x145c8000 },
953 { _MMIO(0x9888), 0x165c8000 },
954 { _MMIO(0x9888), 0x185c8000 },
955 { _MMIO(0x9888), 0x0a4c00a0 },
956 { _MMIO(0x9888), 0x000d8000 },
957 { _MMIO(0x9888), 0x020da000 },
958 { _MMIO(0x9888), 0x040da000 },
959 { _MMIO(0x9888), 0x060d2000 },
960 { _MMIO(0x9888), 0x0c0f5000 },
961 { _MMIO(0x9888), 0x0e0f0055 },
962 { _MMIO(0x9888), 0x022cc000 },
963 { _MMIO(0x9888), 0x042cc000 },
964 { _MMIO(0x9888), 0x062cc000 },
965 { _MMIO(0x9888), 0x082cc000 },
966 { _MMIO(0x9888), 0x0a2c8000 },
967 { _MMIO(0x9888), 0x0c2c8000 },
968 { _MMIO(0x9888), 0x0f828000 },
969 { _MMIO(0x9888), 0x0f8305c0 },
970 { _MMIO(0x9888), 0x09830000 },
971 { _MMIO(0x9888), 0x07830000 },
972 { _MMIO(0x9888), 0x1d950080 },
973 { _MMIO(0x9888), 0x13928000 },
974 { _MMIO(0x9888), 0x0f988000 },
975 { _MMIO(0x9888), 0x31904000 },
976 { _MMIO(0x9888), 0x1190fc00 },
977 { _MMIO(0x9888), 0x37900000 },
978 { _MMIO(0x9888), 0x59900005 },
979 { _MMIO(0x9888), 0x4b900000 },
980 { _MMIO(0x9888), 0x51900000 },
981 { _MMIO(0x9888), 0x41900800 },
982 { _MMIO(0x9888), 0x43900842 },
983 { _MMIO(0x9888), 0x53900000 },
984 { _MMIO(0x9888), 0x45900000 },
985 { _MMIO(0x9888), 0x33900000 },
989 get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
990 const struct i915_oa_reg **regs,
995 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
996 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
998 regs[n] = mux_config_hdc_and_sf;
999 lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
1005 static const struct i915_oa_reg b_counter_config_l3_1[] = {
1006 { _MMIO(0x2740), 0x00000000 },
1007 { _MMIO(0x2744), 0x00800000 },
1008 { _MMIO(0x2710), 0x00000000 },
1009 { _MMIO(0x2714), 0xf0800000 },
1010 { _MMIO(0x2720), 0x00000000 },
1011 { _MMIO(0x2724), 0xf0800000 },
1012 { _MMIO(0x2770), 0x00100070 },
1013 { _MMIO(0x2774), 0x0000fff1 },
1014 { _MMIO(0x2778), 0x00014002 },
1015 { _MMIO(0x277c), 0x0000c3ff },
1016 { _MMIO(0x2780), 0x00010002 },
1017 { _MMIO(0x2784), 0x0000c7ff },
1018 { _MMIO(0x2788), 0x00004002 },
1019 { _MMIO(0x278c), 0x0000d3ff },
1020 { _MMIO(0x2790), 0x00100700 },
1021 { _MMIO(0x2794), 0x0000ff1f },
1022 { _MMIO(0x2798), 0x00001402 },
1023 { _MMIO(0x279c), 0x0000fc3f },
1024 { _MMIO(0x27a0), 0x00001002 },
1025 { _MMIO(0x27a4), 0x0000fc7f },
1026 { _MMIO(0x27a8), 0x00000402 },
1027 { _MMIO(0x27ac), 0x0000fd3f },
1030 static const struct i915_oa_reg flex_eu_config_l3_1[] = {
1031 { _MMIO(0xe458), 0x00005004 },
1032 { _MMIO(0xe558), 0x00010003 },
1033 { _MMIO(0xe658), 0x00012011 },
1034 { _MMIO(0xe758), 0x00015014 },
1035 { _MMIO(0xe45c), 0x00051050 },
1036 { _MMIO(0xe55c), 0x00053052 },
1037 { _MMIO(0xe65c), 0x00055054 },
1040 static const struct i915_oa_reg mux_config_l3_1[] = {
1041 { _MMIO(0x9888), 0x126c7b40 },
1042 { _MMIO(0x9888), 0x166c0020 },
1043 { _MMIO(0x9888), 0x0a603444 },
1044 { _MMIO(0x9888), 0x0a613400 },
1045 { _MMIO(0x9888), 0x1a4ea800 },
1046 { _MMIO(0x9888), 0x1c4e0002 },
1047 { _MMIO(0x9888), 0x024e8000 },
1048 { _MMIO(0x9888), 0x044e8000 },
1049 { _MMIO(0x9888), 0x064e8000 },
1050 { _MMIO(0x9888), 0x084e8000 },
1051 { _MMIO(0x9888), 0x0a4e8000 },
1052 { _MMIO(0x9888), 0x064f4000 },
1053 { _MMIO(0x9888), 0x0c6c5327 },
1054 { _MMIO(0x9888), 0x0e6c5425 },
1055 { _MMIO(0x9888), 0x006c2a00 },
1056 { _MMIO(0x9888), 0x026c285b },
1057 { _MMIO(0x9888), 0x046c005c },
1058 { _MMIO(0x9888), 0x106c0000 },
1059 { _MMIO(0x9888), 0x1c6c0000 },
1060 { _MMIO(0x9888), 0x1e6c0000 },
1061 { _MMIO(0x9888), 0x1a6c0800 },
1062 { _MMIO(0x9888), 0x0c1bc000 },
1063 { _MMIO(0x9888), 0x0e1bc000 },
1064 { _MMIO(0x9888), 0x001b8000 },
1065 { _MMIO(0x9888), 0x021bc000 },
1066 { _MMIO(0x9888), 0x041bc000 },
1067 { _MMIO(0x9888), 0x1c1c003c },
1068 { _MMIO(0x9888), 0x121c8000 },
1069 { _MMIO(0x9888), 0x141c8000 },
1070 { _MMIO(0x9888), 0x161c8000 },
1071 { _MMIO(0x9888), 0x181c8000 },
1072 { _MMIO(0x9888), 0x1a1c0800 },
1073 { _MMIO(0x9888), 0x065b4000 },
1074 { _MMIO(0x9888), 0x1a5c1000 },
1075 { _MMIO(0x9888), 0x10600000 },
1076 { _MMIO(0x9888), 0x04600000 },
1077 { _MMIO(0x9888), 0x0c610044 },
1078 { _MMIO(0x9888), 0x10610000 },
1079 { _MMIO(0x9888), 0x06610000 },
1080 { _MMIO(0x9888), 0x0c4c02a8 },
1081 { _MMIO(0x9888), 0x084ca000 },
1082 { _MMIO(0x9888), 0x0a4c002a },
1083 { _MMIO(0x9888), 0x0c0da000 },
1084 { _MMIO(0x9888), 0x0e0da000 },
1085 { _MMIO(0x9888), 0x000d8000 },
1086 { _MMIO(0x9888), 0x020da000 },
1087 { _MMIO(0x9888), 0x040da000 },
1088 { _MMIO(0x9888), 0x060d2000 },
1089 { _MMIO(0x9888), 0x100f0154 },
1090 { _MMIO(0x9888), 0x0c0f5000 },
1091 { _MMIO(0x9888), 0x0e0f0055 },
1092 { _MMIO(0x9888), 0x182c00aa },
1093 { _MMIO(0x9888), 0x022c8000 },
1094 { _MMIO(0x9888), 0x042c8000 },
1095 { _MMIO(0x9888), 0x062c8000 },
1096 { _MMIO(0x9888), 0x082c8000 },
1097 { _MMIO(0x9888), 0x0a2c8000 },
1098 { _MMIO(0x9888), 0x0c2cc000 },
1099 { _MMIO(0x9888), 0x1190ffc0 },
1100 { _MMIO(0x9888), 0x57900000 },
1101 { _MMIO(0x9888), 0x49900420 },
1102 { _MMIO(0x9888), 0x37900000 },
1103 { _MMIO(0x9888), 0x33900000 },
1104 { _MMIO(0x9888), 0x4b900021 },
1105 { _MMIO(0x9888), 0x59900000 },
1106 { _MMIO(0x9888), 0x51900000 },
1107 { _MMIO(0x9888), 0x41900400 },
1108 { _MMIO(0x9888), 0x43900421 },
1109 { _MMIO(0x9888), 0x53900000 },
1110 { _MMIO(0x9888), 0x45900040 },
1114 get_l3_1_mux_config(struct drm_i915_private *dev_priv,
1115 const struct i915_oa_reg **regs,
1120 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1121 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1123 regs[n] = mux_config_l3_1;
1124 lens[n] = ARRAY_SIZE(mux_config_l3_1);
1130 static const struct i915_oa_reg b_counter_config_l3_2[] = {
1131 { _MMIO(0x2740), 0x00000000 },
1132 { _MMIO(0x2744), 0x00800000 },
1133 { _MMIO(0x2710), 0x00000000 },
1134 { _MMIO(0x2714), 0xf0800000 },
1135 { _MMIO(0x2720), 0x00000000 },
1136 { _MMIO(0x2724), 0x00800000 },
1137 { _MMIO(0x2770), 0x00100070 },
1138 { _MMIO(0x2774), 0x0000fff1 },
1139 { _MMIO(0x2778), 0x00028002 },
1140 { _MMIO(0x277c), 0x000087ff },
1141 { _MMIO(0x2780), 0x00020002 },
1142 { _MMIO(0x2784), 0x00008fff },
1143 { _MMIO(0x2788), 0x00008002 },
1144 { _MMIO(0x278c), 0x0000a7ff },
1147 static const struct i915_oa_reg flex_eu_config_l3_2[] = {
1148 { _MMIO(0xe458), 0x00005004 },
1149 { _MMIO(0xe558), 0x00010003 },
1150 { _MMIO(0xe658), 0x00012011 },
1151 { _MMIO(0xe758), 0x00015014 },
1152 { _MMIO(0xe45c), 0x00051050 },
1153 { _MMIO(0xe55c), 0x00053052 },
1154 { _MMIO(0xe65c), 0x00055054 },
1157 static const struct i915_oa_reg mux_config_l3_2[] = {
1158 { _MMIO(0x9888), 0x126c02e0 },
1159 { _MMIO(0x9888), 0x146c0001 },
1160 { _MMIO(0x9888), 0x0a623400 },
1161 { _MMIO(0x9888), 0x044e8000 },
1162 { _MMIO(0x9888), 0x064e8000 },
1163 { _MMIO(0x9888), 0x084e8000 },
1164 { _MMIO(0x9888), 0x0a4e8000 },
1165 { _MMIO(0x9888), 0x064f4000 },
1166 { _MMIO(0x9888), 0x026c3324 },
1167 { _MMIO(0x9888), 0x046c3422 },
1168 { _MMIO(0x9888), 0x106c0000 },
1169 { _MMIO(0x9888), 0x1a6c0000 },
1170 { _MMIO(0x9888), 0x021bc000 },
1171 { _MMIO(0x9888), 0x041bc000 },
1172 { _MMIO(0x9888), 0x141c8000 },
1173 { _MMIO(0x9888), 0x161c8000 },
1174 { _MMIO(0x9888), 0x181c8000 },
1175 { _MMIO(0x9888), 0x1a1c0800 },
1176 { _MMIO(0x9888), 0x065b4000 },
1177 { _MMIO(0x9888), 0x1a5c1000 },
1178 { _MMIO(0x9888), 0x06614000 },
1179 { _MMIO(0x9888), 0x0c620044 },
1180 { _MMIO(0x9888), 0x10620000 },
1181 { _MMIO(0x9888), 0x06620000 },
1182 { _MMIO(0x9888), 0x084c8000 },
1183 { _MMIO(0x9888), 0x0a4c002a },
1184 { _MMIO(0x9888), 0x020da000 },
1185 { _MMIO(0x9888), 0x040da000 },
1186 { _MMIO(0x9888), 0x060d2000 },
1187 { _MMIO(0x9888), 0x0c0f4000 },
1188 { _MMIO(0x9888), 0x0e0f0055 },
1189 { _MMIO(0x9888), 0x042c8000 },
1190 { _MMIO(0x9888), 0x062c8000 },
1191 { _MMIO(0x9888), 0x082c8000 },
1192 { _MMIO(0x9888), 0x0a2c8000 },
1193 { _MMIO(0x9888), 0x0c2cc000 },
1194 { _MMIO(0x9888), 0x1190f800 },
1195 { _MMIO(0x9888), 0x37900000 },
1196 { _MMIO(0x9888), 0x51900000 },
1197 { _MMIO(0x9888), 0x43900000 },
1198 { _MMIO(0x9888), 0x53900000 },
1199 { _MMIO(0x9888), 0x45900000 },
1200 { _MMIO(0x9888), 0x33900000 },
1204 get_l3_2_mux_config(struct drm_i915_private *dev_priv,
1205 const struct i915_oa_reg **regs,
1210 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1211 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1213 regs[n] = mux_config_l3_2;
1214 lens[n] = ARRAY_SIZE(mux_config_l3_2);
1220 static const struct i915_oa_reg b_counter_config_l3_3[] = {
1221 { _MMIO(0x2740), 0x00000000 },
1222 { _MMIO(0x2744), 0x00800000 },
1223 { _MMIO(0x2710), 0x00000000 },
1224 { _MMIO(0x2714), 0xf0800000 },
1225 { _MMIO(0x2720), 0x00000000 },
1226 { _MMIO(0x2724), 0x00800000 },
1227 { _MMIO(0x2770), 0x00100070 },
1228 { _MMIO(0x2774), 0x0000fff1 },
1229 { _MMIO(0x2778), 0x00028002 },
1230 { _MMIO(0x277c), 0x000087ff },
1231 { _MMIO(0x2780), 0x00020002 },
1232 { _MMIO(0x2784), 0x00008fff },
1233 { _MMIO(0x2788), 0x00008002 },
1234 { _MMIO(0x278c), 0x0000a7ff },
1237 static const struct i915_oa_reg flex_eu_config_l3_3[] = {
1238 { _MMIO(0xe458), 0x00005004 },
1239 { _MMIO(0xe558), 0x00010003 },
1240 { _MMIO(0xe658), 0x00012011 },
1241 { _MMIO(0xe758), 0x00015014 },
1242 { _MMIO(0xe45c), 0x00051050 },
1243 { _MMIO(0xe55c), 0x00053052 },
1244 { _MMIO(0xe65c), 0x00055054 },
1247 static const struct i915_oa_reg mux_config_l3_3[] = {
1248 { _MMIO(0x9888), 0x126c4e80 },
1249 { _MMIO(0x9888), 0x146c0000 },
1250 { _MMIO(0x9888), 0x0a633400 },
1251 { _MMIO(0x9888), 0x044e8000 },
1252 { _MMIO(0x9888), 0x064e8000 },
1253 { _MMIO(0x9888), 0x084e8000 },
1254 { _MMIO(0x9888), 0x0a4e8000 },
1255 { _MMIO(0x9888), 0x0c4e8000 },
1256 { _MMIO(0x9888), 0x026c3321 },
1257 { _MMIO(0x9888), 0x046c342f },
1258 { _MMIO(0x9888), 0x106c0000 },
1259 { _MMIO(0x9888), 0x1a6c2000 },
1260 { _MMIO(0x9888), 0x021bc000 },
1261 { _MMIO(0x9888), 0x041bc000 },
1262 { _MMIO(0x9888), 0x061b4000 },
1263 { _MMIO(0x9888), 0x141c8000 },
1264 { _MMIO(0x9888), 0x161c8000 },
1265 { _MMIO(0x9888), 0x181c8000 },
1266 { _MMIO(0x9888), 0x1a1c1800 },
1267 { _MMIO(0x9888), 0x06604000 },
1268 { _MMIO(0x9888), 0x0c630044 },
1269 { _MMIO(0x9888), 0x10630000 },
1270 { _MMIO(0x9888), 0x06630000 },
1271 { _MMIO(0x9888), 0x084c8000 },
1272 { _MMIO(0x9888), 0x0a4c00aa },
1273 { _MMIO(0x9888), 0x020da000 },
1274 { _MMIO(0x9888), 0x040da000 },
1275 { _MMIO(0x9888), 0x060d2000 },
1276 { _MMIO(0x9888), 0x0c0f4000 },
1277 { _MMIO(0x9888), 0x0e0f0055 },
1278 { _MMIO(0x9888), 0x042c8000 },
1279 { _MMIO(0x9888), 0x062c8000 },
1280 { _MMIO(0x9888), 0x082c8000 },
1281 { _MMIO(0x9888), 0x0a2c8000 },
1282 { _MMIO(0x9888), 0x0c2c8000 },
1283 { _MMIO(0x9888), 0x1190f800 },
1284 { _MMIO(0x9888), 0x37900000 },
1285 { _MMIO(0x9888), 0x51900000 },
1286 { _MMIO(0x9888), 0x43900842 },
1287 { _MMIO(0x9888), 0x53900000 },
1288 { _MMIO(0x9888), 0x45900002 },
1289 { _MMIO(0x9888), 0x33900000 },
1293 get_l3_3_mux_config(struct drm_i915_private *dev_priv,
1294 const struct i915_oa_reg **regs,
1299 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1300 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1302 regs[n] = mux_config_l3_3;
1303 lens[n] = ARRAY_SIZE(mux_config_l3_3);
1309 static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1310 { _MMIO(0x2740), 0x00000000 },
1311 { _MMIO(0x2744), 0x00800000 },
1312 { _MMIO(0x2710), 0x00000000 },
1313 { _MMIO(0x2714), 0x30800000 },
1314 { _MMIO(0x2720), 0x00000000 },
1315 { _MMIO(0x2724), 0x00800000 },
1316 { _MMIO(0x2770), 0x00000002 },
1317 { _MMIO(0x2774), 0x0000efff },
1318 { _MMIO(0x2778), 0x00006000 },
1319 { _MMIO(0x277c), 0x0000f3ff },
1322 static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1323 { _MMIO(0xe458), 0x00005004 },
1324 { _MMIO(0xe558), 0x00010003 },
1325 { _MMIO(0xe658), 0x00012011 },
1326 { _MMIO(0xe758), 0x00015014 },
1327 { _MMIO(0xe45c), 0x00051050 },
1328 { _MMIO(0xe55c), 0x00053052 },
1329 { _MMIO(0xe65c), 0x00055054 },
1332 static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1333 { _MMIO(0x9888), 0x102f3800 },
1334 { _MMIO(0x9888), 0x144d0500 },
1335 { _MMIO(0x9888), 0x120d03c0 },
1336 { _MMIO(0x9888), 0x140d03cf },
1337 { _MMIO(0x9888), 0x0c0f0004 },
1338 { _MMIO(0x9888), 0x0c4e4000 },
1339 { _MMIO(0x9888), 0x042f0480 },
1340 { _MMIO(0x9888), 0x082f0000 },
1341 { _MMIO(0x9888), 0x022f0000 },
1342 { _MMIO(0x9888), 0x0a4c0090 },
1343 { _MMIO(0x9888), 0x064d0027 },
1344 { _MMIO(0x9888), 0x004d0000 },
1345 { _MMIO(0x9888), 0x000d0d40 },
1346 { _MMIO(0x9888), 0x020d803f },
1347 { _MMIO(0x9888), 0x040d8023 },
1348 { _MMIO(0x9888), 0x100d0000 },
1349 { _MMIO(0x9888), 0x060d2000 },
1350 { _MMIO(0x9888), 0x020f0010 },
1351 { _MMIO(0x9888), 0x000f0000 },
1352 { _MMIO(0x9888), 0x0e0f0050 },
1353 { _MMIO(0x9888), 0x0a2c8000 },
1354 { _MMIO(0x9888), 0x0c2c8000 },
1355 { _MMIO(0x9888), 0x1190fc00 },
1356 { _MMIO(0x9888), 0x37900000 },
1357 { _MMIO(0x9888), 0x51900000 },
1358 { _MMIO(0x9888), 0x41901400 },
1359 { _MMIO(0x9888), 0x43901485 },
1360 { _MMIO(0x9888), 0x53900000 },
1361 { _MMIO(0x9888), 0x45900001 },
1362 { _MMIO(0x9888), 0x33900000 },
1366 get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1367 const struct i915_oa_reg **regs,
1372 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1373 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1375 regs[n] = mux_config_rasterizer_and_pixel_backend;
1376 lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1382 static const struct i915_oa_reg b_counter_config_sampler[] = {
1383 { _MMIO(0x2740), 0x00000000 },
1384 { _MMIO(0x2744), 0x00800000 },
1385 { _MMIO(0x2710), 0x00000000 },
1386 { _MMIO(0x2714), 0x70800000 },
1387 { _MMIO(0x2720), 0x00000000 },
1388 { _MMIO(0x2724), 0x00800000 },
1389 { _MMIO(0x2770), 0x0000c000 },
1390 { _MMIO(0x2774), 0x0000e7ff },
1391 { _MMIO(0x2778), 0x00003000 },
1392 { _MMIO(0x277c), 0x0000f9ff },
1393 { _MMIO(0x2780), 0x00000c00 },
1394 { _MMIO(0x2784), 0x0000fe7f },
1397 static const struct i915_oa_reg flex_eu_config_sampler[] = {
1398 { _MMIO(0xe458), 0x00005004 },
1399 { _MMIO(0xe558), 0x00010003 },
1400 { _MMIO(0xe658), 0x00012011 },
1401 { _MMIO(0xe758), 0x00015014 },
1402 { _MMIO(0xe45c), 0x00051050 },
1403 { _MMIO(0xe55c), 0x00053052 },
1404 { _MMIO(0xe65c), 0x00055054 },
1407 static const struct i915_oa_reg mux_config_sampler[] = {
1408 { _MMIO(0x9888), 0x14152c00 },
1409 { _MMIO(0x9888), 0x16150005 },
1410 { _MMIO(0x9888), 0x121600a0 },
1411 { _MMIO(0x9888), 0x14352c00 },
1412 { _MMIO(0x9888), 0x16350005 },
1413 { _MMIO(0x9888), 0x123600a0 },
1414 { _MMIO(0x9888), 0x14552c00 },
1415 { _MMIO(0x9888), 0x16550005 },
1416 { _MMIO(0x9888), 0x125600a0 },
1417 { _MMIO(0x9888), 0x062f6000 },
1418 { _MMIO(0x9888), 0x022f2000 },
1419 { _MMIO(0x9888), 0x0c4c0050 },
1420 { _MMIO(0x9888), 0x0a4c0010 },
1421 { _MMIO(0x9888), 0x0c0d8000 },
1422 { _MMIO(0x9888), 0x0e0da000 },
1423 { _MMIO(0x9888), 0x000d8000 },
1424 { _MMIO(0x9888), 0x020da000 },
1425 { _MMIO(0x9888), 0x040da000 },
1426 { _MMIO(0x9888), 0x060d2000 },
1427 { _MMIO(0x9888), 0x100f0350 },
1428 { _MMIO(0x9888), 0x0c0fb000 },
1429 { _MMIO(0x9888), 0x0e0f00da },
1430 { _MMIO(0x9888), 0x182c0028 },
1431 { _MMIO(0x9888), 0x0a2c8000 },
1432 { _MMIO(0x9888), 0x022dc000 },
1433 { _MMIO(0x9888), 0x042d4000 },
1434 { _MMIO(0x9888), 0x0c138000 },
1435 { _MMIO(0x9888), 0x0e132000 },
1436 { _MMIO(0x9888), 0x0413c000 },
1437 { _MMIO(0x9888), 0x1c140018 },
1438 { _MMIO(0x9888), 0x0c157000 },
1439 { _MMIO(0x9888), 0x0e150078 },
1440 { _MMIO(0x9888), 0x10150000 },
1441 { _MMIO(0x9888), 0x04162180 },
1442 { _MMIO(0x9888), 0x02160000 },
1443 { _MMIO(0x9888), 0x04174000 },
1444 { _MMIO(0x9888), 0x0233a000 },
1445 { _MMIO(0x9888), 0x04333000 },
1446 { _MMIO(0x9888), 0x14348000 },
1447 { _MMIO(0x9888), 0x16348000 },
1448 { _MMIO(0x9888), 0x02357870 },
1449 { _MMIO(0x9888), 0x10350000 },
1450 { _MMIO(0x9888), 0x04360043 },
1451 { _MMIO(0x9888), 0x02360000 },
1452 { _MMIO(0x9888), 0x04371000 },
1453 { _MMIO(0x9888), 0x0e538000 },
1454 { _MMIO(0x9888), 0x00538000 },
1455 { _MMIO(0x9888), 0x06533000 },
1456 { _MMIO(0x9888), 0x1c540020 },
1457 { _MMIO(0x9888), 0x12548000 },
1458 { _MMIO(0x9888), 0x0e557000 },
1459 { _MMIO(0x9888), 0x00557800 },
1460 { _MMIO(0x9888), 0x10550000 },
1461 { _MMIO(0x9888), 0x06560043 },
1462 { _MMIO(0x9888), 0x02560000 },
1463 { _MMIO(0x9888), 0x06571000 },
1464 { _MMIO(0x9888), 0x1190ff80 },
1465 { _MMIO(0x9888), 0x57900000 },
1466 { _MMIO(0x9888), 0x49900000 },
1467 { _MMIO(0x9888), 0x37900000 },
1468 { _MMIO(0x9888), 0x33900000 },
1469 { _MMIO(0x9888), 0x4b900060 },
1470 { _MMIO(0x9888), 0x59900000 },
1471 { _MMIO(0x9888), 0x51900000 },
1472 { _MMIO(0x9888), 0x41900c00 },
1473 { _MMIO(0x9888), 0x43900842 },
1474 { _MMIO(0x9888), 0x53900000 },
1475 { _MMIO(0x9888), 0x45900060 },
1479 get_sampler_mux_config(struct drm_i915_private *dev_priv,
1480 const struct i915_oa_reg **regs,
1485 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1486 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1488 regs[n] = mux_config_sampler;
1489 lens[n] = ARRAY_SIZE(mux_config_sampler);
1495 static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1496 { _MMIO(0x2740), 0x00000000 },
1497 { _MMIO(0x2744), 0x00800000 },
1498 { _MMIO(0x2710), 0x00000000 },
1499 { _MMIO(0x2714), 0xf0800000 },
1500 { _MMIO(0x2720), 0x00000000 },
1501 { _MMIO(0x2724), 0x30800000 },
1502 { _MMIO(0x2770), 0x00000002 },
1503 { _MMIO(0x2774), 0x00007fff },
1504 { _MMIO(0x2778), 0x00000000 },
1505 { _MMIO(0x277c), 0x00009fff },
1506 { _MMIO(0x2780), 0x00000002 },
1507 { _MMIO(0x2784), 0x0000efff },
1508 { _MMIO(0x2788), 0x00000000 },
1509 { _MMIO(0x278c), 0x0000f3ff },
1510 { _MMIO(0x2790), 0x00000002 },
1511 { _MMIO(0x2794), 0x0000fdff },
1512 { _MMIO(0x2798), 0x00000000 },
1513 { _MMIO(0x279c), 0x0000fe7f },
1516 static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1517 { _MMIO(0xe458), 0x00005004 },
1518 { _MMIO(0xe558), 0x00010003 },
1519 { _MMIO(0xe658), 0x00012011 },
1520 { _MMIO(0xe758), 0x00015014 },
1521 { _MMIO(0xe45c), 0x00051050 },
1522 { _MMIO(0xe55c), 0x00053052 },
1523 { _MMIO(0xe65c), 0x00055054 },
1526 static const struct i915_oa_reg mux_config_tdl_1[] = {
1527 { _MMIO(0x9888), 0x12120000 },
1528 { _MMIO(0x9888), 0x12320000 },
1529 { _MMIO(0x9888), 0x12520000 },
1530 { _MMIO(0x9888), 0x002f8000 },
1531 { _MMIO(0x9888), 0x022f3000 },
1532 { _MMIO(0x9888), 0x0a4c0015 },
1533 { _MMIO(0x9888), 0x0c0d8000 },
1534 { _MMIO(0x9888), 0x0e0da000 },
1535 { _MMIO(0x9888), 0x000d8000 },
1536 { _MMIO(0x9888), 0x020da000 },
1537 { _MMIO(0x9888), 0x040da000 },
1538 { _MMIO(0x9888), 0x060d2000 },
1539 { _MMIO(0x9888), 0x100f03a0 },
1540 { _MMIO(0x9888), 0x0c0ff000 },
1541 { _MMIO(0x9888), 0x0e0f0095 },
1542 { _MMIO(0x9888), 0x062c8000 },
1543 { _MMIO(0x9888), 0x082c8000 },
1544 { _MMIO(0x9888), 0x0a2c8000 },
1545 { _MMIO(0x9888), 0x0c2d8000 },
1546 { _MMIO(0x9888), 0x0e2d4000 },
1547 { _MMIO(0x9888), 0x062d4000 },
1548 { _MMIO(0x9888), 0x02108000 },
1549 { _MMIO(0x9888), 0x0410c000 },
1550 { _MMIO(0x9888), 0x02118000 },
1551 { _MMIO(0x9888), 0x0411c000 },
1552 { _MMIO(0x9888), 0x02121880 },
1553 { _MMIO(0x9888), 0x041219b5 },
1554 { _MMIO(0x9888), 0x00120000 },
1555 { _MMIO(0x9888), 0x02134000 },
1556 { _MMIO(0x9888), 0x04135000 },
1557 { _MMIO(0x9888), 0x0c308000 },
1558 { _MMIO(0x9888), 0x0e304000 },
1559 { _MMIO(0x9888), 0x06304000 },
1560 { _MMIO(0x9888), 0x0c318000 },
1561 { _MMIO(0x9888), 0x0e314000 },
1562 { _MMIO(0x9888), 0x06314000 },
1563 { _MMIO(0x9888), 0x0c321a80 },
1564 { _MMIO(0x9888), 0x0e320033 },
1565 { _MMIO(0x9888), 0x06320031 },
1566 { _MMIO(0x9888), 0x00320000 },
1567 { _MMIO(0x9888), 0x0c334000 },
1568 { _MMIO(0x9888), 0x0e331000 },
1569 { _MMIO(0x9888), 0x06331000 },
1570 { _MMIO(0x9888), 0x0e508000 },
1571 { _MMIO(0x9888), 0x00508000 },
1572 { _MMIO(0x9888), 0x02504000 },
1573 { _MMIO(0x9888), 0x0e518000 },
1574 { _MMIO(0x9888), 0x00518000 },
1575 { _MMIO(0x9888), 0x02514000 },
1576 { _MMIO(0x9888), 0x0e521880 },
1577 { _MMIO(0x9888), 0x00521a80 },
1578 { _MMIO(0x9888), 0x02520033 },
1579 { _MMIO(0x9888), 0x0e534000 },
1580 { _MMIO(0x9888), 0x00534000 },
1581 { _MMIO(0x9888), 0x02531000 },
1582 { _MMIO(0x9888), 0x1190ff80 },
1583 { _MMIO(0x9888), 0x57900000 },
1584 { _MMIO(0x9888), 0x49900800 },
1585 { _MMIO(0x9888), 0x37900000 },
1586 { _MMIO(0x9888), 0x33900000 },
1587 { _MMIO(0x9888), 0x4b900062 },
1588 { _MMIO(0x9888), 0x59900000 },
1589 { _MMIO(0x9888), 0x51900000 },
1590 { _MMIO(0x9888), 0x41900c00 },
1591 { _MMIO(0x9888), 0x43900003 },
1592 { _MMIO(0x9888), 0x53900000 },
1593 { _MMIO(0x9888), 0x45900040 },
1597 get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
1598 const struct i915_oa_reg **regs,
1603 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1604 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1606 regs[n] = mux_config_tdl_1;
1607 lens[n] = ARRAY_SIZE(mux_config_tdl_1);
1613 static const struct i915_oa_reg b_counter_config_tdl_2[] = {
1614 { _MMIO(0x2740), 0x00000000 },
1615 { _MMIO(0x2744), 0x00800000 },
1616 { _MMIO(0x2710), 0x00000000 },
1617 { _MMIO(0x2714), 0x00800000 },
1618 { _MMIO(0x2720), 0x00000000 },
1619 { _MMIO(0x2724), 0x00800000 },
1622 static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
1623 { _MMIO(0xe458), 0x00005004 },
1624 { _MMIO(0xe558), 0x00010003 },
1625 { _MMIO(0xe658), 0x00012011 },
1626 { _MMIO(0xe758), 0x00015014 },
1627 { _MMIO(0xe45c), 0x00051050 },
1628 { _MMIO(0xe55c), 0x00053052 },
1629 { _MMIO(0xe65c), 0x00055054 },
1632 static const struct i915_oa_reg mux_config_tdl_2[] = {
1633 { _MMIO(0x9888), 0x12124d60 },
1634 { _MMIO(0x9888), 0x12322e60 },
1635 { _MMIO(0x9888), 0x12524d60 },
1636 { _MMIO(0x9888), 0x022f3000 },
1637 { _MMIO(0x9888), 0x0a4c0014 },
1638 { _MMIO(0x9888), 0x000d8000 },
1639 { _MMIO(0x9888), 0x020da000 },
1640 { _MMIO(0x9888), 0x040da000 },
1641 { _MMIO(0x9888), 0x060d2000 },
1642 { _MMIO(0x9888), 0x0c0fe000 },
1643 { _MMIO(0x9888), 0x0e0f0097 },
1644 { _MMIO(0x9888), 0x082c8000 },
1645 { _MMIO(0x9888), 0x0a2c8000 },
1646 { _MMIO(0x9888), 0x002d8000 },
1647 { _MMIO(0x9888), 0x062d4000 },
1648 { _MMIO(0x9888), 0x0410c000 },
1649 { _MMIO(0x9888), 0x0411c000 },
1650 { _MMIO(0x9888), 0x04121fb7 },
1651 { _MMIO(0x9888), 0x00120000 },
1652 { _MMIO(0x9888), 0x04135000 },
1653 { _MMIO(0x9888), 0x00308000 },
1654 { _MMIO(0x9888), 0x06304000 },
1655 { _MMIO(0x9888), 0x00318000 },
1656 { _MMIO(0x9888), 0x06314000 },
1657 { _MMIO(0x9888), 0x00321b80 },
1658 { _MMIO(0x9888), 0x0632003f },
1659 { _MMIO(0x9888), 0x00334000 },
1660 { _MMIO(0x9888), 0x06331000 },
1661 { _MMIO(0x9888), 0x0250c000 },
1662 { _MMIO(0x9888), 0x0251c000 },
1663 { _MMIO(0x9888), 0x02521fb7 },
1664 { _MMIO(0x9888), 0x00520000 },
1665 { _MMIO(0x9888), 0x02535000 },
1666 { _MMIO(0x9888), 0x1190fc00 },
1667 { _MMIO(0x9888), 0x37900000 },
1668 { _MMIO(0x9888), 0x51900000 },
1669 { _MMIO(0x9888), 0x41900800 },
1670 { _MMIO(0x9888), 0x43900063 },
1671 { _MMIO(0x9888), 0x53900000 },
1672 { _MMIO(0x9888), 0x45900040 },
1673 { _MMIO(0x9888), 0x33900000 },
1677 get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
1678 const struct i915_oa_reg **regs,
1683 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1684 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1686 regs[n] = mux_config_tdl_2;
1687 lens[n] = ARRAY_SIZE(mux_config_tdl_2);
1693 static const struct i915_oa_reg b_counter_config_compute_extra[] = {
1696 static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
1699 static const struct i915_oa_reg mux_config_compute_extra[] = {
1700 { _MMIO(0x9888), 0x121203e0 },
1701 { _MMIO(0x9888), 0x123203e0 },
1702 { _MMIO(0x9888), 0x125203e0 },
1703 { _MMIO(0x9888), 0x129203e0 },
1704 { _MMIO(0x9888), 0x12b203e0 },
1705 { _MMIO(0x9888), 0x12d203e0 },
1706 { _MMIO(0x9888), 0x024ec000 },
1707 { _MMIO(0x9888), 0x044ec000 },
1708 { _MMIO(0x9888), 0x064ec000 },
1709 { _MMIO(0x9888), 0x022f4000 },
1710 { _MMIO(0x9888), 0x084ca000 },
1711 { _MMIO(0x9888), 0x0a4c0042 },
1712 { _MMIO(0x9888), 0x000d8000 },
1713 { _MMIO(0x9888), 0x020da000 },
1714 { _MMIO(0x9888), 0x040da000 },
1715 { _MMIO(0x9888), 0x060d2000 },
1716 { _MMIO(0x9888), 0x0c0f5000 },
1717 { _MMIO(0x9888), 0x0e0f006d },
1718 { _MMIO(0x9888), 0x022c8000 },
1719 { _MMIO(0x9888), 0x042c8000 },
1720 { _MMIO(0x9888), 0x062c8000 },
1721 { _MMIO(0x9888), 0x0c2c8000 },
1722 { _MMIO(0x9888), 0x042d8000 },
1723 { _MMIO(0x9888), 0x06104000 },
1724 { _MMIO(0x9888), 0x06114000 },
1725 { _MMIO(0x9888), 0x06120033 },
1726 { _MMIO(0x9888), 0x00120000 },
1727 { _MMIO(0x9888), 0x06131000 },
1728 { _MMIO(0x9888), 0x04308000 },
1729 { _MMIO(0x9888), 0x04318000 },
1730 { _MMIO(0x9888), 0x04321980 },
1731 { _MMIO(0x9888), 0x00320000 },
1732 { _MMIO(0x9888), 0x04334000 },
1733 { _MMIO(0x9888), 0x04504000 },
1734 { _MMIO(0x9888), 0x04514000 },
1735 { _MMIO(0x9888), 0x04520033 },
1736 { _MMIO(0x9888), 0x00520000 },
1737 { _MMIO(0x9888), 0x04531000 },
1738 { _MMIO(0x9888), 0x00af8000 },
1739 { _MMIO(0x9888), 0x0acc0001 },
1740 { _MMIO(0x9888), 0x008d8000 },
1741 { _MMIO(0x9888), 0x028da000 },
1742 { _MMIO(0x9888), 0x0c8fb000 },
1743 { _MMIO(0x9888), 0x0e8f0001 },
1744 { _MMIO(0x9888), 0x06ac8000 },
1745 { _MMIO(0x9888), 0x02ad4000 },
1746 { _MMIO(0x9888), 0x02908000 },
1747 { _MMIO(0x9888), 0x02918000 },
1748 { _MMIO(0x9888), 0x02921980 },
1749 { _MMIO(0x9888), 0x00920000 },
1750 { _MMIO(0x9888), 0x02934000 },
1751 { _MMIO(0x9888), 0x02b04000 },
1752 { _MMIO(0x9888), 0x02b14000 },
1753 { _MMIO(0x9888), 0x02b20033 },
1754 { _MMIO(0x9888), 0x00b20000 },
1755 { _MMIO(0x9888), 0x02b31000 },
1756 { _MMIO(0x9888), 0x00d08000 },
1757 { _MMIO(0x9888), 0x00d18000 },
1758 { _MMIO(0x9888), 0x00d21980 },
1759 { _MMIO(0x9888), 0x00d34000 },
1760 { _MMIO(0x9888), 0x1190fc00 },
1761 { _MMIO(0x9888), 0x37900000 },
1762 { _MMIO(0x9888), 0x51900000 },
1763 { _MMIO(0x9888), 0x41900c00 },
1764 { _MMIO(0x9888), 0x43900402 },
1765 { _MMIO(0x9888), 0x53901550 },
1766 { _MMIO(0x9888), 0x45900080 },
1767 { _MMIO(0x9888), 0x33900000 },
1771 get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
1772 const struct i915_oa_reg **regs,
1777 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1778 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1780 regs[n] = mux_config_compute_extra;
1781 lens[n] = ARRAY_SIZE(mux_config_compute_extra);
1787 static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
1788 { _MMIO(0x2740), 0x00000000 },
1789 { _MMIO(0x2710), 0x00000000 },
1790 { _MMIO(0x2714), 0xf0800000 },
1791 { _MMIO(0x2720), 0x00000000 },
1792 { _MMIO(0x2724), 0x30800000 },
1793 { _MMIO(0x2770), 0x00100030 },
1794 { _MMIO(0x2774), 0x0000fff9 },
1795 { _MMIO(0x2778), 0x00000002 },
1796 { _MMIO(0x277c), 0x0000fffc },
1797 { _MMIO(0x2780), 0x00000002 },
1798 { _MMIO(0x2784), 0x0000fff3 },
1799 { _MMIO(0x2788), 0x00100180 },
1800 { _MMIO(0x278c), 0x0000ffcf },
1801 { _MMIO(0x2790), 0x00000002 },
1802 { _MMIO(0x2794), 0x0000ffcf },
1803 { _MMIO(0x2798), 0x00000002 },
1804 { _MMIO(0x279c), 0x0000ff3f },
1807 static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
1808 { _MMIO(0xe458), 0x00005004 },
1809 { _MMIO(0xe558), 0x00008003 },
1812 static const struct i915_oa_reg mux_config_vme_pipe[] = {
1813 { _MMIO(0x9888), 0x141a5800 },
1814 { _MMIO(0x9888), 0x161a00c0 },
1815 { _MMIO(0x9888), 0x12180240 },
1816 { _MMIO(0x9888), 0x14180002 },
1817 { _MMIO(0x9888), 0x149a5800 },
1818 { _MMIO(0x9888), 0x169a00c0 },
1819 { _MMIO(0x9888), 0x12980240 },
1820 { _MMIO(0x9888), 0x14980002 },
1821 { _MMIO(0x9888), 0x1a4e3fc0 },
1822 { _MMIO(0x9888), 0x002f1000 },
1823 { _MMIO(0x9888), 0x022f8000 },
1824 { _MMIO(0x9888), 0x042f3000 },
1825 { _MMIO(0x9888), 0x004c4000 },
1826 { _MMIO(0x9888), 0x0a4c9500 },
1827 { _MMIO(0x9888), 0x0c4c002a },
1828 { _MMIO(0x9888), 0x000d2000 },
1829 { _MMIO(0x9888), 0x060d8000 },
1830 { _MMIO(0x9888), 0x080da000 },
1831 { _MMIO(0x9888), 0x0a0da000 },
1832 { _MMIO(0x9888), 0x0c0da000 },
1833 { _MMIO(0x9888), 0x0c0f0400 },
1834 { _MMIO(0x9888), 0x0e0f5500 },
1835 { _MMIO(0x9888), 0x100f0015 },
1836 { _MMIO(0x9888), 0x002c8000 },
1837 { _MMIO(0x9888), 0x0e2c8000 },
1838 { _MMIO(0x9888), 0x162caa00 },
1839 { _MMIO(0x9888), 0x182c000a },
1840 { _MMIO(0x9888), 0x04193000 },
1841 { _MMIO(0x9888), 0x081a28c1 },
1842 { _MMIO(0x9888), 0x001a0000 },
1843 { _MMIO(0x9888), 0x00133000 },
1844 { _MMIO(0x9888), 0x0613c000 },
1845 { _MMIO(0x9888), 0x0813f000 },
1846 { _MMIO(0x9888), 0x00172000 },
1847 { _MMIO(0x9888), 0x06178000 },
1848 { _MMIO(0x9888), 0x0817a000 },
1849 { _MMIO(0x9888), 0x00180037 },
1850 { _MMIO(0x9888), 0x06180940 },
1851 { _MMIO(0x9888), 0x08180000 },
1852 { _MMIO(0x9888), 0x02180000 },
1853 { _MMIO(0x9888), 0x04183000 },
1854 { _MMIO(0x9888), 0x04afc000 },
1855 { _MMIO(0x9888), 0x06af3000 },
1856 { _MMIO(0x9888), 0x0acc4000 },
1857 { _MMIO(0x9888), 0x0ccc0015 },
1858 { _MMIO(0x9888), 0x0a8da000 },
1859 { _MMIO(0x9888), 0x0c8da000 },
1860 { _MMIO(0x9888), 0x0e8f4000 },
1861 { _MMIO(0x9888), 0x108f0015 },
1862 { _MMIO(0x9888), 0x16aca000 },
1863 { _MMIO(0x9888), 0x18ac000a },
1864 { _MMIO(0x9888), 0x06993000 },
1865 { _MMIO(0x9888), 0x0c9a28c1 },
1866 { _MMIO(0x9888), 0x009a0000 },
1867 { _MMIO(0x9888), 0x0a93f000 },
1868 { _MMIO(0x9888), 0x0c93f000 },
1869 { _MMIO(0x9888), 0x0a97a000 },
1870 { _MMIO(0x9888), 0x0c97a000 },
1871 { _MMIO(0x9888), 0x0a980977 },
1872 { _MMIO(0x9888), 0x08980000 },
1873 { _MMIO(0x9888), 0x04980000 },
1874 { _MMIO(0x9888), 0x06983000 },
1875 { _MMIO(0x9888), 0x119000ff },
1876 { _MMIO(0x9888), 0x51900050 },
1877 { _MMIO(0x9888), 0x41900000 },
1878 { _MMIO(0x9888), 0x55900115 },
1879 { _MMIO(0x9888), 0x45900000 },
1880 { _MMIO(0x9888), 0x47900884 },
1881 { _MMIO(0x9888), 0x57900000 },
1882 { _MMIO(0x9888), 0x49900002 },
1883 { _MMIO(0x9888), 0x37900000 },
1884 { _MMIO(0x9888), 0x33900000 },
1888 get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
1889 const struct i915_oa_reg **regs,
1894 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1895 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1897 regs[n] = mux_config_vme_pipe;
1898 lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
1904 static const struct i915_oa_reg b_counter_config_test_oa[] = {
1905 { _MMIO(0x2740), 0x00000000 },
1906 { _MMIO(0x2744), 0x00800000 },
1907 { _MMIO(0x2714), 0xf0800000 },
1908 { _MMIO(0x2710), 0x00000000 },
1909 { _MMIO(0x2724), 0xf0800000 },
1910 { _MMIO(0x2720), 0x00000000 },
1911 { _MMIO(0x2770), 0x00000004 },
1912 { _MMIO(0x2774), 0x00000000 },
1913 { _MMIO(0x2778), 0x00000003 },
1914 { _MMIO(0x277c), 0x00000000 },
1915 { _MMIO(0x2780), 0x00000007 },
1916 { _MMIO(0x2784), 0x00000000 },
1917 { _MMIO(0x2788), 0x00100002 },
1918 { _MMIO(0x278c), 0x0000fff7 },
1919 { _MMIO(0x2790), 0x00100002 },
1920 { _MMIO(0x2794), 0x0000ffcf },
1921 { _MMIO(0x2798), 0x00100082 },
1922 { _MMIO(0x279c), 0x0000ffef },
1923 { _MMIO(0x27a0), 0x001000c2 },
1924 { _MMIO(0x27a4), 0x0000ffe7 },
1925 { _MMIO(0x27a8), 0x00100001 },
1926 { _MMIO(0x27ac), 0x0000ffe7 },
1929 static const struct i915_oa_reg flex_eu_config_test_oa[] = {
1932 static const struct i915_oa_reg mux_config_test_oa[] = {
1933 { _MMIO(0x9888), 0x11810000 },
1934 { _MMIO(0x9888), 0x07810013 },
1935 { _MMIO(0x9888), 0x1f810000 },
1936 { _MMIO(0x9888), 0x1d810000 },
1937 { _MMIO(0x9888), 0x1b930040 },
1938 { _MMIO(0x9888), 0x07e54000 },
1939 { _MMIO(0x9888), 0x1f908000 },
1940 { _MMIO(0x9888), 0x11900000 },
1941 { _MMIO(0x9888), 0x37900000 },
1942 { _MMIO(0x9888), 0x53900000 },
1943 { _MMIO(0x9888), 0x45900000 },
1944 { _MMIO(0x9888), 0x33900000 },
1948 get_test_oa_mux_config(struct drm_i915_private *dev_priv,
1949 const struct i915_oa_reg **regs,
1954 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1955 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1957 regs[n] = mux_config_test_oa;
1958 lens[n] = ARRAY_SIZE(mux_config_test_oa);
1964 int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv)
1966 dev_priv->perf.oa.n_mux_configs = 0;
1967 dev_priv->perf.oa.b_counter_regs = NULL;
1968 dev_priv->perf.oa.b_counter_regs_len = 0;
1969 dev_priv->perf.oa.flex_regs = NULL;
1970 dev_priv->perf.oa.flex_regs_len = 0;
1972 switch (dev_priv->perf.oa.metrics_set) {
1973 case METRIC_SET_ID_RENDER_BASIC:
1974 dev_priv->perf.oa.n_mux_configs =
1975 get_render_basic_mux_config(dev_priv,
1976 dev_priv->perf.oa.mux_regs,
1977 dev_priv->perf.oa.mux_regs_lens);
1978 if (dev_priv->perf.oa.n_mux_configs == 0) {
1979 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
1981 /* EINVAL because *_register_sysfs already checked this
1982 * and so it wouldn't have been advertised to userspace and
1983 * so shouldn't have been requested
1988 dev_priv->perf.oa.b_counter_regs =
1989 b_counter_config_render_basic;
1990 dev_priv->perf.oa.b_counter_regs_len =
1991 ARRAY_SIZE(b_counter_config_render_basic);
1993 dev_priv->perf.oa.flex_regs =
1994 flex_eu_config_render_basic;
1995 dev_priv->perf.oa.flex_regs_len =
1996 ARRAY_SIZE(flex_eu_config_render_basic);
1999 case METRIC_SET_ID_COMPUTE_BASIC:
2000 dev_priv->perf.oa.n_mux_configs =
2001 get_compute_basic_mux_config(dev_priv,
2002 dev_priv->perf.oa.mux_regs,
2003 dev_priv->perf.oa.mux_regs_lens);
2004 if (dev_priv->perf.oa.n_mux_configs == 0) {
2005 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
2007 /* EINVAL because *_register_sysfs already checked this
2008 * and so it wouldn't have been advertised to userspace and
2009 * so shouldn't have been requested
2014 dev_priv->perf.oa.b_counter_regs =
2015 b_counter_config_compute_basic;
2016 dev_priv->perf.oa.b_counter_regs_len =
2017 ARRAY_SIZE(b_counter_config_compute_basic);
2019 dev_priv->perf.oa.flex_regs =
2020 flex_eu_config_compute_basic;
2021 dev_priv->perf.oa.flex_regs_len =
2022 ARRAY_SIZE(flex_eu_config_compute_basic);
2025 case METRIC_SET_ID_RENDER_PIPE_PROFILE:
2026 dev_priv->perf.oa.n_mux_configs =
2027 get_render_pipe_profile_mux_config(dev_priv,
2028 dev_priv->perf.oa.mux_regs,
2029 dev_priv->perf.oa.mux_regs_lens);
2030 if (dev_priv->perf.oa.n_mux_configs == 0) {
2031 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
2033 /* EINVAL because *_register_sysfs already checked this
2034 * and so it wouldn't have been advertised to userspace and
2035 * so shouldn't have been requested
2040 dev_priv->perf.oa.b_counter_regs =
2041 b_counter_config_render_pipe_profile;
2042 dev_priv->perf.oa.b_counter_regs_len =
2043 ARRAY_SIZE(b_counter_config_render_pipe_profile);
2045 dev_priv->perf.oa.flex_regs =
2046 flex_eu_config_render_pipe_profile;
2047 dev_priv->perf.oa.flex_regs_len =
2048 ARRAY_SIZE(flex_eu_config_render_pipe_profile);
2051 case METRIC_SET_ID_MEMORY_READS:
2052 dev_priv->perf.oa.n_mux_configs =
2053 get_memory_reads_mux_config(dev_priv,
2054 dev_priv->perf.oa.mux_regs,
2055 dev_priv->perf.oa.mux_regs_lens);
2056 if (dev_priv->perf.oa.n_mux_configs == 0) {
2057 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
2059 /* EINVAL because *_register_sysfs already checked this
2060 * and so it wouldn't have been advertised to userspace and
2061 * so shouldn't have been requested
2066 dev_priv->perf.oa.b_counter_regs =
2067 b_counter_config_memory_reads;
2068 dev_priv->perf.oa.b_counter_regs_len =
2069 ARRAY_SIZE(b_counter_config_memory_reads);
2071 dev_priv->perf.oa.flex_regs =
2072 flex_eu_config_memory_reads;
2073 dev_priv->perf.oa.flex_regs_len =
2074 ARRAY_SIZE(flex_eu_config_memory_reads);
2077 case METRIC_SET_ID_MEMORY_WRITES:
2078 dev_priv->perf.oa.n_mux_configs =
2079 get_memory_writes_mux_config(dev_priv,
2080 dev_priv->perf.oa.mux_regs,
2081 dev_priv->perf.oa.mux_regs_lens);
2082 if (dev_priv->perf.oa.n_mux_configs == 0) {
2083 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
2085 /* EINVAL because *_register_sysfs already checked this
2086 * and so it wouldn't have been advertised to userspace and
2087 * so shouldn't have been requested
2092 dev_priv->perf.oa.b_counter_regs =
2093 b_counter_config_memory_writes;
2094 dev_priv->perf.oa.b_counter_regs_len =
2095 ARRAY_SIZE(b_counter_config_memory_writes);
2097 dev_priv->perf.oa.flex_regs =
2098 flex_eu_config_memory_writes;
2099 dev_priv->perf.oa.flex_regs_len =
2100 ARRAY_SIZE(flex_eu_config_memory_writes);
2103 case METRIC_SET_ID_COMPUTE_EXTENDED:
2104 dev_priv->perf.oa.n_mux_configs =
2105 get_compute_extended_mux_config(dev_priv,
2106 dev_priv->perf.oa.mux_regs,
2107 dev_priv->perf.oa.mux_regs_lens);
2108 if (dev_priv->perf.oa.n_mux_configs == 0) {
2109 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
2111 /* EINVAL because *_register_sysfs already checked this
2112 * and so it wouldn't have been advertised to userspace and
2113 * so shouldn't have been requested
2118 dev_priv->perf.oa.b_counter_regs =
2119 b_counter_config_compute_extended;
2120 dev_priv->perf.oa.b_counter_regs_len =
2121 ARRAY_SIZE(b_counter_config_compute_extended);
2123 dev_priv->perf.oa.flex_regs =
2124 flex_eu_config_compute_extended;
2125 dev_priv->perf.oa.flex_regs_len =
2126 ARRAY_SIZE(flex_eu_config_compute_extended);
2129 case METRIC_SET_ID_COMPUTE_L3_CACHE:
2130 dev_priv->perf.oa.n_mux_configs =
2131 get_compute_l3_cache_mux_config(dev_priv,
2132 dev_priv->perf.oa.mux_regs,
2133 dev_priv->perf.oa.mux_regs_lens);
2134 if (dev_priv->perf.oa.n_mux_configs == 0) {
2135 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
2137 /* EINVAL because *_register_sysfs already checked this
2138 * and so it wouldn't have been advertised to userspace and
2139 * so shouldn't have been requested
2144 dev_priv->perf.oa.b_counter_regs =
2145 b_counter_config_compute_l3_cache;
2146 dev_priv->perf.oa.b_counter_regs_len =
2147 ARRAY_SIZE(b_counter_config_compute_l3_cache);
2149 dev_priv->perf.oa.flex_regs =
2150 flex_eu_config_compute_l3_cache;
2151 dev_priv->perf.oa.flex_regs_len =
2152 ARRAY_SIZE(flex_eu_config_compute_l3_cache);
2155 case METRIC_SET_ID_HDC_AND_SF:
2156 dev_priv->perf.oa.n_mux_configs =
2157 get_hdc_and_sf_mux_config(dev_priv,
2158 dev_priv->perf.oa.mux_regs,
2159 dev_priv->perf.oa.mux_regs_lens);
2160 if (dev_priv->perf.oa.n_mux_configs == 0) {
2161 DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
2163 /* EINVAL because *_register_sysfs already checked this
2164 * and so it wouldn't have been advertised to userspace and
2165 * so shouldn't have been requested
2170 dev_priv->perf.oa.b_counter_regs =
2171 b_counter_config_hdc_and_sf;
2172 dev_priv->perf.oa.b_counter_regs_len =
2173 ARRAY_SIZE(b_counter_config_hdc_and_sf);
2175 dev_priv->perf.oa.flex_regs =
2176 flex_eu_config_hdc_and_sf;
2177 dev_priv->perf.oa.flex_regs_len =
2178 ARRAY_SIZE(flex_eu_config_hdc_and_sf);
2181 case METRIC_SET_ID_L3_1:
2182 dev_priv->perf.oa.n_mux_configs =
2183 get_l3_1_mux_config(dev_priv,
2184 dev_priv->perf.oa.mux_regs,
2185 dev_priv->perf.oa.mux_regs_lens);
2186 if (dev_priv->perf.oa.n_mux_configs == 0) {
2187 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
2189 /* EINVAL because *_register_sysfs already checked this
2190 * and so it wouldn't have been advertised to userspace and
2191 * so shouldn't have been requested
2196 dev_priv->perf.oa.b_counter_regs =
2197 b_counter_config_l3_1;
2198 dev_priv->perf.oa.b_counter_regs_len =
2199 ARRAY_SIZE(b_counter_config_l3_1);
2201 dev_priv->perf.oa.flex_regs =
2202 flex_eu_config_l3_1;
2203 dev_priv->perf.oa.flex_regs_len =
2204 ARRAY_SIZE(flex_eu_config_l3_1);
2207 case METRIC_SET_ID_L3_2:
2208 dev_priv->perf.oa.n_mux_configs =
2209 get_l3_2_mux_config(dev_priv,
2210 dev_priv->perf.oa.mux_regs,
2211 dev_priv->perf.oa.mux_regs_lens);
2212 if (dev_priv->perf.oa.n_mux_configs == 0) {
2213 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
2215 /* EINVAL because *_register_sysfs already checked this
2216 * and so it wouldn't have been advertised to userspace and
2217 * so shouldn't have been requested
2222 dev_priv->perf.oa.b_counter_regs =
2223 b_counter_config_l3_2;
2224 dev_priv->perf.oa.b_counter_regs_len =
2225 ARRAY_SIZE(b_counter_config_l3_2);
2227 dev_priv->perf.oa.flex_regs =
2228 flex_eu_config_l3_2;
2229 dev_priv->perf.oa.flex_regs_len =
2230 ARRAY_SIZE(flex_eu_config_l3_2);
2233 case METRIC_SET_ID_L3_3:
2234 dev_priv->perf.oa.n_mux_configs =
2235 get_l3_3_mux_config(dev_priv,
2236 dev_priv->perf.oa.mux_regs,
2237 dev_priv->perf.oa.mux_regs_lens);
2238 if (dev_priv->perf.oa.n_mux_configs == 0) {
2239 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
2241 /* EINVAL because *_register_sysfs already checked this
2242 * and so it wouldn't have been advertised to userspace and
2243 * so shouldn't have been requested
2248 dev_priv->perf.oa.b_counter_regs =
2249 b_counter_config_l3_3;
2250 dev_priv->perf.oa.b_counter_regs_len =
2251 ARRAY_SIZE(b_counter_config_l3_3);
2253 dev_priv->perf.oa.flex_regs =
2254 flex_eu_config_l3_3;
2255 dev_priv->perf.oa.flex_regs_len =
2256 ARRAY_SIZE(flex_eu_config_l3_3);
2259 case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
2260 dev_priv->perf.oa.n_mux_configs =
2261 get_rasterizer_and_pixel_backend_mux_config(dev_priv,
2262 dev_priv->perf.oa.mux_regs,
2263 dev_priv->perf.oa.mux_regs_lens);
2264 if (dev_priv->perf.oa.n_mux_configs == 0) {
2265 DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
2267 /* EINVAL because *_register_sysfs already checked this
2268 * and so it wouldn't have been advertised to userspace and
2269 * so shouldn't have been requested
2274 dev_priv->perf.oa.b_counter_regs =
2275 b_counter_config_rasterizer_and_pixel_backend;
2276 dev_priv->perf.oa.b_counter_regs_len =
2277 ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
2279 dev_priv->perf.oa.flex_regs =
2280 flex_eu_config_rasterizer_and_pixel_backend;
2281 dev_priv->perf.oa.flex_regs_len =
2282 ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
2285 case METRIC_SET_ID_SAMPLER:
2286 dev_priv->perf.oa.n_mux_configs =
2287 get_sampler_mux_config(dev_priv,
2288 dev_priv->perf.oa.mux_regs,
2289 dev_priv->perf.oa.mux_regs_lens);
2290 if (dev_priv->perf.oa.n_mux_configs == 0) {
2291 DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
2293 /* EINVAL because *_register_sysfs already checked this
2294 * and so it wouldn't have been advertised to userspace and
2295 * so shouldn't have been requested
2300 dev_priv->perf.oa.b_counter_regs =
2301 b_counter_config_sampler;
2302 dev_priv->perf.oa.b_counter_regs_len =
2303 ARRAY_SIZE(b_counter_config_sampler);
2305 dev_priv->perf.oa.flex_regs =
2306 flex_eu_config_sampler;
2307 dev_priv->perf.oa.flex_regs_len =
2308 ARRAY_SIZE(flex_eu_config_sampler);
2311 case METRIC_SET_ID_TDL_1:
2312 dev_priv->perf.oa.n_mux_configs =
2313 get_tdl_1_mux_config(dev_priv,
2314 dev_priv->perf.oa.mux_regs,
2315 dev_priv->perf.oa.mux_regs_lens);
2316 if (dev_priv->perf.oa.n_mux_configs == 0) {
2317 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2319 /* EINVAL because *_register_sysfs already checked this
2320 * and so it wouldn't have been advertised to userspace and
2321 * so shouldn't have been requested
2326 dev_priv->perf.oa.b_counter_regs =
2327 b_counter_config_tdl_1;
2328 dev_priv->perf.oa.b_counter_regs_len =
2329 ARRAY_SIZE(b_counter_config_tdl_1);
2331 dev_priv->perf.oa.flex_regs =
2332 flex_eu_config_tdl_1;
2333 dev_priv->perf.oa.flex_regs_len =
2334 ARRAY_SIZE(flex_eu_config_tdl_1);
2337 case METRIC_SET_ID_TDL_2:
2338 dev_priv->perf.oa.n_mux_configs =
2339 get_tdl_2_mux_config(dev_priv,
2340 dev_priv->perf.oa.mux_regs,
2341 dev_priv->perf.oa.mux_regs_lens);
2342 if (dev_priv->perf.oa.n_mux_configs == 0) {
2343 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2345 /* EINVAL because *_register_sysfs already checked this
2346 * and so it wouldn't have been advertised to userspace and
2347 * so shouldn't have been requested
2352 dev_priv->perf.oa.b_counter_regs =
2353 b_counter_config_tdl_2;
2354 dev_priv->perf.oa.b_counter_regs_len =
2355 ARRAY_SIZE(b_counter_config_tdl_2);
2357 dev_priv->perf.oa.flex_regs =
2358 flex_eu_config_tdl_2;
2359 dev_priv->perf.oa.flex_regs_len =
2360 ARRAY_SIZE(flex_eu_config_tdl_2);
2363 case METRIC_SET_ID_COMPUTE_EXTRA:
2364 dev_priv->perf.oa.n_mux_configs =
2365 get_compute_extra_mux_config(dev_priv,
2366 dev_priv->perf.oa.mux_regs,
2367 dev_priv->perf.oa.mux_regs_lens);
2368 if (dev_priv->perf.oa.n_mux_configs == 0) {
2369 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
2371 /* EINVAL because *_register_sysfs already checked this
2372 * and so it wouldn't have been advertised to userspace and
2373 * so shouldn't have been requested
2378 dev_priv->perf.oa.b_counter_regs =
2379 b_counter_config_compute_extra;
2380 dev_priv->perf.oa.b_counter_regs_len =
2381 ARRAY_SIZE(b_counter_config_compute_extra);
2383 dev_priv->perf.oa.flex_regs =
2384 flex_eu_config_compute_extra;
2385 dev_priv->perf.oa.flex_regs_len =
2386 ARRAY_SIZE(flex_eu_config_compute_extra);
2389 case METRIC_SET_ID_VME_PIPE:
2390 dev_priv->perf.oa.n_mux_configs =
2391 get_vme_pipe_mux_config(dev_priv,
2392 dev_priv->perf.oa.mux_regs,
2393 dev_priv->perf.oa.mux_regs_lens);
2394 if (dev_priv->perf.oa.n_mux_configs == 0) {
2395 DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
2397 /* EINVAL because *_register_sysfs already checked this
2398 * and so it wouldn't have been advertised to userspace and
2399 * so shouldn't have been requested
2404 dev_priv->perf.oa.b_counter_regs =
2405 b_counter_config_vme_pipe;
2406 dev_priv->perf.oa.b_counter_regs_len =
2407 ARRAY_SIZE(b_counter_config_vme_pipe);
2409 dev_priv->perf.oa.flex_regs =
2410 flex_eu_config_vme_pipe;
2411 dev_priv->perf.oa.flex_regs_len =
2412 ARRAY_SIZE(flex_eu_config_vme_pipe);
2415 case METRIC_SET_ID_TEST_OA:
2416 dev_priv->perf.oa.n_mux_configs =
2417 get_test_oa_mux_config(dev_priv,
2418 dev_priv->perf.oa.mux_regs,
2419 dev_priv->perf.oa.mux_regs_lens);
2420 if (dev_priv->perf.oa.n_mux_configs == 0) {
2421 DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2423 /* EINVAL because *_register_sysfs already checked this
2424 * and so it wouldn't have been advertised to userspace and
2425 * so shouldn't have been requested
2430 dev_priv->perf.oa.b_counter_regs =
2431 b_counter_config_test_oa;
2432 dev_priv->perf.oa.b_counter_regs_len =
2433 ARRAY_SIZE(b_counter_config_test_oa);
2435 dev_priv->perf.oa.flex_regs =
2436 flex_eu_config_test_oa;
2437 dev_priv->perf.oa.flex_regs_len =
2438 ARRAY_SIZE(flex_eu_config_test_oa);
2447 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2449 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2452 static struct device_attribute dev_attr_render_basic_id = {
2453 .attr = { .name = "id", .mode = 0444 },
2454 .show = show_render_basic_id,
2458 static struct attribute *attrs_render_basic[] = {
2459 &dev_attr_render_basic_id.attr,
2463 static struct attribute_group group_render_basic = {
2464 .name = "4616d450-2393-4836-8146-53c5ed84d359",
2465 .attrs = attrs_render_basic,
2469 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2471 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2474 static struct device_attribute dev_attr_compute_basic_id = {
2475 .attr = { .name = "id", .mode = 0444 },
2476 .show = show_compute_basic_id,
2480 static struct attribute *attrs_compute_basic[] = {
2481 &dev_attr_compute_basic_id.attr,
2485 static struct attribute_group group_compute_basic = {
2486 .name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58",
2487 .attrs = attrs_compute_basic,
2491 show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2493 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2496 static struct device_attribute dev_attr_render_pipe_profile_id = {
2497 .attr = { .name = "id", .mode = 0444 },
2498 .show = show_render_pipe_profile_id,
2502 static struct attribute *attrs_render_pipe_profile[] = {
2503 &dev_attr_render_pipe_profile_id.attr,
2507 static struct attribute_group group_render_pipe_profile = {
2508 .name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d",
2509 .attrs = attrs_render_pipe_profile,
2513 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
2515 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
2518 static struct device_attribute dev_attr_memory_reads_id = {
2519 .attr = { .name = "id", .mode = 0444 },
2520 .show = show_memory_reads_id,
2524 static struct attribute *attrs_memory_reads[] = {
2525 &dev_attr_memory_reads_id.attr,
2529 static struct attribute_group group_memory_reads = {
2530 .name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767",
2531 .attrs = attrs_memory_reads,
2535 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
2537 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
2540 static struct device_attribute dev_attr_memory_writes_id = {
2541 .attr = { .name = "id", .mode = 0444 },
2542 .show = show_memory_writes_id,
2546 static struct attribute *attrs_memory_writes[] = {
2547 &dev_attr_memory_writes_id.attr,
2551 static struct attribute_group group_memory_writes = {
2552 .name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14",
2553 .attrs = attrs_memory_writes,
2557 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
2559 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
2562 static struct device_attribute dev_attr_compute_extended_id = {
2563 .attr = { .name = "id", .mode = 0444 },
2564 .show = show_compute_extended_id,
2568 static struct attribute *attrs_compute_extended[] = {
2569 &dev_attr_compute_extended_id.attr,
2573 static struct attribute_group group_compute_extended = {
2574 .name = "52435e0b-f188-42ea-8680-21a56ee20dee",
2575 .attrs = attrs_compute_extended,
2579 show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
2581 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
2584 static struct device_attribute dev_attr_compute_l3_cache_id = {
2585 .attr = { .name = "id", .mode = 0444 },
2586 .show = show_compute_l3_cache_id,
2590 static struct attribute *attrs_compute_l3_cache[] = {
2591 &dev_attr_compute_l3_cache_id.attr,
2595 static struct attribute_group group_compute_l3_cache = {
2596 .name = "27076eeb-49f3-4fed-8423-c66506005c63",
2597 .attrs = attrs_compute_l3_cache,
2601 show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
2603 return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
2606 static struct device_attribute dev_attr_hdc_and_sf_id = {
2607 .attr = { .name = "id", .mode = 0444 },
2608 .show = show_hdc_and_sf_id,
2612 static struct attribute *attrs_hdc_and_sf[] = {
2613 &dev_attr_hdc_and_sf_id.attr,
2617 static struct attribute_group group_hdc_and_sf = {
2618 .name = "8071b409-c39a-4674-94d7-32962ecfb512",
2619 .attrs = attrs_hdc_and_sf,
2623 show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2625 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
2628 static struct device_attribute dev_attr_l3_1_id = {
2629 .attr = { .name = "id", .mode = 0444 },
2630 .show = show_l3_1_id,
2634 static struct attribute *attrs_l3_1[] = {
2635 &dev_attr_l3_1_id.attr,
2639 static struct attribute_group group_l3_1 = {
2640 .name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed",
2641 .attrs = attrs_l3_1,
2645 show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2647 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
2650 static struct device_attribute dev_attr_l3_2_id = {
2651 .attr = { .name = "id", .mode = 0444 },
2652 .show = show_l3_2_id,
2656 static struct attribute *attrs_l3_2[] = {
2657 &dev_attr_l3_2_id.attr,
2661 static struct attribute_group group_l3_2 = {
2662 .name = "25dc828e-1d2d-426e-9546-a1d4233cdf16",
2663 .attrs = attrs_l3_2,
2667 show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
2669 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
2672 static struct device_attribute dev_attr_l3_3_id = {
2673 .attr = { .name = "id", .mode = 0444 },
2674 .show = show_l3_3_id,
2678 static struct attribute *attrs_l3_3[] = {
2679 &dev_attr_l3_3_id.attr,
2683 static struct attribute_group group_l3_3 = {
2684 .name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf",
2685 .attrs = attrs_l3_3,
2689 show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
2691 return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
2694 static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
2695 .attr = { .name = "id", .mode = 0444 },
2696 .show = show_rasterizer_and_pixel_backend_id,
2700 static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
2701 &dev_attr_rasterizer_and_pixel_backend_id.attr,
2705 static struct attribute_group group_rasterizer_and_pixel_backend = {
2706 .name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5",
2707 .attrs = attrs_rasterizer_and_pixel_backend,
2711 show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
2713 return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
2716 static struct device_attribute dev_attr_sampler_id = {
2717 .attr = { .name = "id", .mode = 0444 },
2718 .show = show_sampler_id,
2722 static struct attribute *attrs_sampler[] = {
2723 &dev_attr_sampler_id.attr,
2727 static struct attribute_group group_sampler = {
2728 .name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6",
2729 .attrs = attrs_sampler,
2733 show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2735 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
2738 static struct device_attribute dev_attr_tdl_1_id = {
2739 .attr = { .name = "id", .mode = 0444 },
2740 .show = show_tdl_1_id,
2744 static struct attribute *attrs_tdl_1[] = {
2745 &dev_attr_tdl_1_id.attr,
2749 static struct attribute_group group_tdl_1 = {
2750 .name = "b375c985-9953-455b-bda2-b03f7594e9db",
2751 .attrs = attrs_tdl_1,
2755 show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2757 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
2760 static struct device_attribute dev_attr_tdl_2_id = {
2761 .attr = { .name = "id", .mode = 0444 },
2762 .show = show_tdl_2_id,
2766 static struct attribute *attrs_tdl_2[] = {
2767 &dev_attr_tdl_2_id.attr,
2771 static struct attribute_group group_tdl_2 = {
2772 .name = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d",
2773 .attrs = attrs_tdl_2,
2777 show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
2779 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
2782 static struct device_attribute dev_attr_compute_extra_id = {
2783 .attr = { .name = "id", .mode = 0444 },
2784 .show = show_compute_extra_id,
2788 static struct attribute *attrs_compute_extra[] = {
2789 &dev_attr_compute_extra_id.attr,
2793 static struct attribute_group group_compute_extra = {
2794 .name = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221",
2795 .attrs = attrs_compute_extra,
2799 show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
2801 return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
2804 static struct device_attribute dev_attr_vme_pipe_id = {
2805 .attr = { .name = "id", .mode = 0444 },
2806 .show = show_vme_pipe_id,
2810 static struct attribute *attrs_vme_pipe[] = {
2811 &dev_attr_vme_pipe_id.attr,
2815 static struct attribute_group group_vme_pipe = {
2816 .name = "cfae9232-6ffc-42cc-a703-9790016925f0",
2817 .attrs = attrs_vme_pipe,
2821 show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
2823 return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
2826 static struct device_attribute dev_attr_test_oa_id = {
2827 .attr = { .name = "id", .mode = 0444 },
2828 .show = show_test_oa_id,
2832 static struct attribute *attrs_test_oa[] = {
2833 &dev_attr_test_oa_id.attr,
2837 static struct attribute_group group_test_oa = {
2838 .name = "2b985803-d3c9-4629-8a4f-634bfecba0e8",
2839 .attrs = attrs_test_oa,
2843 i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv)
2845 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2846 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2849 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2850 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2852 goto error_render_basic;
2854 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2855 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2857 goto error_compute_basic;
2859 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
2860 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2862 goto error_render_pipe_profile;
2864 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
2865 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2867 goto error_memory_reads;
2869 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
2870 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2872 goto error_memory_writes;
2874 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
2875 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2877 goto error_compute_extended;
2879 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
2880 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2882 goto error_compute_l3_cache;
2884 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
2885 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2887 goto error_hdc_and_sf;
2889 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2890 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2894 if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2895 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2899 if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
2900 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2904 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
2905 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2907 goto error_rasterizer_and_pixel_backend;
2909 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
2910 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
2914 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2915 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2919 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2920 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2924 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
2925 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2927 goto error_compute_extra;
2929 if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
2930 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2932 goto error_vme_pipe;
2934 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
2935 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2943 if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
2944 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2946 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2947 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2948 error_compute_extra:
2949 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2950 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2952 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2953 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2955 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2956 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2958 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2959 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2960 error_rasterizer_and_pixel_backend:
2961 if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
2962 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2964 if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
2965 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2967 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2968 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2970 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2971 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2973 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2974 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2975 error_compute_l3_cache:
2976 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2977 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2978 error_compute_extended:
2979 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2980 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2981 error_memory_writes:
2982 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2983 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2985 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2986 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2987 error_render_pipe_profile:
2988 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2989 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2990 error_compute_basic:
2991 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2992 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2998 i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv)
3000 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
3001 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
3003 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
3004 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
3005 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
3006 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
3007 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
3008 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
3009 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
3010 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
3011 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
3012 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
3013 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
3014 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
3015 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
3016 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
3017 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
3018 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
3019 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
3020 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
3021 if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
3022 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
3023 if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
3024 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
3025 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
3026 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
3027 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
3028 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
3029 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
3030 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
3031 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
3032 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
3033 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
3034 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
3035 if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
3036 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
3037 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
3038 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
git.samba.org / sfrench / cifs-2.6.git / blob