drivers/gpu/drm/i915/i915_oa_sklgt2.c

   1 /*
   2  * Autogenerated file by GPU Top : https://github.com/rib/gputop
   3  * DO NOT EDIT manually!
   4  *
   5  *
   6  * Copyright (c) 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysfs.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_oa_sklgt2.h"
  33
  34 enum metric_set_id {
  35         METRIC_SET_ID_RENDER_BASIC = 1,
  36         METRIC_SET_ID_COMPUTE_BASIC,
  37         METRIC_SET_ID_RENDER_PIPE_PROFILE,
  38         METRIC_SET_ID_MEMORY_READS,
  39         METRIC_SET_ID_MEMORY_WRITES,
  40         METRIC_SET_ID_COMPUTE_EXTENDED,
  41         METRIC_SET_ID_COMPUTE_L3_CACHE,
  42         METRIC_SET_ID_HDC_AND_SF,
  43         METRIC_SET_ID_L3_1,
  44         METRIC_SET_ID_L3_2,
  45         METRIC_SET_ID_L3_3,
  46         METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
  47         METRIC_SET_ID_SAMPLER,
  48         METRIC_SET_ID_TDL_1,
  49         METRIC_SET_ID_TDL_2,
  50         METRIC_SET_ID_COMPUTE_EXTRA,
  51         METRIC_SET_ID_VME_PIPE,
  52         METRIC_SET_ID_TEST_OA,
  53 };
  54
  55 int i915_oa_n_builtin_metric_sets_sklgt2 = 18;
  56
  57 static const struct i915_oa_reg b_counter_config_render_basic[] = {
  58         { _MMIO(0x2710), 0x00000000 },
  59         { _MMIO(0x2714), 0x00800000 },
  60         { _MMIO(0x2720), 0x00000000 },
  61         { _MMIO(0x2724), 0x00800000 },
  62         { _MMIO(0x2740), 0x00000000 },
  63 };
  64
  65 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
  66         { _MMIO(0xe458), 0x00005004 },
  67         { _MMIO(0xe558), 0x00010003 },
  68         { _MMIO(0xe658), 0x00012011 },
  69         { _MMIO(0xe758), 0x00015014 },
  70         { _MMIO(0xe45c), 0x00051050 },
  71         { _MMIO(0xe55c), 0x00053052 },
  72         { _MMIO(0xe65c), 0x00055054 },
  73 };
  74
  75 static const struct i915_oa_reg mux_config_render_basic_1_sku_gte_0x02[] = {
  76         { _MMIO(0x9888), 0x166c01e0 },
  77         { _MMIO(0x9888), 0x12170280 },
  78         { _MMIO(0x9888), 0x12370280 },
  79         { _MMIO(0x9888), 0x11930317 },
  80         { _MMIO(0x9888), 0x159303df },
  81         { _MMIO(0x9888), 0x3f900003 },
  82         { _MMIO(0x9888), 0x1a4e0080 },
  83         { _MMIO(0x9888), 0x0a6c0053 },
  84         { _MMIO(0x9888), 0x106c0000 },
  85         { _MMIO(0x9888), 0x1c6c0000 },
  86         { _MMIO(0x9888), 0x0a1b4000 },
  87         { _MMIO(0x9888), 0x1c1c0001 },
  88         { _MMIO(0x9888), 0x002f1000 },
  89         { _MMIO(0x9888), 0x042f1000 },
  90         { _MMIO(0x9888), 0x004c4000 },
  91         { _MMIO(0x9888), 0x0a4c8400 },
  92         { _MMIO(0x9888), 0x000d2000 },
  93         { _MMIO(0x9888), 0x060d8000 },
  94         { _MMIO(0x9888), 0x080da000 },
  95         { _MMIO(0x9888), 0x0a0d2000 },
  96         { _MMIO(0x9888), 0x0c0f0400 },
  97         { _MMIO(0x9888), 0x0e0f6600 },
  98         { _MMIO(0x9888), 0x002c8000 },
  99         { _MMIO(0x9888), 0x162c2200 },
 100         { _MMIO(0x9888), 0x062d8000 },
 101         { _MMIO(0x9888), 0x082d8000 },
 102         { _MMIO(0x9888), 0x00133000 },
 103         { _MMIO(0x9888), 0x08133000 },
 104         { _MMIO(0x9888), 0x00170020 },
 105         { _MMIO(0x9888), 0x08170021 },
 106         { _MMIO(0x9888), 0x10170000 },
 107         { _MMIO(0x9888), 0x0633c000 },
 108         { _MMIO(0x9888), 0x0833c000 },
 109         { _MMIO(0x9888), 0x06370800 },
 110         { _MMIO(0x9888), 0x08370840 },
 111         { _MMIO(0x9888), 0x10370000 },
 112         { _MMIO(0x9888), 0x0d933031 },
 113         { _MMIO(0x9888), 0x0f933e3f },
 114         { _MMIO(0x9888), 0x01933d00 },
 115         { _MMIO(0x9888), 0x0393073c },
 116         { _MMIO(0x9888), 0x0593000e },
 117         { _MMIO(0x9888), 0x1d930000 },
 118         { _MMIO(0x9888), 0x19930000 },
 119         { _MMIO(0x9888), 0x1b930000 },
 120         { _MMIO(0x9888), 0x1d900157 },
 121         { _MMIO(0x9888), 0x1f900158 },
 122         { _MMIO(0x9888), 0x35900000 },
 123         { _MMIO(0x9888), 0x2b908000 },
 124         { _MMIO(0x9888), 0x2d908000 },
 125         { _MMIO(0x9888), 0x2f908000 },
 126         { _MMIO(0x9888), 0x31908000 },
 127         { _MMIO(0x9888), 0x15908000 },
 128         { _MMIO(0x9888), 0x17908000 },
 129         { _MMIO(0x9888), 0x19908000 },
 130         { _MMIO(0x9888), 0x1b908000 },
 131         { _MMIO(0x9888), 0x1190001f },
 132         { _MMIO(0x9888), 0x51904400 },
 133         { _MMIO(0x9888), 0x41900020 },
 134         { _MMIO(0x9888), 0x55900000 },
 135         { _MMIO(0x9888), 0x45900c21 },
 136         { _MMIO(0x9888), 0x47900061 },
 137         { _MMIO(0x9888), 0x57904440 },
 138         { _MMIO(0x9888), 0x49900000 },
 139         { _MMIO(0x9888), 0x37900000 },
 140         { _MMIO(0x9888), 0x33900000 },
 141         { _MMIO(0x9888), 0x4b900000 },
 142         { _MMIO(0x9888), 0x59900004 },
 143         { _MMIO(0x9888), 0x43900000 },
 144         { _MMIO(0x9888), 0x53904444 },
 145 };
 146
 147 static int
 148 get_render_basic_mux_config(struct drm_i915_private *dev_priv,
 149                             const struct i915_oa_reg **regs,
 150                             int *lens)
 151 {
 152         int n = 0;
 153
 154         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 155         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 156
 157         if (dev_priv->drm.pdev->revision >= 0x02) {
 158                 regs[n] = mux_config_render_basic_1_sku_gte_0x02;
 159                 lens[n] = ARRAY_SIZE(mux_config_render_basic_1_sku_gte_0x02);
 160                 n++;
 161         }
 162
 163         return n;
 164 }
 165
 166 static const struct i915_oa_reg b_counter_config_compute_basic[] = {
 167         { _MMIO(0x2710), 0x00000000 },
 168         { _MMIO(0x2714), 0x00800000 },
 169         { _MMIO(0x2720), 0x00000000 },
 170         { _MMIO(0x2724), 0x00800000 },
 171         { _MMIO(0x2740), 0x00000000 },
 172 };
 173
 174 static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
 175         { _MMIO(0xe458), 0x00005004 },
 176         { _MMIO(0xe558), 0x00000003 },
 177         { _MMIO(0xe658), 0x00002001 },
 178         { _MMIO(0xe758), 0x00778008 },
 179         { _MMIO(0xe45c), 0x00088078 },
 180         { _MMIO(0xe55c), 0x00808708 },
 181         { _MMIO(0xe65c), 0x00a08908 },
 182 };
 183
 184 static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02[] = {
 185         { _MMIO(0x9888), 0x104f00e0 },
 186         { _MMIO(0x9888), 0x124f1c00 },
 187         { _MMIO(0x9888), 0x106c00e0 },
 188         { _MMIO(0x9888), 0x37906800 },
 189         { _MMIO(0x9888), 0x3f901403 },
 190         { _MMIO(0x9888), 0x184e8000 },
 191         { _MMIO(0x9888), 0x1a4e8200 },
 192         { _MMIO(0x9888), 0x044e8000 },
 193         { _MMIO(0x9888), 0x004f0db2 },
 194         { _MMIO(0x9888), 0x064f0900 },
 195         { _MMIO(0x9888), 0x084f1880 },
 196         { _MMIO(0x9888), 0x0a4f0011 },
 197         { _MMIO(0x9888), 0x0c4f0e3c },
 198         { _MMIO(0x9888), 0x0e4f1d80 },
 199         { _MMIO(0x9888), 0x086c0002 },
 200         { _MMIO(0x9888), 0x0a6c0100 },
 201         { _MMIO(0x9888), 0x0e6c000c },
 202         { _MMIO(0x9888), 0x026c000b },
 203         { _MMIO(0x9888), 0x1c6c0000 },
 204         { _MMIO(0x9888), 0x1a6c0000 },
 205         { _MMIO(0x9888), 0x081b4000 },
 206         { _MMIO(0x9888), 0x0a1b8000 },
 207         { _MMIO(0x9888), 0x0e1b4000 },
 208         { _MMIO(0x9888), 0x021b4000 },
 209         { _MMIO(0x9888), 0x1a1c4000 },
 210         { _MMIO(0x9888), 0x1c1c0012 },
 211         { _MMIO(0x9888), 0x141c8000 },
 212         { _MMIO(0x9888), 0x005bc000 },
 213         { _MMIO(0x9888), 0x065b8000 },
 214         { _MMIO(0x9888), 0x085b8000 },
 215         { _MMIO(0x9888), 0x0a5b4000 },
 216         { _MMIO(0x9888), 0x0c5bc000 },
 217         { _MMIO(0x9888), 0x0e5b8000 },
 218         { _MMIO(0x9888), 0x105c8000 },
 219         { _MMIO(0x9888), 0x1a5ca000 },
 220         { _MMIO(0x9888), 0x1c5c002d },
 221         { _MMIO(0x9888), 0x125c8000 },
 222         { _MMIO(0x9888), 0x0a4c0800 },
 223         { _MMIO(0x9888), 0x0c4c0082 },
 224         { _MMIO(0x9888), 0x084c8000 },
 225         { _MMIO(0x9888), 0x000da000 },
 226         { _MMIO(0x9888), 0x060d8000 },
 227         { _MMIO(0x9888), 0x080da000 },
 228         { _MMIO(0x9888), 0x0a0da000 },
 229         { _MMIO(0x9888), 0x0c0da000 },
 230         { _MMIO(0x9888), 0x0e0da000 },
 231         { _MMIO(0x9888), 0x020d2000 },
 232         { _MMIO(0x9888), 0x0c0f5400 },
 233         { _MMIO(0x9888), 0x0e0f5500 },
 234         { _MMIO(0x9888), 0x100f0155 },
 235         { _MMIO(0x9888), 0x002cc000 },
 236         { _MMIO(0x9888), 0x0e2cc000 },
 237         { _MMIO(0x9888), 0x162cbe00 },
 238         { _MMIO(0x9888), 0x182c00ef },
 239         { _MMIO(0x9888), 0x022cc000 },
 240         { _MMIO(0x9888), 0x042c8000 },
 241         { _MMIO(0x9888), 0x19900157 },
 242         { _MMIO(0x9888), 0x1b900167 },
 243         { _MMIO(0x9888), 0x1d900105 },
 244         { _MMIO(0x9888), 0x1f900103 },
 245         { _MMIO(0x9888), 0x35900000 },
 246         { _MMIO(0xd28), 0x00000000 },
 247         { _MMIO(0x9888), 0x11900fff },
 248         { _MMIO(0x9888), 0x51900000 },
 249         { _MMIO(0x9888), 0x41900840 },
 250         { _MMIO(0x9888), 0x55900000 },
 251         { _MMIO(0x9888), 0x45900842 },
 252         { _MMIO(0x9888), 0x47900840 },
 253         { _MMIO(0x9888), 0x57900000 },
 254         { _MMIO(0x9888), 0x49900840 },
 255         { _MMIO(0x9888), 0x33900000 },
 256         { _MMIO(0x9888), 0x4b900040 },
 257         { _MMIO(0x9888), 0x59900000 },
 258         { _MMIO(0x9888), 0x43900840 },
 259         { _MMIO(0x9888), 0x53901111 },
 260 };
 261
 262 static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02[] = {
 263         { _MMIO(0x9888), 0x104f00e0 },
 264         { _MMIO(0x9888), 0x124f1c00 },
 265         { _MMIO(0x9888), 0x106c00e0 },
 266         { _MMIO(0x9888), 0x37906800 },
 267         { _MMIO(0x9888), 0x3f901403 },
 268         { _MMIO(0x9888), 0x004e8000 },
 269         { _MMIO(0x9888), 0x1a4e0820 },
 270         { _MMIO(0x9888), 0x1c4e0002 },
 271         { _MMIO(0x9888), 0x064f0900 },
 272         { _MMIO(0x9888), 0x084f0032 },
 273         { _MMIO(0x9888), 0x0a4f1810 },
 274         { _MMIO(0x9888), 0x0c4f0e00 },
 275         { _MMIO(0x9888), 0x0e4f003c },
 276         { _MMIO(0x9888), 0x004f0d80 },
 277         { _MMIO(0x9888), 0x024f003b },
 278         { _MMIO(0x9888), 0x006c0002 },
 279         { _MMIO(0x9888), 0x086c0000 },
 280         { _MMIO(0x9888), 0x0c6c000c },
 281         { _MMIO(0x9888), 0x0e6c0b00 },
 282         { _MMIO(0x9888), 0x186c0000 },
 283         { _MMIO(0x9888), 0x1c6c0000 },
 284         { _MMIO(0x9888), 0x1e6c0000 },
 285         { _MMIO(0x9888), 0x001b4000 },
 286         { _MMIO(0x9888), 0x081b8000 },
 287         { _MMIO(0x9888), 0x0c1b4000 },
 288         { _MMIO(0x9888), 0x0e1b8000 },
 289         { _MMIO(0x9888), 0x101c8000 },
 290         { _MMIO(0x9888), 0x1a1c8000 },
 291         { _MMIO(0x9888), 0x1c1c0024 },
 292         { _MMIO(0x9888), 0x065b8000 },
 293         { _MMIO(0x9888), 0x085b4000 },
 294         { _MMIO(0x9888), 0x0a5bc000 },
 295         { _MMIO(0x9888), 0x0c5b8000 },
 296         { _MMIO(0x9888), 0x0e5b4000 },
 297         { _MMIO(0x9888), 0x005b8000 },
 298         { _MMIO(0x9888), 0x025b4000 },
 299         { _MMIO(0x9888), 0x1a5c6000 },
 300         { _MMIO(0x9888), 0x1c5c001b },
 301         { _MMIO(0x9888), 0x125c8000 },
 302         { _MMIO(0x9888), 0x145c8000 },
 303         { _MMIO(0x9888), 0x004c8000 },
 304         { _MMIO(0x9888), 0x0a4c2000 },
 305         { _MMIO(0x9888), 0x0c4c0208 },
 306         { _MMIO(0x9888), 0x000da000 },
 307         { _MMIO(0x9888), 0x060d8000 },
 308         { _MMIO(0x9888), 0x080da000 },
 309         { _MMIO(0x9888), 0x0a0da000 },
 310         { _MMIO(0x9888), 0x0c0da000 },
 311         { _MMIO(0x9888), 0x0e0da000 },
 312         { _MMIO(0x9888), 0x020d2000 },
 313         { _MMIO(0x9888), 0x0c0f5400 },
 314         { _MMIO(0x9888), 0x0e0f5500 },
 315         { _MMIO(0x9888), 0x100f0155 },
 316         { _MMIO(0x9888), 0x002c8000 },
 317         { _MMIO(0x9888), 0x0e2cc000 },
 318         { _MMIO(0x9888), 0x162cfb00 },
 319         { _MMIO(0x9888), 0x182c00be },
 320         { _MMIO(0x9888), 0x022cc000 },
 321         { _MMIO(0x9888), 0x042cc000 },
 322         { _MMIO(0x9888), 0x19900157 },
 323         { _MMIO(0x9888), 0x1b900167 },
 324         { _MMIO(0x9888), 0x1d900105 },
 325         { _MMIO(0x9888), 0x1f900103 },
 326         { _MMIO(0x9888), 0x35900000 },
 327         { _MMIO(0x9888), 0x11900fff },
 328         { _MMIO(0x9888), 0x51900000 },
 329         { _MMIO(0x9888), 0x41900800 },
 330         { _MMIO(0x9888), 0x55900000 },
 331         { _MMIO(0x9888), 0x45900842 },
 332         { _MMIO(0x9888), 0x47900802 },
 333         { _MMIO(0x9888), 0x57900000 },
 334         { _MMIO(0x9888), 0x49900802 },
 335         { _MMIO(0x9888), 0x33900000 },
 336         { _MMIO(0x9888), 0x4b900002 },
 337         { _MMIO(0x9888), 0x59900000 },
 338         { _MMIO(0x9888), 0x43900842 },
 339         { _MMIO(0x9888), 0x53901111 },
 340 };
 341
 342 static int
 343 get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
 344                              const struct i915_oa_reg **regs,
 345                              int *lens)
 346 {
 347         int n = 0;
 348
 349         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
 350         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
 351
 352         if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
 353             (dev_priv->drm.pdev->revision < 0x02)) {
 354                 regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02;
 355                 lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02);
 356                 n++;
 357         }
 358         if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
 359                    (dev_priv->drm.pdev->revision >= 0x02)) {
 360                 regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02;
 361                 lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02);
 362                 n++;
 363         }
 364
 365         return n;
 366 }
 367
 368 static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
 369         { _MMIO(0x2724), 0xf0800000 },
 370         { _MMIO(0x2720), 0x00000000 },
 371         { _MMIO(0x2714), 0xf0800000 },
 372         { _MMIO(0x2710), 0x00000000 },
 373         { _MMIO(0x2740), 0x00000000 },
 374         { _MMIO(0x2770), 0x0007ffea },
 375         { _MMIO(0x2774), 0x00007ffc },
 376         { _MMIO(0x2778), 0x0007affa },
 377         { _MMIO(0x277c), 0x0000f5fd },
 378         { _MMIO(0x2780), 0x00079ffa },
 379         { _MMIO(0x2784), 0x0000f3fb },
 380         { _MMIO(0x2788), 0x0007bf7a },
 381         { _MMIO(0x278c), 0x0000f7e7 },
 382         { _MMIO(0x2790), 0x0007fefa },
 383         { _MMIO(0x2794), 0x0000f7cf },
 384         { _MMIO(0x2798), 0x00077ffa },
 385         { _MMIO(0x279c), 0x0000efdf },
 386         { _MMIO(0x27a0), 0x0006fffa },
 387         { _MMIO(0x27a4), 0x0000cfbf },
 388         { _MMIO(0x27a8), 0x0003fffa },
 389         { _MMIO(0x27ac), 0x00005f7f },
 390 };
 391
 392 static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
 393         { _MMIO(0xe458), 0x00005004 },
 394         { _MMIO(0xe558), 0x00015014 },
 395         { _MMIO(0xe658), 0x00025024 },
 396         { _MMIO(0xe758), 0x00035034 },
 397         { _MMIO(0xe45c), 0x00045044 },
 398         { _MMIO(0xe55c), 0x00055054 },
 399         { _MMIO(0xe65c), 0x00065064 },
 400 };
 401
 402 static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_lt_0x02[] = {
 403         { _MMIO(0x9888), 0x0c0e001f },
 404         { _MMIO(0x9888), 0x0a0f0000 },
 405         { _MMIO(0x9888), 0x10116800 },
 406         { _MMIO(0x9888), 0x178a03e0 },
 407         { _MMIO(0x9888), 0x11824c00 },
 408         { _MMIO(0x9888), 0x11830020 },
 409         { _MMIO(0x9888), 0x13840020 },
 410         { _MMIO(0x9888), 0x11850019 },
 411         { _MMIO(0x9888), 0x11860007 },
 412         { _MMIO(0x9888), 0x01870c40 },
 413         { _MMIO(0x9888), 0x17880000 },
 414         { _MMIO(0x9888), 0x022f4000 },
 415         { _MMIO(0x9888), 0x0a4c0040 },
 416         { _MMIO(0x9888), 0x0c0d8000 },
 417         { _MMIO(0x9888), 0x040d4000 },
 418         { _MMIO(0x9888), 0x060d2000 },
 419         { _MMIO(0x9888), 0x020e5400 },
 420         { _MMIO(0x9888), 0x000e0000 },
 421         { _MMIO(0x9888), 0x080f0040 },
 422         { _MMIO(0x9888), 0x000f0000 },
 423         { _MMIO(0x9888), 0x100f0000 },
 424         { _MMIO(0x9888), 0x0e0f0040 },
 425         { _MMIO(0x9888), 0x0c2c8000 },
 426         { _MMIO(0x9888), 0x06104000 },
 427         { _MMIO(0x9888), 0x06110012 },
 428         { _MMIO(0x9888), 0x06131000 },
 429         { _MMIO(0x9888), 0x01898000 },
 430         { _MMIO(0x9888), 0x0d890100 },
 431         { _MMIO(0x9888), 0x03898000 },
 432         { _MMIO(0x9888), 0x09808000 },
 433         { _MMIO(0x9888), 0x0b808000 },
 434         { _MMIO(0x9888), 0x0380c000 },
 435         { _MMIO(0x9888), 0x0f8a0075 },
 436         { _MMIO(0x9888), 0x1d8a0000 },
 437         { _MMIO(0x9888), 0x118a8000 },
 438         { _MMIO(0x9888), 0x1b8a4000 },
 439         { _MMIO(0x9888), 0x138a8000 },
 440         { _MMIO(0x9888), 0x1d81a000 },
 441         { _MMIO(0x9888), 0x15818000 },
 442         { _MMIO(0x9888), 0x17818000 },
 443         { _MMIO(0x9888), 0x0b820030 },
 444         { _MMIO(0x9888), 0x07828000 },
 445         { _MMIO(0x9888), 0x0d824000 },
 446         { _MMIO(0x9888), 0x0f828000 },
 447         { _MMIO(0x9888), 0x05824000 },
 448         { _MMIO(0x9888), 0x0d830003 },
 449         { _MMIO(0x9888), 0x0583000c },
 450         { _MMIO(0x9888), 0x09830000 },
 451         { _MMIO(0x9888), 0x03838000 },
 452         { _MMIO(0x9888), 0x07838000 },
 453         { _MMIO(0x9888), 0x0b840980 },
 454         { _MMIO(0x9888), 0x03844d80 },
 455         { _MMIO(0x9888), 0x11840000 },
 456         { _MMIO(0x9888), 0x09848000 },
 457         { _MMIO(0x9888), 0x09850080 },
 458         { _MMIO(0x9888), 0x03850003 },
 459         { _MMIO(0x9888), 0x01850000 },
 460         { _MMIO(0x9888), 0x07860000 },
 461         { _MMIO(0x9888), 0x0f860400 },
 462         { _MMIO(0x9888), 0x09870032 },
 463         { _MMIO(0x9888), 0x01888052 },
 464         { _MMIO(0x9888), 0x11880000 },
 465         { _MMIO(0x9888), 0x09884000 },
 466         { _MMIO(0x9888), 0x15968000 },
 467         { _MMIO(0x9888), 0x17968000 },
 468         { _MMIO(0x9888), 0x0f96c000 },
 469         { _MMIO(0x9888), 0x1f950011 },
 470         { _MMIO(0x9888), 0x1d950014 },
 471         { _MMIO(0x9888), 0x0592c000 },
 472         { _MMIO(0x9888), 0x0b928000 },
 473         { _MMIO(0x9888), 0x0d924000 },
 474         { _MMIO(0x9888), 0x0f924000 },
 475         { _MMIO(0x9888), 0x11928000 },
 476         { _MMIO(0x9888), 0x1392c000 },
 477         { _MMIO(0x9888), 0x09924000 },
 478         { _MMIO(0x9888), 0x01985000 },
 479         { _MMIO(0x9888), 0x07988000 },
 480         { _MMIO(0x9888), 0x09981000 },
 481         { _MMIO(0x9888), 0x0b982000 },
 482         { _MMIO(0x9888), 0x0d982000 },
 483         { _MMIO(0x9888), 0x0f989000 },
 484         { _MMIO(0x9888), 0x05982000 },
 485         { _MMIO(0x9888), 0x13904000 },
 486         { _MMIO(0x9888), 0x21904000 },
 487         { _MMIO(0x9888), 0x23904000 },
 488         { _MMIO(0x9888), 0x25908000 },
 489         { _MMIO(0x9888), 0x27904000 },
 490         { _MMIO(0x9888), 0x29908000 },
 491         { _MMIO(0x9888), 0x2b904000 },
 492         { _MMIO(0x9888), 0x2f904000 },
 493         { _MMIO(0x9888), 0x31904000 },
 494         { _MMIO(0x9888), 0x15904000 },
 495         { _MMIO(0x9888), 0x17908000 },
 496         { _MMIO(0x9888), 0x19908000 },
 497         { _MMIO(0x9888), 0x1b904000 },
 498         { _MMIO(0x9888), 0x0b978000 },
 499         { _MMIO(0x9888), 0x0f974000 },
 500         { _MMIO(0x9888), 0x11974000 },
 501         { _MMIO(0x9888), 0x13978000 },
 502         { _MMIO(0x9888), 0x09974000 },
 503         { _MMIO(0xd28), 0x00000000 },
 504         { _MMIO(0x9888), 0x1190c080 },
 505         { _MMIO(0x9888), 0x51900000 },
 506         { _MMIO(0x9888), 0x419010a0 },
 507         { _MMIO(0x9888), 0x55904000 },
 508         { _MMIO(0x9888), 0x45901000 },
 509         { _MMIO(0x9888), 0x47900084 },
 510         { _MMIO(0x9888), 0x57904400 },
 511         { _MMIO(0x9888), 0x499000a5 },
 512         { _MMIO(0x9888), 0x37900000 },
 513         { _MMIO(0x9888), 0x33900000 },
 514         { _MMIO(0x9888), 0x4b900081 },
 515         { _MMIO(0x9888), 0x59900000 },
 516         { _MMIO(0x9888), 0x439014a4 },
 517         { _MMIO(0x9888), 0x53900400 },
 518 };
 519
 520 static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_gte_0x02[] = {
 521         { _MMIO(0x9888), 0x0c0e001f },
 522         { _MMIO(0x9888), 0x0a0f0000 },
 523         { _MMIO(0x9888), 0x10116800 },
 524         { _MMIO(0x9888), 0x178a03e0 },
 525         { _MMIO(0x9888), 0x11824c00 },
 526         { _MMIO(0x9888), 0x11830020 },
 527         { _MMIO(0x9888), 0x13840020 },
 528         { _MMIO(0x9888), 0x11850019 },
 529         { _MMIO(0x9888), 0x11860007 },
 530         { _MMIO(0x9888), 0x01870c40 },
 531         { _MMIO(0x9888), 0x17880000 },
 532         { _MMIO(0x9888), 0x022f4000 },
 533         { _MMIO(0x9888), 0x0a4c0040 },
 534         { _MMIO(0x9888), 0x0c0d8000 },
 535         { _MMIO(0x9888), 0x040d4000 },
 536         { _MMIO(0x9888), 0x060d2000 },
 537         { _MMIO(0x9888), 0x020e5400 },
 538         { _MMIO(0x9888), 0x000e0000 },
 539         { _MMIO(0x9888), 0x080f0040 },
 540         { _MMIO(0x9888), 0x000f0000 },
 541         { _MMIO(0x9888), 0x100f0000 },
 542         { _MMIO(0x9888), 0x0e0f0040 },
 543         { _MMIO(0x9888), 0x0c2c8000 },
 544         { _MMIO(0x9888), 0x06104000 },
 545         { _MMIO(0x9888), 0x06110012 },
 546         { _MMIO(0x9888), 0x06131000 },
 547         { _MMIO(0x9888), 0x01898000 },
 548         { _MMIO(0x9888), 0x0d890100 },
 549         { _MMIO(0x9888), 0x03898000 },
 550         { _MMIO(0x9888), 0x09808000 },
 551         { _MMIO(0x9888), 0x0b808000 },
 552         { _MMIO(0x9888), 0x0380c000 },
 553         { _MMIO(0x9888), 0x0f8a0075 },
 554         { _MMIO(0x9888), 0x1d8a0000 },
 555         { _MMIO(0x9888), 0x118a8000 },
 556         { _MMIO(0x9888), 0x1b8a4000 },
 557         { _MMIO(0x9888), 0x138a8000 },
 558         { _MMIO(0x9888), 0x1d81a000 },
 559         { _MMIO(0x9888), 0x15818000 },
 560         { _MMIO(0x9888), 0x17818000 },
 561         { _MMIO(0x9888), 0x0b820030 },
 562         { _MMIO(0x9888), 0x07828000 },
 563         { _MMIO(0x9888), 0x0d824000 },
 564         { _MMIO(0x9888), 0x0f828000 },
 565         { _MMIO(0x9888), 0x05824000 },
 566         { _MMIO(0x9888), 0x0d830003 },
 567         { _MMIO(0x9888), 0x0583000c },
 568         { _MMIO(0x9888), 0x09830000 },
 569         { _MMIO(0x9888), 0x03838000 },
 570         { _MMIO(0x9888), 0x07838000 },
 571         { _MMIO(0x9888), 0x0b840980 },
 572         { _MMIO(0x9888), 0x03844d80 },
 573         { _MMIO(0x9888), 0x11840000 },
 574         { _MMIO(0x9888), 0x09848000 },
 575         { _MMIO(0x9888), 0x09850080 },
 576         { _MMIO(0x9888), 0x03850003 },
 577         { _MMIO(0x9888), 0x01850000 },
 578         { _MMIO(0x9888), 0x07860000 },
 579         { _MMIO(0x9888), 0x0f860400 },
 580         { _MMIO(0x9888), 0x09870032 },
 581         { _MMIO(0x9888), 0x01888052 },
 582         { _MMIO(0x9888), 0x11880000 },
 583         { _MMIO(0x9888), 0x09884000 },
 584         { _MMIO(0x9888), 0x1b931001 },
 585         { _MMIO(0x9888), 0x1d930001 },
 586         { _MMIO(0x9888), 0x19934000 },
 587         { _MMIO(0x9888), 0x1b958000 },
 588         { _MMIO(0x9888), 0x1d950094 },
 589         { _MMIO(0x9888), 0x19958000 },
 590         { _MMIO(0x9888), 0x05e5a000 },
 591         { _MMIO(0x9888), 0x01e5c000 },
 592         { _MMIO(0x9888), 0x0592c000 },
 593         { _MMIO(0x9888), 0x0b928000 },
 594         { _MMIO(0x9888), 0x0d924000 },
 595         { _MMIO(0x9888), 0x0f924000 },
 596         { _MMIO(0x9888), 0x11928000 },
 597         { _MMIO(0x9888), 0x1392c000 },
 598         { _MMIO(0x9888), 0x09924000 },
 599         { _MMIO(0x9888), 0x01985000 },
 600         { _MMIO(0x9888), 0x07988000 },
 601         { _MMIO(0x9888), 0x09981000 },
 602         { _MMIO(0x9888), 0x0b982000 },
 603         { _MMIO(0x9888), 0x0d982000 },
 604         { _MMIO(0x9888), 0x0f989000 },
 605         { _MMIO(0x9888), 0x05982000 },
 606         { _MMIO(0x9888), 0x13904000 },
 607         { _MMIO(0x9888), 0x21904000 },
 608         { _MMIO(0x9888), 0x23904000 },
 609         { _MMIO(0x9888), 0x25908000 },
 610         { _MMIO(0x9888), 0x27904000 },
 611         { _MMIO(0x9888), 0x29908000 },
 612         { _MMIO(0x9888), 0x2b904000 },
 613         { _MMIO(0x9888), 0x2f904000 },
 614         { _MMIO(0x9888), 0x31904000 },
 615         { _MMIO(0x9888), 0x15904000 },
 616         { _MMIO(0x9888), 0x17908000 },
 617         { _MMIO(0x9888), 0x19908000 },
 618         { _MMIO(0x9888), 0x1b904000 },
 619         { _MMIO(0x9888), 0x1190c080 },
 620         { _MMIO(0x9888), 0x51900000 },
 621         { _MMIO(0x9888), 0x419010a0 },
 622         { _MMIO(0x9888), 0x55904000 },
 623         { _MMIO(0x9888), 0x45901000 },
 624         { _MMIO(0x9888), 0x47900084 },
 625         { _MMIO(0x9888), 0x57904400 },
 626         { _MMIO(0x9888), 0x499000a5 },
 627         { _MMIO(0x9888), 0x37900000 },
 628         { _MMIO(0x9888), 0x33900000 },
 629         { _MMIO(0x9888), 0x4b900081 },
 630         { _MMIO(0x9888), 0x59900000 },
 631         { _MMIO(0x9888), 0x439014a4 },
 632         { _MMIO(0x9888), 0x53900400 },
 633 };
 634
 635 static int
 636 get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
 637                                    const struct i915_oa_reg **regs,
 638                                    int *lens)
 639 {
 640         int n = 0;
 641
 642         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
 643         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
 644
 645         if (dev_priv->drm.pdev->revision < 0x02) {
 646                 regs[n] = mux_config_render_pipe_profile_0_sku_lt_0x02;
 647                 lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_lt_0x02);
 648                 n++;
 649         }
 650         if (dev_priv->drm.pdev->revision >= 0x02) {
 651                 regs[n] = mux_config_render_pipe_profile_0_sku_gte_0x02;
 652                 lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_gte_0x02);
 653                 n++;
 654         }
 655
 656         return n;
 657 }
 658
 659 static const struct i915_oa_reg b_counter_config_memory_reads[] = {
 660         { _MMIO(0x272c), 0xffffffff },
 661         { _MMIO(0x2728), 0xffffffff },
 662         { _MMIO(0x2724), 0xf0800000 },
 663         { _MMIO(0x2720), 0x00000000 },
 664         { _MMIO(0x271c), 0xffffffff },
 665         { _MMIO(0x2718), 0xffffffff },
 666         { _MMIO(0x2714), 0xf0800000 },
 667         { _MMIO(0x2710), 0x00000000 },
 668         { _MMIO(0x274c), 0x86543210 },
 669         { _MMIO(0x2748), 0x86543210 },
 670         { _MMIO(0x2744), 0x00006667 },
 671         { _MMIO(0x2740), 0x00000000 },
 672         { _MMIO(0x275c), 0x86543210 },
 673         { _MMIO(0x2758), 0x86543210 },
 674         { _MMIO(0x2754), 0x00006465 },
 675         { _MMIO(0x2750), 0x00000000 },
 676         { _MMIO(0x2770), 0x0007f81a },
 677         { _MMIO(0x2774), 0x0000fe00 },
 678         { _MMIO(0x2778), 0x0007f82a },
 679         { _MMIO(0x277c), 0x0000fe00 },
 680         { _MMIO(0x2780), 0x0007f872 },
 681         { _MMIO(0x2784), 0x0000fe00 },
 682         { _MMIO(0x2788), 0x0007f8ba },
 683         { _MMIO(0x278c), 0x0000fe00 },
 684         { _MMIO(0x2790), 0x0007f87a },
 685         { _MMIO(0x2794), 0x0000fe00 },
 686         { _MMIO(0x2798), 0x0007f8ea },
 687         { _MMIO(0x279c), 0x0000fe00 },
 688         { _MMIO(0x27a0), 0x0007f8e2 },
 689         { _MMIO(0x27a4), 0x0000fe00 },
 690         { _MMIO(0x27a8), 0x0007f8f2 },
 691         { _MMIO(0x27ac), 0x0000fe00 },
 692 };
 693
 694 static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
 695         { _MMIO(0xe458), 0x00005004 },
 696         { _MMIO(0xe558), 0x00015014 },
 697         { _MMIO(0xe658), 0x00025024 },
 698         { _MMIO(0xe758), 0x00035034 },
 699         { _MMIO(0xe45c), 0x00045044 },
 700         { _MMIO(0xe55c), 0x00055054 },
 701         { _MMIO(0xe65c), 0x00065064 },
 702 };
 703
 704 static const struct i915_oa_reg mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02[] = {
 705         { _MMIO(0x9888), 0x11810c00 },
 706         { _MMIO(0x9888), 0x1381001a },
 707         { _MMIO(0x9888), 0x13946000 },
 708         { _MMIO(0x9888), 0x37906800 },
 709         { _MMIO(0x9888), 0x3f900003 },
 710         { _MMIO(0x9888), 0x03811300 },
 711         { _MMIO(0x9888), 0x05811b12 },
 712         { _MMIO(0x9888), 0x0781001a },
 713         { _MMIO(0x9888), 0x1f810000 },
 714         { _MMIO(0x9888), 0x17810000 },
 715         { _MMIO(0x9888), 0x19810000 },
 716         { _MMIO(0x9888), 0x1b810000 },
 717         { _MMIO(0x9888), 0x1d810000 },
 718         { _MMIO(0x9888), 0x0f968000 },
 719         { _MMIO(0x9888), 0x1196c000 },
 720         { _MMIO(0x9888), 0x13964000 },
 721         { _MMIO(0x9888), 0x11938000 },
 722         { _MMIO(0x9888), 0x1b93fe00 },
 723         { _MMIO(0x9888), 0x01940010 },
 724         { _MMIO(0x9888), 0x07941100 },
 725         { _MMIO(0x9888), 0x09941312 },
 726         { _MMIO(0x9888), 0x0b941514 },
 727         { _MMIO(0x9888), 0x0d941716 },
 728         { _MMIO(0x9888), 0x11940000 },
 729         { _MMIO(0x9888), 0x19940000 },
 730         { _MMIO(0x9888), 0x1b940000 },
 731         { _MMIO(0x9888), 0x1d940000 },
 732         { _MMIO(0x9888), 0x1b954000 },
 733         { _MMIO(0x9888), 0x1d95a550 },
 734         { _MMIO(0x9888), 0x1f9502aa },
 735         { _MMIO(0x9888), 0x2f900157 },
 736         { _MMIO(0x9888), 0x31900105 },
 737         { _MMIO(0x9888), 0x15900103 },
 738         { _MMIO(0x9888), 0x17900101 },
 739         { _MMIO(0x9888), 0x35900000 },
 740         { _MMIO(0x9888), 0x13908000 },
 741         { _MMIO(0x9888), 0x21908000 },
 742         { _MMIO(0x9888), 0x23908000 },
 743         { _MMIO(0x9888), 0x25908000 },
 744         { _MMIO(0x9888), 0x27908000 },
 745         { _MMIO(0x9888), 0x29908000 },
 746         { _MMIO(0x9888), 0x2b908000 },
 747         { _MMIO(0x9888), 0x2d908000 },
 748         { _MMIO(0x9888), 0x19908000 },
 749         { _MMIO(0x9888), 0x1b908000 },
 750         { _MMIO(0x9888), 0x1d908000 },
 751         { _MMIO(0x9888), 0x1f908000 },
 752         { _MMIO(0xd28), 0x00000000 },
 753         { _MMIO(0x9888), 0x11900000 },
 754         { _MMIO(0x9888), 0x51900000 },
 755         { _MMIO(0x9888), 0x41900c00 },
 756         { _MMIO(0x9888), 0x55900000 },
 757         { _MMIO(0x9888), 0x45900000 },
 758         { _MMIO(0x9888), 0x47900000 },
 759         { _MMIO(0x9888), 0x57900000 },
 760         { _MMIO(0x9888), 0x49900000 },
 761         { _MMIO(0x9888), 0x33900000 },
 762         { _MMIO(0x9888), 0x4b900063 },
 763         { _MMIO(0x9888), 0x59900000 },
 764         { _MMIO(0x9888), 0x43900003 },
 765         { _MMIO(0x9888), 0x53900000 },
 766 };
 767
 768 static const struct i915_oa_reg mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02[] = {
 769         { _MMIO(0x9888), 0x11810c00 },
 770         { _MMIO(0x9888), 0x1381001a },
 771         { _MMIO(0x9888), 0x13946000 },
 772         { _MMIO(0x9888), 0x15940016 },
 773         { _MMIO(0x9888), 0x37906800 },
 774         { _MMIO(0x9888), 0x03811300 },
 775         { _MMIO(0x9888), 0x05811b12 },
 776         { _MMIO(0x9888), 0x0781001a },
 777         { _MMIO(0x9888), 0x1f810000 },
 778         { _MMIO(0x9888), 0x17810000 },
 779         { _MMIO(0x9888), 0x19810000 },
 780         { _MMIO(0x9888), 0x1b810000 },
 781         { _MMIO(0x9888), 0x1d810000 },
 782         { _MMIO(0x9888), 0x19930800 },
 783         { _MMIO(0x9888), 0x1b93aa55 },
 784         { _MMIO(0x9888), 0x1d9300aa },
 785         { _MMIO(0x9888), 0x01940010 },
 786         { _MMIO(0x9888), 0x07941100 },
 787         { _MMIO(0x9888), 0x09941312 },
 788         { _MMIO(0x9888), 0x0b941514 },
 789         { _MMIO(0x9888), 0x0d941716 },
 790         { _MMIO(0x9888), 0x0f940018 },
 791         { _MMIO(0x9888), 0x1b940000 },
 792         { _MMIO(0x9888), 0x11940000 },
 793         { _MMIO(0x9888), 0x01e58000 },
 794         { _MMIO(0x9888), 0x03e57000 },
 795         { _MMIO(0x9888), 0x31900105 },
 796         { _MMIO(0x9888), 0x15900103 },
 797         { _MMIO(0x9888), 0x17900101 },
 798         { _MMIO(0x9888), 0x35900000 },
 799         { _MMIO(0x9888), 0x13908000 },
 800         { _MMIO(0x9888), 0x21908000 },
 801         { _MMIO(0x9888), 0x23908000 },
 802         { _MMIO(0x9888), 0x25908000 },
 803         { _MMIO(0x9888), 0x27908000 },
 804         { _MMIO(0x9888), 0x29908000 },
 805         { _MMIO(0x9888), 0x2b908000 },
 806         { _MMIO(0x9888), 0x2d908000 },
 807         { _MMIO(0x9888), 0x2f908000 },
 808         { _MMIO(0x9888), 0x19908000 },
 809         { _MMIO(0x9888), 0x1b908000 },
 810         { _MMIO(0x9888), 0x1d908000 },
 811         { _MMIO(0x9888), 0x1f908000 },
 812         { _MMIO(0x9888), 0x11900000 },
 813         { _MMIO(0x9888), 0x51900000 },
 814         { _MMIO(0x9888), 0x41900c20 },
 815         { _MMIO(0x9888), 0x55900000 },
 816         { _MMIO(0x9888), 0x45900400 },
 817         { _MMIO(0x9888), 0x47900421 },
 818         { _MMIO(0x9888), 0x57900000 },
 819         { _MMIO(0x9888), 0x49900421 },
 820         { _MMIO(0x9888), 0x33900000 },
 821         { _MMIO(0x9888), 0x4b900061 },
 822         { _MMIO(0x9888), 0x59900000 },
 823         { _MMIO(0x9888), 0x43900003 },
 824         { _MMIO(0x9888), 0x53900000 },
 825 };
 826
 827 static const struct i915_oa_reg mux_config_memory_reads_0_sku_gte_0x05[] = {
 828         { _MMIO(0x9888), 0x11810c00 },
 829         { _MMIO(0x9888), 0x1381001a },
 830         { _MMIO(0x9888), 0x37906800 },
 831         { _MMIO(0x9888), 0x3f900064 },
 832         { _MMIO(0x9888), 0x03811300 },
 833         { _MMIO(0x9888), 0x05811b12 },
 834         { _MMIO(0x9888), 0x0781001a },
 835         { _MMIO(0x9888), 0x1f810000 },
 836         { _MMIO(0x9888), 0x17810000 },
 837         { _MMIO(0x9888), 0x19810000 },
 838         { _MMIO(0x9888), 0x1b810000 },
 839         { _MMIO(0x9888), 0x1d810000 },
 840         { _MMIO(0x9888), 0x1b930055 },
 841         { _MMIO(0x9888), 0x03e58000 },
 842         { _MMIO(0x9888), 0x05e5c000 },
 843         { _MMIO(0x9888), 0x07e54000 },
 844         { _MMIO(0x9888), 0x13900150 },
 845         { _MMIO(0x9888), 0x21900151 },
 846         { _MMIO(0x9888), 0x23900152 },
 847         { _MMIO(0x9888), 0x25900153 },
 848         { _MMIO(0x9888), 0x27900154 },
 849         { _MMIO(0x9888), 0x29900155 },
 850         { _MMIO(0x9888), 0x2b900156 },
 851         { _MMIO(0x9888), 0x2d900157 },
 852         { _MMIO(0x9888), 0x2f90015f },
 853         { _MMIO(0x9888), 0x31900105 },
 854         { _MMIO(0x9888), 0x15900103 },
 855         { _MMIO(0x9888), 0x17900101 },
 856         { _MMIO(0x9888), 0x35900000 },
 857         { _MMIO(0x9888), 0x19908000 },
 858         { _MMIO(0x9888), 0x1b908000 },
 859         { _MMIO(0x9888), 0x1d908000 },
 860         { _MMIO(0x9888), 0x1f908000 },
 861         { _MMIO(0x9888), 0x11900000 },
 862         { _MMIO(0x9888), 0x51900000 },
 863         { _MMIO(0x9888), 0x41900c60 },
 864         { _MMIO(0x9888), 0x55900000 },
 865         { _MMIO(0x9888), 0x45900c00 },
 866         { _MMIO(0x9888), 0x47900c63 },
 867         { _MMIO(0x9888), 0x57900000 },
 868         { _MMIO(0x9888), 0x49900c63 },
 869         { _MMIO(0x9888), 0x33900000 },
 870         { _MMIO(0x9888), 0x4b900063 },
 871         { _MMIO(0x9888), 0x59900000 },
 872         { _MMIO(0x9888), 0x43900003 },
 873         { _MMIO(0x9888), 0x53900000 },
 874 };
 875
 876 static int
 877 get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
 878                             const struct i915_oa_reg **regs,
 879                             int *lens)
 880 {
 881         int n = 0;
 882
 883         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3);
 884         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3);
 885
 886         if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
 887             (dev_priv->drm.pdev->revision < 0x02)) {
 888                 regs[n] = mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02;
 889                 lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02);
 890                 n++;
 891         }
 892         if ((dev_priv->drm.pdev->revision < 0x05) &&
 893                    (dev_priv->drm.pdev->revision >= 0x02)) {
 894                 regs[n] = mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02;
 895                 lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02);
 896                 n++;
 897         }
 898         if (dev_priv->drm.pdev->revision >= 0x05) {
 899                 regs[n] = mux_config_memory_reads_0_sku_gte_0x05;
 900                 lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_gte_0x05);
 901                 n++;
 902         }
 903
 904         return n;
 905 }
 906
 907 static const struct i915_oa_reg b_counter_config_memory_writes[] = {
 908         { _MMIO(0x272c), 0xffffffff },
 909         { _MMIO(0x2728), 0xffffffff },
 910         { _MMIO(0x2724), 0xf0800000 },
 911         { _MMIO(0x2720), 0x00000000 },
 912         { _MMIO(0x271c), 0xffffffff },
 913         { _MMIO(0x2718), 0xffffffff },
 914         { _MMIO(0x2714), 0xf0800000 },
 915         { _MMIO(0x2710), 0x00000000 },
 916         { _MMIO(0x274c), 0x86543210 },
 917         { _MMIO(0x2748), 0x86543210 },
 918         { _MMIO(0x2744), 0x00006667 },
 919         { _MMIO(0x2740), 0x00000000 },
 920         { _MMIO(0x275c), 0x86543210 },
 921         { _MMIO(0x2758), 0x86543210 },
 922         { _MMIO(0x2754), 0x00006465 },
 923         { _MMIO(0x2750), 0x00000000 },
 924         { _MMIO(0x2770), 0x0007f81a },
 925         { _MMIO(0x2774), 0x0000fe00 },
 926         { _MMIO(0x2778), 0x0007f82a },
 927         { _MMIO(0x277c), 0x0000fe00 },
 928         { _MMIO(0x2780), 0x0007f822 },
 929         { _MMIO(0x2784), 0x0000fe00 },
 930         { _MMIO(0x2788), 0x0007f8ba },
 931         { _MMIO(0x278c), 0x0000fe00 },
 932         { _MMIO(0x2790), 0x0007f87a },
 933         { _MMIO(0x2794), 0x0000fe00 },
 934         { _MMIO(0x2798), 0x0007f8ea },
 935         { _MMIO(0x279c), 0x0000fe00 },
 936         { _MMIO(0x27a0), 0x0007f8e2 },
 937         { _MMIO(0x27a4), 0x0000fe00 },
 938         { _MMIO(0x27a8), 0x0007f8f2 },
 939         { _MMIO(0x27ac), 0x0000fe00 },
 940 };
 941
 942 static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
 943         { _MMIO(0xe458), 0x00005004 },
 944         { _MMIO(0xe558), 0x00015014 },
 945         { _MMIO(0xe658), 0x00025024 },
 946         { _MMIO(0xe758), 0x00035034 },
 947         { _MMIO(0xe45c), 0x00045044 },
 948         { _MMIO(0xe55c), 0x00055054 },
 949         { _MMIO(0xe65c), 0x00065064 },
 950 };
 951
 952 static const struct i915_oa_reg mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02[] = {
 953         { _MMIO(0x9888), 0x11810c00 },
 954         { _MMIO(0x9888), 0x1381001a },
 955         { _MMIO(0x9888), 0x13945400 },
 956         { _MMIO(0x9888), 0x37906800 },
 957         { _MMIO(0x9888), 0x3f901400 },
 958         { _MMIO(0x9888), 0x03811300 },
 959         { _MMIO(0x9888), 0x05811b12 },
 960         { _MMIO(0x9888), 0x0781001a },
 961         { _MMIO(0x9888), 0x1f810000 },
 962         { _MMIO(0x9888), 0x17810000 },
 963         { _MMIO(0x9888), 0x19810000 },
 964         { _MMIO(0x9888), 0x1b810000 },
 965         { _MMIO(0x9888), 0x1d810000 },
 966         { _MMIO(0x9888), 0x0f968000 },
 967         { _MMIO(0x9888), 0x1196c000 },
 968         { _MMIO(0x9888), 0x13964000 },
 969         { _MMIO(0x9888), 0x11938000 },
 970         { _MMIO(0x9888), 0x1b93fe00 },
 971         { _MMIO(0x9888), 0x01940010 },
 972         { _MMIO(0x9888), 0x07941100 },
 973         { _MMIO(0x9888), 0x09941312 },
 974         { _MMIO(0x9888), 0x0b941514 },
 975         { _MMIO(0x9888), 0x0d941716 },
 976         { _MMIO(0x9888), 0x11940000 },
 977         { _MMIO(0x9888), 0x19940000 },
 978         { _MMIO(0x9888), 0x1b940000 },
 979         { _MMIO(0x9888), 0x1d940000 },
 980         { _MMIO(0x9888), 0x1b954000 },
 981         { _MMIO(0x9888), 0x1d95a550 },
 982         { _MMIO(0x9888), 0x1f9502aa },
 983         { _MMIO(0x9888), 0x2f900167 },
 984         { _MMIO(0x9888), 0x31900105 },
 985         { _MMIO(0x9888), 0x15900103 },
 986         { _MMIO(0x9888), 0x17900101 },
 987         { _MMIO(0x9888), 0x35900000 },
 988         { _MMIO(0x9888), 0x13908000 },
 989         { _MMIO(0x9888), 0x21908000 },
 990         { _MMIO(0x9888), 0x23908000 },
 991         { _MMIO(0x9888), 0x25908000 },
 992         { _MMIO(0x9888), 0x27908000 },
 993         { _MMIO(0x9888), 0x29908000 },
 994         { _MMIO(0x9888), 0x2b908000 },
 995         { _MMIO(0x9888), 0x2d908000 },
 996         { _MMIO(0x9888), 0x19908000 },
 997         { _MMIO(0x9888), 0x1b908000 },
 998         { _MMIO(0x9888), 0x1d908000 },
 999         { _MMIO(0x9888), 0x1f908000 },
1000         { _MMIO(0xd28), 0x00000000 },
1001         { _MMIO(0x9888), 0x11900000 },
1002         { _MMIO(0x9888), 0x51900000 },
1003         { _MMIO(0x9888), 0x41900c00 },
1004         { _MMIO(0x9888), 0x55900000 },
1005         { _MMIO(0x9888), 0x45900000 },
1006         { _MMIO(0x9888), 0x47900000 },
1007         { _MMIO(0x9888), 0x57900000 },
1008         { _MMIO(0x9888), 0x49900000 },
1009         { _MMIO(0x9888), 0x33900000 },
1010         { _MMIO(0x9888), 0x4b900063 },
1011         { _MMIO(0x9888), 0x59900000 },
1012         { _MMIO(0x9888), 0x43900003 },
1013         { _MMIO(0x9888), 0x53900000 },
1014 };
1015
1016 static const struct i915_oa_reg mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02[] = {
1017         { _MMIO(0x9888), 0x11810c00 },
1018         { _MMIO(0x9888), 0x1381001a },
1019         { _MMIO(0x9888), 0x13945400 },
1020         { _MMIO(0x9888), 0x37906800 },
1021         { _MMIO(0x9888), 0x3f901400 },
1022         { _MMIO(0x9888), 0x03811300 },
1023         { _MMIO(0x9888), 0x05811b12 },
1024         { _MMIO(0x9888), 0x0781001a },
1025         { _MMIO(0x9888), 0x1f810000 },
1026         { _MMIO(0x9888), 0x17810000 },
1027         { _MMIO(0x9888), 0x19810000 },
1028         { _MMIO(0x9888), 0x1b810000 },
1029         { _MMIO(0x9888), 0x1d810000 },
1030         { _MMIO(0x9888), 0x19930800 },
1031         { _MMIO(0x9888), 0x1b93aa55 },
1032         { _MMIO(0x9888), 0x1d93002a },
1033         { _MMIO(0x9888), 0x01940010 },
1034         { _MMIO(0x9888), 0x07941100 },
1035         { _MMIO(0x9888), 0x09941312 },
1036         { _MMIO(0x9888), 0x0b941514 },
1037         { _MMIO(0x9888), 0x0d941716 },
1038         { _MMIO(0x9888), 0x1b940000 },
1039         { _MMIO(0x9888), 0x11940000 },
1040         { _MMIO(0x9888), 0x01e58000 },
1041         { _MMIO(0x9888), 0x03e57000 },
1042         { _MMIO(0x9888), 0x2f900167 },
1043         { _MMIO(0x9888), 0x31900105 },
1044         { _MMIO(0x9888), 0x15900103 },
1045         { _MMIO(0x9888), 0x17900101 },
1046         { _MMIO(0x9888), 0x35900000 },
1047         { _MMIO(0x9888), 0x13908000 },
1048         { _MMIO(0x9888), 0x21908000 },
1049         { _MMIO(0x9888), 0x23908000 },
1050         { _MMIO(0x9888), 0x25908000 },
1051         { _MMIO(0x9888), 0x27908000 },
1052         { _MMIO(0x9888), 0x29908000 },
1053         { _MMIO(0x9888), 0x2b908000 },
1054         { _MMIO(0x9888), 0x2d908000 },
1055         { _MMIO(0x9888), 0x19908000 },
1056         { _MMIO(0x9888), 0x1b908000 },
1057         { _MMIO(0x9888), 0x1d908000 },
1058         { _MMIO(0x9888), 0x1f908000 },
1059         { _MMIO(0x9888), 0x11900000 },
1060         { _MMIO(0x9888), 0x51900000 },
1061         { _MMIO(0x9888), 0x41900c20 },
1062         { _MMIO(0x9888), 0x55900000 },
1063         { _MMIO(0x9888), 0x45900400 },
1064         { _MMIO(0x9888), 0x47900421 },
1065         { _MMIO(0x9888), 0x57900000 },
1066         { _MMIO(0x9888), 0x49900421 },
1067         { _MMIO(0x9888), 0x33900000 },
1068         { _MMIO(0x9888), 0x4b900063 },
1069         { _MMIO(0x9888), 0x59900000 },
1070         { _MMIO(0x9888), 0x43900003 },
1071         { _MMIO(0x9888), 0x53900000 },
1072 };
1073
1074 static const struct i915_oa_reg mux_config_memory_writes_0_sku_gte_0x05[] = {
1075         { _MMIO(0x9888), 0x11810c00 },
1076         { _MMIO(0x9888), 0x1381001a },
1077         { _MMIO(0x9888), 0x37906800 },
1078         { _MMIO(0x9888), 0x3f901000 },
1079         { _MMIO(0x9888), 0x03811300 },
1080         { _MMIO(0x9888), 0x05811b12 },
1081         { _MMIO(0x9888), 0x0781001a },
1082         { _MMIO(0x9888), 0x1f810000 },
1083         { _MMIO(0x9888), 0x17810000 },
1084         { _MMIO(0x9888), 0x19810000 },
1085         { _MMIO(0x9888), 0x1b810000 },
1086         { _MMIO(0x9888), 0x1d810000 },
1087         { _MMIO(0x9888), 0x1b930055 },
1088         { _MMIO(0x9888), 0x03e58000 },
1089         { _MMIO(0x9888), 0x05e5c000 },
1090         { _MMIO(0x9888), 0x07e54000 },
1091         { _MMIO(0x9888), 0x13900160 },
1092         { _MMIO(0x9888), 0x21900161 },
1093         { _MMIO(0x9888), 0x23900162 },
1094         { _MMIO(0x9888), 0x25900163 },
1095         { _MMIO(0x9888), 0x27900164 },
1096         { _MMIO(0x9888), 0x29900165 },
1097         { _MMIO(0x9888), 0x2b900166 },
1098         { _MMIO(0x9888), 0x2d900167 },
1099         { _MMIO(0x9888), 0x2f900150 },
1100         { _MMIO(0x9888), 0x31900105 },
1101         { _MMIO(0x9888), 0x15900103 },
1102         { _MMIO(0x9888), 0x17900101 },
1103         { _MMIO(0x9888), 0x35900000 },
1104         { _MMIO(0x9888), 0x19908000 },
1105         { _MMIO(0x9888), 0x1b908000 },
1106         { _MMIO(0x9888), 0x1d908000 },
1107         { _MMIO(0x9888), 0x1f908000 },
1108         { _MMIO(0x9888), 0x11900000 },
1109         { _MMIO(0x9888), 0x51900000 },
1110         { _MMIO(0x9888), 0x41900c60 },
1111         { _MMIO(0x9888), 0x55900000 },
1112         { _MMIO(0x9888), 0x45900c00 },
1113         { _MMIO(0x9888), 0x47900c63 },
1114         { _MMIO(0x9888), 0x57900000 },
1115         { _MMIO(0x9888), 0x49900c63 },
1116         { _MMIO(0x9888), 0x33900000 },
1117         { _MMIO(0x9888), 0x4b900063 },
1118         { _MMIO(0x9888), 0x59900000 },
1119         { _MMIO(0x9888), 0x43900003 },
1120         { _MMIO(0x9888), 0x53900000 },
1121 };
1122
1123 static int
1124 get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
1125                              const struct i915_oa_reg **regs,
1126                              int *lens)
1127 {
1128         int n = 0;
1129
1130         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3);
1131         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3);
1132
1133         if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
1134             (dev_priv->drm.pdev->revision < 0x02)) {
1135                 regs[n] = mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02;
1136                 lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02);
1137                 n++;
1138         }
1139         if ((dev_priv->drm.pdev->revision < 0x05) &&
1140                    (dev_priv->drm.pdev->revision >= 0x02)) {
1141                 regs[n] = mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02;
1142                 lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02);
1143                 n++;
1144         }
1145         if (dev_priv->drm.pdev->revision >= 0x05) {
1146                 regs[n] = mux_config_memory_writes_0_sku_gte_0x05;
1147                 lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_gte_0x05);
1148                 n++;
1149         }
1150
1151         return n;
1152 }
1153
1154 static const struct i915_oa_reg b_counter_config_compute_extended[] = {
1155         { _MMIO(0x2724), 0xf0800000 },
1156         { _MMIO(0x2720), 0x00000000 },
1157         { _MMIO(0x2714), 0xf0800000 },
1158         { _MMIO(0x2710), 0x00000000 },
1159         { _MMIO(0x2740), 0x00000000 },
1160         { _MMIO(0x2770), 0x0007fc2a },
1161         { _MMIO(0x2774), 0x0000bf00 },
1162         { _MMIO(0x2778), 0x0007fc6a },
1163         { _MMIO(0x277c), 0x0000bf00 },
1164         { _MMIO(0x2780), 0x0007fc92 },
1165         { _MMIO(0x2784), 0x0000bf00 },
1166         { _MMIO(0x2788), 0x0007fca2 },
1167         { _MMIO(0x278c), 0x0000bf00 },
1168         { _MMIO(0x2790), 0x0007fc32 },
1169         { _MMIO(0x2794), 0x0000bf00 },
1170         { _MMIO(0x2798), 0x0007fc9a },
1171         { _MMIO(0x279c), 0x0000bf00 },
1172         { _MMIO(0x27a0), 0x0007fe6a },
1173         { _MMIO(0x27a4), 0x0000bf00 },
1174         { _MMIO(0x27a8), 0x0007fe7a },
1175         { _MMIO(0x27ac), 0x0000bf00 },
1176 };
1177
1178 static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
1179         { _MMIO(0xe458), 0x00005004 },
1180         { _MMIO(0xe558), 0x00000003 },
1181         { _MMIO(0xe658), 0x00002001 },
1182         { _MMIO(0xe758), 0x00778008 },
1183         { _MMIO(0xe45c), 0x00088078 },
1184         { _MMIO(0xe55c), 0x00808708 },
1185         { _MMIO(0xe65c), 0x00a08908 },
1186 };
1187
1188 static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = {
1189         { _MMIO(0x9888), 0x106c00e0 },
1190         { _MMIO(0x9888), 0x141c8160 },
1191         { _MMIO(0x9888), 0x161c8015 },
1192         { _MMIO(0x9888), 0x181c0120 },
1193         { _MMIO(0x9888), 0x004e8000 },
1194         { _MMIO(0x9888), 0x0e4e8000 },
1195         { _MMIO(0x9888), 0x184e8000 },
1196         { _MMIO(0x9888), 0x1a4eaaa0 },
1197         { _MMIO(0x9888), 0x1c4e0002 },
1198         { _MMIO(0x9888), 0x024e8000 },
1199         { _MMIO(0x9888), 0x044e8000 },
1200         { _MMIO(0x9888), 0x064e8000 },
1201         { _MMIO(0x9888), 0x084e8000 },
1202         { _MMIO(0x9888), 0x0a4e8000 },
1203         { _MMIO(0x9888), 0x0e6c0b01 },
1204         { _MMIO(0x9888), 0x006c0200 },
1205         { _MMIO(0x9888), 0x026c000c },
1206         { _MMIO(0x9888), 0x1c6c0000 },
1207         { _MMIO(0x9888), 0x1e6c0000 },
1208         { _MMIO(0x9888), 0x1a6c0000 },
1209         { _MMIO(0x9888), 0x0e1bc000 },
1210         { _MMIO(0x9888), 0x001b8000 },
1211         { _MMIO(0x9888), 0x021bc000 },
1212         { _MMIO(0x9888), 0x001c0041 },
1213         { _MMIO(0x9888), 0x061c4200 },
1214         { _MMIO(0x9888), 0x081c4443 },
1215         { _MMIO(0x9888), 0x0a1c4645 },
1216         { _MMIO(0x9888), 0x0c1c7647 },
1217         { _MMIO(0x9888), 0x041c7357 },
1218         { _MMIO(0x9888), 0x1c1c0030 },
1219         { _MMIO(0x9888), 0x101c0000 },
1220         { _MMIO(0x9888), 0x1a1c0000 },
1221         { _MMIO(0x9888), 0x121c8000 },
1222         { _MMIO(0x9888), 0x004c8000 },
1223         { _MMIO(0x9888), 0x0a4caa2a },
1224         { _MMIO(0x9888), 0x0c4c02aa },
1225         { _MMIO(0x9888), 0x084ca000 },
1226         { _MMIO(0x9888), 0x000da000 },
1227         { _MMIO(0x9888), 0x060d8000 },
1228         { _MMIO(0x9888), 0x080da000 },
1229         { _MMIO(0x9888), 0x0a0da000 },
1230         { _MMIO(0x9888), 0x0c0da000 },
1231         { _MMIO(0x9888), 0x0e0da000 },
1232         { _MMIO(0x9888), 0x020da000 },
1233         { _MMIO(0x9888), 0x040da000 },
1234         { _MMIO(0x9888), 0x0c0f5400 },
1235         { _MMIO(0x9888), 0x0e0f5515 },
1236         { _MMIO(0x9888), 0x100f0155 },
1237         { _MMIO(0x9888), 0x002c8000 },
1238         { _MMIO(0x9888), 0x0e2c8000 },
1239         { _MMIO(0x9888), 0x162caa00 },
1240         { _MMIO(0x9888), 0x182c00aa },
1241         { _MMIO(0x9888), 0x022c8000 },
1242         { _MMIO(0x9888), 0x042c8000 },
1243         { _MMIO(0x9888), 0x062c8000 },
1244         { _MMIO(0x9888), 0x082c8000 },
1245         { _MMIO(0x9888), 0x0a2c8000 },
1246         { _MMIO(0xd28), 0x00000000 },
1247         { _MMIO(0x9888), 0x11907fff },
1248         { _MMIO(0x9888), 0x51900000 },
1249         { _MMIO(0x9888), 0x41900040 },
1250         { _MMIO(0x9888), 0x55900000 },
1251         { _MMIO(0x9888), 0x45900802 },
1252         { _MMIO(0x9888), 0x47900842 },
1253         { _MMIO(0x9888), 0x57900000 },
1254         { _MMIO(0x9888), 0x49900842 },
1255         { _MMIO(0x9888), 0x37900000 },
1256         { _MMIO(0x9888), 0x33900000 },
1257         { _MMIO(0x9888), 0x4b900000 },
1258         { _MMIO(0x9888), 0x59900000 },
1259         { _MMIO(0x9888), 0x43900800 },
1260         { _MMIO(0x9888), 0x53900000 },
1261 };
1262
1263 static int
1264 get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
1265                                 const struct i915_oa_reg **regs,
1266                                 int *lens)
1267 {
1268         int n = 0;
1269
1270         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1271         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1272
1273         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
1274                 regs[n] = mux_config_compute_extended_0_subslices_0x01;
1275                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01);
1276                 n++;
1277         }
1278
1279         return n;
1280 }
1281
1282 static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
1283         { _MMIO(0x2710), 0x00000000 },
1284         { _MMIO(0x2714), 0x30800000 },
1285         { _MMIO(0x2720), 0x00000000 },
1286         { _MMIO(0x2724), 0x30800000 },
1287         { _MMIO(0x2740), 0x00000000 },
1288         { _MMIO(0x2770), 0x0007fffa },
1289         { _MMIO(0x2774), 0x0000fefe },
1290         { _MMIO(0x2778), 0x0007fffa },
1291         { _MMIO(0x277c), 0x0000fefd },
1292         { _MMIO(0x2790), 0x0007fffa },
1293         { _MMIO(0x2794), 0x0000fbef },
1294         { _MMIO(0x2798), 0x0007fffa },
1295         { _MMIO(0x279c), 0x0000fbdf },
1296 };
1297
1298 static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
1299         { _MMIO(0xe458), 0x00005004 },
1300         { _MMIO(0xe558), 0x00000003 },
1301         { _MMIO(0xe658), 0x00002001 },
1302         { _MMIO(0xe758), 0x00101100 },
1303         { _MMIO(0xe45c), 0x00201200 },
1304         { _MMIO(0xe55c), 0x00301300 },
1305         { _MMIO(0xe65c), 0x00401400 },
1306 };
1307
1308 static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
1309         { _MMIO(0x9888), 0x166c0760 },
1310         { _MMIO(0x9888), 0x1593001e },
1311         { _MMIO(0x9888), 0x3f901403 },
1312         { _MMIO(0x9888), 0x004e8000 },
1313         { _MMIO(0x9888), 0x0e4e8000 },
1314         { _MMIO(0x9888), 0x184e8000 },
1315         { _MMIO(0x9888), 0x1a4e8020 },
1316         { _MMIO(0x9888), 0x1c4e0002 },
1317         { _MMIO(0x9888), 0x006c0051 },
1318         { _MMIO(0x9888), 0x066c5000 },
1319         { _MMIO(0x9888), 0x086c5c5d },
1320         { _MMIO(0x9888), 0x0e6c5e5f },
1321         { _MMIO(0x9888), 0x106c0000 },
1322         { _MMIO(0x9888), 0x186c0000 },
1323         { _MMIO(0x9888), 0x1c6c0000 },
1324         { _MMIO(0x9888), 0x1e6c0000 },
1325         { _MMIO(0x9888), 0x001b4000 },
1326         { _MMIO(0x9888), 0x061b8000 },
1327         { _MMIO(0x9888), 0x081bc000 },
1328         { _MMIO(0x9888), 0x0e1bc000 },
1329         { _MMIO(0x9888), 0x101c8000 },
1330         { _MMIO(0x9888), 0x1a1ce000 },
1331         { _MMIO(0x9888), 0x1c1c0030 },
1332         { _MMIO(0x9888), 0x004c8000 },
1333         { _MMIO(0x9888), 0x0a4c2a00 },
1334         { _MMIO(0x9888), 0x0c4c0280 },
1335         { _MMIO(0x9888), 0x000d2000 },
1336         { _MMIO(0x9888), 0x060d8000 },
1337         { _MMIO(0x9888), 0x080da000 },
1338         { _MMIO(0x9888), 0x0e0da000 },
1339         { _MMIO(0x9888), 0x0c0f0400 },
1340         { _MMIO(0x9888), 0x0e0f1500 },
1341         { _MMIO(0x9888), 0x100f0140 },
1342         { _MMIO(0x9888), 0x002c8000 },
1343         { _MMIO(0x9888), 0x0e2c8000 },
1344         { _MMIO(0x9888), 0x162c0a00 },
1345         { _MMIO(0x9888), 0x182c00a0 },
1346         { _MMIO(0x9888), 0x03933300 },
1347         { _MMIO(0x9888), 0x05930032 },
1348         { _MMIO(0x9888), 0x11930000 },
1349         { _MMIO(0x9888), 0x1b930000 },
1350         { _MMIO(0x9888), 0x1d900157 },
1351         { _MMIO(0x9888), 0x1f900167 },
1352         { _MMIO(0x9888), 0x35900000 },
1353         { _MMIO(0x9888), 0x19908000 },
1354         { _MMIO(0x9888), 0x1b908000 },
1355         { _MMIO(0x9888), 0x1190030f },
1356         { _MMIO(0x9888), 0x51900000 },
1357         { _MMIO(0x9888), 0x41900000 },
1358         { _MMIO(0x9888), 0x55900000 },
1359         { _MMIO(0x9888), 0x45900042 },
1360         { _MMIO(0x9888), 0x47900000 },
1361         { _MMIO(0x9888), 0x37900000 },
1362         { _MMIO(0x9888), 0x33900000 },
1363         { _MMIO(0x9888), 0x57900000 },
1364         { _MMIO(0x9888), 0x4b900000 },
1365         { _MMIO(0x9888), 0x59900000 },
1366         { _MMIO(0x9888), 0x53901111 },
1367         { _MMIO(0x9888), 0x43900420 },
1368 };
1369
1370 static int
1371 get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
1372                                 const struct i915_oa_reg **regs,
1373                                 int *lens)
1374 {
1375         int n = 0;
1376
1377         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1378         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1379
1380         regs[n] = mux_config_compute_l3_cache;
1381         lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
1382         n++;
1383
1384         return n;
1385 }
1386
1387 static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
1388         { _MMIO(0x2740), 0x00000000 },
1389         { _MMIO(0x2744), 0x00800000 },
1390         { _MMIO(0x2710), 0x00000000 },
1391         { _MMIO(0x2714), 0x10800000 },
1392         { _MMIO(0x2720), 0x00000000 },
1393         { _MMIO(0x2724), 0x00800000 },
1394         { _MMIO(0x2770), 0x00000002 },
1395         { _MMIO(0x2774), 0x0000fdff },
1396 };
1397
1398 static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
1399         { _MMIO(0xe458), 0x00005004 },
1400         { _MMIO(0xe558), 0x00010003 },
1401         { _MMIO(0xe658), 0x00012011 },
1402         { _MMIO(0xe758), 0x00015014 },
1403         { _MMIO(0xe45c), 0x00051050 },
1404         { _MMIO(0xe55c), 0x00053052 },
1405         { _MMIO(0xe65c), 0x00055054 },
1406 };
1407
1408 static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
1409         { _MMIO(0x9888), 0x104f0232 },
1410         { _MMIO(0x9888), 0x124f4640 },
1411         { _MMIO(0x9888), 0x106c0232 },
1412         { _MMIO(0x9888), 0x11834400 },
1413         { _MMIO(0x9888), 0x0a4e8000 },
1414         { _MMIO(0x9888), 0x0c4e8000 },
1415         { _MMIO(0x9888), 0x004f1880 },
1416         { _MMIO(0x9888), 0x024f08bb },
1417         { _MMIO(0x9888), 0x044f001b },
1418         { _MMIO(0x9888), 0x046c0100 },
1419         { _MMIO(0x9888), 0x066c000b },
1420         { _MMIO(0x9888), 0x1a6c0000 },
1421         { _MMIO(0x9888), 0x041b8000 },
1422         { _MMIO(0x9888), 0x061b4000 },
1423         { _MMIO(0x9888), 0x1a1c1800 },
1424         { _MMIO(0x9888), 0x005b8000 },
1425         { _MMIO(0x9888), 0x025bc000 },
1426         { _MMIO(0x9888), 0x045b4000 },
1427         { _MMIO(0x9888), 0x125c8000 },
1428         { _MMIO(0x9888), 0x145c8000 },
1429         { _MMIO(0x9888), 0x165c8000 },
1430         { _MMIO(0x9888), 0x185c8000 },
1431         { _MMIO(0x9888), 0x0a4c00a0 },
1432         { _MMIO(0x9888), 0x000d8000 },
1433         { _MMIO(0x9888), 0x020da000 },
1434         { _MMIO(0x9888), 0x040da000 },
1435         { _MMIO(0x9888), 0x060d2000 },
1436         { _MMIO(0x9888), 0x0c0f5000 },
1437         { _MMIO(0x9888), 0x0e0f0055 },
1438         { _MMIO(0x9888), 0x022cc000 },
1439         { _MMIO(0x9888), 0x042cc000 },
1440         { _MMIO(0x9888), 0x062cc000 },
1441         { _MMIO(0x9888), 0x082cc000 },
1442         { _MMIO(0x9888), 0x0a2c8000 },
1443         { _MMIO(0x9888), 0x0c2c8000 },
1444         { _MMIO(0x9888), 0x0f828000 },
1445         { _MMIO(0x9888), 0x0f8305c0 },
1446         { _MMIO(0x9888), 0x09830000 },
1447         { _MMIO(0x9888), 0x07830000 },
1448         { _MMIO(0x9888), 0x1d950080 },
1449         { _MMIO(0x9888), 0x13928000 },
1450         { _MMIO(0x9888), 0x0f988000 },
1451         { _MMIO(0x9888), 0x31904000 },
1452         { _MMIO(0x9888), 0x1190fc00 },
1453         { _MMIO(0x9888), 0x37900000 },
1454         { _MMIO(0x9888), 0x59900000 },
1455         { _MMIO(0x9888), 0x4b9000a0 },
1456         { _MMIO(0x9888), 0x51900000 },
1457         { _MMIO(0x9888), 0x41900800 },
1458         { _MMIO(0x9888), 0x43900842 },
1459         { _MMIO(0x9888), 0x53900000 },
1460         { _MMIO(0x9888), 0x45900000 },
1461         { _MMIO(0x9888), 0x33900000 },
1462 };
1463
1464 static int
1465 get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
1466                           const struct i915_oa_reg **regs,
1467                           int *lens)
1468 {
1469         int n = 0;
1470
1471         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1472         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1473
1474         regs[n] = mux_config_hdc_and_sf;
1475         lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
1476         n++;
1477
1478         return n;
1479 }
1480
1481 static const struct i915_oa_reg b_counter_config_l3_1[] = {
1482         { _MMIO(0x2740), 0x00000000 },
1483         { _MMIO(0x2744), 0x00800000 },
1484         { _MMIO(0x2710), 0x00000000 },
1485         { _MMIO(0x2714), 0xf0800000 },
1486         { _MMIO(0x2720), 0x00000000 },
1487         { _MMIO(0x2724), 0xf0800000 },
1488         { _MMIO(0x2770), 0x00100070 },
1489         { _MMIO(0x2774), 0x0000fff1 },
1490         { _MMIO(0x2778), 0x00014002 },
1491         { _MMIO(0x277c), 0x0000c3ff },
1492         { _MMIO(0x2780), 0x00010002 },
1493         { _MMIO(0x2784), 0x0000c7ff },
1494         { _MMIO(0x2788), 0x00004002 },
1495         { _MMIO(0x278c), 0x0000d3ff },
1496         { _MMIO(0x2790), 0x00100700 },
1497         { _MMIO(0x2794), 0x0000ff1f },
1498         { _MMIO(0x2798), 0x00001402 },
1499         { _MMIO(0x279c), 0x0000fc3f },
1500         { _MMIO(0x27a0), 0x00001002 },
1501         { _MMIO(0x27a4), 0x0000fc7f },
1502         { _MMIO(0x27a8), 0x00000402 },
1503         { _MMIO(0x27ac), 0x0000fd3f },
1504 };
1505
1506 static const struct i915_oa_reg flex_eu_config_l3_1[] = {
1507         { _MMIO(0xe458), 0x00005004 },
1508         { _MMIO(0xe558), 0x00010003 },
1509         { _MMIO(0xe658), 0x00012011 },
1510         { _MMIO(0xe758), 0x00015014 },
1511         { _MMIO(0xe45c), 0x00051050 },
1512         { _MMIO(0xe55c), 0x00053052 },
1513         { _MMIO(0xe65c), 0x00055054 },
1514 };
1515
1516 static const struct i915_oa_reg mux_config_l3_1[] = {
1517         { _MMIO(0x9888), 0x126c7b40 },
1518         { _MMIO(0x9888), 0x166c0020 },
1519         { _MMIO(0x9888), 0x0a603444 },
1520         { _MMIO(0x9888), 0x0a613400 },
1521         { _MMIO(0x9888), 0x1a4ea800 },
1522         { _MMIO(0x9888), 0x1c4e0002 },
1523         { _MMIO(0x9888), 0x024e8000 },
1524         { _MMIO(0x9888), 0x044e8000 },
1525         { _MMIO(0x9888), 0x064e8000 },
1526         { _MMIO(0x9888), 0x084e8000 },
1527         { _MMIO(0x9888), 0x0a4e8000 },
1528         { _MMIO(0x9888), 0x064f4000 },
1529         { _MMIO(0x9888), 0x0c6c5327 },
1530         { _MMIO(0x9888), 0x0e6c5425 },
1531         { _MMIO(0x9888), 0x006c2a00 },
1532         { _MMIO(0x9888), 0x026c285b },
1533         { _MMIO(0x9888), 0x046c005c },
1534         { _MMIO(0x9888), 0x106c0000 },
1535         { _MMIO(0x9888), 0x1c6c0000 },
1536         { _MMIO(0x9888), 0x1e6c0000 },
1537         { _MMIO(0x9888), 0x1a6c0800 },
1538         { _MMIO(0x9888), 0x0c1bc000 },
1539         { _MMIO(0x9888), 0x0e1bc000 },
1540         { _MMIO(0x9888), 0x001b8000 },
1541         { _MMIO(0x9888), 0x021bc000 },
1542         { _MMIO(0x9888), 0x041bc000 },
1543         { _MMIO(0x9888), 0x1c1c003c },
1544         { _MMIO(0x9888), 0x121c8000 },
1545         { _MMIO(0x9888), 0x141c8000 },
1546         { _MMIO(0x9888), 0x161c8000 },
1547         { _MMIO(0x9888), 0x181c8000 },
1548         { _MMIO(0x9888), 0x1a1c0800 },
1549         { _MMIO(0x9888), 0x065b4000 },
1550         { _MMIO(0x9888), 0x1a5c1000 },
1551         { _MMIO(0x9888), 0x10600000 },
1552         { _MMIO(0x9888), 0x04600000 },
1553         { _MMIO(0x9888), 0x0c610044 },
1554         { _MMIO(0x9888), 0x10610000 },
1555         { _MMIO(0x9888), 0x06610000 },
1556         { _MMIO(0x9888), 0x0c4c02a8 },
1557         { _MMIO(0x9888), 0x084ca000 },
1558         { _MMIO(0x9888), 0x0a4c002a },
1559         { _MMIO(0x9888), 0x0c0da000 },
1560         { _MMIO(0x9888), 0x0e0da000 },
1561         { _MMIO(0x9888), 0x000d8000 },
1562         { _MMIO(0x9888), 0x020da000 },
1563         { _MMIO(0x9888), 0x040da000 },
1564         { _MMIO(0x9888), 0x060d2000 },
1565         { _MMIO(0x9888), 0x100f0154 },
1566         { _MMIO(0x9888), 0x0c0f5000 },
1567         { _MMIO(0x9888), 0x0e0f0055 },
1568         { _MMIO(0x9888), 0x182c00aa },
1569         { _MMIO(0x9888), 0x022c8000 },
1570         { _MMIO(0x9888), 0x042c8000 },
1571         { _MMIO(0x9888), 0x062c8000 },
1572         { _MMIO(0x9888), 0x082c8000 },
1573         { _MMIO(0x9888), 0x0a2c8000 },
1574         { _MMIO(0x9888), 0x0c2cc000 },
1575         { _MMIO(0x9888), 0x1190ffc0 },
1576         { _MMIO(0x9888), 0x57900000 },
1577         { _MMIO(0x9888), 0x49900420 },
1578         { _MMIO(0x9888), 0x37900000 },
1579         { _MMIO(0x9888), 0x33900000 },
1580         { _MMIO(0x9888), 0x4b900021 },
1581         { _MMIO(0x9888), 0x59900000 },
1582         { _MMIO(0x9888), 0x51900000 },
1583         { _MMIO(0x9888), 0x41900400 },
1584         { _MMIO(0x9888), 0x43900421 },
1585         { _MMIO(0x9888), 0x53900000 },
1586         { _MMIO(0x9888), 0x45900040 },
1587 };
1588
1589 static int
1590 get_l3_1_mux_config(struct drm_i915_private *dev_priv,
1591                     const struct i915_oa_reg **regs,
1592                     int *lens)
1593 {
1594         int n = 0;
1595
1596         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1597         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1598
1599         regs[n] = mux_config_l3_1;
1600         lens[n] = ARRAY_SIZE(mux_config_l3_1);
1601         n++;
1602
1603         return n;
1604 }
1605
1606 static const struct i915_oa_reg b_counter_config_l3_2[] = {
1607         { _MMIO(0x2740), 0x00000000 },
1608         { _MMIO(0x2744), 0x00800000 },
1609         { _MMIO(0x2710), 0x00000000 },
1610         { _MMIO(0x2714), 0xf0800000 },
1611         { _MMIO(0x2720), 0x00000000 },
1612         { _MMIO(0x2724), 0x00800000 },
1613         { _MMIO(0x2770), 0x00100070 },
1614         { _MMIO(0x2774), 0x0000fff1 },
1615         { _MMIO(0x2778), 0x00028002 },
1616         { _MMIO(0x277c), 0x000087ff },
1617         { _MMIO(0x2780), 0x00020002 },
1618         { _MMIO(0x2784), 0x00008fff },
1619         { _MMIO(0x2788), 0x00008002 },
1620         { _MMIO(0x278c), 0x0000a7ff },
1621 };
1622
1623 static const struct i915_oa_reg flex_eu_config_l3_2[] = {
1624         { _MMIO(0xe458), 0x00005004 },
1625         { _MMIO(0xe558), 0x00010003 },
1626         { _MMIO(0xe658), 0x00012011 },
1627         { _MMIO(0xe758), 0x00015014 },
1628         { _MMIO(0xe45c), 0x00051050 },
1629         { _MMIO(0xe55c), 0x00053052 },
1630         { _MMIO(0xe65c), 0x00055054 },
1631 };
1632
1633 static const struct i915_oa_reg mux_config_l3_2[] = {
1634         { _MMIO(0x9888), 0x126c02e0 },
1635         { _MMIO(0x9888), 0x146c0001 },
1636         { _MMIO(0x9888), 0x0a623400 },
1637         { _MMIO(0x9888), 0x044e8000 },
1638         { _MMIO(0x9888), 0x064e8000 },
1639         { _MMIO(0x9888), 0x084e8000 },
1640         { _MMIO(0x9888), 0x0a4e8000 },
1641         { _MMIO(0x9888), 0x064f4000 },
1642         { _MMIO(0x9888), 0x026c3324 },
1643         { _MMIO(0x9888), 0x046c3422 },
1644         { _MMIO(0x9888), 0x106c0000 },
1645         { _MMIO(0x9888), 0x1a6c0000 },
1646         { _MMIO(0x9888), 0x021bc000 },
1647         { _MMIO(0x9888), 0x041bc000 },
1648         { _MMIO(0x9888), 0x141c8000 },
1649         { _MMIO(0x9888), 0x161c8000 },
1650         { _MMIO(0x9888), 0x181c8000 },
1651         { _MMIO(0x9888), 0x1a1c0800 },
1652         { _MMIO(0x9888), 0x065b4000 },
1653         { _MMIO(0x9888), 0x1a5c1000 },
1654         { _MMIO(0x9888), 0x06614000 },
1655         { _MMIO(0x9888), 0x0c620044 },
1656         { _MMIO(0x9888), 0x10620000 },
1657         { _MMIO(0x9888), 0x06620000 },
1658         { _MMIO(0x9888), 0x084c8000 },
1659         { _MMIO(0x9888), 0x0a4c002a },
1660         { _MMIO(0x9888), 0x020da000 },
1661         { _MMIO(0x9888), 0x040da000 },
1662         { _MMIO(0x9888), 0x060d2000 },
1663         { _MMIO(0x9888), 0x0c0f4000 },
1664         { _MMIO(0x9888), 0x0e0f0055 },
1665         { _MMIO(0x9888), 0x042c8000 },
1666         { _MMIO(0x9888), 0x062c8000 },
1667         { _MMIO(0x9888), 0x082c8000 },
1668         { _MMIO(0x9888), 0x0a2c8000 },
1669         { _MMIO(0x9888), 0x0c2cc000 },
1670         { _MMIO(0x9888), 0x1190f800 },
1671         { _MMIO(0x9888), 0x37900000 },
1672         { _MMIO(0x9888), 0x51900000 },
1673         { _MMIO(0x9888), 0x43900000 },
1674         { _MMIO(0x9888), 0x53900000 },
1675         { _MMIO(0x9888), 0x45900000 },
1676         { _MMIO(0x9888), 0x33900000 },
1677 };
1678
1679 static int
1680 get_l3_2_mux_config(struct drm_i915_private *dev_priv,
1681                     const struct i915_oa_reg **regs,
1682                     int *lens)
1683 {
1684         int n = 0;
1685
1686         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1687         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1688
1689         regs[n] = mux_config_l3_2;
1690         lens[n] = ARRAY_SIZE(mux_config_l3_2);
1691         n++;
1692
1693         return n;
1694 }
1695
1696 static const struct i915_oa_reg b_counter_config_l3_3[] = {
1697         { _MMIO(0x2740), 0x00000000 },
1698         { _MMIO(0x2744), 0x00800000 },
1699         { _MMIO(0x2710), 0x00000000 },
1700         { _MMIO(0x2714), 0xf0800000 },
1701         { _MMIO(0x2720), 0x00000000 },
1702         { _MMIO(0x2724), 0x00800000 },
1703         { _MMIO(0x2770), 0x00100070 },
1704         { _MMIO(0x2774), 0x0000fff1 },
1705         { _MMIO(0x2778), 0x00028002 },
1706         { _MMIO(0x277c), 0x000087ff },
1707         { _MMIO(0x2780), 0x00020002 },
1708         { _MMIO(0x2784), 0x00008fff },
1709         { _MMIO(0x2788), 0x00008002 },
1710         { _MMIO(0x278c), 0x0000a7ff },
1711 };
1712
1713 static const struct i915_oa_reg flex_eu_config_l3_3[] = {
1714         { _MMIO(0xe458), 0x00005004 },
1715         { _MMIO(0xe558), 0x00010003 },
1716         { _MMIO(0xe658), 0x00012011 },
1717         { _MMIO(0xe758), 0x00015014 },
1718         { _MMIO(0xe45c), 0x00051050 },
1719         { _MMIO(0xe55c), 0x00053052 },
1720         { _MMIO(0xe65c), 0x00055054 },
1721 };
1722
1723 static const struct i915_oa_reg mux_config_l3_3[] = {
1724         { _MMIO(0x9888), 0x126c4e80 },
1725         { _MMIO(0x9888), 0x146c0000 },
1726         { _MMIO(0x9888), 0x0a633400 },
1727         { _MMIO(0x9888), 0x044e8000 },
1728         { _MMIO(0x9888), 0x064e8000 },
1729         { _MMIO(0x9888), 0x084e8000 },
1730         { _MMIO(0x9888), 0x0a4e8000 },
1731         { _MMIO(0x9888), 0x0c4e8000 },
1732         { _MMIO(0x9888), 0x026c3321 },
1733         { _MMIO(0x9888), 0x046c342f },
1734         { _MMIO(0x9888), 0x106c0000 },
1735         { _MMIO(0x9888), 0x1a6c2000 },
1736         { _MMIO(0x9888), 0x021bc000 },
1737         { _MMIO(0x9888), 0x041bc000 },
1738         { _MMIO(0x9888), 0x061b4000 },
1739         { _MMIO(0x9888), 0x141c8000 },
1740         { _MMIO(0x9888), 0x161c8000 },
1741         { _MMIO(0x9888), 0x181c8000 },
1742         { _MMIO(0x9888), 0x1a1c1800 },
1743         { _MMIO(0x9888), 0x06604000 },
1744         { _MMIO(0x9888), 0x0c630044 },
1745         { _MMIO(0x9888), 0x10630000 },
1746         { _MMIO(0x9888), 0x06630000 },
1747         { _MMIO(0x9888), 0x084c8000 },
1748         { _MMIO(0x9888), 0x0a4c00aa },
1749         { _MMIO(0x9888), 0x020da000 },
1750         { _MMIO(0x9888), 0x040da000 },
1751         { _MMIO(0x9888), 0x060d2000 },
1752         { _MMIO(0x9888), 0x0c0f4000 },
1753         { _MMIO(0x9888), 0x0e0f0055 },
1754         { _MMIO(0x9888), 0x042c8000 },
1755         { _MMIO(0x9888), 0x062c8000 },
1756         { _MMIO(0x9888), 0x082c8000 },
1757         { _MMIO(0x9888), 0x0a2c8000 },
1758         { _MMIO(0x9888), 0x0c2c8000 },
1759         { _MMIO(0x9888), 0x1190f800 },
1760         { _MMIO(0x9888), 0x37900000 },
1761         { _MMIO(0x9888), 0x51900000 },
1762         { _MMIO(0x9888), 0x43900842 },
1763         { _MMIO(0x9888), 0x53900000 },
1764         { _MMIO(0x9888), 0x45900002 },
1765         { _MMIO(0x9888), 0x33900000 },
1766 };
1767
1768 static int
1769 get_l3_3_mux_config(struct drm_i915_private *dev_priv,
1770                     const struct i915_oa_reg **regs,
1771                     int *lens)
1772 {
1773         int n = 0;
1774
1775         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1776         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1777
1778         regs[n] = mux_config_l3_3;
1779         lens[n] = ARRAY_SIZE(mux_config_l3_3);
1780         n++;
1781
1782         return n;
1783 }
1784
1785 static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1786         { _MMIO(0x2740), 0x00000000 },
1787         { _MMIO(0x2744), 0x00800000 },
1788         { _MMIO(0x2710), 0x00000000 },
1789         { _MMIO(0x2714), 0x30800000 },
1790         { _MMIO(0x2720), 0x00000000 },
1791         { _MMIO(0x2724), 0x00800000 },
1792         { _MMIO(0x2770), 0x00000002 },
1793         { _MMIO(0x2774), 0x0000efff },
1794         { _MMIO(0x2778), 0x00006000 },
1795         { _MMIO(0x277c), 0x0000f3ff },
1796 };
1797
1798 static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1799         { _MMIO(0xe458), 0x00005004 },
1800         { _MMIO(0xe558), 0x00010003 },
1801         { _MMIO(0xe658), 0x00012011 },
1802         { _MMIO(0xe758), 0x00015014 },
1803         { _MMIO(0xe45c), 0x00051050 },
1804         { _MMIO(0xe55c), 0x00053052 },
1805         { _MMIO(0xe65c), 0x00055054 },
1806 };
1807
1808 static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1809         { _MMIO(0x9888), 0x102f3800 },
1810         { _MMIO(0x9888), 0x144d0500 },
1811         { _MMIO(0x9888), 0x120d03c0 },
1812         { _MMIO(0x9888), 0x140d03cf },
1813         { _MMIO(0x9888), 0x0c0f0004 },
1814         { _MMIO(0x9888), 0x0c4e4000 },
1815         { _MMIO(0x9888), 0x042f0480 },
1816         { _MMIO(0x9888), 0x082f0000 },
1817         { _MMIO(0x9888), 0x022f0000 },
1818         { _MMIO(0x9888), 0x0a4c0090 },
1819         { _MMIO(0x9888), 0x064d0027 },
1820         { _MMIO(0x9888), 0x004d0000 },
1821         { _MMIO(0x9888), 0x000d0d40 },
1822         { _MMIO(0x9888), 0x020d803f },
1823         { _MMIO(0x9888), 0x040d8023 },
1824         { _MMIO(0x9888), 0x100d0000 },
1825         { _MMIO(0x9888), 0x060d2000 },
1826         { _MMIO(0x9888), 0x020f0010 },
1827         { _MMIO(0x9888), 0x000f0000 },
1828         { _MMIO(0x9888), 0x0e0f0050 },
1829         { _MMIO(0x9888), 0x0a2c8000 },
1830         { _MMIO(0x9888), 0x0c2c8000 },
1831         { _MMIO(0x9888), 0x1190fc00 },
1832         { _MMIO(0x9888), 0x37900000 },
1833         { _MMIO(0x9888), 0x51900000 },
1834         { _MMIO(0x9888), 0x41901400 },
1835         { _MMIO(0x9888), 0x43901485 },
1836         { _MMIO(0x9888), 0x53900000 },
1837         { _MMIO(0x9888), 0x45900001 },
1838         { _MMIO(0x9888), 0x33900000 },
1839 };
1840
1841 static int
1842 get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1843                                             const struct i915_oa_reg **regs,
1844                                             int *lens)
1845 {
1846         int n = 0;
1847
1848         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1849         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1850
1851         regs[n] = mux_config_rasterizer_and_pixel_backend;
1852         lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1853         n++;
1854
1855         return n;
1856 }
1857
1858 static const struct i915_oa_reg b_counter_config_sampler[] = {
1859         { _MMIO(0x2740), 0x00000000 },
1860         { _MMIO(0x2744), 0x00800000 },
1861         { _MMIO(0x2710), 0x00000000 },
1862         { _MMIO(0x2714), 0x70800000 },
1863         { _MMIO(0x2720), 0x00000000 },
1864         { _MMIO(0x2724), 0x00800000 },
1865         { _MMIO(0x2770), 0x0000c000 },
1866         { _MMIO(0x2774), 0x0000e7ff },
1867         { _MMIO(0x2778), 0x00003000 },
1868         { _MMIO(0x277c), 0x0000f9ff },
1869         { _MMIO(0x2780), 0x00000c00 },
1870         { _MMIO(0x2784), 0x0000fe7f },
1871 };
1872
1873 static const struct i915_oa_reg flex_eu_config_sampler[] = {
1874         { _MMIO(0xe458), 0x00005004 },
1875         { _MMIO(0xe558), 0x00010003 },
1876         { _MMIO(0xe658), 0x00012011 },
1877         { _MMIO(0xe758), 0x00015014 },
1878         { _MMIO(0xe45c), 0x00051050 },
1879         { _MMIO(0xe55c), 0x00053052 },
1880         { _MMIO(0xe65c), 0x00055054 },
1881 };
1882
1883 static const struct i915_oa_reg mux_config_sampler[] = {
1884         { _MMIO(0x9888), 0x14152c00 },
1885         { _MMIO(0x9888), 0x16150005 },
1886         { _MMIO(0x9888), 0x121600a0 },
1887         { _MMIO(0x9888), 0x14352c00 },
1888         { _MMIO(0x9888), 0x16350005 },
1889         { _MMIO(0x9888), 0x123600a0 },
1890         { _MMIO(0x9888), 0x14552c00 },
1891         { _MMIO(0x9888), 0x16550005 },
1892         { _MMIO(0x9888), 0x125600a0 },
1893         { _MMIO(0x9888), 0x062f6000 },
1894         { _MMIO(0x9888), 0x022f2000 },
1895         { _MMIO(0x9888), 0x0c4c0050 },
1896         { _MMIO(0x9888), 0x0a4c0010 },
1897         { _MMIO(0x9888), 0x0c0d8000 },
1898         { _MMIO(0x9888), 0x0e0da000 },
1899         { _MMIO(0x9888), 0x000d8000 },
1900         { _MMIO(0x9888), 0x020da000 },
1901         { _MMIO(0x9888), 0x040da000 },
1902         { _MMIO(0x9888), 0x060d2000 },
1903         { _MMIO(0x9888), 0x100f0350 },
1904         { _MMIO(0x9888), 0x0c0fb000 },
1905         { _MMIO(0x9888), 0x0e0f00da },
1906         { _MMIO(0x9888), 0x182c0028 },
1907         { _MMIO(0x9888), 0x0a2c8000 },
1908         { _MMIO(0x9888), 0x022dc000 },
1909         { _MMIO(0x9888), 0x042d4000 },
1910         { _MMIO(0x9888), 0x0c138000 },
1911         { _MMIO(0x9888), 0x0e132000 },
1912         { _MMIO(0x9888), 0x0413c000 },
1913         { _MMIO(0x9888), 0x1c140018 },
1914         { _MMIO(0x9888), 0x0c157000 },
1915         { _MMIO(0x9888), 0x0e150078 },
1916         { _MMIO(0x9888), 0x10150000 },
1917         { _MMIO(0x9888), 0x04162180 },
1918         { _MMIO(0x9888), 0x02160000 },
1919         { _MMIO(0x9888), 0x04174000 },
1920         { _MMIO(0x9888), 0x0233a000 },
1921         { _MMIO(0x9888), 0x04333000 },
1922         { _MMIO(0x9888), 0x14348000 },
1923         { _MMIO(0x9888), 0x16348000 },
1924         { _MMIO(0x9888), 0x02357870 },
1925         { _MMIO(0x9888), 0x10350000 },
1926         { _MMIO(0x9888), 0x04360043 },
1927         { _MMIO(0x9888), 0x02360000 },
1928         { _MMIO(0x9888), 0x04371000 },
1929         { _MMIO(0x9888), 0x0e538000 },
1930         { _MMIO(0x9888), 0x00538000 },
1931         { _MMIO(0x9888), 0x06533000 },
1932         { _MMIO(0x9888), 0x1c540020 },
1933         { _MMIO(0x9888), 0x12548000 },
1934         { _MMIO(0x9888), 0x0e557000 },
1935         { _MMIO(0x9888), 0x00557800 },
1936         { _MMIO(0x9888), 0x10550000 },
1937         { _MMIO(0x9888), 0x06560043 },
1938         { _MMIO(0x9888), 0x02560000 },
1939         { _MMIO(0x9888), 0x06571000 },
1940         { _MMIO(0x9888), 0x1190ff80 },
1941         { _MMIO(0x9888), 0x57900000 },
1942         { _MMIO(0x9888), 0x49900000 },
1943         { _MMIO(0x9888), 0x37900000 },
1944         { _MMIO(0x9888), 0x33900000 },
1945         { _MMIO(0x9888), 0x4b900060 },
1946         { _MMIO(0x9888), 0x59900000 },
1947         { _MMIO(0x9888), 0x51900000 },
1948         { _MMIO(0x9888), 0x41900c00 },
1949         { _MMIO(0x9888), 0x43900842 },
1950         { _MMIO(0x9888), 0x53900000 },
1951         { _MMIO(0x9888), 0x45900060 },
1952 };
1953
1954 static int
1955 get_sampler_mux_config(struct drm_i915_private *dev_priv,
1956                        const struct i915_oa_reg **regs,
1957                        int *lens)
1958 {
1959         int n = 0;
1960
1961         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1962         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1963
1964         regs[n] = mux_config_sampler;
1965         lens[n] = ARRAY_SIZE(mux_config_sampler);
1966         n++;
1967
1968         return n;
1969 }
1970
1971 static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1972         { _MMIO(0x2740), 0x00000000 },
1973         { _MMIO(0x2744), 0x00800000 },
1974         { _MMIO(0x2710), 0x00000000 },
1975         { _MMIO(0x2714), 0xf0800000 },
1976         { _MMIO(0x2720), 0x00000000 },
1977         { _MMIO(0x2724), 0x30800000 },
1978         { _MMIO(0x2770), 0x00000002 },
1979         { _MMIO(0x2774), 0x00007fff },
1980         { _MMIO(0x2778), 0x00000000 },
1981         { _MMIO(0x277c), 0x00009fff },
1982         { _MMIO(0x2780), 0x00000002 },
1983         { _MMIO(0x2784), 0x0000efff },
1984         { _MMIO(0x2788), 0x00000000 },
1985         { _MMIO(0x278c), 0x0000f3ff },
1986         { _MMIO(0x2790), 0x00000002 },
1987         { _MMIO(0x2794), 0x0000fdff },
1988         { _MMIO(0x2798), 0x00000000 },
1989         { _MMIO(0x279c), 0x0000fe7f },
1990 };
1991
1992 static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1993         { _MMIO(0xe458), 0x00005004 },
1994         { _MMIO(0xe558), 0x00010003 },
1995         { _MMIO(0xe658), 0x00012011 },
1996         { _MMIO(0xe758), 0x00015014 },
1997         { _MMIO(0xe45c), 0x00051050 },
1998         { _MMIO(0xe55c), 0x00053052 },
1999         { _MMIO(0xe65c), 0x00055054 },
2000 };
2001
2002 static const struct i915_oa_reg mux_config_tdl_1[] = {
2003         { _MMIO(0x9888), 0x12120000 },
2004         { _MMIO(0x9888), 0x12320000 },
2005         { _MMIO(0x9888), 0x12520000 },
2006         { _MMIO(0x9888), 0x002f8000 },
2007         { _MMIO(0x9888), 0x022f3000 },
2008         { _MMIO(0x9888), 0x0a4c0015 },
2009         { _MMIO(0x9888), 0x0c0d8000 },
2010         { _MMIO(0x9888), 0x0e0da000 },
2011         { _MMIO(0x9888), 0x000d8000 },
2012         { _MMIO(0x9888), 0x020da000 },
2013         { _MMIO(0x9888), 0x040da000 },
2014         { _MMIO(0x9888), 0x060d2000 },
2015         { _MMIO(0x9888), 0x100f03a0 },
2016         { _MMIO(0x9888), 0x0c0ff000 },
2017         { _MMIO(0x9888), 0x0e0f0095 },
2018         { _MMIO(0x9888), 0x062c8000 },
2019         { _MMIO(0x9888), 0x082c8000 },
2020         { _MMIO(0x9888), 0x0a2c8000 },
2021         { _MMIO(0x9888), 0x0c2d8000 },
2022         { _MMIO(0x9888), 0x0e2d4000 },
2023         { _MMIO(0x9888), 0x062d4000 },
2024         { _MMIO(0x9888), 0x02108000 },
2025         { _MMIO(0x9888), 0x0410c000 },
2026         { _MMIO(0x9888), 0x02118000 },
2027         { _MMIO(0x9888), 0x0411c000 },
2028         { _MMIO(0x9888), 0x02121880 },
2029         { _MMIO(0x9888), 0x041219b5 },
2030         { _MMIO(0x9888), 0x00120000 },
2031         { _MMIO(0x9888), 0x02134000 },
2032         { _MMIO(0x9888), 0x04135000 },
2033         { _MMIO(0x9888), 0x0c308000 },
2034         { _MMIO(0x9888), 0x0e304000 },
2035         { _MMIO(0x9888), 0x06304000 },
2036         { _MMIO(0x9888), 0x0c318000 },
2037         { _MMIO(0x9888), 0x0e314000 },
2038         { _MMIO(0x9888), 0x06314000 },
2039         { _MMIO(0x9888), 0x0c321a80 },
2040         { _MMIO(0x9888), 0x0e320033 },
2041         { _MMIO(0x9888), 0x06320031 },
2042         { _MMIO(0x9888), 0x00320000 },
2043         { _MMIO(0x9888), 0x0c334000 },
2044         { _MMIO(0x9888), 0x0e331000 },
2045         { _MMIO(0x9888), 0x06331000 },
2046         { _MMIO(0x9888), 0x0e508000 },
2047         { _MMIO(0x9888), 0x00508000 },
2048         { _MMIO(0x9888), 0x02504000 },
2049         { _MMIO(0x9888), 0x0e518000 },
2050         { _MMIO(0x9888), 0x00518000 },
2051         { _MMIO(0x9888), 0x02514000 },
2052         { _MMIO(0x9888), 0x0e521880 },
2053         { _MMIO(0x9888), 0x00521a80 },
2054         { _MMIO(0x9888), 0x02520033 },
2055         { _MMIO(0x9888), 0x0e534000 },
2056         { _MMIO(0x9888), 0x00534000 },
2057         { _MMIO(0x9888), 0x02531000 },
2058         { _MMIO(0x9888), 0x1190ff80 },
2059         { _MMIO(0x9888), 0x57900000 },
2060         { _MMIO(0x9888), 0x49900800 },
2061         { _MMIO(0x9888), 0x37900000 },
2062         { _MMIO(0x9888), 0x33900000 },
2063         { _MMIO(0x9888), 0x4b900062 },
2064         { _MMIO(0x9888), 0x59900000 },
2065         { _MMIO(0x9888), 0x51900000 },
2066         { _MMIO(0x9888), 0x41900c00 },
2067         { _MMIO(0x9888), 0x43900003 },
2068         { _MMIO(0x9888), 0x53900000 },
2069         { _MMIO(0x9888), 0x45900040 },
2070 };
2071
2072 static int
2073 get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
2074                      const struct i915_oa_reg **regs,
2075                      int *lens)
2076 {
2077         int n = 0;
2078
2079         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2080         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2081
2082         regs[n] = mux_config_tdl_1;
2083         lens[n] = ARRAY_SIZE(mux_config_tdl_1);
2084         n++;
2085
2086         return n;
2087 }
2088
2089 static const struct i915_oa_reg b_counter_config_tdl_2[] = {
2090         { _MMIO(0x2740), 0x00000000 },
2091         { _MMIO(0x2744), 0x00800000 },
2092         { _MMIO(0x2710), 0x00000000 },
2093         { _MMIO(0x2714), 0x00800000 },
2094         { _MMIO(0x2720), 0x00000000 },
2095         { _MMIO(0x2724), 0x00800000 },
2096 };
2097
2098 static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
2099         { _MMIO(0xe458), 0x00005004 },
2100         { _MMIO(0xe558), 0x00010003 },
2101         { _MMIO(0xe658), 0x00012011 },
2102         { _MMIO(0xe758), 0x00015014 },
2103         { _MMIO(0xe45c), 0x00051050 },
2104         { _MMIO(0xe55c), 0x00053052 },
2105         { _MMIO(0xe65c), 0x00055054 },
2106 };
2107
2108 static const struct i915_oa_reg mux_config_tdl_2[] = {
2109         { _MMIO(0x9888), 0x12124d60 },
2110         { _MMIO(0x9888), 0x12322e60 },
2111         { _MMIO(0x9888), 0x12524d60 },
2112         { _MMIO(0x9888), 0x022f3000 },
2113         { _MMIO(0x9888), 0x0a4c0014 },
2114         { _MMIO(0x9888), 0x000d8000 },
2115         { _MMIO(0x9888), 0x020da000 },
2116         { _MMIO(0x9888), 0x040da000 },
2117         { _MMIO(0x9888), 0x060d2000 },
2118         { _MMIO(0x9888), 0x0c0fe000 },
2119         { _MMIO(0x9888), 0x0e0f0097 },
2120         { _MMIO(0x9888), 0x082c8000 },
2121         { _MMIO(0x9888), 0x0a2c8000 },
2122         { _MMIO(0x9888), 0x002d8000 },
2123         { _MMIO(0x9888), 0x062d4000 },
2124         { _MMIO(0x9888), 0x0410c000 },
2125         { _MMIO(0x9888), 0x0411c000 },
2126         { _MMIO(0x9888), 0x04121fb7 },
2127         { _MMIO(0x9888), 0x00120000 },
2128         { _MMIO(0x9888), 0x04135000 },
2129         { _MMIO(0x9888), 0x00308000 },
2130         { _MMIO(0x9888), 0x06304000 },
2131         { _MMIO(0x9888), 0x00318000 },
2132         { _MMIO(0x9888), 0x06314000 },
2133         { _MMIO(0x9888), 0x00321b80 },
2134         { _MMIO(0x9888), 0x0632003f },
2135         { _MMIO(0x9888), 0x00334000 },
2136         { _MMIO(0x9888), 0x06331000 },
2137         { _MMIO(0x9888), 0x0250c000 },
2138         { _MMIO(0x9888), 0x0251c000 },
2139         { _MMIO(0x9888), 0x02521fb7 },
2140         { _MMIO(0x9888), 0x00520000 },
2141         { _MMIO(0x9888), 0x02535000 },
2142         { _MMIO(0x9888), 0x1190fc00 },
2143         { _MMIO(0x9888), 0x37900000 },
2144         { _MMIO(0x9888), 0x51900000 },
2145         { _MMIO(0x9888), 0x41900800 },
2146         { _MMIO(0x9888), 0x43900063 },
2147         { _MMIO(0x9888), 0x53900000 },
2148         { _MMIO(0x9888), 0x45900040 },
2149         { _MMIO(0x9888), 0x33900000 },
2150 };
2151
2152 static int
2153 get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
2154                      const struct i915_oa_reg **regs,
2155                      int *lens)
2156 {
2157         int n = 0;
2158
2159         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2160         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2161
2162         regs[n] = mux_config_tdl_2;
2163         lens[n] = ARRAY_SIZE(mux_config_tdl_2);
2164         n++;
2165
2166         return n;
2167 }
2168
2169 static const struct i915_oa_reg b_counter_config_compute_extra[] = {
2170         { _MMIO(0x2740), 0x00000000 },
2171         { _MMIO(0x2744), 0x00800000 },
2172         { _MMIO(0x2710), 0x00000000 },
2173         { _MMIO(0x2714), 0x00800000 },
2174         { _MMIO(0x2720), 0x00000000 },
2175         { _MMIO(0x2724), 0x00800000 },
2176 };
2177
2178 static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
2179         { _MMIO(0xe458), 0x00001000 },
2180         { _MMIO(0xe558), 0x00003002 },
2181         { _MMIO(0xe658), 0x00005004 },
2182         { _MMIO(0xe758), 0x00011010 },
2183         { _MMIO(0xe45c), 0x00050012 },
2184         { _MMIO(0xe55c), 0x00052051 },
2185         { _MMIO(0xe65c), 0x00000008 },
2186 };
2187
2188 static const struct i915_oa_reg mux_config_compute_extra[] = {
2189         { _MMIO(0x9888), 0x121203e0 },
2190         { _MMIO(0x9888), 0x123203e0 },
2191         { _MMIO(0x9888), 0x125203e0 },
2192         { _MMIO(0x9888), 0x022f4000 },
2193         { _MMIO(0x9888), 0x0a4c0040 },
2194         { _MMIO(0x9888), 0x040da000 },
2195         { _MMIO(0x9888), 0x060d2000 },
2196         { _MMIO(0x9888), 0x0e0f006c },
2197         { _MMIO(0x9888), 0x0c2c8000 },
2198         { _MMIO(0x9888), 0x042d8000 },
2199         { _MMIO(0x9888), 0x06104000 },
2200         { _MMIO(0x9888), 0x06114000 },
2201         { _MMIO(0x9888), 0x06120033 },
2202         { _MMIO(0x9888), 0x00120000 },
2203         { _MMIO(0x9888), 0x06131000 },
2204         { _MMIO(0x9888), 0x04308000 },
2205         { _MMIO(0x9888), 0x04318000 },
2206         { _MMIO(0x9888), 0x04321980 },
2207         { _MMIO(0x9888), 0x00320000 },
2208         { _MMIO(0x9888), 0x04334000 },
2209         { _MMIO(0x9888), 0x04504000 },
2210         { _MMIO(0x9888), 0x04514000 },
2211         { _MMIO(0x9888), 0x04520033 },
2212         { _MMIO(0x9888), 0x00520000 },
2213         { _MMIO(0x9888), 0x04531000 },
2214         { _MMIO(0x9888), 0x1190e000 },
2215         { _MMIO(0x9888), 0x37900000 },
2216         { _MMIO(0x9888), 0x53900000 },
2217         { _MMIO(0x9888), 0x43900c00 },
2218         { _MMIO(0x9888), 0x45900002 },
2219         { _MMIO(0x9888), 0x33900000 },
2220 };
2221
2222 static int
2223 get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
2224                              const struct i915_oa_reg **regs,
2225                              int *lens)
2226 {
2227         int n = 0;
2228
2229         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2230         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2231
2232         regs[n] = mux_config_compute_extra;
2233         lens[n] = ARRAY_SIZE(mux_config_compute_extra);
2234         n++;
2235
2236         return n;
2237 }
2238
2239 static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
2240         { _MMIO(0x2740), 0x00000000 },
2241         { _MMIO(0x2710), 0x00000000 },
2242         { _MMIO(0x2714), 0xf0800000 },
2243         { _MMIO(0x2720), 0x00000000 },
2244         { _MMIO(0x2724), 0x30800000 },
2245         { _MMIO(0x2770), 0x00100030 },
2246         { _MMIO(0x2774), 0x0000fff9 },
2247         { _MMIO(0x2778), 0x00000002 },
2248         { _MMIO(0x277c), 0x0000fffc },
2249         { _MMIO(0x2780), 0x00000002 },
2250         { _MMIO(0x2784), 0x0000fff3 },
2251         { _MMIO(0x2788), 0x00100180 },
2252         { _MMIO(0x278c), 0x0000ffcf },
2253         { _MMIO(0x2790), 0x00000002 },
2254         { _MMIO(0x2794), 0x0000ffcf },
2255         { _MMIO(0x2798), 0x00000002 },
2256         { _MMIO(0x279c), 0x0000ff3f },
2257 };
2258
2259 static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
2260         { _MMIO(0xe458), 0x00005004 },
2261         { _MMIO(0xe558), 0x00008003 },
2262 };
2263
2264 static const struct i915_oa_reg mux_config_vme_pipe[] = {
2265         { _MMIO(0x9888), 0x141a5800 },
2266         { _MMIO(0x9888), 0x161a00c0 },
2267         { _MMIO(0x9888), 0x12180240 },
2268         { _MMIO(0x9888), 0x14180002 },
2269         { _MMIO(0x9888), 0x143a5800 },
2270         { _MMIO(0x9888), 0x163a00c0 },
2271         { _MMIO(0x9888), 0x12380240 },
2272         { _MMIO(0x9888), 0x14380002 },
2273         { _MMIO(0x9888), 0x002f1000 },
2274         { _MMIO(0x9888), 0x022f8000 },
2275         { _MMIO(0x9888), 0x042f3000 },
2276         { _MMIO(0x9888), 0x004c4000 },
2277         { _MMIO(0x9888), 0x0a4c1500 },
2278         { _MMIO(0x9888), 0x000d2000 },
2279         { _MMIO(0x9888), 0x060d8000 },
2280         { _MMIO(0x9888), 0x080da000 },
2281         { _MMIO(0x9888), 0x0a0da000 },
2282         { _MMIO(0x9888), 0x0c0da000 },
2283         { _MMIO(0x9888), 0x0c0f0400 },
2284         { _MMIO(0x9888), 0x0e0f9500 },
2285         { _MMIO(0x9888), 0x100f002a },
2286         { _MMIO(0x9888), 0x002c8000 },
2287         { _MMIO(0x9888), 0x0e2c8000 },
2288         { _MMIO(0x9888), 0x162c0a00 },
2289         { _MMIO(0x9888), 0x0a2dc000 },
2290         { _MMIO(0x9888), 0x0c2dc000 },
2291         { _MMIO(0x9888), 0x04193000 },
2292         { _MMIO(0x9888), 0x081a28c1 },
2293         { _MMIO(0x9888), 0x001a0000 },
2294         { _MMIO(0x9888), 0x00133000 },
2295         { _MMIO(0x9888), 0x0613c000 },
2296         { _MMIO(0x9888), 0x0813f000 },
2297         { _MMIO(0x9888), 0x00172000 },
2298         { _MMIO(0x9888), 0x06178000 },
2299         { _MMIO(0x9888), 0x0817a000 },
2300         { _MMIO(0x9888), 0x00180037 },
2301         { _MMIO(0x9888), 0x06180940 },
2302         { _MMIO(0x9888), 0x08180000 },
2303         { _MMIO(0x9888), 0x02180000 },
2304         { _MMIO(0x9888), 0x04183000 },
2305         { _MMIO(0x9888), 0x06393000 },
2306         { _MMIO(0x9888), 0x0c3a28c1 },
2307         { _MMIO(0x9888), 0x003a0000 },
2308         { _MMIO(0x9888), 0x0a33f000 },
2309         { _MMIO(0x9888), 0x0c33f000 },
2310         { _MMIO(0x9888), 0x0a37a000 },
2311         { _MMIO(0x9888), 0x0c37a000 },
2312         { _MMIO(0x9888), 0x0a380977 },
2313         { _MMIO(0x9888), 0x08380000 },
2314         { _MMIO(0x9888), 0x04380000 },
2315         { _MMIO(0x9888), 0x06383000 },
2316         { _MMIO(0x9888), 0x119000ff },
2317         { _MMIO(0x9888), 0x51900000 },
2318         { _MMIO(0x9888), 0x41900040 },
2319         { _MMIO(0x9888), 0x55900000 },
2320         { _MMIO(0x9888), 0x45900800 },
2321         { _MMIO(0x9888), 0x47901000 },
2322         { _MMIO(0x9888), 0x57900000 },
2323         { _MMIO(0x9888), 0x49900844 },
2324         { _MMIO(0x9888), 0x37900000 },
2325         { _MMIO(0x9888), 0x33900000 },
2326 };
2327
2328 static int
2329 get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
2330                         const struct i915_oa_reg **regs,
2331                         int *lens)
2332 {
2333         int n = 0;
2334
2335         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2336         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2337
2338         regs[n] = mux_config_vme_pipe;
2339         lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
2340         n++;
2341
2342         return n;
2343 }
2344
2345 static const struct i915_oa_reg b_counter_config_test_oa[] = {
2346         { _MMIO(0x2740), 0x00000000 },
2347         { _MMIO(0x2714), 0xf0800000 },
2348         { _MMIO(0x2710), 0x00000000 },
2349         { _MMIO(0x2724), 0xf0800000 },
2350         { _MMIO(0x2720), 0x00000000 },
2351         { _MMIO(0x2770), 0x00000004 },
2352         { _MMIO(0x2774), 0x00000000 },
2353         { _MMIO(0x2778), 0x00000003 },
2354         { _MMIO(0x277c), 0x00000000 },
2355         { _MMIO(0x2780), 0x00000007 },
2356         { _MMIO(0x2784), 0x00000000 },
2357         { _MMIO(0x2788), 0x00100002 },
2358         { _MMIO(0x278c), 0x0000fff7 },
2359         { _MMIO(0x2790), 0x00100002 },
2360         { _MMIO(0x2794), 0x0000ffcf },
2361         { _MMIO(0x2798), 0x00100082 },
2362         { _MMIO(0x279c), 0x0000ffef },
2363         { _MMIO(0x27a0), 0x001000c2 },
2364         { _MMIO(0x27a4), 0x0000ffe7 },
2365         { _MMIO(0x27a8), 0x00100001 },
2366         { _MMIO(0x27ac), 0x0000ffe7 },
2367 };
2368
2369 static const struct i915_oa_reg flex_eu_config_test_oa[] = {
2370 };
2371
2372 static const struct i915_oa_reg mux_config_test_oa[] = {
2373         { _MMIO(0x9888), 0x11810000 },
2374         { _MMIO(0x9888), 0x07810016 },
2375         { _MMIO(0x9888), 0x1f810000 },
2376         { _MMIO(0x9888), 0x1d810000 },
2377         { _MMIO(0x9888), 0x1b930040 },
2378         { _MMIO(0x9888), 0x07e54000 },
2379         { _MMIO(0x9888), 0x1f908000 },
2380         { _MMIO(0x9888), 0x11900000 },
2381         { _MMIO(0x9888), 0x37900000 },
2382         { _MMIO(0x9888), 0x53900000 },
2383         { _MMIO(0x9888), 0x45900000 },
2384         { _MMIO(0x9888), 0x33900000 },
2385 };
2386
2387 static int
2388 get_test_oa_mux_config(struct drm_i915_private *dev_priv,
2389                        const struct i915_oa_reg **regs,
2390                        int *lens)
2391 {
2392         int n = 0;
2393
2394         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2395         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2396
2397         regs[n] = mux_config_test_oa;
2398         lens[n] = ARRAY_SIZE(mux_config_test_oa);
2399         n++;
2400
2401         return n;
2402 }
2403
2404 int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv)
2405 {
2406         dev_priv->perf.oa.n_mux_configs = 0;
2407         dev_priv->perf.oa.b_counter_regs = NULL;
2408         dev_priv->perf.oa.b_counter_regs_len = 0;
2409         dev_priv->perf.oa.flex_regs = NULL;
2410         dev_priv->perf.oa.flex_regs_len = 0;
2411
2412         switch (dev_priv->perf.oa.metrics_set) {
2413         case METRIC_SET_ID_RENDER_BASIC:
2414                 dev_priv->perf.oa.n_mux_configs =
2415                         get_render_basic_mux_config(dev_priv,
2416                                                     dev_priv->perf.oa.mux_regs,
2417                                                     dev_priv->perf.oa.mux_regs_lens);
2418                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2419                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
2420
2421                         /* EINVAL because *_register_sysfs already checked this
2422                          * and so it wouldn't have been advertised to userspace and
2423                          * so shouldn't have been requested
2424                          */
2425                         return -EINVAL;
2426                 }
2427
2428                 dev_priv->perf.oa.b_counter_regs =
2429                         b_counter_config_render_basic;
2430                 dev_priv->perf.oa.b_counter_regs_len =
2431                         ARRAY_SIZE(b_counter_config_render_basic);
2432
2433                 dev_priv->perf.oa.flex_regs =
2434                         flex_eu_config_render_basic;
2435                 dev_priv->perf.oa.flex_regs_len =
2436                         ARRAY_SIZE(flex_eu_config_render_basic);
2437
2438                 return 0;
2439         case METRIC_SET_ID_COMPUTE_BASIC:
2440                 dev_priv->perf.oa.n_mux_configs =
2441                         get_compute_basic_mux_config(dev_priv,
2442                                                      dev_priv->perf.oa.mux_regs,
2443                                                      dev_priv->perf.oa.mux_regs_lens);
2444                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2445                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
2446
2447                         /* EINVAL because *_register_sysfs already checked this
2448                          * and so it wouldn't have been advertised to userspace and
2449                          * so shouldn't have been requested
2450                          */
2451                         return -EINVAL;
2452                 }
2453
2454                 dev_priv->perf.oa.b_counter_regs =
2455                         b_counter_config_compute_basic;
2456                 dev_priv->perf.oa.b_counter_regs_len =
2457                         ARRAY_SIZE(b_counter_config_compute_basic);
2458
2459                 dev_priv->perf.oa.flex_regs =
2460                         flex_eu_config_compute_basic;
2461                 dev_priv->perf.oa.flex_regs_len =
2462                         ARRAY_SIZE(flex_eu_config_compute_basic);
2463
2464                 return 0;
2465         case METRIC_SET_ID_RENDER_PIPE_PROFILE:
2466                 dev_priv->perf.oa.n_mux_configs =
2467                         get_render_pipe_profile_mux_config(dev_priv,
2468                                                            dev_priv->perf.oa.mux_regs,
2469                                                            dev_priv->perf.oa.mux_regs_lens);
2470                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2471                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
2472
2473                         /* EINVAL because *_register_sysfs already checked this
2474                          * and so it wouldn't have been advertised to userspace and
2475                          * so shouldn't have been requested
2476                          */
2477                         return -EINVAL;
2478                 }
2479
2480                 dev_priv->perf.oa.b_counter_regs =
2481                         b_counter_config_render_pipe_profile;
2482                 dev_priv->perf.oa.b_counter_regs_len =
2483                         ARRAY_SIZE(b_counter_config_render_pipe_profile);
2484
2485                 dev_priv->perf.oa.flex_regs =
2486                         flex_eu_config_render_pipe_profile;
2487                 dev_priv->perf.oa.flex_regs_len =
2488                         ARRAY_SIZE(flex_eu_config_render_pipe_profile);
2489
2490                 return 0;
2491         case METRIC_SET_ID_MEMORY_READS:
2492                 dev_priv->perf.oa.n_mux_configs =
2493                         get_memory_reads_mux_config(dev_priv,
2494                                                     dev_priv->perf.oa.mux_regs,
2495                                                     dev_priv->perf.oa.mux_regs_lens);
2496                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2497                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
2498
2499                         /* EINVAL because *_register_sysfs already checked this
2500                          * and so it wouldn't have been advertised to userspace and
2501                          * so shouldn't have been requested
2502                          */
2503                         return -EINVAL;
2504                 }
2505
2506                 dev_priv->perf.oa.b_counter_regs =
2507                         b_counter_config_memory_reads;
2508                 dev_priv->perf.oa.b_counter_regs_len =
2509                         ARRAY_SIZE(b_counter_config_memory_reads);
2510
2511                 dev_priv->perf.oa.flex_regs =
2512                         flex_eu_config_memory_reads;
2513                 dev_priv->perf.oa.flex_regs_len =
2514                         ARRAY_SIZE(flex_eu_config_memory_reads);
2515
2516                 return 0;
2517         case METRIC_SET_ID_MEMORY_WRITES:
2518                 dev_priv->perf.oa.n_mux_configs =
2519                         get_memory_writes_mux_config(dev_priv,
2520                                                      dev_priv->perf.oa.mux_regs,
2521                                                      dev_priv->perf.oa.mux_regs_lens);
2522                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2523                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
2524
2525                         /* EINVAL because *_register_sysfs already checked this
2526                          * and so it wouldn't have been advertised to userspace and
2527                          * so shouldn't have been requested
2528                          */
2529                         return -EINVAL;
2530                 }
2531
2532                 dev_priv->perf.oa.b_counter_regs =
2533                         b_counter_config_memory_writes;
2534                 dev_priv->perf.oa.b_counter_regs_len =
2535                         ARRAY_SIZE(b_counter_config_memory_writes);
2536
2537                 dev_priv->perf.oa.flex_regs =
2538                         flex_eu_config_memory_writes;
2539                 dev_priv->perf.oa.flex_regs_len =
2540                         ARRAY_SIZE(flex_eu_config_memory_writes);
2541
2542                 return 0;
2543         case METRIC_SET_ID_COMPUTE_EXTENDED:
2544                 dev_priv->perf.oa.n_mux_configs =
2545                         get_compute_extended_mux_config(dev_priv,
2546                                                         dev_priv->perf.oa.mux_regs,
2547                                                         dev_priv->perf.oa.mux_regs_lens);
2548                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2549                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
2550
2551                         /* EINVAL because *_register_sysfs already checked this
2552                          * and so it wouldn't have been advertised to userspace and
2553                          * so shouldn't have been requested
2554                          */
2555                         return -EINVAL;
2556                 }
2557
2558                 dev_priv->perf.oa.b_counter_regs =
2559                         b_counter_config_compute_extended;
2560                 dev_priv->perf.oa.b_counter_regs_len =
2561                         ARRAY_SIZE(b_counter_config_compute_extended);
2562
2563                 dev_priv->perf.oa.flex_regs =
2564                         flex_eu_config_compute_extended;
2565                 dev_priv->perf.oa.flex_regs_len =
2566                         ARRAY_SIZE(flex_eu_config_compute_extended);
2567
2568                 return 0;
2569         case METRIC_SET_ID_COMPUTE_L3_CACHE:
2570                 dev_priv->perf.oa.n_mux_configs =
2571                         get_compute_l3_cache_mux_config(dev_priv,
2572                                                         dev_priv->perf.oa.mux_regs,
2573                                                         dev_priv->perf.oa.mux_regs_lens);
2574                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2575                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
2576
2577                         /* EINVAL because *_register_sysfs already checked this
2578                          * and so it wouldn't have been advertised to userspace and
2579                          * so shouldn't have been requested
2580                          */
2581                         return -EINVAL;
2582                 }
2583
2584                 dev_priv->perf.oa.b_counter_regs =
2585                         b_counter_config_compute_l3_cache;
2586                 dev_priv->perf.oa.b_counter_regs_len =
2587                         ARRAY_SIZE(b_counter_config_compute_l3_cache);
2588
2589                 dev_priv->perf.oa.flex_regs =
2590                         flex_eu_config_compute_l3_cache;
2591                 dev_priv->perf.oa.flex_regs_len =
2592                         ARRAY_SIZE(flex_eu_config_compute_l3_cache);
2593
2594                 return 0;
2595         case METRIC_SET_ID_HDC_AND_SF:
2596                 dev_priv->perf.oa.n_mux_configs =
2597                         get_hdc_and_sf_mux_config(dev_priv,
2598                                                   dev_priv->perf.oa.mux_regs,
2599                                                   dev_priv->perf.oa.mux_regs_lens);
2600                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2601                         DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
2602
2603                         /* EINVAL because *_register_sysfs already checked this
2604                          * and so it wouldn't have been advertised to userspace and
2605                          * so shouldn't have been requested
2606                          */
2607                         return -EINVAL;
2608                 }
2609
2610                 dev_priv->perf.oa.b_counter_regs =
2611                         b_counter_config_hdc_and_sf;
2612                 dev_priv->perf.oa.b_counter_regs_len =
2613                         ARRAY_SIZE(b_counter_config_hdc_and_sf);
2614
2615                 dev_priv->perf.oa.flex_regs =
2616                         flex_eu_config_hdc_and_sf;
2617                 dev_priv->perf.oa.flex_regs_len =
2618                         ARRAY_SIZE(flex_eu_config_hdc_and_sf);
2619
2620                 return 0;
2621         case METRIC_SET_ID_L3_1:
2622                 dev_priv->perf.oa.n_mux_configs =
2623                         get_l3_1_mux_config(dev_priv,
2624                                             dev_priv->perf.oa.mux_regs,
2625                                             dev_priv->perf.oa.mux_regs_lens);
2626                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2627                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
2628
2629                         /* EINVAL because *_register_sysfs already checked this
2630                          * and so it wouldn't have been advertised to userspace and
2631                          * so shouldn't have been requested
2632                          */
2633                         return -EINVAL;
2634                 }
2635
2636                 dev_priv->perf.oa.b_counter_regs =
2637                         b_counter_config_l3_1;
2638                 dev_priv->perf.oa.b_counter_regs_len =
2639                         ARRAY_SIZE(b_counter_config_l3_1);
2640
2641                 dev_priv->perf.oa.flex_regs =
2642                         flex_eu_config_l3_1;
2643                 dev_priv->perf.oa.flex_regs_len =
2644                         ARRAY_SIZE(flex_eu_config_l3_1);
2645
2646                 return 0;
2647         case METRIC_SET_ID_L3_2:
2648                 dev_priv->perf.oa.n_mux_configs =
2649                         get_l3_2_mux_config(dev_priv,
2650                                             dev_priv->perf.oa.mux_regs,
2651                                             dev_priv->perf.oa.mux_regs_lens);
2652                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2653                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
2654
2655                         /* EINVAL because *_register_sysfs already checked this
2656                          * and so it wouldn't have been advertised to userspace and
2657                          * so shouldn't have been requested
2658                          */
2659                         return -EINVAL;
2660                 }
2661
2662                 dev_priv->perf.oa.b_counter_regs =
2663                         b_counter_config_l3_2;
2664                 dev_priv->perf.oa.b_counter_regs_len =
2665                         ARRAY_SIZE(b_counter_config_l3_2);
2666
2667                 dev_priv->perf.oa.flex_regs =
2668                         flex_eu_config_l3_2;
2669                 dev_priv->perf.oa.flex_regs_len =
2670                         ARRAY_SIZE(flex_eu_config_l3_2);
2671
2672                 return 0;
2673         case METRIC_SET_ID_L3_3:
2674                 dev_priv->perf.oa.n_mux_configs =
2675                         get_l3_3_mux_config(dev_priv,
2676                                             dev_priv->perf.oa.mux_regs,
2677                                             dev_priv->perf.oa.mux_regs_lens);
2678                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2679                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
2680
2681                         /* EINVAL because *_register_sysfs already checked this
2682                          * and so it wouldn't have been advertised to userspace and
2683                          * so shouldn't have been requested
2684                          */
2685                         return -EINVAL;
2686                 }
2687
2688                 dev_priv->perf.oa.b_counter_regs =
2689                         b_counter_config_l3_3;
2690                 dev_priv->perf.oa.b_counter_regs_len =
2691                         ARRAY_SIZE(b_counter_config_l3_3);
2692
2693                 dev_priv->perf.oa.flex_regs =
2694                         flex_eu_config_l3_3;
2695                 dev_priv->perf.oa.flex_regs_len =
2696                         ARRAY_SIZE(flex_eu_config_l3_3);
2697
2698                 return 0;
2699         case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
2700                 dev_priv->perf.oa.n_mux_configs =
2701                         get_rasterizer_and_pixel_backend_mux_config(dev_priv,
2702                                                                     dev_priv->perf.oa.mux_regs,
2703                                                                     dev_priv->perf.oa.mux_regs_lens);
2704                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2705                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
2706
2707                         /* EINVAL because *_register_sysfs already checked this
2708                          * and so it wouldn't have been advertised to userspace and
2709                          * so shouldn't have been requested
2710                          */
2711                         return -EINVAL;
2712                 }
2713
2714                 dev_priv->perf.oa.b_counter_regs =
2715                         b_counter_config_rasterizer_and_pixel_backend;
2716                 dev_priv->perf.oa.b_counter_regs_len =
2717                         ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
2718
2719                 dev_priv->perf.oa.flex_regs =
2720                         flex_eu_config_rasterizer_and_pixel_backend;
2721                 dev_priv->perf.oa.flex_regs_len =
2722                         ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
2723
2724                 return 0;
2725         case METRIC_SET_ID_SAMPLER:
2726                 dev_priv->perf.oa.n_mux_configs =
2727                         get_sampler_mux_config(dev_priv,
2728                                                dev_priv->perf.oa.mux_regs,
2729                                                dev_priv->perf.oa.mux_regs_lens);
2730                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2731                         DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
2732
2733                         /* EINVAL because *_register_sysfs already checked this
2734                          * and so it wouldn't have been advertised to userspace and
2735                          * so shouldn't have been requested
2736                          */
2737                         return -EINVAL;
2738                 }
2739
2740                 dev_priv->perf.oa.b_counter_regs =
2741                         b_counter_config_sampler;
2742                 dev_priv->perf.oa.b_counter_regs_len =
2743                         ARRAY_SIZE(b_counter_config_sampler);
2744
2745                 dev_priv->perf.oa.flex_regs =
2746                         flex_eu_config_sampler;
2747                 dev_priv->perf.oa.flex_regs_len =
2748                         ARRAY_SIZE(flex_eu_config_sampler);
2749
2750                 return 0;
2751         case METRIC_SET_ID_TDL_1:
2752                 dev_priv->perf.oa.n_mux_configs =
2753                         get_tdl_1_mux_config(dev_priv,
2754                                              dev_priv->perf.oa.mux_regs,
2755                                              dev_priv->perf.oa.mux_regs_lens);
2756                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2757                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2758
2759                         /* EINVAL because *_register_sysfs already checked this
2760                          * and so it wouldn't have been advertised to userspace and
2761                          * so shouldn't have been requested
2762                          */
2763                         return -EINVAL;
2764                 }
2765
2766                 dev_priv->perf.oa.b_counter_regs =
2767                         b_counter_config_tdl_1;
2768                 dev_priv->perf.oa.b_counter_regs_len =
2769                         ARRAY_SIZE(b_counter_config_tdl_1);
2770
2771                 dev_priv->perf.oa.flex_regs =
2772                         flex_eu_config_tdl_1;
2773                 dev_priv->perf.oa.flex_regs_len =
2774                         ARRAY_SIZE(flex_eu_config_tdl_1);
2775
2776                 return 0;
2777         case METRIC_SET_ID_TDL_2:
2778                 dev_priv->perf.oa.n_mux_configs =
2779                         get_tdl_2_mux_config(dev_priv,
2780                                              dev_priv->perf.oa.mux_regs,
2781                                              dev_priv->perf.oa.mux_regs_lens);
2782                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2783                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2784
2785                         /* EINVAL because *_register_sysfs already checked this
2786                          * and so it wouldn't have been advertised to userspace and
2787                          * so shouldn't have been requested
2788                          */
2789                         return -EINVAL;
2790                 }
2791
2792                 dev_priv->perf.oa.b_counter_regs =
2793                         b_counter_config_tdl_2;
2794                 dev_priv->perf.oa.b_counter_regs_len =
2795                         ARRAY_SIZE(b_counter_config_tdl_2);
2796
2797                 dev_priv->perf.oa.flex_regs =
2798                         flex_eu_config_tdl_2;
2799                 dev_priv->perf.oa.flex_regs_len =
2800                         ARRAY_SIZE(flex_eu_config_tdl_2);
2801
2802                 return 0;
2803         case METRIC_SET_ID_COMPUTE_EXTRA:
2804                 dev_priv->perf.oa.n_mux_configs =
2805                         get_compute_extra_mux_config(dev_priv,
2806                                                      dev_priv->perf.oa.mux_regs,
2807                                                      dev_priv->perf.oa.mux_regs_lens);
2808                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2809                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
2810
2811                         /* EINVAL because *_register_sysfs already checked this
2812                          * and so it wouldn't have been advertised to userspace and
2813                          * so shouldn't have been requested
2814                          */
2815                         return -EINVAL;
2816                 }
2817
2818                 dev_priv->perf.oa.b_counter_regs =
2819                         b_counter_config_compute_extra;
2820                 dev_priv->perf.oa.b_counter_regs_len =
2821                         ARRAY_SIZE(b_counter_config_compute_extra);
2822
2823                 dev_priv->perf.oa.flex_regs =
2824                         flex_eu_config_compute_extra;
2825                 dev_priv->perf.oa.flex_regs_len =
2826                         ARRAY_SIZE(flex_eu_config_compute_extra);
2827
2828                 return 0;
2829         case METRIC_SET_ID_VME_PIPE:
2830                 dev_priv->perf.oa.n_mux_configs =
2831                         get_vme_pipe_mux_config(dev_priv,
2832                                                 dev_priv->perf.oa.mux_regs,
2833                                                 dev_priv->perf.oa.mux_regs_lens);
2834                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2835                         DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
2836
2837                         /* EINVAL because *_register_sysfs already checked this
2838                          * and so it wouldn't have been advertised to userspace and
2839                          * so shouldn't have been requested
2840                          */
2841                         return -EINVAL;
2842                 }
2843
2844                 dev_priv->perf.oa.b_counter_regs =
2845                         b_counter_config_vme_pipe;
2846                 dev_priv->perf.oa.b_counter_regs_len =
2847                         ARRAY_SIZE(b_counter_config_vme_pipe);
2848
2849                 dev_priv->perf.oa.flex_regs =
2850                         flex_eu_config_vme_pipe;
2851                 dev_priv->perf.oa.flex_regs_len =
2852                         ARRAY_SIZE(flex_eu_config_vme_pipe);
2853
2854                 return 0;
2855         case METRIC_SET_ID_TEST_OA:
2856                 dev_priv->perf.oa.n_mux_configs =
2857                         get_test_oa_mux_config(dev_priv,
2858                                                dev_priv->perf.oa.mux_regs,
2859                                                dev_priv->perf.oa.mux_regs_lens);
2860                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2861                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2862
2863                         /* EINVAL because *_register_sysfs already checked this
2864                          * and so it wouldn't have been advertised to userspace and
2865                          * so shouldn't have been requested
2866                          */
2867                         return -EINVAL;
2868                 }
2869
2870                 dev_priv->perf.oa.b_counter_regs =
2871                         b_counter_config_test_oa;
2872                 dev_priv->perf.oa.b_counter_regs_len =
2873                         ARRAY_SIZE(b_counter_config_test_oa);
2874
2875                 dev_priv->perf.oa.flex_regs =
2876                         flex_eu_config_test_oa;
2877                 dev_priv->perf.oa.flex_regs_len =
2878                         ARRAY_SIZE(flex_eu_config_test_oa);
2879
2880                 return 0;
2881         default:
2882                 return -ENODEV;
2883         }
2884 }
2885
2886 static ssize_t
2887 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2888 {
2889         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2890 }
2891
2892 static struct device_attribute dev_attr_render_basic_id = {
2893         .attr = { .name = "id", .mode = 0444 },
2894         .show = show_render_basic_id,
2895         .store = NULL,
2896 };
2897
2898 static struct attribute *attrs_render_basic[] = {
2899         &dev_attr_render_basic_id.attr,
2900         NULL,
2901 };
2902
2903 static struct attribute_group group_render_basic = {
2904         .name = "f519e481-24d2-4d42-87c9-3fdd12c00202",
2905         .attrs =  attrs_render_basic,
2906 };
2907
2908 static ssize_t
2909 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2910 {
2911         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2912 }
2913
2914 static struct device_attribute dev_attr_compute_basic_id = {
2915         .attr = { .name = "id", .mode = 0444 },
2916         .show = show_compute_basic_id,
2917         .store = NULL,
2918 };
2919
2920 static struct attribute *attrs_compute_basic[] = {
2921         &dev_attr_compute_basic_id.attr,
2922         NULL,
2923 };
2924
2925 static struct attribute_group group_compute_basic = {
2926         .name = "fe47b29d-ae51-423e-bff4-27d965a95b60",
2927         .attrs =  attrs_compute_basic,
2928 };
2929
2930 static ssize_t
2931 show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2932 {
2933         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2934 }
2935
2936 static struct device_attribute dev_attr_render_pipe_profile_id = {
2937         .attr = { .name = "id", .mode = 0444 },
2938         .show = show_render_pipe_profile_id,
2939         .store = NULL,
2940 };
2941
2942 static struct attribute *attrs_render_pipe_profile[] = {
2943         &dev_attr_render_pipe_profile_id.attr,
2944         NULL,
2945 };
2946
2947 static struct attribute_group group_render_pipe_profile = {
2948         .name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774",
2949         .attrs =  attrs_render_pipe_profile,
2950 };
2951
2952 static ssize_t
2953 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
2954 {
2955         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
2956 }
2957
2958 static struct device_attribute dev_attr_memory_reads_id = {
2959         .attr = { .name = "id", .mode = 0444 },
2960         .show = show_memory_reads_id,
2961         .store = NULL,
2962 };
2963
2964 static struct attribute *attrs_memory_reads[] = {
2965         &dev_attr_memory_reads_id.attr,
2966         NULL,
2967 };
2968
2969 static struct attribute_group group_memory_reads = {
2970         .name = "9bc436dd-6130-4add-affc-283eb6eaa864",
2971         .attrs =  attrs_memory_reads,
2972 };
2973
2974 static ssize_t
2975 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
2976 {
2977         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
2978 }
2979
2980 static struct device_attribute dev_attr_memory_writes_id = {
2981         .attr = { .name = "id", .mode = 0444 },
2982         .show = show_memory_writes_id,
2983         .store = NULL,
2984 };
2985
2986 static struct attribute *attrs_memory_writes[] = {
2987         &dev_attr_memory_writes_id.attr,
2988         NULL,
2989 };
2990
2991 static struct attribute_group group_memory_writes = {
2992         .name = "2ea0da8f-3527-4669-9d9d-13099a7435bf",
2993         .attrs =  attrs_memory_writes,
2994 };
2995
2996 static ssize_t
2997 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
2998 {
2999         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
3000 }
3001
3002 static struct device_attribute dev_attr_compute_extended_id = {
3003         .attr = { .name = "id", .mode = 0444 },
3004         .show = show_compute_extended_id,
3005         .store = NULL,
3006 };
3007
3008 static struct attribute *attrs_compute_extended[] = {
3009         &dev_attr_compute_extended_id.attr,
3010         NULL,
3011 };
3012
3013 static struct attribute_group group_compute_extended = {
3014         .name = "d97d16af-028b-4cd1-a672-6210cb5513dd",
3015         .attrs =  attrs_compute_extended,
3016 };
3017
3018 static ssize_t
3019 show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
3020 {
3021         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
3022 }
3023
3024 static struct device_attribute dev_attr_compute_l3_cache_id = {
3025         .attr = { .name = "id", .mode = 0444 },
3026         .show = show_compute_l3_cache_id,
3027         .store = NULL,
3028 };
3029
3030 static struct attribute *attrs_compute_l3_cache[] = {
3031         &dev_attr_compute_l3_cache_id.attr,
3032         NULL,
3033 };
3034
3035 static struct attribute_group group_compute_l3_cache = {
3036         .name = "9fb22842-e708-43f7-9752-e0e41670c39e",
3037         .attrs =  attrs_compute_l3_cache,
3038 };
3039
3040 static ssize_t
3041 show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
3042 {
3043         return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
3044 }
3045
3046 static struct device_attribute dev_attr_hdc_and_sf_id = {
3047         .attr = { .name = "id", .mode = 0444 },
3048         .show = show_hdc_and_sf_id,
3049         .store = NULL,
3050 };
3051
3052 static struct attribute *attrs_hdc_and_sf[] = {
3053         &dev_attr_hdc_and_sf_id.attr,
3054         NULL,
3055 };
3056
3057 static struct attribute_group group_hdc_and_sf = {
3058         .name = "5378e2a1-4248-4188-a4ae-da25a794c603",
3059         .attrs =  attrs_hdc_and_sf,
3060 };
3061
3062 static ssize_t
3063 show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
3064 {
3065         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
3066 }
3067
3068 static struct device_attribute dev_attr_l3_1_id = {
3069         .attr = { .name = "id", .mode = 0444 },
3070         .show = show_l3_1_id,
3071         .store = NULL,
3072 };
3073
3074 static struct attribute *attrs_l3_1[] = {
3075         &dev_attr_l3_1_id.attr,
3076         NULL,
3077 };
3078
3079 static struct attribute_group group_l3_1 = {
3080         .name = "f42cdd6a-b000-42cb-870f-5eb423a7f514",
3081         .attrs =  attrs_l3_1,
3082 };
3083
3084 static ssize_t
3085 show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
3086 {
3087         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
3088 }
3089
3090 static struct device_attribute dev_attr_l3_2_id = {
3091         .attr = { .name = "id", .mode = 0444 },
3092         .show = show_l3_2_id,
3093         .store = NULL,
3094 };
3095
3096 static struct attribute *attrs_l3_2[] = {
3097         &dev_attr_l3_2_id.attr,
3098         NULL,
3099 };
3100
3101 static struct attribute_group group_l3_2 = {
3102         .name = "b9bf2423-d88c-4a7b-a051-627611d00dcc",
3103         .attrs =  attrs_l3_2,
3104 };
3105
3106 static ssize_t
3107 show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
3108 {
3109         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
3110 }
3111
3112 static struct device_attribute dev_attr_l3_3_id = {
3113         .attr = { .name = "id", .mode = 0444 },
3114         .show = show_l3_3_id,
3115         .store = NULL,
3116 };
3117
3118 static struct attribute *attrs_l3_3[] = {
3119         &dev_attr_l3_3_id.attr,
3120         NULL,
3121 };
3122
3123 static struct attribute_group group_l3_3 = {
3124         .name = "2414a93d-d84f-406e-99c0-472161194b40",
3125         .attrs =  attrs_l3_3,
3126 };
3127
3128 static ssize_t
3129 show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
3130 {
3131         return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
3132 }
3133
3134 static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
3135         .attr = { .name = "id", .mode = 0444 },
3136         .show = show_rasterizer_and_pixel_backend_id,
3137         .store = NULL,
3138 };
3139
3140 static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
3141         &dev_attr_rasterizer_and_pixel_backend_id.attr,
3142         NULL,
3143 };
3144
3145 static struct attribute_group group_rasterizer_and_pixel_backend = {
3146         .name = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5",
3147         .attrs =  attrs_rasterizer_and_pixel_backend,
3148 };
3149
3150 static ssize_t
3151 show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
3152 {
3153         return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
3154 }
3155
3156 static struct device_attribute dev_attr_sampler_id = {
3157         .attr = { .name = "id", .mode = 0444 },
3158         .show = show_sampler_id,
3159         .store = NULL,
3160 };
3161
3162 static struct attribute *attrs_sampler[] = {
3163         &dev_attr_sampler_id.attr,
3164         NULL,
3165 };
3166
3167 static struct attribute_group group_sampler = {
3168         .name = "b4cff514-a91e-4798-a0b3-426ca13fc9c1",
3169         .attrs =  attrs_sampler,
3170 };
3171
3172 static ssize_t
3173 show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
3174 {
3175         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
3176 }
3177
3178 static struct device_attribute dev_attr_tdl_1_id = {
3179         .attr = { .name = "id", .mode = 0444 },
3180         .show = show_tdl_1_id,
3181         .store = NULL,
3182 };
3183
3184 static struct attribute *attrs_tdl_1[] = {
3185         &dev_attr_tdl_1_id.attr,
3186         NULL,
3187 };
3188
3189 static struct attribute_group group_tdl_1 = {
3190         .name = "7821d13b-9b8b-4405-9618-78cd56b62cce",
3191         .attrs =  attrs_tdl_1,
3192 };
3193
3194 static ssize_t
3195 show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
3196 {
3197         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
3198 }
3199
3200 static struct device_attribute dev_attr_tdl_2_id = {
3201         .attr = { .name = "id", .mode = 0444 },
3202         .show = show_tdl_2_id,
3203         .store = NULL,
3204 };
3205
3206 static struct attribute *attrs_tdl_2[] = {
3207         &dev_attr_tdl_2_id.attr,
3208         NULL,
3209 };
3210
3211 static struct attribute_group group_tdl_2 = {
3212         .name = "893f1a4d-919d-4388-8cb7-746d73ea7259",
3213         .attrs =  attrs_tdl_2,
3214 };
3215
3216 static ssize_t
3217 show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
3218 {
3219         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
3220 }
3221
3222 static struct device_attribute dev_attr_compute_extra_id = {
3223         .attr = { .name = "id", .mode = 0444 },
3224         .show = show_compute_extra_id,
3225         .store = NULL,
3226 };
3227
3228 static struct attribute *attrs_compute_extra[] = {
3229         &dev_attr_compute_extra_id.attr,
3230         NULL,
3231 };
3232
3233 static struct attribute_group group_compute_extra = {
3234         .name = "41a24047-7484-4ead-ae37-de907e5ff2b2",
3235         .attrs =  attrs_compute_extra,
3236 };
3237
3238 static ssize_t
3239 show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
3240 {
3241         return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
3242 }
3243
3244 static struct device_attribute dev_attr_vme_pipe_id = {
3245         .attr = { .name = "id", .mode = 0444 },
3246         .show = show_vme_pipe_id,
3247         .store = NULL,
3248 };
3249
3250 static struct attribute *attrs_vme_pipe[] = {
3251         &dev_attr_vme_pipe_id.attr,
3252         NULL,
3253 };
3254
3255 static struct attribute_group group_vme_pipe = {
3256         .name = "95910492-943f-44bd-9461-390240f243fd",
3257         .attrs =  attrs_vme_pipe,
3258 };
3259
3260 static ssize_t
3261 show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
3262 {
3263         return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
3264 }
3265
3266 static struct device_attribute dev_attr_test_oa_id = {
3267         .attr = { .name = "id", .mode = 0444 },
3268         .show = show_test_oa_id,
3269         .store = NULL,
3270 };
3271
3272 static struct attribute *attrs_test_oa[] = {
3273         &dev_attr_test_oa_id.attr,
3274         NULL,
3275 };
3276
3277 static struct attribute_group group_test_oa = {
3278         .name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1",
3279         .attrs =  attrs_test_oa,
3280 };
3281
3282 int
3283 i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv)
3284 {
3285         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
3286         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
3287         int ret = 0;
3288
3289         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
3290                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
3291                 if (ret)
3292                         goto error_render_basic;
3293         }
3294         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
3295                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
3296                 if (ret)
3297                         goto error_compute_basic;
3298         }
3299         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
3300                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
3301                 if (ret)
3302                         goto error_render_pipe_profile;
3303         }
3304         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
3305                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
3306                 if (ret)
3307                         goto error_memory_reads;
3308         }
3309         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
3310                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
3311                 if (ret)
3312                         goto error_memory_writes;
3313         }
3314         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
3315                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
3316                 if (ret)
3317                         goto error_compute_extended;
3318         }
3319         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
3320                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
3321                 if (ret)
3322                         goto error_compute_l3_cache;
3323         }
3324         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
3325                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
3326                 if (ret)
3327                         goto error_hdc_and_sf;
3328         }
3329         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
3330                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
3331                 if (ret)
3332                         goto error_l3_1;
3333         }
3334         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
3335                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
3336                 if (ret)
3337                         goto error_l3_2;
3338         }
3339         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
3340                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
3341                 if (ret)
3342                         goto error_l3_3;
3343         }
3344         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
3345                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
3346                 if (ret)
3347                         goto error_rasterizer_and_pixel_backend;
3348         }
3349         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
3350                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
3351                 if (ret)
3352                         goto error_sampler;
3353         }
3354         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
3355                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
3356                 if (ret)
3357                         goto error_tdl_1;
3358         }
3359         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
3360                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
3361                 if (ret)
3362                         goto error_tdl_2;
3363         }
3364         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
3365                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
3366                 if (ret)
3367                         goto error_compute_extra;
3368         }
3369         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
3370                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
3371                 if (ret)
3372                         goto error_vme_pipe;
3373         }
3374         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
3375                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
3376                 if (ret)
3377                         goto error_test_oa;
3378         }
3379
3380         return 0;
3381
3382 error_test_oa:
3383         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
3384                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
3385 error_vme_pipe:
3386         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
3387                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
3388 error_compute_extra:
3389         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
3390                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
3391 error_tdl_2:
3392         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
3393                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
3394 error_tdl_1:
3395         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
3396                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
3397 error_sampler:
3398         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
3399                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
3400 error_rasterizer_and_pixel_backend:
3401         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
3402                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
3403 error_l3_3:
3404         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
3405                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
3406 error_l3_2:
3407         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
3408                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
3409 error_l3_1:
3410         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
3411                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
3412 error_hdc_and_sf:
3413         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
3414                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
3415 error_compute_l3_cache:
3416         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
3417                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
3418 error_compute_extended:
3419         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
3420                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
3421 error_memory_writes:
3422         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
3423                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
3424 error_memory_reads:
3425         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
3426                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
3427 error_render_pipe_profile:
3428         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
3429                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
3430 error_compute_basic:
3431         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
3432                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
3433 error_render_basic:
3434         return ret;
3435 }
3436
3437 void
3438 i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv)
3439 {
3440         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
3441         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
3442
3443         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
3444                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
3445         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
3446                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
3447         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
3448                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
3449         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
3450                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
3451         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
3452                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
3453         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
3454                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
3455         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
3456                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
3457         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
3458                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
3459         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
3460                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
3461         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
3462                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
3463         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
3464                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
3465         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
3466                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
3467         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
3468                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
3469         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
3470                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
3471         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
3472                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
3473         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
3474                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
3475         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
3476                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
3477         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
3478                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
3479 }