drivers/gpu/drm/i915/i915_oa_kblgt2.c

   1 /*
   2  * Autogenerated file by GPU Top : https://github.com/rib/gputop
   3  * DO NOT EDIT manually!
   4  *
   5  *
   6  * Copyright (c) 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysfs.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_oa_kblgt2.h"
  33
  34 enum metric_set_id {
  35         METRIC_SET_ID_RENDER_BASIC = 1,
  36         METRIC_SET_ID_COMPUTE_BASIC,
  37         METRIC_SET_ID_RENDER_PIPE_PROFILE,
  38         METRIC_SET_ID_MEMORY_READS,
  39         METRIC_SET_ID_MEMORY_WRITES,
  40         METRIC_SET_ID_COMPUTE_EXTENDED,
  41         METRIC_SET_ID_COMPUTE_L3_CACHE,
  42         METRIC_SET_ID_HDC_AND_SF,
  43         METRIC_SET_ID_L3_1,
  44         METRIC_SET_ID_L3_2,
  45         METRIC_SET_ID_L3_3,
  46         METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
  47         METRIC_SET_ID_SAMPLER,
  48         METRIC_SET_ID_TDL_1,
  49         METRIC_SET_ID_TDL_2,
  50         METRIC_SET_ID_COMPUTE_EXTRA,
  51         METRIC_SET_ID_VME_PIPE,
  52         METRIC_SET_ID_TEST_OA,
  53 };
  54
  55 int i915_oa_n_builtin_metric_sets_kblgt2 = 18;
  56
  57 static const struct i915_oa_reg b_counter_config_render_basic[] = {
  58         { _MMIO(0x2710), 0x00000000 },
  59         { _MMIO(0x2714), 0x00800000 },
  60         { _MMIO(0x2720), 0x00000000 },
  61         { _MMIO(0x2724), 0x00800000 },
  62         { _MMIO(0x2740), 0x00000000 },
  63 };
  64
  65 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
  66         { _MMIO(0xe458), 0x00005004 },
  67         { _MMIO(0xe558), 0x00010003 },
  68         { _MMIO(0xe658), 0x00012011 },
  69         { _MMIO(0xe758), 0x00015014 },
  70         { _MMIO(0xe45c), 0x00051050 },
  71         { _MMIO(0xe55c), 0x00053052 },
  72         { _MMIO(0xe65c), 0x00055054 },
  73 };
  74
  75 static const struct i915_oa_reg mux_config_render_basic[] = {
  76         { _MMIO(0x9888), 0x166c01e0 },
  77         { _MMIO(0x9888), 0x12170280 },
  78         { _MMIO(0x9888), 0x12370280 },
  79         { _MMIO(0x9888), 0x11930317 },
  80         { _MMIO(0x9888), 0x159303df },
  81         { _MMIO(0x9888), 0x3f900003 },
  82         { _MMIO(0x9888), 0x1a4e0080 },
  83         { _MMIO(0x9888), 0x0a6c0053 },
  84         { _MMIO(0x9888), 0x106c0000 },
  85         { _MMIO(0x9888), 0x1c6c0000 },
  86         { _MMIO(0x9888), 0x0a1b4000 },
  87         { _MMIO(0x9888), 0x1c1c0001 },
  88         { _MMIO(0x9888), 0x002f1000 },
  89         { _MMIO(0x9888), 0x042f1000 },
  90         { _MMIO(0x9888), 0x004c4000 },
  91         { _MMIO(0x9888), 0x0a4c8400 },
  92         { _MMIO(0x9888), 0x000d2000 },
  93         { _MMIO(0x9888), 0x060d8000 },
  94         { _MMIO(0x9888), 0x080da000 },
  95         { _MMIO(0x9888), 0x0a0d2000 },
  96         { _MMIO(0x9888), 0x0c0f0400 },
  97         { _MMIO(0x9888), 0x0e0f6600 },
  98         { _MMIO(0x9888), 0x002c8000 },
  99         { _MMIO(0x9888), 0x162c2200 },
 100         { _MMIO(0x9888), 0x062d8000 },
 101         { _MMIO(0x9888), 0x082d8000 },
 102         { _MMIO(0x9888), 0x00133000 },
 103         { _MMIO(0x9888), 0x08133000 },
 104         { _MMIO(0x9888), 0x00170020 },
 105         { _MMIO(0x9888), 0x08170021 },
 106         { _MMIO(0x9888), 0x10170000 },
 107         { _MMIO(0x9888), 0x0633c000 },
 108         { _MMIO(0x9888), 0x0833c000 },
 109         { _MMIO(0x9888), 0x06370800 },
 110         { _MMIO(0x9888), 0x08370840 },
 111         { _MMIO(0x9888), 0x10370000 },
 112         { _MMIO(0x9888), 0x0d933031 },
 113         { _MMIO(0x9888), 0x0f933e3f },
 114         { _MMIO(0x9888), 0x01933d00 },
 115         { _MMIO(0x9888), 0x0393073c },
 116         { _MMIO(0x9888), 0x0593000e },
 117         { _MMIO(0x9888), 0x1d930000 },
 118         { _MMIO(0x9888), 0x19930000 },
 119         { _MMIO(0x9888), 0x1b930000 },
 120         { _MMIO(0x9888), 0x1d900157 },
 121         { _MMIO(0x9888), 0x1f900158 },
 122         { _MMIO(0x9888), 0x35900000 },
 123         { _MMIO(0x9888), 0x2b908000 },
 124         { _MMIO(0x9888), 0x2d908000 },
 125         { _MMIO(0x9888), 0x2f908000 },
 126         { _MMIO(0x9888), 0x31908000 },
 127         { _MMIO(0x9888), 0x15908000 },
 128         { _MMIO(0x9888), 0x17908000 },
 129         { _MMIO(0x9888), 0x19908000 },
 130         { _MMIO(0x9888), 0x1b908000 },
 131         { _MMIO(0x9888), 0x1190001f },
 132         { _MMIO(0x9888), 0x51904400 },
 133         { _MMIO(0x9888), 0x41900020 },
 134         { _MMIO(0x9888), 0x55900000 },
 135         { _MMIO(0x9888), 0x45900c21 },
 136         { _MMIO(0x9888), 0x47900061 },
 137         { _MMIO(0x9888), 0x57904440 },
 138         { _MMIO(0x9888), 0x49900000 },
 139         { _MMIO(0x9888), 0x37900000 },
 140         { _MMIO(0x9888), 0x33900000 },
 141         { _MMIO(0x9888), 0x4b900000 },
 142         { _MMIO(0x9888), 0x59900004 },
 143         { _MMIO(0x9888), 0x43900000 },
 144         { _MMIO(0x9888), 0x53904444 },
 145 };
 146
 147 static int
 148 get_render_basic_mux_config(struct drm_i915_private *dev_priv,
 149                             const struct i915_oa_reg **regs,
 150                             int *lens)
 151 {
 152         int n = 0;
 153
 154         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 155         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 156
 157         regs[n] = mux_config_render_basic;
 158         lens[n] = ARRAY_SIZE(mux_config_render_basic);
 159         n++;
 160
 161         return n;
 162 }
 163
 164 static const struct i915_oa_reg b_counter_config_compute_basic[] = {
 165         { _MMIO(0x2710), 0x00000000 },
 166         { _MMIO(0x2714), 0x00800000 },
 167         { _MMIO(0x2720), 0x00000000 },
 168         { _MMIO(0x2724), 0x00800000 },
 169         { _MMIO(0x2740), 0x00000000 },
 170 };
 171
 172 static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
 173         { _MMIO(0xe458), 0x00005004 },
 174         { _MMIO(0xe558), 0x00000003 },
 175         { _MMIO(0xe658), 0x00002001 },
 176         { _MMIO(0xe758), 0x00778008 },
 177         { _MMIO(0xe45c), 0x00088078 },
 178         { _MMIO(0xe55c), 0x00808708 },
 179         { _MMIO(0xe65c), 0x00a08908 },
 180 };
 181
 182 static const struct i915_oa_reg mux_config_compute_basic[] = {
 183         { _MMIO(0x9888), 0x104f00e0 },
 184         { _MMIO(0x9888), 0x124f1c00 },
 185         { _MMIO(0x9888), 0x106c00e0 },
 186         { _MMIO(0x9888), 0x37906800 },
 187         { _MMIO(0x9888), 0x3f900003 },
 188         { _MMIO(0x9888), 0x004e8000 },
 189         { _MMIO(0x9888), 0x1a4e0820 },
 190         { _MMIO(0x9888), 0x1c4e0002 },
 191         { _MMIO(0x9888), 0x064f0900 },
 192         { _MMIO(0x9888), 0x084f0032 },
 193         { _MMIO(0x9888), 0x0a4f1891 },
 194         { _MMIO(0x9888), 0x0c4f0e00 },
 195         { _MMIO(0x9888), 0x0e4f003c },
 196         { _MMIO(0x9888), 0x004f0d80 },
 197         { _MMIO(0x9888), 0x024f003b },
 198         { _MMIO(0x9888), 0x006c0002 },
 199         { _MMIO(0x9888), 0x086c0100 },
 200         { _MMIO(0x9888), 0x0c6c000c },
 201         { _MMIO(0x9888), 0x0e6c0b00 },
 202         { _MMIO(0x9888), 0x186c0000 },
 203         { _MMIO(0x9888), 0x1c6c0000 },
 204         { _MMIO(0x9888), 0x1e6c0000 },
 205         { _MMIO(0x9888), 0x001b4000 },
 206         { _MMIO(0x9888), 0x081b8000 },
 207         { _MMIO(0x9888), 0x0c1b4000 },
 208         { _MMIO(0x9888), 0x0e1b8000 },
 209         { _MMIO(0x9888), 0x101c8000 },
 210         { _MMIO(0x9888), 0x1a1c8000 },
 211         { _MMIO(0x9888), 0x1c1c0024 },
 212         { _MMIO(0x9888), 0x065b8000 },
 213         { _MMIO(0x9888), 0x085b4000 },
 214         { _MMIO(0x9888), 0x0a5bc000 },
 215         { _MMIO(0x9888), 0x0c5b8000 },
 216         { _MMIO(0x9888), 0x0e5b4000 },
 217         { _MMIO(0x9888), 0x005b8000 },
 218         { _MMIO(0x9888), 0x025b4000 },
 219         { _MMIO(0x9888), 0x1a5c6000 },
 220         { _MMIO(0x9888), 0x1c5c001b },
 221         { _MMIO(0x9888), 0x125c8000 },
 222         { _MMIO(0x9888), 0x145c8000 },
 223         { _MMIO(0x9888), 0x004c8000 },
 224         { _MMIO(0x9888), 0x0a4c2000 },
 225         { _MMIO(0x9888), 0x0c4c0208 },
 226         { _MMIO(0x9888), 0x000da000 },
 227         { _MMIO(0x9888), 0x060d8000 },
 228         { _MMIO(0x9888), 0x080da000 },
 229         { _MMIO(0x9888), 0x0a0da000 },
 230         { _MMIO(0x9888), 0x0c0da000 },
 231         { _MMIO(0x9888), 0x0e0da000 },
 232         { _MMIO(0x9888), 0x020d2000 },
 233         { _MMIO(0x9888), 0x0c0f5400 },
 234         { _MMIO(0x9888), 0x0e0f5500 },
 235         { _MMIO(0x9888), 0x100f0155 },
 236         { _MMIO(0x9888), 0x002c8000 },
 237         { _MMIO(0x9888), 0x0e2cc000 },
 238         { _MMIO(0x9888), 0x162cfb00 },
 239         { _MMIO(0x9888), 0x182c00be },
 240         { _MMIO(0x9888), 0x022cc000 },
 241         { _MMIO(0x9888), 0x042cc000 },
 242         { _MMIO(0x9888), 0x19900157 },
 243         { _MMIO(0x9888), 0x1b900158 },
 244         { _MMIO(0x9888), 0x1d900105 },
 245         { _MMIO(0x9888), 0x1f900103 },
 246         { _MMIO(0x9888), 0x35900000 },
 247         { _MMIO(0x9888), 0x11900fff },
 248         { _MMIO(0x9888), 0x51900000 },
 249         { _MMIO(0x9888), 0x41900800 },
 250         { _MMIO(0x9888), 0x55900000 },
 251         { _MMIO(0x9888), 0x45900821 },
 252         { _MMIO(0x9888), 0x47900802 },
 253         { _MMIO(0x9888), 0x57900000 },
 254         { _MMIO(0x9888), 0x49900802 },
 255         { _MMIO(0x9888), 0x33900000 },
 256         { _MMIO(0x9888), 0x4b900002 },
 257         { _MMIO(0x9888), 0x59900000 },
 258         { _MMIO(0x9888), 0x43900422 },
 259         { _MMIO(0x9888), 0x53904444 },
 260 };
 261
 262 static int
 263 get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
 264                              const struct i915_oa_reg **regs,
 265                              int *lens)
 266 {
 267         int n = 0;
 268
 269         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 270         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 271
 272         regs[n] = mux_config_compute_basic;
 273         lens[n] = ARRAY_SIZE(mux_config_compute_basic);
 274         n++;
 275
 276         return n;
 277 }
 278
 279 static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
 280         { _MMIO(0x2724), 0xf0800000 },
 281         { _MMIO(0x2720), 0x00000000 },
 282         { _MMIO(0x2714), 0xf0800000 },
 283         { _MMIO(0x2710), 0x00000000 },
 284         { _MMIO(0x2740), 0x00000000 },
 285         { _MMIO(0x2770), 0x0007ffea },
 286         { _MMIO(0x2774), 0x00007ffc },
 287         { _MMIO(0x2778), 0x0007affa },
 288         { _MMIO(0x277c), 0x0000f5fd },
 289         { _MMIO(0x2780), 0x00079ffa },
 290         { _MMIO(0x2784), 0x0000f3fb },
 291         { _MMIO(0x2788), 0x0007bf7a },
 292         { _MMIO(0x278c), 0x0000f7e7 },
 293         { _MMIO(0x2790), 0x0007fefa },
 294         { _MMIO(0x2794), 0x0000f7cf },
 295         { _MMIO(0x2798), 0x00077ffa },
 296         { _MMIO(0x279c), 0x0000efdf },
 297         { _MMIO(0x27a0), 0x0006fffa },
 298         { _MMIO(0x27a4), 0x0000cfbf },
 299         { _MMIO(0x27a8), 0x0003fffa },
 300         { _MMIO(0x27ac), 0x00005f7f },
 301 };
 302
 303 static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
 304         { _MMIO(0xe458), 0x00005004 },
 305         { _MMIO(0xe558), 0x00015014 },
 306         { _MMIO(0xe658), 0x00025024 },
 307         { _MMIO(0xe758), 0x00035034 },
 308         { _MMIO(0xe45c), 0x00045044 },
 309         { _MMIO(0xe55c), 0x00055054 },
 310         { _MMIO(0xe65c), 0x00065064 },
 311 };
 312
 313 static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
 314         { _MMIO(0x9888), 0x0c0e001f },
 315         { _MMIO(0x9888), 0x0a0f0000 },
 316         { _MMIO(0x9888), 0x10116800 },
 317         { _MMIO(0x9888), 0x178a03e0 },
 318         { _MMIO(0x9888), 0x11824c00 },
 319         { _MMIO(0x9888), 0x11830020 },
 320         { _MMIO(0x9888), 0x13840020 },
 321         { _MMIO(0x9888), 0x11850019 },
 322         { _MMIO(0x9888), 0x11860007 },
 323         { _MMIO(0x9888), 0x01870c40 },
 324         { _MMIO(0x9888), 0x17880000 },
 325         { _MMIO(0x9888), 0x022f4000 },
 326         { _MMIO(0x9888), 0x0a4c0040 },
 327         { _MMIO(0x9888), 0x0c0d8000 },
 328         { _MMIO(0x9888), 0x040d4000 },
 329         { _MMIO(0x9888), 0x060d2000 },
 330         { _MMIO(0x9888), 0x020e5400 },
 331         { _MMIO(0x9888), 0x000e0000 },
 332         { _MMIO(0x9888), 0x080f0040 },
 333         { _MMIO(0x9888), 0x000f0000 },
 334         { _MMIO(0x9888), 0x100f0000 },
 335         { _MMIO(0x9888), 0x0e0f0040 },
 336         { _MMIO(0x9888), 0x0c2c8000 },
 337         { _MMIO(0x9888), 0x06104000 },
 338         { _MMIO(0x9888), 0x06110012 },
 339         { _MMIO(0x9888), 0x06131000 },
 340         { _MMIO(0x9888), 0x01898000 },
 341         { _MMIO(0x9888), 0x0d890100 },
 342         { _MMIO(0x9888), 0x03898000 },
 343         { _MMIO(0x9888), 0x09808000 },
 344         { _MMIO(0x9888), 0x0b808000 },
 345         { _MMIO(0x9888), 0x0380c000 },
 346         { _MMIO(0x9888), 0x0f8a0075 },
 347         { _MMIO(0x9888), 0x1d8a0000 },
 348         { _MMIO(0x9888), 0x118a8000 },
 349         { _MMIO(0x9888), 0x1b8a4000 },
 350         { _MMIO(0x9888), 0x138a8000 },
 351         { _MMIO(0x9888), 0x1d81a000 },
 352         { _MMIO(0x9888), 0x15818000 },
 353         { _MMIO(0x9888), 0x17818000 },
 354         { _MMIO(0x9888), 0x0b820030 },
 355         { _MMIO(0x9888), 0x07828000 },
 356         { _MMIO(0x9888), 0x0d824000 },
 357         { _MMIO(0x9888), 0x0f828000 },
 358         { _MMIO(0x9888), 0x05824000 },
 359         { _MMIO(0x9888), 0x0d830003 },
 360         { _MMIO(0x9888), 0x0583000c },
 361         { _MMIO(0x9888), 0x09830000 },
 362         { _MMIO(0x9888), 0x03838000 },
 363         { _MMIO(0x9888), 0x07838000 },
 364         { _MMIO(0x9888), 0x0b840980 },
 365         { _MMIO(0x9888), 0x03844d80 },
 366         { _MMIO(0x9888), 0x11840000 },
 367         { _MMIO(0x9888), 0x09848000 },
 368         { _MMIO(0x9888), 0x09850080 },
 369         { _MMIO(0x9888), 0x03850003 },
 370         { _MMIO(0x9888), 0x01850000 },
 371         { _MMIO(0x9888), 0x07860000 },
 372         { _MMIO(0x9888), 0x0f860400 },
 373         { _MMIO(0x9888), 0x09870032 },
 374         { _MMIO(0x9888), 0x01888052 },
 375         { _MMIO(0x9888), 0x11880000 },
 376         { _MMIO(0x9888), 0x09884000 },
 377         { _MMIO(0x9888), 0x1b931001 },
 378         { _MMIO(0x9888), 0x1d930001 },
 379         { _MMIO(0x9888), 0x19934000 },
 380         { _MMIO(0x9888), 0x1b958000 },
 381         { _MMIO(0x9888), 0x1d950094 },
 382         { _MMIO(0x9888), 0x19958000 },
 383         { _MMIO(0x9888), 0x09e58000 },
 384         { _MMIO(0x9888), 0x0be58000 },
 385         { _MMIO(0x9888), 0x03e5c000 },
 386         { _MMIO(0x9888), 0x0592c000 },
 387         { _MMIO(0x9888), 0x0b928000 },
 388         { _MMIO(0x9888), 0x0d924000 },
 389         { _MMIO(0x9888), 0x0f924000 },
 390         { _MMIO(0x9888), 0x11928000 },
 391         { _MMIO(0x9888), 0x1392c000 },
 392         { _MMIO(0x9888), 0x09924000 },
 393         { _MMIO(0x9888), 0x01985000 },
 394         { _MMIO(0x9888), 0x07988000 },
 395         { _MMIO(0x9888), 0x09981000 },
 396         { _MMIO(0x9888), 0x0b982000 },
 397         { _MMIO(0x9888), 0x0d982000 },
 398         { _MMIO(0x9888), 0x0f989000 },
 399         { _MMIO(0x9888), 0x05982000 },
 400         { _MMIO(0x9888), 0x13904000 },
 401         { _MMIO(0x9888), 0x21904000 },
 402         { _MMIO(0x9888), 0x23904000 },
 403         { _MMIO(0x9888), 0x25908000 },
 404         { _MMIO(0x9888), 0x27904000 },
 405         { _MMIO(0x9888), 0x29908000 },
 406         { _MMIO(0x9888), 0x2b904000 },
 407         { _MMIO(0x9888), 0x2f904000 },
 408         { _MMIO(0x9888), 0x31904000 },
 409         { _MMIO(0x9888), 0x15904000 },
 410         { _MMIO(0x9888), 0x17908000 },
 411         { _MMIO(0x9888), 0x19908000 },
 412         { _MMIO(0x9888), 0x1b904000 },
 413         { _MMIO(0x9888), 0x1190c080 },
 414         { _MMIO(0x9888), 0x51900000 },
 415         { _MMIO(0x9888), 0x41900440 },
 416         { _MMIO(0x9888), 0x55900000 },
 417         { _MMIO(0x9888), 0x45900400 },
 418         { _MMIO(0x9888), 0x47900c21 },
 419         { _MMIO(0x9888), 0x57900400 },
 420         { _MMIO(0x9888), 0x49900042 },
 421         { _MMIO(0x9888), 0x37900000 },
 422         { _MMIO(0x9888), 0x33900000 },
 423         { _MMIO(0x9888), 0x4b900024 },
 424         { _MMIO(0x9888), 0x59900000 },
 425         { _MMIO(0x9888), 0x43900841 },
 426         { _MMIO(0x9888), 0x53900400 },
 427 };
 428
 429 static int
 430 get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
 431                                    const struct i915_oa_reg **regs,
 432                                    int *lens)
 433 {
 434         int n = 0;
 435
 436         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 437         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 438
 439         regs[n] = mux_config_render_pipe_profile;
 440         lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
 441         n++;
 442
 443         return n;
 444 }
 445
 446 static const struct i915_oa_reg b_counter_config_memory_reads[] = {
 447         { _MMIO(0x272c), 0xffffffff },
 448         { _MMIO(0x2728), 0xffffffff },
 449         { _MMIO(0x2724), 0xf0800000 },
 450         { _MMIO(0x2720), 0x00000000 },
 451         { _MMIO(0x271c), 0xffffffff },
 452         { _MMIO(0x2718), 0xffffffff },
 453         { _MMIO(0x2714), 0xf0800000 },
 454         { _MMIO(0x2710), 0x00000000 },
 455         { _MMIO(0x274c), 0x86543210 },
 456         { _MMIO(0x2748), 0x86543210 },
 457         { _MMIO(0x2744), 0x00006667 },
 458         { _MMIO(0x2740), 0x00000000 },
 459         { _MMIO(0x275c), 0x86543210 },
 460         { _MMIO(0x2758), 0x86543210 },
 461         { _MMIO(0x2754), 0x00006465 },
 462         { _MMIO(0x2750), 0x00000000 },
 463         { _MMIO(0x2770), 0x0007f81a },
 464         { _MMIO(0x2774), 0x0000fe00 },
 465         { _MMIO(0x2778), 0x0007f82a },
 466         { _MMIO(0x277c), 0x0000fe00 },
 467         { _MMIO(0x2780), 0x0007f872 },
 468         { _MMIO(0x2784), 0x0000fe00 },
 469         { _MMIO(0x2788), 0x0007f8ba },
 470         { _MMIO(0x278c), 0x0000fe00 },
 471         { _MMIO(0x2790), 0x0007f87a },
 472         { _MMIO(0x2794), 0x0000fe00 },
 473         { _MMIO(0x2798), 0x0007f8ea },
 474         { _MMIO(0x279c), 0x0000fe00 },
 475         { _MMIO(0x27a0), 0x0007f8e2 },
 476         { _MMIO(0x27a4), 0x0000fe00 },
 477         { _MMIO(0x27a8), 0x0007f8f2 },
 478         { _MMIO(0x27ac), 0x0000fe00 },
 479 };
 480
 481 static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
 482         { _MMIO(0xe458), 0x00005004 },
 483         { _MMIO(0xe558), 0x00015014 },
 484         { _MMIO(0xe658), 0x00025024 },
 485         { _MMIO(0xe758), 0x00035034 },
 486         { _MMIO(0xe45c), 0x00045044 },
 487         { _MMIO(0xe55c), 0x00055054 },
 488         { _MMIO(0xe65c), 0x00065064 },
 489 };
 490
 491 static const struct i915_oa_reg mux_config_memory_reads[] = {
 492         { _MMIO(0x9888), 0x11810c00 },
 493         { _MMIO(0x9888), 0x1381001a },
 494         { _MMIO(0x9888), 0x37906800 },
 495         { _MMIO(0x9888), 0x3f900064 },
 496         { _MMIO(0x9888), 0x03811300 },
 497         { _MMIO(0x9888), 0x05811b12 },
 498         { _MMIO(0x9888), 0x0781001a },
 499         { _MMIO(0x9888), 0x1f810000 },
 500         { _MMIO(0x9888), 0x17810000 },
 501         { _MMIO(0x9888), 0x19810000 },
 502         { _MMIO(0x9888), 0x1b810000 },
 503         { _MMIO(0x9888), 0x1d810000 },
 504         { _MMIO(0x9888), 0x1b930055 },
 505         { _MMIO(0x9888), 0x03e58000 },
 506         { _MMIO(0x9888), 0x05e5c000 },
 507         { _MMIO(0x9888), 0x07e54000 },
 508         { _MMIO(0x9888), 0x13900150 },
 509         { _MMIO(0x9888), 0x21900151 },
 510         { _MMIO(0x9888), 0x23900152 },
 511         { _MMIO(0x9888), 0x25900153 },
 512         { _MMIO(0x9888), 0x27900154 },
 513         { _MMIO(0x9888), 0x29900155 },
 514         { _MMIO(0x9888), 0x2b900156 },
 515         { _MMIO(0x9888), 0x2d900157 },
 516         { _MMIO(0x9888), 0x2f90015f },
 517         { _MMIO(0x9888), 0x31900105 },
 518         { _MMIO(0x9888), 0x15900103 },
 519         { _MMIO(0x9888), 0x17900101 },
 520         { _MMIO(0x9888), 0x35900000 },
 521         { _MMIO(0x9888), 0x19908000 },
 522         { _MMIO(0x9888), 0x1b908000 },
 523         { _MMIO(0x9888), 0x1d908000 },
 524         { _MMIO(0x9888), 0x1f908000 },
 525         { _MMIO(0x9888), 0x11900000 },
 526         { _MMIO(0x9888), 0x51900000 },
 527         { _MMIO(0x9888), 0x41900c60 },
 528         { _MMIO(0x9888), 0x55900000 },
 529         { _MMIO(0x9888), 0x45900c00 },
 530         { _MMIO(0x9888), 0x47900c63 },
 531         { _MMIO(0x9888), 0x57900000 },
 532         { _MMIO(0x9888), 0x49900c63 },
 533         { _MMIO(0x9888), 0x33900000 },
 534         { _MMIO(0x9888), 0x4b900063 },
 535         { _MMIO(0x9888), 0x59900000 },
 536         { _MMIO(0x9888), 0x43900003 },
 537         { _MMIO(0x9888), 0x53900000 },
 538 };
 539
 540 static int
 541 get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
 542                             const struct i915_oa_reg **regs,
 543                             int *lens)
 544 {
 545         int n = 0;
 546
 547         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 548         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 549
 550         regs[n] = mux_config_memory_reads;
 551         lens[n] = ARRAY_SIZE(mux_config_memory_reads);
 552         n++;
 553
 554         return n;
 555 }
 556
 557 static const struct i915_oa_reg b_counter_config_memory_writes[] = {
 558         { _MMIO(0x272c), 0xffffffff },
 559         { _MMIO(0x2728), 0xffffffff },
 560         { _MMIO(0x2724), 0xf0800000 },
 561         { _MMIO(0x2720), 0x00000000 },
 562         { _MMIO(0x271c), 0xffffffff },
 563         { _MMIO(0x2718), 0xffffffff },
 564         { _MMIO(0x2714), 0xf0800000 },
 565         { _MMIO(0x2710), 0x00000000 },
 566         { _MMIO(0x274c), 0x86543210 },
 567         { _MMIO(0x2748), 0x86543210 },
 568         { _MMIO(0x2744), 0x00006667 },
 569         { _MMIO(0x2740), 0x00000000 },
 570         { _MMIO(0x275c), 0x86543210 },
 571         { _MMIO(0x2758), 0x86543210 },
 572         { _MMIO(0x2754), 0x00006465 },
 573         { _MMIO(0x2750), 0x00000000 },
 574         { _MMIO(0x2770), 0x0007f81a },
 575         { _MMIO(0x2774), 0x0000fe00 },
 576         { _MMIO(0x2778), 0x0007f82a },
 577         { _MMIO(0x277c), 0x0000fe00 },
 578         { _MMIO(0x2780), 0x0007f822 },
 579         { _MMIO(0x2784), 0x0000fe00 },
 580         { _MMIO(0x2788), 0x0007f8ba },
 581         { _MMIO(0x278c), 0x0000fe00 },
 582         { _MMIO(0x2790), 0x0007f87a },
 583         { _MMIO(0x2794), 0x0000fe00 },
 584         { _MMIO(0x2798), 0x0007f8ea },
 585         { _MMIO(0x279c), 0x0000fe00 },
 586         { _MMIO(0x27a0), 0x0007f8e2 },
 587         { _MMIO(0x27a4), 0x0000fe00 },
 588         { _MMIO(0x27a8), 0x0007f8f2 },
 589         { _MMIO(0x27ac), 0x0000fe00 },
 590 };
 591
 592 static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
 593         { _MMIO(0xe458), 0x00005004 },
 594         { _MMIO(0xe558), 0x00015014 },
 595         { _MMIO(0xe658), 0x00025024 },
 596         { _MMIO(0xe758), 0x00035034 },
 597         { _MMIO(0xe45c), 0x00045044 },
 598         { _MMIO(0xe55c), 0x00055054 },
 599         { _MMIO(0xe65c), 0x00065064 },
 600 };
 601
 602 static const struct i915_oa_reg mux_config_memory_writes[] = {
 603         { _MMIO(0x9888), 0x11810c00 },
 604         { _MMIO(0x9888), 0x1381001a },
 605         { _MMIO(0x9888), 0x37906800 },
 606         { _MMIO(0x9888), 0x3f901000 },
 607         { _MMIO(0x9888), 0x03811300 },
 608         { _MMIO(0x9888), 0x05811b12 },
 609         { _MMIO(0x9888), 0x0781001a },
 610         { _MMIO(0x9888), 0x1f810000 },
 611         { _MMIO(0x9888), 0x17810000 },
 612         { _MMIO(0x9888), 0x19810000 },
 613         { _MMIO(0x9888), 0x1b810000 },
 614         { _MMIO(0x9888), 0x1d810000 },
 615         { _MMIO(0x9888), 0x1b930055 },
 616         { _MMIO(0x9888), 0x03e58000 },
 617         { _MMIO(0x9888), 0x05e5c000 },
 618         { _MMIO(0x9888), 0x07e54000 },
 619         { _MMIO(0x9888), 0x13900160 },
 620         { _MMIO(0x9888), 0x21900161 },
 621         { _MMIO(0x9888), 0x23900162 },
 622         { _MMIO(0x9888), 0x25900163 },
 623         { _MMIO(0x9888), 0x27900164 },
 624         { _MMIO(0x9888), 0x29900165 },
 625         { _MMIO(0x9888), 0x2b900166 },
 626         { _MMIO(0x9888), 0x2d900167 },
 627         { _MMIO(0x9888), 0x2f900150 },
 628         { _MMIO(0x9888), 0x31900105 },
 629         { _MMIO(0x9888), 0x15900103 },
 630         { _MMIO(0x9888), 0x17900101 },
 631         { _MMIO(0x9888), 0x35900000 },
 632         { _MMIO(0x9888), 0x19908000 },
 633         { _MMIO(0x9888), 0x1b908000 },
 634         { _MMIO(0x9888), 0x1d908000 },
 635         { _MMIO(0x9888), 0x1f908000 },
 636         { _MMIO(0x9888), 0x11900000 },
 637         { _MMIO(0x9888), 0x51900000 },
 638         { _MMIO(0x9888), 0x41900c60 },
 639         { _MMIO(0x9888), 0x55900000 },
 640         { _MMIO(0x9888), 0x45900c00 },
 641         { _MMIO(0x9888), 0x47900c63 },
 642         { _MMIO(0x9888), 0x57900000 },
 643         { _MMIO(0x9888), 0x49900c63 },
 644         { _MMIO(0x9888), 0x33900000 },
 645         { _MMIO(0x9888), 0x4b900063 },
 646         { _MMIO(0x9888), 0x59900000 },
 647         { _MMIO(0x9888), 0x43900003 },
 648         { _MMIO(0x9888), 0x53900000 },
 649 };
 650
 651 static int
 652 get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
 653                              const struct i915_oa_reg **regs,
 654                              int *lens)
 655 {
 656         int n = 0;
 657
 658         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 659         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 660
 661         regs[n] = mux_config_memory_writes;
 662         lens[n] = ARRAY_SIZE(mux_config_memory_writes);
 663         n++;
 664
 665         return n;
 666 }
 667
 668 static const struct i915_oa_reg b_counter_config_compute_extended[] = {
 669         { _MMIO(0x2724), 0xf0800000 },
 670         { _MMIO(0x2720), 0x00000000 },
 671         { _MMIO(0x2714), 0xf0800000 },
 672         { _MMIO(0x2710), 0x00000000 },
 673         { _MMIO(0x2740), 0x00000000 },
 674         { _MMIO(0x2770), 0x0007fc2a },
 675         { _MMIO(0x2774), 0x0000bf00 },
 676         { _MMIO(0x2778), 0x0007fc6a },
 677         { _MMIO(0x277c), 0x0000bf00 },
 678         { _MMIO(0x2780), 0x0007fc92 },
 679         { _MMIO(0x2784), 0x0000bf00 },
 680         { _MMIO(0x2788), 0x0007fca2 },
 681         { _MMIO(0x278c), 0x0000bf00 },
 682         { _MMIO(0x2790), 0x0007fc32 },
 683         { _MMIO(0x2794), 0x0000bf00 },
 684         { _MMIO(0x2798), 0x0007fc9a },
 685         { _MMIO(0x279c), 0x0000bf00 },
 686         { _MMIO(0x27a0), 0x0007fe6a },
 687         { _MMIO(0x27a4), 0x0000bf00 },
 688         { _MMIO(0x27a8), 0x0007fe7a },
 689         { _MMIO(0x27ac), 0x0000bf00 },
 690 };
 691
 692 static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
 693         { _MMIO(0xe458), 0x00005004 },
 694         { _MMIO(0xe558), 0x00000003 },
 695         { _MMIO(0xe658), 0x00002001 },
 696         { _MMIO(0xe758), 0x00778008 },
 697         { _MMIO(0xe45c), 0x00088078 },
 698         { _MMIO(0xe55c), 0x00808708 },
 699         { _MMIO(0xe65c), 0x00a08908 },
 700 };
 701
 702 static const struct i915_oa_reg mux_config_compute_extended[] = {
 703         { _MMIO(0x9888), 0x106c00e0 },
 704         { _MMIO(0x9888), 0x141c8160 },
 705         { _MMIO(0x9888), 0x161c8015 },
 706         { _MMIO(0x9888), 0x181c0120 },
 707         { _MMIO(0x9888), 0x004e8000 },
 708         { _MMIO(0x9888), 0x0e4e8000 },
 709         { _MMIO(0x9888), 0x184e8000 },
 710         { _MMIO(0x9888), 0x1a4eaaa0 },
 711         { _MMIO(0x9888), 0x1c4e0002 },
 712         { _MMIO(0x9888), 0x024e8000 },
 713         { _MMIO(0x9888), 0x044e8000 },
 714         { _MMIO(0x9888), 0x064e8000 },
 715         { _MMIO(0x9888), 0x084e8000 },
 716         { _MMIO(0x9888), 0x0a4e8000 },
 717         { _MMIO(0x9888), 0x0e6c0b01 },
 718         { _MMIO(0x9888), 0x006c0200 },
 719         { _MMIO(0x9888), 0x026c000c },
 720         { _MMIO(0x9888), 0x1c6c0000 },
 721         { _MMIO(0x9888), 0x1e6c0000 },
 722         { _MMIO(0x9888), 0x1a6c0000 },
 723         { _MMIO(0x9888), 0x0e1bc000 },
 724         { _MMIO(0x9888), 0x001b8000 },
 725         { _MMIO(0x9888), 0x021bc000 },
 726         { _MMIO(0x9888), 0x001c0041 },
 727         { _MMIO(0x9888), 0x061c4200 },
 728         { _MMIO(0x9888), 0x081c4443 },
 729         { _MMIO(0x9888), 0x0a1c4645 },
 730         { _MMIO(0x9888), 0x0c1c7647 },
 731         { _MMIO(0x9888), 0x041c7357 },
 732         { _MMIO(0x9888), 0x1c1c0030 },
 733         { _MMIO(0x9888), 0x101c0000 },
 734         { _MMIO(0x9888), 0x1a1c0000 },
 735         { _MMIO(0x9888), 0x121c8000 },
 736         { _MMIO(0x9888), 0x004c8000 },
 737         { _MMIO(0x9888), 0x0a4caa2a },
 738         { _MMIO(0x9888), 0x0c4c02aa },
 739         { _MMIO(0x9888), 0x084ca000 },
 740         { _MMIO(0x9888), 0x000da000 },
 741         { _MMIO(0x9888), 0x060d8000 },
 742         { _MMIO(0x9888), 0x080da000 },
 743         { _MMIO(0x9888), 0x0a0da000 },
 744         { _MMIO(0x9888), 0x0c0da000 },
 745         { _MMIO(0x9888), 0x0e0da000 },
 746         { _MMIO(0x9888), 0x020da000 },
 747         { _MMIO(0x9888), 0x040da000 },
 748         { _MMIO(0x9888), 0x0c0f5400 },
 749         { _MMIO(0x9888), 0x0e0f5515 },
 750         { _MMIO(0x9888), 0x100f0155 },
 751         { _MMIO(0x9888), 0x002c8000 },
 752         { _MMIO(0x9888), 0x0e2c8000 },
 753         { _MMIO(0x9888), 0x162caa00 },
 754         { _MMIO(0x9888), 0x182c00aa },
 755         { _MMIO(0x9888), 0x022c8000 },
 756         { _MMIO(0x9888), 0x042c8000 },
 757         { _MMIO(0x9888), 0x062c8000 },
 758         { _MMIO(0x9888), 0x082c8000 },
 759         { _MMIO(0x9888), 0x0a2c8000 },
 760         { _MMIO(0x9888), 0x11907fff },
 761         { _MMIO(0x9888), 0x51900000 },
 762         { _MMIO(0x9888), 0x41900040 },
 763         { _MMIO(0x9888), 0x55900000 },
 764         { _MMIO(0x9888), 0x45900802 },
 765         { _MMIO(0x9888), 0x47900842 },
 766         { _MMIO(0x9888), 0x57900000 },
 767         { _MMIO(0x9888), 0x49900842 },
 768         { _MMIO(0x9888), 0x37900000 },
 769         { _MMIO(0x9888), 0x33900000 },
 770         { _MMIO(0x9888), 0x4b900000 },
 771         { _MMIO(0x9888), 0x59900000 },
 772         { _MMIO(0x9888), 0x43900800 },
 773         { _MMIO(0x9888), 0x53900000 },
 774 };
 775
 776 static int
 777 get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
 778                                 const struct i915_oa_reg **regs,
 779                                 int *lens)
 780 {
 781         int n = 0;
 782
 783         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 784         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 785
 786         regs[n] = mux_config_compute_extended;
 787         lens[n] = ARRAY_SIZE(mux_config_compute_extended);
 788         n++;
 789
 790         return n;
 791 }
 792
 793 static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
 794         { _MMIO(0x2710), 0x00000000 },
 795         { _MMIO(0x2714), 0x30800000 },
 796         { _MMIO(0x2720), 0x00000000 },
 797         { _MMIO(0x2724), 0x30800000 },
 798         { _MMIO(0x2740), 0x00000000 },
 799         { _MMIO(0x2770), 0x0007fffa },
 800         { _MMIO(0x2774), 0x0000fefe },
 801         { _MMIO(0x2778), 0x0007fffa },
 802         { _MMIO(0x277c), 0x0000fefd },
 803         { _MMIO(0x2790), 0x0007fffa },
 804         { _MMIO(0x2794), 0x0000fbef },
 805         { _MMIO(0x2798), 0x0007fffa },
 806         { _MMIO(0x279c), 0x0000fbdf },
 807 };
 808
 809 static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
 810         { _MMIO(0xe458), 0x00005004 },
 811         { _MMIO(0xe558), 0x00000003 },
 812         { _MMIO(0xe658), 0x00002001 },
 813         { _MMIO(0xe758), 0x00101100 },
 814         { _MMIO(0xe45c), 0x00201200 },
 815         { _MMIO(0xe55c), 0x00301300 },
 816         { _MMIO(0xe65c), 0x00401400 },
 817 };
 818
 819 static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
 820         { _MMIO(0x9888), 0x166c0760 },
 821         { _MMIO(0x9888), 0x1593001e },
 822         { _MMIO(0x9888), 0x3f900003 },
 823         { _MMIO(0x9888), 0x004e8000 },
 824         { _MMIO(0x9888), 0x0e4e8000 },
 825         { _MMIO(0x9888), 0x184e8000 },
 826         { _MMIO(0x9888), 0x1a4e8020 },
 827         { _MMIO(0x9888), 0x1c4e0002 },
 828         { _MMIO(0x9888), 0x006c0051 },
 829         { _MMIO(0x9888), 0x066c5000 },
 830         { _MMIO(0x9888), 0x086c5c5d },
 831         { _MMIO(0x9888), 0x0e6c5e5f },
 832         { _MMIO(0x9888), 0x106c0000 },
 833         { _MMIO(0x9888), 0x186c0000 },
 834         { _MMIO(0x9888), 0x1c6c0000 },
 835         { _MMIO(0x9888), 0x1e6c0000 },
 836         { _MMIO(0x9888), 0x001b4000 },
 837         { _MMIO(0x9888), 0x061b8000 },
 838         { _MMIO(0x9888), 0x081bc000 },
 839         { _MMIO(0x9888), 0x0e1bc000 },
 840         { _MMIO(0x9888), 0x101c8000 },
 841         { _MMIO(0x9888), 0x1a1ce000 },
 842         { _MMIO(0x9888), 0x1c1c0030 },
 843         { _MMIO(0x9888), 0x004c8000 },
 844         { _MMIO(0x9888), 0x0a4c2a00 },
 845         { _MMIO(0x9888), 0x0c4c0280 },
 846         { _MMIO(0x9888), 0x000d2000 },
 847         { _MMIO(0x9888), 0x060d8000 },
 848         { _MMIO(0x9888), 0x080da000 },
 849         { _MMIO(0x9888), 0x0e0da000 },
 850         { _MMIO(0x9888), 0x0c0f0400 },
 851         { _MMIO(0x9888), 0x0e0f1500 },
 852         { _MMIO(0x9888), 0x100f0140 },
 853         { _MMIO(0x9888), 0x002c8000 },
 854         { _MMIO(0x9888), 0x0e2c8000 },
 855         { _MMIO(0x9888), 0x162c0a00 },
 856         { _MMIO(0x9888), 0x182c00a0 },
 857         { _MMIO(0x9888), 0x03933300 },
 858         { _MMIO(0x9888), 0x05930032 },
 859         { _MMIO(0x9888), 0x11930000 },
 860         { _MMIO(0x9888), 0x1b930000 },
 861         { _MMIO(0x9888), 0x1d900157 },
 862         { _MMIO(0x9888), 0x1f900158 },
 863         { _MMIO(0x9888), 0x35900000 },
 864         { _MMIO(0x9888), 0x19908000 },
 865         { _MMIO(0x9888), 0x1b908000 },
 866         { _MMIO(0x9888), 0x1190030f },
 867         { _MMIO(0x9888), 0x51900000 },
 868         { _MMIO(0x9888), 0x41900000 },
 869         { _MMIO(0x9888), 0x55900000 },
 870         { _MMIO(0x9888), 0x45900021 },
 871         { _MMIO(0x9888), 0x47900000 },
 872         { _MMIO(0x9888), 0x37900000 },
 873         { _MMIO(0x9888), 0x33900000 },
 874         { _MMIO(0x9888), 0x57900000 },
 875         { _MMIO(0x9888), 0x4b900000 },
 876         { _MMIO(0x9888), 0x59900000 },
 877         { _MMIO(0x9888), 0x53904444 },
 878         { _MMIO(0x9888), 0x43900000 },
 879 };
 880
 881 static int
 882 get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
 883                                 const struct i915_oa_reg **regs,
 884                                 int *lens)
 885 {
 886         int n = 0;
 887
 888         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 889         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 890
 891         regs[n] = mux_config_compute_l3_cache;
 892         lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
 893         n++;
 894
 895         return n;
 896 }
 897
 898 static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
 899         { _MMIO(0x2740), 0x00000000 },
 900         { _MMIO(0x2744), 0x00800000 },
 901         { _MMIO(0x2710), 0x00000000 },
 902         { _MMIO(0x2714), 0x10800000 },
 903         { _MMIO(0x2720), 0x00000000 },
 904         { _MMIO(0x2724), 0x00800000 },
 905         { _MMIO(0x2770), 0x00000002 },
 906         { _MMIO(0x2774), 0x0000fdff },
 907 };
 908
 909 static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
 910         { _MMIO(0xe458), 0x00005004 },
 911         { _MMIO(0xe558), 0x00010003 },
 912         { _MMIO(0xe658), 0x00012011 },
 913         { _MMIO(0xe758), 0x00015014 },
 914         { _MMIO(0xe45c), 0x00051050 },
 915         { _MMIO(0xe55c), 0x00053052 },
 916         { _MMIO(0xe65c), 0x00055054 },
 917 };
 918
 919 static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
 920         { _MMIO(0x9888), 0x104f0232 },
 921         { _MMIO(0x9888), 0x124f4640 },
 922         { _MMIO(0x9888), 0x106c0232 },
 923         { _MMIO(0x9888), 0x11834400 },
 924         { _MMIO(0x9888), 0x0a4e8000 },
 925         { _MMIO(0x9888), 0x0c4e8000 },
 926         { _MMIO(0x9888), 0x004f1880 },
 927         { _MMIO(0x9888), 0x024f08bb },
 928         { _MMIO(0x9888), 0x044f001b },
 929         { _MMIO(0x9888), 0x046c0100 },
 930         { _MMIO(0x9888), 0x066c000b },
 931         { _MMIO(0x9888), 0x1a6c0000 },
 932         { _MMIO(0x9888), 0x041b8000 },
 933         { _MMIO(0x9888), 0x061b4000 },
 934         { _MMIO(0x9888), 0x1a1c1800 },
 935         { _MMIO(0x9888), 0x005b8000 },
 936         { _MMIO(0x9888), 0x025bc000 },
 937         { _MMIO(0x9888), 0x045b4000 },
 938         { _MMIO(0x9888), 0x125c8000 },
 939         { _MMIO(0x9888), 0x145c8000 },
 940         { _MMIO(0x9888), 0x165c8000 },
 941         { _MMIO(0x9888), 0x185c8000 },
 942         { _MMIO(0x9888), 0x0a4c00a0 },
 943         { _MMIO(0x9888), 0x000d8000 },
 944         { _MMIO(0x9888), 0x020da000 },
 945         { _MMIO(0x9888), 0x040da000 },
 946         { _MMIO(0x9888), 0x060d2000 },
 947         { _MMIO(0x9888), 0x0c0f5000 },
 948         { _MMIO(0x9888), 0x0e0f0055 },
 949         { _MMIO(0x9888), 0x022cc000 },
 950         { _MMIO(0x9888), 0x042cc000 },
 951         { _MMIO(0x9888), 0x062cc000 },
 952         { _MMIO(0x9888), 0x082cc000 },
 953         { _MMIO(0x9888), 0x0a2c8000 },
 954         { _MMIO(0x9888), 0x0c2c8000 },
 955         { _MMIO(0x9888), 0x0f828000 },
 956         { _MMIO(0x9888), 0x0f8305c0 },
 957         { _MMIO(0x9888), 0x09830000 },
 958         { _MMIO(0x9888), 0x07830000 },
 959         { _MMIO(0x9888), 0x1d950080 },
 960         { _MMIO(0x9888), 0x13928000 },
 961         { _MMIO(0x9888), 0x0f988000 },
 962         { _MMIO(0x9888), 0x31904000 },
 963         { _MMIO(0x9888), 0x1190fc00 },
 964         { _MMIO(0x9888), 0x37900000 },
 965         { _MMIO(0x9888), 0x59900000 },
 966         { _MMIO(0x9888), 0x4b900040 },
 967         { _MMIO(0x9888), 0x51900000 },
 968         { _MMIO(0x9888), 0x41900800 },
 969         { _MMIO(0x9888), 0x43900842 },
 970         { _MMIO(0x9888), 0x53900000 },
 971         { _MMIO(0x9888), 0x45900000 },
 972         { _MMIO(0x9888), 0x33900000 },
 973 };
 974
 975 static int
 976 get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
 977                           const struct i915_oa_reg **regs,
 978                           int *lens)
 979 {
 980         int n = 0;
 981
 982         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 983         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 984
 985         regs[n] = mux_config_hdc_and_sf;
 986         lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
 987         n++;
 988
 989         return n;
 990 }
 991
 992 static const struct i915_oa_reg b_counter_config_l3_1[] = {
 993         { _MMIO(0x2740), 0x00000000 },
 994         { _MMIO(0x2744), 0x00800000 },
 995         { _MMIO(0x2710), 0x00000000 },
 996         { _MMIO(0x2714), 0xf0800000 },
 997         { _MMIO(0x2720), 0x00000000 },
 998         { _MMIO(0x2724), 0xf0800000 },
 999         { _MMIO(0x2770), 0x00100070 },
1000         { _MMIO(0x2774), 0x0000fff1 },
1001         { _MMIO(0x2778), 0x00014002 },
1002         { _MMIO(0x277c), 0x0000c3ff },
1003         { _MMIO(0x2780), 0x00010002 },
1004         { _MMIO(0x2784), 0x0000c7ff },
1005         { _MMIO(0x2788), 0x00004002 },
1006         { _MMIO(0x278c), 0x0000d3ff },
1007         { _MMIO(0x2790), 0x00100700 },
1008         { _MMIO(0x2794), 0x0000ff1f },
1009         { _MMIO(0x2798), 0x00001402 },
1010         { _MMIO(0x279c), 0x0000fc3f },
1011         { _MMIO(0x27a0), 0x00001002 },
1012         { _MMIO(0x27a4), 0x0000fc7f },
1013         { _MMIO(0x27a8), 0x00000402 },
1014         { _MMIO(0x27ac), 0x0000fd3f },
1015 };
1016
1017 static const struct i915_oa_reg flex_eu_config_l3_1[] = {
1018         { _MMIO(0xe458), 0x00005004 },
1019         { _MMIO(0xe558), 0x00010003 },
1020         { _MMIO(0xe658), 0x00012011 },
1021         { _MMIO(0xe758), 0x00015014 },
1022         { _MMIO(0xe45c), 0x00051050 },
1023         { _MMIO(0xe55c), 0x00053052 },
1024         { _MMIO(0xe65c), 0x00055054 },
1025 };
1026
1027 static const struct i915_oa_reg mux_config_l3_1[] = {
1028         { _MMIO(0x9888), 0x126c7b40 },
1029         { _MMIO(0x9888), 0x166c0020 },
1030         { _MMIO(0x9888), 0x0a603444 },
1031         { _MMIO(0x9888), 0x0a613400 },
1032         { _MMIO(0x9888), 0x1a4ea800 },
1033         { _MMIO(0x9888), 0x1c4e0002 },
1034         { _MMIO(0x9888), 0x024e8000 },
1035         { _MMIO(0x9888), 0x044e8000 },
1036         { _MMIO(0x9888), 0x064e8000 },
1037         { _MMIO(0x9888), 0x084e8000 },
1038         { _MMIO(0x9888), 0x0a4e8000 },
1039         { _MMIO(0x9888), 0x064f4000 },
1040         { _MMIO(0x9888), 0x0c6c5327 },
1041         { _MMIO(0x9888), 0x0e6c5425 },
1042         { _MMIO(0x9888), 0x006c2a00 },
1043         { _MMIO(0x9888), 0x026c285b },
1044         { _MMIO(0x9888), 0x046c005c },
1045         { _MMIO(0x9888), 0x106c0000 },
1046         { _MMIO(0x9888), 0x1c6c0000 },
1047         { _MMIO(0x9888), 0x1e6c0000 },
1048         { _MMIO(0x9888), 0x1a6c0800 },
1049         { _MMIO(0x9888), 0x0c1bc000 },
1050         { _MMIO(0x9888), 0x0e1bc000 },
1051         { _MMIO(0x9888), 0x001b8000 },
1052         { _MMIO(0x9888), 0x021bc000 },
1053         { _MMIO(0x9888), 0x041bc000 },
1054         { _MMIO(0x9888), 0x1c1c003c },
1055         { _MMIO(0x9888), 0x121c8000 },
1056         { _MMIO(0x9888), 0x141c8000 },
1057         { _MMIO(0x9888), 0x161c8000 },
1058         { _MMIO(0x9888), 0x181c8000 },
1059         { _MMIO(0x9888), 0x1a1c0800 },
1060         { _MMIO(0x9888), 0x065b4000 },
1061         { _MMIO(0x9888), 0x1a5c1000 },
1062         { _MMIO(0x9888), 0x10600000 },
1063         { _MMIO(0x9888), 0x04600000 },
1064         { _MMIO(0x9888), 0x0c610044 },
1065         { _MMIO(0x9888), 0x10610000 },
1066         { _MMIO(0x9888), 0x06610000 },
1067         { _MMIO(0x9888), 0x0c4c02a8 },
1068         { _MMIO(0x9888), 0x084ca000 },
1069         { _MMIO(0x9888), 0x0a4c002a },
1070         { _MMIO(0x9888), 0x0c0da000 },
1071         { _MMIO(0x9888), 0x0e0da000 },
1072         { _MMIO(0x9888), 0x000d8000 },
1073         { _MMIO(0x9888), 0x020da000 },
1074         { _MMIO(0x9888), 0x040da000 },
1075         { _MMIO(0x9888), 0x060d2000 },
1076         { _MMIO(0x9888), 0x100f0154 },
1077         { _MMIO(0x9888), 0x0c0f5000 },
1078         { _MMIO(0x9888), 0x0e0f0055 },
1079         { _MMIO(0x9888), 0x182c00aa },
1080         { _MMIO(0x9888), 0x022c8000 },
1081         { _MMIO(0x9888), 0x042c8000 },
1082         { _MMIO(0x9888), 0x062c8000 },
1083         { _MMIO(0x9888), 0x082c8000 },
1084         { _MMIO(0x9888), 0x0a2c8000 },
1085         { _MMIO(0x9888), 0x0c2cc000 },
1086         { _MMIO(0x9888), 0x1190ffc0 },
1087         { _MMIO(0x9888), 0x57900000 },
1088         { _MMIO(0x9888), 0x49900420 },
1089         { _MMIO(0x9888), 0x37900000 },
1090         { _MMIO(0x9888), 0x33900000 },
1091         { _MMIO(0x9888), 0x4b900021 },
1092         { _MMIO(0x9888), 0x59900000 },
1093         { _MMIO(0x9888), 0x51900000 },
1094         { _MMIO(0x9888), 0x41900400 },
1095         { _MMIO(0x9888), 0x43900421 },
1096         { _MMIO(0x9888), 0x53900000 },
1097         { _MMIO(0x9888), 0x45900040 },
1098 };
1099
1100 static int
1101 get_l3_1_mux_config(struct drm_i915_private *dev_priv,
1102                     const struct i915_oa_reg **regs,
1103                     int *lens)
1104 {
1105         int n = 0;
1106
1107         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1108         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1109
1110         regs[n] = mux_config_l3_1;
1111         lens[n] = ARRAY_SIZE(mux_config_l3_1);
1112         n++;
1113
1114         return n;
1115 }
1116
1117 static const struct i915_oa_reg b_counter_config_l3_2[] = {
1118         { _MMIO(0x2740), 0x00000000 },
1119         { _MMIO(0x2744), 0x00800000 },
1120         { _MMIO(0x2710), 0x00000000 },
1121         { _MMIO(0x2714), 0xf0800000 },
1122         { _MMIO(0x2720), 0x00000000 },
1123         { _MMIO(0x2724), 0x00800000 },
1124         { _MMIO(0x2770), 0x00100070 },
1125         { _MMIO(0x2774), 0x0000fff1 },
1126         { _MMIO(0x2778), 0x00028002 },
1127         { _MMIO(0x277c), 0x000087ff },
1128         { _MMIO(0x2780), 0x00020002 },
1129         { _MMIO(0x2784), 0x00008fff },
1130         { _MMIO(0x2788), 0x00008002 },
1131         { _MMIO(0x278c), 0x0000a7ff },
1132 };
1133
1134 static const struct i915_oa_reg flex_eu_config_l3_2[] = {
1135         { _MMIO(0xe458), 0x00005004 },
1136         { _MMIO(0xe558), 0x00010003 },
1137         { _MMIO(0xe658), 0x00012011 },
1138         { _MMIO(0xe758), 0x00015014 },
1139         { _MMIO(0xe45c), 0x00051050 },
1140         { _MMIO(0xe55c), 0x00053052 },
1141         { _MMIO(0xe65c), 0x00055054 },
1142 };
1143
1144 static const struct i915_oa_reg mux_config_l3_2[] = {
1145         { _MMIO(0x9888), 0x126c02e0 },
1146         { _MMIO(0x9888), 0x146c0001 },
1147         { _MMIO(0x9888), 0x0a623400 },
1148         { _MMIO(0x9888), 0x044e8000 },
1149         { _MMIO(0x9888), 0x064e8000 },
1150         { _MMIO(0x9888), 0x084e8000 },
1151         { _MMIO(0x9888), 0x0a4e8000 },
1152         { _MMIO(0x9888), 0x064f4000 },
1153         { _MMIO(0x9888), 0x026c3324 },
1154         { _MMIO(0x9888), 0x046c3422 },
1155         { _MMIO(0x9888), 0x106c0000 },
1156         { _MMIO(0x9888), 0x1a6c0000 },
1157         { _MMIO(0x9888), 0x021bc000 },
1158         { _MMIO(0x9888), 0x041bc000 },
1159         { _MMIO(0x9888), 0x141c8000 },
1160         { _MMIO(0x9888), 0x161c8000 },
1161         { _MMIO(0x9888), 0x181c8000 },
1162         { _MMIO(0x9888), 0x1a1c0800 },
1163         { _MMIO(0x9888), 0x065b4000 },
1164         { _MMIO(0x9888), 0x1a5c1000 },
1165         { _MMIO(0x9888), 0x06614000 },
1166         { _MMIO(0x9888), 0x0c620044 },
1167         { _MMIO(0x9888), 0x10620000 },
1168         { _MMIO(0x9888), 0x06620000 },
1169         { _MMIO(0x9888), 0x084c8000 },
1170         { _MMIO(0x9888), 0x0a4c002a },
1171         { _MMIO(0x9888), 0x020da000 },
1172         { _MMIO(0x9888), 0x040da000 },
1173         { _MMIO(0x9888), 0x060d2000 },
1174         { _MMIO(0x9888), 0x0c0f4000 },
1175         { _MMIO(0x9888), 0x0e0f0055 },
1176         { _MMIO(0x9888), 0x042c8000 },
1177         { _MMIO(0x9888), 0x062c8000 },
1178         { _MMIO(0x9888), 0x082c8000 },
1179         { _MMIO(0x9888), 0x0a2c8000 },
1180         { _MMIO(0x9888), 0x0c2cc000 },
1181         { _MMIO(0x9888), 0x1190f800 },
1182         { _MMIO(0x9888), 0x37900000 },
1183         { _MMIO(0x9888), 0x51900000 },
1184         { _MMIO(0x9888), 0x43900000 },
1185         { _MMIO(0x9888), 0x53900000 },
1186         { _MMIO(0x9888), 0x45900000 },
1187         { _MMIO(0x9888), 0x33900000 },
1188 };
1189
1190 static int
1191 get_l3_2_mux_config(struct drm_i915_private *dev_priv,
1192                     const struct i915_oa_reg **regs,
1193                     int *lens)
1194 {
1195         int n = 0;
1196
1197         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1198         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1199
1200         regs[n] = mux_config_l3_2;
1201         lens[n] = ARRAY_SIZE(mux_config_l3_2);
1202         n++;
1203
1204         return n;
1205 }
1206
1207 static const struct i915_oa_reg b_counter_config_l3_3[] = {
1208         { _MMIO(0x2740), 0x00000000 },
1209         { _MMIO(0x2744), 0x00800000 },
1210         { _MMIO(0x2710), 0x00000000 },
1211         { _MMIO(0x2714), 0xf0800000 },
1212         { _MMIO(0x2720), 0x00000000 },
1213         { _MMIO(0x2724), 0x00800000 },
1214         { _MMIO(0x2770), 0x00100070 },
1215         { _MMIO(0x2774), 0x0000fff1 },
1216         { _MMIO(0x2778), 0x00028002 },
1217         { _MMIO(0x277c), 0x000087ff },
1218         { _MMIO(0x2780), 0x00020002 },
1219         { _MMIO(0x2784), 0x00008fff },
1220         { _MMIO(0x2788), 0x00008002 },
1221         { _MMIO(0x278c), 0x0000a7ff },
1222 };
1223
1224 static const struct i915_oa_reg flex_eu_config_l3_3[] = {
1225         { _MMIO(0xe458), 0x00005004 },
1226         { _MMIO(0xe558), 0x00010003 },
1227         { _MMIO(0xe658), 0x00012011 },
1228         { _MMIO(0xe758), 0x00015014 },
1229         { _MMIO(0xe45c), 0x00051050 },
1230         { _MMIO(0xe55c), 0x00053052 },
1231         { _MMIO(0xe65c), 0x00055054 },
1232 };
1233
1234 static const struct i915_oa_reg mux_config_l3_3[] = {
1235         { _MMIO(0x9888), 0x126c4e80 },
1236         { _MMIO(0x9888), 0x146c0000 },
1237         { _MMIO(0x9888), 0x0a633400 },
1238         { _MMIO(0x9888), 0x044e8000 },
1239         { _MMIO(0x9888), 0x064e8000 },
1240         { _MMIO(0x9888), 0x084e8000 },
1241         { _MMIO(0x9888), 0x0a4e8000 },
1242         { _MMIO(0x9888), 0x0c4e8000 },
1243         { _MMIO(0x9888), 0x026c3321 },
1244         { _MMIO(0x9888), 0x046c342f },
1245         { _MMIO(0x9888), 0x106c0000 },
1246         { _MMIO(0x9888), 0x1a6c2000 },
1247         { _MMIO(0x9888), 0x021bc000 },
1248         { _MMIO(0x9888), 0x041bc000 },
1249         { _MMIO(0x9888), 0x061b4000 },
1250         { _MMIO(0x9888), 0x141c8000 },
1251         { _MMIO(0x9888), 0x161c8000 },
1252         { _MMIO(0x9888), 0x181c8000 },
1253         { _MMIO(0x9888), 0x1a1c1800 },
1254         { _MMIO(0x9888), 0x06604000 },
1255         { _MMIO(0x9888), 0x0c630044 },
1256         { _MMIO(0x9888), 0x10630000 },
1257         { _MMIO(0x9888), 0x06630000 },
1258         { _MMIO(0x9888), 0x084c8000 },
1259         { _MMIO(0x9888), 0x0a4c00aa },
1260         { _MMIO(0x9888), 0x020da000 },
1261         { _MMIO(0x9888), 0x040da000 },
1262         { _MMIO(0x9888), 0x060d2000 },
1263         { _MMIO(0x9888), 0x0c0f4000 },
1264         { _MMIO(0x9888), 0x0e0f0055 },
1265         { _MMIO(0x9888), 0x042c8000 },
1266         { _MMIO(0x9888), 0x062c8000 },
1267         { _MMIO(0x9888), 0x082c8000 },
1268         { _MMIO(0x9888), 0x0a2c8000 },
1269         { _MMIO(0x9888), 0x0c2c8000 },
1270         { _MMIO(0x9888), 0x1190f800 },
1271         { _MMIO(0x9888), 0x37900000 },
1272         { _MMIO(0x9888), 0x51900000 },
1273         { _MMIO(0x9888), 0x43900842 },
1274         { _MMIO(0x9888), 0x53900000 },
1275         { _MMIO(0x9888), 0x45900002 },
1276         { _MMIO(0x9888), 0x33900000 },
1277 };
1278
1279 static int
1280 get_l3_3_mux_config(struct drm_i915_private *dev_priv,
1281                     const struct i915_oa_reg **regs,
1282                     int *lens)
1283 {
1284         int n = 0;
1285
1286         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1287         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1288
1289         regs[n] = mux_config_l3_3;
1290         lens[n] = ARRAY_SIZE(mux_config_l3_3);
1291         n++;
1292
1293         return n;
1294 }
1295
1296 static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1297         { _MMIO(0x2740), 0x00000000 },
1298         { _MMIO(0x2744), 0x00800000 },
1299         { _MMIO(0x2710), 0x00000000 },
1300         { _MMIO(0x2714), 0x30800000 },
1301         { _MMIO(0x2720), 0x00000000 },
1302         { _MMIO(0x2724), 0x00800000 },
1303         { _MMIO(0x2770), 0x00000002 },
1304         { _MMIO(0x2774), 0x0000efff },
1305         { _MMIO(0x2778), 0x00006000 },
1306         { _MMIO(0x277c), 0x0000f3ff },
1307 };
1308
1309 static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1310         { _MMIO(0xe458), 0x00005004 },
1311         { _MMIO(0xe558), 0x00010003 },
1312         { _MMIO(0xe658), 0x00012011 },
1313         { _MMIO(0xe758), 0x00015014 },
1314         { _MMIO(0xe45c), 0x00051050 },
1315         { _MMIO(0xe55c), 0x00053052 },
1316         { _MMIO(0xe65c), 0x00055054 },
1317 };
1318
1319 static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1320         { _MMIO(0x9888), 0x102f3800 },
1321         { _MMIO(0x9888), 0x144d0500 },
1322         { _MMIO(0x9888), 0x120d03c0 },
1323         { _MMIO(0x9888), 0x140d03cf },
1324         { _MMIO(0x9888), 0x0c0f0004 },
1325         { _MMIO(0x9888), 0x0c4e4000 },
1326         { _MMIO(0x9888), 0x042f0480 },
1327         { _MMIO(0x9888), 0x082f0000 },
1328         { _MMIO(0x9888), 0x022f0000 },
1329         { _MMIO(0x9888), 0x0a4c0090 },
1330         { _MMIO(0x9888), 0x064d0027 },
1331         { _MMIO(0x9888), 0x004d0000 },
1332         { _MMIO(0x9888), 0x000d0d40 },
1333         { _MMIO(0x9888), 0x020d803f },
1334         { _MMIO(0x9888), 0x040d8023 },
1335         { _MMIO(0x9888), 0x100d0000 },
1336         { _MMIO(0x9888), 0x060d2000 },
1337         { _MMIO(0x9888), 0x020f0010 },
1338         { _MMIO(0x9888), 0x000f0000 },
1339         { _MMIO(0x9888), 0x0e0f0050 },
1340         { _MMIO(0x9888), 0x0a2c8000 },
1341         { _MMIO(0x9888), 0x0c2c8000 },
1342         { _MMIO(0x9888), 0x1190fc00 },
1343         { _MMIO(0x9888), 0x37900000 },
1344         { _MMIO(0x9888), 0x51900000 },
1345         { _MMIO(0x9888), 0x41901400 },
1346         { _MMIO(0x9888), 0x43901485 },
1347         { _MMIO(0x9888), 0x53900000 },
1348         { _MMIO(0x9888), 0x45900001 },
1349         { _MMIO(0x9888), 0x33900000 },
1350 };
1351
1352 static int
1353 get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1354                                             const struct i915_oa_reg **regs,
1355                                             int *lens)
1356 {
1357         int n = 0;
1358
1359         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1360         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1361
1362         regs[n] = mux_config_rasterizer_and_pixel_backend;
1363         lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1364         n++;
1365
1366         return n;
1367 }
1368
1369 static const struct i915_oa_reg b_counter_config_sampler[] = {
1370         { _MMIO(0x2740), 0x00000000 },
1371         { _MMIO(0x2744), 0x00800000 },
1372         { _MMIO(0x2710), 0x00000000 },
1373         { _MMIO(0x2714), 0x70800000 },
1374         { _MMIO(0x2720), 0x00000000 },
1375         { _MMIO(0x2724), 0x00800000 },
1376         { _MMIO(0x2770), 0x0000c000 },
1377         { _MMIO(0x2774), 0x0000e7ff },
1378         { _MMIO(0x2778), 0x00003000 },
1379         { _MMIO(0x277c), 0x0000f9ff },
1380         { _MMIO(0x2780), 0x00000c00 },
1381         { _MMIO(0x2784), 0x0000fe7f },
1382 };
1383
1384 static const struct i915_oa_reg flex_eu_config_sampler[] = {
1385         { _MMIO(0xe458), 0x00005004 },
1386         { _MMIO(0xe558), 0x00010003 },
1387         { _MMIO(0xe658), 0x00012011 },
1388         { _MMIO(0xe758), 0x00015014 },
1389         { _MMIO(0xe45c), 0x00051050 },
1390         { _MMIO(0xe55c), 0x00053052 },
1391         { _MMIO(0xe65c), 0x00055054 },
1392 };
1393
1394 static const struct i915_oa_reg mux_config_sampler[] = {
1395         { _MMIO(0x9888), 0x14152c00 },
1396         { _MMIO(0x9888), 0x16150005 },
1397         { _MMIO(0x9888), 0x121600a0 },
1398         { _MMIO(0x9888), 0x14352c00 },
1399         { _MMIO(0x9888), 0x16350005 },
1400         { _MMIO(0x9888), 0x123600a0 },
1401         { _MMIO(0x9888), 0x14552c00 },
1402         { _MMIO(0x9888), 0x16550005 },
1403         { _MMIO(0x9888), 0x125600a0 },
1404         { _MMIO(0x9888), 0x062f6000 },
1405         { _MMIO(0x9888), 0x022f2000 },
1406         { _MMIO(0x9888), 0x0c4c0050 },
1407         { _MMIO(0x9888), 0x0a4c0010 },
1408         { _MMIO(0x9888), 0x0c0d8000 },
1409         { _MMIO(0x9888), 0x0e0da000 },
1410         { _MMIO(0x9888), 0x000d8000 },
1411         { _MMIO(0x9888), 0x020da000 },
1412         { _MMIO(0x9888), 0x040da000 },
1413         { _MMIO(0x9888), 0x060d2000 },
1414         { _MMIO(0x9888), 0x100f0350 },
1415         { _MMIO(0x9888), 0x0c0fb000 },
1416         { _MMIO(0x9888), 0x0e0f00da },
1417         { _MMIO(0x9888), 0x182c0028 },
1418         { _MMIO(0x9888), 0x0a2c8000 },
1419         { _MMIO(0x9888), 0x022dc000 },
1420         { _MMIO(0x9888), 0x042d4000 },
1421         { _MMIO(0x9888), 0x0c138000 },
1422         { _MMIO(0x9888), 0x0e132000 },
1423         { _MMIO(0x9888), 0x0413c000 },
1424         { _MMIO(0x9888), 0x1c140018 },
1425         { _MMIO(0x9888), 0x0c157000 },
1426         { _MMIO(0x9888), 0x0e150078 },
1427         { _MMIO(0x9888), 0x10150000 },
1428         { _MMIO(0x9888), 0x04162180 },
1429         { _MMIO(0x9888), 0x02160000 },
1430         { _MMIO(0x9888), 0x04174000 },
1431         { _MMIO(0x9888), 0x0233a000 },
1432         { _MMIO(0x9888), 0x04333000 },
1433         { _MMIO(0x9888), 0x14348000 },
1434         { _MMIO(0x9888), 0x16348000 },
1435         { _MMIO(0x9888), 0x02357870 },
1436         { _MMIO(0x9888), 0x10350000 },
1437         { _MMIO(0x9888), 0x04360043 },
1438         { _MMIO(0x9888), 0x02360000 },
1439         { _MMIO(0x9888), 0x04371000 },
1440         { _MMIO(0x9888), 0x0e538000 },
1441         { _MMIO(0x9888), 0x00538000 },
1442         { _MMIO(0x9888), 0x06533000 },
1443         { _MMIO(0x9888), 0x1c540020 },
1444         { _MMIO(0x9888), 0x12548000 },
1445         { _MMIO(0x9888), 0x0e557000 },
1446         { _MMIO(0x9888), 0x00557800 },
1447         { _MMIO(0x9888), 0x10550000 },
1448         { _MMIO(0x9888), 0x06560043 },
1449         { _MMIO(0x9888), 0x02560000 },
1450         { _MMIO(0x9888), 0x06571000 },
1451         { _MMIO(0x9888), 0x1190ff80 },
1452         { _MMIO(0x9888), 0x57900000 },
1453         { _MMIO(0x9888), 0x49900000 },
1454         { _MMIO(0x9888), 0x37900000 },
1455         { _MMIO(0x9888), 0x33900000 },
1456         { _MMIO(0x9888), 0x4b900060 },
1457         { _MMIO(0x9888), 0x59900000 },
1458         { _MMIO(0x9888), 0x51900000 },
1459         { _MMIO(0x9888), 0x41900c00 },
1460         { _MMIO(0x9888), 0x43900842 },
1461         { _MMIO(0x9888), 0x53900000 },
1462         { _MMIO(0x9888), 0x45900060 },
1463 };
1464
1465 static int
1466 get_sampler_mux_config(struct drm_i915_private *dev_priv,
1467                        const struct i915_oa_reg **regs,
1468                        int *lens)
1469 {
1470         int n = 0;
1471
1472         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1473         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1474
1475         regs[n] = mux_config_sampler;
1476         lens[n] = ARRAY_SIZE(mux_config_sampler);
1477         n++;
1478
1479         return n;
1480 }
1481
1482 static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1483         { _MMIO(0x2740), 0x00000000 },
1484         { _MMIO(0x2744), 0x00800000 },
1485         { _MMIO(0x2710), 0x00000000 },
1486         { _MMIO(0x2714), 0xf0800000 },
1487         { _MMIO(0x2720), 0x00000000 },
1488         { _MMIO(0x2724), 0x30800000 },
1489         { _MMIO(0x2770), 0x00000002 },
1490         { _MMIO(0x2774), 0x00007fff },
1491         { _MMIO(0x2778), 0x00000000 },
1492         { _MMIO(0x277c), 0x00009fff },
1493         { _MMIO(0x2780), 0x00000002 },
1494         { _MMIO(0x2784), 0x0000efff },
1495         { _MMIO(0x2788), 0x00000000 },
1496         { _MMIO(0x278c), 0x0000f3ff },
1497         { _MMIO(0x2790), 0x00000002 },
1498         { _MMIO(0x2794), 0x0000fdff },
1499         { _MMIO(0x2798), 0x00000000 },
1500         { _MMIO(0x279c), 0x0000fe7f },
1501 };
1502
1503 static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1504         { _MMIO(0xe458), 0x00005004 },
1505         { _MMIO(0xe558), 0x00010003 },
1506         { _MMIO(0xe658), 0x00012011 },
1507         { _MMIO(0xe758), 0x00015014 },
1508         { _MMIO(0xe45c), 0x00051050 },
1509         { _MMIO(0xe55c), 0x00053052 },
1510         { _MMIO(0xe65c), 0x00055054 },
1511 };
1512
1513 static const struct i915_oa_reg mux_config_tdl_1[] = {
1514         { _MMIO(0x9888), 0x12120000 },
1515         { _MMIO(0x9888), 0x12320000 },
1516         { _MMIO(0x9888), 0x12520000 },
1517         { _MMIO(0x9888), 0x002f8000 },
1518         { _MMIO(0x9888), 0x022f3000 },
1519         { _MMIO(0x9888), 0x0a4c0015 },
1520         { _MMIO(0x9888), 0x0c0d8000 },
1521         { _MMIO(0x9888), 0x0e0da000 },
1522         { _MMIO(0x9888), 0x000d8000 },
1523         { _MMIO(0x9888), 0x020da000 },
1524         { _MMIO(0x9888), 0x040da000 },
1525         { _MMIO(0x9888), 0x060d2000 },
1526         { _MMIO(0x9888), 0x100f03a0 },
1527         { _MMIO(0x9888), 0x0c0ff000 },
1528         { _MMIO(0x9888), 0x0e0f0095 },
1529         { _MMIO(0x9888), 0x062c8000 },
1530         { _MMIO(0x9888), 0x082c8000 },
1531         { _MMIO(0x9888), 0x0a2c8000 },
1532         { _MMIO(0x9888), 0x0c2d8000 },
1533         { _MMIO(0x9888), 0x0e2d4000 },
1534         { _MMIO(0x9888), 0x062d4000 },
1535         { _MMIO(0x9888), 0x02108000 },
1536         { _MMIO(0x9888), 0x0410c000 },
1537         { _MMIO(0x9888), 0x02118000 },
1538         { _MMIO(0x9888), 0x0411c000 },
1539         { _MMIO(0x9888), 0x02121880 },
1540         { _MMIO(0x9888), 0x041219b5 },
1541         { _MMIO(0x9888), 0x00120000 },
1542         { _MMIO(0x9888), 0x02134000 },
1543         { _MMIO(0x9888), 0x04135000 },
1544         { _MMIO(0x9888), 0x0c308000 },
1545         { _MMIO(0x9888), 0x0e304000 },
1546         { _MMIO(0x9888), 0x06304000 },
1547         { _MMIO(0x9888), 0x0c318000 },
1548         { _MMIO(0x9888), 0x0e314000 },
1549         { _MMIO(0x9888), 0x06314000 },
1550         { _MMIO(0x9888), 0x0c321a80 },
1551         { _MMIO(0x9888), 0x0e320033 },
1552         { _MMIO(0x9888), 0x06320031 },
1553         { _MMIO(0x9888), 0x00320000 },
1554         { _MMIO(0x9888), 0x0c334000 },
1555         { _MMIO(0x9888), 0x0e331000 },
1556         { _MMIO(0x9888), 0x06331000 },
1557         { _MMIO(0x9888), 0x0e508000 },
1558         { _MMIO(0x9888), 0x00508000 },
1559         { _MMIO(0x9888), 0x02504000 },
1560         { _MMIO(0x9888), 0x0e518000 },
1561         { _MMIO(0x9888), 0x00518000 },
1562         { _MMIO(0x9888), 0x02514000 },
1563         { _MMIO(0x9888), 0x0e521880 },
1564         { _MMIO(0x9888), 0x00521a80 },
1565         { _MMIO(0x9888), 0x02520033 },
1566         { _MMIO(0x9888), 0x0e534000 },
1567         { _MMIO(0x9888), 0x00534000 },
1568         { _MMIO(0x9888), 0x02531000 },
1569         { _MMIO(0x9888), 0x1190ff80 },
1570         { _MMIO(0x9888), 0x57900000 },
1571         { _MMIO(0x9888), 0x49900800 },
1572         { _MMIO(0x9888), 0x37900000 },
1573         { _MMIO(0x9888), 0x33900000 },
1574         { _MMIO(0x9888), 0x4b900062 },
1575         { _MMIO(0x9888), 0x59900000 },
1576         { _MMIO(0x9888), 0x51900000 },
1577         { _MMIO(0x9888), 0x41900c00 },
1578         { _MMIO(0x9888), 0x43900003 },
1579         { _MMIO(0x9888), 0x53900000 },
1580         { _MMIO(0x9888), 0x45900040 },
1581 };
1582
1583 static int
1584 get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
1585                      const struct i915_oa_reg **regs,
1586                      int *lens)
1587 {
1588         int n = 0;
1589
1590         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1591         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1592
1593         regs[n] = mux_config_tdl_1;
1594         lens[n] = ARRAY_SIZE(mux_config_tdl_1);
1595         n++;
1596
1597         return n;
1598 }
1599
1600 static const struct i915_oa_reg b_counter_config_tdl_2[] = {
1601         { _MMIO(0x2740), 0x00000000 },
1602         { _MMIO(0x2744), 0x00800000 },
1603         { _MMIO(0x2710), 0x00000000 },
1604         { _MMIO(0x2714), 0x00800000 },
1605         { _MMIO(0x2720), 0x00000000 },
1606         { _MMIO(0x2724), 0x00800000 },
1607 };
1608
1609 static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
1610         { _MMIO(0xe458), 0x00005004 },
1611         { _MMIO(0xe558), 0x00010003 },
1612         { _MMIO(0xe658), 0x00012011 },
1613         { _MMIO(0xe758), 0x00015014 },
1614         { _MMIO(0xe45c), 0x00051050 },
1615         { _MMIO(0xe55c), 0x00053052 },
1616         { _MMIO(0xe65c), 0x00055054 },
1617 };
1618
1619 static const struct i915_oa_reg mux_config_tdl_2[] = {
1620         { _MMIO(0x9888), 0x12124d60 },
1621         { _MMIO(0x9888), 0x12322e60 },
1622         { _MMIO(0x9888), 0x12524d60 },
1623         { _MMIO(0x9888), 0x022f3000 },
1624         { _MMIO(0x9888), 0x0a4c0014 },
1625         { _MMIO(0x9888), 0x000d8000 },
1626         { _MMIO(0x9888), 0x020da000 },
1627         { _MMIO(0x9888), 0x040da000 },
1628         { _MMIO(0x9888), 0x060d2000 },
1629         { _MMIO(0x9888), 0x0c0fe000 },
1630         { _MMIO(0x9888), 0x0e0f0097 },
1631         { _MMIO(0x9888), 0x082c8000 },
1632         { _MMIO(0x9888), 0x0a2c8000 },
1633         { _MMIO(0x9888), 0x002d8000 },
1634         { _MMIO(0x9888), 0x062d4000 },
1635         { _MMIO(0x9888), 0x0410c000 },
1636         { _MMIO(0x9888), 0x0411c000 },
1637         { _MMIO(0x9888), 0x04121fb7 },
1638         { _MMIO(0x9888), 0x00120000 },
1639         { _MMIO(0x9888), 0x04135000 },
1640         { _MMIO(0x9888), 0x00308000 },
1641         { _MMIO(0x9888), 0x06304000 },
1642         { _MMIO(0x9888), 0x00318000 },
1643         { _MMIO(0x9888), 0x06314000 },
1644         { _MMIO(0x9888), 0x00321b80 },
1645         { _MMIO(0x9888), 0x0632003f },
1646         { _MMIO(0x9888), 0x00334000 },
1647         { _MMIO(0x9888), 0x06331000 },
1648         { _MMIO(0x9888), 0x0250c000 },
1649         { _MMIO(0x9888), 0x0251c000 },
1650         { _MMIO(0x9888), 0x02521fb7 },
1651         { _MMIO(0x9888), 0x00520000 },
1652         { _MMIO(0x9888), 0x02535000 },
1653         { _MMIO(0x9888), 0x1190fc00 },
1654         { _MMIO(0x9888), 0x37900000 },
1655         { _MMIO(0x9888), 0x51900000 },
1656         { _MMIO(0x9888), 0x41900800 },
1657         { _MMIO(0x9888), 0x43900063 },
1658         { _MMIO(0x9888), 0x53900000 },
1659         { _MMIO(0x9888), 0x45900040 },
1660         { _MMIO(0x9888), 0x33900000 },
1661 };
1662
1663 static int
1664 get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
1665                      const struct i915_oa_reg **regs,
1666                      int *lens)
1667 {
1668         int n = 0;
1669
1670         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1671         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1672
1673         regs[n] = mux_config_tdl_2;
1674         lens[n] = ARRAY_SIZE(mux_config_tdl_2);
1675         n++;
1676
1677         return n;
1678 }
1679
1680 static const struct i915_oa_reg b_counter_config_compute_extra[] = {
1681         { _MMIO(0x2740), 0x00000000 },
1682         { _MMIO(0x2744), 0x00800000 },
1683         { _MMIO(0x2710), 0x00000000 },
1684         { _MMIO(0x2714), 0x00800000 },
1685         { _MMIO(0x2720), 0x00000000 },
1686         { _MMIO(0x2724), 0x00800000 },
1687 };
1688
1689 static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
1690         { _MMIO(0xe458), 0x00001000 },
1691         { _MMIO(0xe558), 0x00003002 },
1692         { _MMIO(0xe658), 0x00005004 },
1693         { _MMIO(0xe758), 0x00011010 },
1694         { _MMIO(0xe45c), 0x00050012 },
1695         { _MMIO(0xe55c), 0x00052051 },
1696         { _MMIO(0xe65c), 0x00000008 },
1697 };
1698
1699 static const struct i915_oa_reg mux_config_compute_extra[] = {
1700         { _MMIO(0x9888), 0x121203e0 },
1701         { _MMIO(0x9888), 0x123203e0 },
1702         { _MMIO(0x9888), 0x125203e0 },
1703         { _MMIO(0x9888), 0x022f4000 },
1704         { _MMIO(0x9888), 0x0a4c0040 },
1705         { _MMIO(0x9888), 0x040da000 },
1706         { _MMIO(0x9888), 0x060d2000 },
1707         { _MMIO(0x9888), 0x0e0f006c },
1708         { _MMIO(0x9888), 0x0c2c8000 },
1709         { _MMIO(0x9888), 0x042d8000 },
1710         { _MMIO(0x9888), 0x06104000 },
1711         { _MMIO(0x9888), 0x06114000 },
1712         { _MMIO(0x9888), 0x06120033 },
1713         { _MMIO(0x9888), 0x00120000 },
1714         { _MMIO(0x9888), 0x06131000 },
1715         { _MMIO(0x9888), 0x04308000 },
1716         { _MMIO(0x9888), 0x04318000 },
1717         { _MMIO(0x9888), 0x04321980 },
1718         { _MMIO(0x9888), 0x00320000 },
1719         { _MMIO(0x9888), 0x04334000 },
1720         { _MMIO(0x9888), 0x04504000 },
1721         { _MMIO(0x9888), 0x04514000 },
1722         { _MMIO(0x9888), 0x04520033 },
1723         { _MMIO(0x9888), 0x00520000 },
1724         { _MMIO(0x9888), 0x04531000 },
1725         { _MMIO(0x9888), 0x1190e000 },
1726         { _MMIO(0x9888), 0x37900000 },
1727         { _MMIO(0x9888), 0x53900000 },
1728         { _MMIO(0x9888), 0x43900c00 },
1729         { _MMIO(0x9888), 0x45900002 },
1730         { _MMIO(0x9888), 0x33900000 },
1731 };
1732
1733 static int
1734 get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
1735                              const struct i915_oa_reg **regs,
1736                              int *lens)
1737 {
1738         int n = 0;
1739
1740         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1741         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1742
1743         regs[n] = mux_config_compute_extra;
1744         lens[n] = ARRAY_SIZE(mux_config_compute_extra);
1745         n++;
1746
1747         return n;
1748 }
1749
1750 static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
1751         { _MMIO(0x2740), 0x00000000 },
1752         { _MMIO(0x2710), 0x00000000 },
1753         { _MMIO(0x2714), 0xf0800000 },
1754         { _MMIO(0x2720), 0x00000000 },
1755         { _MMIO(0x2724), 0x30800000 },
1756         { _MMIO(0x2770), 0x00100030 },
1757         { _MMIO(0x2774), 0x0000fff9 },
1758         { _MMIO(0x2778), 0x00000002 },
1759         { _MMIO(0x277c), 0x0000fffc },
1760         { _MMIO(0x2780), 0x00000002 },
1761         { _MMIO(0x2784), 0x0000fff3 },
1762         { _MMIO(0x2788), 0x00100180 },
1763         { _MMIO(0x278c), 0x0000ffcf },
1764         { _MMIO(0x2790), 0x00000002 },
1765         { _MMIO(0x2794), 0x0000ffcf },
1766         { _MMIO(0x2798), 0x00000002 },
1767         { _MMIO(0x279c), 0x0000ff3f },
1768 };
1769
1770 static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
1771         { _MMIO(0xe458), 0x00005004 },
1772         { _MMIO(0xe558), 0x00008003 },
1773 };
1774
1775 static const struct i915_oa_reg mux_config_vme_pipe[] = {
1776         { _MMIO(0x9888), 0x141a5800 },
1777         { _MMIO(0x9888), 0x161a00c0 },
1778         { _MMIO(0x9888), 0x12180240 },
1779         { _MMIO(0x9888), 0x14180002 },
1780         { _MMIO(0x9888), 0x143a5800 },
1781         { _MMIO(0x9888), 0x163a00c0 },
1782         { _MMIO(0x9888), 0x12380240 },
1783         { _MMIO(0x9888), 0x14380002 },
1784         { _MMIO(0x9888), 0x002f1000 },
1785         { _MMIO(0x9888), 0x022f8000 },
1786         { _MMIO(0x9888), 0x042f3000 },
1787         { _MMIO(0x9888), 0x004c4000 },
1788         { _MMIO(0x9888), 0x0a4c1500 },
1789         { _MMIO(0x9888), 0x000d2000 },
1790         { _MMIO(0x9888), 0x060d8000 },
1791         { _MMIO(0x9888), 0x080da000 },
1792         { _MMIO(0x9888), 0x0a0da000 },
1793         { _MMIO(0x9888), 0x0c0da000 },
1794         { _MMIO(0x9888), 0x0c0f0400 },
1795         { _MMIO(0x9888), 0x0e0f9500 },
1796         { _MMIO(0x9888), 0x100f002a },
1797         { _MMIO(0x9888), 0x002c8000 },
1798         { _MMIO(0x9888), 0x0e2c8000 },
1799         { _MMIO(0x9888), 0x162c0a00 },
1800         { _MMIO(0x9888), 0x0a2dc000 },
1801         { _MMIO(0x9888), 0x0c2dc000 },
1802         { _MMIO(0x9888), 0x04193000 },
1803         { _MMIO(0x9888), 0x081a28c1 },
1804         { _MMIO(0x9888), 0x001a0000 },
1805         { _MMIO(0x9888), 0x00133000 },
1806         { _MMIO(0x9888), 0x0613c000 },
1807         { _MMIO(0x9888), 0x0813f000 },
1808         { _MMIO(0x9888), 0x00172000 },
1809         { _MMIO(0x9888), 0x06178000 },
1810         { _MMIO(0x9888), 0x0817a000 },
1811         { _MMIO(0x9888), 0x00180037 },
1812         { _MMIO(0x9888), 0x06180940 },
1813         { _MMIO(0x9888), 0x08180000 },
1814         { _MMIO(0x9888), 0x02180000 },
1815         { _MMIO(0x9888), 0x04183000 },
1816         { _MMIO(0x9888), 0x06393000 },
1817         { _MMIO(0x9888), 0x0c3a28c1 },
1818         { _MMIO(0x9888), 0x003a0000 },
1819         { _MMIO(0x9888), 0x0a33f000 },
1820         { _MMIO(0x9888), 0x0c33f000 },
1821         { _MMIO(0x9888), 0x0a37a000 },
1822         { _MMIO(0x9888), 0x0c37a000 },
1823         { _MMIO(0x9888), 0x0a380977 },
1824         { _MMIO(0x9888), 0x08380000 },
1825         { _MMIO(0x9888), 0x04380000 },
1826         { _MMIO(0x9888), 0x06383000 },
1827         { _MMIO(0x9888), 0x119000ff },
1828         { _MMIO(0x9888), 0x51900000 },
1829         { _MMIO(0x9888), 0x41900040 },
1830         { _MMIO(0x9888), 0x55900000 },
1831         { _MMIO(0x9888), 0x45900800 },
1832         { _MMIO(0x9888), 0x47901000 },
1833         { _MMIO(0x9888), 0x57900000 },
1834         { _MMIO(0x9888), 0x49900844 },
1835         { _MMIO(0x9888), 0x37900000 },
1836         { _MMIO(0x9888), 0x33900000 },
1837 };
1838
1839 static int
1840 get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
1841                         const struct i915_oa_reg **regs,
1842                         int *lens)
1843 {
1844         int n = 0;
1845
1846         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1847         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1848
1849         regs[n] = mux_config_vme_pipe;
1850         lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
1851         n++;
1852
1853         return n;
1854 }
1855
1856 static const struct i915_oa_reg b_counter_config_test_oa[] = {
1857         { _MMIO(0x2740), 0x00000000 },
1858         { _MMIO(0x2744), 0x00800000 },
1859         { _MMIO(0x2714), 0xf0800000 },
1860         { _MMIO(0x2710), 0x00000000 },
1861         { _MMIO(0x2724), 0xf0800000 },
1862         { _MMIO(0x2720), 0x00000000 },
1863         { _MMIO(0x2770), 0x00000004 },
1864         { _MMIO(0x2774), 0x00000000 },
1865         { _MMIO(0x2778), 0x00000003 },
1866         { _MMIO(0x277c), 0x00000000 },
1867         { _MMIO(0x2780), 0x00000007 },
1868         { _MMIO(0x2784), 0x00000000 },
1869         { _MMIO(0x2788), 0x00100002 },
1870         { _MMIO(0x278c), 0x0000fff7 },
1871         { _MMIO(0x2790), 0x00100002 },
1872         { _MMIO(0x2794), 0x0000ffcf },
1873         { _MMIO(0x2798), 0x00100082 },
1874         { _MMIO(0x279c), 0x0000ffef },
1875         { _MMIO(0x27a0), 0x001000c2 },
1876         { _MMIO(0x27a4), 0x0000ffe7 },
1877         { _MMIO(0x27a8), 0x00100001 },
1878         { _MMIO(0x27ac), 0x0000ffe7 },
1879 };
1880
1881 static const struct i915_oa_reg flex_eu_config_test_oa[] = {
1882 };
1883
1884 static const struct i915_oa_reg mux_config_test_oa[] = {
1885         { _MMIO(0x9888), 0x11810000 },
1886         { _MMIO(0x9888), 0x07810013 },
1887         { _MMIO(0x9888), 0x1f810000 },
1888         { _MMIO(0x9888), 0x1d810000 },
1889         { _MMIO(0x9888), 0x1b930040 },
1890         { _MMIO(0x9888), 0x07e54000 },
1891         { _MMIO(0x9888), 0x1f908000 },
1892         { _MMIO(0x9888), 0x11900000 },
1893         { _MMIO(0x9888), 0x37900000 },
1894         { _MMIO(0x9888), 0x53900000 },
1895         { _MMIO(0x9888), 0x45900000 },
1896         { _MMIO(0x9888), 0x33900000 },
1897 };
1898
1899 static int
1900 get_test_oa_mux_config(struct drm_i915_private *dev_priv,
1901                        const struct i915_oa_reg **regs,
1902                        int *lens)
1903 {
1904         int n = 0;
1905
1906         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1907         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1908
1909         regs[n] = mux_config_test_oa;
1910         lens[n] = ARRAY_SIZE(mux_config_test_oa);
1911         n++;
1912
1913         return n;
1914 }
1915
1916 int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv)
1917 {
1918         dev_priv->perf.oa.n_mux_configs = 0;
1919         dev_priv->perf.oa.b_counter_regs = NULL;
1920         dev_priv->perf.oa.b_counter_regs_len = 0;
1921         dev_priv->perf.oa.flex_regs = NULL;
1922         dev_priv->perf.oa.flex_regs_len = 0;
1923
1924         switch (dev_priv->perf.oa.metrics_set) {
1925         case METRIC_SET_ID_RENDER_BASIC:
1926                 dev_priv->perf.oa.n_mux_configs =
1927                         get_render_basic_mux_config(dev_priv,
1928                                                     dev_priv->perf.oa.mux_regs,
1929                                                     dev_priv->perf.oa.mux_regs_lens);
1930                 if (dev_priv->perf.oa.n_mux_configs == 0) {
1931                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
1932
1933                         /* EINVAL because *_register_sysfs already checked this
1934                          * and so it wouldn't have been advertised to userspace and
1935                          * so shouldn't have been requested
1936                          */
1937                         return -EINVAL;
1938                 }
1939
1940                 dev_priv->perf.oa.b_counter_regs =
1941                         b_counter_config_render_basic;
1942                 dev_priv->perf.oa.b_counter_regs_len =
1943                         ARRAY_SIZE(b_counter_config_render_basic);
1944
1945                 dev_priv->perf.oa.flex_regs =
1946                         flex_eu_config_render_basic;
1947                 dev_priv->perf.oa.flex_regs_len =
1948                         ARRAY_SIZE(flex_eu_config_render_basic);
1949
1950                 return 0;
1951         case METRIC_SET_ID_COMPUTE_BASIC:
1952                 dev_priv->perf.oa.n_mux_configs =
1953                         get_compute_basic_mux_config(dev_priv,
1954                                                      dev_priv->perf.oa.mux_regs,
1955                                                      dev_priv->perf.oa.mux_regs_lens);
1956                 if (dev_priv->perf.oa.n_mux_configs == 0) {
1957                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
1958
1959                         /* EINVAL because *_register_sysfs already checked this
1960                          * and so it wouldn't have been advertised to userspace and
1961                          * so shouldn't have been requested
1962                          */
1963                         return -EINVAL;
1964                 }
1965
1966                 dev_priv->perf.oa.b_counter_regs =
1967                         b_counter_config_compute_basic;
1968                 dev_priv->perf.oa.b_counter_regs_len =
1969                         ARRAY_SIZE(b_counter_config_compute_basic);
1970
1971                 dev_priv->perf.oa.flex_regs =
1972                         flex_eu_config_compute_basic;
1973                 dev_priv->perf.oa.flex_regs_len =
1974                         ARRAY_SIZE(flex_eu_config_compute_basic);
1975
1976                 return 0;
1977         case METRIC_SET_ID_RENDER_PIPE_PROFILE:
1978                 dev_priv->perf.oa.n_mux_configs =
1979                         get_render_pipe_profile_mux_config(dev_priv,
1980                                                            dev_priv->perf.oa.mux_regs,
1981                                                            dev_priv->perf.oa.mux_regs_lens);
1982                 if (dev_priv->perf.oa.n_mux_configs == 0) {
1983                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
1984
1985                         /* EINVAL because *_register_sysfs already checked this
1986                          * and so it wouldn't have been advertised to userspace and
1987                          * so shouldn't have been requested
1988                          */
1989                         return -EINVAL;
1990                 }
1991
1992                 dev_priv->perf.oa.b_counter_regs =
1993                         b_counter_config_render_pipe_profile;
1994                 dev_priv->perf.oa.b_counter_regs_len =
1995                         ARRAY_SIZE(b_counter_config_render_pipe_profile);
1996
1997                 dev_priv->perf.oa.flex_regs =
1998                         flex_eu_config_render_pipe_profile;
1999                 dev_priv->perf.oa.flex_regs_len =
2000                         ARRAY_SIZE(flex_eu_config_render_pipe_profile);
2001
2002                 return 0;
2003         case METRIC_SET_ID_MEMORY_READS:
2004                 dev_priv->perf.oa.n_mux_configs =
2005                         get_memory_reads_mux_config(dev_priv,
2006                                                     dev_priv->perf.oa.mux_regs,
2007                                                     dev_priv->perf.oa.mux_regs_lens);
2008                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2009                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
2010
2011                         /* EINVAL because *_register_sysfs already checked this
2012                          * and so it wouldn't have been advertised to userspace and
2013                          * so shouldn't have been requested
2014                          */
2015                         return -EINVAL;
2016                 }
2017
2018                 dev_priv->perf.oa.b_counter_regs =
2019                         b_counter_config_memory_reads;
2020                 dev_priv->perf.oa.b_counter_regs_len =
2021                         ARRAY_SIZE(b_counter_config_memory_reads);
2022
2023                 dev_priv->perf.oa.flex_regs =
2024                         flex_eu_config_memory_reads;
2025                 dev_priv->perf.oa.flex_regs_len =
2026                         ARRAY_SIZE(flex_eu_config_memory_reads);
2027
2028                 return 0;
2029         case METRIC_SET_ID_MEMORY_WRITES:
2030                 dev_priv->perf.oa.n_mux_configs =
2031                         get_memory_writes_mux_config(dev_priv,
2032                                                      dev_priv->perf.oa.mux_regs,
2033                                                      dev_priv->perf.oa.mux_regs_lens);
2034                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2035                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
2036
2037                         /* EINVAL because *_register_sysfs already checked this
2038                          * and so it wouldn't have been advertised to userspace and
2039                          * so shouldn't have been requested
2040                          */
2041                         return -EINVAL;
2042                 }
2043
2044                 dev_priv->perf.oa.b_counter_regs =
2045                         b_counter_config_memory_writes;
2046                 dev_priv->perf.oa.b_counter_regs_len =
2047                         ARRAY_SIZE(b_counter_config_memory_writes);
2048
2049                 dev_priv->perf.oa.flex_regs =
2050                         flex_eu_config_memory_writes;
2051                 dev_priv->perf.oa.flex_regs_len =
2052                         ARRAY_SIZE(flex_eu_config_memory_writes);
2053
2054                 return 0;
2055         case METRIC_SET_ID_COMPUTE_EXTENDED:
2056                 dev_priv->perf.oa.n_mux_configs =
2057                         get_compute_extended_mux_config(dev_priv,
2058                                                         dev_priv->perf.oa.mux_regs,
2059                                                         dev_priv->perf.oa.mux_regs_lens);
2060                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2061                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
2062
2063                         /* EINVAL because *_register_sysfs already checked this
2064                          * and so it wouldn't have been advertised to userspace and
2065                          * so shouldn't have been requested
2066                          */
2067                         return -EINVAL;
2068                 }
2069
2070                 dev_priv->perf.oa.b_counter_regs =
2071                         b_counter_config_compute_extended;
2072                 dev_priv->perf.oa.b_counter_regs_len =
2073                         ARRAY_SIZE(b_counter_config_compute_extended);
2074
2075                 dev_priv->perf.oa.flex_regs =
2076                         flex_eu_config_compute_extended;
2077                 dev_priv->perf.oa.flex_regs_len =
2078                         ARRAY_SIZE(flex_eu_config_compute_extended);
2079
2080                 return 0;
2081         case METRIC_SET_ID_COMPUTE_L3_CACHE:
2082                 dev_priv->perf.oa.n_mux_configs =
2083                         get_compute_l3_cache_mux_config(dev_priv,
2084                                                         dev_priv->perf.oa.mux_regs,
2085                                                         dev_priv->perf.oa.mux_regs_lens);
2086                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2087                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
2088
2089                         /* EINVAL because *_register_sysfs already checked this
2090                          * and so it wouldn't have been advertised to userspace and
2091                          * so shouldn't have been requested
2092                          */
2093                         return -EINVAL;
2094                 }
2095
2096                 dev_priv->perf.oa.b_counter_regs =
2097                         b_counter_config_compute_l3_cache;
2098                 dev_priv->perf.oa.b_counter_regs_len =
2099                         ARRAY_SIZE(b_counter_config_compute_l3_cache);
2100
2101                 dev_priv->perf.oa.flex_regs =
2102                         flex_eu_config_compute_l3_cache;
2103                 dev_priv->perf.oa.flex_regs_len =
2104                         ARRAY_SIZE(flex_eu_config_compute_l3_cache);
2105
2106                 return 0;
2107         case METRIC_SET_ID_HDC_AND_SF:
2108                 dev_priv->perf.oa.n_mux_configs =
2109                         get_hdc_and_sf_mux_config(dev_priv,
2110                                                   dev_priv->perf.oa.mux_regs,
2111                                                   dev_priv->perf.oa.mux_regs_lens);
2112                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2113                         DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
2114
2115                         /* EINVAL because *_register_sysfs already checked this
2116                          * and so it wouldn't have been advertised to userspace and
2117                          * so shouldn't have been requested
2118                          */
2119                         return -EINVAL;
2120                 }
2121
2122                 dev_priv->perf.oa.b_counter_regs =
2123                         b_counter_config_hdc_and_sf;
2124                 dev_priv->perf.oa.b_counter_regs_len =
2125                         ARRAY_SIZE(b_counter_config_hdc_and_sf);
2126
2127                 dev_priv->perf.oa.flex_regs =
2128                         flex_eu_config_hdc_and_sf;
2129                 dev_priv->perf.oa.flex_regs_len =
2130                         ARRAY_SIZE(flex_eu_config_hdc_and_sf);
2131
2132                 return 0;
2133         case METRIC_SET_ID_L3_1:
2134                 dev_priv->perf.oa.n_mux_configs =
2135                         get_l3_1_mux_config(dev_priv,
2136                                             dev_priv->perf.oa.mux_regs,
2137                                             dev_priv->perf.oa.mux_regs_lens);
2138                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2139                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
2140
2141                         /* EINVAL because *_register_sysfs already checked this
2142                          * and so it wouldn't have been advertised to userspace and
2143                          * so shouldn't have been requested
2144                          */
2145                         return -EINVAL;
2146                 }
2147
2148                 dev_priv->perf.oa.b_counter_regs =
2149                         b_counter_config_l3_1;
2150                 dev_priv->perf.oa.b_counter_regs_len =
2151                         ARRAY_SIZE(b_counter_config_l3_1);
2152
2153                 dev_priv->perf.oa.flex_regs =
2154                         flex_eu_config_l3_1;
2155                 dev_priv->perf.oa.flex_regs_len =
2156                         ARRAY_SIZE(flex_eu_config_l3_1);
2157
2158                 return 0;
2159         case METRIC_SET_ID_L3_2:
2160                 dev_priv->perf.oa.n_mux_configs =
2161                         get_l3_2_mux_config(dev_priv,
2162                                             dev_priv->perf.oa.mux_regs,
2163                                             dev_priv->perf.oa.mux_regs_lens);
2164                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2165                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
2166
2167                         /* EINVAL because *_register_sysfs already checked this
2168                          * and so it wouldn't have been advertised to userspace and
2169                          * so shouldn't have been requested
2170                          */
2171                         return -EINVAL;
2172                 }
2173
2174                 dev_priv->perf.oa.b_counter_regs =
2175                         b_counter_config_l3_2;
2176                 dev_priv->perf.oa.b_counter_regs_len =
2177                         ARRAY_SIZE(b_counter_config_l3_2);
2178
2179                 dev_priv->perf.oa.flex_regs =
2180                         flex_eu_config_l3_2;
2181                 dev_priv->perf.oa.flex_regs_len =
2182                         ARRAY_SIZE(flex_eu_config_l3_2);
2183
2184                 return 0;
2185         case METRIC_SET_ID_L3_3:
2186                 dev_priv->perf.oa.n_mux_configs =
2187                         get_l3_3_mux_config(dev_priv,
2188                                             dev_priv->perf.oa.mux_regs,
2189                                             dev_priv->perf.oa.mux_regs_lens);
2190                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2191                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
2192
2193                         /* EINVAL because *_register_sysfs already checked this
2194                          * and so it wouldn't have been advertised to userspace and
2195                          * so shouldn't have been requested
2196                          */
2197                         return -EINVAL;
2198                 }
2199
2200                 dev_priv->perf.oa.b_counter_regs =
2201                         b_counter_config_l3_3;
2202                 dev_priv->perf.oa.b_counter_regs_len =
2203                         ARRAY_SIZE(b_counter_config_l3_3);
2204
2205                 dev_priv->perf.oa.flex_regs =
2206                         flex_eu_config_l3_3;
2207                 dev_priv->perf.oa.flex_regs_len =
2208                         ARRAY_SIZE(flex_eu_config_l3_3);
2209
2210                 return 0;
2211         case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
2212                 dev_priv->perf.oa.n_mux_configs =
2213                         get_rasterizer_and_pixel_backend_mux_config(dev_priv,
2214                                                                     dev_priv->perf.oa.mux_regs,
2215                                                                     dev_priv->perf.oa.mux_regs_lens);
2216                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2217                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
2218
2219                         /* EINVAL because *_register_sysfs already checked this
2220                          * and so it wouldn't have been advertised to userspace and
2221                          * so shouldn't have been requested
2222                          */
2223                         return -EINVAL;
2224                 }
2225
2226                 dev_priv->perf.oa.b_counter_regs =
2227                         b_counter_config_rasterizer_and_pixel_backend;
2228                 dev_priv->perf.oa.b_counter_regs_len =
2229                         ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
2230
2231                 dev_priv->perf.oa.flex_regs =
2232                         flex_eu_config_rasterizer_and_pixel_backend;
2233                 dev_priv->perf.oa.flex_regs_len =
2234                         ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
2235
2236                 return 0;
2237         case METRIC_SET_ID_SAMPLER:
2238                 dev_priv->perf.oa.n_mux_configs =
2239                         get_sampler_mux_config(dev_priv,
2240                                                dev_priv->perf.oa.mux_regs,
2241                                                dev_priv->perf.oa.mux_regs_lens);
2242                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2243                         DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
2244
2245                         /* EINVAL because *_register_sysfs already checked this
2246                          * and so it wouldn't have been advertised to userspace and
2247                          * so shouldn't have been requested
2248                          */
2249                         return -EINVAL;
2250                 }
2251
2252                 dev_priv->perf.oa.b_counter_regs =
2253                         b_counter_config_sampler;
2254                 dev_priv->perf.oa.b_counter_regs_len =
2255                         ARRAY_SIZE(b_counter_config_sampler);
2256
2257                 dev_priv->perf.oa.flex_regs =
2258                         flex_eu_config_sampler;
2259                 dev_priv->perf.oa.flex_regs_len =
2260                         ARRAY_SIZE(flex_eu_config_sampler);
2261
2262                 return 0;
2263         case METRIC_SET_ID_TDL_1:
2264                 dev_priv->perf.oa.n_mux_configs =
2265                         get_tdl_1_mux_config(dev_priv,
2266                                              dev_priv->perf.oa.mux_regs,
2267                                              dev_priv->perf.oa.mux_regs_lens);
2268                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2269                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2270
2271                         /* EINVAL because *_register_sysfs already checked this
2272                          * and so it wouldn't have been advertised to userspace and
2273                          * so shouldn't have been requested
2274                          */
2275                         return -EINVAL;
2276                 }
2277
2278                 dev_priv->perf.oa.b_counter_regs =
2279                         b_counter_config_tdl_1;
2280                 dev_priv->perf.oa.b_counter_regs_len =
2281                         ARRAY_SIZE(b_counter_config_tdl_1);
2282
2283                 dev_priv->perf.oa.flex_regs =
2284                         flex_eu_config_tdl_1;
2285                 dev_priv->perf.oa.flex_regs_len =
2286                         ARRAY_SIZE(flex_eu_config_tdl_1);
2287
2288                 return 0;
2289         case METRIC_SET_ID_TDL_2:
2290                 dev_priv->perf.oa.n_mux_configs =
2291                         get_tdl_2_mux_config(dev_priv,
2292                                              dev_priv->perf.oa.mux_regs,
2293                                              dev_priv->perf.oa.mux_regs_lens);
2294                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2295                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2296
2297                         /* EINVAL because *_register_sysfs already checked this
2298                          * and so it wouldn't have been advertised to userspace and
2299                          * so shouldn't have been requested
2300                          */
2301                         return -EINVAL;
2302                 }
2303
2304                 dev_priv->perf.oa.b_counter_regs =
2305                         b_counter_config_tdl_2;
2306                 dev_priv->perf.oa.b_counter_regs_len =
2307                         ARRAY_SIZE(b_counter_config_tdl_2);
2308
2309                 dev_priv->perf.oa.flex_regs =
2310                         flex_eu_config_tdl_2;
2311                 dev_priv->perf.oa.flex_regs_len =
2312                         ARRAY_SIZE(flex_eu_config_tdl_2);
2313
2314                 return 0;
2315         case METRIC_SET_ID_COMPUTE_EXTRA:
2316                 dev_priv->perf.oa.n_mux_configs =
2317                         get_compute_extra_mux_config(dev_priv,
2318                                                      dev_priv->perf.oa.mux_regs,
2319                                                      dev_priv->perf.oa.mux_regs_lens);
2320                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2321                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
2322
2323                         /* EINVAL because *_register_sysfs already checked this
2324                          * and so it wouldn't have been advertised to userspace and
2325                          * so shouldn't have been requested
2326                          */
2327                         return -EINVAL;
2328                 }
2329
2330                 dev_priv->perf.oa.b_counter_regs =
2331                         b_counter_config_compute_extra;
2332                 dev_priv->perf.oa.b_counter_regs_len =
2333                         ARRAY_SIZE(b_counter_config_compute_extra);
2334
2335                 dev_priv->perf.oa.flex_regs =
2336                         flex_eu_config_compute_extra;
2337                 dev_priv->perf.oa.flex_regs_len =
2338                         ARRAY_SIZE(flex_eu_config_compute_extra);
2339
2340                 return 0;
2341         case METRIC_SET_ID_VME_PIPE:
2342                 dev_priv->perf.oa.n_mux_configs =
2343                         get_vme_pipe_mux_config(dev_priv,
2344                                                 dev_priv->perf.oa.mux_regs,
2345                                                 dev_priv->perf.oa.mux_regs_lens);
2346                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2347                         DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
2348
2349                         /* EINVAL because *_register_sysfs already checked this
2350                          * and so it wouldn't have been advertised to userspace and
2351                          * so shouldn't have been requested
2352                          */
2353                         return -EINVAL;
2354                 }
2355
2356                 dev_priv->perf.oa.b_counter_regs =
2357                         b_counter_config_vme_pipe;
2358                 dev_priv->perf.oa.b_counter_regs_len =
2359                         ARRAY_SIZE(b_counter_config_vme_pipe);
2360
2361                 dev_priv->perf.oa.flex_regs =
2362                         flex_eu_config_vme_pipe;
2363                 dev_priv->perf.oa.flex_regs_len =
2364                         ARRAY_SIZE(flex_eu_config_vme_pipe);
2365
2366                 return 0;
2367         case METRIC_SET_ID_TEST_OA:
2368                 dev_priv->perf.oa.n_mux_configs =
2369                         get_test_oa_mux_config(dev_priv,
2370                                                dev_priv->perf.oa.mux_regs,
2371                                                dev_priv->perf.oa.mux_regs_lens);
2372                 if (dev_priv->perf.oa.n_mux_configs == 0) {
2373                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2374
2375                         /* EINVAL because *_register_sysfs already checked this
2376                          * and so it wouldn't have been advertised to userspace and
2377                          * so shouldn't have been requested
2378                          */
2379                         return -EINVAL;
2380                 }
2381
2382                 dev_priv->perf.oa.b_counter_regs =
2383                         b_counter_config_test_oa;
2384                 dev_priv->perf.oa.b_counter_regs_len =
2385                         ARRAY_SIZE(b_counter_config_test_oa);
2386
2387                 dev_priv->perf.oa.flex_regs =
2388                         flex_eu_config_test_oa;
2389                 dev_priv->perf.oa.flex_regs_len =
2390                         ARRAY_SIZE(flex_eu_config_test_oa);
2391
2392                 return 0;
2393         default:
2394                 return -ENODEV;
2395         }
2396 }
2397
2398 static ssize_t
2399 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2400 {
2401         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2402 }
2403
2404 static struct device_attribute dev_attr_render_basic_id = {
2405         .attr = { .name = "id", .mode = 0444 },
2406         .show = show_render_basic_id,
2407         .store = NULL,
2408 };
2409
2410 static struct attribute *attrs_render_basic[] = {
2411         &dev_attr_render_basic_id.attr,
2412         NULL,
2413 };
2414
2415 static struct attribute_group group_render_basic = {
2416         .name = "f8d677e9-ff6f-4df1-9310-0334c6efacce",
2417         .attrs =  attrs_render_basic,
2418 };
2419
2420 static ssize_t
2421 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2422 {
2423         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2424 }
2425
2426 static struct device_attribute dev_attr_compute_basic_id = {
2427         .attr = { .name = "id", .mode = 0444 },
2428         .show = show_compute_basic_id,
2429         .store = NULL,
2430 };
2431
2432 static struct attribute *attrs_compute_basic[] = {
2433         &dev_attr_compute_basic_id.attr,
2434         NULL,
2435 };
2436
2437 static struct attribute_group group_compute_basic = {
2438         .name = "e17fc42a-e614-41b6-90c4-1074841a6c77",
2439         .attrs =  attrs_compute_basic,
2440 };
2441
2442 static ssize_t
2443 show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2444 {
2445         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2446 }
2447
2448 static struct device_attribute dev_attr_render_pipe_profile_id = {
2449         .attr = { .name = "id", .mode = 0444 },
2450         .show = show_render_pipe_profile_id,
2451         .store = NULL,
2452 };
2453
2454 static struct attribute *attrs_render_pipe_profile[] = {
2455         &dev_attr_render_pipe_profile_id.attr,
2456         NULL,
2457 };
2458
2459 static struct attribute_group group_render_pipe_profile = {
2460         .name = "d7a17a3a-ca71-40d2-a919-ace80d50633f",
2461         .attrs =  attrs_render_pipe_profile,
2462 };
2463
2464 static ssize_t
2465 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
2466 {
2467         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
2468 }
2469
2470 static struct device_attribute dev_attr_memory_reads_id = {
2471         .attr = { .name = "id", .mode = 0444 },
2472         .show = show_memory_reads_id,
2473         .store = NULL,
2474 };
2475
2476 static struct attribute *attrs_memory_reads[] = {
2477         &dev_attr_memory_reads_id.attr,
2478         NULL,
2479 };
2480
2481 static struct attribute_group group_memory_reads = {
2482         .name = "57b59202-172b-477a-87de-33f85572c589",
2483         .attrs =  attrs_memory_reads,
2484 };
2485
2486 static ssize_t
2487 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
2488 {
2489         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
2490 }
2491
2492 static struct device_attribute dev_attr_memory_writes_id = {
2493         .attr = { .name = "id", .mode = 0444 },
2494         .show = show_memory_writes_id,
2495         .store = NULL,
2496 };
2497
2498 static struct attribute *attrs_memory_writes[] = {
2499         &dev_attr_memory_writes_id.attr,
2500         NULL,
2501 };
2502
2503 static struct attribute_group group_memory_writes = {
2504         .name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0",
2505         .attrs =  attrs_memory_writes,
2506 };
2507
2508 static ssize_t
2509 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
2510 {
2511         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
2512 }
2513
2514 static struct device_attribute dev_attr_compute_extended_id = {
2515         .attr = { .name = "id", .mode = 0444 },
2516         .show = show_compute_extended_id,
2517         .store = NULL,
2518 };
2519
2520 static struct attribute *attrs_compute_extended[] = {
2521         &dev_attr_compute_extended_id.attr,
2522         NULL,
2523 };
2524
2525 static struct attribute_group group_compute_extended = {
2526         .name = "4af0400a-81c3-47db-a6b6-deddbd75680e",
2527         .attrs =  attrs_compute_extended,
2528 };
2529
2530 static ssize_t
2531 show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
2532 {
2533         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
2534 }
2535
2536 static struct device_attribute dev_attr_compute_l3_cache_id = {
2537         .attr = { .name = "id", .mode = 0444 },
2538         .show = show_compute_l3_cache_id,
2539         .store = NULL,
2540 };
2541
2542 static struct attribute *attrs_compute_l3_cache[] = {
2543         &dev_attr_compute_l3_cache_id.attr,
2544         NULL,
2545 };
2546
2547 static struct attribute_group group_compute_l3_cache = {
2548         .name = "0e22f995-79ca-4f67-83ab-e9d9772488d8",
2549         .attrs =  attrs_compute_l3_cache,
2550 };
2551
2552 static ssize_t
2553 show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
2554 {
2555         return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
2556 }
2557
2558 static struct device_attribute dev_attr_hdc_and_sf_id = {
2559         .attr = { .name = "id", .mode = 0444 },
2560         .show = show_hdc_and_sf_id,
2561         .store = NULL,
2562 };
2563
2564 static struct attribute *attrs_hdc_and_sf[] = {
2565         &dev_attr_hdc_and_sf_id.attr,
2566         NULL,
2567 };
2568
2569 static struct attribute_group group_hdc_and_sf = {
2570         .name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937",
2571         .attrs =  attrs_hdc_and_sf,
2572 };
2573
2574 static ssize_t
2575 show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2576 {
2577         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
2578 }
2579
2580 static struct device_attribute dev_attr_l3_1_id = {
2581         .attr = { .name = "id", .mode = 0444 },
2582         .show = show_l3_1_id,
2583         .store = NULL,
2584 };
2585
2586 static struct attribute *attrs_l3_1[] = {
2587         &dev_attr_l3_1_id.attr,
2588         NULL,
2589 };
2590
2591 static struct attribute_group group_l3_1 = {
2592         .name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2",
2593         .attrs =  attrs_l3_1,
2594 };
2595
2596 static ssize_t
2597 show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2598 {
2599         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
2600 }
2601
2602 static struct device_attribute dev_attr_l3_2_id = {
2603         .attr = { .name = "id", .mode = 0444 },
2604         .show = show_l3_2_id,
2605         .store = NULL,
2606 };
2607
2608 static struct attribute *attrs_l3_2[] = {
2609         &dev_attr_l3_2_id.attr,
2610         NULL,
2611 };
2612
2613 static struct attribute_group group_l3_2 = {
2614         .name = "2f8e32e4-5956-46e2-af31-c8ea95887332",
2615         .attrs =  attrs_l3_2,
2616 };
2617
2618 static ssize_t
2619 show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
2620 {
2621         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
2622 }
2623
2624 static struct device_attribute dev_attr_l3_3_id = {
2625         .attr = { .name = "id", .mode = 0444 },
2626         .show = show_l3_3_id,
2627         .store = NULL,
2628 };
2629
2630 static struct attribute *attrs_l3_3[] = {
2631         &dev_attr_l3_3_id.attr,
2632         NULL,
2633 };
2634
2635 static struct attribute_group group_l3_3 = {
2636         .name = "ca046aad-b5fb-4101-adce-6473ee6e5b14",
2637         .attrs =  attrs_l3_3,
2638 };
2639
2640 static ssize_t
2641 show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
2642 {
2643         return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
2644 }
2645
2646 static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
2647         .attr = { .name = "id", .mode = 0444 },
2648         .show = show_rasterizer_and_pixel_backend_id,
2649         .store = NULL,
2650 };
2651
2652 static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
2653         &dev_attr_rasterizer_and_pixel_backend_id.attr,
2654         NULL,
2655 };
2656
2657 static struct attribute_group group_rasterizer_and_pixel_backend = {
2658         .name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f",
2659         .attrs =  attrs_rasterizer_and_pixel_backend,
2660 };
2661
2662 static ssize_t
2663 show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
2664 {
2665         return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
2666 }
2667
2668 static struct device_attribute dev_attr_sampler_id = {
2669         .attr = { .name = "id", .mode = 0444 },
2670         .show = show_sampler_id,
2671         .store = NULL,
2672 };
2673
2674 static struct attribute *attrs_sampler[] = {
2675         &dev_attr_sampler_id.attr,
2676         NULL,
2677 };
2678
2679 static struct attribute_group group_sampler = {
2680         .name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af",
2681         .attrs =  attrs_sampler,
2682 };
2683
2684 static ssize_t
2685 show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2686 {
2687         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
2688 }
2689
2690 static struct device_attribute dev_attr_tdl_1_id = {
2691         .attr = { .name = "id", .mode = 0444 },
2692         .show = show_tdl_1_id,
2693         .store = NULL,
2694 };
2695
2696 static struct attribute *attrs_tdl_1[] = {
2697         &dev_attr_tdl_1_id.attr,
2698         NULL,
2699 };
2700
2701 static struct attribute_group group_tdl_1 = {
2702         .name = "105db928-5542-466b-9128-e1f3c91426cb",
2703         .attrs =  attrs_tdl_1,
2704 };
2705
2706 static ssize_t
2707 show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2708 {
2709         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
2710 }
2711
2712 static struct device_attribute dev_attr_tdl_2_id = {
2713         .attr = { .name = "id", .mode = 0444 },
2714         .show = show_tdl_2_id,
2715         .store = NULL,
2716 };
2717
2718 static struct attribute *attrs_tdl_2[] = {
2719         &dev_attr_tdl_2_id.attr,
2720         NULL,
2721 };
2722
2723 static struct attribute_group group_tdl_2 = {
2724         .name = "03db94d2-b37f-4c58-a791-0d2067b013bb",
2725         .attrs =  attrs_tdl_2,
2726 };
2727
2728 static ssize_t
2729 show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
2730 {
2731         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
2732 }
2733
2734 static struct device_attribute dev_attr_compute_extra_id = {
2735         .attr = { .name = "id", .mode = 0444 },
2736         .show = show_compute_extra_id,
2737         .store = NULL,
2738 };
2739
2740 static struct attribute *attrs_compute_extra[] = {
2741         &dev_attr_compute_extra_id.attr,
2742         NULL,
2743 };
2744
2745 static struct attribute_group group_compute_extra = {
2746         .name = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16",
2747         .attrs =  attrs_compute_extra,
2748 };
2749
2750 static ssize_t
2751 show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
2752 {
2753         return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
2754 }
2755
2756 static struct device_attribute dev_attr_vme_pipe_id = {
2757         .attr = { .name = "id", .mode = 0444 },
2758         .show = show_vme_pipe_id,
2759         .store = NULL,
2760 };
2761
2762 static struct attribute *attrs_vme_pipe[] = {
2763         &dev_attr_vme_pipe_id.attr,
2764         NULL,
2765 };
2766
2767 static struct attribute_group group_vme_pipe = {
2768         .name = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61",
2769         .attrs =  attrs_vme_pipe,
2770 };
2771
2772 static ssize_t
2773 show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
2774 {
2775         return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
2776 }
2777
2778 static struct device_attribute dev_attr_test_oa_id = {
2779         .attr = { .name = "id", .mode = 0444 },
2780         .show = show_test_oa_id,
2781         .store = NULL,
2782 };
2783
2784 static struct attribute *attrs_test_oa[] = {
2785         &dev_attr_test_oa_id.attr,
2786         NULL,
2787 };
2788
2789 static struct attribute_group group_test_oa = {
2790         .name = "baa3c7e4-52b6-4b85-801e-465a94b746dd",
2791         .attrs =  attrs_test_oa,
2792 };
2793
2794 int
2795 i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv)
2796 {
2797         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2798         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2799         int ret = 0;
2800
2801         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2802                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2803                 if (ret)
2804                         goto error_render_basic;
2805         }
2806         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2807                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2808                 if (ret)
2809                         goto error_compute_basic;
2810         }
2811         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
2812                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2813                 if (ret)
2814                         goto error_render_pipe_profile;
2815         }
2816         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
2817                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2818                 if (ret)
2819                         goto error_memory_reads;
2820         }
2821         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
2822                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2823                 if (ret)
2824                         goto error_memory_writes;
2825         }
2826         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
2827                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2828                 if (ret)
2829                         goto error_compute_extended;
2830         }
2831         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
2832                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2833                 if (ret)
2834                         goto error_compute_l3_cache;
2835         }
2836         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
2837                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2838                 if (ret)
2839                         goto error_hdc_and_sf;
2840         }
2841         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2842                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2843                 if (ret)
2844                         goto error_l3_1;
2845         }
2846         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2847                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2848                 if (ret)
2849                         goto error_l3_2;
2850         }
2851         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
2852                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2853                 if (ret)
2854                         goto error_l3_3;
2855         }
2856         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
2857                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2858                 if (ret)
2859                         goto error_rasterizer_and_pixel_backend;
2860         }
2861         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
2862                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
2863                 if (ret)
2864                         goto error_sampler;
2865         }
2866         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2867                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2868                 if (ret)
2869                         goto error_tdl_1;
2870         }
2871         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2872                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2873                 if (ret)
2874                         goto error_tdl_2;
2875         }
2876         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
2877                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2878                 if (ret)
2879                         goto error_compute_extra;
2880         }
2881         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
2882                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2883                 if (ret)
2884                         goto error_vme_pipe;
2885         }
2886         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
2887                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2888                 if (ret)
2889                         goto error_test_oa;
2890         }
2891
2892         return 0;
2893
2894 error_test_oa:
2895         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
2896                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2897 error_vme_pipe:
2898         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2899                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2900 error_compute_extra:
2901         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2902                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2903 error_tdl_2:
2904         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2905                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2906 error_tdl_1:
2907         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2908                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2909 error_sampler:
2910         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2911                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2912 error_rasterizer_and_pixel_backend:
2913         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
2914                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2915 error_l3_3:
2916         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
2917                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2918 error_l3_2:
2919         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2920                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2921 error_l3_1:
2922         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2923                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2924 error_hdc_and_sf:
2925         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2926                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2927 error_compute_l3_cache:
2928         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2929                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2930 error_compute_extended:
2931         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2932                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2933 error_memory_writes:
2934         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2935                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2936 error_memory_reads:
2937         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2938                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2939 error_render_pipe_profile:
2940         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2941                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2942 error_compute_basic:
2943         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2944                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2945 error_render_basic:
2946         return ret;
2947 }
2948
2949 void
2950 i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv)
2951 {
2952         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2953         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2954
2955         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2956                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2957         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2958                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2959         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2960                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2961         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2962                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2963         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2964                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2965         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2966                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2967         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2968                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2969         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2970                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2971         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2972                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2973         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
2974                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2975         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
2976                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2977         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2978                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2979         if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2980                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2981         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2982                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2983         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2984                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2985         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2986                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2987         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
2988                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
2989         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
2990                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2991 }