drivers/gpu/drm/i915/i915_oa_bdw.c

   1 /*
   2  * Autogenerated file by GPU Top : https://github.com/rib/gputop
   3  * DO NOT EDIT manually!
   4  *
   5  *
   6  * Copyright (c) 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysfs.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_oa_bdw.h"
  33
  34 enum metric_set_id {
  35         METRIC_SET_ID_RENDER_BASIC = 1,
  36         METRIC_SET_ID_COMPUTE_BASIC,
  37         METRIC_SET_ID_RENDER_PIPE_PROFILE,
  38         METRIC_SET_ID_MEMORY_READS,
  39         METRIC_SET_ID_MEMORY_WRITES,
  40         METRIC_SET_ID_COMPUTE_EXTENDED,
  41         METRIC_SET_ID_COMPUTE_L3_CACHE,
  42         METRIC_SET_ID_DATA_PORT_READS_COALESCING,
  43         METRIC_SET_ID_DATA_PORT_WRITES_COALESCING,
  44         METRIC_SET_ID_HDC_AND_SF,
  45         METRIC_SET_ID_L3_1,
  46         METRIC_SET_ID_L3_2,
  47         METRIC_SET_ID_L3_3,
  48         METRIC_SET_ID_L3_4,
  49         METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
  50         METRIC_SET_ID_SAMPLER_1,
  51         METRIC_SET_ID_SAMPLER_2,
  52         METRIC_SET_ID_TDL_1,
  53         METRIC_SET_ID_TDL_2,
  54         METRIC_SET_ID_COMPUTE_EXTRA,
  55         METRIC_SET_ID_VME_PIPE,
  56         METRIC_SET_ID_TEST_OA,
  57 };
  58
  59 int i915_oa_n_builtin_metric_sets_bdw = 22;
  60
  61 static const struct i915_oa_reg b_counter_config_render_basic[] = {
  62         { _MMIO(0x2710), 0x00000000 },
  63         { _MMIO(0x2714), 0x00800000 },
  64         { _MMIO(0x2720), 0x00000000 },
  65         { _MMIO(0x2724), 0x00800000 },
  66         { _MMIO(0x2740), 0x00000000 },
  67 };
  68
  69 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
  70         { _MMIO(0xe458), 0x00005004 },
  71         { _MMIO(0xe558), 0x00010003 },
  72         { _MMIO(0xe658), 0x00012011 },
  73         { _MMIO(0xe758), 0x00015014 },
  74         { _MMIO(0xe45c), 0x00051050 },
  75         { _MMIO(0xe55c), 0x00053052 },
  76         { _MMIO(0xe65c), 0x00055054 },
  77 };
  78
  79 static const struct i915_oa_reg mux_config_render_basic_0_slices_0x01[] = {
  80         { _MMIO(0x9888), 0x143f000f },
  81         { _MMIO(0x9888), 0x14110014 },
  82         { _MMIO(0x9888), 0x14310014 },
  83         { _MMIO(0x9888), 0x14bf000f },
  84         { _MMIO(0x9888), 0x118a0317 },
  85         { _MMIO(0x9888), 0x13837be0 },
  86         { _MMIO(0x9888), 0x3b800060 },
  87         { _MMIO(0x9888), 0x3d800005 },
  88         { _MMIO(0x9888), 0x005c4000 },
  89         { _MMIO(0x9888), 0x065c8000 },
  90         { _MMIO(0x9888), 0x085cc000 },
  91         { _MMIO(0x9888), 0x003d8000 },
  92         { _MMIO(0x9888), 0x183d0800 },
  93         { _MMIO(0x9888), 0x0a3f0023 },
  94         { _MMIO(0x9888), 0x103f0000 },
  95         { _MMIO(0x9888), 0x00584000 },
  96         { _MMIO(0x9888), 0x08584000 },
  97         { _MMIO(0x9888), 0x0a5a4000 },
  98         { _MMIO(0x9888), 0x005b4000 },
  99         { _MMIO(0x9888), 0x0e5b8000 },
 100         { _MMIO(0x9888), 0x185b2400 },
 101         { _MMIO(0x9888), 0x0a1d4000 },
 102         { _MMIO(0x9888), 0x0c1f0800 },
 103         { _MMIO(0x9888), 0x0e1faa00 },
 104         { _MMIO(0x9888), 0x00384000 },
 105         { _MMIO(0x9888), 0x0e384000 },
 106         { _MMIO(0x9888), 0x16384000 },
 107         { _MMIO(0x9888), 0x18380001 },
 108         { _MMIO(0x9888), 0x00392000 },
 109         { _MMIO(0x9888), 0x06398000 },
 110         { _MMIO(0x9888), 0x0839a000 },
 111         { _MMIO(0x9888), 0x0a391000 },
 112         { _MMIO(0x9888), 0x00104000 },
 113         { _MMIO(0x9888), 0x08104000 },
 114         { _MMIO(0x9888), 0x00110030 },
 115         { _MMIO(0x9888), 0x08110031 },
 116         { _MMIO(0x9888), 0x10110000 },
 117         { _MMIO(0x9888), 0x00134000 },
 118         { _MMIO(0x9888), 0x16130020 },
 119         { _MMIO(0x9888), 0x06308000 },
 120         { _MMIO(0x9888), 0x08308000 },
 121         { _MMIO(0x9888), 0x06311800 },
 122         { _MMIO(0x9888), 0x08311880 },
 123         { _MMIO(0x9888), 0x10310000 },
 124         { _MMIO(0x9888), 0x0e334000 },
 125         { _MMIO(0x9888), 0x16330080 },
 126         { _MMIO(0x9888), 0x0abf1180 },
 127         { _MMIO(0x9888), 0x10bf0000 },
 128         { _MMIO(0x9888), 0x0ada8000 },
 129         { _MMIO(0x9888), 0x0a9d8000 },
 130         { _MMIO(0x9888), 0x109f0002 },
 131         { _MMIO(0x9888), 0x0ab94000 },
 132         { _MMIO(0x9888), 0x0d888000 },
 133         { _MMIO(0x9888), 0x038a0380 },
 134         { _MMIO(0x9888), 0x058a000e },
 135         { _MMIO(0x9888), 0x018a8000 },
 136         { _MMIO(0x9888), 0x0f8a8000 },
 137         { _MMIO(0x9888), 0x198a8000 },
 138         { _MMIO(0x9888), 0x1b8a00a0 },
 139         { _MMIO(0x9888), 0x078a0000 },
 140         { _MMIO(0x9888), 0x098a0000 },
 141         { _MMIO(0x9888), 0x238b2820 },
 142         { _MMIO(0x9888), 0x258b2550 },
 143         { _MMIO(0x9888), 0x198c1000 },
 144         { _MMIO(0x9888), 0x0b8d8000 },
 145         { _MMIO(0x9888), 0x1f85aa80 },
 146         { _MMIO(0x9888), 0x2185aaa0 },
 147         { _MMIO(0x9888), 0x2385002a },
 148         { _MMIO(0x9888), 0x0d831021 },
 149         { _MMIO(0x9888), 0x0f83572f },
 150         { _MMIO(0x9888), 0x01835680 },
 151         { _MMIO(0x9888), 0x0383002c },
 152         { _MMIO(0x9888), 0x11830000 },
 153         { _MMIO(0x9888), 0x19835400 },
 154         { _MMIO(0x9888), 0x1b830001 },
 155         { _MMIO(0x9888), 0x05830000 },
 156         { _MMIO(0x9888), 0x07834000 },
 157         { _MMIO(0x9888), 0x09834000 },
 158         { _MMIO(0x9888), 0x0184c000 },
 159         { _MMIO(0x9888), 0x07848000 },
 160         { _MMIO(0x9888), 0x0984c000 },
 161         { _MMIO(0x9888), 0x0b84c000 },
 162         { _MMIO(0x9888), 0x0d84c000 },
 163         { _MMIO(0x9888), 0x0f84c000 },
 164         { _MMIO(0x9888), 0x0384c000 },
 165         { _MMIO(0x9888), 0x05844000 },
 166         { _MMIO(0x9888), 0x1b80c137 },
 167         { _MMIO(0x9888), 0x1d80c147 },
 168         { _MMIO(0x9888), 0x21800000 },
 169         { _MMIO(0x9888), 0x1180c000 },
 170         { _MMIO(0x9888), 0x17808000 },
 171         { _MMIO(0x9888), 0x1980c000 },
 172         { _MMIO(0x9888), 0x1f80c000 },
 173         { _MMIO(0x9888), 0x1380c000 },
 174         { _MMIO(0x9888), 0x15804000 },
 175         { _MMIO(0x9888), 0x4d801110 },
 176         { _MMIO(0x9888), 0x4f800331 },
 177         { _MMIO(0x9888), 0x43800802 },
 178         { _MMIO(0x9888), 0x51800000 },
 179         { _MMIO(0x9888), 0x45801465 },
 180         { _MMIO(0x9888), 0x53801111 },
 181         { _MMIO(0x9888), 0x478014a5 },
 182         { _MMIO(0x9888), 0x31800000 },
 183         { _MMIO(0x9888), 0x3f800ca5 },
 184         { _MMIO(0x9888), 0x41800003 },
 185 };
 186
 187 static const struct i915_oa_reg mux_config_render_basic_1_slices_0x02[] = {
 188         { _MMIO(0x9888), 0x143f000f },
 189         { _MMIO(0x9888), 0x14bf000f },
 190         { _MMIO(0x9888), 0x14910014 },
 191         { _MMIO(0x9888), 0x14b10014 },
 192         { _MMIO(0x9888), 0x118a0317 },
 193         { _MMIO(0x9888), 0x13837be0 },
 194         { _MMIO(0x9888), 0x3b800060 },
 195         { _MMIO(0x9888), 0x3d800005 },
 196         { _MMIO(0x9888), 0x0a3f0023 },
 197         { _MMIO(0x9888), 0x103f0000 },
 198         { _MMIO(0x9888), 0x0a5a4000 },
 199         { _MMIO(0x9888), 0x0a1d4000 },
 200         { _MMIO(0x9888), 0x0e1f8000 },
 201         { _MMIO(0x9888), 0x0a391000 },
 202         { _MMIO(0x9888), 0x00dc4000 },
 203         { _MMIO(0x9888), 0x06dc8000 },
 204         { _MMIO(0x9888), 0x08dcc000 },
 205         { _MMIO(0x9888), 0x00bd8000 },
 206         { _MMIO(0x9888), 0x18bd0800 },
 207         { _MMIO(0x9888), 0x0abf1180 },
 208         { _MMIO(0x9888), 0x10bf0000 },
 209         { _MMIO(0x9888), 0x00d84000 },
 210         { _MMIO(0x9888), 0x08d84000 },
 211         { _MMIO(0x9888), 0x0ada8000 },
 212         { _MMIO(0x9888), 0x00db4000 },
 213         { _MMIO(0x9888), 0x0edb8000 },
 214         { _MMIO(0x9888), 0x18db2400 },
 215         { _MMIO(0x9888), 0x0a9d8000 },
 216         { _MMIO(0x9888), 0x0c9f0800 },
 217         { _MMIO(0x9888), 0x0e9f2a00 },
 218         { _MMIO(0x9888), 0x109f0002 },
 219         { _MMIO(0x9888), 0x00b84000 },
 220         { _MMIO(0x9888), 0x0eb84000 },
 221         { _MMIO(0x9888), 0x16b84000 },
 222         { _MMIO(0x9888), 0x18b80001 },
 223         { _MMIO(0x9888), 0x00b92000 },
 224         { _MMIO(0x9888), 0x06b98000 },
 225         { _MMIO(0x9888), 0x08b9a000 },
 226         { _MMIO(0x9888), 0x0ab94000 },
 227         { _MMIO(0x9888), 0x00904000 },
 228         { _MMIO(0x9888), 0x08904000 },
 229         { _MMIO(0x9888), 0x00910030 },
 230         { _MMIO(0x9888), 0x08910031 },
 231         { _MMIO(0x9888), 0x10910000 },
 232         { _MMIO(0x9888), 0x00934000 },
 233         { _MMIO(0x9888), 0x16930020 },
 234         { _MMIO(0x9888), 0x06b08000 },
 235         { _MMIO(0x9888), 0x08b08000 },
 236         { _MMIO(0x9888), 0x06b11800 },
 237         { _MMIO(0x9888), 0x08b11880 },
 238         { _MMIO(0x9888), 0x10b10000 },
 239         { _MMIO(0x9888), 0x0eb34000 },
 240         { _MMIO(0x9888), 0x16b30080 },
 241         { _MMIO(0x9888), 0x01888000 },
 242         { _MMIO(0x9888), 0x0d88b800 },
 243         { _MMIO(0x9888), 0x038a0380 },
 244         { _MMIO(0x9888), 0x058a000e },
 245         { _MMIO(0x9888), 0x1b8a0080 },
 246         { _MMIO(0x9888), 0x078a0000 },
 247         { _MMIO(0x9888), 0x098a0000 },
 248         { _MMIO(0x9888), 0x238b2840 },
 249         { _MMIO(0x9888), 0x258b26a0 },
 250         { _MMIO(0x9888), 0x018c4000 },
 251         { _MMIO(0x9888), 0x0f8c4000 },
 252         { _MMIO(0x9888), 0x178c2000 },
 253         { _MMIO(0x9888), 0x198c1100 },
 254         { _MMIO(0x9888), 0x018d2000 },
 255         { _MMIO(0x9888), 0x078d8000 },
 256         { _MMIO(0x9888), 0x098da000 },
 257         { _MMIO(0x9888), 0x0b8d8000 },
 258         { _MMIO(0x9888), 0x1f85aa80 },
 259         { _MMIO(0x9888), 0x2185aaa0 },
 260         { _MMIO(0x9888), 0x2385002a },
 261         { _MMIO(0x9888), 0x0d831021 },
 262         { _MMIO(0x9888), 0x0f83572f },
 263         { _MMIO(0x9888), 0x01835680 },
 264         { _MMIO(0x9888), 0x0383002c },
 265         { _MMIO(0x9888), 0x11830000 },
 266         { _MMIO(0x9888), 0x19835400 },
 267         { _MMIO(0x9888), 0x1b830001 },
 268         { _MMIO(0x9888), 0x05830000 },
 269         { _MMIO(0x9888), 0x07834000 },
 270         { _MMIO(0x9888), 0x09834000 },
 271         { _MMIO(0x9888), 0x0184c000 },
 272         { _MMIO(0x9888), 0x07848000 },
 273         { _MMIO(0x9888), 0x0984c000 },
 274         { _MMIO(0x9888), 0x0b84c000 },
 275         { _MMIO(0x9888), 0x0d84c000 },
 276         { _MMIO(0x9888), 0x0f84c000 },
 277         { _MMIO(0x9888), 0x0384c000 },
 278         { _MMIO(0x9888), 0x05844000 },
 279         { _MMIO(0x9888), 0x1b80c137 },
 280         { _MMIO(0x9888), 0x1d80c147 },
 281         { _MMIO(0x9888), 0x21800000 },
 282         { _MMIO(0x9888), 0x1180c000 },
 283         { _MMIO(0x9888), 0x17808000 },
 284         { _MMIO(0x9888), 0x1980c000 },
 285         { _MMIO(0x9888), 0x1f80c000 },
 286         { _MMIO(0x9888), 0x1380c000 },
 287         { _MMIO(0x9888), 0x15804000 },
 288         { _MMIO(0x9888), 0x4d801550 },
 289         { _MMIO(0x9888), 0x4f800331 },
 290         { _MMIO(0x9888), 0x43800802 },
 291         { _MMIO(0x9888), 0x51800400 },
 292         { _MMIO(0x9888), 0x458004a1 },
 293         { _MMIO(0x9888), 0x53805555 },
 294         { _MMIO(0x9888), 0x47800421 },
 295         { _MMIO(0x9888), 0x31800000 },
 296         { _MMIO(0x9888), 0x3f801421 },
 297         { _MMIO(0x9888), 0x41800845 },
 298 };
 299
 300 static int
 301 get_render_basic_mux_config(struct drm_i915_private *dev_priv,
 302                             const struct i915_oa_reg **regs,
 303                             int *lens)
 304 {
 305         int n = 0;
 306
 307         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
 308         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
 309
 310         if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) {
 311                 regs[n] = mux_config_render_basic_0_slices_0x01;
 312                 lens[n] = ARRAY_SIZE(mux_config_render_basic_0_slices_0x01);
 313                 n++;
 314         }
 315         if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) {
 316                 regs[n] = mux_config_render_basic_1_slices_0x02;
 317                 lens[n] = ARRAY_SIZE(mux_config_render_basic_1_slices_0x02);
 318                 n++;
 319         }
 320
 321         return n;
 322 }
 323
 324 static const struct i915_oa_reg b_counter_config_compute_basic[] = {
 325         { _MMIO(0x2710), 0x00000000 },
 326         { _MMIO(0x2714), 0x00800000 },
 327         { _MMIO(0x2720), 0x00000000 },
 328         { _MMIO(0x2724), 0x00800000 },
 329         { _MMIO(0x2740), 0x00000000 },
 330 };
 331
 332 static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
 333         { _MMIO(0xe458), 0x00005004 },
 334         { _MMIO(0xe558), 0x00000003 },
 335         { _MMIO(0xe658), 0x00002001 },
 336         { _MMIO(0xe758), 0x00778008 },
 337         { _MMIO(0xe45c), 0x00088078 },
 338         { _MMIO(0xe55c), 0x00808708 },
 339         { _MMIO(0xe65c), 0x00a08908 },
 340 };
 341
 342 static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01[] = {
 343         { _MMIO(0x9888), 0x105c00e0 },
 344         { _MMIO(0x9888), 0x105800e0 },
 345         { _MMIO(0x9888), 0x103800e0 },
 346         { _MMIO(0x9888), 0x3580001a },
 347         { _MMIO(0x9888), 0x3b800060 },
 348         { _MMIO(0x9888), 0x3d800005 },
 349         { _MMIO(0x9888), 0x065c2100 },
 350         { _MMIO(0x9888), 0x0a5c0041 },
 351         { _MMIO(0x9888), 0x0c5c6600 },
 352         { _MMIO(0x9888), 0x005c6580 },
 353         { _MMIO(0x9888), 0x085c8000 },
 354         { _MMIO(0x9888), 0x0e5c8000 },
 355         { _MMIO(0x9888), 0x00580042 },
 356         { _MMIO(0x9888), 0x08582080 },
 357         { _MMIO(0x9888), 0x0c58004c },
 358         { _MMIO(0x9888), 0x0e582580 },
 359         { _MMIO(0x9888), 0x005b4000 },
 360         { _MMIO(0x9888), 0x185b1000 },
 361         { _MMIO(0x9888), 0x1a5b0104 },
 362         { _MMIO(0x9888), 0x0c1fa800 },
 363         { _MMIO(0x9888), 0x0e1faa00 },
 364         { _MMIO(0x9888), 0x101f02aa },
 365         { _MMIO(0x9888), 0x08380042 },
 366         { _MMIO(0x9888), 0x0a382080 },
 367         { _MMIO(0x9888), 0x0e38404c },
 368         { _MMIO(0x9888), 0x0238404b },
 369         { _MMIO(0x9888), 0x00384000 },
 370         { _MMIO(0x9888), 0x16380000 },
 371         { _MMIO(0x9888), 0x18381145 },
 372         { _MMIO(0x9888), 0x04380000 },
 373         { _MMIO(0x9888), 0x0039a000 },
 374         { _MMIO(0x9888), 0x06398000 },
 375         { _MMIO(0x9888), 0x0839a000 },
 376         { _MMIO(0x9888), 0x0a39a000 },
 377         { _MMIO(0x9888), 0x0c39a000 },
 378         { _MMIO(0x9888), 0x0e39a000 },
 379         { _MMIO(0x9888), 0x02392000 },
 380         { _MMIO(0x9888), 0x018a8000 },
 381         { _MMIO(0x9888), 0x0f8a8000 },
 382         { _MMIO(0x9888), 0x198a8000 },
 383         { _MMIO(0x9888), 0x1b8aaaa0 },
 384         { _MMIO(0x9888), 0x1d8a0002 },
 385         { _MMIO(0x9888), 0x038a8000 },
 386         { _MMIO(0x9888), 0x058a8000 },
 387         { _MMIO(0x9888), 0x238b02a0 },
 388         { _MMIO(0x9888), 0x258b5550 },
 389         { _MMIO(0x9888), 0x278b0015 },
 390         { _MMIO(0x9888), 0x1f850a80 },
 391         { _MMIO(0x9888), 0x2185aaa0 },
 392         { _MMIO(0x9888), 0x2385002a },
 393         { _MMIO(0x9888), 0x01834000 },
 394         { _MMIO(0x9888), 0x0f834000 },
 395         { _MMIO(0x9888), 0x19835400 },
 396         { _MMIO(0x9888), 0x1b830155 },
 397         { _MMIO(0x9888), 0x03834000 },
 398         { _MMIO(0x9888), 0x05834000 },
 399         { _MMIO(0x9888), 0x0184c000 },
 400         { _MMIO(0x9888), 0x07848000 },
 401         { _MMIO(0x9888), 0x0984c000 },
 402         { _MMIO(0x9888), 0x0b84c000 },
 403         { _MMIO(0x9888), 0x0d84c000 },
 404         { _MMIO(0x9888), 0x0f84c000 },
 405         { _MMIO(0x9888), 0x03844000 },
 406         { _MMIO(0x9888), 0x17808137 },
 407         { _MMIO(0x9888), 0x1980c147 },
 408         { _MMIO(0x9888), 0x1b80c0e5 },
 409         { _MMIO(0x9888), 0x1d80c0e3 },
 410         { _MMIO(0x9888), 0x21800000 },
 411         { _MMIO(0x9888), 0x1180c000 },
 412         { _MMIO(0x9888), 0x1f80c000 },
 413         { _MMIO(0x9888), 0x13804000 },
 414         { _MMIO(0x9888), 0x15800000 },
 415         { _MMIO(0xd24), 0x00000000 },
 416         { _MMIO(0x9888), 0x4d801000 },
 417         { _MMIO(0x9888), 0x4f800111 },
 418         { _MMIO(0x9888), 0x43800062 },
 419         { _MMIO(0x9888), 0x51800000 },
 420         { _MMIO(0x9888), 0x45800062 },
 421         { _MMIO(0x9888), 0x53800000 },
 422         { _MMIO(0x9888), 0x47800062 },
 423         { _MMIO(0x9888), 0x31800000 },
 424         { _MMIO(0x9888), 0x3f801062 },
 425         { _MMIO(0x9888), 0x41801084 },
 426 };
 427
 428 static const struct i915_oa_reg mux_config_compute_basic_2_slices_0x02[] = {
 429         { _MMIO(0x9888), 0x10dc00e0 },
 430         { _MMIO(0x9888), 0x10d800e0 },
 431         { _MMIO(0x9888), 0x10b800e0 },
 432         { _MMIO(0x9888), 0x3580001a },
 433         { _MMIO(0x9888), 0x3b800060 },
 434         { _MMIO(0x9888), 0x3d800005 },
 435         { _MMIO(0x9888), 0x06dc2100 },
 436         { _MMIO(0x9888), 0x0adc0041 },
 437         { _MMIO(0x9888), 0x0cdc6600 },
 438         { _MMIO(0x9888), 0x00dc6580 },
 439         { _MMIO(0x9888), 0x08dc8000 },
 440         { _MMIO(0x9888), 0x0edc8000 },
 441         { _MMIO(0x9888), 0x00d80042 },
 442         { _MMIO(0x9888), 0x08d82080 },
 443         { _MMIO(0x9888), 0x0cd8004c },
 444         { _MMIO(0x9888), 0x0ed82580 },
 445         { _MMIO(0x9888), 0x00db4000 },
 446         { _MMIO(0x9888), 0x18db1000 },
 447         { _MMIO(0x9888), 0x1adb0104 },
 448         { _MMIO(0x9888), 0x0c9fa800 },
 449         { _MMIO(0x9888), 0x0e9faa00 },
 450         { _MMIO(0x9888), 0x109f02aa },
 451         { _MMIO(0x9888), 0x08b80042 },
 452         { _MMIO(0x9888), 0x0ab82080 },
 453         { _MMIO(0x9888), 0x0eb8404c },
 454         { _MMIO(0x9888), 0x02b8404b },
 455         { _MMIO(0x9888), 0x00b84000 },
 456         { _MMIO(0x9888), 0x16b80000 },
 457         { _MMIO(0x9888), 0x18b81145 },
 458         { _MMIO(0x9888), 0x04b80000 },
 459         { _MMIO(0x9888), 0x00b9a000 },
 460         { _MMIO(0x9888), 0x06b98000 },
 461         { _MMIO(0x9888), 0x08b9a000 },
 462         { _MMIO(0x9888), 0x0ab9a000 },
 463         { _MMIO(0x9888), 0x0cb9a000 },
 464         { _MMIO(0x9888), 0x0eb9a000 },
 465         { _MMIO(0x9888), 0x02b92000 },
 466         { _MMIO(0x9888), 0x01888000 },
 467         { _MMIO(0x9888), 0x0d88f800 },
 468         { _MMIO(0x9888), 0x0f88000f },
 469         { _MMIO(0x9888), 0x03888000 },
 470         { _MMIO(0x9888), 0x05888000 },
 471         { _MMIO(0x9888), 0x238b0540 },
 472         { _MMIO(0x9888), 0x258baaa0 },
 473         { _MMIO(0x9888), 0x278b002a },
 474         { _MMIO(0x9888), 0x018c4000 },
 475         { _MMIO(0x9888), 0x0f8c4000 },
 476         { _MMIO(0x9888), 0x178c2000 },
 477         { _MMIO(0x9888), 0x198c5500 },
 478         { _MMIO(0x9888), 0x1b8c0015 },
 479         { _MMIO(0x9888), 0x038c4000 },
 480         { _MMIO(0x9888), 0x058c4000 },
 481         { _MMIO(0x9888), 0x018da000 },
 482         { _MMIO(0x9888), 0x078d8000 },
 483         { _MMIO(0x9888), 0x098da000 },
 484         { _MMIO(0x9888), 0x0b8da000 },
 485         { _MMIO(0x9888), 0x0d8da000 },
 486         { _MMIO(0x9888), 0x0f8da000 },
 487         { _MMIO(0x9888), 0x038d2000 },
 488         { _MMIO(0x9888), 0x1f850a80 },
 489         { _MMIO(0x9888), 0x2185aaa0 },
 490         { _MMIO(0x9888), 0x2385002a },
 491         { _MMIO(0x9888), 0x01834000 },
 492         { _MMIO(0x9888), 0x0f834000 },
 493         { _MMIO(0x9888), 0x19835400 },
 494         { _MMIO(0x9888), 0x1b830155 },
 495         { _MMIO(0x9888), 0x03834000 },
 496         { _MMIO(0x9888), 0x05834000 },
 497         { _MMIO(0x9888), 0x0184c000 },
 498         { _MMIO(0x9888), 0x07848000 },
 499         { _MMIO(0x9888), 0x0984c000 },
 500         { _MMIO(0x9888), 0x0b84c000 },
 501         { _MMIO(0x9888), 0x0d84c000 },
 502         { _MMIO(0x9888), 0x0f84c000 },
 503         { _MMIO(0x9888), 0x03844000 },
 504         { _MMIO(0x9888), 0x17808137 },
 505         { _MMIO(0x9888), 0x1980c147 },
 506         { _MMIO(0x9888), 0x1b80c0e5 },
 507         { _MMIO(0x9888), 0x1d80c0e3 },
 508         { _MMIO(0x9888), 0x21800000 },
 509         { _MMIO(0x9888), 0x1180c000 },
 510         { _MMIO(0x9888), 0x1f80c000 },
 511         { _MMIO(0x9888), 0x13804000 },
 512         { _MMIO(0x9888), 0x15800000 },
 513         { _MMIO(0xd24), 0x00000000 },
 514         { _MMIO(0x9888), 0x4d805000 },
 515         { _MMIO(0x9888), 0x4f800555 },
 516         { _MMIO(0x9888), 0x43800062 },
 517         { _MMIO(0x9888), 0x51800000 },
 518         { _MMIO(0x9888), 0x45800062 },
 519         { _MMIO(0x9888), 0x53800000 },
 520         { _MMIO(0x9888), 0x47800062 },
 521         { _MMIO(0x9888), 0x31800000 },
 522         { _MMIO(0x9888), 0x3f800062 },
 523         { _MMIO(0x9888), 0x41800000 },
 524 };
 525
 526 static int
 527 get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
 528                              const struct i915_oa_reg **regs,
 529                              int *lens)
 530 {
 531         int n = 0;
 532
 533         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
 534         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
 535
 536         if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) {
 537                 regs[n] = mux_config_compute_basic_0_slices_0x01;
 538                 lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01);
 539                 n++;
 540         }
 541         if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) {
 542                 regs[n] = mux_config_compute_basic_2_slices_0x02;
 543                 lens[n] = ARRAY_SIZE(mux_config_compute_basic_2_slices_0x02);
 544                 n++;
 545         }
 546
 547         return n;
 548 }
 549
 550 static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
 551         { _MMIO(0x2724), 0xf0800000 },
 552         { _MMIO(0x2720), 0x00000000 },
 553         { _MMIO(0x2714), 0xf0800000 },
 554         { _MMIO(0x2710), 0x00000000 },
 555         { _MMIO(0x2740), 0x00000000 },
 556         { _MMIO(0x2770), 0x0007ffea },
 557         { _MMIO(0x2774), 0x00007ffc },
 558         { _MMIO(0x2778), 0x0007affa },
 559         { _MMIO(0x277c), 0x0000f5fd },
 560         { _MMIO(0x2780), 0x00079ffa },
 561         { _MMIO(0x2784), 0x0000f3fb },
 562         { _MMIO(0x2788), 0x0007bf7a },
 563         { _MMIO(0x278c), 0x0000f7e7 },
 564         { _MMIO(0x2790), 0x0007fefa },
 565         { _MMIO(0x2794), 0x0000f7cf },
 566         { _MMIO(0x2798), 0x00077ffa },
 567         { _MMIO(0x279c), 0x0000efdf },
 568         { _MMIO(0x27a0), 0x0006fffa },
 569         { _MMIO(0x27a4), 0x0000cfbf },
 570         { _MMIO(0x27a8), 0x0003fffa },
 571         { _MMIO(0x27ac), 0x00005f7f },
 572 };
 573
 574 static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
 575         { _MMIO(0xe458), 0x00005004 },
 576         { _MMIO(0xe558), 0x00015014 },
 577         { _MMIO(0xe658), 0x00025024 },
 578         { _MMIO(0xe758), 0x00035034 },
 579         { _MMIO(0xe45c), 0x00045044 },
 580         { _MMIO(0xe55c), 0x00055054 },
 581         { _MMIO(0xe65c), 0x00065064 },
 582 };
 583
 584 static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
 585         { _MMIO(0x9888), 0x0a1e0000 },
 586         { _MMIO(0x9888), 0x0c1f000f },
 587         { _MMIO(0x9888), 0x10176800 },
 588         { _MMIO(0x9888), 0x1191001f },
 589         { _MMIO(0x9888), 0x0b880320 },
 590         { _MMIO(0x9888), 0x01890c40 },
 591         { _MMIO(0x9888), 0x118a1c00 },
 592         { _MMIO(0x9888), 0x118d7c00 },
 593         { _MMIO(0x9888), 0x118e0020 },
 594         { _MMIO(0x9888), 0x118f4c00 },
 595         { _MMIO(0x9888), 0x11900000 },
 596         { _MMIO(0x9888), 0x13900001 },
 597         { _MMIO(0x9888), 0x065c4000 },
 598         { _MMIO(0x9888), 0x0c3d8000 },
 599         { _MMIO(0x9888), 0x06584000 },
 600         { _MMIO(0x9888), 0x0c5b4000 },
 601         { _MMIO(0x9888), 0x081e0040 },
 602         { _MMIO(0x9888), 0x0e1e0000 },
 603         { _MMIO(0x9888), 0x021f5400 },
 604         { _MMIO(0x9888), 0x001f0000 },
 605         { _MMIO(0x9888), 0x101f0010 },
 606         { _MMIO(0x9888), 0x0e1f0080 },
 607         { _MMIO(0x9888), 0x0c384000 },
 608         { _MMIO(0x9888), 0x06392000 },
 609         { _MMIO(0x9888), 0x0c13c000 },
 610         { _MMIO(0x9888), 0x06164000 },
 611         { _MMIO(0x9888), 0x06170012 },
 612         { _MMIO(0x9888), 0x00170000 },
 613         { _MMIO(0x9888), 0x01910005 },
 614         { _MMIO(0x9888), 0x07880002 },
 615         { _MMIO(0x9888), 0x01880c00 },
 616         { _MMIO(0x9888), 0x0f880000 },
 617         { _MMIO(0x9888), 0x0d880000 },
 618         { _MMIO(0x9888), 0x05880000 },
 619         { _MMIO(0x9888), 0x09890032 },
 620         { _MMIO(0x9888), 0x078a0800 },
 621         { _MMIO(0x9888), 0x0f8a0a00 },
 622         { _MMIO(0x9888), 0x198a4000 },
 623         { _MMIO(0x9888), 0x1b8a2000 },
 624         { _MMIO(0x9888), 0x1d8a0000 },
 625         { _MMIO(0x9888), 0x038a4000 },
 626         { _MMIO(0x9888), 0x0b8a8000 },
 627         { _MMIO(0x9888), 0x0d8a8000 },
 628         { _MMIO(0x9888), 0x238b54c0 },
 629         { _MMIO(0x9888), 0x258baa55 },
 630         { _MMIO(0x9888), 0x278b0019 },
 631         { _MMIO(0x9888), 0x198c0100 },
 632         { _MMIO(0x9888), 0x058c4000 },
 633         { _MMIO(0x9888), 0x0f8d0015 },
 634         { _MMIO(0x9888), 0x018d1000 },
 635         { _MMIO(0x9888), 0x098d8000 },
 636         { _MMIO(0x9888), 0x0b8df000 },
 637         { _MMIO(0x9888), 0x0d8d3000 },
 638         { _MMIO(0x9888), 0x038de000 },
 639         { _MMIO(0x9888), 0x058d3000 },
 640         { _MMIO(0x9888), 0x0d8e0004 },
 641         { _MMIO(0x9888), 0x058e000c },
 642         { _MMIO(0x9888), 0x098e0000 },
 643         { _MMIO(0x9888), 0x078e0000 },
 644         { _MMIO(0x9888), 0x038e0000 },
 645         { _MMIO(0x9888), 0x0b8f0020 },
 646         { _MMIO(0x9888), 0x198f0c00 },
 647         { _MMIO(0x9888), 0x078f8000 },
 648         { _MMIO(0x9888), 0x098f4000 },
 649         { _MMIO(0x9888), 0x0b900980 },
 650         { _MMIO(0x9888), 0x03900d80 },
 651         { _MMIO(0x9888), 0x01900000 },
 652         { _MMIO(0x9888), 0x1f85aa80 },
 653         { _MMIO(0x9888), 0x2185aaaa },
 654         { _MMIO(0x9888), 0x2385002a },
 655         { _MMIO(0x9888), 0x01834000 },
 656         { _MMIO(0x9888), 0x0f834000 },
 657         { _MMIO(0x9888), 0x19835400 },
 658         { _MMIO(0x9888), 0x1b830155 },
 659         { _MMIO(0x9888), 0x03834000 },
 660         { _MMIO(0x9888), 0x05834000 },
 661         { _MMIO(0x9888), 0x07834000 },
 662         { _MMIO(0x9888), 0x09834000 },
 663         { _MMIO(0x9888), 0x0b834000 },
 664         { _MMIO(0x9888), 0x0d834000 },
 665         { _MMIO(0x9888), 0x0184c000 },
 666         { _MMIO(0x9888), 0x0784c000 },
 667         { _MMIO(0x9888), 0x0984c000 },
 668         { _MMIO(0x9888), 0x0b84c000 },
 669         { _MMIO(0x9888), 0x0d84c000 },
 670         { _MMIO(0x9888), 0x0f84c000 },
 671         { _MMIO(0x9888), 0x0384c000 },
 672         { _MMIO(0x9888), 0x0584c000 },
 673         { _MMIO(0x9888), 0x1180c000 },
 674         { _MMIO(0x9888), 0x1780c000 },
 675         { _MMIO(0x9888), 0x1980c000 },
 676         { _MMIO(0x9888), 0x1b80c000 },
 677         { _MMIO(0x9888), 0x1d80c000 },
 678         { _MMIO(0x9888), 0x1f80c000 },
 679         { _MMIO(0x9888), 0x1380c000 },
 680         { _MMIO(0x9888), 0x1580c000 },
 681         { _MMIO(0xd24), 0x00000000 },
 682         { _MMIO(0x9888), 0x4d801111 },
 683         { _MMIO(0x9888), 0x3d800800 },
 684         { _MMIO(0x9888), 0x4f801011 },
 685         { _MMIO(0x9888), 0x43800443 },
 686         { _MMIO(0x9888), 0x51801111 },
 687         { _MMIO(0x9888), 0x45800422 },
 688         { _MMIO(0x9888), 0x53801111 },
 689         { _MMIO(0x9888), 0x47800c60 },
 690         { _MMIO(0x9888), 0x21800000 },
 691         { _MMIO(0x9888), 0x31800000 },
 692         { _MMIO(0x9888), 0x3f800422 },
 693         { _MMIO(0x9888), 0x41800021 },
 694 };
 695
 696 static int
 697 get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
 698                                    const struct i915_oa_reg **regs,
 699                                    int *lens)
 700 {
 701         int n = 0;
 702
 703         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 704         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 705
 706         regs[n] = mux_config_render_pipe_profile;
 707         lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
 708         n++;
 709
 710         return n;
 711 }
 712
 713 static const struct i915_oa_reg b_counter_config_memory_reads[] = {
 714         { _MMIO(0x2724), 0xf0800000 },
 715         { _MMIO(0x2720), 0x00000000 },
 716         { _MMIO(0x2714), 0xf0800000 },
 717         { _MMIO(0x2710), 0x00000000 },
 718         { _MMIO(0x274c), 0x86543210 },
 719         { _MMIO(0x2748), 0x86543210 },
 720         { _MMIO(0x2744), 0x00006667 },
 721         { _MMIO(0x2740), 0x00000000 },
 722         { _MMIO(0x275c), 0x86543210 },
 723         { _MMIO(0x2758), 0x86543210 },
 724         { _MMIO(0x2754), 0x00006465 },
 725         { _MMIO(0x2750), 0x00000000 },
 726         { _MMIO(0x2770), 0x0007f81a },
 727         { _MMIO(0x2774), 0x0000fe00 },
 728         { _MMIO(0x2778), 0x0007f82a },
 729         { _MMIO(0x277c), 0x0000fe00 },
 730         { _MMIO(0x2780), 0x0007f872 },
 731         { _MMIO(0x2784), 0x0000fe00 },
 732         { _MMIO(0x2788), 0x0007f8ba },
 733         { _MMIO(0x278c), 0x0000fe00 },
 734         { _MMIO(0x2790), 0x0007f87a },
 735         { _MMIO(0x2794), 0x0000fe00 },
 736         { _MMIO(0x2798), 0x0007f8ea },
 737         { _MMIO(0x279c), 0x0000fe00 },
 738         { _MMIO(0x27a0), 0x0007f8e2 },
 739         { _MMIO(0x27a4), 0x0000fe00 },
 740         { _MMIO(0x27a8), 0x0007f8f2 },
 741         { _MMIO(0x27ac), 0x0000fe00 },
 742 };
 743
 744 static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
 745         { _MMIO(0xe458), 0x00005004 },
 746         { _MMIO(0xe558), 0x00015014 },
 747         { _MMIO(0xe658), 0x00025024 },
 748         { _MMIO(0xe758), 0x00035034 },
 749         { _MMIO(0xe45c), 0x00045044 },
 750         { _MMIO(0xe55c), 0x00055054 },
 751         { _MMIO(0xe65c), 0x00065064 },
 752 };
 753
 754 static const struct i915_oa_reg mux_config_memory_reads[] = {
 755         { _MMIO(0x9888), 0x198b0343 },
 756         { _MMIO(0x9888), 0x13845800 },
 757         { _MMIO(0x9888), 0x15840018 },
 758         { _MMIO(0x9888), 0x3580001a },
 759         { _MMIO(0x9888), 0x038b6300 },
 760         { _MMIO(0x9888), 0x058b6b62 },
 761         { _MMIO(0x9888), 0x078b006a },
 762         { _MMIO(0x9888), 0x118b0000 },
 763         { _MMIO(0x9888), 0x238b0000 },
 764         { _MMIO(0x9888), 0x258b0000 },
 765         { _MMIO(0x9888), 0x1f85a080 },
 766         { _MMIO(0x9888), 0x2185aaaa },
 767         { _MMIO(0x9888), 0x2385000a },
 768         { _MMIO(0x9888), 0x07834000 },
 769         { _MMIO(0x9888), 0x09834000 },
 770         { _MMIO(0x9888), 0x0b834000 },
 771         { _MMIO(0x9888), 0x0d834000 },
 772         { _MMIO(0x9888), 0x01840018 },
 773         { _MMIO(0x9888), 0x07844c80 },
 774         { _MMIO(0x9888), 0x09840d9a },
 775         { _MMIO(0x9888), 0x0b840e9c },
 776         { _MMIO(0x9888), 0x0d840f9e },
 777         { _MMIO(0x9888), 0x0f840010 },
 778         { _MMIO(0x9888), 0x11840000 },
 779         { _MMIO(0x9888), 0x03848000 },
 780         { _MMIO(0x9888), 0x0584c000 },
 781         { _MMIO(0x9888), 0x2f8000e5 },
 782         { _MMIO(0x9888), 0x138080e3 },
 783         { _MMIO(0x9888), 0x1580c0e1 },
 784         { _MMIO(0x9888), 0x21800000 },
 785         { _MMIO(0x9888), 0x11804000 },
 786         { _MMIO(0x9888), 0x1780c000 },
 787         { _MMIO(0x9888), 0x1980c000 },
 788         { _MMIO(0x9888), 0x1b80c000 },
 789         { _MMIO(0x9888), 0x1d80c000 },
 790         { _MMIO(0x9888), 0x1f804000 },
 791         { _MMIO(0xd24), 0x00000000 },
 792         { _MMIO(0x9888), 0x4d800000 },
 793         { _MMIO(0x9888), 0x3d800800 },
 794         { _MMIO(0x9888), 0x4f800000 },
 795         { _MMIO(0x9888), 0x43800842 },
 796         { _MMIO(0x9888), 0x51800000 },
 797         { _MMIO(0x9888), 0x45800842 },
 798         { _MMIO(0x9888), 0x53800000 },
 799         { _MMIO(0x9888), 0x47801042 },
 800         { _MMIO(0x9888), 0x31800000 },
 801         { _MMIO(0x9888), 0x3f800084 },
 802         { _MMIO(0x9888), 0x41800000 },
 803 };
 804
 805 static int
 806 get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
 807                             const struct i915_oa_reg **regs,
 808                             int *lens)
 809 {
 810         int n = 0;
 811
 812         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 813         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 814
 815         regs[n] = mux_config_memory_reads;
 816         lens[n] = ARRAY_SIZE(mux_config_memory_reads);
 817         n++;
 818
 819         return n;
 820 }
 821
 822 static const struct i915_oa_reg b_counter_config_memory_writes[] = {
 823         { _MMIO(0x2724), 0xf0800000 },
 824         { _MMIO(0x2720), 0x00000000 },
 825         { _MMIO(0x2714), 0xf0800000 },
 826         { _MMIO(0x2710), 0x00000000 },
 827         { _MMIO(0x274c), 0x86543210 },
 828         { _MMIO(0x2748), 0x86543210 },
 829         { _MMIO(0x2744), 0x00006667 },
 830         { _MMIO(0x2740), 0x00000000 },
 831         { _MMIO(0x275c), 0x86543210 },
 832         { _MMIO(0x2758), 0x86543210 },
 833         { _MMIO(0x2754), 0x00006465 },
 834         { _MMIO(0x2750), 0x00000000 },
 835         { _MMIO(0x2770), 0x0007f81a },
 836         { _MMIO(0x2774), 0x0000fe00 },
 837         { _MMIO(0x2778), 0x0007f82a },
 838         { _MMIO(0x277c), 0x0000fe00 },
 839         { _MMIO(0x2780), 0x0007f822 },
 840         { _MMIO(0x2784), 0x0000fe00 },
 841         { _MMIO(0x2788), 0x0007f8ba },
 842         { _MMIO(0x278c), 0x0000fe00 },
 843         { _MMIO(0x2790), 0x0007f87a },
 844         { _MMIO(0x2794), 0x0000fe00 },
 845         { _MMIO(0x2798), 0x0007f8ea },
 846         { _MMIO(0x279c), 0x0000fe00 },
 847         { _MMIO(0x27a0), 0x0007f8e2 },
 848         { _MMIO(0x27a4), 0x0000fe00 },
 849         { _MMIO(0x27a8), 0x0007f8f2 },
 850         { _MMIO(0x27ac), 0x0000fe00 },
 851 };
 852
 853 static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
 854         { _MMIO(0xe458), 0x00005004 },
 855         { _MMIO(0xe558), 0x00015014 },
 856         { _MMIO(0xe658), 0x00025024 },
 857         { _MMIO(0xe758), 0x00035034 },
 858         { _MMIO(0xe45c), 0x00045044 },
 859         { _MMIO(0xe55c), 0x00055054 },
 860         { _MMIO(0xe65c), 0x00065064 },
 861 };
 862
 863 static const struct i915_oa_reg mux_config_memory_writes[] = {
 864         { _MMIO(0x9888), 0x198b0343 },
 865         { _MMIO(0x9888), 0x13845400 },
 866         { _MMIO(0x9888), 0x3580001a },
 867         { _MMIO(0x9888), 0x3d800805 },
 868         { _MMIO(0x9888), 0x038b6300 },
 869         { _MMIO(0x9888), 0x058b6b62 },
 870         { _MMIO(0x9888), 0x078b006a },
 871         { _MMIO(0x9888), 0x118b0000 },
 872         { _MMIO(0x9888), 0x238b0000 },
 873         { _MMIO(0x9888), 0x258b0000 },
 874         { _MMIO(0x9888), 0x1f85a080 },
 875         { _MMIO(0x9888), 0x2185aaaa },
 876         { _MMIO(0x9888), 0x23850002 },
 877         { _MMIO(0x9888), 0x07834000 },
 878         { _MMIO(0x9888), 0x09834000 },
 879         { _MMIO(0x9888), 0x0b834000 },
 880         { _MMIO(0x9888), 0x0d834000 },
 881         { _MMIO(0x9888), 0x01840010 },
 882         { _MMIO(0x9888), 0x07844880 },
 883         { _MMIO(0x9888), 0x09840992 },
 884         { _MMIO(0x9888), 0x0b840a94 },
 885         { _MMIO(0x9888), 0x0d840b96 },
 886         { _MMIO(0x9888), 0x11840000 },
 887         { _MMIO(0x9888), 0x03848000 },
 888         { _MMIO(0x9888), 0x0584c000 },
 889         { _MMIO(0x9888), 0x2d800147 },
 890         { _MMIO(0x9888), 0x2f8000e5 },
 891         { _MMIO(0x9888), 0x138080e3 },
 892         { _MMIO(0x9888), 0x1580c0e1 },
 893         { _MMIO(0x9888), 0x21800000 },
 894         { _MMIO(0x9888), 0x11804000 },
 895         { _MMIO(0x9888), 0x1780c000 },
 896         { _MMIO(0x9888), 0x1980c000 },
 897         { _MMIO(0x9888), 0x1b80c000 },
 898         { _MMIO(0x9888), 0x1d80c000 },
 899         { _MMIO(0x9888), 0x1f800000 },
 900         { _MMIO(0xd24), 0x00000000 },
 901         { _MMIO(0x9888), 0x4d800000 },
 902         { _MMIO(0x9888), 0x4f800000 },
 903         { _MMIO(0x9888), 0x43800842 },
 904         { _MMIO(0x9888), 0x51800000 },
 905         { _MMIO(0x9888), 0x45800842 },
 906         { _MMIO(0x9888), 0x53800000 },
 907         { _MMIO(0x9888), 0x47801082 },
 908         { _MMIO(0x9888), 0x31800000 },
 909         { _MMIO(0x9888), 0x3f800084 },
 910         { _MMIO(0x9888), 0x41800000 },
 911 };
 912
 913 static int
 914 get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
 915                              const struct i915_oa_reg **regs,
 916                              int *lens)
 917 {
 918         int n = 0;
 919
 920         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
 921         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
 922
 923         regs[n] = mux_config_memory_writes;
 924         lens[n] = ARRAY_SIZE(mux_config_memory_writes);
 925         n++;
 926
 927         return n;
 928 }
 929
 930 static const struct i915_oa_reg b_counter_config_compute_extended[] = {
 931         { _MMIO(0x2724), 0xf0800000 },
 932         { _MMIO(0x2720), 0x00000000 },
 933         { _MMIO(0x2714), 0xf0800000 },
 934         { _MMIO(0x2710), 0x00000000 },
 935         { _MMIO(0x2740), 0x00000000 },
 936         { _MMIO(0x2770), 0x0007fc2a },
 937         { _MMIO(0x2774), 0x0000bf00 },
 938         { _MMIO(0x2778), 0x0007fc6a },
 939         { _MMIO(0x277c), 0x0000bf00 },
 940         { _MMIO(0x2780), 0x0007fc92 },
 941         { _MMIO(0x2784), 0x0000bf00 },
 942         { _MMIO(0x2788), 0x0007fca2 },
 943         { _MMIO(0x278c), 0x0000bf00 },
 944         { _MMIO(0x2790), 0x0007fc32 },
 945         { _MMIO(0x2794), 0x0000bf00 },
 946         { _MMIO(0x2798), 0x0007fc9a },
 947         { _MMIO(0x279c), 0x0000bf00 },
 948         { _MMIO(0x27a0), 0x0007fe6a },
 949         { _MMIO(0x27a4), 0x0000bf00 },
 950         { _MMIO(0x27a8), 0x0007fe7a },
 951         { _MMIO(0x27ac), 0x0000bf00 },
 952 };
 953
 954 static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
 955         { _MMIO(0xe458), 0x00005004 },
 956         { _MMIO(0xe558), 0x00000003 },
 957         { _MMIO(0xe658), 0x00002001 },
 958         { _MMIO(0xe758), 0x00778008 },
 959         { _MMIO(0xe45c), 0x00088078 },
 960         { _MMIO(0xe55c), 0x00808708 },
 961         { _MMIO(0xe65c), 0x00a08908 },
 962 };
 963
 964 static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = {
 965         { _MMIO(0x9888), 0x143d0160 },
 966         { _MMIO(0x9888), 0x163d2800 },
 967         { _MMIO(0x9888), 0x183d0120 },
 968         { _MMIO(0x9888), 0x105800e0 },
 969         { _MMIO(0x9888), 0x005cc000 },
 970         { _MMIO(0x9888), 0x065c8000 },
 971         { _MMIO(0x9888), 0x085cc000 },
 972         { _MMIO(0x9888), 0x0a5cc000 },
 973         { _MMIO(0x9888), 0x0c5cc000 },
 974         { _MMIO(0x9888), 0x0e5cc000 },
 975         { _MMIO(0x9888), 0x025cc000 },
 976         { _MMIO(0x9888), 0x045cc000 },
 977         { _MMIO(0x9888), 0x003d0011 },
 978         { _MMIO(0x9888), 0x063d0900 },
 979         { _MMIO(0x9888), 0x083d0a13 },
 980         { _MMIO(0x9888), 0x0a3d0b15 },
 981         { _MMIO(0x9888), 0x0c3d2317 },
 982         { _MMIO(0x9888), 0x043d21b7 },
 983         { _MMIO(0x9888), 0x103d0000 },
 984         { _MMIO(0x9888), 0x0e3d0000 },
 985         { _MMIO(0x9888), 0x1a3d0000 },
 986         { _MMIO(0x9888), 0x0e5825c1 },
 987         { _MMIO(0x9888), 0x00586100 },
 988         { _MMIO(0x9888), 0x0258204c },
 989         { _MMIO(0x9888), 0x06588000 },
 990         { _MMIO(0x9888), 0x0858c000 },
 991         { _MMIO(0x9888), 0x0a58c000 },
 992         { _MMIO(0x9888), 0x0c58c000 },
 993         { _MMIO(0x9888), 0x0458c000 },
 994         { _MMIO(0x9888), 0x005b4000 },
 995         { _MMIO(0x9888), 0x0e5b4000 },
 996         { _MMIO(0x9888), 0x185b5400 },
 997         { _MMIO(0x9888), 0x1a5b0155 },
 998         { _MMIO(0x9888), 0x025b4000 },
 999         { _MMIO(0x9888), 0x045b4000 },
1000         { _MMIO(0x9888), 0x065b4000 },
1001         { _MMIO(0x9888), 0x085b4000 },
1002         { _MMIO(0x9888), 0x0a5b4000 },
1003         { _MMIO(0x9888), 0x0c1fa800 },
1004         { _MMIO(0x9888), 0x0e1faa2a },
1005         { _MMIO(0x9888), 0x101f02aa },
1006         { _MMIO(0x9888), 0x00384000 },
1007         { _MMIO(0x9888), 0x0e384000 },
1008         { _MMIO(0x9888), 0x16384000 },
1009         { _MMIO(0x9888), 0x18381555 },
1010         { _MMIO(0x9888), 0x02384000 },
1011         { _MMIO(0x9888), 0x04384000 },
1012         { _MMIO(0x9888), 0x06384000 },
1013         { _MMIO(0x9888), 0x08384000 },
1014         { _MMIO(0x9888), 0x0a384000 },
1015         { _MMIO(0x9888), 0x0039a000 },
1016         { _MMIO(0x9888), 0x06398000 },
1017         { _MMIO(0x9888), 0x0839a000 },
1018         { _MMIO(0x9888), 0x0a39a000 },
1019         { _MMIO(0x9888), 0x0c39a000 },
1020         { _MMIO(0x9888), 0x0e39a000 },
1021         { _MMIO(0x9888), 0x0239a000 },
1022         { _MMIO(0x9888), 0x0439a000 },
1023         { _MMIO(0x9888), 0x018a8000 },
1024         { _MMIO(0x9888), 0x0f8a8000 },
1025         { _MMIO(0x9888), 0x198a8000 },
1026         { _MMIO(0x9888), 0x1b8aaaa0 },
1027         { _MMIO(0x9888), 0x1d8a0002 },
1028         { _MMIO(0x9888), 0x038a8000 },
1029         { _MMIO(0x9888), 0x058a8000 },
1030         { _MMIO(0x9888), 0x078a8000 },
1031         { _MMIO(0x9888), 0x098a8000 },
1032         { _MMIO(0x9888), 0x0b8a8000 },
1033         { _MMIO(0x9888), 0x238b2aa0 },
1034         { _MMIO(0x9888), 0x258b5551 },
1035         { _MMIO(0x9888), 0x278b0015 },
1036         { _MMIO(0x9888), 0x1f85aa80 },
1037         { _MMIO(0x9888), 0x2185aaa2 },
1038         { _MMIO(0x9888), 0x2385002a },
1039         { _MMIO(0x9888), 0x01834000 },
1040         { _MMIO(0x9888), 0x0f834000 },
1041         { _MMIO(0x9888), 0x19835400 },
1042         { _MMIO(0x9888), 0x1b830155 },
1043         { _MMIO(0x9888), 0x03834000 },
1044         { _MMIO(0x9888), 0x05834000 },
1045         { _MMIO(0x9888), 0x07834000 },
1046         { _MMIO(0x9888), 0x09834000 },
1047         { _MMIO(0x9888), 0x0b834000 },
1048         { _MMIO(0x9888), 0x0184c000 },
1049         { _MMIO(0x9888), 0x07848000 },
1050         { _MMIO(0x9888), 0x0984c000 },
1051         { _MMIO(0x9888), 0x0b84c000 },
1052         { _MMIO(0x9888), 0x0d84c000 },
1053         { _MMIO(0x9888), 0x0f84c000 },
1054         { _MMIO(0x9888), 0x0384c000 },
1055         { _MMIO(0x9888), 0x0584c000 },
1056         { _MMIO(0x9888), 0x1180c000 },
1057         { _MMIO(0x9888), 0x17808000 },
1058         { _MMIO(0x9888), 0x1980c000 },
1059         { _MMIO(0x9888), 0x1b80c000 },
1060         { _MMIO(0x9888), 0x1d80c000 },
1061         { _MMIO(0x9888), 0x1f80c000 },
1062         { _MMIO(0x9888), 0x1380c000 },
1063         { _MMIO(0x9888), 0x1580c000 },
1064         { _MMIO(0xd24), 0x00000000 },
1065         { _MMIO(0x9888), 0x4d800000 },
1066         { _MMIO(0x9888), 0x3d800000 },
1067         { _MMIO(0x9888), 0x4f800000 },
1068         { _MMIO(0x9888), 0x43800000 },
1069         { _MMIO(0x9888), 0x51800000 },
1070         { _MMIO(0x9888), 0x45800000 },
1071         { _MMIO(0x9888), 0x53800000 },
1072         { _MMIO(0x9888), 0x47800420 },
1073         { _MMIO(0x9888), 0x21800000 },
1074         { _MMIO(0x9888), 0x31800000 },
1075         { _MMIO(0x9888), 0x3f800421 },
1076         { _MMIO(0x9888), 0x41800000 },
1077 };
1078
1079 static const struct i915_oa_reg mux_config_compute_extended_2_subslices_0x02[] = {
1080         { _MMIO(0x9888), 0x105c00e0 },
1081         { _MMIO(0x9888), 0x145b0160 },
1082         { _MMIO(0x9888), 0x165b2800 },
1083         { _MMIO(0x9888), 0x185b0120 },
1084         { _MMIO(0x9888), 0x0e5c25c1 },
1085         { _MMIO(0x9888), 0x005c6100 },
1086         { _MMIO(0x9888), 0x025c204c },
1087         { _MMIO(0x9888), 0x065c8000 },
1088         { _MMIO(0x9888), 0x085cc000 },
1089         { _MMIO(0x9888), 0x0a5cc000 },
1090         { _MMIO(0x9888), 0x0c5cc000 },
1091         { _MMIO(0x9888), 0x045cc000 },
1092         { _MMIO(0x9888), 0x005b0011 },
1093         { _MMIO(0x9888), 0x065b0900 },
1094         { _MMIO(0x9888), 0x085b0a13 },
1095         { _MMIO(0x9888), 0x0a5b0b15 },
1096         { _MMIO(0x9888), 0x0c5b2317 },
1097         { _MMIO(0x9888), 0x045b21b7 },
1098         { _MMIO(0x9888), 0x105b0000 },
1099         { _MMIO(0x9888), 0x0e5b0000 },
1100         { _MMIO(0x9888), 0x1a5b0000 },
1101         { _MMIO(0x9888), 0x0c1fa800 },
1102         { _MMIO(0x9888), 0x0e1faa2a },
1103         { _MMIO(0x9888), 0x101f02aa },
1104         { _MMIO(0x9888), 0x00384000 },
1105         { _MMIO(0x9888), 0x0e384000 },
1106         { _MMIO(0x9888), 0x16384000 },
1107         { _MMIO(0x9888), 0x18381555 },
1108         { _MMIO(0x9888), 0x02384000 },
1109         { _MMIO(0x9888), 0x04384000 },
1110         { _MMIO(0x9888), 0x06384000 },
1111         { _MMIO(0x9888), 0x08384000 },
1112         { _MMIO(0x9888), 0x0a384000 },
1113         { _MMIO(0x9888), 0x0039a000 },
1114         { _MMIO(0x9888), 0x06398000 },
1115         { _MMIO(0x9888), 0x0839a000 },
1116         { _MMIO(0x9888), 0x0a39a000 },
1117         { _MMIO(0x9888), 0x0c39a000 },
1118         { _MMIO(0x9888), 0x0e39a000 },
1119         { _MMIO(0x9888), 0x0239a000 },
1120         { _MMIO(0x9888), 0x0439a000 },
1121         { _MMIO(0x9888), 0x018a8000 },
1122         { _MMIO(0x9888), 0x0f8a8000 },
1123         { _MMIO(0x9888), 0x198a8000 },
1124         { _MMIO(0x9888), 0x1b8aaaa0 },
1125         { _MMIO(0x9888), 0x1d8a0002 },
1126         { _MMIO(0x9888), 0x038a8000 },
1127         { _MMIO(0x9888), 0x058a8000 },
1128         { _MMIO(0x9888), 0x078a8000 },
1129         { _MMIO(0x9888), 0x098a8000 },
1130         { _MMIO(0x9888), 0x0b8a8000 },
1131         { _MMIO(0x9888), 0x238b2aa0 },
1132         { _MMIO(0x9888), 0x258b5551 },
1133         { _MMIO(0x9888), 0x278b0015 },
1134         { _MMIO(0x9888), 0x1f85aa80 },
1135         { _MMIO(0x9888), 0x2185aaa2 },
1136         { _MMIO(0x9888), 0x2385002a },
1137         { _MMIO(0x9888), 0x01834000 },
1138         { _MMIO(0x9888), 0x0f834000 },
1139         { _MMIO(0x9888), 0x19835400 },
1140         { _MMIO(0x9888), 0x1b830155 },
1141         { _MMIO(0x9888), 0x03834000 },
1142         { _MMIO(0x9888), 0x05834000 },
1143         { _MMIO(0x9888), 0x07834000 },
1144         { _MMIO(0x9888), 0x09834000 },
1145         { _MMIO(0x9888), 0x0b834000 },
1146         { _MMIO(0x9888), 0x0184c000 },
1147         { _MMIO(0x9888), 0x07848000 },
1148         { _MMIO(0x9888), 0x0984c000 },
1149         { _MMIO(0x9888), 0x0b84c000 },
1150         { _MMIO(0x9888), 0x0d84c000 },
1151         { _MMIO(0x9888), 0x0f84c000 },
1152         { _MMIO(0x9888), 0x0384c000 },
1153         { _MMIO(0x9888), 0x0584c000 },
1154         { _MMIO(0x9888), 0x1180c000 },
1155         { _MMIO(0x9888), 0x17808000 },
1156         { _MMIO(0x9888), 0x1980c000 },
1157         { _MMIO(0x9888), 0x1b80c000 },
1158         { _MMIO(0x9888), 0x1d80c000 },
1159         { _MMIO(0x9888), 0x1f80c000 },
1160         { _MMIO(0x9888), 0x1380c000 },
1161         { _MMIO(0x9888), 0x1580c000 },
1162         { _MMIO(0xd24), 0x00000000 },
1163         { _MMIO(0x9888), 0x4d800000 },
1164         { _MMIO(0x9888), 0x3d800000 },
1165         { _MMIO(0x9888), 0x4f800000 },
1166         { _MMIO(0x9888), 0x43800000 },
1167         { _MMIO(0x9888), 0x51800000 },
1168         { _MMIO(0x9888), 0x45800000 },
1169         { _MMIO(0x9888), 0x53800000 },
1170         { _MMIO(0x9888), 0x47800420 },
1171         { _MMIO(0x9888), 0x21800000 },
1172         { _MMIO(0x9888), 0x31800000 },
1173         { _MMIO(0x9888), 0x3f800421 },
1174         { _MMIO(0x9888), 0x41800000 },
1175 };
1176
1177 static const struct i915_oa_reg mux_config_compute_extended_4_subslices_0x04[] = {
1178         { _MMIO(0x9888), 0x103800e0 },
1179         { _MMIO(0x9888), 0x143a0160 },
1180         { _MMIO(0x9888), 0x163a2800 },
1181         { _MMIO(0x9888), 0x183a0120 },
1182         { _MMIO(0x9888), 0x0c1fa800 },
1183         { _MMIO(0x9888), 0x0e1faa2a },
1184         { _MMIO(0x9888), 0x101f02aa },
1185         { _MMIO(0x9888), 0x0e38a5c1 },
1186         { _MMIO(0x9888), 0x0038a100 },
1187         { _MMIO(0x9888), 0x0238204c },
1188         { _MMIO(0x9888), 0x16388000 },
1189         { _MMIO(0x9888), 0x183802aa },
1190         { _MMIO(0x9888), 0x04380000 },
1191         { _MMIO(0x9888), 0x06380000 },
1192         { _MMIO(0x9888), 0x08388000 },
1193         { _MMIO(0x9888), 0x0a388000 },
1194         { _MMIO(0x9888), 0x0039a000 },
1195         { _MMIO(0x9888), 0x06398000 },
1196         { _MMIO(0x9888), 0x0839a000 },
1197         { _MMIO(0x9888), 0x0a39a000 },
1198         { _MMIO(0x9888), 0x0c39a000 },
1199         { _MMIO(0x9888), 0x0e39a000 },
1200         { _MMIO(0x9888), 0x0239a000 },
1201         { _MMIO(0x9888), 0x0439a000 },
1202         { _MMIO(0x9888), 0x003a0011 },
1203         { _MMIO(0x9888), 0x063a0900 },
1204         { _MMIO(0x9888), 0x083a0a13 },
1205         { _MMIO(0x9888), 0x0a3a0b15 },
1206         { _MMIO(0x9888), 0x0c3a2317 },
1207         { _MMIO(0x9888), 0x043a21b7 },
1208         { _MMIO(0x9888), 0x103a0000 },
1209         { _MMIO(0x9888), 0x0e3a0000 },
1210         { _MMIO(0x9888), 0x1a3a0000 },
1211         { _MMIO(0x9888), 0x018a8000 },
1212         { _MMIO(0x9888), 0x0f8a8000 },
1213         { _MMIO(0x9888), 0x198a8000 },
1214         { _MMIO(0x9888), 0x1b8aaaa0 },
1215         { _MMIO(0x9888), 0x1d8a0002 },
1216         { _MMIO(0x9888), 0x038a8000 },
1217         { _MMIO(0x9888), 0x058a8000 },
1218         { _MMIO(0x9888), 0x078a8000 },
1219         { _MMIO(0x9888), 0x098a8000 },
1220         { _MMIO(0x9888), 0x0b8a8000 },
1221         { _MMIO(0x9888), 0x238b2aa0 },
1222         { _MMIO(0x9888), 0x258b5551 },
1223         { _MMIO(0x9888), 0x278b0015 },
1224         { _MMIO(0x9888), 0x1f85aa80 },
1225         { _MMIO(0x9888), 0x2185aaa2 },
1226         { _MMIO(0x9888), 0x2385002a },
1227         { _MMIO(0x9888), 0x01834000 },
1228         { _MMIO(0x9888), 0x0f834000 },
1229         { _MMIO(0x9888), 0x19835400 },
1230         { _MMIO(0x9888), 0x1b830155 },
1231         { _MMIO(0x9888), 0x03834000 },
1232         { _MMIO(0x9888), 0x05834000 },
1233         { _MMIO(0x9888), 0x07834000 },
1234         { _MMIO(0x9888), 0x09834000 },
1235         { _MMIO(0x9888), 0x0b834000 },
1236         { _MMIO(0x9888), 0x0184c000 },
1237         { _MMIO(0x9888), 0x07848000 },
1238         { _MMIO(0x9888), 0x0984c000 },
1239         { _MMIO(0x9888), 0x0b84c000 },
1240         { _MMIO(0x9888), 0x0d84c000 },
1241         { _MMIO(0x9888), 0x0f84c000 },
1242         { _MMIO(0x9888), 0x0384c000 },
1243         { _MMIO(0x9888), 0x0584c000 },
1244         { _MMIO(0x9888), 0x1180c000 },
1245         { _MMIO(0x9888), 0x17808000 },
1246         { _MMIO(0x9888), 0x1980c000 },
1247         { _MMIO(0x9888), 0x1b80c000 },
1248         { _MMIO(0x9888), 0x1d80c000 },
1249         { _MMIO(0x9888), 0x1f80c000 },
1250         { _MMIO(0x9888), 0x1380c000 },
1251         { _MMIO(0x9888), 0x1580c000 },
1252         { _MMIO(0xd24), 0x00000000 },
1253         { _MMIO(0x9888), 0x4d800000 },
1254         { _MMIO(0x9888), 0x3d800000 },
1255         { _MMIO(0x9888), 0x4f800000 },
1256         { _MMIO(0x9888), 0x43800000 },
1257         { _MMIO(0x9888), 0x51800000 },
1258         { _MMIO(0x9888), 0x45800000 },
1259         { _MMIO(0x9888), 0x53800000 },
1260         { _MMIO(0x9888), 0x47800420 },
1261         { _MMIO(0x9888), 0x21800000 },
1262         { _MMIO(0x9888), 0x31800000 },
1263         { _MMIO(0x9888), 0x3f800421 },
1264         { _MMIO(0x9888), 0x41800000 },
1265 };
1266
1267 static const struct i915_oa_reg mux_config_compute_extended_1_subslices_0x08[] = {
1268         { _MMIO(0x9888), 0x14bd0160 },
1269         { _MMIO(0x9888), 0x16bd2800 },
1270         { _MMIO(0x9888), 0x18bd0120 },
1271         { _MMIO(0x9888), 0x10d800e0 },
1272         { _MMIO(0x9888), 0x00dcc000 },
1273         { _MMIO(0x9888), 0x06dc8000 },
1274         { _MMIO(0x9888), 0x08dcc000 },
1275         { _MMIO(0x9888), 0x0adcc000 },
1276         { _MMIO(0x9888), 0x0cdcc000 },
1277         { _MMIO(0x9888), 0x0edcc000 },
1278         { _MMIO(0x9888), 0x02dcc000 },
1279         { _MMIO(0x9888), 0x04dcc000 },
1280         { _MMIO(0x9888), 0x00bd0011 },
1281         { _MMIO(0x9888), 0x06bd0900 },
1282         { _MMIO(0x9888), 0x08bd0a13 },
1283         { _MMIO(0x9888), 0x0abd0b15 },
1284         { _MMIO(0x9888), 0x0cbd2317 },
1285         { _MMIO(0x9888), 0x04bd21b7 },
1286         { _MMIO(0x9888), 0x10bd0000 },
1287         { _MMIO(0x9888), 0x0ebd0000 },
1288         { _MMIO(0x9888), 0x1abd0000 },
1289         { _MMIO(0x9888), 0x0ed825c1 },
1290         { _MMIO(0x9888), 0x00d86100 },
1291         { _MMIO(0x9888), 0x02d8204c },
1292         { _MMIO(0x9888), 0x06d88000 },
1293         { _MMIO(0x9888), 0x08d8c000 },
1294         { _MMIO(0x9888), 0x0ad8c000 },
1295         { _MMIO(0x9888), 0x0cd8c000 },
1296         { _MMIO(0x9888), 0x04d8c000 },
1297         { _MMIO(0x9888), 0x00db4000 },
1298         { _MMIO(0x9888), 0x0edb4000 },
1299         { _MMIO(0x9888), 0x18db5400 },
1300         { _MMIO(0x9888), 0x1adb0155 },
1301         { _MMIO(0x9888), 0x02db4000 },
1302         { _MMIO(0x9888), 0x04db4000 },
1303         { _MMIO(0x9888), 0x06db4000 },
1304         { _MMIO(0x9888), 0x08db4000 },
1305         { _MMIO(0x9888), 0x0adb4000 },
1306         { _MMIO(0x9888), 0x0c9fa800 },
1307         { _MMIO(0x9888), 0x0e9faa2a },
1308         { _MMIO(0x9888), 0x109f02aa },
1309         { _MMIO(0x9888), 0x00b84000 },
1310         { _MMIO(0x9888), 0x0eb84000 },
1311         { _MMIO(0x9888), 0x16b84000 },
1312         { _MMIO(0x9888), 0x18b81555 },
1313         { _MMIO(0x9888), 0x02b84000 },
1314         { _MMIO(0x9888), 0x04b84000 },
1315         { _MMIO(0x9888), 0x06b84000 },
1316         { _MMIO(0x9888), 0x08b84000 },
1317         { _MMIO(0x9888), 0x0ab84000 },
1318         { _MMIO(0x9888), 0x00b9a000 },
1319         { _MMIO(0x9888), 0x06b98000 },
1320         { _MMIO(0x9888), 0x08b9a000 },
1321         { _MMIO(0x9888), 0x0ab9a000 },
1322         { _MMIO(0x9888), 0x0cb9a000 },
1323         { _MMIO(0x9888), 0x0eb9a000 },
1324         { _MMIO(0x9888), 0x02b9a000 },
1325         { _MMIO(0x9888), 0x04b9a000 },
1326         { _MMIO(0x9888), 0x01888000 },
1327         { _MMIO(0x9888), 0x0d88f800 },
1328         { _MMIO(0x9888), 0x0f88000f },
1329         { _MMIO(0x9888), 0x03888000 },
1330         { _MMIO(0x9888), 0x05888000 },
1331         { _MMIO(0x9888), 0x07888000 },
1332         { _MMIO(0x9888), 0x09888000 },
1333         { _MMIO(0x9888), 0x0b888000 },
1334         { _MMIO(0x9888), 0x238b5540 },
1335         { _MMIO(0x9888), 0x258baaa2 },
1336         { _MMIO(0x9888), 0x278b002a },
1337         { _MMIO(0x9888), 0x018c4000 },
1338         { _MMIO(0x9888), 0x0f8c4000 },
1339         { _MMIO(0x9888), 0x178c2000 },
1340         { _MMIO(0x9888), 0x198c5500 },
1341         { _MMIO(0x9888), 0x1b8c0015 },
1342         { _MMIO(0x9888), 0x038c4000 },
1343         { _MMIO(0x9888), 0x058c4000 },
1344         { _MMIO(0x9888), 0x078c4000 },
1345         { _MMIO(0x9888), 0x098c4000 },
1346         { _MMIO(0x9888), 0x0b8c4000 },
1347         { _MMIO(0x9888), 0x018da000 },
1348         { _MMIO(0x9888), 0x078d8000 },
1349         { _MMIO(0x9888), 0x098da000 },
1350         { _MMIO(0x9888), 0x0b8da000 },
1351         { _MMIO(0x9888), 0x0d8da000 },
1352         { _MMIO(0x9888), 0x0f8da000 },
1353         { _MMIO(0x9888), 0x038da000 },
1354         { _MMIO(0x9888), 0x058da000 },
1355         { _MMIO(0x9888), 0x1f85aa80 },
1356         { _MMIO(0x9888), 0x2185aaa2 },
1357         { _MMIO(0x9888), 0x2385002a },
1358         { _MMIO(0x9888), 0x01834000 },
1359         { _MMIO(0x9888), 0x0f834000 },
1360         { _MMIO(0x9888), 0x19835400 },
1361         { _MMIO(0x9888), 0x1b830155 },
1362         { _MMIO(0x9888), 0x03834000 },
1363         { _MMIO(0x9888), 0x05834000 },
1364         { _MMIO(0x9888), 0x07834000 },
1365         { _MMIO(0x9888), 0x09834000 },
1366         { _MMIO(0x9888), 0x0b834000 },
1367         { _MMIO(0x9888), 0x0184c000 },
1368         { _MMIO(0x9888), 0x07848000 },
1369         { _MMIO(0x9888), 0x0984c000 },
1370         { _MMIO(0x9888), 0x0b84c000 },
1371         { _MMIO(0x9888), 0x0d84c000 },
1372         { _MMIO(0x9888), 0x0f84c000 },
1373         { _MMIO(0x9888), 0x0384c000 },
1374         { _MMIO(0x9888), 0x0584c000 },
1375         { _MMIO(0x9888), 0x1180c000 },
1376         { _MMIO(0x9888), 0x17808000 },
1377         { _MMIO(0x9888), 0x1980c000 },
1378         { _MMIO(0x9888), 0x1b80c000 },
1379         { _MMIO(0x9888), 0x1d80c000 },
1380         { _MMIO(0x9888), 0x1f80c000 },
1381         { _MMIO(0x9888), 0x1380c000 },
1382         { _MMIO(0x9888), 0x1580c000 },
1383         { _MMIO(0xd24), 0x00000000 },
1384         { _MMIO(0x9888), 0x4d800000 },
1385         { _MMIO(0x9888), 0x3d800000 },
1386         { _MMIO(0x9888), 0x4f800000 },
1387         { _MMIO(0x9888), 0x43800000 },
1388         { _MMIO(0x9888), 0x51800000 },
1389         { _MMIO(0x9888), 0x45800000 },
1390         { _MMIO(0x9888), 0x53800000 },
1391         { _MMIO(0x9888), 0x47800420 },
1392         { _MMIO(0x9888), 0x21800000 },
1393         { _MMIO(0x9888), 0x31800000 },
1394         { _MMIO(0x9888), 0x3f800421 },
1395         { _MMIO(0x9888), 0x41800000 },
1396 };
1397
1398 static const struct i915_oa_reg mux_config_compute_extended_3_subslices_0x10[] = {
1399         { _MMIO(0x9888), 0x10dc00e0 },
1400         { _MMIO(0x9888), 0x14db0160 },
1401         { _MMIO(0x9888), 0x16db2800 },
1402         { _MMIO(0x9888), 0x18db0120 },
1403         { _MMIO(0x9888), 0x0edc25c1 },
1404         { _MMIO(0x9888), 0x00dc6100 },
1405         { _MMIO(0x9888), 0x02dc204c },
1406         { _MMIO(0x9888), 0x06dc8000 },
1407         { _MMIO(0x9888), 0x08dcc000 },
1408         { _MMIO(0x9888), 0x0adcc000 },
1409         { _MMIO(0x9888), 0x0cdcc000 },
1410         { _MMIO(0x9888), 0x04dcc000 },
1411         { _MMIO(0x9888), 0x00db0011 },
1412         { _MMIO(0x9888), 0x06db0900 },
1413         { _MMIO(0x9888), 0x08db0a13 },
1414         { _MMIO(0x9888), 0x0adb0b15 },
1415         { _MMIO(0x9888), 0x0cdb2317 },
1416         { _MMIO(0x9888), 0x04db21b7 },
1417         { _MMIO(0x9888), 0x10db0000 },
1418         { _MMIO(0x9888), 0x0edb0000 },
1419         { _MMIO(0x9888), 0x1adb0000 },
1420         { _MMIO(0x9888), 0x0c9fa800 },
1421         { _MMIO(0x9888), 0x0e9faa2a },
1422         { _MMIO(0x9888), 0x109f02aa },
1423         { _MMIO(0x9888), 0x00b84000 },
1424         { _MMIO(0x9888), 0x0eb84000 },
1425         { _MMIO(0x9888), 0x16b84000 },
1426         { _MMIO(0x9888), 0x18b81555 },
1427         { _MMIO(0x9888), 0x02b84000 },
1428         { _MMIO(0x9888), 0x04b84000 },
1429         { _MMIO(0x9888), 0x06b84000 },
1430         { _MMIO(0x9888), 0x08b84000 },
1431         { _MMIO(0x9888), 0x0ab84000 },
1432         { _MMIO(0x9888), 0x00b9a000 },
1433         { _MMIO(0x9888), 0x06b98000 },
1434         { _MMIO(0x9888), 0x08b9a000 },
1435         { _MMIO(0x9888), 0x0ab9a000 },
1436         { _MMIO(0x9888), 0x0cb9a000 },
1437         { _MMIO(0x9888), 0x0eb9a000 },
1438         { _MMIO(0x9888), 0x02b9a000 },
1439         { _MMIO(0x9888), 0x04b9a000 },
1440         { _MMIO(0x9888), 0x01888000 },
1441         { _MMIO(0x9888), 0x0d88f800 },
1442         { _MMIO(0x9888), 0x0f88000f },
1443         { _MMIO(0x9888), 0x03888000 },
1444         { _MMIO(0x9888), 0x05888000 },
1445         { _MMIO(0x9888), 0x07888000 },
1446         { _MMIO(0x9888), 0x09888000 },
1447         { _MMIO(0x9888), 0x0b888000 },
1448         { _MMIO(0x9888), 0x238b5540 },
1449         { _MMIO(0x9888), 0x258baaa2 },
1450         { _MMIO(0x9888), 0x278b002a },
1451         { _MMIO(0x9888), 0x018c4000 },
1452         { _MMIO(0x9888), 0x0f8c4000 },
1453         { _MMIO(0x9888), 0x178c2000 },
1454         { _MMIO(0x9888), 0x198c5500 },
1455         { _MMIO(0x9888), 0x1b8c0015 },
1456         { _MMIO(0x9888), 0x038c4000 },
1457         { _MMIO(0x9888), 0x058c4000 },
1458         { _MMIO(0x9888), 0x078c4000 },
1459         { _MMIO(0x9888), 0x098c4000 },
1460         { _MMIO(0x9888), 0x0b8c4000 },
1461         { _MMIO(0x9888), 0x018da000 },
1462         { _MMIO(0x9888), 0x078d8000 },
1463         { _MMIO(0x9888), 0x098da000 },
1464         { _MMIO(0x9888), 0x0b8da000 },
1465         { _MMIO(0x9888), 0x0d8da000 },
1466         { _MMIO(0x9888), 0x0f8da000 },
1467         { _MMIO(0x9888), 0x038da000 },
1468         { _MMIO(0x9888), 0x058da000 },
1469         { _MMIO(0x9888), 0x1f85aa80 },
1470         { _MMIO(0x9888), 0x2185aaa2 },
1471         { _MMIO(0x9888), 0x2385002a },
1472         { _MMIO(0x9888), 0x01834000 },
1473         { _MMIO(0x9888), 0x0f834000 },
1474         { _MMIO(0x9888), 0x19835400 },
1475         { _MMIO(0x9888), 0x1b830155 },
1476         { _MMIO(0x9888), 0x03834000 },
1477         { _MMIO(0x9888), 0x05834000 },
1478         { _MMIO(0x9888), 0x07834000 },
1479         { _MMIO(0x9888), 0x09834000 },
1480         { _MMIO(0x9888), 0x0b834000 },
1481         { _MMIO(0x9888), 0x0184c000 },
1482         { _MMIO(0x9888), 0x07848000 },
1483         { _MMIO(0x9888), 0x0984c000 },
1484         { _MMIO(0x9888), 0x0b84c000 },
1485         { _MMIO(0x9888), 0x0d84c000 },
1486         { _MMIO(0x9888), 0x0f84c000 },
1487         { _MMIO(0x9888), 0x0384c000 },
1488         { _MMIO(0x9888), 0x0584c000 },
1489         { _MMIO(0x9888), 0x1180c000 },
1490         { _MMIO(0x9888), 0x17808000 },
1491         { _MMIO(0x9888), 0x1980c000 },
1492         { _MMIO(0x9888), 0x1b80c000 },
1493         { _MMIO(0x9888), 0x1d80c000 },
1494         { _MMIO(0x9888), 0x1f80c000 },
1495         { _MMIO(0x9888), 0x1380c000 },
1496         { _MMIO(0x9888), 0x1580c000 },
1497         { _MMIO(0xd24), 0x00000000 },
1498         { _MMIO(0x9888), 0x4d800000 },
1499         { _MMIO(0x9888), 0x3d800000 },
1500         { _MMIO(0x9888), 0x4f800000 },
1501         { _MMIO(0x9888), 0x43800000 },
1502         { _MMIO(0x9888), 0x51800000 },
1503         { _MMIO(0x9888), 0x45800000 },
1504         { _MMIO(0x9888), 0x53800000 },
1505         { _MMIO(0x9888), 0x47800420 },
1506         { _MMIO(0x9888), 0x21800000 },
1507         { _MMIO(0x9888), 0x31800000 },
1508         { _MMIO(0x9888), 0x3f800421 },
1509         { _MMIO(0x9888), 0x41800000 },
1510 };
1511
1512 static const struct i915_oa_reg mux_config_compute_extended_5_subslices_0x20[] = {
1513         { _MMIO(0x9888), 0x10b800e0 },
1514         { _MMIO(0x9888), 0x14ba0160 },
1515         { _MMIO(0x9888), 0x16ba2800 },
1516         { _MMIO(0x9888), 0x18ba0120 },
1517         { _MMIO(0x9888), 0x0c9fa800 },
1518         { _MMIO(0x9888), 0x0e9faa2a },
1519         { _MMIO(0x9888), 0x109f02aa },
1520         { _MMIO(0x9888), 0x0eb8a5c1 },
1521         { _MMIO(0x9888), 0x00b8a100 },
1522         { _MMIO(0x9888), 0x02b8204c },
1523         { _MMIO(0x9888), 0x16b88000 },
1524         { _MMIO(0x9888), 0x18b802aa },
1525         { _MMIO(0x9888), 0x04b80000 },
1526         { _MMIO(0x9888), 0x06b80000 },
1527         { _MMIO(0x9888), 0x08b88000 },
1528         { _MMIO(0x9888), 0x0ab88000 },
1529         { _MMIO(0x9888), 0x00b9a000 },
1530         { _MMIO(0x9888), 0x06b98000 },
1531         { _MMIO(0x9888), 0x08b9a000 },
1532         { _MMIO(0x9888), 0x0ab9a000 },
1533         { _MMIO(0x9888), 0x0cb9a000 },
1534         { _MMIO(0x9888), 0x0eb9a000 },
1535         { _MMIO(0x9888), 0x02b9a000 },
1536         { _MMIO(0x9888), 0x04b9a000 },
1537         { _MMIO(0x9888), 0x00ba0011 },
1538         { _MMIO(0x9888), 0x06ba0900 },
1539         { _MMIO(0x9888), 0x08ba0a13 },
1540         { _MMIO(0x9888), 0x0aba0b15 },
1541         { _MMIO(0x9888), 0x0cba2317 },
1542         { _MMIO(0x9888), 0x04ba21b7 },
1543         { _MMIO(0x9888), 0x10ba0000 },
1544         { _MMIO(0x9888), 0x0eba0000 },
1545         { _MMIO(0x9888), 0x1aba0000 },
1546         { _MMIO(0x9888), 0x01888000 },
1547         { _MMIO(0x9888), 0x0d88f800 },
1548         { _MMIO(0x9888), 0x0f88000f },
1549         { _MMIO(0x9888), 0x03888000 },
1550         { _MMIO(0x9888), 0x05888000 },
1551         { _MMIO(0x9888), 0x07888000 },
1552         { _MMIO(0x9888), 0x09888000 },
1553         { _MMIO(0x9888), 0x0b888000 },
1554         { _MMIO(0x9888), 0x238b5540 },
1555         { _MMIO(0x9888), 0x258baaa2 },
1556         { _MMIO(0x9888), 0x278b002a },
1557         { _MMIO(0x9888), 0x018c4000 },
1558         { _MMIO(0x9888), 0x0f8c4000 },
1559         { _MMIO(0x9888), 0x178c2000 },
1560         { _MMIO(0x9888), 0x198c5500 },
1561         { _MMIO(0x9888), 0x1b8c0015 },
1562         { _MMIO(0x9888), 0x038c4000 },
1563         { _MMIO(0x9888), 0x058c4000 },
1564         { _MMIO(0x9888), 0x078c4000 },
1565         { _MMIO(0x9888), 0x098c4000 },
1566         { _MMIO(0x9888), 0x0b8c4000 },
1567         { _MMIO(0x9888), 0x018da000 },
1568         { _MMIO(0x9888), 0x078d8000 },
1569         { _MMIO(0x9888), 0x098da000 },
1570         { _MMIO(0x9888), 0x0b8da000 },
1571         { _MMIO(0x9888), 0x0d8da000 },
1572         { _MMIO(0x9888), 0x0f8da000 },
1573         { _MMIO(0x9888), 0x038da000 },
1574         { _MMIO(0x9888), 0x058da000 },
1575         { _MMIO(0x9888), 0x1f85aa80 },
1576         { _MMIO(0x9888), 0x2185aaa2 },
1577         { _MMIO(0x9888), 0x2385002a },
1578         { _MMIO(0x9888), 0x01834000 },
1579         { _MMIO(0x9888), 0x0f834000 },
1580         { _MMIO(0x9888), 0x19835400 },
1581         { _MMIO(0x9888), 0x1b830155 },
1582         { _MMIO(0x9888), 0x03834000 },
1583         { _MMIO(0x9888), 0x05834000 },
1584         { _MMIO(0x9888), 0x07834000 },
1585         { _MMIO(0x9888), 0x09834000 },
1586         { _MMIO(0x9888), 0x0b834000 },
1587         { _MMIO(0x9888), 0x0184c000 },
1588         { _MMIO(0x9888), 0x07848000 },
1589         { _MMIO(0x9888), 0x0984c000 },
1590         { _MMIO(0x9888), 0x0b84c000 },
1591         { _MMIO(0x9888), 0x0d84c000 },
1592         { _MMIO(0x9888), 0x0f84c000 },
1593         { _MMIO(0x9888), 0x0384c000 },
1594         { _MMIO(0x9888), 0x0584c000 },
1595         { _MMIO(0x9888), 0x1180c000 },
1596         { _MMIO(0x9888), 0x17808000 },
1597         { _MMIO(0x9888), 0x1980c000 },
1598         { _MMIO(0x9888), 0x1b80c000 },
1599         { _MMIO(0x9888), 0x1d80c000 },
1600         { _MMIO(0x9888), 0x1f80c000 },
1601         { _MMIO(0x9888), 0x1380c000 },
1602         { _MMIO(0x9888), 0x1580c000 },
1603         { _MMIO(0xd24), 0x00000000 },
1604         { _MMIO(0x9888), 0x4d800000 },
1605         { _MMIO(0x9888), 0x3d800000 },
1606         { _MMIO(0x9888), 0x4f800000 },
1607         { _MMIO(0x9888), 0x43800000 },
1608         { _MMIO(0x9888), 0x51800000 },
1609         { _MMIO(0x9888), 0x45800000 },
1610         { _MMIO(0x9888), 0x53800000 },
1611         { _MMIO(0x9888), 0x47800420 },
1612         { _MMIO(0x9888), 0x21800000 },
1613         { _MMIO(0x9888), 0x31800000 },
1614         { _MMIO(0x9888), 0x3f800421 },
1615         { _MMIO(0x9888), 0x41800000 },
1616 };
1617
1618 static int
1619 get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
1620                                 const struct i915_oa_reg **regs,
1621                                 int *lens)
1622 {
1623         int n = 0;
1624
1625         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 6);
1626         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 6);
1627
1628         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
1629                 regs[n] = mux_config_compute_extended_0_subslices_0x01;
1630                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01);
1631                 n++;
1632         }
1633         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) {
1634                 regs[n] = mux_config_compute_extended_1_subslices_0x08;
1635                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_1_subslices_0x08);
1636                 n++;
1637         }
1638         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) {
1639                 regs[n] = mux_config_compute_extended_2_subslices_0x02;
1640                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_2_subslices_0x02);
1641                 n++;
1642         }
1643         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) {
1644                 regs[n] = mux_config_compute_extended_3_subslices_0x10;
1645                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_3_subslices_0x10);
1646                 n++;
1647         }
1648         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) {
1649                 regs[n] = mux_config_compute_extended_4_subslices_0x04;
1650                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_4_subslices_0x04);
1651                 n++;
1652         }
1653         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) {
1654                 regs[n] = mux_config_compute_extended_5_subslices_0x20;
1655                 lens[n] = ARRAY_SIZE(mux_config_compute_extended_5_subslices_0x20);
1656                 n++;
1657         }
1658
1659         return n;
1660 }
1661
1662 static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
1663         { _MMIO(0x2710), 0x00000000 },
1664         { _MMIO(0x2714), 0x30800000 },
1665         { _MMIO(0x2720), 0x00000000 },
1666         { _MMIO(0x2724), 0x30800000 },
1667         { _MMIO(0x2740), 0x00000000 },
1668         { _MMIO(0x2770), 0x0007fffa },
1669         { _MMIO(0x2774), 0x0000fefe },
1670         { _MMIO(0x2778), 0x0007fffa },
1671         { _MMIO(0x277c), 0x0000fefd },
1672         { _MMIO(0x2790), 0x0007fffa },
1673         { _MMIO(0x2794), 0x0000fbef },
1674         { _MMIO(0x2798), 0x0007fffa },
1675         { _MMIO(0x279c), 0x0000fbdf },
1676 };
1677
1678 static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
1679         { _MMIO(0xe458), 0x00005004 },
1680         { _MMIO(0xe558), 0x00000003 },
1681         { _MMIO(0xe658), 0x00002001 },
1682         { _MMIO(0xe758), 0x00101100 },
1683         { _MMIO(0xe45c), 0x00201200 },
1684         { _MMIO(0xe55c), 0x00301300 },
1685         { _MMIO(0xe65c), 0x00401400 },
1686 };
1687
1688 static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
1689         { _MMIO(0x9888), 0x143f00b3 },
1690         { _MMIO(0x9888), 0x14bf00b3 },
1691         { _MMIO(0x9888), 0x138303c0 },
1692         { _MMIO(0x9888), 0x3b800060 },
1693         { _MMIO(0x9888), 0x3d800805 },
1694         { _MMIO(0x9888), 0x003f0029 },
1695         { _MMIO(0x9888), 0x063f1400 },
1696         { _MMIO(0x9888), 0x083f1225 },
1697         { _MMIO(0x9888), 0x0e3f1327 },
1698         { _MMIO(0x9888), 0x103f0000 },
1699         { _MMIO(0x9888), 0x005a4000 },
1700         { _MMIO(0x9888), 0x065a8000 },
1701         { _MMIO(0x9888), 0x085ac000 },
1702         { _MMIO(0x9888), 0x0e5ac000 },
1703         { _MMIO(0x9888), 0x001d4000 },
1704         { _MMIO(0x9888), 0x061d8000 },
1705         { _MMIO(0x9888), 0x081dc000 },
1706         { _MMIO(0x9888), 0x0e1dc000 },
1707         { _MMIO(0x9888), 0x0c1f0800 },
1708         { _MMIO(0x9888), 0x0e1f2a00 },
1709         { _MMIO(0x9888), 0x101f0280 },
1710         { _MMIO(0x9888), 0x00391000 },
1711         { _MMIO(0x9888), 0x06394000 },
1712         { _MMIO(0x9888), 0x08395000 },
1713         { _MMIO(0x9888), 0x0e395000 },
1714         { _MMIO(0x9888), 0x0abf1429 },
1715         { _MMIO(0x9888), 0x0cbf1225 },
1716         { _MMIO(0x9888), 0x00bf1380 },
1717         { _MMIO(0x9888), 0x02bf0026 },
1718         { _MMIO(0x9888), 0x10bf0000 },
1719         { _MMIO(0x9888), 0x0adac000 },
1720         { _MMIO(0x9888), 0x0cdac000 },
1721         { _MMIO(0x9888), 0x00da8000 },
1722         { _MMIO(0x9888), 0x02da4000 },
1723         { _MMIO(0x9888), 0x0a9dc000 },
1724         { _MMIO(0x9888), 0x0c9dc000 },
1725         { _MMIO(0x9888), 0x009d8000 },
1726         { _MMIO(0x9888), 0x029d4000 },
1727         { _MMIO(0x9888), 0x0e9f8000 },
1728         { _MMIO(0x9888), 0x109f002a },
1729         { _MMIO(0x9888), 0x0c9fa000 },
1730         { _MMIO(0x9888), 0x0ab95000 },
1731         { _MMIO(0x9888), 0x0cb95000 },
1732         { _MMIO(0x9888), 0x00b94000 },
1733         { _MMIO(0x9888), 0x02b91000 },
1734         { _MMIO(0x9888), 0x0d88c000 },
1735         { _MMIO(0x9888), 0x0f880003 },
1736         { _MMIO(0x9888), 0x03888000 },
1737         { _MMIO(0x9888), 0x05888000 },
1738         { _MMIO(0x9888), 0x018a8000 },
1739         { _MMIO(0x9888), 0x0f8a8000 },
1740         { _MMIO(0x9888), 0x198a8000 },
1741         { _MMIO(0x9888), 0x1b8a8020 },
1742         { _MMIO(0x9888), 0x1d8a0002 },
1743         { _MMIO(0x9888), 0x238b0520 },
1744         { _MMIO(0x9888), 0x258ba950 },
1745         { _MMIO(0x9888), 0x278b0016 },
1746         { _MMIO(0x9888), 0x198c5400 },
1747         { _MMIO(0x9888), 0x1b8c0001 },
1748         { _MMIO(0x9888), 0x038c4000 },
1749         { _MMIO(0x9888), 0x058c4000 },
1750         { _MMIO(0x9888), 0x0b8da000 },
1751         { _MMIO(0x9888), 0x0d8da000 },
1752         { _MMIO(0x9888), 0x018d8000 },
1753         { _MMIO(0x9888), 0x038d2000 },
1754         { _MMIO(0x9888), 0x1f85aa80 },
1755         { _MMIO(0x9888), 0x2185aaa0 },
1756         { _MMIO(0x9888), 0x2385002a },
1757         { _MMIO(0x9888), 0x03835180 },
1758         { _MMIO(0x9888), 0x05834022 },
1759         { _MMIO(0x9888), 0x11830000 },
1760         { _MMIO(0x9888), 0x01834000 },
1761         { _MMIO(0x9888), 0x0f834000 },
1762         { _MMIO(0x9888), 0x19835400 },
1763         { _MMIO(0x9888), 0x1b830155 },
1764         { _MMIO(0x9888), 0x07830000 },
1765         { _MMIO(0x9888), 0x09830000 },
1766         { _MMIO(0x9888), 0x0184c000 },
1767         { _MMIO(0x9888), 0x07848000 },
1768         { _MMIO(0x9888), 0x0984c000 },
1769         { _MMIO(0x9888), 0x0b84c000 },
1770         { _MMIO(0x9888), 0x0d84c000 },
1771         { _MMIO(0x9888), 0x0f84c000 },
1772         { _MMIO(0x9888), 0x0384c000 },
1773         { _MMIO(0x9888), 0x05844000 },
1774         { _MMIO(0x9888), 0x1b80c137 },
1775         { _MMIO(0x9888), 0x1d80c147 },
1776         { _MMIO(0x9888), 0x21800000 },
1777         { _MMIO(0x9888), 0x1180c000 },
1778         { _MMIO(0x9888), 0x17808000 },
1779         { _MMIO(0x9888), 0x1980c000 },
1780         { _MMIO(0x9888), 0x1f80c000 },
1781         { _MMIO(0x9888), 0x1380c000 },
1782         { _MMIO(0x9888), 0x15804000 },
1783         { _MMIO(0xd24), 0x00000000 },
1784         { _MMIO(0x9888), 0x4d801000 },
1785         { _MMIO(0x9888), 0x4f800111 },
1786         { _MMIO(0x9888), 0x43800842 },
1787         { _MMIO(0x9888), 0x51800000 },
1788         { _MMIO(0x9888), 0x45800000 },
1789         { _MMIO(0x9888), 0x53800000 },
1790         { _MMIO(0x9888), 0x47800840 },
1791         { _MMIO(0x9888), 0x31800000 },
1792         { _MMIO(0x9888), 0x3f800800 },
1793         { _MMIO(0x9888), 0x418014a2 },
1794 };
1795
1796 static int
1797 get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
1798                                 const struct i915_oa_reg **regs,
1799                                 int *lens)
1800 {
1801         int n = 0;
1802
1803         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1804         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1805
1806         regs[n] = mux_config_compute_l3_cache;
1807         lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
1808         n++;
1809
1810         return n;
1811 }
1812
1813 static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = {
1814         { _MMIO(0x2724), 0xf0800000 },
1815         { _MMIO(0x2720), 0x00000000 },
1816         { _MMIO(0x2714), 0xf0800000 },
1817         { _MMIO(0x2710), 0x00000000 },
1818         { _MMIO(0x274c), 0xba98ba98 },
1819         { _MMIO(0x2748), 0xba98ba98 },
1820         { _MMIO(0x2744), 0x00003377 },
1821         { _MMIO(0x2740), 0x00000000 },
1822         { _MMIO(0x2770), 0x0007fff2 },
1823         { _MMIO(0x2774), 0x00007ff0 },
1824         { _MMIO(0x2778), 0x0007ffe2 },
1825         { _MMIO(0x277c), 0x00007ff0 },
1826         { _MMIO(0x2780), 0x0007ffc2 },
1827         { _MMIO(0x2784), 0x00007ff0 },
1828         { _MMIO(0x2788), 0x0007ff82 },
1829         { _MMIO(0x278c), 0x00007ff0 },
1830         { _MMIO(0x2790), 0x0007fffa },
1831         { _MMIO(0x2794), 0x0000bfef },
1832         { _MMIO(0x2798), 0x0007fffa },
1833         { _MMIO(0x279c), 0x0000bfdf },
1834         { _MMIO(0x27a0), 0x0007fffa },
1835         { _MMIO(0x27a4), 0x0000bfbf },
1836         { _MMIO(0x27a8), 0x0007fffa },
1837         { _MMIO(0x27ac), 0x0000bf7f },
1838 };
1839
1840 static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = {
1841         { _MMIO(0xe458), 0x00005004 },
1842         { _MMIO(0xe558), 0x00000003 },
1843         { _MMIO(0xe658), 0x00002001 },
1844         { _MMIO(0xe758), 0x00778008 },
1845         { _MMIO(0xe45c), 0x00088078 },
1846         { _MMIO(0xe55c), 0x00808708 },
1847         { _MMIO(0xe65c), 0x00a08908 },
1848 };
1849
1850 static const struct i915_oa_reg mux_config_data_port_reads_coalescing_0_subslices_0x01[] = {
1851         { _MMIO(0x9888), 0x103d0005 },
1852         { _MMIO(0x9888), 0x163d240b },
1853         { _MMIO(0x9888), 0x1058022f },
1854         { _MMIO(0x9888), 0x185b5520 },
1855         { _MMIO(0x9888), 0x198b0003 },
1856         { _MMIO(0x9888), 0x005cc000 },
1857         { _MMIO(0x9888), 0x065cc000 },
1858         { _MMIO(0x9888), 0x085cc000 },
1859         { _MMIO(0x9888), 0x0a5cc000 },
1860         { _MMIO(0x9888), 0x0c5cc000 },
1861         { _MMIO(0x9888), 0x0e5cc000 },
1862         { _MMIO(0x9888), 0x025c4000 },
1863         { _MMIO(0x9888), 0x045c8000 },
1864         { _MMIO(0x9888), 0x003d0000 },
1865         { _MMIO(0x9888), 0x063d00b0 },
1866         { _MMIO(0x9888), 0x083d0182 },
1867         { _MMIO(0x9888), 0x0a3d10a0 },
1868         { _MMIO(0x9888), 0x0c3d11a2 },
1869         { _MMIO(0x9888), 0x0e3d0000 },
1870         { _MMIO(0x9888), 0x183d0000 },
1871         { _MMIO(0x9888), 0x1a3d0000 },
1872         { _MMIO(0x9888), 0x0e582242 },
1873         { _MMIO(0x9888), 0x00586700 },
1874         { _MMIO(0x9888), 0x0258004f },
1875         { _MMIO(0x9888), 0x0658c000 },
1876         { _MMIO(0x9888), 0x0858c000 },
1877         { _MMIO(0x9888), 0x0a58c000 },
1878         { _MMIO(0x9888), 0x0c58c000 },
1879         { _MMIO(0x9888), 0x045b6300 },
1880         { _MMIO(0x9888), 0x105b0000 },
1881         { _MMIO(0x9888), 0x005b4000 },
1882         { _MMIO(0x9888), 0x0e5b4000 },
1883         { _MMIO(0x9888), 0x1a5b0155 },
1884         { _MMIO(0x9888), 0x025b4000 },
1885         { _MMIO(0x9888), 0x0a5b0000 },
1886         { _MMIO(0x9888), 0x0c5b4000 },
1887         { _MMIO(0x9888), 0x0c1fa800 },
1888         { _MMIO(0x9888), 0x0e1faaa0 },
1889         { _MMIO(0x9888), 0x101f02aa },
1890         { _MMIO(0x9888), 0x00384000 },
1891         { _MMIO(0x9888), 0x0e384000 },
1892         { _MMIO(0x9888), 0x16384000 },
1893         { _MMIO(0x9888), 0x18381555 },
1894         { _MMIO(0x9888), 0x02384000 },
1895         { _MMIO(0x9888), 0x04384000 },
1896         { _MMIO(0x9888), 0x0a384000 },
1897         { _MMIO(0x9888), 0x0c384000 },
1898         { _MMIO(0x9888), 0x0039a000 },
1899         { _MMIO(0x9888), 0x0639a000 },
1900         { _MMIO(0x9888), 0x0839a000 },
1901         { _MMIO(0x9888), 0x0a39a000 },
1902         { _MMIO(0x9888), 0x0c39a000 },
1903         { _MMIO(0x9888), 0x0e39a000 },
1904         { _MMIO(0x9888), 0x02392000 },
1905         { _MMIO(0x9888), 0x04398000 },
1906         { _MMIO(0x9888), 0x018a8000 },
1907         { _MMIO(0x9888), 0x0f8a8000 },
1908         { _MMIO(0x9888), 0x198a8000 },
1909         { _MMIO(0x9888), 0x1b8aaaa0 },
1910         { _MMIO(0x9888), 0x1d8a0002 },
1911         { _MMIO(0x9888), 0x038a8000 },
1912         { _MMIO(0x9888), 0x058a8000 },
1913         { _MMIO(0x9888), 0x0b8a8000 },
1914         { _MMIO(0x9888), 0x0d8a8000 },
1915         { _MMIO(0x9888), 0x038b6300 },
1916         { _MMIO(0x9888), 0x058b0062 },
1917         { _MMIO(0x9888), 0x118b0000 },
1918         { _MMIO(0x9888), 0x238b02a0 },
1919         { _MMIO(0x9888), 0x258b5555 },
1920         { _MMIO(0x9888), 0x278b0015 },
1921         { _MMIO(0x9888), 0x1f85aa80 },
1922         { _MMIO(0x9888), 0x2185aaaa },
1923         { _MMIO(0x9888), 0x2385002a },
1924         { _MMIO(0x9888), 0x01834000 },
1925         { _MMIO(0x9888), 0x0f834000 },
1926         { _MMIO(0x9888), 0x19835400 },
1927         { _MMIO(0x9888), 0x1b830155 },
1928         { _MMIO(0x9888), 0x03834000 },
1929         { _MMIO(0x9888), 0x05834000 },
1930         { _MMIO(0x9888), 0x07834000 },
1931         { _MMIO(0x9888), 0x09834000 },
1932         { _MMIO(0x9888), 0x0b834000 },
1933         { _MMIO(0x9888), 0x0d834000 },
1934         { _MMIO(0x9888), 0x0184c000 },
1935         { _MMIO(0x9888), 0x0784c000 },
1936         { _MMIO(0x9888), 0x0984c000 },
1937         { _MMIO(0x9888), 0x0b84c000 },
1938         { _MMIO(0x9888), 0x0d84c000 },
1939         { _MMIO(0x9888), 0x0f84c000 },
1940         { _MMIO(0x9888), 0x0384c000 },
1941         { _MMIO(0x9888), 0x0584c000 },
1942         { _MMIO(0x9888), 0x1180c000 },
1943         { _MMIO(0x9888), 0x1780c000 },
1944         { _MMIO(0x9888), 0x1980c000 },
1945         { _MMIO(0x9888), 0x1b80c000 },
1946         { _MMIO(0x9888), 0x1d80c000 },
1947         { _MMIO(0x9888), 0x1f80c000 },
1948         { _MMIO(0x9888), 0x1380c000 },
1949         { _MMIO(0x9888), 0x1580c000 },
1950         { _MMIO(0xd24), 0x00000000 },
1951         { _MMIO(0x9888), 0x4d801000 },
1952         { _MMIO(0x9888), 0x3d800000 },
1953         { _MMIO(0x9888), 0x4f800001 },
1954         { _MMIO(0x9888), 0x43800000 },
1955         { _MMIO(0x9888), 0x51800000 },
1956         { _MMIO(0x9888), 0x45800000 },
1957         { _MMIO(0x9888), 0x53800000 },
1958         { _MMIO(0x9888), 0x47800420 },
1959         { _MMIO(0x9888), 0x21800000 },
1960         { _MMIO(0x9888), 0x31800000 },
1961         { _MMIO(0x9888), 0x3f800421 },
1962         { _MMIO(0x9888), 0x41800041 },
1963 };
1964
1965 static int
1966 get_data_port_reads_coalescing_mux_config(struct drm_i915_private *dev_priv,
1967                                           const struct i915_oa_reg **regs,
1968                                           int *lens)
1969 {
1970         int n = 0;
1971
1972         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1973         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1974
1975         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
1976                 regs[n] = mux_config_data_port_reads_coalescing_0_subslices_0x01;
1977                 lens[n] = ARRAY_SIZE(mux_config_data_port_reads_coalescing_0_subslices_0x01);
1978                 n++;
1979         }
1980
1981         return n;
1982 }
1983
1984 static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = {
1985         { _MMIO(0x2724), 0xf0800000 },
1986         { _MMIO(0x2720), 0x00000000 },
1987         { _MMIO(0x2714), 0xf0800000 },
1988         { _MMIO(0x2710), 0x00000000 },
1989         { _MMIO(0x274c), 0xba98ba98 },
1990         { _MMIO(0x2748), 0xba98ba98 },
1991         { _MMIO(0x2744), 0x00003377 },
1992         { _MMIO(0x2740), 0x00000000 },
1993         { _MMIO(0x2770), 0x0007ff72 },
1994         { _MMIO(0x2774), 0x0000bfd0 },
1995         { _MMIO(0x2778), 0x0007ff62 },
1996         { _MMIO(0x277c), 0x0000bfd0 },
1997         { _MMIO(0x2780), 0x0007ff42 },
1998         { _MMIO(0x2784), 0x0000bfd0 },
1999         { _MMIO(0x2788), 0x0007ff02 },
2000         { _MMIO(0x278c), 0x0000bfd0 },
2001         { _MMIO(0x2790), 0x0005fff2 },
2002         { _MMIO(0x2794), 0x0000bfd0 },
2003         { _MMIO(0x2798), 0x0005ffe2 },
2004         { _MMIO(0x279c), 0x0000bfd0 },
2005         { _MMIO(0x27a0), 0x0005ffc2 },
2006         { _MMIO(0x27a4), 0x0000bfd0 },
2007         { _MMIO(0x27a8), 0x0005ff82 },
2008         { _MMIO(0x27ac), 0x0000bfd0 },
2009 };
2010
2011 static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = {
2012         { _MMIO(0xe458), 0x00005004 },
2013         { _MMIO(0xe558), 0x00000003 },
2014         { _MMIO(0xe658), 0x00002001 },
2015         { _MMIO(0xe758), 0x00778008 },
2016         { _MMIO(0xe45c), 0x00088078 },
2017         { _MMIO(0xe55c), 0x00808708 },
2018         { _MMIO(0xe65c), 0x00a08908 },
2019 };
2020
2021 static const struct i915_oa_reg mux_config_data_port_writes_coalescing_0_subslices_0x01[] = {
2022         { _MMIO(0x9888), 0x103d0005 },
2023         { _MMIO(0x9888), 0x143d0120 },
2024         { _MMIO(0x9888), 0x163d2400 },
2025         { _MMIO(0x9888), 0x1058022f },
2026         { _MMIO(0x9888), 0x105b0000 },
2027         { _MMIO(0x9888), 0x198b0003 },
2028         { _MMIO(0x9888), 0x005cc000 },
2029         { _MMIO(0x9888), 0x065cc000 },
2030         { _MMIO(0x9888), 0x085cc000 },
2031         { _MMIO(0x9888), 0x0a5cc000 },
2032         { _MMIO(0x9888), 0x0e5cc000 },
2033         { _MMIO(0x9888), 0x025c4000 },
2034         { _MMIO(0x9888), 0x045c8000 },
2035         { _MMIO(0x9888), 0x003d0000 },
2036         { _MMIO(0x9888), 0x063d0094 },
2037         { _MMIO(0x9888), 0x083d0182 },
2038         { _MMIO(0x9888), 0x0a3d1814 },
2039         { _MMIO(0x9888), 0x0e3d0000 },
2040         { _MMIO(0x9888), 0x183d0000 },
2041         { _MMIO(0x9888), 0x1a3d0000 },
2042         { _MMIO(0x9888), 0x0c3d0000 },
2043         { _MMIO(0x9888), 0x0e582242 },
2044         { _MMIO(0x9888), 0x00586700 },
2045         { _MMIO(0x9888), 0x0258004f },
2046         { _MMIO(0x9888), 0x0658c000 },
2047         { _MMIO(0x9888), 0x0858c000 },
2048         { _MMIO(0x9888), 0x0a58c000 },
2049         { _MMIO(0x9888), 0x045b6a80 },
2050         { _MMIO(0x9888), 0x005b4000 },
2051         { _MMIO(0x9888), 0x0e5b4000 },
2052         { _MMIO(0x9888), 0x185b5400 },
2053         { _MMIO(0x9888), 0x1a5b0141 },
2054         { _MMIO(0x9888), 0x025b4000 },
2055         { _MMIO(0x9888), 0x0a5b0000 },
2056         { _MMIO(0x9888), 0x0c5b4000 },
2057         { _MMIO(0x9888), 0x0c1fa800 },
2058         { _MMIO(0x9888), 0x0e1faaa0 },
2059         { _MMIO(0x9888), 0x101f0282 },
2060         { _MMIO(0x9888), 0x00384000 },
2061         { _MMIO(0x9888), 0x0e384000 },
2062         { _MMIO(0x9888), 0x16384000 },
2063         { _MMIO(0x9888), 0x18381415 },
2064         { _MMIO(0x9888), 0x02384000 },
2065         { _MMIO(0x9888), 0x04384000 },
2066         { _MMIO(0x9888), 0x0a384000 },
2067         { _MMIO(0x9888), 0x0c384000 },
2068         { _MMIO(0x9888), 0x0039a000 },
2069         { _MMIO(0x9888), 0x0639a000 },
2070         { _MMIO(0x9888), 0x0839a000 },
2071         { _MMIO(0x9888), 0x0a39a000 },
2072         { _MMIO(0x9888), 0x0e39a000 },
2073         { _MMIO(0x9888), 0x02392000 },
2074         { _MMIO(0x9888), 0x04398000 },
2075         { _MMIO(0x9888), 0x018a8000 },
2076         { _MMIO(0x9888), 0x0f8a8000 },
2077         { _MMIO(0x9888), 0x198a8000 },
2078         { _MMIO(0x9888), 0x1b8a82a0 },
2079         { _MMIO(0x9888), 0x1d8a0002 },
2080         { _MMIO(0x9888), 0x038a8000 },
2081         { _MMIO(0x9888), 0x058a8000 },
2082         { _MMIO(0x9888), 0x0b8a8000 },
2083         { _MMIO(0x9888), 0x0d8a8000 },
2084         { _MMIO(0x9888), 0x038b6300 },
2085         { _MMIO(0x9888), 0x058b0062 },
2086         { _MMIO(0x9888), 0x118b0000 },
2087         { _MMIO(0x9888), 0x238b02a0 },
2088         { _MMIO(0x9888), 0x258b1555 },
2089         { _MMIO(0x9888), 0x278b0014 },
2090         { _MMIO(0x9888), 0x1f85aa80 },
2091         { _MMIO(0x9888), 0x21852aaa },
2092         { _MMIO(0x9888), 0x23850028 },
2093         { _MMIO(0x9888), 0x01834000 },
2094         { _MMIO(0x9888), 0x0f834000 },
2095         { _MMIO(0x9888), 0x19835400 },
2096         { _MMIO(0x9888), 0x1b830141 },
2097         { _MMIO(0x9888), 0x03834000 },
2098         { _MMIO(0x9888), 0x05834000 },
2099         { _MMIO(0x9888), 0x07834000 },
2100         { _MMIO(0x9888), 0x09834000 },
2101         { _MMIO(0x9888), 0x0b834000 },
2102         { _MMIO(0x9888), 0x0d834000 },
2103         { _MMIO(0x9888), 0x0184c000 },
2104         { _MMIO(0x9888), 0x0784c000 },
2105         { _MMIO(0x9888), 0x0984c000 },
2106         { _MMIO(0x9888), 0x0b84c000 },
2107         { _MMIO(0x9888), 0x0f84c000 },
2108         { _MMIO(0x9888), 0x0384c000 },
2109         { _MMIO(0x9888), 0x0584c000 },
2110         { _MMIO(0x9888), 0x1180c000 },
2111         { _MMIO(0x9888), 0x1780c000 },
2112         { _MMIO(0x9888), 0x1980c000 },
2113         { _MMIO(0x9888), 0x1b80c000 },
2114         { _MMIO(0x9888), 0x1f80c000 },
2115         { _MMIO(0x9888), 0x1380c000 },
2116         { _MMIO(0x9888), 0x1580c000 },
2117         { _MMIO(0xd24), 0x00000000 },
2118         { _MMIO(0x9888), 0x4d801000 },
2119         { _MMIO(0x9888), 0x3d800000 },
2120         { _MMIO(0x9888), 0x4f800001 },
2121         { _MMIO(0x9888), 0x43800000 },
2122         { _MMIO(0x9888), 0x51800000 },
2123         { _MMIO(0x9888), 0x45800000 },
2124         { _MMIO(0x9888), 0x21800000 },
2125         { _MMIO(0x9888), 0x31800000 },
2126         { _MMIO(0x9888), 0x53800000 },
2127         { _MMIO(0x9888), 0x47800420 },
2128         { _MMIO(0x9888), 0x3f800421 },
2129         { _MMIO(0x9888), 0x41800041 },
2130 };
2131
2132 static int
2133 get_data_port_writes_coalescing_mux_config(struct drm_i915_private *dev_priv,
2134                                            const struct i915_oa_reg **regs,
2135                                            int *lens)
2136 {
2137         int n = 0;
2138
2139         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2140         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2141
2142         if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
2143                 regs[n] = mux_config_data_port_writes_coalescing_0_subslices_0x01;
2144                 lens[n] = ARRAY_SIZE(mux_config_data_port_writes_coalescing_0_subslices_0x01);
2145                 n++;
2146         }
2147
2148         return n;
2149 }
2150
2151 static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
2152         { _MMIO(0x2740), 0x00000000 },
2153         { _MMIO(0x2744), 0x00800000 },
2154         { _MMIO(0x2710), 0x00000000 },
2155         { _MMIO(0x2714), 0x10800000 },
2156         { _MMIO(0x2720), 0x00000000 },
2157         { _MMIO(0x2724), 0x00800000 },
2158         { _MMIO(0x2770), 0x00000002 },
2159         { _MMIO(0x2774), 0x0000fff7 },
2160 };
2161
2162 static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
2163         { _MMIO(0xe458), 0x00005004 },
2164         { _MMIO(0xe558), 0x00010003 },
2165         { _MMIO(0xe658), 0x00012011 },
2166         { _MMIO(0xe758), 0x00015014 },
2167         { _MMIO(0xe45c), 0x00051050 },
2168         { _MMIO(0xe55c), 0x00053052 },
2169         { _MMIO(0xe65c), 0x00055054 },
2170 };
2171
2172 static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
2173         { _MMIO(0x9888), 0x105c0232 },
2174         { _MMIO(0x9888), 0x10580232 },
2175         { _MMIO(0x9888), 0x10380232 },
2176         { _MMIO(0x9888), 0x10dc0232 },
2177         { _MMIO(0x9888), 0x10d80232 },
2178         { _MMIO(0x9888), 0x10b80232 },
2179         { _MMIO(0x9888), 0x118e4400 },
2180         { _MMIO(0x9888), 0x025c6080 },
2181         { _MMIO(0x9888), 0x045c004b },
2182         { _MMIO(0x9888), 0x005c8000 },
2183         { _MMIO(0x9888), 0x00582080 },
2184         { _MMIO(0x9888), 0x0258004b },
2185         { _MMIO(0x9888), 0x025b4000 },
2186         { _MMIO(0x9888), 0x045b4000 },
2187         { _MMIO(0x9888), 0x0c1fa000 },
2188         { _MMIO(0x9888), 0x0e1f00aa },
2189         { _MMIO(0x9888), 0x04386080 },
2190         { _MMIO(0x9888), 0x0638404b },
2191         { _MMIO(0x9888), 0x02384000 },
2192         { _MMIO(0x9888), 0x08384000 },
2193         { _MMIO(0x9888), 0x0a380000 },
2194         { _MMIO(0x9888), 0x0c380000 },
2195         { _MMIO(0x9888), 0x00398000 },
2196         { _MMIO(0x9888), 0x0239a000 },
2197         { _MMIO(0x9888), 0x0439a000 },
2198         { _MMIO(0x9888), 0x06392000 },
2199         { _MMIO(0x9888), 0x0cdc25c1 },
2200         { _MMIO(0x9888), 0x0adcc000 },
2201         { _MMIO(0x9888), 0x0ad825c1 },
2202         { _MMIO(0x9888), 0x18db4000 },
2203         { _MMIO(0x9888), 0x1adb0001 },
2204         { _MMIO(0x9888), 0x0e9f8000 },
2205         { _MMIO(0x9888), 0x109f02aa },
2206         { _MMIO(0x9888), 0x0eb825c1 },
2207         { _MMIO(0x9888), 0x18b80154 },
2208         { _MMIO(0x9888), 0x0ab9a000 },
2209         { _MMIO(0x9888), 0x0cb9a000 },
2210         { _MMIO(0x9888), 0x0eb9a000 },
2211         { _MMIO(0x9888), 0x0d88c000 },
2212         { _MMIO(0x9888), 0x0f88000f },
2213         { _MMIO(0x9888), 0x038a8000 },
2214         { _MMIO(0x9888), 0x058a8000 },
2215         { _MMIO(0x9888), 0x078a8000 },
2216         { _MMIO(0x9888), 0x098a8000 },
2217         { _MMIO(0x9888), 0x0b8a8000 },
2218         { _MMIO(0x9888), 0x0d8a8000 },
2219         { _MMIO(0x9888), 0x258baa05 },
2220         { _MMIO(0x9888), 0x278b002a },
2221         { _MMIO(0x9888), 0x238b2a80 },
2222         { _MMIO(0x9888), 0x198c5400 },
2223         { _MMIO(0x9888), 0x1b8c0015 },
2224         { _MMIO(0x9888), 0x098dc000 },
2225         { _MMIO(0x9888), 0x0b8da000 },
2226         { _MMIO(0x9888), 0x0d8da000 },
2227         { _MMIO(0x9888), 0x0f8da000 },
2228         { _MMIO(0x9888), 0x098e05c0 },
2229         { _MMIO(0x9888), 0x058e0000 },
2230         { _MMIO(0x9888), 0x198f0020 },
2231         { _MMIO(0x9888), 0x2185aa0a },
2232         { _MMIO(0x9888), 0x2385002a },
2233         { _MMIO(0x9888), 0x1f85aa00 },
2234         { _MMIO(0x9888), 0x19835000 },
2235         { _MMIO(0x9888), 0x1b830155 },
2236         { _MMIO(0x9888), 0x03834000 },
2237         { _MMIO(0x9888), 0x05834000 },
2238         { _MMIO(0x9888), 0x07834000 },
2239         { _MMIO(0x9888), 0x09834000 },
2240         { _MMIO(0x9888), 0x0b834000 },
2241         { _MMIO(0x9888), 0x0d834000 },
2242         { _MMIO(0x9888), 0x09848000 },
2243         { _MMIO(0x9888), 0x0b84c000 },
2244         { _MMIO(0x9888), 0x0d84c000 },
2245         { _MMIO(0x9888), 0x0f84c000 },
2246         { _MMIO(0x9888), 0x01848000 },
2247         { _MMIO(0x9888), 0x0384c000 },
2248         { _MMIO(0x9888), 0x0584c000 },
2249         { _MMIO(0x9888), 0x07844000 },
2250         { _MMIO(0x9888), 0x19808000 },
2251         { _MMIO(0x9888), 0x1b80c000 },
2252         { _MMIO(0x9888), 0x1d80c000 },
2253         { _MMIO(0x9888), 0x1f80c000 },
2254         { _MMIO(0x9888), 0x11808000 },
2255         { _MMIO(0x9888), 0x1380c000 },
2256         { _MMIO(0x9888), 0x1580c000 },
2257         { _MMIO(0x9888), 0x17804000 },
2258         { _MMIO(0x9888), 0x51800040 },
2259         { _MMIO(0x9888), 0x43800400 },
2260         { _MMIO(0x9888), 0x45800800 },
2261         { _MMIO(0x9888), 0x53800000 },
2262         { _MMIO(0x9888), 0x47800c62 },
2263         { _MMIO(0x9888), 0x21800000 },
2264         { _MMIO(0x9888), 0x31800000 },
2265         { _MMIO(0x9888), 0x4d800000 },
2266         { _MMIO(0x9888), 0x3f801042 },
2267         { _MMIO(0x9888), 0x4f800000 },
2268         { _MMIO(0x9888), 0x418014a4 },
2269 };
2270
2271 static int
2272 get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
2273                           const struct i915_oa_reg **regs,
2274                           int *lens)
2275 {
2276         int n = 0;
2277
2278         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2279         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2280
2281         regs[n] = mux_config_hdc_and_sf;
2282         lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
2283         n++;
2284
2285         return n;
2286 }
2287
2288 static const struct i915_oa_reg b_counter_config_l3_1[] = {
2289         { _MMIO(0x2740), 0x00000000 },
2290         { _MMIO(0x2744), 0x00800000 },
2291         { _MMIO(0x2710), 0x00000000 },
2292         { _MMIO(0x2714), 0xf0800000 },
2293         { _MMIO(0x2720), 0x00000000 },
2294         { _MMIO(0x2724), 0xf0800000 },
2295         { _MMIO(0x2770), 0x00100070 },
2296         { _MMIO(0x2774), 0x0000fff1 },
2297         { _MMIO(0x2778), 0x00014002 },
2298         { _MMIO(0x277c), 0x0000c3ff },
2299         { _MMIO(0x2780), 0x00010002 },
2300         { _MMIO(0x2784), 0x0000c7ff },
2301         { _MMIO(0x2788), 0x00004002 },
2302         { _MMIO(0x278c), 0x0000d3ff },
2303         { _MMIO(0x2790), 0x00100700 },
2304         { _MMIO(0x2794), 0x0000ff1f },
2305         { _MMIO(0x2798), 0x00001402 },
2306         { _MMIO(0x279c), 0x0000fc3f },
2307         { _MMIO(0x27a0), 0x00001002 },
2308         { _MMIO(0x27a4), 0x0000fc7f },
2309         { _MMIO(0x27a8), 0x00000402 },
2310         { _MMIO(0x27ac), 0x0000fd3f },
2311 };
2312
2313 static const struct i915_oa_reg flex_eu_config_l3_1[] = {
2314         { _MMIO(0xe458), 0x00005004 },
2315         { _MMIO(0xe558), 0x00010003 },
2316         { _MMIO(0xe658), 0x00012011 },
2317         { _MMIO(0xe758), 0x00015014 },
2318         { _MMIO(0xe45c), 0x00051050 },
2319         { _MMIO(0xe55c), 0x00053052 },
2320         { _MMIO(0xe65c), 0x00055054 },
2321 };
2322
2323 static const struct i915_oa_reg mux_config_l3_1[] = {
2324         { _MMIO(0x9888), 0x10bf03da },
2325         { _MMIO(0x9888), 0x14bf0001 },
2326         { _MMIO(0x9888), 0x12980340 },
2327         { _MMIO(0x9888), 0x12990340 },
2328         { _MMIO(0x9888), 0x0cbf1187 },
2329         { _MMIO(0x9888), 0x0ebf1205 },
2330         { _MMIO(0x9888), 0x00bf0500 },
2331         { _MMIO(0x9888), 0x02bf042b },
2332         { _MMIO(0x9888), 0x04bf002c },
2333         { _MMIO(0x9888), 0x0cdac000 },
2334         { _MMIO(0x9888), 0x0edac000 },
2335         { _MMIO(0x9888), 0x00da8000 },
2336         { _MMIO(0x9888), 0x02dac000 },
2337         { _MMIO(0x9888), 0x04da4000 },
2338         { _MMIO(0x9888), 0x04983400 },
2339         { _MMIO(0x9888), 0x10980000 },
2340         { _MMIO(0x9888), 0x06990034 },
2341         { _MMIO(0x9888), 0x10990000 },
2342         { _MMIO(0x9888), 0x0c9dc000 },
2343         { _MMIO(0x9888), 0x0e9dc000 },
2344         { _MMIO(0x9888), 0x009d8000 },
2345         { _MMIO(0x9888), 0x029dc000 },
2346         { _MMIO(0x9888), 0x049d4000 },
2347         { _MMIO(0x9888), 0x109f02a8 },
2348         { _MMIO(0x9888), 0x0c9fa000 },
2349         { _MMIO(0x9888), 0x0e9f00ba },
2350         { _MMIO(0x9888), 0x0cb88000 },
2351         { _MMIO(0x9888), 0x0cb95000 },
2352         { _MMIO(0x9888), 0x0eb95000 },
2353         { _MMIO(0x9888), 0x00b94000 },
2354         { _MMIO(0x9888), 0x02b95000 },
2355         { _MMIO(0x9888), 0x04b91000 },
2356         { _MMIO(0x9888), 0x06b92000 },
2357         { _MMIO(0x9888), 0x0cba4000 },
2358         { _MMIO(0x9888), 0x0f88000f },
2359         { _MMIO(0x9888), 0x03888000 },
2360         { _MMIO(0x9888), 0x05888000 },
2361         { _MMIO(0x9888), 0x07888000 },
2362         { _MMIO(0x9888), 0x09888000 },
2363         { _MMIO(0x9888), 0x0b888000 },
2364         { _MMIO(0x9888), 0x0d880400 },
2365         { _MMIO(0x9888), 0x258b800a },
2366         { _MMIO(0x9888), 0x278b002a },
2367         { _MMIO(0x9888), 0x238b5500 },
2368         { _MMIO(0x9888), 0x198c4000 },
2369         { _MMIO(0x9888), 0x1b8c0015 },
2370         { _MMIO(0x9888), 0x038c4000 },
2371         { _MMIO(0x9888), 0x058c4000 },
2372         { _MMIO(0x9888), 0x078c4000 },
2373         { _MMIO(0x9888), 0x098c4000 },
2374         { _MMIO(0x9888), 0x0b8c4000 },
2375         { _MMIO(0x9888), 0x0d8c4000 },
2376         { _MMIO(0x9888), 0x0d8da000 },
2377         { _MMIO(0x9888), 0x0f8da000 },
2378         { _MMIO(0x9888), 0x018d8000 },
2379         { _MMIO(0x9888), 0x038da000 },
2380         { _MMIO(0x9888), 0x058da000 },
2381         { _MMIO(0x9888), 0x078d2000 },
2382         { _MMIO(0x9888), 0x2185800a },
2383         { _MMIO(0x9888), 0x2385002a },
2384         { _MMIO(0x9888), 0x1f85aa00 },
2385         { _MMIO(0x9888), 0x1b830154 },
2386         { _MMIO(0x9888), 0x03834000 },
2387         { _MMIO(0x9888), 0x05834000 },
2388         { _MMIO(0x9888), 0x07834000 },
2389         { _MMIO(0x9888), 0x09834000 },
2390         { _MMIO(0x9888), 0x0b834000 },
2391         { _MMIO(0x9888), 0x0d834000 },
2392         { _MMIO(0x9888), 0x0d84c000 },
2393         { _MMIO(0x9888), 0x0f84c000 },
2394         { _MMIO(0x9888), 0x01848000 },
2395         { _MMIO(0x9888), 0x0384c000 },
2396         { _MMIO(0x9888), 0x0584c000 },
2397         { _MMIO(0x9888), 0x07844000 },
2398         { _MMIO(0x9888), 0x1d80c000 },
2399         { _MMIO(0x9888), 0x1f80c000 },
2400         { _MMIO(0x9888), 0x11808000 },
2401         { _MMIO(0x9888), 0x1380c000 },
2402         { _MMIO(0x9888), 0x1580c000 },
2403         { _MMIO(0x9888), 0x17804000 },
2404         { _MMIO(0x9888), 0x53800000 },
2405         { _MMIO(0x9888), 0x45800000 },
2406         { _MMIO(0x9888), 0x47800000 },
2407         { _MMIO(0x9888), 0x21800000 },
2408         { _MMIO(0x9888), 0x31800000 },
2409         { _MMIO(0x9888), 0x4d800000 },
2410         { _MMIO(0x9888), 0x3f800000 },
2411         { _MMIO(0x9888), 0x4f800000 },
2412         { _MMIO(0x9888), 0x41800060 },
2413 };
2414
2415 static int
2416 get_l3_1_mux_config(struct drm_i915_private *dev_priv,
2417                     const struct i915_oa_reg **regs,
2418                     int *lens)
2419 {
2420         int n = 0;
2421
2422         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2423         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2424
2425         regs[n] = mux_config_l3_1;
2426         lens[n] = ARRAY_SIZE(mux_config_l3_1);
2427         n++;
2428
2429         return n;
2430 }
2431
2432 static const struct i915_oa_reg b_counter_config_l3_2[] = {
2433         { _MMIO(0x2740), 0x00000000 },
2434         { _MMIO(0x2744), 0x00800000 },
2435         { _MMIO(0x2710), 0x00000000 },
2436         { _MMIO(0x2714), 0xf0800000 },
2437         { _MMIO(0x2720), 0x00000000 },
2438         { _MMIO(0x2724), 0xf0800000 },
2439         { _MMIO(0x2770), 0x00100070 },
2440         { _MMIO(0x2774), 0x0000fff1 },
2441         { _MMIO(0x2778), 0x00014002 },
2442         { _MMIO(0x277c), 0x0000c3ff },
2443         { _MMIO(0x2780), 0x00010002 },
2444         { _MMIO(0x2784), 0x0000c7ff },
2445         { _MMIO(0x2788), 0x00004002 },
2446         { _MMIO(0x278c), 0x0000d3ff },
2447         { _MMIO(0x2790), 0x00100700 },
2448         { _MMIO(0x2794), 0x0000ff1f },
2449         { _MMIO(0x2798), 0x00001402 },
2450         { _MMIO(0x279c), 0x0000fc3f },
2451         { _MMIO(0x27a0), 0x00001002 },
2452         { _MMIO(0x27a4), 0x0000fc7f },
2453         { _MMIO(0x27a8), 0x00000402 },
2454         { _MMIO(0x27ac), 0x0000fd3f },
2455 };
2456
2457 static const struct i915_oa_reg flex_eu_config_l3_2[] = {
2458         { _MMIO(0xe458), 0x00005004 },
2459         { _MMIO(0xe558), 0x00010003 },
2460         { _MMIO(0xe658), 0x00012011 },
2461         { _MMIO(0xe758), 0x00015014 },
2462         { _MMIO(0xe45c), 0x00051050 },
2463         { _MMIO(0xe55c), 0x00053052 },
2464         { _MMIO(0xe65c), 0x00055054 },
2465 };
2466
2467 static const struct i915_oa_reg mux_config_l3_2[] = {
2468         { _MMIO(0x9888), 0x103f03da },
2469         { _MMIO(0x9888), 0x143f0001 },
2470         { _MMIO(0x9888), 0x12180340 },
2471         { _MMIO(0x9888), 0x12190340 },
2472         { _MMIO(0x9888), 0x0c3f1187 },
2473         { _MMIO(0x9888), 0x0e3f1205 },
2474         { _MMIO(0x9888), 0x003f0500 },
2475         { _MMIO(0x9888), 0x023f042b },
2476         { _MMIO(0x9888), 0x043f002c },
2477         { _MMIO(0x9888), 0x0c5ac000 },
2478         { _MMIO(0x9888), 0x0e5ac000 },
2479         { _MMIO(0x9888), 0x005a8000 },
2480         { _MMIO(0x9888), 0x025ac000 },
2481         { _MMIO(0x9888), 0x045a4000 },
2482         { _MMIO(0x9888), 0x04183400 },
2483         { _MMIO(0x9888), 0x10180000 },
2484         { _MMIO(0x9888), 0x06190034 },
2485         { _MMIO(0x9888), 0x10190000 },
2486         { _MMIO(0x9888), 0x0c1dc000 },
2487         { _MMIO(0x9888), 0x0e1dc000 },
2488         { _MMIO(0x9888), 0x001d8000 },
2489         { _MMIO(0x9888), 0x021dc000 },
2490         { _MMIO(0x9888), 0x041d4000 },
2491         { _MMIO(0x9888), 0x101f02a8 },
2492         { _MMIO(0x9888), 0x0c1fa000 },
2493         { _MMIO(0x9888), 0x0e1f00ba },
2494         { _MMIO(0x9888), 0x0c388000 },
2495         { _MMIO(0x9888), 0x0c395000 },
2496         { _MMIO(0x9888), 0x0e395000 },
2497         { _MMIO(0x9888), 0x00394000 },
2498         { _MMIO(0x9888), 0x02395000 },
2499         { _MMIO(0x9888), 0x04391000 },
2500         { _MMIO(0x9888), 0x06392000 },
2501         { _MMIO(0x9888), 0x0c3a4000 },
2502         { _MMIO(0x9888), 0x1b8aa800 },
2503         { _MMIO(0x9888), 0x1d8a0002 },
2504         { _MMIO(0x9888), 0x038a8000 },
2505         { _MMIO(0x9888), 0x058a8000 },
2506         { _MMIO(0x9888), 0x078a8000 },
2507         { _MMIO(0x9888), 0x098a8000 },
2508         { _MMIO(0x9888), 0x0b8a8000 },
2509         { _MMIO(0x9888), 0x0d8a8000 },
2510         { _MMIO(0x9888), 0x258b4005 },
2511         { _MMIO(0x9888), 0x278b0015 },
2512         { _MMIO(0x9888), 0x238b2a80 },
2513         { _MMIO(0x9888), 0x2185800a },
2514         { _MMIO(0x9888), 0x2385002a },
2515         { _MMIO(0x9888), 0x1f85aa00 },
2516         { _MMIO(0x9888), 0x1b830154 },
2517         { _MMIO(0x9888), 0x03834000 },
2518         { _MMIO(0x9888), 0x05834000 },
2519         { _MMIO(0x9888), 0x07834000 },
2520         { _MMIO(0x9888), 0x09834000 },
2521         { _MMIO(0x9888), 0x0b834000 },
2522         { _MMIO(0x9888), 0x0d834000 },
2523         { _MMIO(0x9888), 0x0d84c000 },
2524         { _MMIO(0x9888), 0x0f84c000 },
2525         { _MMIO(0x9888), 0x01848000 },
2526         { _MMIO(0x9888), 0x0384c000 },
2527         { _MMIO(0x9888), 0x0584c000 },
2528         { _MMIO(0x9888), 0x07844000 },
2529         { _MMIO(0x9888), 0x1d80c000 },
2530         { _MMIO(0x9888), 0x1f80c000 },
2531         { _MMIO(0x9888), 0x11808000 },
2532         { _MMIO(0x9888), 0x1380c000 },
2533         { _MMIO(0x9888), 0x1580c000 },
2534         { _MMIO(0x9888), 0x17804000 },
2535         { _MMIO(0x9888), 0x53800000 },
2536         { _MMIO(0x9888), 0x45800000 },
2537         { _MMIO(0x9888), 0x47800000 },
2538         { _MMIO(0x9888), 0x21800000 },
2539         { _MMIO(0x9888), 0x31800000 },
2540         { _MMIO(0x9888), 0x4d800000 },
2541         { _MMIO(0x9888), 0x3f800000 },
2542         { _MMIO(0x9888), 0x4f800000 },
2543         { _MMIO(0x9888), 0x41800060 },
2544 };
2545
2546 static int
2547 get_l3_2_mux_config(struct drm_i915_private *dev_priv,
2548                     const struct i915_oa_reg **regs,
2549                     int *lens)
2550 {
2551         int n = 0;
2552
2553         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2554         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2555
2556         regs[n] = mux_config_l3_2;
2557         lens[n] = ARRAY_SIZE(mux_config_l3_2);
2558         n++;
2559
2560         return n;
2561 }
2562
2563 static const struct i915_oa_reg b_counter_config_l3_3[] = {
2564         { _MMIO(0x2740), 0x00000000 },
2565         { _MMIO(0x2744), 0x00800000 },
2566         { _MMIO(0x2710), 0x00000000 },
2567         { _MMIO(0x2714), 0xf0800000 },
2568         { _MMIO(0x2720), 0x00000000 },
2569         { _MMIO(0x2724), 0xf0800000 },
2570         { _MMIO(0x2770), 0x00100070 },
2571         { _MMIO(0x2774), 0x0000fff1 },
2572         { _MMIO(0x2778), 0x00014002 },
2573         { _MMIO(0x277c), 0x0000c3ff },
2574         { _MMIO(0x2780), 0x00010002 },
2575         { _MMIO(0x2784), 0x0000c7ff },
2576         { _MMIO(0x2788), 0x00004002 },
2577         { _MMIO(0x278c), 0x0000d3ff },
2578         { _MMIO(0x2790), 0x00100700 },
2579         { _MMIO(0x2794), 0x0000ff1f },
2580         { _MMIO(0x2798), 0x00001402 },
2581         { _MMIO(0x279c), 0x0000fc3f },
2582         { _MMIO(0x27a0), 0x00001002 },
2583         { _MMIO(0x27a4), 0x0000fc7f },
2584         { _MMIO(0x27a8), 0x00000402 },
2585         { _MMIO(0x27ac), 0x0000fd3f },
2586 };
2587
2588 static const struct i915_oa_reg flex_eu_config_l3_3[] = {
2589         { _MMIO(0xe458), 0x00005004 },
2590         { _MMIO(0xe558), 0x00010003 },
2591         { _MMIO(0xe658), 0x00012011 },
2592         { _MMIO(0xe758), 0x00015014 },
2593         { _MMIO(0xe45c), 0x00051050 },
2594         { _MMIO(0xe55c), 0x00053052 },
2595         { _MMIO(0xe65c), 0x00055054 },
2596 };
2597
2598 static const struct i915_oa_reg mux_config_l3_3[] = {
2599         { _MMIO(0x9888), 0x121b0340 },
2600         { _MMIO(0x9888), 0x103f0274 },
2601         { _MMIO(0x9888), 0x123f0000 },
2602         { _MMIO(0x9888), 0x129b0340 },
2603         { _MMIO(0x9888), 0x10bf0274 },
2604         { _MMIO(0x9888), 0x12bf0000 },
2605         { _MMIO(0x9888), 0x041b3400 },
2606         { _MMIO(0x9888), 0x101b0000 },
2607         { _MMIO(0x9888), 0x045c8000 },
2608         { _MMIO(0x9888), 0x0a3d4000 },
2609         { _MMIO(0x9888), 0x003f0080 },
2610         { _MMIO(0x9888), 0x023f0793 },
2611         { _MMIO(0x9888), 0x043f0014 },
2612         { _MMIO(0x9888), 0x04588000 },
2613         { _MMIO(0x9888), 0x005a8000 },
2614         { _MMIO(0x9888), 0x025ac000 },
2615         { _MMIO(0x9888), 0x045a4000 },
2616         { _MMIO(0x9888), 0x0a5b4000 },
2617         { _MMIO(0x9888), 0x001d8000 },
2618         { _MMIO(0x9888), 0x021dc000 },
2619         { _MMIO(0x9888), 0x041d4000 },
2620         { _MMIO(0x9888), 0x0c1fa000 },
2621         { _MMIO(0x9888), 0x0e1f002a },
2622         { _MMIO(0x9888), 0x0a384000 },
2623         { _MMIO(0x9888), 0x00394000 },
2624         { _MMIO(0x9888), 0x02395000 },
2625         { _MMIO(0x9888), 0x04399000 },
2626         { _MMIO(0x9888), 0x069b0034 },
2627         { _MMIO(0x9888), 0x109b0000 },
2628         { _MMIO(0x9888), 0x06dc4000 },
2629         { _MMIO(0x9888), 0x0cbd4000 },
2630         { _MMIO(0x9888), 0x0cbf0981 },
2631         { _MMIO(0x9888), 0x0ebf0a0f },
2632         { _MMIO(0x9888), 0x06d84000 },
2633         { _MMIO(0x9888), 0x0cdac000 },
2634         { _MMIO(0x9888), 0x0edac000 },
2635         { _MMIO(0x9888), 0x0cdb4000 },
2636         { _MMIO(0x9888), 0x0c9dc000 },
2637         { _MMIO(0x9888), 0x0e9dc000 },
2638         { _MMIO(0x9888), 0x109f02a8 },
2639         { _MMIO(0x9888), 0x0e9f0080 },
2640         { _MMIO(0x9888), 0x0cb84000 },
2641         { _MMIO(0x9888), 0x0cb95000 },
2642         { _MMIO(0x9888), 0x0eb95000 },
2643         { _MMIO(0x9888), 0x06b92000 },
2644         { _MMIO(0x9888), 0x0f88000f },
2645         { _MMIO(0x9888), 0x0d880400 },
2646         { _MMIO(0x9888), 0x038a8000 },
2647         { _MMIO(0x9888), 0x058a8000 },
2648         { _MMIO(0x9888), 0x078a8000 },
2649         { _MMIO(0x9888), 0x098a8000 },
2650         { _MMIO(0x9888), 0x0b8a8000 },
2651         { _MMIO(0x9888), 0x258b8009 },
2652         { _MMIO(0x9888), 0x278b002a },
2653         { _MMIO(0x9888), 0x238b2a80 },
2654         { _MMIO(0x9888), 0x198c4000 },
2655         { _MMIO(0x9888), 0x1b8c0015 },
2656         { _MMIO(0x9888), 0x0d8c4000 },
2657         { _MMIO(0x9888), 0x0d8da000 },
2658         { _MMIO(0x9888), 0x0f8da000 },
2659         { _MMIO(0x9888), 0x078d2000 },
2660         { _MMIO(0x9888), 0x2185800a },
2661         { _MMIO(0x9888), 0x2385002a },
2662         { _MMIO(0x9888), 0x1f85aa00 },
2663         { _MMIO(0x9888), 0x1b830154 },
2664         { _MMIO(0x9888), 0x03834000 },
2665         { _MMIO(0x9888), 0x05834000 },
2666         { _MMIO(0x9888), 0x07834000 },
2667         { _MMIO(0x9888), 0x09834000 },
2668         { _MMIO(0x9888), 0x0b834000 },
2669         { _MMIO(0x9888), 0x0d834000 },
2670         { _MMIO(0x9888), 0x0d84c000 },
2671         { _MMIO(0x9888), 0x0f84c000 },
2672         { _MMIO(0x9888), 0x01848000 },
2673         { _MMIO(0x9888), 0x0384c000 },
2674         { _MMIO(0x9888), 0x0584c000 },
2675         { _MMIO(0x9888), 0x07844000 },
2676         { _MMIO(0x9888), 0x1d80c000 },
2677         { _MMIO(0x9888), 0x1f80c000 },
2678         { _MMIO(0x9888), 0x11808000 },
2679         { _MMIO(0x9888), 0x1380c000 },
2680         { _MMIO(0x9888), 0x1580c000 },
2681         { _MMIO(0x9888), 0x17804000 },
2682         { _MMIO(0x9888), 0x53800000 },
2683         { _MMIO(0x9888), 0x45800c00 },
2684         { _MMIO(0x9888), 0x47800c63 },
2685         { _MMIO(0x9888), 0x21800000 },
2686         { _MMIO(0x9888), 0x31800000 },
2687         { _MMIO(0x9888), 0x4d800000 },
2688         { _MMIO(0x9888), 0x3f8014a5 },
2689         { _MMIO(0x9888), 0x4f800000 },
2690         { _MMIO(0x9888), 0x41800045 },
2691 };
2692
2693 static int
2694 get_l3_3_mux_config(struct drm_i915_private *dev_priv,
2695                     const struct i915_oa_reg **regs,
2696                     int *lens)
2697 {
2698         int n = 0;
2699
2700         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2701         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2702
2703         regs[n] = mux_config_l3_3;
2704         lens[n] = ARRAY_SIZE(mux_config_l3_3);
2705         n++;
2706
2707         return n;
2708 }
2709
2710 static const struct i915_oa_reg b_counter_config_l3_4[] = {
2711         { _MMIO(0x2740), 0x00000000 },
2712         { _MMIO(0x2744), 0x00800000 },
2713         { _MMIO(0x2710), 0x00000000 },
2714         { _MMIO(0x2714), 0xf0800000 },
2715         { _MMIO(0x2720), 0x00000000 },
2716         { _MMIO(0x2724), 0xf0800000 },
2717         { _MMIO(0x2770), 0x00100070 },
2718         { _MMIO(0x2774), 0x0000fff1 },
2719         { _MMIO(0x2778), 0x00014002 },
2720         { _MMIO(0x277c), 0x0000c3ff },
2721         { _MMIO(0x2780), 0x00010002 },
2722         { _MMIO(0x2784), 0x0000c7ff },
2723         { _MMIO(0x2788), 0x00004002 },
2724         { _MMIO(0x278c), 0x0000d3ff },
2725         { _MMIO(0x2790), 0x00100700 },
2726         { _MMIO(0x2794), 0x0000ff1f },
2727         { _MMIO(0x2798), 0x00001402 },
2728         { _MMIO(0x279c), 0x0000fc3f },
2729         { _MMIO(0x27a0), 0x00001002 },
2730         { _MMIO(0x27a4), 0x0000fc7f },
2731         { _MMIO(0x27a8), 0x00000402 },
2732         { _MMIO(0x27ac), 0x0000fd3f },
2733 };
2734
2735 static const struct i915_oa_reg flex_eu_config_l3_4[] = {
2736         { _MMIO(0xe458), 0x00005004 },
2737         { _MMIO(0xe558), 0x00010003 },
2738         { _MMIO(0xe658), 0x00012011 },
2739         { _MMIO(0xe758), 0x00015014 },
2740         { _MMIO(0xe45c), 0x00051050 },
2741         { _MMIO(0xe55c), 0x00053052 },
2742         { _MMIO(0xe65c), 0x00055054 },
2743 };
2744
2745 static const struct i915_oa_reg mux_config_l3_4[] = {
2746         { _MMIO(0x9888), 0x121a0340 },
2747         { _MMIO(0x9888), 0x103f0017 },
2748         { _MMIO(0x9888), 0x123f0020 },
2749         { _MMIO(0x9888), 0x129a0340 },
2750         { _MMIO(0x9888), 0x10bf0017 },
2751         { _MMIO(0x9888), 0x12bf0020 },
2752         { _MMIO(0x9888), 0x041a3400 },
2753         { _MMIO(0x9888), 0x101a0000 },
2754         { _MMIO(0x9888), 0x043b8000 },
2755         { _MMIO(0x9888), 0x0a3e0010 },
2756         { _MMIO(0x9888), 0x003f0200 },
2757         { _MMIO(0x9888), 0x023f0113 },
2758         { _MMIO(0x9888), 0x043f0014 },
2759         { _MMIO(0x9888), 0x02592000 },
2760         { _MMIO(0x9888), 0x005a8000 },
2761         { _MMIO(0x9888), 0x025ac000 },
2762         { _MMIO(0x9888), 0x045a4000 },
2763         { _MMIO(0x9888), 0x0a1c8000 },
2764         { _MMIO(0x9888), 0x001d8000 },
2765         { _MMIO(0x9888), 0x021dc000 },
2766         { _MMIO(0x9888), 0x041d4000 },
2767         { _MMIO(0x9888), 0x0a1e8000 },
2768         { _MMIO(0x9888), 0x0c1fa000 },
2769         { _MMIO(0x9888), 0x0e1f001a },
2770         { _MMIO(0x9888), 0x00394000 },
2771         { _MMIO(0x9888), 0x02395000 },
2772         { _MMIO(0x9888), 0x04391000 },
2773         { _MMIO(0x9888), 0x069a0034 },
2774         { _MMIO(0x9888), 0x109a0000 },
2775         { _MMIO(0x9888), 0x06bb4000 },
2776         { _MMIO(0x9888), 0x0abe0040 },
2777         { _MMIO(0x9888), 0x0cbf0984 },
2778         { _MMIO(0x9888), 0x0ebf0a02 },
2779         { _MMIO(0x9888), 0x02d94000 },
2780         { _MMIO(0x9888), 0x0cdac000 },
2781         { _MMIO(0x9888), 0x0edac000 },
2782         { _MMIO(0x9888), 0x0c9c0400 },
2783         { _MMIO(0x9888), 0x0c9dc000 },
2784         { _MMIO(0x9888), 0x0e9dc000 },
2785         { _MMIO(0x9888), 0x0c9e0400 },
2786         { _MMIO(0x9888), 0x109f02a8 },
2787         { _MMIO(0x9888), 0x0e9f0040 },
2788         { _MMIO(0x9888), 0x0cb95000 },
2789         { _MMIO(0x9888), 0x0eb95000 },
2790         { _MMIO(0x9888), 0x0f88000f },
2791         { _MMIO(0x9888), 0x0d880400 },
2792         { _MMIO(0x9888), 0x038a8000 },
2793         { _MMIO(0x9888), 0x058a8000 },
2794         { _MMIO(0x9888), 0x078a8000 },
2795         { _MMIO(0x9888), 0x098a8000 },
2796         { _MMIO(0x9888), 0x0b8a8000 },
2797         { _MMIO(0x9888), 0x258b8009 },
2798         { _MMIO(0x9888), 0x278b002a },
2799         { _MMIO(0x9888), 0x238b2a80 },
2800         { _MMIO(0x9888), 0x198c4000 },
2801         { _MMIO(0x9888), 0x1b8c0015 },
2802         { _MMIO(0x9888), 0x0d8c4000 },
2803         { _MMIO(0x9888), 0x0d8da000 },
2804         { _MMIO(0x9888), 0x0f8da000 },
2805         { _MMIO(0x9888), 0x078d2000 },
2806         { _MMIO(0x9888), 0x2185800a },
2807         { _MMIO(0x9888), 0x2385002a },
2808         { _MMIO(0x9888), 0x1f85aa00 },
2809         { _MMIO(0x9888), 0x1b830154 },
2810         { _MMIO(0x9888), 0x03834000 },
2811         { _MMIO(0x9888), 0x05834000 },
2812         { _MMIO(0x9888), 0x07834000 },
2813         { _MMIO(0x9888), 0x09834000 },
2814         { _MMIO(0x9888), 0x0b834000 },
2815         { _MMIO(0x9888), 0x0d834000 },
2816         { _MMIO(0x9888), 0x0d84c000 },
2817         { _MMIO(0x9888), 0x0f84c000 },
2818         { _MMIO(0x9888), 0x01848000 },
2819         { _MMIO(0x9888), 0x0384c000 },
2820         { _MMIO(0x9888), 0x0584c000 },
2821         { _MMIO(0x9888), 0x07844000 },
2822         { _MMIO(0x9888), 0x1d80c000 },
2823         { _MMIO(0x9888), 0x1f80c000 },
2824         { _MMIO(0x9888), 0x11808000 },
2825         { _MMIO(0x9888), 0x1380c000 },
2826         { _MMIO(0x9888), 0x1580c000 },
2827         { _MMIO(0x9888), 0x17804000 },
2828         { _MMIO(0x9888), 0x53800000 },
2829         { _MMIO(0x9888), 0x45800800 },
2830         { _MMIO(0x9888), 0x47800842 },
2831         { _MMIO(0x9888), 0x21800000 },
2832         { _MMIO(0x9888), 0x31800000 },
2833         { _MMIO(0x9888), 0x4d800000 },
2834         { _MMIO(0x9888), 0x3f801084 },
2835         { _MMIO(0x9888), 0x4f800000 },
2836         { _MMIO(0x9888), 0x41800044 },
2837 };
2838
2839 static int
2840 get_l3_4_mux_config(struct drm_i915_private *dev_priv,
2841                     const struct i915_oa_reg **regs,
2842                     int *lens)
2843 {
2844         int n = 0;
2845
2846         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2847         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2848
2849         regs[n] = mux_config_l3_4;
2850         lens[n] = ARRAY_SIZE(mux_config_l3_4);
2851         n++;
2852
2853         return n;
2854 }
2855
2856 static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
2857         { _MMIO(0x2740), 0x00000000 },
2858         { _MMIO(0x2744), 0x00800000 },
2859         { _MMIO(0x2710), 0x00000000 },
2860         { _MMIO(0x2714), 0xf0800000 },
2861         { _MMIO(0x2720), 0x00000000 },
2862         { _MMIO(0x2724), 0x30800000 },
2863         { _MMIO(0x2770), 0x00006000 },
2864         { _MMIO(0x2774), 0x0000f3ff },
2865         { _MMIO(0x2778), 0x00001800 },
2866         { _MMIO(0x277c), 0x0000fcff },
2867         { _MMIO(0x2780), 0x00000600 },
2868         { _MMIO(0x2784), 0x0000ff3f },
2869         { _MMIO(0x2788), 0x00000180 },
2870         { _MMIO(0x278c), 0x0000ffcf },
2871         { _MMIO(0x2790), 0x00000060 },
2872         { _MMIO(0x2794), 0x0000fff3 },
2873         { _MMIO(0x2798), 0x00000018 },
2874         { _MMIO(0x279c), 0x0000fffc },
2875 };
2876
2877 static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
2878         { _MMIO(0xe458), 0x00005004 },
2879         { _MMIO(0xe558), 0x00010003 },
2880         { _MMIO(0xe658), 0x00012011 },
2881         { _MMIO(0xe758), 0x00015014 },
2882         { _MMIO(0xe45c), 0x00051050 },
2883         { _MMIO(0xe55c), 0x00053052 },
2884         { _MMIO(0xe65c), 0x00055054 },
2885 };
2886
2887 static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
2888         { _MMIO(0x9888), 0x143b000e },
2889         { _MMIO(0x9888), 0x043c55c0 },
2890         { _MMIO(0x9888), 0x0a1e0280 },
2891         { _MMIO(0x9888), 0x0c1e0408 },
2892         { _MMIO(0x9888), 0x10390000 },
2893         { _MMIO(0x9888), 0x12397a1f },
2894         { _MMIO(0x9888), 0x14bb000e },
2895         { _MMIO(0x9888), 0x04bc5000 },
2896         { _MMIO(0x9888), 0x0a9e0296 },
2897         { _MMIO(0x9888), 0x0c9e0008 },
2898         { _MMIO(0x9888), 0x10b90000 },
2899         { _MMIO(0x9888), 0x12b97a1f },
2900         { _MMIO(0x9888), 0x063b0042 },
2901         { _MMIO(0x9888), 0x103b0000 },
2902         { _MMIO(0x9888), 0x083c0000 },
2903         { _MMIO(0x9888), 0x0a3e0040 },
2904         { _MMIO(0x9888), 0x043f8000 },
2905         { _MMIO(0x9888), 0x02594000 },
2906         { _MMIO(0x9888), 0x045a8000 },
2907         { _MMIO(0x9888), 0x0c1c0400 },
2908         { _MMIO(0x9888), 0x041d8000 },
2909         { _MMIO(0x9888), 0x081e02c0 },
2910         { _MMIO(0x9888), 0x0e1e0000 },
2911         { _MMIO(0x9888), 0x0c1fa800 },
2912         { _MMIO(0x9888), 0x0e1f0260 },
2913         { _MMIO(0x9888), 0x101f0014 },
2914         { _MMIO(0x9888), 0x003905e0 },
2915         { _MMIO(0x9888), 0x06390bc0 },
2916         { _MMIO(0x9888), 0x02390018 },
2917         { _MMIO(0x9888), 0x04394000 },
2918         { _MMIO(0x9888), 0x04bb0042 },
2919         { _MMIO(0x9888), 0x10bb0000 },
2920         { _MMIO(0x9888), 0x02bc05c0 },
2921         { _MMIO(0x9888), 0x08bc0000 },
2922         { _MMIO(0x9888), 0x0abe0004 },
2923         { _MMIO(0x9888), 0x02bf8000 },
2924         { _MMIO(0x9888), 0x02d91000 },
2925         { _MMIO(0x9888), 0x02da8000 },
2926         { _MMIO(0x9888), 0x089c8000 },
2927         { _MMIO(0x9888), 0x029d8000 },
2928         { _MMIO(0x9888), 0x089e8000 },
2929         { _MMIO(0x9888), 0x0e9e0000 },
2930         { _MMIO(0x9888), 0x0e9fa806 },
2931         { _MMIO(0x9888), 0x109f0142 },
2932         { _MMIO(0x9888), 0x08b90617 },
2933         { _MMIO(0x9888), 0x0ab90be0 },
2934         { _MMIO(0x9888), 0x02b94000 },
2935         { _MMIO(0x9888), 0x0d88f000 },
2936         { _MMIO(0x9888), 0x0f88000c },
2937         { _MMIO(0x9888), 0x07888000 },
2938         { _MMIO(0x9888), 0x09888000 },
2939         { _MMIO(0x9888), 0x018a8000 },
2940         { _MMIO(0x9888), 0x0f8a8000 },
2941         { _MMIO(0x9888), 0x1b8a2800 },
2942         { _MMIO(0x9888), 0x038a8000 },
2943         { _MMIO(0x9888), 0x058a8000 },
2944         { _MMIO(0x9888), 0x0b8a8000 },
2945         { _MMIO(0x9888), 0x0d8a8000 },
2946         { _MMIO(0x9888), 0x238b52a0 },
2947         { _MMIO(0x9888), 0x258b6a95 },
2948         { _MMIO(0x9888), 0x278b0029 },
2949         { _MMIO(0x9888), 0x178c2000 },
2950         { _MMIO(0x9888), 0x198c1500 },
2951         { _MMIO(0x9888), 0x1b8c0014 },
2952         { _MMIO(0x9888), 0x078c4000 },
2953         { _MMIO(0x9888), 0x098c4000 },
2954         { _MMIO(0x9888), 0x098da000 },
2955         { _MMIO(0x9888), 0x0b8da000 },
2956         { _MMIO(0x9888), 0x0f8da000 },
2957         { _MMIO(0x9888), 0x038d8000 },
2958         { _MMIO(0x9888), 0x058d2000 },
2959         { _MMIO(0x9888), 0x1f85aa80 },
2960         { _MMIO(0x9888), 0x2185aaaa },
2961         { _MMIO(0x9888), 0x2385002a },
2962         { _MMIO(0x9888), 0x01834000 },
2963         { _MMIO(0x9888), 0x0f834000 },
2964         { _MMIO(0x9888), 0x19835400 },
2965         { _MMIO(0x9888), 0x1b830155 },
2966         { _MMIO(0x9888), 0x03834000 },
2967         { _MMIO(0x9888), 0x05834000 },
2968         { _MMIO(0x9888), 0x07834000 },
2969         { _MMIO(0x9888), 0x09834000 },
2970         { _MMIO(0x9888), 0x0b834000 },
2971         { _MMIO(0x9888), 0x0d834000 },
2972         { _MMIO(0x9888), 0x0184c000 },
2973         { _MMIO(0x9888), 0x0784c000 },
2974         { _MMIO(0x9888), 0x0984c000 },
2975         { _MMIO(0x9888), 0x0b84c000 },
2976         { _MMIO(0x9888), 0x0d84c000 },
2977         { _MMIO(0x9888), 0x0f84c000 },
2978         { _MMIO(0x9888), 0x0384c000 },
2979         { _MMIO(0x9888), 0x0584c000 },
2980         { _MMIO(0x9888), 0x1180c000 },
2981         { _MMIO(0x9888), 0x1780c000 },
2982         { _MMIO(0x9888), 0x1980c000 },
2983         { _MMIO(0x9888), 0x1b80c000 },
2984         { _MMIO(0x9888), 0x1d80c000 },
2985         { _MMIO(0x9888), 0x1f80c000 },
2986         { _MMIO(0x9888), 0x1380c000 },
2987         { _MMIO(0x9888), 0x1580c000 },
2988         { _MMIO(0x9888), 0x4d800444 },
2989         { _MMIO(0x9888), 0x3d800000 },
2990         { _MMIO(0x9888), 0x4f804000 },
2991         { _MMIO(0x9888), 0x43801080 },
2992         { _MMIO(0x9888), 0x51800000 },
2993         { _MMIO(0x9888), 0x45800084 },
2994         { _MMIO(0x9888), 0x53800044 },
2995         { _MMIO(0x9888), 0x47801080 },
2996         { _MMIO(0x9888), 0x21800000 },
2997         { _MMIO(0x9888), 0x31800000 },
2998         { _MMIO(0x9888), 0x3f800000 },
2999         { _MMIO(0x9888), 0x41800840 },
3000 };
3001
3002 static int
3003 get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
3004                                             const struct i915_oa_reg **regs,
3005                                             int *lens)
3006 {
3007         int n = 0;
3008
3009         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
3010         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
3011
3012         regs[n] = mux_config_rasterizer_and_pixel_backend;
3013         lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
3014         n++;
3015
3016         return n;
3017 }
3018
3019 static const struct i915_oa_reg b_counter_config_sampler_1[] = {
3020         { _MMIO(0x2740), 0x00000000 },
3021         { _MMIO(0x2744), 0x00800000 },
3022         { _MMIO(0x2710), 0x00000000 },
3023         { _MMIO(0x2714), 0x70800000 },
3024         { _MMIO(0x2720), 0x00000000 },
3025         { _MMIO(0x2724), 0x00800000 },
3026         { _MMIO(0x2770), 0x0000c000 },
3027         { _MMIO(0x2774), 0x0000e7ff },
3028         { _MMIO(0x2778), 0x00003000 },
3029         { _MMIO(0x277c), 0x0000f9ff },
3030         { _MMIO(0x2780), 0x00000c00 },
3031         { _MMIO(0x2784), 0x0000fe7f },
3032 };
3033
3034 static const struct i915_oa_reg flex_eu_config_sampler_1[] = {
3035         { _MMIO(0xe458), 0x00005004 },
3036         { _MMIO(0xe558), 0x00010003 },
3037         { _MMIO(0xe658), 0x00012011 },
3038         { _MMIO(0xe758), 0x00015014 },
3039         { _MMIO(0xe45c), 0x00051050 },
3040         { _MMIO(0xe55c), 0x00053052 },
3041         { _MMIO(0xe65c), 0x00055054 },
3042 };
3043
3044 static const struct i915_oa_reg mux_config_sampler_1[] = {
3045         { _MMIO(0x9888), 0x18921400 },
3046         { _MMIO(0x9888), 0x149500ab },
3047         { _MMIO(0x9888), 0x18b21400 },
3048         { _MMIO(0x9888), 0x14b500ab },
3049         { _MMIO(0x9888), 0x18d21400 },
3050         { _MMIO(0x9888), 0x14d500ab },
3051         { _MMIO(0x9888), 0x0cdc8000 },
3052         { _MMIO(0x9888), 0x0edc4000 },
3053         { _MMIO(0x9888), 0x02dcc000 },
3054         { _MMIO(0x9888), 0x04dcc000 },
3055         { _MMIO(0x9888), 0x1abd00a0 },
3056         { _MMIO(0x9888), 0x0abd8000 },
3057         { _MMIO(0x9888), 0x0cd88000 },
3058         { _MMIO(0x9888), 0x0ed84000 },
3059         { _MMIO(0x9888), 0x04d88000 },
3060         { _MMIO(0x9888), 0x1adb0050 },
3061         { _MMIO(0x9888), 0x04db8000 },
3062         { _MMIO(0x9888), 0x06db8000 },
3063         { _MMIO(0x9888), 0x08db8000 },
3064         { _MMIO(0x9888), 0x0adb4000 },
3065         { _MMIO(0x9888), 0x109f02a0 },
3066         { _MMIO(0x9888), 0x0c9fa000 },
3067         { _MMIO(0x9888), 0x0e9f00aa },
3068         { _MMIO(0x9888), 0x18b82500 },
3069         { _MMIO(0x9888), 0x02b88000 },
3070         { _MMIO(0x9888), 0x04b84000 },
3071         { _MMIO(0x9888), 0x06b84000 },
3072         { _MMIO(0x9888), 0x08b84000 },
3073         { _MMIO(0x9888), 0x0ab84000 },
3074         { _MMIO(0x9888), 0x0cb88000 },
3075         { _MMIO(0x9888), 0x0cb98000 },
3076         { _MMIO(0x9888), 0x0eb9a000 },
3077         { _MMIO(0x9888), 0x00b98000 },
3078         { _MMIO(0x9888), 0x02b9a000 },
3079         { _MMIO(0x9888), 0x04b9a000 },
3080         { _MMIO(0x9888), 0x06b92000 },
3081         { _MMIO(0x9888), 0x1aba0200 },
3082         { _MMIO(0x9888), 0x02ba8000 },
3083         { _MMIO(0x9888), 0x0cba8000 },
3084         { _MMIO(0x9888), 0x04908000 },
3085         { _MMIO(0x9888), 0x04918000 },
3086         { _MMIO(0x9888), 0x04927300 },
3087         { _MMIO(0x9888), 0x10920000 },
3088         { _MMIO(0x9888), 0x1893000a },
3089         { _MMIO(0x9888), 0x0a934000 },
3090         { _MMIO(0x9888), 0x0a946000 },
3091         { _MMIO(0x9888), 0x0c959000 },
3092         { _MMIO(0x9888), 0x0e950098 },
3093         { _MMIO(0x9888), 0x10950000 },
3094         { _MMIO(0x9888), 0x04b04000 },
3095         { _MMIO(0x9888), 0x04b14000 },
3096         { _MMIO(0x9888), 0x04b20073 },
3097         { _MMIO(0x9888), 0x10b20000 },
3098         { _MMIO(0x9888), 0x04b38000 },
3099         { _MMIO(0x9888), 0x06b38000 },
3100         { _MMIO(0x9888), 0x08b34000 },
3101         { _MMIO(0x9888), 0x04b4c000 },
3102         { _MMIO(0x9888), 0x02b59890 },
3103         { _MMIO(0x9888), 0x10b50000 },
3104         { _MMIO(0x9888), 0x06d04000 },
3105         { _MMIO(0x9888), 0x06d14000 },
3106         { _MMIO(0x9888), 0x06d20073 },
3107         { _MMIO(0x9888), 0x10d20000 },
3108         { _MMIO(0x9888), 0x18d30020 },
3109         { _MMIO(0x9888), 0x02d38000 },
3110         { _MMIO(0x9888), 0x0cd34000 },
3111         { _MMIO(0x9888), 0x0ad48000 },
3112         { _MMIO(0x9888), 0x04d42000 },
3113         { _MMIO(0x9888), 0x0ed59000 },
3114         { _MMIO(0x9888), 0x00d59800 },
3115         { _MMIO(0x9888), 0x10d50000 },
3116         { _MMIO(0x9888), 0x0f88000e },
3117         { _MMIO(0x9888), 0x03888000 },
3118         { _MMIO(0x9888), 0x05888000 },
3119         { _MMIO(0x9888), 0x07888000 },
3120         { _MMIO(0x9888), 0x09888000 },
3121         { _MMIO(0x9888), 0x0b888000 },
3122         { _MMIO(0x9888), 0x0d880400 },
3123         { _MMIO(0x9888), 0x278b002a },
3124         { _MMIO(0x9888), 0x238b5500 },
3125         { _MMIO(0x9888), 0x258b000a },
3126         { _MMIO(0x9888), 0x1b8c0015 },
3127         { _MMIO(0x9888), 0x038c4000 },
3128         { _MMIO(0x9888), 0x058c4000 },
3129         { _MMIO(0x9888), 0x078c4000 },
3130         { _MMIO(0x9888), 0x098c4000 },
3131         { _MMIO(0x9888), 0x0b8c4000 },
3132         { _MMIO(0x9888), 0x0d8c4000 },
3133         { _MMIO(0x9888), 0x0d8d8000 },
3134         { _MMIO(0x9888), 0x0f8da000 },
3135         { _MMIO(0x9888), 0x018d8000 },
3136         { _MMIO(0x9888), 0x038da000 },
3137         { _MMIO(0x9888), 0x058da000 },
3138         { _MMIO(0x9888), 0x078d2000 },
3139         { _MMIO(0x9888), 0x2385002a },
3140         { _MMIO(0x9888), 0x1f85aa00 },
3141         { _MMIO(0x9888), 0x2185000a },
3142         { _MMIO(0x9888), 0x1b830150 },
3143         { _MMIO(0x9888), 0x03834000 },
3144         { _MMIO(0x9888), 0x05834000 },
3145         { _MMIO(0x9888), 0x07834000 },
3146         { _MMIO(0x9888), 0x09834000 },
3147         { _MMIO(0x9888), 0x0b834000 },
3148         { _MMIO(0x9888), 0x0d834000 },
3149         { _MMIO(0x9888), 0x0d848000 },
3150         { _MMIO(0x9888), 0x0f84c000 },
3151         { _MMIO(0x9888), 0x01848000 },
3152         { _MMIO(0x9888), 0x0384c000 },
3153         { _MMIO(0x9888), 0x0584c000 },
3154         { _MMIO(0x9888), 0x07844000 },
3155         { _MMIO(0x9888), 0x1d808000 },
3156         { _MMIO(0x9888), 0x1f80c000 },
3157         { _MMIO(0x9888), 0x11808000 },
3158         { _MMIO(0x9888), 0x1380c000 },
3159         { _MMIO(0x9888), 0x1580c000 },
3160         { _MMIO(0x9888), 0x17804000 },
3161         { _MMIO(0x9888), 0x53800000 },
3162         { _MMIO(0x9888), 0x47801021 },
3163         { _MMIO(0x9888), 0x21800000 },
3164         { _MMIO(0x9888), 0x31800000 },
3165         { _MMIO(0x9888), 0x4d800000 },
3166         { _MMIO(0x9888), 0x3f800c64 },
3167         { _MMIO(0x9888), 0x4f800000 },
3168         { _MMIO(0x9888), 0x41800c02 },
3169 };
3170
3171 static int
3172 get_sampler_1_mux_config(struct drm_i915_private *dev_priv,
3173                          const struct i915_oa_reg **regs,
3174                          int *lens)
3175 {
3176         int n = 0;
3177
3178         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
3179         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
3180
3181         regs[n] = mux_config_sampler_1;
3182         lens[n] = ARRAY_SIZE(mux_config_sampler_1);
3183         n++;
3184
3185         return n;
3186 }
3187
3188 static const struct i915_oa_reg b_counter_config_sampler_2[] = {
3189         { _MMIO(0x2740), 0x00000000 },
3190         { _MMIO(0x2744), 0x00800000 },
3191         { _MMIO(0x2710), 0x00000000 },
3192         { _MMIO(0x2714), 0x70800000 },
3193         { _MMIO(0x2720), 0x00000000 },
3194         { _MMIO(0x2724), 0x00800000 },
3195         { _MMIO(0x2770), 0x0000c000 },
3196         { _MMIO(0x2774), 0x0000e7ff },
3197         { _MMIO(0x2778), 0x00003000 },
3198         { _MMIO(0x277c), 0x0000f9ff },
3199         { _MMIO(0x2780), 0x00000c00 },
3200         { _MMIO(0x2784), 0x0000fe7f },
3201 };
3202
3203 static const struct i915_oa_reg flex_eu_config_sampler_2[] = {
3204         { _MMIO(0xe458), 0x00005004 },
3205         { _MMIO(0xe558), 0x00010003 },
3206         { _MMIO(0xe658), 0x00012011 },
3207         { _MMIO(0xe758), 0x00015014 },
3208         { _MMIO(0xe45c), 0x00051050 },
3209         { _MMIO(0xe55c), 0x00053052 },
3210         { _MMIO(0xe65c), 0x00055054 },
3211 };
3212
3213 static const struct i915_oa_reg mux_config_sampler_2[] = {
3214         { _MMIO(0x9888), 0x18121400 },
3215         { _MMIO(0x9888), 0x141500ab },
3216         { _MMIO(0x9888), 0x18321400 },
3217         { _MMIO(0x9888), 0x143500ab },
3218         { _MMIO(0x9888), 0x18521400 },
3219         { _MMIO(0x9888), 0x145500ab },
3220         { _MMIO(0x9888), 0x0c5c8000 },
3221         { _MMIO(0x9888), 0x0e5c4000 },
3222         { _MMIO(0x9888), 0x025cc000 },
3223         { _MMIO(0x9888), 0x045cc000 },
3224         { _MMIO(0x9888), 0x1a3d00a0 },
3225         { _MMIO(0x9888), 0x0a3d8000 },
3226         { _MMIO(0x9888), 0x0c588000 },
3227         { _MMIO(0x9888), 0x0e584000 },
3228         { _MMIO(0x9888), 0x04588000 },
3229         { _MMIO(0x9888), 0x1a5b0050 },
3230         { _MMIO(0x9888), 0x045b8000 },
3231         { _MMIO(0x9888), 0x065b8000 },
3232         { _MMIO(0x9888), 0x085b8000 },
3233         { _MMIO(0x9888), 0x0a5b4000 },
3234         { _MMIO(0x9888), 0x101f02a0 },
3235         { _MMIO(0x9888), 0x0c1fa000 },
3236         { _MMIO(0x9888), 0x0e1f00aa },
3237         { _MMIO(0x9888), 0x18382500 },
3238         { _MMIO(0x9888), 0x02388000 },
3239         { _MMIO(0x9888), 0x04384000 },
3240         { _MMIO(0x9888), 0x06384000 },
3241         { _MMIO(0x9888), 0x08384000 },
3242         { _MMIO(0x9888), 0x0a384000 },
3243         { _MMIO(0x9888), 0x0c388000 },
3244         { _MMIO(0x9888), 0x0c398000 },
3245         { _MMIO(0x9888), 0x0e39a000 },
3246         { _MMIO(0x9888), 0x00398000 },
3247         { _MMIO(0x9888), 0x0239a000 },
3248         { _MMIO(0x9888), 0x0439a000 },
3249         { _MMIO(0x9888), 0x06392000 },
3250         { _MMIO(0x9888), 0x1a3a0200 },
3251         { _MMIO(0x9888), 0x023a8000 },
3252         { _MMIO(0x9888), 0x0c3a8000 },
3253         { _MMIO(0x9888), 0x04108000 },
3254         { _MMIO(0x9888), 0x04118000 },
3255         { _MMIO(0x9888), 0x04127300 },
3256         { _MMIO(0x9888), 0x10120000 },
3257         { _MMIO(0x9888), 0x1813000a },
3258         { _MMIO(0x9888), 0x0a134000 },
3259         { _MMIO(0x9888), 0x0a146000 },
3260         { _MMIO(0x9888), 0x0c159000 },
3261         { _MMIO(0x9888), 0x0e150098 },
3262         { _MMIO(0x9888), 0x10150000 },
3263         { _MMIO(0x9888), 0x04304000 },
3264         { _MMIO(0x9888), 0x04314000 },
3265         { _MMIO(0x9888), 0x04320073 },
3266         { _MMIO(0x9888), 0x10320000 },
3267         { _MMIO(0x9888), 0x04338000 },
3268         { _MMIO(0x9888), 0x06338000 },
3269         { _MMIO(0x9888), 0x08334000 },
3270         { _MMIO(0x9888), 0x0434c000 },
3271         { _MMIO(0x9888), 0x02359890 },
3272         { _MMIO(0x9888), 0x10350000 },
3273         { _MMIO(0x9888), 0x06504000 },
3274         { _MMIO(0x9888), 0x06514000 },
3275         { _MMIO(0x9888), 0x06520073 },
3276         { _MMIO(0x9888), 0x10520000 },
3277         { _MMIO(0x9888), 0x18530020 },
3278         { _MMIO(0x9888), 0x02538000 },
3279         { _MMIO(0x9888), 0x0c534000 },
3280         { _MMIO(0x9888), 0x0a548000 },
3281         { _MMIO(0x9888), 0x04542000 },
3282         { _MMIO(0x9888), 0x0e559000 },
3283         { _MMIO(0x9888), 0x00559800 },
3284         { _MMIO(0x9888), 0x10550000 },
3285         { _MMIO(0x9888), 0x1b8aa000 },
3286         { _MMIO(0x9888), 0x1d8a0002 },
3287         { _MMIO(0x9888), 0x038a8000 },
3288         { _MMIO(0x9888), 0x058a8000 },
3289         { _MMIO(0x9888), 0x078a8000 },
3290         { _MMIO(0x9888), 0x098a8000 },
3291         { _MMIO(0x9888), 0x0b8a8000 },
3292         { _MMIO(0x9888), 0x0d8a8000 },
3293         { _MMIO(0x9888), 0x278b0015 },
3294         { _MMIO(0x9888), 0x238b2a80 },
3295         { _MMIO(0x9888), 0x258b0005 },
3296         { _MMIO(0x9888), 0x2385002a },
3297         { _MMIO(0x9888), 0x1f85aa00 },
3298         { _MMIO(0x9888), 0x2185000a },
3299         { _MMIO(0x9888), 0x1b830150 },
3300         { _MMIO(0x9888), 0x03834000 },
3301         { _MMIO(0x9888), 0x05834000 },
3302         { _MMIO(0x9888), 0x07834000 },
3303         { _MMIO(0x9888), 0x09834000 },
3304         { _MMIO(0x9888), 0x0b834000 },
3305         { _MMIO(0x9888), 0x0d834000 },
3306         { _MMIO(0x9888), 0x0d848000 },
3307         { _MMIO(0x9888), 0x0f84c000 },
3308         { _MMIO(0x9888), 0x01848000 },
3309         { _MMIO(0x9888), 0x0384c000 },
3310         { _MMIO(0x9888), 0x0584c000 },
3311         { _MMIO(0x9888), 0x07844000 },
3312         { _MMIO(0x9888), 0x1d808000 },
3313         { _MMIO(0x9888), 0x1f80c000 },
3314         { _MMIO(0x9888), 0x11808000 },
3315         { _MMIO(0x9888), 0x1380c000 },
3316         { _MMIO(0x9888), 0x1580c000 },
3317         { _MMIO(0x9888), 0x17804000 },
3318         { _MMIO(0x9888), 0x53800000 },
3319         { _MMIO(0x9888), 0x47801021 },
3320         { _MMIO(0x9888), 0x21800000 },
3321         { _MMIO(0x9888), 0x31800000 },
3322         { _MMIO(0x9888), 0x4d800000 },
3323         { _MMIO(0x9888), 0x3f800c64 },
3324         { _MMIO(0x9888), 0x4f800000 },
3325         { _MMIO(0x9888), 0x41800c02 },
3326 };
3327
3328 static int
3329 get_sampler_2_mux_config(struct drm_i915_private *dev_priv,
3330                          const struct i915_oa_reg **regs,
3331                          int *lens)
3332 {
3333         int n = 0;
3334
3335         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
3336         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
3337
3338         regs[n] = mux_config_sampler_2;
3339         lens[n] = ARRAY_SIZE(mux_config_sampler_2);
3340         n++;
3341
3342         return n;
3343 }
3344
3345 static const struct i915_oa_reg b_counter_config_tdl_1[] = {
3346         { _MMIO(0x2740), 0x00000000 },
3347         { _MMIO(0x2744), 0x00800000 },
3348         { _MMIO(0x2710), 0x00000000 },
3349         { _MMIO(0x2714), 0xf0800000 },
3350         { _MMIO(0x2720), 0x00000000 },
3351         { _MMIO(0x2724), 0x30800000 },
3352         { _MMIO(0x2770), 0x00000002 },
3353         { _MMIO(0x2774), 0x0000fdff },
3354         { _MMIO(0x2778), 0x00000000 },
3355         { _MMIO(0x277c), 0x0000fe7f },
3356         { _MMIO(0x2780), 0x00000002 },
3357         { _MMIO(0x2784), 0x0000ffbf },
3358         { _MMIO(0x2788), 0x00000000 },
3359         { _MMIO(0x278c), 0x0000ffcf },
3360         { _MMIO(0x2790), 0x00000002 },
3361         { _MMIO(0x2794), 0x0000fff7 },
3362         { _MMIO(0x2798), 0x00000000 },
3363         { _MMIO(0x279c), 0x0000fff9 },
3364 };
3365
3366 static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
3367         { _MMIO(0xe458), 0x00005004 },
3368         { _MMIO(0xe558), 0x00010003 },
3369         { _MMIO(0xe658), 0x00012011 },
3370         { _MMIO(0xe758), 0x00015014 },
3371         { _MMIO(0xe45c), 0x00051050 },
3372         { _MMIO(0xe55c), 0x00053052 },
3373         { _MMIO(0xe65c), 0x00055054 },
3374 };
3375
3376 static const struct i915_oa_reg mux_config_tdl_1[] = {
3377         { _MMIO(0x9888), 0x16154d60 },
3378         { _MMIO(0x9888), 0x16352e60 },
3379         { _MMIO(0x9888), 0x16554d60 },
3380         { _MMIO(0x9888), 0x16950000 },
3381         { _MMIO(0x9888), 0x16b50000 },
3382         { _MMIO(0x9888), 0x16d50000 },
3383         { _MMIO(0x9888), 0x005c8000 },
3384         { _MMIO(0x9888), 0x045cc000 },
3385         { _MMIO(0x9888), 0x065c4000 },
3386         { _MMIO(0x9888), 0x083d8000 },
3387         { _MMIO(0x9888), 0x0a3d8000 },
3388         { _MMIO(0x9888), 0x0458c000 },
3389         { _MMIO(0x9888), 0x025b8000 },
3390         { _MMIO(0x9888), 0x085b4000 },
3391         { _MMIO(0x9888), 0x0a5b4000 },
3392         { _MMIO(0x9888), 0x0c5b8000 },
3393         { _MMIO(0x9888), 0x0c1fa000 },
3394         { _MMIO(0x9888), 0x0e1f00aa },
3395         { _MMIO(0x9888), 0x02384000 },
3396         { _MMIO(0x9888), 0x04388000 },
3397         { _MMIO(0x9888), 0x06388000 },
3398         { _MMIO(0x9888), 0x08384000 },
3399         { _MMIO(0x9888), 0x0a384000 },
3400         { _MMIO(0x9888), 0x0c384000 },
3401         { _MMIO(0x9888), 0x00398000 },
3402         { _MMIO(0x9888), 0x0239a000 },
3403         { _MMIO(0x9888), 0x0439a000 },
3404         { _MMIO(0x9888), 0x06392000 },
3405         { _MMIO(0x9888), 0x043a8000 },
3406         { _MMIO(0x9888), 0x063a8000 },
3407         { _MMIO(0x9888), 0x08138000 },
3408         { _MMIO(0x9888), 0x0a138000 },
3409         { _MMIO(0x9888), 0x06143000 },
3410         { _MMIO(0x9888), 0x0415cfc7 },
3411         { _MMIO(0x9888), 0x10150000 },
3412         { _MMIO(0x9888), 0x02338000 },
3413         { _MMIO(0x9888), 0x0c338000 },
3414         { _MMIO(0x9888), 0x04342000 },
3415         { _MMIO(0x9888), 0x06344000 },
3416         { _MMIO(0x9888), 0x0035c700 },
3417         { _MMIO(0x9888), 0x063500cf },
3418         { _MMIO(0x9888), 0x10350000 },
3419         { _MMIO(0x9888), 0x04538000 },
3420         { _MMIO(0x9888), 0x06538000 },
3421         { _MMIO(0x9888), 0x0454c000 },
3422         { _MMIO(0x9888), 0x0255cfc7 },
3423         { _MMIO(0x9888), 0x10550000 },
3424         { _MMIO(0x9888), 0x06dc8000 },
3425         { _MMIO(0x9888), 0x08dc4000 },
3426         { _MMIO(0x9888), 0x0cdcc000 },
3427         { _MMIO(0x9888), 0x0edcc000 },
3428         { _MMIO(0x9888), 0x1abd00a8 },
3429         { _MMIO(0x9888), 0x0cd8c000 },
3430         { _MMIO(0x9888), 0x0ed84000 },
3431         { _MMIO(0x9888), 0x0edb8000 },
3432         { _MMIO(0x9888), 0x18db0800 },
3433         { _MMIO(0x9888), 0x1adb0254 },
3434         { _MMIO(0x9888), 0x0e9faa00 },
3435         { _MMIO(0x9888), 0x109f02aa },
3436         { _MMIO(0x9888), 0x0eb84000 },
3437         { _MMIO(0x9888), 0x16b84000 },
3438         { _MMIO(0x9888), 0x18b8156a },
3439         { _MMIO(0x9888), 0x06b98000 },
3440         { _MMIO(0x9888), 0x08b9a000 },
3441         { _MMIO(0x9888), 0x0ab9a000 },
3442         { _MMIO(0x9888), 0x0cb9a000 },
3443         { _MMIO(0x9888), 0x0eb9a000 },
3444         { _MMIO(0x9888), 0x18baa000 },
3445         { _MMIO(0x9888), 0x1aba0002 },
3446         { _MMIO(0x9888), 0x16934000 },
3447         { _MMIO(0x9888), 0x1893000a },
3448         { _MMIO(0x9888), 0x0a947000 },
3449         { _MMIO(0x9888), 0x0c95c5c1 },
3450         { _MMIO(0x9888), 0x0e9500c3 },
3451         { _MMIO(0x9888), 0x10950000 },
3452         { _MMIO(0x9888), 0x0eb38000 },
3453         { _MMIO(0x9888), 0x16b30040 },
3454         { _MMIO(0x9888), 0x18b30020 },
3455         { _MMIO(0x9888), 0x06b48000 },
3456         { _MMIO(0x9888), 0x08b41000 },
3457         { _MMIO(0x9888), 0x0ab48000 },
3458         { _MMIO(0x9888), 0x06b5c500 },
3459         { _MMIO(0x9888), 0x08b500c3 },
3460         { _MMIO(0x9888), 0x0eb5c100 },
3461         { _MMIO(0x9888), 0x10b50000 },
3462         { _MMIO(0x9888), 0x16d31500 },
3463         { _MMIO(0x9888), 0x08d4e000 },
3464         { _MMIO(0x9888), 0x08d5c100 },
3465         { _MMIO(0x9888), 0x0ad5c3c5 },
3466         { _MMIO(0x9888), 0x10d50000 },
3467         { _MMIO(0x9888), 0x0d88f800 },
3468         { _MMIO(0x9888), 0x0f88000f },
3469         { _MMIO(0x9888), 0x038a8000 },
3470         { _MMIO(0x9888), 0x058a8000 },
3471         { _MMIO(0x9888), 0x078a8000 },
3472         { _MMIO(0x9888), 0x098a8000 },
3473         { _MMIO(0x9888), 0x0b8a8000 },
3474         { _MMIO(0x9888), 0x0d8a8000 },
3475         { _MMIO(0x9888), 0x258baaa5 },
3476         { _MMIO(0x9888), 0x278b002a },
3477         { _MMIO(0x9888), 0x238b2a80 },
3478         { _MMIO(0x9888), 0x0f8c4000 },
3479         { _MMIO(0x9888), 0x178c2000 },
3480         { _MMIO(0x9888), 0x198c5500 },
3481         { _MMIO(0x9888), 0x1b8c0015 },
3482         { _MMIO(0x9888), 0x078d8000 },
3483         { _MMIO(0x9888), 0x098da000 },
3484         { _MMIO(0x9888), 0x0b8da000 },
3485         { _MMIO(0x9888), 0x0d8da000 },
3486         { _MMIO(0x9888), 0x0f8da000 },
3487         { _MMIO(0x9888), 0x2185aaaa },
3488         { _MMIO(0x9888), 0x2385002a },
3489         { _MMIO(0x9888), 0x1f85aa00 },
3490         { _MMIO(0x9888), 0x0f834000 },
3491         { _MMIO(0x9888), 0x19835400 },
3492         { _MMIO(0x9888), 0x1b830155 },
3493         { _MMIO(0x9888), 0x03834000 },
3494         { _MMIO(0x9888), 0x05834000 },
3495         { _MMIO(0x9888), 0x07834000 },
3496         { _MMIO(0x9888), 0x09834000 },
3497         { _MMIO(0x9888), 0x0b834000 },
3498         { _MMIO(0x9888), 0x0d834000 },
3499         { _MMIO(0x9888), 0x0784c000 },
3500         { _MMIO(0x9888), 0x0984c000 },
3501         { _MMIO(0x9888), 0x0b84c000 },
3502         { _MMIO(0x9888), 0x0d84c000 },
3503         { _MMIO(0x9888), 0x0f84c000 },
3504         { _MMIO(0x9888), 0x01848000 },
3505         { _MMIO(0x9888), 0x0384c000 },
3506         { _MMIO(0x9888), 0x0584c000 },
3507         { _MMIO(0x9888), 0x1780c000 },
3508         { _MMIO(0x9888), 0x1980c000 },
3509         { _MMIO(0x9888), 0x1b80c000 },
3510         { _MMIO(0x9888), 0x1d80c000 },
3511         { _MMIO(0x9888), 0x1f80c000 },
3512         { _MMIO(0x9888), 0x11808000 },
3513         { _MMIO(0x9888), 0x1380c000 },
3514         { _MMIO(0x9888), 0x1580c000 },
3515         { _MMIO(0x9888), 0x4f800000 },
3516         { _MMIO(0x9888), 0x43800c42 },
3517         { _MMIO(0x9888), 0x51800000 },
3518         { _MMIO(0x9888), 0x45800063 },
3519         { _MMIO(0x9888), 0x53800000 },
3520         { _MMIO(0x9888), 0x47800800 },
3521         { _MMIO(0x9888), 0x21800000 },
3522         { _MMIO(0x9888), 0x31800000 },
3523         { _MMIO(0x9888), 0x4d800000 },
3524         { _MMIO(0x9888), 0x3f8014a4 },
3525         { _MMIO(0x9888), 0x41801042 },
3526 };
3527
3528 static int
3529 get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
3530                      const struct i915_oa_reg **regs,
3531                      int *lens)
3532 {
3533         int n = 0;
3534
3535         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
3536         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
3537
3538         regs[n] = mux_config_tdl_1;
3539         lens[n] = ARRAY_SIZE(mux_config_tdl_1);
3540         n++;
3541
3542         return n;
3543 }
3544
3545 static const struct i915_oa_reg b_counter_config_tdl_2[] = {
3546         { _MMIO(0x2740), 0x00000000 },
3547         { _MMIO(0x2744), 0x00800000 },
3548         { _MMIO(0x2710), 0x00000000 },
3549         { _MMIO(0x2714), 0xf0800000 },
3550         { _MMIO(0x2720), 0x00000000 },
3551         { _MMIO(0x2724), 0x30800000 },
3552         { _MMIO(0x2770), 0x00000002 },
3553         { _MMIO(0x2774), 0x0000fdff },
3554         { _MMIO(0x2778), 0x00000000 },
3555         { _MMIO(0x277c), 0x0000fe7f },
3556         { _MMIO(0x2780), 0x00000000 },
3557         { _MMIO(0x2784), 0x0000ff9f },
3558         { _MMIO(0x2788), 0x00000000 },
3559         { _MMIO(0x278c), 0x0000ffe7 },
3560         { _MMIO(0x2790), 0x00000002 },
3561         { _MMIO(0x2794), 0x0000fffb },
3562         { _MMIO(0x2798), 0x00000002 },
3563         { _MMIO(0x279c), 0x0000fffd },
3564 };
3565
3566 static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
3567         { _MMIO(0xe458), 0x00005004 },
3568         { _MMIO(0xe558), 0x00010003 },
3569         { _MMIO(0xe658), 0x00012011 },
3570         { _MMIO(0xe758), 0x00015014 },
3571         { _MMIO(0xe45c), 0x00051050 },
3572         { _MMIO(0xe55c), 0x00053052 },
3573         { _MMIO(0xe65c), 0x00055054 },
3574 };
3575
3576 static const struct i915_oa_reg mux_config_tdl_2[] = {
3577         { _MMIO(0x9888), 0x16150000 },
3578         { _MMIO(0x9888), 0x16350000 },
3579         { _MMIO(0x9888), 0x16550000 },
3580         { _MMIO(0x9888), 0x16952e60 },
3581         { _MMIO(0x9888), 0x16b54d60 },
3582         { _MMIO(0x9888), 0x16d52e60 },
3583         { _MMIO(0x9888), 0x065c8000 },
3584         { _MMIO(0x9888), 0x085cc000 },
3585         { _MMIO(0x9888), 0x0a5cc000 },
3586         { _MMIO(0x9888), 0x0c5c4000 },
3587         { _MMIO(0x9888), 0x0e3d8000 },
3588         { _MMIO(0x9888), 0x183da000 },
3589         { _MMIO(0x9888), 0x06588000 },
3590         { _MMIO(0x9888), 0x08588000 },
3591         { _MMIO(0x9888), 0x0a584000 },
3592         { _MMIO(0x9888), 0x0e5b4000 },
3593         { _MMIO(0x9888), 0x185b5800 },
3594         { _MMIO(0x9888), 0x1a5b000a },
3595         { _MMIO(0x9888), 0x0e1faa00 },
3596         { _MMIO(0x9888), 0x101f02aa },
3597         { _MMIO(0x9888), 0x0e384000 },
3598         { _MMIO(0x9888), 0x16384000 },
3599         { _MMIO(0x9888), 0x18382a55 },
3600         { _MMIO(0x9888), 0x06398000 },
3601         { _MMIO(0x9888), 0x0839a000 },
3602         { _MMIO(0x9888), 0x0a39a000 },
3603         { _MMIO(0x9888), 0x0c39a000 },
3604         { _MMIO(0x9888), 0x0e39a000 },
3605         { _MMIO(0x9888), 0x1a3a02a0 },
3606         { _MMIO(0x9888), 0x0e138000 },
3607         { _MMIO(0x9888), 0x16130500 },
3608         { _MMIO(0x9888), 0x06148000 },
3609         { _MMIO(0x9888), 0x08146000 },
3610         { _MMIO(0x9888), 0x0615c100 },
3611         { _MMIO(0x9888), 0x0815c500 },
3612         { _MMIO(0x9888), 0x0a1500c3 },
3613         { _MMIO(0x9888), 0x10150000 },
3614         { _MMIO(0x9888), 0x16335040 },
3615         { _MMIO(0x9888), 0x08349000 },
3616         { _MMIO(0x9888), 0x0a341000 },
3617         { _MMIO(0x9888), 0x083500c1 },
3618         { _MMIO(0x9888), 0x0a35c500 },
3619         { _MMIO(0x9888), 0x0c3500c3 },
3620         { _MMIO(0x9888), 0x10350000 },
3621         { _MMIO(0x9888), 0x1853002a },
3622         { _MMIO(0x9888), 0x0a54e000 },
3623         { _MMIO(0x9888), 0x0c55c500 },
3624         { _MMIO(0x9888), 0x0e55c1c3 },
3625         { _MMIO(0x9888), 0x10550000 },
3626         { _MMIO(0x9888), 0x00dc8000 },
3627         { _MMIO(0x9888), 0x02dcc000 },
3628         { _MMIO(0x9888), 0x04dc4000 },
3629         { _MMIO(0x9888), 0x04bd8000 },
3630         { _MMIO(0x9888), 0x06bd8000 },
3631         { _MMIO(0x9888), 0x02d8c000 },
3632         { _MMIO(0x9888), 0x02db8000 },
3633         { _MMIO(0x9888), 0x04db4000 },
3634         { _MMIO(0x9888), 0x06db4000 },
3635         { _MMIO(0x9888), 0x08db8000 },
3636         { _MMIO(0x9888), 0x0c9fa000 },
3637         { _MMIO(0x9888), 0x0e9f00aa },
3638         { _MMIO(0x9888), 0x02b84000 },
3639         { _MMIO(0x9888), 0x04b84000 },
3640         { _MMIO(0x9888), 0x06b84000 },
3641         { _MMIO(0x9888), 0x08b84000 },
3642         { _MMIO(0x9888), 0x0ab88000 },
3643         { _MMIO(0x9888), 0x0cb88000 },
3644         { _MMIO(0x9888), 0x00b98000 },
3645         { _MMIO(0x9888), 0x02b9a000 },
3646         { _MMIO(0x9888), 0x04b9a000 },
3647         { _MMIO(0x9888), 0x06b92000 },
3648         { _MMIO(0x9888), 0x0aba8000 },
3649         { _MMIO(0x9888), 0x0cba8000 },
3650         { _MMIO(0x9888), 0x04938000 },
3651         { _MMIO(0x9888), 0x06938000 },
3652         { _MMIO(0x9888), 0x0494c000 },
3653         { _MMIO(0x9888), 0x0295cfc7 },
3654         { _MMIO(0x9888), 0x10950000 },
3655         { _MMIO(0x9888), 0x02b38000 },
3656         { _MMIO(0x9888), 0x08b38000 },
3657         { _MMIO(0x9888), 0x04b42000 },
3658         { _MMIO(0x9888), 0x06b41000 },
3659         { _MMIO(0x9888), 0x00b5c700 },
3660         { _MMIO(0x9888), 0x04b500cf },
3661         { _MMIO(0x9888), 0x10b50000 },
3662         { _MMIO(0x9888), 0x0ad38000 },
3663         { _MMIO(0x9888), 0x0cd38000 },
3664         { _MMIO(0x9888), 0x06d46000 },
3665         { _MMIO(0x9888), 0x04d5c700 },
3666         { _MMIO(0x9888), 0x06d500cf },
3667         { _MMIO(0x9888), 0x10d50000 },
3668         { _MMIO(0x9888), 0x03888000 },
3669         { _MMIO(0x9888), 0x05888000 },
3670         { _MMIO(0x9888), 0x07888000 },
3671         { _MMIO(0x9888), 0x09888000 },
3672         { _MMIO(0x9888), 0x0b888000 },
3673         { _MMIO(0x9888), 0x0d880400 },
3674         { _MMIO(0x9888), 0x0f8a8000 },
3675         { _MMIO(0x9888), 0x198a8000 },
3676         { _MMIO(0x9888), 0x1b8aaaa0 },
3677         { _MMIO(0x9888), 0x1d8a0002 },
3678         { _MMIO(0x9888), 0x258b555a },
3679         { _MMIO(0x9888), 0x278b0015 },
3680         { _MMIO(0x9888), 0x238b5500 },
3681         { _MMIO(0x9888), 0x038c4000 },
3682         { _MMIO(0x9888), 0x058c4000 },
3683         { _MMIO(0x9888), 0x078c4000 },
3684         { _MMIO(0x9888), 0x098c4000 },
3685         { _MMIO(0x9888), 0x0b8c4000 },
3686         { _MMIO(0x9888), 0x0d8c4000 },
3687         { _MMIO(0x9888), 0x018d8000 },
3688         { _MMIO(0x9888), 0x038da000 },
3689         { _MMIO(0x9888), 0x058da000 },
3690         { _MMIO(0x9888), 0x078d2000 },
3691         { _MMIO(0x9888), 0x2185aaaa },
3692         { _MMIO(0x9888), 0x2385002a },
3693         { _MMIO(0x9888), 0x1f85aa00 },
3694         { _MMIO(0x9888), 0x0f834000 },
3695         { _MMIO(0x9888), 0x19835400 },
3696         { _MMIO(0x9888), 0x1b830155 },
3697         { _MMIO(0x9888), 0x03834000 },
3698         { _MMIO(0x9888), 0x05834000 },
3699         { _MMIO(0x9888), 0x07834000 },
3700         { _MMIO(0x9888), 0x09834000 },
3701         { _MMIO(0x9888), 0x0b834000 },
3702         { _MMIO(0x9888), 0x0d834000 },
3703         { _MMIO(0x9888), 0x0784c000 },
3704         { _MMIO(0x9888), 0x0984c000 },
3705         { _MMIO(0x9888), 0x0b84c000 },
3706         { _MMIO(0x9888), 0x0d84c000 },
3707         { _MMIO(0x9888), 0x0f84c000 },
3708         { _MMIO(0x9888), 0x01848000 },
3709         { _MMIO(0x9888), 0x0384c000 },
3710         { _MMIO(0x9888), 0x0584c000 },
3711         { _MMIO(0x9888), 0x1780c000 },
3712         { _MMIO(0x9888), 0x1980c000 },
3713         { _MMIO(0x9888), 0x1b80c000 },
3714         { _MMIO(0x9888), 0x1d80c000 },
3715         { _MMIO(0x9888), 0x1f80c000 },
3716         { _MMIO(0x9888), 0x11808000 },
3717         { _MMIO(0x9888), 0x1380c000 },
3718         { _MMIO(0x9888), 0x1580c000 },
3719         { _MMIO(0x9888), 0x4f800000 },
3720         { _MMIO(0x9888), 0x43800882 },
3721         { _MMIO(0x9888), 0x51800000 },
3722         { _MMIO(0x9888), 0x45801082 },
3723         { _MMIO(0x9888), 0x53800000 },
3724         { _MMIO(0x9888), 0x478014a5 },
3725         { _MMIO(0x9888), 0x21800000 },
3726         { _MMIO(0x9888), 0x31800000 },
3727         { _MMIO(0x9888), 0x4d800000 },
3728         { _MMIO(0x9888), 0x3f800002 },
3729         { _MMIO(0x9888), 0x41800c62 },
3730 };
3731
3732 static int
3733 get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
3734                      const struct i915_oa_reg **regs,
3735                      int *lens)
3736 {
3737         int n = 0;
3738
3739         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
3740         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
3741
3742         regs[n] = mux_config_tdl_2;
3743         lens[n] = ARRAY_SIZE(mux_config_tdl_2);
3744         n++;
3745
3746         return n;
3747 }
3748
3749 static const struct i915_oa_reg b_counter_config_compute_extra[] = {
3750         { _MMIO(0x2740), 0x00000000 },
3751         { _MMIO(0x2744), 0x00800000 },
3752         { _MMIO(0x2710), 0x00000000 },
3753         { _MMIO(0x2714), 0x00800000 },
3754         { _MMIO(0x2720), 0x00000000 },
3755         { _MMIO(0x2724), 0x00800000 },
3756 };
3757
3758 static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
3759         { _MMIO(0xe458), 0x00001000 },
3760         { _MMIO(0xe558), 0x00003002 },
3761         { _MMIO(0xe658), 0x00005004 },
3762         { _MMIO(0xe758), 0x00011010 },
3763         { _MMIO(0xe45c), 0x00050012 },
3764         { _MMIO(0xe55c), 0x00052051 },
3765         { _MMIO(0xe65c), 0x00000008 },
3766 };
3767
3768 static const struct i915_oa_reg mux_config_compute_extra[] = {
3769         { _MMIO(0x9888), 0x161503e0 },
3770         { _MMIO(0x9888), 0x163503e0 },
3771         { _MMIO(0x9888), 0x165503e0 },
3772         { _MMIO(0x9888), 0x169503e0 },
3773         { _MMIO(0x9888), 0x16b503e0 },
3774         { _MMIO(0x9888), 0x16d503e0 },
3775         { _MMIO(0x9888), 0x045cc000 },
3776         { _MMIO(0x9888), 0x083d8000 },
3777         { _MMIO(0x9888), 0x04584000 },
3778         { _MMIO(0x9888), 0x085b4000 },
3779         { _MMIO(0x9888), 0x0a5b8000 },
3780         { _MMIO(0x9888), 0x0e1f00a8 },
3781         { _MMIO(0x9888), 0x08384000 },
3782         { _MMIO(0x9888), 0x0a384000 },
3783         { _MMIO(0x9888), 0x0c388000 },
3784         { _MMIO(0x9888), 0x0439a000 },
3785         { _MMIO(0x9888), 0x06392000 },
3786         { _MMIO(0x9888), 0x0c3a8000 },
3787         { _MMIO(0x9888), 0x08138000 },
3788         { _MMIO(0x9888), 0x06141000 },
3789         { _MMIO(0x9888), 0x041500c3 },
3790         { _MMIO(0x9888), 0x10150000 },
3791         { _MMIO(0x9888), 0x0a338000 },
3792         { _MMIO(0x9888), 0x06342000 },
3793         { _MMIO(0x9888), 0x0435c300 },
3794         { _MMIO(0x9888), 0x10350000 },
3795         { _MMIO(0x9888), 0x0c538000 },
3796         { _MMIO(0x9888), 0x06544000 },
3797         { _MMIO(0x9888), 0x065500c3 },
3798         { _MMIO(0x9888), 0x10550000 },
3799         { _MMIO(0x9888), 0x00dc8000 },
3800         { _MMIO(0x9888), 0x02dc4000 },
3801         { _MMIO(0x9888), 0x02bd8000 },
3802         { _MMIO(0x9888), 0x00d88000 },
3803         { _MMIO(0x9888), 0x02db4000 },
3804         { _MMIO(0x9888), 0x04db8000 },
3805         { _MMIO(0x9888), 0x0c9fa000 },
3806         { _MMIO(0x9888), 0x0e9f0002 },
3807         { _MMIO(0x9888), 0x02b84000 },
3808         { _MMIO(0x9888), 0x04b84000 },
3809         { _MMIO(0x9888), 0x06b88000 },
3810         { _MMIO(0x9888), 0x00b98000 },
3811         { _MMIO(0x9888), 0x02b9a000 },
3812         { _MMIO(0x9888), 0x06ba8000 },
3813         { _MMIO(0x9888), 0x02938000 },
3814         { _MMIO(0x9888), 0x04942000 },
3815         { _MMIO(0x9888), 0x0095c300 },
3816         { _MMIO(0x9888), 0x10950000 },
3817         { _MMIO(0x9888), 0x04b38000 },
3818         { _MMIO(0x9888), 0x04b44000 },
3819         { _MMIO(0x9888), 0x02b500c3 },
3820         { _MMIO(0x9888), 0x10b50000 },
3821         { _MMIO(0x9888), 0x06d38000 },
3822         { _MMIO(0x9888), 0x04d48000 },
3823         { _MMIO(0x9888), 0x02d5c300 },
3824         { _MMIO(0x9888), 0x10d50000 },
3825         { _MMIO(0x9888), 0x03888000 },
3826         { _MMIO(0x9888), 0x05888000 },
3827         { _MMIO(0x9888), 0x07888000 },
3828         { _MMIO(0x9888), 0x098a8000 },
3829         { _MMIO(0x9888), 0x0b8a8000 },
3830         { _MMIO(0x9888), 0x0d8a8000 },
3831         { _MMIO(0x9888), 0x238b3500 },
3832         { _MMIO(0x9888), 0x258b0005 },
3833         { _MMIO(0x9888), 0x038c4000 },
3834         { _MMIO(0x9888), 0x058c4000 },
3835         { _MMIO(0x9888), 0x078c4000 },
3836         { _MMIO(0x9888), 0x018d8000 },
3837         { _MMIO(0x9888), 0x038da000 },
3838         { _MMIO(0x9888), 0x1f85aa00 },
3839         { _MMIO(0x9888), 0x2185000a },
3840         { _MMIO(0x9888), 0x03834000 },
3841         { _MMIO(0x9888), 0x05834000 },
3842         { _MMIO(0x9888), 0x07834000 },
3843         { _MMIO(0x9888), 0x09834000 },
3844         { _MMIO(0x9888), 0x0b834000 },
3845         { _MMIO(0x9888), 0x0d834000 },
3846         { _MMIO(0x9888), 0x01848000 },
3847         { _MMIO(0x9888), 0x0384c000 },
3848         { _MMIO(0x9888), 0x0584c000 },
3849         { _MMIO(0x9888), 0x07844000 },
3850         { _MMIO(0x9888), 0x11808000 },
3851         { _MMIO(0x9888), 0x1380c000 },
3852         { _MMIO(0x9888), 0x1580c000 },
3853         { _MMIO(0x9888), 0x17804000 },
3854         { _MMIO(0x9888), 0x21800000 },
3855         { _MMIO(0x9888), 0x4d800000 },
3856         { _MMIO(0x9888), 0x3f800c40 },
3857         { _MMIO(0x9888), 0x4f800000 },
3858         { _MMIO(0x9888), 0x41801482 },
3859         { _MMIO(0x9888), 0x31800000 },
3860 };
3861
3862 static int
3863 get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
3864                              const struct i915_oa_reg **regs,
3865                              int *lens)
3866 {
3867         int n = 0;
3868
3869         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
3870         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
3871
3872         regs[n] = mux_config_compute_extra;
3873         lens[n] = ARRAY_SIZE(mux_config_compute_extra);
3874         n++;
3875
3876         return n;
3877 }
3878
3879 static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
3880         { _MMIO(0x2740), 0x00000000 },
3881         { _MMIO(0x2710), 0x00000000 },
3882         { _MMIO(0x2714), 0xf0800000 },
3883         { _MMIO(0x2720), 0x00000000 },
3884         { _MMIO(0x2724), 0x30800000 },
3885         { _MMIO(0x2770), 0x00100030 },
3886         { _MMIO(0x2774), 0x0000fff9 },
3887         { _MMIO(0x2778), 0x00000002 },
3888         { _MMIO(0x277c), 0x0000fffc },
3889         { _MMIO(0x2780), 0x00000002 },
3890         { _MMIO(0x2784), 0x0000fff3 },
3891         { _MMIO(0x2788), 0x00100180 },
3892         { _MMIO(0x278c), 0x0000ffcf },
3893         { _MMIO(0x2790), 0x00000002 },
3894         { _MMIO(0x2794), 0x0000ffcf },
3895         { _MMIO(0x2798), 0x00000002 },
3896         { _MMIO(0x279c), 0x0000ff3f },
3897 };
3898
3899 static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
3900         { _MMIO(0xe458), 0x00005004 },
3901         { _MMIO(0xe558), 0x00008003 },
3902 };
3903
3904 static const struct i915_oa_reg mux_config_vme_pipe[] = {
3905         { _MMIO(0x9888), 0x14100812 },
3906         { _MMIO(0x9888), 0x14125800 },
3907         { _MMIO(0x9888), 0x161200c0 },
3908         { _MMIO(0x9888), 0x14300812 },
3909         { _MMIO(0x9888), 0x14325800 },
3910         { _MMIO(0x9888), 0x163200c0 },
3911         { _MMIO(0x9888), 0x005c4000 },
3912         { _MMIO(0x9888), 0x065c8000 },
3913         { _MMIO(0x9888), 0x085cc000 },
3914         { _MMIO(0x9888), 0x0a5cc000 },
3915         { _MMIO(0x9888), 0x0c5cc000 },
3916         { _MMIO(0x9888), 0x003d8000 },
3917         { _MMIO(0x9888), 0x0e3d8000 },
3918         { _MMIO(0x9888), 0x183d2800 },
3919         { _MMIO(0x9888), 0x00584000 },
3920         { _MMIO(0x9888), 0x06588000 },
3921         { _MMIO(0x9888), 0x0858c000 },
3922         { _MMIO(0x9888), 0x005b4000 },
3923         { _MMIO(0x9888), 0x0e5b4000 },
3924         { _MMIO(0x9888), 0x185b9400 },
3925         { _MMIO(0x9888), 0x1a5b002a },
3926         { _MMIO(0x9888), 0x0c1f0800 },
3927         { _MMIO(0x9888), 0x0e1faa00 },
3928         { _MMIO(0x9888), 0x101f002a },
3929         { _MMIO(0x9888), 0x00384000 },
3930         { _MMIO(0x9888), 0x0e384000 },
3931         { _MMIO(0x9888), 0x16384000 },
3932         { _MMIO(0x9888), 0x18380155 },
3933         { _MMIO(0x9888), 0x00392000 },
3934         { _MMIO(0x9888), 0x06398000 },
3935         { _MMIO(0x9888), 0x0839a000 },
3936         { _MMIO(0x9888), 0x0a39a000 },
3937         { _MMIO(0x9888), 0x0c39a000 },
3938         { _MMIO(0x9888), 0x00100047 },
3939         { _MMIO(0x9888), 0x06101a80 },
3940         { _MMIO(0x9888), 0x10100000 },
3941         { _MMIO(0x9888), 0x0810c000 },
3942         { _MMIO(0x9888), 0x0811c000 },
3943         { _MMIO(0x9888), 0x08126151 },
3944         { _MMIO(0x9888), 0x10120000 },
3945         { _MMIO(0x9888), 0x00134000 },
3946         { _MMIO(0x9888), 0x0e134000 },
3947         { _MMIO(0x9888), 0x161300a0 },
3948         { _MMIO(0x9888), 0x0a301ac7 },
3949         { _MMIO(0x9888), 0x10300000 },
3950         { _MMIO(0x9888), 0x0c30c000 },
3951         { _MMIO(0x9888), 0x0c31c000 },
3952         { _MMIO(0x9888), 0x0c326151 },
3953         { _MMIO(0x9888), 0x10320000 },
3954         { _MMIO(0x9888), 0x16332a00 },
3955         { _MMIO(0x9888), 0x18330001 },
3956         { _MMIO(0x9888), 0x018a8000 },
3957         { _MMIO(0x9888), 0x0f8a8000 },
3958         { _MMIO(0x9888), 0x198a8000 },
3959         { _MMIO(0x9888), 0x1b8a2aa0 },
3960         { _MMIO(0x9888), 0x238b0020 },
3961         { _MMIO(0x9888), 0x258b5550 },
3962         { _MMIO(0x9888), 0x278b0001 },
3963         { _MMIO(0x9888), 0x1f850080 },
3964         { _MMIO(0x9888), 0x2185aaa0 },
3965         { _MMIO(0x9888), 0x23850002 },
3966         { _MMIO(0x9888), 0x01834000 },
3967         { _MMIO(0x9888), 0x0f834000 },
3968         { _MMIO(0x9888), 0x19835400 },
3969         { _MMIO(0x9888), 0x1b830015 },
3970         { _MMIO(0x9888), 0x01844000 },
3971         { _MMIO(0x9888), 0x07848000 },
3972         { _MMIO(0x9888), 0x0984c000 },
3973         { _MMIO(0x9888), 0x0b84c000 },
3974         { _MMIO(0x9888), 0x0d84c000 },
3975         { _MMIO(0x9888), 0x11804000 },
3976         { _MMIO(0x9888), 0x17808000 },
3977         { _MMIO(0x9888), 0x1980c000 },
3978         { _MMIO(0x9888), 0x1b80c000 },
3979         { _MMIO(0x9888), 0x1d80c000 },
3980         { _MMIO(0x9888), 0x4d800000 },
3981         { _MMIO(0x9888), 0x3d800800 },
3982         { _MMIO(0x9888), 0x4f800000 },
3983         { _MMIO(0x9888), 0x43800002 },
3984         { _MMIO(0x9888), 0x51800000 },
3985         { _MMIO(0x9888), 0x45800884 },
3986         { _MMIO(0x9888), 0x53800000 },
3987         { _MMIO(0x9888), 0x47800002 },
3988         { _MMIO(0x9888), 0x21800000 },
3989         { _MMIO(0x9888), 0x31800000 },
3990 };
3991
3992 static int
3993 get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
3994                         const struct i915_oa_reg **regs,
3995                         int *lens)
3996 {
3997         int n = 0;
3998
3999         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
4000         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
4001
4002         regs[n] = mux_config_vme_pipe;
4003         lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
4004         n++;
4005
4006         return n;
4007 }
4008
4009 static const struct i915_oa_reg b_counter_config_test_oa[] = {
4010         { _MMIO(0x2740), 0x00000000 },
4011         { _MMIO(0x2744), 0x00800000 },
4012         { _MMIO(0x2714), 0xf0800000 },
4013         { _MMIO(0x2710), 0x00000000 },
4014         { _MMIO(0x2724), 0xf0800000 },
4015         { _MMIO(0x2720), 0x00000000 },
4016         { _MMIO(0x2770), 0x00000004 },
4017         { _MMIO(0x2774), 0x00000000 },
4018         { _MMIO(0x2778), 0x00000003 },
4019         { _MMIO(0x277c), 0x00000000 },
4020         { _MMIO(0x2780), 0x00000007 },
4021         { _MMIO(0x2784), 0x00000000 },
4022         { _MMIO(0x2788), 0x00100002 },
4023         { _MMIO(0x278c), 0x0000fff7 },
4024         { _MMIO(0x2790), 0x00100002 },
4025         { _MMIO(0x2794), 0x0000ffcf },
4026         { _MMIO(0x2798), 0x00100082 },
4027         { _MMIO(0x279c), 0x0000ffef },
4028         { _MMIO(0x27a0), 0x001000c2 },
4029         { _MMIO(0x27a4), 0x0000ffe7 },
4030         { _MMIO(0x27a8), 0x00100001 },
4031         { _MMIO(0x27ac), 0x0000ffe7 },
4032 };
4033
4034 static const struct i915_oa_reg flex_eu_config_test_oa[] = {
4035 };
4036
4037 static const struct i915_oa_reg mux_config_test_oa[] = {
4038         { _MMIO(0x9888), 0x198b0000 },
4039         { _MMIO(0x9888), 0x078b0066 },
4040         { _MMIO(0x9888), 0x118b0000 },
4041         { _MMIO(0x9888), 0x258b0000 },
4042         { _MMIO(0x9888), 0x21850008 },
4043         { _MMIO(0x9888), 0x0d834000 },
4044         { _MMIO(0x9888), 0x07844000 },
4045         { _MMIO(0x9888), 0x17804000 },
4046         { _MMIO(0x9888), 0x21800000 },
4047         { _MMIO(0x9888), 0x4f800000 },
4048         { _MMIO(0x9888), 0x41800000 },
4049         { _MMIO(0x9888), 0x31800000 },
4050 };
4051
4052 static int
4053 get_test_oa_mux_config(struct drm_i915_private *dev_priv,
4054                        const struct i915_oa_reg **regs,
4055                        int *lens)
4056 {
4057         int n = 0;
4058
4059         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
4060         BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
4061
4062         regs[n] = mux_config_test_oa;
4063         lens[n] = ARRAY_SIZE(mux_config_test_oa);
4064         n++;
4065
4066         return n;
4067 }
4068
4069 int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
4070 {
4071         dev_priv->perf.oa.n_mux_configs = 0;
4072         dev_priv->perf.oa.b_counter_regs = NULL;
4073         dev_priv->perf.oa.b_counter_regs_len = 0;
4074         dev_priv->perf.oa.flex_regs = NULL;
4075         dev_priv->perf.oa.flex_regs_len = 0;
4076
4077         switch (dev_priv->perf.oa.metrics_set) {
4078         case METRIC_SET_ID_RENDER_BASIC:
4079                 dev_priv->perf.oa.n_mux_configs =
4080                         get_render_basic_mux_config(dev_priv,
4081                                                     dev_priv->perf.oa.mux_regs,
4082                                                     dev_priv->perf.oa.mux_regs_lens);
4083                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4084                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
4085
4086                         /* EINVAL because *_register_sysfs already checked this
4087                          * and so it wouldn't have been advertised to userspace and
4088                          * so shouldn't have been requested
4089                          */
4090                         return -EINVAL;
4091                 }
4092
4093                 dev_priv->perf.oa.b_counter_regs =
4094                         b_counter_config_render_basic;
4095                 dev_priv->perf.oa.b_counter_regs_len =
4096                         ARRAY_SIZE(b_counter_config_render_basic);
4097
4098                 dev_priv->perf.oa.flex_regs =
4099                         flex_eu_config_render_basic;
4100                 dev_priv->perf.oa.flex_regs_len =
4101                         ARRAY_SIZE(flex_eu_config_render_basic);
4102
4103                 return 0;
4104         case METRIC_SET_ID_COMPUTE_BASIC:
4105                 dev_priv->perf.oa.n_mux_configs =
4106                         get_compute_basic_mux_config(dev_priv,
4107                                                      dev_priv->perf.oa.mux_regs,
4108                                                      dev_priv->perf.oa.mux_regs_lens);
4109                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4110                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
4111
4112                         /* EINVAL because *_register_sysfs already checked this
4113                          * and so it wouldn't have been advertised to userspace and
4114                          * so shouldn't have been requested
4115                          */
4116                         return -EINVAL;
4117                 }
4118
4119                 dev_priv->perf.oa.b_counter_regs =
4120                         b_counter_config_compute_basic;
4121                 dev_priv->perf.oa.b_counter_regs_len =
4122                         ARRAY_SIZE(b_counter_config_compute_basic);
4123
4124                 dev_priv->perf.oa.flex_regs =
4125                         flex_eu_config_compute_basic;
4126                 dev_priv->perf.oa.flex_regs_len =
4127                         ARRAY_SIZE(flex_eu_config_compute_basic);
4128
4129                 return 0;
4130         case METRIC_SET_ID_RENDER_PIPE_PROFILE:
4131                 dev_priv->perf.oa.n_mux_configs =
4132                         get_render_pipe_profile_mux_config(dev_priv,
4133                                                            dev_priv->perf.oa.mux_regs,
4134                                                            dev_priv->perf.oa.mux_regs_lens);
4135                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4136                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
4137
4138                         /* EINVAL because *_register_sysfs already checked this
4139                          * and so it wouldn't have been advertised to userspace and
4140                          * so shouldn't have been requested
4141                          */
4142                         return -EINVAL;
4143                 }
4144
4145                 dev_priv->perf.oa.b_counter_regs =
4146                         b_counter_config_render_pipe_profile;
4147                 dev_priv->perf.oa.b_counter_regs_len =
4148                         ARRAY_SIZE(b_counter_config_render_pipe_profile);
4149
4150                 dev_priv->perf.oa.flex_regs =
4151                         flex_eu_config_render_pipe_profile;
4152                 dev_priv->perf.oa.flex_regs_len =
4153                         ARRAY_SIZE(flex_eu_config_render_pipe_profile);
4154
4155                 return 0;
4156         case METRIC_SET_ID_MEMORY_READS:
4157                 dev_priv->perf.oa.n_mux_configs =
4158                         get_memory_reads_mux_config(dev_priv,
4159                                                     dev_priv->perf.oa.mux_regs,
4160                                                     dev_priv->perf.oa.mux_regs_lens);
4161                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4162                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
4163
4164                         /* EINVAL because *_register_sysfs already checked this
4165                          * and so it wouldn't have been advertised to userspace and
4166                          * so shouldn't have been requested
4167                          */
4168                         return -EINVAL;
4169                 }
4170
4171                 dev_priv->perf.oa.b_counter_regs =
4172                         b_counter_config_memory_reads;
4173                 dev_priv->perf.oa.b_counter_regs_len =
4174                         ARRAY_SIZE(b_counter_config_memory_reads);
4175
4176                 dev_priv->perf.oa.flex_regs =
4177                         flex_eu_config_memory_reads;
4178                 dev_priv->perf.oa.flex_regs_len =
4179                         ARRAY_SIZE(flex_eu_config_memory_reads);
4180
4181                 return 0;
4182         case METRIC_SET_ID_MEMORY_WRITES:
4183                 dev_priv->perf.oa.n_mux_configs =
4184                         get_memory_writes_mux_config(dev_priv,
4185                                                      dev_priv->perf.oa.mux_regs,
4186                                                      dev_priv->perf.oa.mux_regs_lens);
4187                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4188                         DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
4189
4190                         /* EINVAL because *_register_sysfs already checked this
4191                          * and so it wouldn't have been advertised to userspace and
4192                          * so shouldn't have been requested
4193                          */
4194                         return -EINVAL;
4195                 }
4196
4197                 dev_priv->perf.oa.b_counter_regs =
4198                         b_counter_config_memory_writes;
4199                 dev_priv->perf.oa.b_counter_regs_len =
4200                         ARRAY_SIZE(b_counter_config_memory_writes);
4201
4202                 dev_priv->perf.oa.flex_regs =
4203                         flex_eu_config_memory_writes;
4204                 dev_priv->perf.oa.flex_regs_len =
4205                         ARRAY_SIZE(flex_eu_config_memory_writes);
4206
4207                 return 0;
4208         case METRIC_SET_ID_COMPUTE_EXTENDED:
4209                 dev_priv->perf.oa.n_mux_configs =
4210                         get_compute_extended_mux_config(dev_priv,
4211                                                         dev_priv->perf.oa.mux_regs,
4212                                                         dev_priv->perf.oa.mux_regs_lens);
4213                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4214                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
4215
4216                         /* EINVAL because *_register_sysfs already checked this
4217                          * and so it wouldn't have been advertised to userspace and
4218                          * so shouldn't have been requested
4219                          */
4220                         return -EINVAL;
4221                 }
4222
4223                 dev_priv->perf.oa.b_counter_regs =
4224                         b_counter_config_compute_extended;
4225                 dev_priv->perf.oa.b_counter_regs_len =
4226                         ARRAY_SIZE(b_counter_config_compute_extended);
4227
4228                 dev_priv->perf.oa.flex_regs =
4229                         flex_eu_config_compute_extended;
4230                 dev_priv->perf.oa.flex_regs_len =
4231                         ARRAY_SIZE(flex_eu_config_compute_extended);
4232
4233                 return 0;
4234         case METRIC_SET_ID_COMPUTE_L3_CACHE:
4235                 dev_priv->perf.oa.n_mux_configs =
4236                         get_compute_l3_cache_mux_config(dev_priv,
4237                                                         dev_priv->perf.oa.mux_regs,
4238                                                         dev_priv->perf.oa.mux_regs_lens);
4239                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4240                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
4241
4242                         /* EINVAL because *_register_sysfs already checked this
4243                          * and so it wouldn't have been advertised to userspace and
4244                          * so shouldn't have been requested
4245                          */
4246                         return -EINVAL;
4247                 }
4248
4249                 dev_priv->perf.oa.b_counter_regs =
4250                         b_counter_config_compute_l3_cache;
4251                 dev_priv->perf.oa.b_counter_regs_len =
4252                         ARRAY_SIZE(b_counter_config_compute_l3_cache);
4253
4254                 dev_priv->perf.oa.flex_regs =
4255                         flex_eu_config_compute_l3_cache;
4256                 dev_priv->perf.oa.flex_regs_len =
4257                         ARRAY_SIZE(flex_eu_config_compute_l3_cache);
4258
4259                 return 0;
4260         case METRIC_SET_ID_DATA_PORT_READS_COALESCING:
4261                 dev_priv->perf.oa.n_mux_configs =
4262                         get_data_port_reads_coalescing_mux_config(dev_priv,
4263                                                                   dev_priv->perf.oa.mux_regs,
4264                                                                   dev_priv->perf.oa.mux_regs_lens);
4265                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4266                         DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set\n");
4267
4268                         /* EINVAL because *_register_sysfs already checked this
4269                          * and so it wouldn't have been advertised to userspace and
4270                          * so shouldn't have been requested
4271                          */
4272                         return -EINVAL;
4273                 }
4274
4275                 dev_priv->perf.oa.b_counter_regs =
4276                         b_counter_config_data_port_reads_coalescing;
4277                 dev_priv->perf.oa.b_counter_regs_len =
4278                         ARRAY_SIZE(b_counter_config_data_port_reads_coalescing);
4279
4280                 dev_priv->perf.oa.flex_regs =
4281                         flex_eu_config_data_port_reads_coalescing;
4282                 dev_priv->perf.oa.flex_regs_len =
4283                         ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing);
4284
4285                 return 0;
4286         case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING:
4287                 dev_priv->perf.oa.n_mux_configs =
4288                         get_data_port_writes_coalescing_mux_config(dev_priv,
4289                                                                    dev_priv->perf.oa.mux_regs,
4290                                                                    dev_priv->perf.oa.mux_regs_lens);
4291                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4292                         DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set\n");
4293
4294                         /* EINVAL because *_register_sysfs already checked this
4295                          * and so it wouldn't have been advertised to userspace and
4296                          * so shouldn't have been requested
4297                          */
4298                         return -EINVAL;
4299                 }
4300
4301                 dev_priv->perf.oa.b_counter_regs =
4302                         b_counter_config_data_port_writes_coalescing;
4303                 dev_priv->perf.oa.b_counter_regs_len =
4304                         ARRAY_SIZE(b_counter_config_data_port_writes_coalescing);
4305
4306                 dev_priv->perf.oa.flex_regs =
4307                         flex_eu_config_data_port_writes_coalescing;
4308                 dev_priv->perf.oa.flex_regs_len =
4309                         ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing);
4310
4311                 return 0;
4312         case METRIC_SET_ID_HDC_AND_SF:
4313                 dev_priv->perf.oa.n_mux_configs =
4314                         get_hdc_and_sf_mux_config(dev_priv,
4315                                                   dev_priv->perf.oa.mux_regs,
4316                                                   dev_priv->perf.oa.mux_regs_lens);
4317                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4318                         DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
4319
4320                         /* EINVAL because *_register_sysfs already checked this
4321                          * and so it wouldn't have been advertised to userspace and
4322                          * so shouldn't have been requested
4323                          */
4324                         return -EINVAL;
4325                 }
4326
4327                 dev_priv->perf.oa.b_counter_regs =
4328                         b_counter_config_hdc_and_sf;
4329                 dev_priv->perf.oa.b_counter_regs_len =
4330                         ARRAY_SIZE(b_counter_config_hdc_and_sf);
4331
4332                 dev_priv->perf.oa.flex_regs =
4333                         flex_eu_config_hdc_and_sf;
4334                 dev_priv->perf.oa.flex_regs_len =
4335                         ARRAY_SIZE(flex_eu_config_hdc_and_sf);
4336
4337                 return 0;
4338         case METRIC_SET_ID_L3_1:
4339                 dev_priv->perf.oa.n_mux_configs =
4340                         get_l3_1_mux_config(dev_priv,
4341                                             dev_priv->perf.oa.mux_regs,
4342                                             dev_priv->perf.oa.mux_regs_lens);
4343                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4344                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
4345
4346                         /* EINVAL because *_register_sysfs already checked this
4347                          * and so it wouldn't have been advertised to userspace and
4348                          * so shouldn't have been requested
4349                          */
4350                         return -EINVAL;
4351                 }
4352
4353                 dev_priv->perf.oa.b_counter_regs =
4354                         b_counter_config_l3_1;
4355                 dev_priv->perf.oa.b_counter_regs_len =
4356                         ARRAY_SIZE(b_counter_config_l3_1);
4357
4358                 dev_priv->perf.oa.flex_regs =
4359                         flex_eu_config_l3_1;
4360                 dev_priv->perf.oa.flex_regs_len =
4361                         ARRAY_SIZE(flex_eu_config_l3_1);
4362
4363                 return 0;
4364         case METRIC_SET_ID_L3_2:
4365                 dev_priv->perf.oa.n_mux_configs =
4366                         get_l3_2_mux_config(dev_priv,
4367                                             dev_priv->perf.oa.mux_regs,
4368                                             dev_priv->perf.oa.mux_regs_lens);
4369                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4370                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
4371
4372                         /* EINVAL because *_register_sysfs already checked this
4373                          * and so it wouldn't have been advertised to userspace and
4374                          * so shouldn't have been requested
4375                          */
4376                         return -EINVAL;
4377                 }
4378
4379                 dev_priv->perf.oa.b_counter_regs =
4380                         b_counter_config_l3_2;
4381                 dev_priv->perf.oa.b_counter_regs_len =
4382                         ARRAY_SIZE(b_counter_config_l3_2);
4383
4384                 dev_priv->perf.oa.flex_regs =
4385                         flex_eu_config_l3_2;
4386                 dev_priv->perf.oa.flex_regs_len =
4387                         ARRAY_SIZE(flex_eu_config_l3_2);
4388
4389                 return 0;
4390         case METRIC_SET_ID_L3_3:
4391                 dev_priv->perf.oa.n_mux_configs =
4392                         get_l3_3_mux_config(dev_priv,
4393                                             dev_priv->perf.oa.mux_regs,
4394                                             dev_priv->perf.oa.mux_regs_lens);
4395                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4396                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
4397
4398                         /* EINVAL because *_register_sysfs already checked this
4399                          * and so it wouldn't have been advertised to userspace and
4400                          * so shouldn't have been requested
4401                          */
4402                         return -EINVAL;
4403                 }
4404
4405                 dev_priv->perf.oa.b_counter_regs =
4406                         b_counter_config_l3_3;
4407                 dev_priv->perf.oa.b_counter_regs_len =
4408                         ARRAY_SIZE(b_counter_config_l3_3);
4409
4410                 dev_priv->perf.oa.flex_regs =
4411                         flex_eu_config_l3_3;
4412                 dev_priv->perf.oa.flex_regs_len =
4413                         ARRAY_SIZE(flex_eu_config_l3_3);
4414
4415                 return 0;
4416         case METRIC_SET_ID_L3_4:
4417                 dev_priv->perf.oa.n_mux_configs =
4418                         get_l3_4_mux_config(dev_priv,
4419                                             dev_priv->perf.oa.mux_regs,
4420                                             dev_priv->perf.oa.mux_regs_lens);
4421                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4422                         DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n");
4423
4424                         /* EINVAL because *_register_sysfs already checked this
4425                          * and so it wouldn't have been advertised to userspace and
4426                          * so shouldn't have been requested
4427                          */
4428                         return -EINVAL;
4429                 }
4430
4431                 dev_priv->perf.oa.b_counter_regs =
4432                         b_counter_config_l3_4;
4433                 dev_priv->perf.oa.b_counter_regs_len =
4434                         ARRAY_SIZE(b_counter_config_l3_4);
4435
4436                 dev_priv->perf.oa.flex_regs =
4437                         flex_eu_config_l3_4;
4438                 dev_priv->perf.oa.flex_regs_len =
4439                         ARRAY_SIZE(flex_eu_config_l3_4);
4440
4441                 return 0;
4442         case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
4443                 dev_priv->perf.oa.n_mux_configs =
4444                         get_rasterizer_and_pixel_backend_mux_config(dev_priv,
4445                                                                     dev_priv->perf.oa.mux_regs,
4446                                                                     dev_priv->perf.oa.mux_regs_lens);
4447                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4448                         DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
4449
4450                         /* EINVAL because *_register_sysfs already checked this
4451                          * and so it wouldn't have been advertised to userspace and
4452                          * so shouldn't have been requested
4453                          */
4454                         return -EINVAL;
4455                 }
4456
4457                 dev_priv->perf.oa.b_counter_regs =
4458                         b_counter_config_rasterizer_and_pixel_backend;
4459                 dev_priv->perf.oa.b_counter_regs_len =
4460                         ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
4461
4462                 dev_priv->perf.oa.flex_regs =
4463                         flex_eu_config_rasterizer_and_pixel_backend;
4464                 dev_priv->perf.oa.flex_regs_len =
4465                         ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
4466
4467                 return 0;
4468         case METRIC_SET_ID_SAMPLER_1:
4469                 dev_priv->perf.oa.n_mux_configs =
4470                         get_sampler_1_mux_config(dev_priv,
4471                                                  dev_priv->perf.oa.mux_regs,
4472                                                  dev_priv->perf.oa.mux_regs_lens);
4473                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4474                         DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n");
4475
4476                         /* EINVAL because *_register_sysfs already checked this
4477                          * and so it wouldn't have been advertised to userspace and
4478                          * so shouldn't have been requested
4479                          */
4480                         return -EINVAL;
4481                 }
4482
4483                 dev_priv->perf.oa.b_counter_regs =
4484                         b_counter_config_sampler_1;
4485                 dev_priv->perf.oa.b_counter_regs_len =
4486                         ARRAY_SIZE(b_counter_config_sampler_1);
4487
4488                 dev_priv->perf.oa.flex_regs =
4489                         flex_eu_config_sampler_1;
4490                 dev_priv->perf.oa.flex_regs_len =
4491                         ARRAY_SIZE(flex_eu_config_sampler_1);
4492
4493                 return 0;
4494         case METRIC_SET_ID_SAMPLER_2:
4495                 dev_priv->perf.oa.n_mux_configs =
4496                         get_sampler_2_mux_config(dev_priv,
4497                                                  dev_priv->perf.oa.mux_regs,
4498                                                  dev_priv->perf.oa.mux_regs_lens);
4499                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4500                         DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n");
4501
4502                         /* EINVAL because *_register_sysfs already checked this
4503                          * and so it wouldn't have been advertised to userspace and
4504                          * so shouldn't have been requested
4505                          */
4506                         return -EINVAL;
4507                 }
4508
4509                 dev_priv->perf.oa.b_counter_regs =
4510                         b_counter_config_sampler_2;
4511                 dev_priv->perf.oa.b_counter_regs_len =
4512                         ARRAY_SIZE(b_counter_config_sampler_2);
4513
4514                 dev_priv->perf.oa.flex_regs =
4515                         flex_eu_config_sampler_2;
4516                 dev_priv->perf.oa.flex_regs_len =
4517                         ARRAY_SIZE(flex_eu_config_sampler_2);
4518
4519                 return 0;
4520         case METRIC_SET_ID_TDL_1:
4521                 dev_priv->perf.oa.n_mux_configs =
4522                         get_tdl_1_mux_config(dev_priv,
4523                                              dev_priv->perf.oa.mux_regs,
4524                                              dev_priv->perf.oa.mux_regs_lens);
4525                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4526                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
4527
4528                         /* EINVAL because *_register_sysfs already checked this
4529                          * and so it wouldn't have been advertised to userspace and
4530                          * so shouldn't have been requested
4531                          */
4532                         return -EINVAL;
4533                 }
4534
4535                 dev_priv->perf.oa.b_counter_regs =
4536                         b_counter_config_tdl_1;
4537                 dev_priv->perf.oa.b_counter_regs_len =
4538                         ARRAY_SIZE(b_counter_config_tdl_1);
4539
4540                 dev_priv->perf.oa.flex_regs =
4541                         flex_eu_config_tdl_1;
4542                 dev_priv->perf.oa.flex_regs_len =
4543                         ARRAY_SIZE(flex_eu_config_tdl_1);
4544
4545                 return 0;
4546         case METRIC_SET_ID_TDL_2:
4547                 dev_priv->perf.oa.n_mux_configs =
4548                         get_tdl_2_mux_config(dev_priv,
4549                                              dev_priv->perf.oa.mux_regs,
4550                                              dev_priv->perf.oa.mux_regs_lens);
4551                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4552                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
4553
4554                         /* EINVAL because *_register_sysfs already checked this
4555                          * and so it wouldn't have been advertised to userspace and
4556                          * so shouldn't have been requested
4557                          */
4558                         return -EINVAL;
4559                 }
4560
4561                 dev_priv->perf.oa.b_counter_regs =
4562                         b_counter_config_tdl_2;
4563                 dev_priv->perf.oa.b_counter_regs_len =
4564                         ARRAY_SIZE(b_counter_config_tdl_2);
4565
4566                 dev_priv->perf.oa.flex_regs =
4567                         flex_eu_config_tdl_2;
4568                 dev_priv->perf.oa.flex_regs_len =
4569                         ARRAY_SIZE(flex_eu_config_tdl_2);
4570
4571                 return 0;
4572         case METRIC_SET_ID_COMPUTE_EXTRA:
4573                 dev_priv->perf.oa.n_mux_configs =
4574                         get_compute_extra_mux_config(dev_priv,
4575                                                      dev_priv->perf.oa.mux_regs,
4576                                                      dev_priv->perf.oa.mux_regs_lens);
4577                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4578                         DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
4579
4580                         /* EINVAL because *_register_sysfs already checked this
4581                          * and so it wouldn't have been advertised to userspace and
4582                          * so shouldn't have been requested
4583                          */
4584                         return -EINVAL;
4585                 }
4586
4587                 dev_priv->perf.oa.b_counter_regs =
4588                         b_counter_config_compute_extra;
4589                 dev_priv->perf.oa.b_counter_regs_len =
4590                         ARRAY_SIZE(b_counter_config_compute_extra);
4591
4592                 dev_priv->perf.oa.flex_regs =
4593                         flex_eu_config_compute_extra;
4594                 dev_priv->perf.oa.flex_regs_len =
4595                         ARRAY_SIZE(flex_eu_config_compute_extra);
4596
4597                 return 0;
4598         case METRIC_SET_ID_VME_PIPE:
4599                 dev_priv->perf.oa.n_mux_configs =
4600                         get_vme_pipe_mux_config(dev_priv,
4601                                                 dev_priv->perf.oa.mux_regs,
4602                                                 dev_priv->perf.oa.mux_regs_lens);
4603                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4604                         DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
4605
4606                         /* EINVAL because *_register_sysfs already checked this
4607                          * and so it wouldn't have been advertised to userspace and
4608                          * so shouldn't have been requested
4609                          */
4610                         return -EINVAL;
4611                 }
4612
4613                 dev_priv->perf.oa.b_counter_regs =
4614                         b_counter_config_vme_pipe;
4615                 dev_priv->perf.oa.b_counter_regs_len =
4616                         ARRAY_SIZE(b_counter_config_vme_pipe);
4617
4618                 dev_priv->perf.oa.flex_regs =
4619                         flex_eu_config_vme_pipe;
4620                 dev_priv->perf.oa.flex_regs_len =
4621                         ARRAY_SIZE(flex_eu_config_vme_pipe);
4622
4623                 return 0;
4624         case METRIC_SET_ID_TEST_OA:
4625                 dev_priv->perf.oa.n_mux_configs =
4626                         get_test_oa_mux_config(dev_priv,
4627                                                dev_priv->perf.oa.mux_regs,
4628                                                dev_priv->perf.oa.mux_regs_lens);
4629                 if (dev_priv->perf.oa.n_mux_configs == 0) {
4630                         DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
4631
4632                         /* EINVAL because *_register_sysfs already checked this
4633                          * and so it wouldn't have been advertised to userspace and
4634                          * so shouldn't have been requested
4635                          */
4636                         return -EINVAL;
4637                 }
4638
4639                 dev_priv->perf.oa.b_counter_regs =
4640                         b_counter_config_test_oa;
4641                 dev_priv->perf.oa.b_counter_regs_len =
4642                         ARRAY_SIZE(b_counter_config_test_oa);
4643
4644                 dev_priv->perf.oa.flex_regs =
4645                         flex_eu_config_test_oa;
4646                 dev_priv->perf.oa.flex_regs_len =
4647                         ARRAY_SIZE(flex_eu_config_test_oa);
4648
4649                 return 0;
4650         default:
4651                 return -ENODEV;
4652         }
4653 }
4654
4655 static ssize_t
4656 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
4657 {
4658         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
4659 }
4660
4661 static struct device_attribute dev_attr_render_basic_id = {
4662         .attr = { .name = "id", .mode = 0444 },
4663         .show = show_render_basic_id,
4664         .store = NULL,
4665 };
4666
4667 static struct attribute *attrs_render_basic[] = {
4668         &dev_attr_render_basic_id.attr,
4669         NULL,
4670 };
4671
4672 static struct attribute_group group_render_basic = {
4673         .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
4674         .attrs =  attrs_render_basic,
4675 };
4676
4677 static ssize_t
4678 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
4679 {
4680         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
4681 }
4682
4683 static struct device_attribute dev_attr_compute_basic_id = {
4684         .attr = { .name = "id", .mode = 0444 },
4685         .show = show_compute_basic_id,
4686         .store = NULL,
4687 };
4688
4689 static struct attribute *attrs_compute_basic[] = {
4690         &dev_attr_compute_basic_id.attr,
4691         NULL,
4692 };
4693
4694 static struct attribute_group group_compute_basic = {
4695         .name = "35fbc9b2-a891-40a6-a38d-022bb7057552",
4696         .attrs =  attrs_compute_basic,
4697 };
4698
4699 static ssize_t
4700 show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
4701 {
4702         return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
4703 }
4704
4705 static struct device_attribute dev_attr_render_pipe_profile_id = {
4706         .attr = { .name = "id", .mode = 0444 },
4707         .show = show_render_pipe_profile_id,
4708         .store = NULL,
4709 };
4710
4711 static struct attribute *attrs_render_pipe_profile[] = {
4712         &dev_attr_render_pipe_profile_id.attr,
4713         NULL,
4714 };
4715
4716 static struct attribute_group group_render_pipe_profile = {
4717         .name = "233d0544-fff7-4281-8291-e02f222aff72",
4718         .attrs =  attrs_render_pipe_profile,
4719 };
4720
4721 static ssize_t
4722 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
4723 {
4724         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
4725 }
4726
4727 static struct device_attribute dev_attr_memory_reads_id = {
4728         .attr = { .name = "id", .mode = 0444 },
4729         .show = show_memory_reads_id,
4730         .store = NULL,
4731 };
4732
4733 static struct attribute *attrs_memory_reads[] = {
4734         &dev_attr_memory_reads_id.attr,
4735         NULL,
4736 };
4737
4738 static struct attribute_group group_memory_reads = {
4739         .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c",
4740         .attrs =  attrs_memory_reads,
4741 };
4742
4743 static ssize_t
4744 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
4745 {
4746         return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
4747 }
4748
4749 static struct device_attribute dev_attr_memory_writes_id = {
4750         .attr = { .name = "id", .mode = 0444 },
4751         .show = show_memory_writes_id,
4752         .store = NULL,
4753 };
4754
4755 static struct attribute *attrs_memory_writes[] = {
4756         &dev_attr_memory_writes_id.attr,
4757         NULL,
4758 };
4759
4760 static struct attribute_group group_memory_writes = {
4761         .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c",
4762         .attrs =  attrs_memory_writes,
4763 };
4764
4765 static ssize_t
4766 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
4767 {
4768         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
4769 }
4770
4771 static struct device_attribute dev_attr_compute_extended_id = {
4772         .attr = { .name = "id", .mode = 0444 },
4773         .show = show_compute_extended_id,
4774         .store = NULL,
4775 };
4776
4777 static struct attribute *attrs_compute_extended[] = {
4778         &dev_attr_compute_extended_id.attr,
4779         NULL,
4780 };
4781
4782 static struct attribute_group group_compute_extended = {
4783         .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43",
4784         .attrs =  attrs_compute_extended,
4785 };
4786
4787 static ssize_t
4788 show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
4789 {
4790         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
4791 }
4792
4793 static struct device_attribute dev_attr_compute_l3_cache_id = {
4794         .attr = { .name = "id", .mode = 0444 },
4795         .show = show_compute_l3_cache_id,
4796         .store = NULL,
4797 };
4798
4799 static struct attribute *attrs_compute_l3_cache[] = {
4800         &dev_attr_compute_l3_cache_id.attr,
4801         NULL,
4802 };
4803
4804 static struct attribute_group group_compute_l3_cache = {
4805         .name = "27a364dc-8225-4ecb-b607-d6f1925598d9",
4806         .attrs =  attrs_compute_l3_cache,
4807 };
4808
4809 static ssize_t
4810 show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf)
4811 {
4812         return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING);
4813 }
4814
4815 static struct device_attribute dev_attr_data_port_reads_coalescing_id = {
4816         .attr = { .name = "id", .mode = 0444 },
4817         .show = show_data_port_reads_coalescing_id,
4818         .store = NULL,
4819 };
4820
4821 static struct attribute *attrs_data_port_reads_coalescing[] = {
4822         &dev_attr_data_port_reads_coalescing_id.attr,
4823         NULL,
4824 };
4825
4826 static struct attribute_group group_data_port_reads_coalescing = {
4827         .name = "857fc630-2f09-4804-85f1-084adfadd5ab",
4828         .attrs =  attrs_data_port_reads_coalescing,
4829 };
4830
4831 static ssize_t
4832 show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf)
4833 {
4834         return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING);
4835 }
4836
4837 static struct device_attribute dev_attr_data_port_writes_coalescing_id = {
4838         .attr = { .name = "id", .mode = 0444 },
4839         .show = show_data_port_writes_coalescing_id,
4840         .store = NULL,
4841 };
4842
4843 static struct attribute *attrs_data_port_writes_coalescing[] = {
4844         &dev_attr_data_port_writes_coalescing_id.attr,
4845         NULL,
4846 };
4847
4848 static struct attribute_group group_data_port_writes_coalescing = {
4849         .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20",
4850         .attrs =  attrs_data_port_writes_coalescing,
4851 };
4852
4853 static ssize_t
4854 show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
4855 {
4856         return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
4857 }
4858
4859 static struct device_attribute dev_attr_hdc_and_sf_id = {
4860         .attr = { .name = "id", .mode = 0444 },
4861         .show = show_hdc_and_sf_id,
4862         .store = NULL,
4863 };
4864
4865 static struct attribute *attrs_hdc_and_sf[] = {
4866         &dev_attr_hdc_and_sf_id.attr,
4867         NULL,
4868 };
4869
4870 static struct attribute_group group_hdc_and_sf = {
4871         .name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e",
4872         .attrs =  attrs_hdc_and_sf,
4873 };
4874
4875 static ssize_t
4876 show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
4877 {
4878         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
4879 }
4880
4881 static struct device_attribute dev_attr_l3_1_id = {
4882         .attr = { .name = "id", .mode = 0444 },
4883         .show = show_l3_1_id,
4884         .store = NULL,
4885 };
4886
4887 static struct attribute *attrs_l3_1[] = {
4888         &dev_attr_l3_1_id.attr,
4889         NULL,
4890 };
4891
4892 static struct attribute_group group_l3_1 = {
4893         .name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b",
4894         .attrs =  attrs_l3_1,
4895 };
4896
4897 static ssize_t
4898 show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
4899 {
4900         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
4901 }
4902
4903 static struct device_attribute dev_attr_l3_2_id = {
4904         .attr = { .name = "id", .mode = 0444 },
4905         .show = show_l3_2_id,
4906         .store = NULL,
4907 };
4908
4909 static struct attribute *attrs_l3_2[] = {
4910         &dev_attr_l3_2_id.attr,
4911         NULL,
4912 };
4913
4914 static struct attribute_group group_l3_2 = {
4915         .name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a",
4916         .attrs =  attrs_l3_2,
4917 };
4918
4919 static ssize_t
4920 show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
4921 {
4922         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
4923 }
4924
4925 static struct device_attribute dev_attr_l3_3_id = {
4926         .attr = { .name = "id", .mode = 0444 },
4927         .show = show_l3_3_id,
4928         .store = NULL,
4929 };
4930
4931 static struct attribute *attrs_l3_3[] = {
4932         &dev_attr_l3_3_id.attr,
4933         NULL,
4934 };
4935
4936 static struct attribute_group group_l3_3 = {
4937         .name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c",
4938         .attrs =  attrs_l3_3,
4939 };
4940
4941 static ssize_t
4942 show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf)
4943 {
4944         return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4);
4945 }
4946
4947 static struct device_attribute dev_attr_l3_4_id = {
4948         .attr = { .name = "id", .mode = 0444 },
4949         .show = show_l3_4_id,
4950         .store = NULL,
4951 };
4952
4953 static struct attribute *attrs_l3_4[] = {
4954         &dev_attr_l3_4_id.attr,
4955         NULL,
4956 };
4957
4958 static struct attribute_group group_l3_4 = {
4959         .name = "92b493d9-df18-4bed-be06-5cac6f2a6f5f",
4960         .attrs =  attrs_l3_4,
4961 };
4962
4963 static ssize_t
4964 show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
4965 {
4966         return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
4967 }
4968
4969 static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
4970         .attr = { .name = "id", .mode = 0444 },
4971         .show = show_rasterizer_and_pixel_backend_id,
4972         .store = NULL,
4973 };
4974
4975 static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
4976         &dev_attr_rasterizer_and_pixel_backend_id.attr,
4977         NULL,
4978 };
4979
4980 static struct attribute_group group_rasterizer_and_pixel_backend = {
4981         .name = "14345c35-cc46-40d0-bb04-6ed1fbb43679",
4982         .attrs =  attrs_rasterizer_and_pixel_backend,
4983 };
4984
4985 static ssize_t
4986 show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
4987 {
4988         return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1);
4989 }
4990
4991 static struct device_attribute dev_attr_sampler_1_id = {
4992         .attr = { .name = "id", .mode = 0444 },
4993         .show = show_sampler_1_id,
4994         .store = NULL,
4995 };
4996
4997 static struct attribute *attrs_sampler_1[] = {
4998         &dev_attr_sampler_1_id.attr,
4999         NULL,
5000 };
5001
5002 static struct attribute_group group_sampler_1 = {
5003         .name = "f0c6ba37-d3d3-4211-91b5-226730312a54",
5004         .attrs =  attrs_sampler_1,
5005 };
5006
5007 static ssize_t
5008 show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
5009 {
5010         return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2);
5011 }
5012
5013 static struct device_attribute dev_attr_sampler_2_id = {
5014         .attr = { .name = "id", .mode = 0444 },
5015         .show = show_sampler_2_id,
5016         .store = NULL,
5017 };
5018
5019 static struct attribute *attrs_sampler_2[] = {
5020         &dev_attr_sampler_2_id.attr,
5021         NULL,
5022 };
5023
5024 static struct attribute_group group_sampler_2 = {
5025         .name = "30bf3702-48cf-4bca-b412-7cf50bb2f564",
5026         .attrs =  attrs_sampler_2,
5027 };
5028
5029 static ssize_t
5030 show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
5031 {
5032         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
5033 }
5034
5035 static struct device_attribute dev_attr_tdl_1_id = {
5036         .attr = { .name = "id", .mode = 0444 },
5037         .show = show_tdl_1_id,
5038         .store = NULL,
5039 };
5040
5041 static struct attribute *attrs_tdl_1[] = {
5042         &dev_attr_tdl_1_id.attr,
5043         NULL,
5044 };
5045
5046 static struct attribute_group group_tdl_1 = {
5047         .name = "238bec85-df05-44f3-b905-d166712f2451",
5048         .attrs =  attrs_tdl_1,
5049 };
5050
5051 static ssize_t
5052 show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
5053 {
5054         return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
5055 }
5056
5057 static struct device_attribute dev_attr_tdl_2_id = {
5058         .attr = { .name = "id", .mode = 0444 },
5059         .show = show_tdl_2_id,
5060         .store = NULL,
5061 };
5062
5063 static struct attribute *attrs_tdl_2[] = {
5064         &dev_attr_tdl_2_id.attr,
5065         NULL,
5066 };
5067
5068 static struct attribute_group group_tdl_2 = {
5069         .name = "24bf02cd-8693-4583-981c-c4165b33da01",
5070         .attrs =  attrs_tdl_2,
5071 };
5072
5073 static ssize_t
5074 show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
5075 {
5076         return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
5077 }
5078
5079 static struct device_attribute dev_attr_compute_extra_id = {
5080         .attr = { .name = "id", .mode = 0444 },
5081         .show = show_compute_extra_id,
5082         .store = NULL,
5083 };
5084
5085 static struct attribute *attrs_compute_extra[] = {
5086         &dev_attr_compute_extra_id.attr,
5087         NULL,
5088 };
5089
5090 static struct attribute_group group_compute_extra = {
5091         .name = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e",
5092         .attrs =  attrs_compute_extra,
5093 };
5094
5095 static ssize_t
5096 show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
5097 {
5098         return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
5099 }
5100
5101 static struct device_attribute dev_attr_vme_pipe_id = {
5102         .attr = { .name = "id", .mode = 0444 },
5103         .show = show_vme_pipe_id,
5104         .store = NULL,
5105 };
5106
5107 static struct attribute *attrs_vme_pipe[] = {
5108         &dev_attr_vme_pipe_id.attr,
5109         NULL,
5110 };
5111
5112 static struct attribute_group group_vme_pipe = {
5113         .name = "e1743ca0-7fc8-410b-a066-de7bbb9280b7",
5114         .attrs =  attrs_vme_pipe,
5115 };
5116
5117 static ssize_t
5118 show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
5119 {
5120         return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
5121 }
5122
5123 static struct device_attribute dev_attr_test_oa_id = {
5124         .attr = { .name = "id", .mode = 0444 },
5125         .show = show_test_oa_id,
5126         .store = NULL,
5127 };
5128
5129 static struct attribute *attrs_test_oa[] = {
5130         &dev_attr_test_oa_id.attr,
5131         NULL,
5132 };
5133
5134 static struct attribute_group group_test_oa = {
5135         .name = "d6de6f55-e526-4f79-a6a6-d7315c09044e",
5136         .attrs =  attrs_test_oa,
5137 };
5138
5139 int
5140 i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv)
5141 {
5142         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
5143         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
5144         int ret = 0;
5145
5146         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
5147                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
5148                 if (ret)
5149                         goto error_render_basic;
5150         }
5151         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
5152                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
5153                 if (ret)
5154                         goto error_compute_basic;
5155         }
5156         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
5157                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
5158                 if (ret)
5159                         goto error_render_pipe_profile;
5160         }
5161         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
5162                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
5163                 if (ret)
5164                         goto error_memory_reads;
5165         }
5166         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
5167                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
5168                 if (ret)
5169                         goto error_memory_writes;
5170         }
5171         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
5172                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
5173                 if (ret)
5174                         goto error_compute_extended;
5175         }
5176         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
5177                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
5178                 if (ret)
5179                         goto error_compute_l3_cache;
5180         }
5181         if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) {
5182                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
5183                 if (ret)
5184                         goto error_data_port_reads_coalescing;
5185         }
5186         if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) {
5187                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
5188                 if (ret)
5189                         goto error_data_port_writes_coalescing;
5190         }
5191         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
5192                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
5193                 if (ret)
5194                         goto error_hdc_and_sf;
5195         }
5196         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
5197                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
5198                 if (ret)
5199                         goto error_l3_1;
5200         }
5201         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
5202                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
5203                 if (ret)
5204                         goto error_l3_2;
5205         }
5206         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
5207                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
5208                 if (ret)
5209                         goto error_l3_3;
5210         }
5211         if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) {
5212                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4);
5213                 if (ret)
5214                         goto error_l3_4;
5215         }
5216         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
5217                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
5218                 if (ret)
5219                         goto error_rasterizer_and_pixel_backend;
5220         }
5221         if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) {
5222                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
5223                 if (ret)
5224                         goto error_sampler_1;
5225         }
5226         if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) {
5227                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
5228                 if (ret)
5229                         goto error_sampler_2;
5230         }
5231         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
5232                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
5233                 if (ret)
5234                         goto error_tdl_1;
5235         }
5236         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
5237                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
5238                 if (ret)
5239                         goto error_tdl_2;
5240         }
5241         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
5242                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
5243                 if (ret)
5244                         goto error_compute_extra;
5245         }
5246         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
5247                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
5248                 if (ret)
5249                         goto error_vme_pipe;
5250         }
5251         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
5252                 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
5253                 if (ret)
5254                         goto error_test_oa;
5255         }
5256
5257         return 0;
5258
5259 error_test_oa:
5260         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
5261                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
5262 error_vme_pipe:
5263         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
5264                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
5265 error_compute_extra:
5266         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
5267                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
5268 error_tdl_2:
5269         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
5270                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
5271 error_tdl_1:
5272         if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
5273                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
5274 error_sampler_2:
5275         if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
5276                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
5277 error_sampler_1:
5278         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
5279                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
5280 error_rasterizer_and_pixel_backend:
5281         if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
5282                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
5283 error_l3_4:
5284         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
5285                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
5286 error_l3_3:
5287         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
5288                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
5289 error_l3_2:
5290         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
5291                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
5292 error_l3_1:
5293         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
5294                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
5295 error_hdc_and_sf:
5296         if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
5297                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
5298 error_data_port_writes_coalescing:
5299         if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
5300                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
5301 error_data_port_reads_coalescing:
5302         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
5303                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
5304 error_compute_l3_cache:
5305         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
5306                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
5307 error_compute_extended:
5308         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
5309                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
5310 error_memory_writes:
5311         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
5312                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
5313 error_memory_reads:
5314         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
5315                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
5316 error_render_pipe_profile:
5317         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
5318                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
5319 error_compute_basic:
5320         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
5321                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
5322 error_render_basic:
5323         return ret;
5324 }
5325
5326 void
5327 i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv)
5328 {
5329         const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
5330         int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
5331
5332         if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
5333                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
5334         if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
5335                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
5336         if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
5337                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
5338         if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
5339                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
5340         if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
5341                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
5342         if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
5343                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
5344         if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
5345                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
5346         if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
5347                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
5348         if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
5349                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
5350         if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
5351                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
5352         if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
5353                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
5354         if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
5355                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
5356         if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
5357                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
5358         if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
5359                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
5360         if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
5361                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
5362         if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
5363                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
5364         if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
5365                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
5366         if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
5367                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
5368         if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
5369                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
5370         if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
5371                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
5372         if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
5373                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
5374         if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
5375                 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
5376 }