2 * Copyright © 2008-2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
27 #include <linux/sched.h>
28 #include <linux/sched/clock.h>
29 #include <linux/sched/signal.h>
33 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
38 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
40 /* The timeline struct (as part of the ppgtt underneath a context)
41 * may be freed when the request is no longer in use by the GPU.
42 * We could extend the life of a context to beyond that of all
43 * fences, possibly keeping the hw resource around indefinitely,
44 * or we just give them a false name. Since
45 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
46 * lie seems justifiable.
48 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
51 return to_request(fence)->timeline->common->name;
54 static bool i915_fence_signaled(struct dma_fence *fence)
56 return i915_gem_request_completed(to_request(fence));
59 static bool i915_fence_enable_signaling(struct dma_fence *fence)
61 if (i915_fence_signaled(fence))
64 intel_engine_enable_signaling(to_request(fence), true);
65 return !i915_fence_signaled(fence);
68 static signed long i915_fence_wait(struct dma_fence *fence,
72 return i915_wait_request(to_request(fence), interruptible, timeout);
75 static void i915_fence_release(struct dma_fence *fence)
77 struct drm_i915_gem_request *req = to_request(fence);
79 /* The request is put onto a RCU freelist (i.e. the address
80 * is immediately reused), mark the fences as being freed now.
81 * Otherwise the debugobjects for the fences are only marked as
82 * freed when the slab cache itself is freed, and so we would get
83 * caught trying to reuse dead objects.
85 i915_sw_fence_fini(&req->submit);
87 kmem_cache_free(req->i915->requests, req);
90 const struct dma_fence_ops i915_fence_ops = {
91 .get_driver_name = i915_fence_get_driver_name,
92 .get_timeline_name = i915_fence_get_timeline_name,
93 .enable_signaling = i915_fence_enable_signaling,
94 .signaled = i915_fence_signaled,
95 .wait = i915_fence_wait,
96 .release = i915_fence_release,
100 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
102 struct drm_i915_file_private *file_priv;
104 file_priv = request->file_priv;
108 spin_lock(&file_priv->mm.lock);
109 if (request->file_priv) {
110 list_del(&request->client_link);
111 request->file_priv = NULL;
113 spin_unlock(&file_priv->mm.lock);
116 static struct i915_dependency *
117 i915_dependency_alloc(struct drm_i915_private *i915)
119 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
123 i915_dependency_free(struct drm_i915_private *i915,
124 struct i915_dependency *dep)
126 kmem_cache_free(i915->dependencies, dep);
130 __i915_priotree_add_dependency(struct i915_priotree *pt,
131 struct i915_priotree *signal,
132 struct i915_dependency *dep,
135 INIT_LIST_HEAD(&dep->dfs_link);
136 list_add(&dep->wait_link, &signal->waiters_list);
137 list_add(&dep->signal_link, &pt->signalers_list);
138 dep->signaler = signal;
143 i915_priotree_add_dependency(struct drm_i915_private *i915,
144 struct i915_priotree *pt,
145 struct i915_priotree *signal)
147 struct i915_dependency *dep;
149 dep = i915_dependency_alloc(i915);
153 __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
158 i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
160 struct i915_dependency *dep, *next;
162 GEM_BUG_ON(!list_empty(&pt->link));
164 /* Everyone we depended upon (the fences we wait to be signaled)
165 * should retire before us and remove themselves from our list.
166 * However, retirement is run independently on each timeline and
167 * so we may be called out-of-order.
169 list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
170 list_del(&dep->wait_link);
171 if (dep->flags & I915_DEPENDENCY_ALLOC)
172 i915_dependency_free(i915, dep);
175 /* Remove ourselves from everyone who depends upon us */
176 list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
177 list_del(&dep->signal_link);
178 if (dep->flags & I915_DEPENDENCY_ALLOC)
179 i915_dependency_free(i915, dep);
184 i915_priotree_init(struct i915_priotree *pt)
186 INIT_LIST_HEAD(&pt->signalers_list);
187 INIT_LIST_HEAD(&pt->waiters_list);
188 INIT_LIST_HEAD(&pt->link);
189 pt->priority = I915_PRIORITY_INVALID;
192 static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
194 struct intel_engine_cs *engine;
195 enum intel_engine_id id;
198 /* Carefully retire all requests without writing to the rings */
199 ret = i915_gem_wait_for_idle(i915,
200 I915_WAIT_INTERRUPTIBLE |
205 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
206 for_each_engine(engine, i915, id) {
207 struct i915_gem_timeline *timeline;
208 struct intel_timeline *tl = engine->timeline;
210 if (!i915_seqno_passed(seqno, tl->seqno)) {
211 /* spin until threads are complete */
212 while (intel_breadcrumbs_busy(engine))
216 /* Check we are idle before we fiddle with hw state! */
217 GEM_BUG_ON(!intel_engine_is_idle(engine));
218 GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request));
220 /* Finally reset hw state */
221 intel_engine_init_global_seqno(engine, seqno);
224 list_for_each_entry(timeline, &i915->gt.timelines, link)
225 memset(timeline->engine[id].global_sync, 0,
226 sizeof(timeline->engine[id].global_sync));
232 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
234 struct drm_i915_private *dev_priv = to_i915(dev);
236 lockdep_assert_held(&dev_priv->drm.struct_mutex);
241 /* HWS page needs to be set less than what we
242 * will inject to ring
244 return reset_all_global_seqno(dev_priv, seqno - 1);
247 static void mark_busy(struct drm_i915_private *i915)
252 GEM_BUG_ON(!i915->gt.active_requests);
254 intel_runtime_pm_get_noresume(i915);
257 * It seems that the DMC likes to transition between the DC states a lot
258 * when there are no connected displays (no active power domains) during
259 * command submission.
261 * This activity has negative impact on the performance of the chip with
262 * huge latencies observed in the interrupt handler and elsewhere.
264 * Work around it by grabbing a GT IRQ power domain whilst there is any
265 * GT activity, preventing any DC state transitions.
267 intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
269 i915->gt.awake = true;
271 intel_enable_gt_powersave(i915);
272 i915_update_gfx_val(i915);
273 if (INTEL_GEN(i915) >= 6)
275 i915_pmu_gt_unparked(i915);
277 intel_engines_unpark(i915);
279 queue_delayed_work(i915->wq,
280 &i915->gt.retire_work,
281 round_jiffies_up_relative(HZ));
284 static int reserve_engine(struct intel_engine_cs *engine)
286 struct drm_i915_private *i915 = engine->i915;
287 u32 active = ++engine->timeline->inflight_seqnos;
288 u32 seqno = engine->timeline->seqno;
291 /* Reservation is fine until we need to wrap around */
292 if (unlikely(add_overflows(seqno, active))) {
293 ret = reset_all_global_seqno(i915, 0);
295 engine->timeline->inflight_seqnos--;
300 if (!i915->gt.active_requests++)
306 static void unreserve_engine(struct intel_engine_cs *engine)
308 struct drm_i915_private *i915 = engine->i915;
310 if (!--i915->gt.active_requests) {
311 /* Cancel the mark_busy() from our reserve_engine() */
312 GEM_BUG_ON(!i915->gt.awake);
313 mod_delayed_work(i915->wq,
315 msecs_to_jiffies(100));
318 GEM_BUG_ON(!engine->timeline->inflight_seqnos);
319 engine->timeline->inflight_seqnos--;
322 void i915_gem_retire_noop(struct i915_gem_active *active,
323 struct drm_i915_gem_request *request)
325 /* Space left intentionally blank */
328 static void advance_ring(struct drm_i915_gem_request *request)
332 /* We know the GPU must have read the request to have
333 * sent us the seqno + interrupt, so use the position
334 * of tail of the request to update the last known position
337 * Note this requires that we are always called in request
340 if (list_is_last(&request->ring_link, &request->ring->request_list)) {
341 /* We may race here with execlists resubmitting this request
342 * as we retire it. The resubmission will move the ring->tail
343 * forwards (to request->wa_tail). We either read the
344 * current value that was written to hw, or the value that
345 * is just about to be. Either works, if we miss the last two
346 * noops - they are safe to be replayed on a reset.
348 tail = READ_ONCE(request->ring->tail);
350 tail = request->postfix;
352 list_del(&request->ring_link);
354 request->ring->head = tail;
357 static void free_capture_list(struct drm_i915_gem_request *request)
359 struct i915_gem_capture_list *capture;
361 capture = request->capture_list;
363 struct i915_gem_capture_list *next = capture->next;
370 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
372 struct intel_engine_cs *engine = request->engine;
373 struct i915_gem_active *active, *next;
375 lockdep_assert_held(&request->i915->drm.struct_mutex);
376 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
377 GEM_BUG_ON(!i915_gem_request_completed(request));
378 GEM_BUG_ON(!request->i915->gt.active_requests);
380 trace_i915_gem_request_retire(request);
382 spin_lock_irq(&engine->timeline->lock);
383 list_del_init(&request->link);
384 spin_unlock_irq(&engine->timeline->lock);
386 unreserve_engine(request->engine);
387 advance_ring(request);
389 free_capture_list(request);
391 /* Walk through the active list, calling retire on each. This allows
392 * objects to track their GPU activity and mark themselves as idle
393 * when their *last* active request is completed (updating state
394 * tracking lists for eviction, active references for GEM, etc).
396 * As the ->retire() may free the node, we decouple it first and
397 * pass along the auxiliary information (to avoid dereferencing
398 * the node after the callback).
400 list_for_each_entry_safe(active, next, &request->active_list, link) {
401 /* In microbenchmarks or focusing upon time inside the kernel,
402 * we may spend an inordinate amount of time simply handling
403 * the retirement of requests and processing their callbacks.
404 * Of which, this loop itself is particularly hot due to the
405 * cache misses when jumping around the list of i915_gem_active.
406 * So we try to keep this loop as streamlined as possible and
407 * also prefetch the next i915_gem_active to try and hide
408 * the likely cache miss.
412 INIT_LIST_HEAD(&active->link);
413 RCU_INIT_POINTER(active->request, NULL);
415 active->retire(active, request);
418 i915_gem_request_remove_from_client(request);
420 /* Retirement decays the ban score as it is a sign of ctx progress */
421 atomic_dec_if_positive(&request->ctx->ban_score);
423 /* The backing object for the context is done after switching to the
424 * *next* context. Therefore we cannot retire the previous context until
425 * the next context has already started running. However, since we
426 * cannot take the required locks at i915_gem_request_submit() we
427 * defer the unpinning of the active context to now, retirement of
428 * the subsequent request.
430 if (engine->last_retired_context)
431 engine->context_unpin(engine, engine->last_retired_context);
432 engine->last_retired_context = request->ctx;
434 spin_lock_irq(&request->lock);
435 if (request->waitboost)
436 atomic_dec(&request->i915->gt_pm.rps.num_waiters);
437 dma_fence_signal_locked(&request->fence);
438 spin_unlock_irq(&request->lock);
440 i915_priotree_fini(request->i915, &request->priotree);
441 i915_gem_request_put(request);
444 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
446 struct intel_engine_cs *engine = req->engine;
447 struct drm_i915_gem_request *tmp;
449 lockdep_assert_held(&req->i915->drm.struct_mutex);
450 GEM_BUG_ON(!i915_gem_request_completed(req));
452 if (list_empty(&req->link))
456 tmp = list_first_entry(&engine->timeline->requests,
459 i915_gem_request_retire(tmp);
460 } while (tmp != req);
463 static u32 timeline_get_seqno(struct intel_timeline *tl)
468 void __i915_gem_request_submit(struct drm_i915_gem_request *request)
470 struct intel_engine_cs *engine = request->engine;
471 struct intel_timeline *timeline;
474 GEM_BUG_ON(!irqs_disabled());
475 lockdep_assert_held(&engine->timeline->lock);
477 trace_i915_gem_request_execute(request);
479 /* Transfer from per-context onto the global per-engine timeline */
480 timeline = engine->timeline;
481 GEM_BUG_ON(timeline == request->timeline);
482 GEM_BUG_ON(request->global_seqno);
484 seqno = timeline_get_seqno(timeline);
486 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
488 /* We may be recursing from the signal callback of another i915 fence */
489 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
490 request->global_seqno = seqno;
491 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
492 intel_engine_enable_signaling(request, false);
493 spin_unlock(&request->lock);
495 engine->emit_breadcrumb(request,
496 request->ring->vaddr + request->postfix);
498 spin_lock(&request->timeline->lock);
499 list_move_tail(&request->link, &timeline->requests);
500 spin_unlock(&request->timeline->lock);
502 wake_up_all(&request->execute);
505 void i915_gem_request_submit(struct drm_i915_gem_request *request)
507 struct intel_engine_cs *engine = request->engine;
510 /* Will be called from irq-context when using foreign fences. */
511 spin_lock_irqsave(&engine->timeline->lock, flags);
513 __i915_gem_request_submit(request);
515 spin_unlock_irqrestore(&engine->timeline->lock, flags);
518 void __i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
520 struct intel_engine_cs *engine = request->engine;
521 struct intel_timeline *timeline;
523 GEM_BUG_ON(!irqs_disabled());
524 lockdep_assert_held(&engine->timeline->lock);
526 /* Only unwind in reverse order, required so that the per-context list
527 * is kept in seqno/ring order.
529 GEM_BUG_ON(!request->global_seqno);
530 GEM_BUG_ON(request->global_seqno != engine->timeline->seqno);
531 engine->timeline->seqno--;
533 /* We may be recursing from the signal callback of another i915 fence */
534 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
535 request->global_seqno = 0;
536 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
537 intel_engine_cancel_signaling(request);
538 spin_unlock(&request->lock);
540 /* Transfer back from the global per-engine timeline to per-context */
541 timeline = request->timeline;
542 GEM_BUG_ON(timeline == engine->timeline);
544 spin_lock(&timeline->lock);
545 list_move(&request->link, &timeline->requests);
546 spin_unlock(&timeline->lock);
548 /* We don't need to wake_up any waiters on request->execute, they
549 * will get woken by any other event or us re-adding this request
550 * to the engine timeline (__i915_gem_request_submit()). The waiters
551 * should be quite adapt at finding that the request now has a new
552 * global_seqno to the one they went to sleep on.
556 void i915_gem_request_unsubmit(struct drm_i915_gem_request *request)
558 struct intel_engine_cs *engine = request->engine;
561 /* Will be called from irq-context when using foreign fences. */
562 spin_lock_irqsave(&engine->timeline->lock, flags);
564 __i915_gem_request_unsubmit(request);
566 spin_unlock_irqrestore(&engine->timeline->lock, flags);
569 static int __i915_sw_fence_call
570 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
572 struct drm_i915_gem_request *request =
573 container_of(fence, typeof(*request), submit);
577 trace_i915_gem_request_submit(request);
579 * We need to serialize use of the submit_request() callback with its
580 * hotplugging performed during an emergency i915_gem_set_wedged().
581 * We use the RCU mechanism to mark the critical section in order to
582 * force i915_gem_set_wedged() to wait until the submit_request() is
583 * completed before proceeding.
586 request->engine->submit_request(request);
591 i915_gem_request_put(request);
599 * i915_gem_request_alloc - allocate a request structure
601 * @engine: engine that we wish to issue the request on.
602 * @ctx: context that the request will be associated with.
604 * Returns a pointer to the allocated request if successful,
605 * or an error code if not.
607 struct drm_i915_gem_request *
608 i915_gem_request_alloc(struct intel_engine_cs *engine,
609 struct i915_gem_context *ctx)
611 struct drm_i915_private *dev_priv = engine->i915;
612 struct drm_i915_gem_request *req;
613 struct intel_ring *ring;
616 lockdep_assert_held(&dev_priv->drm.struct_mutex);
619 * Preempt contexts are reserved for exclusive use to inject a
620 * preemption context switch. They are never to be used for any trivial
623 GEM_BUG_ON(ctx == dev_priv->preempt_context);
625 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
626 * EIO if the GPU is already wedged.
628 if (i915_terminally_wedged(&dev_priv->gpu_error))
629 return ERR_PTR(-EIO);
631 /* Pinning the contexts may generate requests in order to acquire
632 * GGTT space, so do this first before we reserve a seqno for
635 ring = engine->context_pin(engine, ctx);
637 return ERR_CAST(ring);
640 ret = reserve_engine(engine);
644 ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST);
648 /* Move the oldest request to the slab-cache (if not in use!) */
649 req = list_first_entry_or_null(&engine->timeline->requests,
651 if (req && i915_gem_request_completed(req))
652 i915_gem_request_retire(req);
654 /* Beware: Dragons be flying overhead.
656 * We use RCU to look up requests in flight. The lookups may
657 * race with the request being allocated from the slab freelist.
658 * That is the request we are writing to here, may be in the process
659 * of being read by __i915_gem_active_get_rcu(). As such,
660 * we have to be very careful when overwriting the contents. During
661 * the RCU lookup, we change chase the request->engine pointer,
662 * read the request->global_seqno and increment the reference count.
664 * The reference count is incremented atomically. If it is zero,
665 * the lookup knows the request is unallocated and complete. Otherwise,
666 * it is either still in use, or has been reallocated and reset
667 * with dma_fence_init(). This increment is safe for release as we
668 * check that the request we have a reference to and matches the active
671 * Before we increment the refcount, we chase the request->engine
672 * pointer. We must not call kmem_cache_zalloc() or else we set
673 * that pointer to NULL and cause a crash during the lookup. If
674 * we see the request is completed (based on the value of the
675 * old engine and seqno), the lookup is complete and reports NULL.
676 * If we decide the request is not completed (new engine or seqno),
677 * then we grab a reference and double check that it is still the
678 * active request - which it won't be and restart the lookup.
680 * Do not use kmem_cache_zalloc() here!
682 req = kmem_cache_alloc(dev_priv->requests,
683 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
684 if (unlikely(!req)) {
685 /* Ratelimit ourselves to prevent oom from malicious clients */
686 ret = i915_gem_wait_for_idle(dev_priv,
688 I915_WAIT_INTERRUPTIBLE);
692 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
699 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
700 GEM_BUG_ON(req->timeline == engine->timeline);
702 spin_lock_init(&req->lock);
703 dma_fence_init(&req->fence,
706 req->timeline->fence_context,
707 timeline_get_seqno(req->timeline));
709 /* We bump the ref for the fence chain */
710 i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
711 init_waitqueue_head(&req->execute);
713 i915_priotree_init(&req->priotree);
715 INIT_LIST_HEAD(&req->active_list);
716 req->i915 = dev_priv;
717 req->engine = engine;
721 /* No zalloc, must clear what we need by hand */
722 req->global_seqno = 0;
723 req->file_priv = NULL;
725 req->capture_list = NULL;
726 req->waitboost = false;
729 * Reserve space in the ring buffer for all the commands required to
730 * eventually emit this request. This is to guarantee that the
731 * i915_add_request() call can't fail. Note that the reserve may need
732 * to be redone if the request is not actually submitted straight
733 * away, e.g. because a GPU scheduler has deferred it.
735 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
736 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
739 * Record the position of the start of the request so that
740 * should we detect the updated seqno part-way through the
741 * GPU processing the request, we never over-estimate the
742 * position of the head.
744 req->head = req->ring->emit;
746 /* Unconditionally invalidate GPU caches and TLBs. */
747 ret = engine->emit_flush(req, EMIT_INVALIDATE);
751 ret = engine->request_alloc(req);
755 /* Check that we didn't interrupt ourselves with a new request */
756 GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
760 req->ring->emit = req->head;
762 /* Make sure we didn't add ourselves to external state before freeing */
763 GEM_BUG_ON(!list_empty(&req->active_list));
764 GEM_BUG_ON(!list_empty(&req->priotree.signalers_list));
765 GEM_BUG_ON(!list_empty(&req->priotree.waiters_list));
767 kmem_cache_free(dev_priv->requests, req);
769 unreserve_engine(engine);
771 engine->context_unpin(engine, ctx);
776 i915_gem_request_await_request(struct drm_i915_gem_request *to,
777 struct drm_i915_gem_request *from)
781 GEM_BUG_ON(to == from);
782 GEM_BUG_ON(to->timeline == from->timeline);
784 if (i915_gem_request_completed(from))
787 if (to->engine->schedule) {
788 ret = i915_priotree_add_dependency(to->i915,
795 if (to->engine == from->engine) {
796 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
799 return ret < 0 ? ret : 0;
802 if (to->engine->semaphore.sync_to) {
805 GEM_BUG_ON(!from->engine->semaphore.signal);
807 seqno = i915_gem_request_global_seqno(from);
809 goto await_dma_fence;
811 if (seqno <= to->timeline->global_sync[from->engine->id])
814 trace_i915_gem_ring_sync_to(to, from);
815 ret = to->engine->semaphore.sync_to(to, from);
819 to->timeline->global_sync[from->engine->id] = seqno;
824 ret = i915_sw_fence_await_dma_fence(&to->submit,
827 return ret < 0 ? ret : 0;
831 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
832 struct dma_fence *fence)
834 struct dma_fence **child = &fence;
835 unsigned int nchild = 1;
838 /* Note that if the fence-array was created in signal-on-any mode,
839 * we should *not* decompose it into its individual fences. However,
840 * we don't currently store which mode the fence-array is operating
841 * in. Fortunately, the only user of signal-on-any is private to
842 * amdgpu and we should not see any incoming fence-array from
843 * sync-file being in signal-on-any mode.
845 if (dma_fence_is_array(fence)) {
846 struct dma_fence_array *array = to_dma_fence_array(fence);
848 child = array->fences;
849 nchild = array->num_fences;
855 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
859 * Requests on the same timeline are explicitly ordered, along
860 * with their dependencies, by i915_add_request() which ensures
861 * that requests are submitted in-order through each ring.
863 if (fence->context == req->fence.context)
866 /* Squash repeated waits to the same timelines */
867 if (fence->context != req->i915->mm.unordered_timeline &&
868 intel_timeline_sync_is_later(req->timeline, fence))
871 if (dma_fence_is_i915(fence))
872 ret = i915_gem_request_await_request(req,
875 ret = i915_sw_fence_await_dma_fence(&req->submit, fence,
881 /* Record the latest fence used against each timeline */
882 if (fence->context != req->i915->mm.unordered_timeline)
883 intel_timeline_sync_set(req->timeline, fence);
890 * i915_gem_request_await_object - set this request to (async) wait upon a bo
892 * @to: request we are wishing to use
893 * @obj: object which may be in use on another ring.
895 * This code is meant to abstract object synchronization with the GPU.
896 * Conceptually we serialise writes between engines inside the GPU.
897 * We only allow one engine to write into a buffer at any time, but
898 * multiple readers. To ensure each has a coherent view of memory, we must:
900 * - If there is an outstanding write request to the object, the new
901 * request must wait for it to complete (either CPU or in hw, requests
902 * on the same ring will be naturally ordered).
904 * - If we are a write request (pending_write_domain is set), the new
905 * request must wait for outstanding read requests to complete.
907 * Returns 0 if successful, else propagates up the lower layer error.
910 i915_gem_request_await_object(struct drm_i915_gem_request *to,
911 struct drm_i915_gem_object *obj,
914 struct dma_fence *excl;
918 struct dma_fence **shared;
919 unsigned int count, i;
921 ret = reservation_object_get_fences_rcu(obj->resv,
922 &excl, &count, &shared);
926 for (i = 0; i < count; i++) {
927 ret = i915_gem_request_await_dma_fence(to, shared[i]);
931 dma_fence_put(shared[i]);
934 for (; i < count; i++)
935 dma_fence_put(shared[i]);
938 excl = reservation_object_get_excl_rcu(obj->resv);
943 ret = i915_gem_request_await_dma_fence(to, excl);
952 * NB: This function is not allowed to fail. Doing so would mean the the
953 * request is not being tracked for completion but the work itself is
954 * going to happen on the hardware. This would be a Bad Thing(tm).
956 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
958 struct intel_engine_cs *engine = request->engine;
959 struct intel_ring *ring = request->ring;
960 struct intel_timeline *timeline = request->timeline;
961 struct drm_i915_gem_request *prev;
965 lockdep_assert_held(&request->i915->drm.struct_mutex);
966 trace_i915_gem_request_add(request);
968 /* Make sure that no request gazumped us - if it was allocated after
969 * our i915_gem_request_alloc() and called __i915_add_request() before
970 * us, the timeline will hold its seqno which is later than ours.
972 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
975 * To ensure that this call will not fail, space for its emissions
976 * should already have been reserved in the ring buffer. Let the ring
977 * know that it is time to use that space up.
979 request->reserved_space = 0;
982 * Emit any outstanding flushes - execbuf can fail to emit the flush
983 * after having emitted the batchbuffer command. Hence we need to fix
984 * things up similar to emitting the lazy request. The difference here
985 * is that the flush _must_ happen before the next request, no matter
989 err = engine->emit_flush(request, EMIT_FLUSH);
991 /* Not allowed to fail! */
992 WARN(err, "engine->emit_flush() failed: %d!\n", err);
995 /* Record the position of the start of the breadcrumb so that
996 * should we detect the updated seqno part-way through the
997 * GPU processing the request, we never over-estimate the
998 * position of the ring's HEAD.
1000 cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
1001 GEM_BUG_ON(IS_ERR(cs));
1002 request->postfix = intel_ring_offset(request, cs);
1004 /* Seal the request and mark it as pending execution. Note that
1005 * we may inspect this state, without holding any locks, during
1006 * hangcheck. Hence we apply the barrier to ensure that we do not
1007 * see a more recent value in the hws than we are tracking.
1010 prev = i915_gem_active_raw(&timeline->last_request,
1011 &request->i915->drm.struct_mutex);
1013 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
1015 if (engine->schedule)
1016 __i915_priotree_add_dependency(&request->priotree,
1022 spin_lock_irq(&timeline->lock);
1023 list_add_tail(&request->link, &timeline->requests);
1024 spin_unlock_irq(&timeline->lock);
1026 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
1027 i915_gem_active_set(&timeline->last_request, request);
1029 list_add_tail(&request->ring_link, &ring->request_list);
1030 request->emitted_jiffies = jiffies;
1032 /* Let the backend know a new request has arrived that may need
1033 * to adjust the existing execution schedule due to a high priority
1034 * request - i.e. we may want to preempt the current request in order
1035 * to run a high priority dependency chain *before* we can execute this
1038 * This is called before the request is ready to run so that we can
1039 * decide whether to preempt the entire chain so that it is ready to
1040 * run at the earliest possible convenience.
1042 if (engine->schedule)
1043 engine->schedule(request, request->ctx->priority);
1046 i915_sw_fence_commit(&request->submit);
1047 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1050 static unsigned long local_clock_us(unsigned int *cpu)
1054 /* Cheaply and approximately convert from nanoseconds to microseconds.
1055 * The result and subsequent calculations are also defined in the same
1056 * approximate microseconds units. The principal source of timing
1057 * error here is from the simple truncation.
1059 * Note that local_clock() is only defined wrt to the current CPU;
1060 * the comparisons are no longer valid if we switch CPUs. Instead of
1061 * blocking preemption for the entire busywait, we can detect the CPU
1062 * switch and use that as indicator of system load and a reason to
1063 * stop busywaiting, see busywait_stop().
1066 t = local_clock() >> 10;
1072 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1074 unsigned int this_cpu;
1076 if (time_after(local_clock_us(&this_cpu), timeout))
1079 return this_cpu != cpu;
1082 static bool __i915_spin_request(const struct drm_i915_gem_request *req,
1083 u32 seqno, int state, unsigned long timeout_us)
1085 struct intel_engine_cs *engine = req->engine;
1086 unsigned int irq, cpu;
1091 * Only wait for the request if we know it is likely to complete.
1093 * We don't track the timestamps around requests, nor the average
1094 * request length, so we do not have a good indicator that this
1095 * request will complete within the timeout. What we do know is the
1096 * order in which requests are executed by the engine and so we can
1097 * tell if the request has started. If the request hasn't started yet,
1098 * it is a fair assumption that it will not complete within our
1099 * relatively short timeout.
1101 if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1))
1104 /* When waiting for high frequency requests, e.g. during synchronous
1105 * rendering split between the CPU and GPU, the finite amount of time
1106 * required to set up the irq and wait upon it limits the response
1107 * rate. By busywaiting on the request completion for a short while we
1108 * can service the high frequency waits as quick as possible. However,
1109 * if it is a slow request, we want to sleep as quickly as possible.
1110 * The tradeoff between waiting and sleeping is roughly the time it
1111 * takes to sleep on a request, on the order of a microsecond.
1114 irq = atomic_read(&engine->irq_count);
1115 timeout_us += local_clock_us(&cpu);
1117 if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
1118 return seqno == i915_gem_request_global_seqno(req);
1120 /* Seqno are meant to be ordered *before* the interrupt. If
1121 * we see an interrupt without a corresponding seqno advance,
1122 * assume we won't see one in the near future but require
1123 * the engine->seqno_barrier() to fixup coherency.
1125 if (atomic_read(&engine->irq_count) != irq)
1128 if (signal_pending_state(state, current))
1131 if (busywait_stop(timeout_us, cpu))
1135 } while (!need_resched());
1140 static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *request)
1142 if (likely(!i915_reset_handoff(&request->i915->gpu_error)))
1145 __set_current_state(TASK_RUNNING);
1146 i915_reset(request->i915, 0);
1151 * i915_wait_request - wait until execution of request has finished
1152 * @req: the request to wait upon
1153 * @flags: how to wait
1154 * @timeout: how long to wait in jiffies
1156 * i915_wait_request() waits for the request to be completed, for a
1157 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1160 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1161 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1162 * must not specify that the wait is locked.
1164 * Returns the remaining time (in jiffies) if the request completed, which may
1165 * be zero or -ETIME if the request is unfinished after the timeout expires.
1166 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1167 * pending before the request completes.
1169 long i915_wait_request(struct drm_i915_gem_request *req,
1173 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1174 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1175 wait_queue_head_t *errq = &req->i915->gpu_error.wait_queue;
1176 DEFINE_WAIT_FUNC(reset, default_wake_function);
1177 DEFINE_WAIT_FUNC(exec, default_wake_function);
1178 struct intel_wait wait;
1181 #if IS_ENABLED(CONFIG_LOCKDEP)
1182 GEM_BUG_ON(debug_locks &&
1183 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
1184 !!(flags & I915_WAIT_LOCKED));
1186 GEM_BUG_ON(timeout < 0);
1188 if (i915_gem_request_completed(req))
1194 trace_i915_gem_request_wait_begin(req, flags);
1196 add_wait_queue(&req->execute, &exec);
1197 if (flags & I915_WAIT_LOCKED)
1198 add_wait_queue(errq, &reset);
1200 intel_wait_init(&wait, req);
1204 set_current_state(state);
1205 if (intel_wait_update_request(&wait, req))
1208 if (flags & I915_WAIT_LOCKED &&
1209 __i915_wait_request_check_and_reset(req))
1212 if (signal_pending_state(state, current)) {
1213 timeout = -ERESTARTSYS;
1222 timeout = io_schedule_timeout(timeout);
1225 GEM_BUG_ON(!intel_wait_has_seqno(&wait));
1226 GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
1228 /* Optimistic short spin before touching IRQs */
1229 if (__i915_spin_request(req, wait.seqno, state, 5))
1232 set_current_state(state);
1233 if (intel_engine_add_wait(req->engine, &wait))
1234 /* In order to check that we haven't missed the interrupt
1235 * as we enabled it, we need to kick ourselves to do a
1236 * coherent check on the seqno before we sleep.
1240 if (flags & I915_WAIT_LOCKED)
1241 __i915_wait_request_check_and_reset(req);
1244 if (signal_pending_state(state, current)) {
1245 timeout = -ERESTARTSYS;
1254 timeout = io_schedule_timeout(timeout);
1256 if (intel_wait_complete(&wait) &&
1257 intel_wait_check_request(&wait, req))
1260 set_current_state(state);
1263 /* Carefully check if the request is complete, giving time
1264 * for the seqno to be visible following the interrupt.
1265 * We also have to check in case we are kicked by the GPU
1266 * reset in order to drop the struct_mutex.
1268 if (__i915_request_irq_complete(req))
1271 /* If the GPU is hung, and we hold the lock, reset the GPU
1272 * and then check for completion. On a full reset, the engine's
1273 * HW seqno will be advanced passed us and we are complete.
1274 * If we do a partial reset, we have to wait for the GPU to
1275 * resume and update the breadcrumb.
1277 * If we don't hold the mutex, we can just wait for the worker
1278 * to come along and update the breadcrumb (either directly
1279 * itself, or indirectly by recovering the GPU).
1281 if (flags & I915_WAIT_LOCKED &&
1282 __i915_wait_request_check_and_reset(req))
1285 /* Only spin if we know the GPU is processing this request */
1286 if (__i915_spin_request(req, wait.seqno, state, 2))
1289 if (!intel_wait_check_request(&wait, req)) {
1290 intel_engine_remove_wait(req->engine, &wait);
1295 intel_engine_remove_wait(req->engine, &wait);
1297 __set_current_state(TASK_RUNNING);
1298 if (flags & I915_WAIT_LOCKED)
1299 remove_wait_queue(errq, &reset);
1300 remove_wait_queue(&req->execute, &exec);
1301 trace_i915_gem_request_wait_end(req);
1306 static void engine_retire_requests(struct intel_engine_cs *engine)
1308 struct drm_i915_gem_request *request, *next;
1309 u32 seqno = intel_engine_get_seqno(engine);
1312 spin_lock_irq(&engine->timeline->lock);
1313 list_for_each_entry_safe(request, next,
1314 &engine->timeline->requests, link) {
1315 if (!i915_seqno_passed(seqno, request->global_seqno))
1318 list_move_tail(&request->link, &retire);
1320 spin_unlock_irq(&engine->timeline->lock);
1322 list_for_each_entry_safe(request, next, &retire, link)
1323 i915_gem_request_retire(request);
1326 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1328 struct intel_engine_cs *engine;
1329 enum intel_engine_id id;
1331 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1333 if (!dev_priv->gt.active_requests)
1336 for_each_engine(engine, dev_priv, id)
1337 engine_retire_requests(engine);
1340 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1341 #include "selftests/mock_request.c"
1342 #include "selftests/i915_gem_request.c"