2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
55 if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
58 return obj->pin_display;
62 insert_mappable_node(struct i915_ggtt *ggtt,
63 struct drm_mm_node *node, u32 size)
65 memset(node, 0, sizeof(*node));
66 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
67 size, 0, I915_COLOR_UNEVICTABLE,
68 0, ggtt->mappable_end,
73 remove_mappable_node(struct drm_mm_node *node)
75 drm_mm_remove_node(node);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
82 spin_lock(&dev_priv->mm.object_stat_lock);
83 dev_priv->mm.object_count++;
84 dev_priv->mm.object_memory += size;
85 spin_unlock(&dev_priv->mm.object_stat_lock);
88 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
91 spin_lock(&dev_priv->mm.object_stat_lock);
92 dev_priv->mm.object_count--;
93 dev_priv->mm.object_memory -= size;
94 spin_unlock(&dev_priv->mm.object_stat_lock);
98 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret = wait_event_interruptible_timeout(error->reset_queue,
110 !i915_reset_backoff(error),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret < 0) {
122 int i915_mutex_lock_interruptible(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = to_i915(dev);
127 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
131 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
142 struct drm_i915_private *dev_priv = to_i915(dev);
143 struct i915_ggtt *ggtt = &dev_priv->ggtt;
144 struct drm_i915_gem_get_aperture *args = data;
145 struct i915_vma *vma;
148 pinned = ggtt->base.reserved;
149 mutex_lock(&dev->struct_mutex);
150 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
151 if (i915_vma_is_pinned(vma))
152 pinned += vma->node.size;
153 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
154 if (i915_vma_is_pinned(vma))
155 pinned += vma->node.size;
156 mutex_unlock(&dev->struct_mutex);
158 args->aper_size = ggtt->base.total;
159 args->aper_available_size = args->aper_size - pinned;
164 static struct sg_table *
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
167 struct address_space *mapping = obj->base.filp->f_mapping;
168 drm_dma_handle_t *phys;
170 struct scatterlist *sg;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
175 return ERR_PTR(-EINVAL);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys = drm_pci_alloc(obj->base.dev,
183 roundup_pow_of_two(obj->base.size));
185 return ERR_PTR(-ENOMEM);
188 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
192 page = shmem_read_mapping_page(mapping, i);
198 src = kmap_atomic(page);
199 memcpy(vaddr, src, PAGE_SIZE);
200 drm_clflush_virt_range(vaddr, PAGE_SIZE);
207 i915_gem_chipset_flush(to_i915(obj->base.dev));
209 st = kmalloc(sizeof(*st), GFP_KERNEL);
211 st = ERR_PTR(-ENOMEM);
215 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
217 st = ERR_PTR(-ENOMEM);
223 sg->length = obj->base.size;
225 sg_dma_address(sg) = phys->busaddr;
226 sg_dma_len(sg) = obj->base.size;
228 obj->phys_handle = phys;
232 drm_pci_free(obj->base.dev, phys);
236 static void __start_cpu_write(struct drm_i915_gem_object *obj)
238 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
239 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
240 if (cpu_write_needs_clflush(obj))
241 obj->cache_dirty = true;
245 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
246 struct sg_table *pages,
249 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251 if (obj->mm.madv == I915_MADV_DONTNEED)
252 obj->mm.dirty = false;
255 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
256 !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
257 drm_clflush_sg(pages);
259 __start_cpu_write(obj);
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
264 struct sg_table *pages)
266 __i915_gem_object_release_shmem(obj, pages, false);
269 struct address_space *mapping = obj->base.filp->f_mapping;
270 char *vaddr = obj->phys_handle->vaddr;
273 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
277 page = shmem_read_mapping_page(mapping, i);
281 dst = kmap_atomic(page);
282 drm_clflush_virt_range(vaddr, PAGE_SIZE);
283 memcpy(dst, vaddr, PAGE_SIZE);
286 set_page_dirty(page);
287 if (obj->mm.madv == I915_MADV_WILLNEED)
288 mark_page_accessed(page);
292 obj->mm.dirty = false;
295 sg_free_table(pages);
298 drm_pci_free(obj->base.dev, obj->phys_handle);
302 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
304 i915_gem_object_unpin_pages(obj);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
308 .get_pages = i915_gem_object_get_pages_phys,
309 .put_pages = i915_gem_object_put_pages_phys,
310 .release = i915_gem_object_release_phys,
313 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
315 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
317 struct i915_vma *vma;
318 LIST_HEAD(still_in_list);
321 lockdep_assert_held(&obj->base.dev->struct_mutex);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret = i915_gem_object_wait(obj,
329 I915_WAIT_INTERRUPTIBLE |
332 MAX_SCHEDULE_TIMEOUT,
337 i915_gem_retire_requests(to_i915(obj->base.dev));
339 while ((vma = list_first_entry_or_null(&obj->vma_list,
342 list_move_tail(&vma->obj_link, &still_in_list);
343 ret = i915_vma_unbind(vma);
347 list_splice(&still_in_list, &obj->vma_list);
353 i915_gem_object_wait_fence(struct dma_fence *fence,
356 struct intel_rps_client *rps)
358 struct drm_i915_gem_request *rq;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
365 if (!dma_fence_is_i915(fence))
366 return dma_fence_wait_timeout(fence,
367 flags & I915_WAIT_INTERRUPTIBLE,
370 rq = to_request(fence);
371 if (i915_gem_request_completed(rq))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq->i915) >= 6)
391 gen6_rps_boost(rq, rps);
396 timeout = i915_wait_request(rq, flags, timeout);
399 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
400 i915_gem_request_retire_upto(rq);
406 i915_gem_object_wait_reservation(struct reservation_object *resv,
409 struct intel_rps_client *rps)
411 unsigned int seq = __read_seqcount_begin(&resv->seq);
412 struct dma_fence *excl;
413 bool prune_fences = false;
415 if (flags & I915_WAIT_ALL) {
416 struct dma_fence **shared;
417 unsigned int count, i;
420 ret = reservation_object_get_fences_rcu(resv,
421 &excl, &count, &shared);
425 for (i = 0; i < count; i++) {
426 timeout = i915_gem_object_wait_fence(shared[i],
432 dma_fence_put(shared[i]);
435 for (; i < count; i++)
436 dma_fence_put(shared[i]);
439 prune_fences = count && timeout >= 0;
441 excl = reservation_object_get_excl_rcu(resv);
444 if (excl && timeout >= 0) {
445 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
446 prune_fences = timeout >= 0;
451 /* Oportunistically prune the fences iff we know they have *all* been
452 * signaled and that the reservation object has not been changed (i.e.
453 * no new fences have been added).
455 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
456 if (reservation_object_trylock(resv)) {
457 if (!__read_seqcount_retry(&resv->seq, seq))
458 reservation_object_add_excl_fence(resv, NULL);
459 reservation_object_unlock(resv);
466 static void __fence_set_priority(struct dma_fence *fence, int prio)
468 struct drm_i915_gem_request *rq;
469 struct intel_engine_cs *engine;
471 if (!dma_fence_is_i915(fence))
474 rq = to_request(fence);
476 if (!engine->schedule)
479 engine->schedule(rq, prio);
482 static void fence_set_priority(struct dma_fence *fence, int prio)
484 /* Recurse once into a fence-array */
485 if (dma_fence_is_array(fence)) {
486 struct dma_fence_array *array = to_dma_fence_array(fence);
489 for (i = 0; i < array->num_fences; i++)
490 __fence_set_priority(array->fences[i], prio);
492 __fence_set_priority(fence, prio);
497 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
501 struct dma_fence *excl;
503 if (flags & I915_WAIT_ALL) {
504 struct dma_fence **shared;
505 unsigned int count, i;
508 ret = reservation_object_get_fences_rcu(obj->resv,
509 &excl, &count, &shared);
513 for (i = 0; i < count; i++) {
514 fence_set_priority(shared[i], prio);
515 dma_fence_put(shared[i]);
520 excl = reservation_object_get_excl_rcu(obj->resv);
524 fence_set_priority(excl, prio);
531 * Waits for rendering to the object to be completed
532 * @obj: i915 gem object
533 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
534 * @timeout: how long to wait
535 * @rps: client (user process) to charge for any waitboosting
538 i915_gem_object_wait(struct drm_i915_gem_object *obj,
541 struct intel_rps_client *rps)
544 #if IS_ENABLED(CONFIG_LOCKDEP)
545 GEM_BUG_ON(debug_locks &&
546 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
547 !!(flags & I915_WAIT_LOCKED));
549 GEM_BUG_ON(timeout < 0);
551 timeout = i915_gem_object_wait_reservation(obj->resv,
554 return timeout < 0 ? timeout : 0;
557 static struct intel_rps_client *to_rps_client(struct drm_file *file)
559 struct drm_i915_file_private *fpriv = file->driver_priv;
565 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
566 struct drm_i915_gem_pwrite *args,
567 struct drm_file *file)
569 void *vaddr = obj->phys_handle->vaddr + args->offset;
570 char __user *user_data = u64_to_user_ptr(args->data_ptr);
572 /* We manually control the domain here and pretend that it
573 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
575 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
576 if (copy_from_user(vaddr, user_data, args->size))
579 drm_clflush_virt_range(vaddr, args->size);
580 i915_gem_chipset_flush(to_i915(obj->base.dev));
582 intel_fb_obj_flush(obj, ORIGIN_CPU);
586 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
588 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
591 void i915_gem_object_free(struct drm_i915_gem_object *obj)
593 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
594 kmem_cache_free(dev_priv->objects, obj);
598 i915_gem_create(struct drm_file *file,
599 struct drm_i915_private *dev_priv,
603 struct drm_i915_gem_object *obj;
607 size = roundup(size, PAGE_SIZE);
611 /* Allocate the new object */
612 obj = i915_gem_object_create(dev_priv, size);
616 ret = drm_gem_handle_create(file, &obj->base, &handle);
617 /* drop reference from allocate - handle holds it now */
618 i915_gem_object_put(obj);
627 i915_gem_dumb_create(struct drm_file *file,
628 struct drm_device *dev,
629 struct drm_mode_create_dumb *args)
631 /* have to work out size/pitch and return them */
632 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
633 args->size = args->pitch * args->height;
634 return i915_gem_create(file, to_i915(dev),
635 args->size, &args->handle);
638 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
640 return !(obj->cache_level == I915_CACHE_NONE ||
641 obj->cache_level == I915_CACHE_WT);
645 * Creates a new mm object and returns a handle to it.
646 * @dev: drm device pointer
647 * @data: ioctl data blob
648 * @file: drm file pointer
651 i915_gem_create_ioctl(struct drm_device *dev, void *data,
652 struct drm_file *file)
654 struct drm_i915_private *dev_priv = to_i915(dev);
655 struct drm_i915_gem_create *args = data;
657 i915_gem_flush_free_objects(dev_priv);
659 return i915_gem_create(file, dev_priv,
660 args->size, &args->handle);
663 static inline enum fb_op_origin
664 fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
666 return (domain == I915_GEM_DOMAIN_GTT ?
667 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
671 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
673 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
675 if (!(obj->base.write_domain & flush_domains))
678 /* No actual flushing is required for the GTT write domain. Writes
679 * to it "immediately" go to main memory as far as we know, so there's
680 * no chipset flush. It also doesn't land in render cache.
682 * However, we do have to enforce the order so that all writes through
683 * the GTT land before any writes to the device, such as updates to
686 * We also have to wait a bit for the writes to land from the GTT.
687 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
688 * timing. This issue has only been observed when switching quickly
689 * between GTT writes and CPU reads from inside the kernel on recent hw,
690 * and it appears to only affect discrete GTT blocks (i.e. on LLC
691 * system agents we cannot reproduce this behaviour).
695 switch (obj->base.write_domain) {
696 case I915_GEM_DOMAIN_GTT:
697 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
698 if (intel_runtime_pm_get_if_in_use(dev_priv)) {
699 spin_lock_irq(&dev_priv->uncore.lock);
700 POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
701 spin_unlock_irq(&dev_priv->uncore.lock);
702 intel_runtime_pm_put(dev_priv);
706 intel_fb_obj_flush(obj,
707 fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
710 case I915_GEM_DOMAIN_CPU:
711 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
714 case I915_GEM_DOMAIN_RENDER:
715 if (gpu_write_needs_clflush(obj))
716 obj->cache_dirty = true;
720 obj->base.write_domain = 0;
724 __copy_to_user_swizzled(char __user *cpu_vaddr,
725 const char *gpu_vaddr, int gpu_offset,
728 int ret, cpu_offset = 0;
731 int cacheline_end = ALIGN(gpu_offset + 1, 64);
732 int this_length = min(cacheline_end - gpu_offset, length);
733 int swizzled_gpu_offset = gpu_offset ^ 64;
735 ret = __copy_to_user(cpu_vaddr + cpu_offset,
736 gpu_vaddr + swizzled_gpu_offset,
741 cpu_offset += this_length;
742 gpu_offset += this_length;
743 length -= this_length;
750 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
751 const char __user *cpu_vaddr,
754 int ret, cpu_offset = 0;
757 int cacheline_end = ALIGN(gpu_offset + 1, 64);
758 int this_length = min(cacheline_end - gpu_offset, length);
759 int swizzled_gpu_offset = gpu_offset ^ 64;
761 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
762 cpu_vaddr + cpu_offset,
767 cpu_offset += this_length;
768 gpu_offset += this_length;
769 length -= this_length;
776 * Pins the specified object's pages and synchronizes the object with
777 * GPU accesses. Sets needs_clflush to non-zero if the caller should
778 * flush the object from the CPU cache.
780 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
781 unsigned int *needs_clflush)
785 lockdep_assert_held(&obj->base.dev->struct_mutex);
788 if (!i915_gem_object_has_struct_page(obj))
791 ret = i915_gem_object_wait(obj,
792 I915_WAIT_INTERRUPTIBLE |
794 MAX_SCHEDULE_TIMEOUT,
799 ret = i915_gem_object_pin_pages(obj);
803 if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
804 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
805 ret = i915_gem_object_set_to_cpu_domain(obj, false);
812 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
814 /* If we're not in the cpu read domain, set ourself into the gtt
815 * read domain and manually flush cachelines (if required). This
816 * optimizes for the case when the gpu will dirty the data
817 * anyway again before the next pread happens.
819 if (!obj->cache_dirty &&
820 !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
821 *needs_clflush = CLFLUSH_BEFORE;
824 /* return with the pages pinned */
828 i915_gem_object_unpin_pages(obj);
832 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
833 unsigned int *needs_clflush)
837 lockdep_assert_held(&obj->base.dev->struct_mutex);
840 if (!i915_gem_object_has_struct_page(obj))
843 ret = i915_gem_object_wait(obj,
844 I915_WAIT_INTERRUPTIBLE |
847 MAX_SCHEDULE_TIMEOUT,
852 ret = i915_gem_object_pin_pages(obj);
856 if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
857 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
858 ret = i915_gem_object_set_to_cpu_domain(obj, true);
865 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
867 /* If we're not in the cpu write domain, set ourself into the
868 * gtt write domain and manually flush cachelines (as required).
869 * This optimizes for the case when the gpu will use the data
870 * right away and we therefore have to clflush anyway.
872 if (!obj->cache_dirty) {
873 *needs_clflush |= CLFLUSH_AFTER;
876 * Same trick applies to invalidate partially written
877 * cachelines read before writing.
879 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
880 *needs_clflush |= CLFLUSH_BEFORE;
884 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
885 obj->mm.dirty = true;
886 /* return with the pages pinned */
890 i915_gem_object_unpin_pages(obj);
895 shmem_clflush_swizzled_range(char *addr, unsigned long length,
898 if (unlikely(swizzled)) {
899 unsigned long start = (unsigned long) addr;
900 unsigned long end = (unsigned long) addr + length;
902 /* For swizzling simply ensure that we always flush both
903 * channels. Lame, but simple and it works. Swizzled
904 * pwrite/pread is far from a hotpath - current userspace
905 * doesn't use it at all. */
906 start = round_down(start, 128);
907 end = round_up(end, 128);
909 drm_clflush_virt_range((void *)start, end - start);
911 drm_clflush_virt_range(addr, length);
916 /* Only difference to the fast-path function is that this can handle bit17
917 * and uses non-atomic copy and kmap functions. */
919 shmem_pread_slow(struct page *page, int offset, int length,
920 char __user *user_data,
921 bool page_do_bit17_swizzling, bool needs_clflush)
928 shmem_clflush_swizzled_range(vaddr + offset, length,
929 page_do_bit17_swizzling);
931 if (page_do_bit17_swizzling)
932 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
934 ret = __copy_to_user(user_data, vaddr + offset, length);
937 return ret ? - EFAULT : 0;
941 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
942 bool page_do_bit17_swizzling, bool needs_clflush)
947 if (!page_do_bit17_swizzling) {
948 char *vaddr = kmap_atomic(page);
951 drm_clflush_virt_range(vaddr + offset, length);
952 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
953 kunmap_atomic(vaddr);
958 return shmem_pread_slow(page, offset, length, user_data,
959 page_do_bit17_swizzling, needs_clflush);
963 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
964 struct drm_i915_gem_pread *args)
966 char __user *user_data;
968 unsigned int obj_do_bit17_swizzling;
969 unsigned int needs_clflush;
970 unsigned int idx, offset;
973 obj_do_bit17_swizzling = 0;
974 if (i915_gem_object_needs_bit17_swizzle(obj))
975 obj_do_bit17_swizzling = BIT(17);
977 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
981 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
982 mutex_unlock(&obj->base.dev->struct_mutex);
987 user_data = u64_to_user_ptr(args->data_ptr);
988 offset = offset_in_page(args->offset);
989 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
990 struct page *page = i915_gem_object_get_page(obj, idx);
994 if (offset + length > PAGE_SIZE)
995 length = PAGE_SIZE - offset;
997 ret = shmem_pread(page, offset, length, user_data,
998 page_to_phys(page) & obj_do_bit17_swizzling,
1004 user_data += length;
1008 i915_gem_obj_finish_shmem_access(obj);
1013 gtt_user_read(struct io_mapping *mapping,
1014 loff_t base, int offset,
1015 char __user *user_data, int length)
1018 unsigned long unwritten;
1020 /* We can use the cpu mem copy function because this is X86. */
1021 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1022 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1023 io_mapping_unmap_atomic(vaddr);
1025 vaddr = (void __force *)
1026 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1027 unwritten = copy_to_user(user_data, vaddr + offset, length);
1028 io_mapping_unmap(vaddr);
1034 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1035 const struct drm_i915_gem_pread *args)
1037 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1038 struct i915_ggtt *ggtt = &i915->ggtt;
1039 struct drm_mm_node node;
1040 struct i915_vma *vma;
1041 void __user *user_data;
1045 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1049 intel_runtime_pm_get(i915);
1050 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1051 PIN_MAPPABLE | PIN_NONBLOCK);
1053 node.start = i915_ggtt_offset(vma);
1054 node.allocated = false;
1055 ret = i915_vma_put_fence(vma);
1057 i915_vma_unpin(vma);
1062 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1065 GEM_BUG_ON(!node.allocated);
1068 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1072 mutex_unlock(&i915->drm.struct_mutex);
1074 user_data = u64_to_user_ptr(args->data_ptr);
1075 remain = args->size;
1076 offset = args->offset;
1078 while (remain > 0) {
1079 /* Operation in this page
1081 * page_base = page offset within aperture
1082 * page_offset = offset within page
1083 * page_length = bytes to copy for this page
1085 u32 page_base = node.start;
1086 unsigned page_offset = offset_in_page(offset);
1087 unsigned page_length = PAGE_SIZE - page_offset;
1088 page_length = remain < page_length ? remain : page_length;
1089 if (node.allocated) {
1091 ggtt->base.insert_page(&ggtt->base,
1092 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1093 node.start, I915_CACHE_NONE, 0);
1096 page_base += offset & PAGE_MASK;
1099 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1100 user_data, page_length)) {
1105 remain -= page_length;
1106 user_data += page_length;
1107 offset += page_length;
1110 mutex_lock(&i915->drm.struct_mutex);
1112 if (node.allocated) {
1114 ggtt->base.clear_range(&ggtt->base,
1115 node.start, node.size);
1116 remove_mappable_node(&node);
1118 i915_vma_unpin(vma);
1121 intel_runtime_pm_put(i915);
1122 mutex_unlock(&i915->drm.struct_mutex);
1128 * Reads data from the object referenced by handle.
1129 * @dev: drm device pointer
1130 * @data: ioctl data blob
1131 * @file: drm file pointer
1133 * On error, the contents of *data are undefined.
1136 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *file)
1139 struct drm_i915_gem_pread *args = data;
1140 struct drm_i915_gem_object *obj;
1143 if (args->size == 0)
1146 if (!access_ok(VERIFY_WRITE,
1147 u64_to_user_ptr(args->data_ptr),
1151 obj = i915_gem_object_lookup(file, args->handle);
1155 /* Bounds check source. */
1156 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1161 trace_i915_gem_object_pread(obj, args->offset, args->size);
1163 ret = i915_gem_object_wait(obj,
1164 I915_WAIT_INTERRUPTIBLE,
1165 MAX_SCHEDULE_TIMEOUT,
1166 to_rps_client(file));
1170 ret = i915_gem_object_pin_pages(obj);
1174 ret = i915_gem_shmem_pread(obj, args);
1175 if (ret == -EFAULT || ret == -ENODEV)
1176 ret = i915_gem_gtt_pread(obj, args);
1178 i915_gem_object_unpin_pages(obj);
1180 i915_gem_object_put(obj);
1184 /* This is the fast write path which cannot handle
1185 * page faults in the source data
1189 ggtt_write(struct io_mapping *mapping,
1190 loff_t base, int offset,
1191 char __user *user_data, int length)
1194 unsigned long unwritten;
1196 /* We can use the cpu mem copy function because this is X86. */
1197 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1198 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1200 io_mapping_unmap_atomic(vaddr);
1202 vaddr = (void __force *)
1203 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1204 unwritten = copy_from_user(vaddr + offset, user_data, length);
1205 io_mapping_unmap(vaddr);
1212 * This is the fast pwrite path, where we copy the data directly from the
1213 * user into the GTT, uncached.
1214 * @obj: i915 GEM object
1215 * @args: pwrite arguments structure
1218 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1219 const struct drm_i915_gem_pwrite *args)
1221 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1222 struct i915_ggtt *ggtt = &i915->ggtt;
1223 struct drm_mm_node node;
1224 struct i915_vma *vma;
1226 void __user *user_data;
1229 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1233 intel_runtime_pm_get(i915);
1234 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1235 PIN_MAPPABLE | PIN_NONBLOCK);
1237 node.start = i915_ggtt_offset(vma);
1238 node.allocated = false;
1239 ret = i915_vma_put_fence(vma);
1241 i915_vma_unpin(vma);
1246 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1249 GEM_BUG_ON(!node.allocated);
1252 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1256 mutex_unlock(&i915->drm.struct_mutex);
1258 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1260 user_data = u64_to_user_ptr(args->data_ptr);
1261 offset = args->offset;
1262 remain = args->size;
1264 /* Operation in this page
1266 * page_base = page offset within aperture
1267 * page_offset = offset within page
1268 * page_length = bytes to copy for this page
1270 u32 page_base = node.start;
1271 unsigned int page_offset = offset_in_page(offset);
1272 unsigned int page_length = PAGE_SIZE - page_offset;
1273 page_length = remain < page_length ? remain : page_length;
1274 if (node.allocated) {
1275 wmb(); /* flush the write before we modify the GGTT */
1276 ggtt->base.insert_page(&ggtt->base,
1277 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1278 node.start, I915_CACHE_NONE, 0);
1279 wmb(); /* flush modifications to the GGTT (insert_page) */
1281 page_base += offset & PAGE_MASK;
1283 /* If we get a fault while copying data, then (presumably) our
1284 * source page isn't available. Return the error and we'll
1285 * retry in the slow path.
1286 * If the object is non-shmem backed, we retry again with the
1287 * path that handles page fault.
1289 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1290 user_data, page_length)) {
1295 remain -= page_length;
1296 user_data += page_length;
1297 offset += page_length;
1299 intel_fb_obj_flush(obj, ORIGIN_CPU);
1301 mutex_lock(&i915->drm.struct_mutex);
1303 if (node.allocated) {
1305 ggtt->base.clear_range(&ggtt->base,
1306 node.start, node.size);
1307 remove_mappable_node(&node);
1309 i915_vma_unpin(vma);
1312 intel_runtime_pm_put(i915);
1313 mutex_unlock(&i915->drm.struct_mutex);
1318 shmem_pwrite_slow(struct page *page, int offset, int length,
1319 char __user *user_data,
1320 bool page_do_bit17_swizzling,
1321 bool needs_clflush_before,
1322 bool needs_clflush_after)
1328 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1329 shmem_clflush_swizzled_range(vaddr + offset, length,
1330 page_do_bit17_swizzling);
1331 if (page_do_bit17_swizzling)
1332 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1335 ret = __copy_from_user(vaddr + offset, user_data, length);
1336 if (needs_clflush_after)
1337 shmem_clflush_swizzled_range(vaddr + offset, length,
1338 page_do_bit17_swizzling);
1341 return ret ? -EFAULT : 0;
1344 /* Per-page copy function for the shmem pwrite fastpath.
1345 * Flushes invalid cachelines before writing to the target if
1346 * needs_clflush_before is set and flushes out any written cachelines after
1347 * writing if needs_clflush is set.
1350 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1351 bool page_do_bit17_swizzling,
1352 bool needs_clflush_before,
1353 bool needs_clflush_after)
1358 if (!page_do_bit17_swizzling) {
1359 char *vaddr = kmap_atomic(page);
1361 if (needs_clflush_before)
1362 drm_clflush_virt_range(vaddr + offset, len);
1363 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1364 if (needs_clflush_after)
1365 drm_clflush_virt_range(vaddr + offset, len);
1367 kunmap_atomic(vaddr);
1372 return shmem_pwrite_slow(page, offset, len, user_data,
1373 page_do_bit17_swizzling,
1374 needs_clflush_before,
1375 needs_clflush_after);
1379 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1380 const struct drm_i915_gem_pwrite *args)
1382 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1383 void __user *user_data;
1385 unsigned int obj_do_bit17_swizzling;
1386 unsigned int partial_cacheline_write;
1387 unsigned int needs_clflush;
1388 unsigned int offset, idx;
1391 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1395 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1396 mutex_unlock(&i915->drm.struct_mutex);
1400 obj_do_bit17_swizzling = 0;
1401 if (i915_gem_object_needs_bit17_swizzle(obj))
1402 obj_do_bit17_swizzling = BIT(17);
1404 /* If we don't overwrite a cacheline completely we need to be
1405 * careful to have up-to-date data by first clflushing. Don't
1406 * overcomplicate things and flush the entire patch.
1408 partial_cacheline_write = 0;
1409 if (needs_clflush & CLFLUSH_BEFORE)
1410 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1412 user_data = u64_to_user_ptr(args->data_ptr);
1413 remain = args->size;
1414 offset = offset_in_page(args->offset);
1415 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1416 struct page *page = i915_gem_object_get_page(obj, idx);
1420 if (offset + length > PAGE_SIZE)
1421 length = PAGE_SIZE - offset;
1423 ret = shmem_pwrite(page, offset, length, user_data,
1424 page_to_phys(page) & obj_do_bit17_swizzling,
1425 (offset | length) & partial_cacheline_write,
1426 needs_clflush & CLFLUSH_AFTER);
1431 user_data += length;
1435 intel_fb_obj_flush(obj, ORIGIN_CPU);
1436 i915_gem_obj_finish_shmem_access(obj);
1441 * Writes data to the object referenced by handle.
1443 * @data: ioctl data blob
1446 * On error, the contents of the buffer that were to be modified are undefined.
1449 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *file)
1452 struct drm_i915_gem_pwrite *args = data;
1453 struct drm_i915_gem_object *obj;
1456 if (args->size == 0)
1459 if (!access_ok(VERIFY_READ,
1460 u64_to_user_ptr(args->data_ptr),
1464 obj = i915_gem_object_lookup(file, args->handle);
1468 /* Bounds check destination. */
1469 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1474 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1477 if (obj->ops->pwrite)
1478 ret = obj->ops->pwrite(obj, args);
1482 ret = i915_gem_object_wait(obj,
1483 I915_WAIT_INTERRUPTIBLE |
1485 MAX_SCHEDULE_TIMEOUT,
1486 to_rps_client(file));
1490 ret = i915_gem_object_pin_pages(obj);
1495 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1496 * it would end up going through the fenced access, and we'll get
1497 * different detiling behavior between reading and writing.
1498 * pread/pwrite currently are reading and writing from the CPU
1499 * perspective, requiring manual detiling by the client.
1501 if (!i915_gem_object_has_struct_page(obj) ||
1502 cpu_write_needs_clflush(obj))
1503 /* Note that the gtt paths might fail with non-page-backed user
1504 * pointers (e.g. gtt mappings when moving data between
1505 * textures). Fallback to the shmem path in that case.
1507 ret = i915_gem_gtt_pwrite_fast(obj, args);
1509 if (ret == -EFAULT || ret == -ENOSPC) {
1510 if (obj->phys_handle)
1511 ret = i915_gem_phys_pwrite(obj, args, file);
1513 ret = i915_gem_shmem_pwrite(obj, args);
1516 i915_gem_object_unpin_pages(obj);
1518 i915_gem_object_put(obj);
1522 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1524 struct drm_i915_private *i915;
1525 struct list_head *list;
1526 struct i915_vma *vma;
1528 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1529 if (!i915_vma_is_ggtt(vma))
1532 if (i915_vma_is_active(vma))
1535 if (!drm_mm_node_allocated(&vma->node))
1538 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1541 i915 = to_i915(obj->base.dev);
1542 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1543 list_move_tail(&obj->global_link, list);
1547 * Called when user space prepares to use an object with the CPU, either
1548 * through the mmap ioctl's mapping or a GTT mapping.
1550 * @data: ioctl data blob
1554 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1555 struct drm_file *file)
1557 struct drm_i915_gem_set_domain *args = data;
1558 struct drm_i915_gem_object *obj;
1559 uint32_t read_domains = args->read_domains;
1560 uint32_t write_domain = args->write_domain;
1563 /* Only handle setting domains to types used by the CPU. */
1564 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1567 /* Having something in the write domain implies it's in the read
1568 * domain, and only that read domain. Enforce that in the request.
1570 if (write_domain != 0 && read_domains != write_domain)
1573 obj = i915_gem_object_lookup(file, args->handle);
1577 /* Try to flush the object off the GPU without holding the lock.
1578 * We will repeat the flush holding the lock in the normal manner
1579 * to catch cases where we are gazumped.
1581 err = i915_gem_object_wait(obj,
1582 I915_WAIT_INTERRUPTIBLE |
1583 (write_domain ? I915_WAIT_ALL : 0),
1584 MAX_SCHEDULE_TIMEOUT,
1585 to_rps_client(file));
1589 /* Flush and acquire obj->pages so that we are coherent through
1590 * direct access in memory with previous cached writes through
1591 * shmemfs and that our cache domain tracking remains valid.
1592 * For example, if the obj->filp was moved to swap without us
1593 * being notified and releasing the pages, we would mistakenly
1594 * continue to assume that the obj remained out of the CPU cached
1597 err = i915_gem_object_pin_pages(obj);
1601 err = i915_mutex_lock_interruptible(dev);
1605 if (read_domains & I915_GEM_DOMAIN_WC)
1606 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
1607 else if (read_domains & I915_GEM_DOMAIN_GTT)
1608 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
1610 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
1612 /* And bump the LRU for this access */
1613 i915_gem_object_bump_inactive_ggtt(obj);
1615 mutex_unlock(&dev->struct_mutex);
1617 if (write_domain != 0)
1618 intel_fb_obj_invalidate(obj,
1619 fb_write_origin(obj, write_domain));
1622 i915_gem_object_unpin_pages(obj);
1624 i915_gem_object_put(obj);
1629 * Called when user space has done writes to this buffer
1631 * @data: ioctl data blob
1635 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1636 struct drm_file *file)
1638 struct drm_i915_gem_sw_finish *args = data;
1639 struct drm_i915_gem_object *obj;
1641 obj = i915_gem_object_lookup(file, args->handle);
1645 /* Pinned buffers may be scanout, so flush the cache */
1646 i915_gem_object_flush_if_display(obj);
1647 i915_gem_object_put(obj);
1653 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1656 * @data: ioctl data blob
1659 * While the mapping holds a reference on the contents of the object, it doesn't
1660 * imply a ref on the object itself.
1664 * DRM driver writers who look a this function as an example for how to do GEM
1665 * mmap support, please don't implement mmap support like here. The modern way
1666 * to implement DRM mmap support is with an mmap offset ioctl (like
1667 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1668 * That way debug tooling like valgrind will understand what's going on, hiding
1669 * the mmap call in a driver private ioctl will break that. The i915 driver only
1670 * does cpu mmaps this way because we didn't know better.
1673 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file)
1676 struct drm_i915_gem_mmap *args = data;
1677 struct drm_i915_gem_object *obj;
1680 if (args->flags & ~(I915_MMAP_WC))
1683 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1686 obj = i915_gem_object_lookup(file, args->handle);
1690 /* prime objects have no backing filp to GEM mmap
1693 if (!obj->base.filp) {
1694 i915_gem_object_put(obj);
1698 addr = vm_mmap(obj->base.filp, 0, args->size,
1699 PROT_READ | PROT_WRITE, MAP_SHARED,
1701 if (args->flags & I915_MMAP_WC) {
1702 struct mm_struct *mm = current->mm;
1703 struct vm_area_struct *vma;
1705 if (down_write_killable(&mm->mmap_sem)) {
1706 i915_gem_object_put(obj);
1709 vma = find_vma(mm, addr);
1712 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1715 up_write(&mm->mmap_sem);
1717 /* This may race, but that's ok, it only gets set */
1718 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1720 i915_gem_object_put(obj);
1721 if (IS_ERR((void *)addr))
1724 args->addr_ptr = (uint64_t) addr;
1729 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1731 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1735 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1737 * A history of the GTT mmap interface:
1739 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1740 * aligned and suitable for fencing, and still fit into the available
1741 * mappable space left by the pinned display objects. A classic problem
1742 * we called the page-fault-of-doom where we would ping-pong between
1743 * two objects that could not fit inside the GTT and so the memcpy
1744 * would page one object in at the expense of the other between every
1747 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1748 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1749 * object is too large for the available space (or simply too large
1750 * for the mappable aperture!), a view is created instead and faulted
1751 * into userspace. (This view is aligned and sized appropriately for
1754 * 2 - Recognise WC as a separate cache domain so that we can flush the
1755 * delayed writes via GTT before performing direct access via WC.
1759 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1760 * hangs on some architectures, corruption on others. An attempt to service
1761 * a GTT page fault from a snoopable object will generate a SIGBUS.
1763 * * the object must be able to fit into RAM (physical memory, though no
1764 * limited to the mappable aperture).
1769 * * a new GTT page fault will synchronize rendering from the GPU and flush
1770 * all data to system memory. Subsequent access will not be synchronized.
1772 * * all mappings are revoked on runtime device suspend.
1774 * * there are only 8, 16 or 32 fence registers to share between all users
1775 * (older machines require fence register for display and blitter access
1776 * as well). Contention of the fence registers will cause the previous users
1777 * to be unmapped and any new access will generate new page faults.
1779 * * running out of memory while servicing a fault may generate a SIGBUS,
1780 * rather than the expected SIGSEGV.
1782 int i915_gem_mmap_gtt_version(void)
1787 static inline struct i915_ggtt_view
1788 compute_partial_view(struct drm_i915_gem_object *obj,
1789 pgoff_t page_offset,
1792 struct i915_ggtt_view view;
1794 if (i915_gem_object_is_tiled(obj))
1795 chunk = roundup(chunk, tile_row_pages(obj));
1797 view.type = I915_GGTT_VIEW_PARTIAL;
1798 view.partial.offset = rounddown(page_offset, chunk);
1800 min_t(unsigned int, chunk,
1801 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1803 /* If the partial covers the entire object, just create a normal VMA. */
1804 if (chunk >= obj->base.size >> PAGE_SHIFT)
1805 view.type = I915_GGTT_VIEW_NORMAL;
1811 * i915_gem_fault - fault a page into the GTT
1814 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1815 * from userspace. The fault handler takes care of binding the object to
1816 * the GTT (if needed), allocating and programming a fence register (again,
1817 * only if needed based on whether the old reg is still valid or the object
1818 * is tiled) and inserting a new PTE into the faulting process.
1820 * Note that the faulting process may involve evicting existing objects
1821 * from the GTT and/or fence registers to make room. So performance may
1822 * suffer if the GTT working set is large or there are few fence registers
1825 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1826 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1828 int i915_gem_fault(struct vm_fault *vmf)
1830 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1831 struct vm_area_struct *area = vmf->vma;
1832 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1833 struct drm_device *dev = obj->base.dev;
1834 struct drm_i915_private *dev_priv = to_i915(dev);
1835 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1836 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1837 struct i915_vma *vma;
1838 pgoff_t page_offset;
1842 /* We don't use vmf->pgoff since that has the fake offset */
1843 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1845 trace_i915_gem_object_fault(obj, page_offset, true, write);
1847 /* Try to flush the object off the GPU first without holding the lock.
1848 * Upon acquiring the lock, we will perform our sanity checks and then
1849 * repeat the flush holding the lock in the normal manner to catch cases
1850 * where we are gazumped.
1852 ret = i915_gem_object_wait(obj,
1853 I915_WAIT_INTERRUPTIBLE,
1854 MAX_SCHEDULE_TIMEOUT,
1859 ret = i915_gem_object_pin_pages(obj);
1863 intel_runtime_pm_get(dev_priv);
1865 ret = i915_mutex_lock_interruptible(dev);
1869 /* Access to snoopable pages through the GTT is incoherent. */
1870 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1875 /* If the object is smaller than a couple of partial vma, it is
1876 * not worth only creating a single partial vma - we may as well
1877 * clear enough space for the full object.
1879 flags = PIN_MAPPABLE;
1880 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1881 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1883 /* Now pin it into the GTT as needed */
1884 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1886 /* Use a partial view if it is bigger than available space */
1887 struct i915_ggtt_view view =
1888 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1890 /* Userspace is now writing through an untracked VMA, abandon
1891 * all hope that the hardware is able to track future writes.
1893 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1895 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1902 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1906 ret = i915_vma_get_fence(vma);
1910 /* Mark as being mmapped into userspace for later revocation */
1911 assert_rpm_wakelock_held(dev_priv);
1912 if (list_empty(&obj->userfault_link))
1913 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1915 /* Finally, remap it using the new GTT offset */
1916 ret = remap_io_mapping(area,
1917 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1918 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1919 min_t(u64, vma->size, area->vm_end - area->vm_start),
1923 __i915_vma_unpin(vma);
1925 mutex_unlock(&dev->struct_mutex);
1927 intel_runtime_pm_put(dev_priv);
1928 i915_gem_object_unpin_pages(obj);
1933 * We eat errors when the gpu is terminally wedged to avoid
1934 * userspace unduly crashing (gl has no provisions for mmaps to
1935 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1936 * and so needs to be reported.
1938 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1939 ret = VM_FAULT_SIGBUS;
1944 * EAGAIN means the gpu is hung and we'll wait for the error
1945 * handler to reset everything when re-faulting in
1946 * i915_mutex_lock_interruptible.
1953 * EBUSY is ok: this just means that another thread
1954 * already did the job.
1956 ret = VM_FAULT_NOPAGE;
1963 ret = VM_FAULT_SIGBUS;
1966 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1967 ret = VM_FAULT_SIGBUS;
1974 * i915_gem_release_mmap - remove physical page mappings
1975 * @obj: obj in question
1977 * Preserve the reservation of the mmapping with the DRM core code, but
1978 * relinquish ownership of the pages back to the system.
1980 * It is vital that we remove the page mapping if we have mapped a tiled
1981 * object through the GTT and then lose the fence register due to
1982 * resource pressure. Similarly if the object has been moved out of the
1983 * aperture, than pages mapped into userspace must be revoked. Removing the
1984 * mapping will then trigger a page fault on the next user access, allowing
1985 * fixup by i915_gem_fault().
1988 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1990 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1992 /* Serialisation between user GTT access and our code depends upon
1993 * revoking the CPU's PTE whilst the mutex is held. The next user
1994 * pagefault then has to wait until we release the mutex.
1996 * Note that RPM complicates somewhat by adding an additional
1997 * requirement that operations to the GGTT be made holding the RPM
2000 lockdep_assert_held(&i915->drm.struct_mutex);
2001 intel_runtime_pm_get(i915);
2003 if (list_empty(&obj->userfault_link))
2006 list_del_init(&obj->userfault_link);
2007 drm_vma_node_unmap(&obj->base.vma_node,
2008 obj->base.dev->anon_inode->i_mapping);
2010 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2011 * memory transactions from userspace before we return. The TLB
2012 * flushing implied above by changing the PTE above *should* be
2013 * sufficient, an extra barrier here just provides us with a bit
2014 * of paranoid documentation about our requirement to serialise
2015 * memory writes before touching registers / GSM.
2020 intel_runtime_pm_put(i915);
2023 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2025 struct drm_i915_gem_object *obj, *on;
2029 * Only called during RPM suspend. All users of the userfault_list
2030 * must be holding an RPM wakeref to ensure that this can not
2031 * run concurrently with themselves (and use the struct_mutex for
2032 * protection between themselves).
2035 list_for_each_entry_safe(obj, on,
2036 &dev_priv->mm.userfault_list, userfault_link) {
2037 list_del_init(&obj->userfault_link);
2038 drm_vma_node_unmap(&obj->base.vma_node,
2039 obj->base.dev->anon_inode->i_mapping);
2042 /* The fence will be lost when the device powers down. If any were
2043 * in use by hardware (i.e. they are pinned), we should not be powering
2044 * down! All other fences will be reacquired by the user upon waking.
2046 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2047 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2049 /* Ideally we want to assert that the fence register is not
2050 * live at this point (i.e. that no piece of code will be
2051 * trying to write through fence + GTT, as that both violates
2052 * our tracking of activity and associated locking/barriers,
2053 * but also is illegal given that the hw is powered down).
2055 * Previously we used reg->pin_count as a "liveness" indicator.
2056 * That is not sufficient, and we need a more fine-grained
2057 * tool if we want to have a sanity check here.
2063 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2068 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2070 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2073 err = drm_gem_create_mmap_offset(&obj->base);
2077 /* Attempt to reap some mmap space from dead objects */
2079 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2083 i915_gem_drain_freed_objects(dev_priv);
2084 err = drm_gem_create_mmap_offset(&obj->base);
2088 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2093 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2095 drm_gem_free_mmap_offset(&obj->base);
2099 i915_gem_mmap_gtt(struct drm_file *file,
2100 struct drm_device *dev,
2104 struct drm_i915_gem_object *obj;
2107 obj = i915_gem_object_lookup(file, handle);
2111 ret = i915_gem_object_create_mmap_offset(obj);
2113 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2115 i915_gem_object_put(obj);
2120 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2122 * @data: GTT mapping ioctl data
2123 * @file: GEM object info
2125 * Simply returns the fake offset to userspace so it can mmap it.
2126 * The mmap call will end up in drm_gem_mmap(), which will set things
2127 * up so we can get faults in the handler above.
2129 * The fault handler will take care of binding the object into the GTT
2130 * (since it may have been evicted to make room for something), allocating
2131 * a fence register, and mapping the appropriate aperture address into
2135 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *file)
2138 struct drm_i915_gem_mmap_gtt *args = data;
2140 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2143 /* Immediately discard the backing storage */
2145 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2147 i915_gem_object_free_mmap_offset(obj);
2149 if (obj->base.filp == NULL)
2152 /* Our goal here is to return as much of the memory as
2153 * is possible back to the system as we are called from OOM.
2154 * To do this we must instruct the shmfs to drop all of its
2155 * backing pages, *now*.
2157 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2158 obj->mm.madv = __I915_MADV_PURGED;
2159 obj->mm.pages = ERR_PTR(-EFAULT);
2162 /* Try to discard unwanted pages */
2163 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2165 struct address_space *mapping;
2167 lockdep_assert_held(&obj->mm.lock);
2168 GEM_BUG_ON(obj->mm.pages);
2170 switch (obj->mm.madv) {
2171 case I915_MADV_DONTNEED:
2172 i915_gem_object_truncate(obj);
2173 case __I915_MADV_PURGED:
2177 if (obj->base.filp == NULL)
2180 mapping = obj->base.filp->f_mapping,
2181 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2185 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2186 struct sg_table *pages)
2188 struct sgt_iter sgt_iter;
2191 __i915_gem_object_release_shmem(obj, pages, true);
2193 i915_gem_gtt_finish_pages(obj, pages);
2195 if (i915_gem_object_needs_bit17_swizzle(obj))
2196 i915_gem_object_save_bit_17_swizzle(obj, pages);
2198 for_each_sgt_page(page, sgt_iter, pages) {
2200 set_page_dirty(page);
2202 if (obj->mm.madv == I915_MADV_WILLNEED)
2203 mark_page_accessed(page);
2207 obj->mm.dirty = false;
2209 sg_free_table(pages);
2213 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2215 struct radix_tree_iter iter;
2218 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2219 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2222 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2223 enum i915_mm_subclass subclass)
2225 struct sg_table *pages;
2227 if (i915_gem_object_has_pinned_pages(obj))
2230 GEM_BUG_ON(obj->bind_count);
2231 if (!READ_ONCE(obj->mm.pages))
2234 /* May be called by shrinker from within get_pages() (on another bo) */
2235 mutex_lock_nested(&obj->mm.lock, subclass);
2236 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2239 /* ->put_pages might need to allocate memory for the bit17 swizzle
2240 * array, hence protect them from being reaped by removing them from gtt
2242 pages = fetch_and_zero(&obj->mm.pages);
2245 if (obj->mm.mapping) {
2248 ptr = page_mask_bits(obj->mm.mapping);
2249 if (is_vmalloc_addr(ptr))
2252 kunmap(kmap_to_page(ptr));
2254 obj->mm.mapping = NULL;
2257 __i915_gem_object_reset_page_iter(obj);
2260 obj->ops->put_pages(obj, pages);
2263 mutex_unlock(&obj->mm.lock);
2266 static bool i915_sg_trim(struct sg_table *orig_st)
2268 struct sg_table new_st;
2269 struct scatterlist *sg, *new_sg;
2272 if (orig_st->nents == orig_st->orig_nents)
2275 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2278 new_sg = new_st.sgl;
2279 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2280 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2281 /* called before being DMA mapped, no need to copy sg->dma_* */
2282 new_sg = sg_next(new_sg);
2284 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2286 sg_free_table(orig_st);
2292 static struct sg_table *
2293 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2295 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2296 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2298 struct address_space *mapping;
2299 struct sg_table *st;
2300 struct scatterlist *sg;
2301 struct sgt_iter sgt_iter;
2303 unsigned long last_pfn = 0; /* suppress gcc warning */
2304 unsigned int max_segment;
2308 /* Assert that the object is not currently in any GPU domain. As it
2309 * wasn't in the GTT, there shouldn't be any way it could have been in
2312 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2313 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2315 max_segment = swiotlb_max_segment();
2317 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2319 st = kmalloc(sizeof(*st), GFP_KERNEL);
2321 return ERR_PTR(-ENOMEM);
2324 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2326 return ERR_PTR(-ENOMEM);
2329 /* Get the list of pages out of our struct file. They'll be pinned
2330 * at this point until we release them.
2332 * Fail silently without starting the shrinker
2334 mapping = obj->base.filp->f_mapping;
2335 noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
2336 noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
2340 for (i = 0; i < page_count; i++) {
2341 const unsigned int shrink[] = {
2342 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE,
2345 gfp_t gfp = noreclaim;
2348 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2349 if (likely(!IS_ERR(page)))
2353 ret = PTR_ERR(page);
2357 i915_gem_shrink(dev_priv, 2 * page_count, *s++);
2360 /* We've tried hard to allocate the memory by reaping
2361 * our own buffer, now let the real VM do its job and
2362 * go down in flames if truly OOM.
2364 * However, since graphics tend to be disposable,
2365 * defer the oom here by reporting the ENOMEM back
2369 /* reclaim and warn, but no oom */
2370 gfp = mapping_gfp_mask(mapping);
2372 /* Our bo are always dirty and so we require
2373 * kswapd to reclaim our pages (direct reclaim
2374 * does not effectively begin pageout of our
2375 * buffers on its own). However, direct reclaim
2376 * only waits for kswapd when under allocation
2377 * congestion. So as a result __GFP_RECLAIM is
2378 * unreliable and fails to actually reclaim our
2379 * dirty pages -- unless you try over and over
2380 * again with !__GFP_NORETRY. However, we still
2381 * want to fail this allocation rather than
2382 * trigger the out-of-memory killer and for
2383 * this we want __GFP_RETRY_MAYFAIL.
2385 gfp |= __GFP_RETRY_MAYFAIL;
2390 sg->length >= max_segment ||
2391 page_to_pfn(page) != last_pfn + 1) {
2395 sg_set_page(sg, page, PAGE_SIZE, 0);
2397 sg->length += PAGE_SIZE;
2399 last_pfn = page_to_pfn(page);
2401 /* Check that the i965g/gm workaround works. */
2402 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2404 if (sg) /* loop terminated early; short sg table */
2407 /* Trim unused sg entries to avoid wasting memory. */
2410 ret = i915_gem_gtt_prepare_pages(obj, st);
2412 /* DMA remapping failed? One possible cause is that
2413 * it could not reserve enough large entries, asking
2414 * for PAGE_SIZE chunks instead may be helpful.
2416 if (max_segment > PAGE_SIZE) {
2417 for_each_sgt_page(page, sgt_iter, st)
2421 max_segment = PAGE_SIZE;
2424 dev_warn(&dev_priv->drm.pdev->dev,
2425 "Failed to DMA remap %lu pages\n",
2431 if (i915_gem_object_needs_bit17_swizzle(obj))
2432 i915_gem_object_do_bit_17_swizzle(obj, st);
2439 for_each_sgt_page(page, sgt_iter, st)
2444 /* shmemfs first checks if there is enough memory to allocate the page
2445 * and reports ENOSPC should there be insufficient, along with the usual
2446 * ENOMEM for a genuine allocation failure.
2448 * We use ENOSPC in our driver to mean that we have run out of aperture
2449 * space and so want to translate the error from shmemfs back to our
2450 * usual understanding of ENOMEM.
2455 return ERR_PTR(ret);
2458 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2459 struct sg_table *pages)
2461 lockdep_assert_held(&obj->mm.lock);
2463 obj->mm.get_page.sg_pos = pages->sgl;
2464 obj->mm.get_page.sg_idx = 0;
2466 obj->mm.pages = pages;
2468 if (i915_gem_object_is_tiled(obj) &&
2469 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2470 GEM_BUG_ON(obj->mm.quirked);
2471 __i915_gem_object_pin_pages(obj);
2472 obj->mm.quirked = true;
2476 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2478 struct sg_table *pages;
2480 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2482 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2483 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2487 pages = obj->ops->get_pages(obj);
2488 if (unlikely(IS_ERR(pages)))
2489 return PTR_ERR(pages);
2491 __i915_gem_object_set_pages(obj, pages);
2495 /* Ensure that the associated pages are gathered from the backing storage
2496 * and pinned into our object. i915_gem_object_pin_pages() may be called
2497 * multiple times before they are released by a single call to
2498 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2499 * either as a result of memory pressure (reaping pages under the shrinker)
2500 * or as the object is itself released.
2502 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2506 err = mutex_lock_interruptible(&obj->mm.lock);
2510 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2511 err = ____i915_gem_object_get_pages(obj);
2515 smp_mb__before_atomic();
2517 atomic_inc(&obj->mm.pages_pin_count);
2520 mutex_unlock(&obj->mm.lock);
2524 /* The 'mapping' part of i915_gem_object_pin_map() below */
2525 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2526 enum i915_map_type type)
2528 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2529 struct sg_table *sgt = obj->mm.pages;
2530 struct sgt_iter sgt_iter;
2532 struct page *stack_pages[32];
2533 struct page **pages = stack_pages;
2534 unsigned long i = 0;
2538 /* A single page can always be kmapped */
2539 if (n_pages == 1 && type == I915_MAP_WB)
2540 return kmap(sg_page(sgt->sgl));
2542 if (n_pages > ARRAY_SIZE(stack_pages)) {
2543 /* Too big for stack -- allocate temporary array instead */
2544 pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY);
2549 for_each_sgt_page(page, sgt_iter, sgt)
2552 /* Check that we have the expected number of pages */
2553 GEM_BUG_ON(i != n_pages);
2557 pgprot = PAGE_KERNEL;
2560 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2563 addr = vmap(pages, n_pages, 0, pgprot);
2565 if (pages != stack_pages)
2571 /* get, pin, and map the pages of the object into kernel space */
2572 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2573 enum i915_map_type type)
2575 enum i915_map_type has_type;
2580 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2582 ret = mutex_lock_interruptible(&obj->mm.lock);
2584 return ERR_PTR(ret);
2587 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2588 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2589 ret = ____i915_gem_object_get_pages(obj);
2593 smp_mb__before_atomic();
2595 atomic_inc(&obj->mm.pages_pin_count);
2598 GEM_BUG_ON(!obj->mm.pages);
2600 ptr = page_unpack_bits(obj->mm.mapping, &has_type);
2601 if (ptr && has_type != type) {
2607 if (is_vmalloc_addr(ptr))
2610 kunmap(kmap_to_page(ptr));
2612 ptr = obj->mm.mapping = NULL;
2616 ptr = i915_gem_object_map(obj, type);
2622 obj->mm.mapping = page_pack_bits(ptr, type);
2626 mutex_unlock(&obj->mm.lock);
2630 atomic_dec(&obj->mm.pages_pin_count);
2637 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2638 const struct drm_i915_gem_pwrite *arg)
2640 struct address_space *mapping = obj->base.filp->f_mapping;
2641 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2645 /* Before we instantiate/pin the backing store for our use, we
2646 * can prepopulate the shmemfs filp efficiently using a write into
2647 * the pagecache. We avoid the penalty of instantiating all the
2648 * pages, important if the user is just writing to a few and never
2649 * uses the object on the GPU, and using a direct write into shmemfs
2650 * allows it to avoid the cost of retrieving a page (either swapin
2651 * or clearing-before-use) before it is overwritten.
2653 if (READ_ONCE(obj->mm.pages))
2656 /* Before the pages are instantiated the object is treated as being
2657 * in the CPU domain. The pages will be clflushed as required before
2658 * use, and we can freely write into the pages directly. If userspace
2659 * races pwrite with any other operation; corruption will ensue -
2660 * that is userspace's prerogative!
2664 offset = arg->offset;
2665 pg = offset_in_page(offset);
2668 unsigned int len, unwritten;
2673 len = PAGE_SIZE - pg;
2677 err = pagecache_write_begin(obj->base.filp, mapping,
2684 unwritten = copy_from_user(vaddr + pg, user_data, len);
2687 err = pagecache_write_end(obj->base.filp, mapping,
2688 offset, len, len - unwritten,
2705 static bool ban_context(const struct i915_gem_context *ctx,
2708 return (i915_gem_context_is_bannable(ctx) &&
2709 score >= CONTEXT_SCORE_BAN_THRESHOLD);
2712 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2717 atomic_inc(&ctx->guilty_count);
2719 score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
2720 banned = ban_context(ctx, score);
2721 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2722 ctx->name, score, yesno(banned));
2726 i915_gem_context_set_banned(ctx);
2727 if (!IS_ERR_OR_NULL(ctx->file_priv)) {
2728 atomic_inc(&ctx->file_priv->context_bans);
2729 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2730 ctx->name, atomic_read(&ctx->file_priv->context_bans));
2734 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2736 atomic_inc(&ctx->active_count);
2739 struct drm_i915_gem_request *
2740 i915_gem_find_active_request(struct intel_engine_cs *engine)
2742 struct drm_i915_gem_request *request, *active = NULL;
2743 unsigned long flags;
2745 /* We are called by the error capture and reset at a random
2746 * point in time. In particular, note that neither is crucially
2747 * ordered with an interrupt. After a hang, the GPU is dead and we
2748 * assume that no more writes can happen (we waited long enough for
2749 * all writes that were in transaction to be flushed) - adding an
2750 * extra delay for a recent interrupt is pointless. Hence, we do
2751 * not need an engine->irq_seqno_barrier() before the seqno reads.
2753 spin_lock_irqsave(&engine->timeline->lock, flags);
2754 list_for_each_entry(request, &engine->timeline->requests, link) {
2755 if (__i915_gem_request_completed(request,
2756 request->global_seqno))
2759 GEM_BUG_ON(request->engine != engine);
2760 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2761 &request->fence.flags));
2766 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2771 static bool engine_stalled(struct intel_engine_cs *engine)
2773 if (!engine->hangcheck.stalled)
2776 /* Check for possible seqno movement after hang declaration */
2777 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2778 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2786 * Ensure irq handler finishes, and not run again.
2787 * Also return the active request so that we only search for it once.
2789 struct drm_i915_gem_request *
2790 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
2792 struct drm_i915_gem_request *request = NULL;
2794 /* Prevent the signaler thread from updating the request
2795 * state (by calling dma_fence_signal) as we are processing
2796 * the reset. The write from the GPU of the seqno is
2797 * asynchronous and the signaler thread may see a different
2798 * value to us and declare the request complete, even though
2799 * the reset routine have picked that request as the active
2800 * (incomplete) request. This conflict is not handled
2803 kthread_park(engine->breadcrumbs.signaler);
2805 /* Prevent request submission to the hardware until we have
2806 * completed the reset in i915_gem_reset_finish(). If a request
2807 * is completed by one engine, it may then queue a request
2808 * to a second via its engine->irq_tasklet *just* as we are
2809 * calling engine->init_hw() and also writing the ELSP.
2810 * Turning off the engine->irq_tasklet until the reset is over
2811 * prevents the race.
2813 tasklet_kill(&engine->irq_tasklet);
2814 tasklet_disable(&engine->irq_tasklet);
2816 if (engine->irq_seqno_barrier)
2817 engine->irq_seqno_barrier(engine);
2819 request = i915_gem_find_active_request(engine);
2820 if (request && request->fence.error == -EIO)
2821 request = ERR_PTR(-EIO); /* Previous reset failed! */
2826 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2828 struct intel_engine_cs *engine;
2829 struct drm_i915_gem_request *request;
2830 enum intel_engine_id id;
2833 for_each_engine(engine, dev_priv, id) {
2834 request = i915_gem_reset_prepare_engine(engine);
2835 if (IS_ERR(request)) {
2836 err = PTR_ERR(request);
2840 engine->hangcheck.active_request = request;
2843 i915_gem_revoke_fences(dev_priv);
2848 static void skip_request(struct drm_i915_gem_request *request)
2850 void *vaddr = request->ring->vaddr;
2853 /* As this request likely depends on state from the lost
2854 * context, clear out all the user operations leaving the
2855 * breadcrumb at the end (so we get the fence notifications).
2857 head = request->head;
2858 if (request->postfix < head) {
2859 memset(vaddr + head, 0, request->ring->size - head);
2862 memset(vaddr + head, 0, request->postfix - head);
2864 dma_fence_set_error(&request->fence, -EIO);
2867 static void engine_skip_context(struct drm_i915_gem_request *request)
2869 struct intel_engine_cs *engine = request->engine;
2870 struct i915_gem_context *hung_ctx = request->ctx;
2871 struct intel_timeline *timeline;
2872 unsigned long flags;
2874 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2876 spin_lock_irqsave(&engine->timeline->lock, flags);
2877 spin_lock(&timeline->lock);
2879 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2880 if (request->ctx == hung_ctx)
2881 skip_request(request);
2883 list_for_each_entry(request, &timeline->requests, link)
2884 skip_request(request);
2886 spin_unlock(&timeline->lock);
2887 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2890 /* Returns the request if it was guilty of the hang */
2891 static struct drm_i915_gem_request *
2892 i915_gem_reset_request(struct intel_engine_cs *engine,
2893 struct drm_i915_gem_request *request)
2895 /* The guilty request will get skipped on a hung engine.
2897 * Users of client default contexts do not rely on logical
2898 * state preserved between batches so it is safe to execute
2899 * queued requests following the hang. Non default contexts
2900 * rely on preserved state, so skipping a batch loses the
2901 * evolution of the state and it needs to be considered corrupted.
2902 * Executing more queued batches on top of corrupted state is
2903 * risky. But we take the risk by trying to advance through
2904 * the queued requests in order to make the client behaviour
2905 * more predictable around resets, by not throwing away random
2906 * amount of batches it has prepared for execution. Sophisticated
2907 * clients can use gem_reset_stats_ioctl and dma fence status
2908 * (exported via sync_file info ioctl on explicit fences) to observe
2909 * when it loses the context state and should rebuild accordingly.
2911 * The context ban, and ultimately the client ban, mechanism are safety
2912 * valves if client submission ends up resulting in nothing more than
2916 if (engine_stalled(engine)) {
2917 i915_gem_context_mark_guilty(request->ctx);
2918 skip_request(request);
2920 /* If this context is now banned, skip all pending requests. */
2921 if (i915_gem_context_is_banned(request->ctx))
2922 engine_skip_context(request);
2925 * Since this is not the hung engine, it may have advanced
2926 * since the hang declaration. Double check by refinding
2927 * the active request at the time of the reset.
2929 request = i915_gem_find_active_request(engine);
2931 i915_gem_context_mark_innocent(request->ctx);
2932 dma_fence_set_error(&request->fence, -EAGAIN);
2934 /* Rewind the engine to replay the incomplete rq */
2935 spin_lock_irq(&engine->timeline->lock);
2936 request = list_prev_entry(request, link);
2937 if (&request->link == &engine->timeline->requests)
2939 spin_unlock_irq(&engine->timeline->lock);
2946 void i915_gem_reset_engine(struct intel_engine_cs *engine,
2947 struct drm_i915_gem_request *request)
2949 engine->irq_posted = 0;
2952 request = i915_gem_reset_request(engine, request);
2955 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2956 engine->name, request->global_seqno);
2959 /* Setup the CS to resume from the breadcrumb of the hung request */
2960 engine->reset_hw(engine, request);
2963 void i915_gem_reset(struct drm_i915_private *dev_priv)
2965 struct intel_engine_cs *engine;
2966 enum intel_engine_id id;
2968 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2970 i915_gem_retire_requests(dev_priv);
2972 for_each_engine(engine, dev_priv, id) {
2973 struct i915_gem_context *ctx;
2975 i915_gem_reset_engine(engine, engine->hangcheck.active_request);
2976 ctx = fetch_and_zero(&engine->last_retired_context);
2978 engine->context_unpin(engine, ctx);
2981 i915_gem_restore_fences(dev_priv);
2983 if (dev_priv->gt.awake) {
2984 intel_sanitize_gt_powersave(dev_priv);
2985 intel_enable_gt_powersave(dev_priv);
2986 if (INTEL_GEN(dev_priv) >= 6)
2987 gen6_rps_busy(dev_priv);
2991 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
2993 tasklet_enable(&engine->irq_tasklet);
2994 kthread_unpark(engine->breadcrumbs.signaler);
2997 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
2999 struct intel_engine_cs *engine;
3000 enum intel_engine_id id;
3002 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3004 for_each_engine(engine, dev_priv, id) {
3005 engine->hangcheck.active_request = NULL;
3006 i915_gem_reset_finish_engine(engine);
3010 static void nop_submit_request(struct drm_i915_gem_request *request)
3012 GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error));
3013 dma_fence_set_error(&request->fence, -EIO);
3014 i915_gem_request_submit(request);
3015 intel_engine_init_global_seqno(request->engine, request->global_seqno);
3018 static void engine_set_wedged(struct intel_engine_cs *engine)
3020 struct drm_i915_gem_request *request;
3021 unsigned long flags;
3023 /* We need to be sure that no thread is running the old callback as
3024 * we install the nop handler (otherwise we would submit a request
3025 * to hardware that will never complete). In order to prevent this
3026 * race, we wait until the machine is idle before making the swap
3027 * (using stop_machine()).
3029 engine->submit_request = nop_submit_request;
3031 /* Mark all executing requests as skipped */
3032 spin_lock_irqsave(&engine->timeline->lock, flags);
3033 list_for_each_entry(request, &engine->timeline->requests, link)
3034 if (!i915_gem_request_completed(request))
3035 dma_fence_set_error(&request->fence, -EIO);
3036 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3039 * Clear the execlists queue up before freeing the requests, as those
3040 * are the ones that keep the context and ringbuffer backing objects
3044 if (i915.enable_execlists) {
3045 struct execlist_port *port = engine->execlist_port;
3046 unsigned long flags;
3049 spin_lock_irqsave(&engine->timeline->lock, flags);
3051 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
3052 i915_gem_request_put(port_request(&port[n]));
3053 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
3054 engine->execlist_queue = RB_ROOT;
3055 engine->execlist_first = NULL;
3057 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3059 /* The port is checked prior to scheduling a tasklet, but
3060 * just in case we have suspended the tasklet to do the
3061 * wedging make sure that when it wakes, it decides there
3062 * is no work to do by clearing the irq_posted bit.
3064 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
3067 /* Mark all pending requests as complete so that any concurrent
3068 * (lockless) lookup doesn't try and wait upon the request as we
3071 intel_engine_init_global_seqno(engine,
3072 intel_engine_last_submit(engine));
3075 static int __i915_gem_set_wedged_BKL(void *data)
3077 struct drm_i915_private *i915 = data;
3078 struct intel_engine_cs *engine;
3079 enum intel_engine_id id;
3081 for_each_engine(engine, i915, id)
3082 engine_set_wedged(engine);
3084 set_bit(I915_WEDGED, &i915->gpu_error.flags);
3085 wake_up_all(&i915->gpu_error.reset_queue);
3090 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
3092 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
3095 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3097 struct i915_gem_timeline *tl;
3100 lockdep_assert_held(&i915->drm.struct_mutex);
3101 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3104 /* Before unwedging, make sure that all pending operations
3105 * are flushed and errored out - we may have requests waiting upon
3106 * third party fences. We marked all inflight requests as EIO, and
3107 * every execbuf since returned EIO, for consistency we want all
3108 * the currently pending requests to also be marked as EIO, which
3109 * is done inside our nop_submit_request - and so we must wait.
3111 * No more can be submitted until we reset the wedged bit.
3113 list_for_each_entry(tl, &i915->gt.timelines, link) {
3114 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3115 struct drm_i915_gem_request *rq;
3117 rq = i915_gem_active_peek(&tl->engine[i].last_request,
3118 &i915->drm.struct_mutex);
3122 /* We can't use our normal waiter as we want to
3123 * avoid recursively trying to handle the current
3124 * reset. The basic dma_fence_default_wait() installs
3125 * a callback for dma_fence_signal(), which is
3126 * triggered by our nop handler (indirectly, the
3127 * callback enables the signaler thread which is
3128 * woken by the nop_submit_request() advancing the seqno
3129 * and when the seqno passes the fence, the signaler
3130 * then signals the fence waking us up).
3132 if (dma_fence_default_wait(&rq->fence, true,
3133 MAX_SCHEDULE_TIMEOUT) < 0)
3138 /* Undo nop_submit_request. We prevent all new i915 requests from
3139 * being queued (by disallowing execbuf whilst wedged) so having
3140 * waited for all active requests above, we know the system is idle
3141 * and do not have to worry about a thread being inside
3142 * engine->submit_request() as we swap over. So unlike installing
3143 * the nop_submit_request on reset, we can do this from normal
3144 * context and do not require stop_machine().
3146 intel_engines_reset_default_submission(i915);
3147 i915_gem_contexts_lost(i915);
3149 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3150 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3156 i915_gem_retire_work_handler(struct work_struct *work)
3158 struct drm_i915_private *dev_priv =
3159 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3160 struct drm_device *dev = &dev_priv->drm;
3162 /* Come back later if the device is busy... */
3163 if (mutex_trylock(&dev->struct_mutex)) {
3164 i915_gem_retire_requests(dev_priv);
3165 mutex_unlock(&dev->struct_mutex);
3168 /* Keep the retire handler running until we are finally idle.
3169 * We do not need to do this test under locking as in the worst-case
3170 * we queue the retire worker once too often.
3172 if (READ_ONCE(dev_priv->gt.awake)) {
3173 i915_queue_hangcheck(dev_priv);
3174 queue_delayed_work(dev_priv->wq,
3175 &dev_priv->gt.retire_work,
3176 round_jiffies_up_relative(HZ));
3181 i915_gem_idle_work_handler(struct work_struct *work)
3183 struct drm_i915_private *dev_priv =
3184 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3185 struct drm_device *dev = &dev_priv->drm;
3186 bool rearm_hangcheck;
3188 if (!READ_ONCE(dev_priv->gt.awake))
3192 * Wait for last execlists context complete, but bail out in case a
3193 * new request is submitted.
3195 wait_for(intel_engines_are_idle(dev_priv), 10);
3196 if (READ_ONCE(dev_priv->gt.active_requests))
3200 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3202 if (!mutex_trylock(&dev->struct_mutex)) {
3203 /* Currently busy, come back later */
3204 mod_delayed_work(dev_priv->wq,
3205 &dev_priv->gt.idle_work,
3206 msecs_to_jiffies(50));
3211 * New request retired after this work handler started, extend active
3212 * period until next instance of the work.
3214 if (work_pending(work))
3217 if (dev_priv->gt.active_requests)
3220 if (wait_for(intel_engines_are_idle(dev_priv), 10))
3221 DRM_ERROR("Timeout waiting for engines to idle\n");
3223 intel_engines_mark_idle(dev_priv);
3224 i915_gem_timelines_mark_idle(dev_priv);
3226 GEM_BUG_ON(!dev_priv->gt.awake);
3227 dev_priv->gt.awake = false;
3228 rearm_hangcheck = false;
3230 if (INTEL_GEN(dev_priv) >= 6)
3231 gen6_rps_idle(dev_priv);
3232 intel_runtime_pm_put(dev_priv);
3234 mutex_unlock(&dev->struct_mutex);
3237 if (rearm_hangcheck) {
3238 GEM_BUG_ON(!dev_priv->gt.awake);
3239 i915_queue_hangcheck(dev_priv);
3243 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3245 struct drm_i915_private *i915 = to_i915(gem->dev);
3246 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3247 struct drm_i915_file_private *fpriv = file->driver_priv;
3248 struct i915_lut_handle *lut, *ln;
3250 mutex_lock(&i915->drm.struct_mutex);
3252 list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) {
3253 struct i915_gem_context *ctx = lut->ctx;
3254 struct i915_vma *vma;
3256 if (ctx->file_priv != fpriv)
3259 vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
3261 if (!i915_vma_is_ggtt(vma))
3262 i915_vma_close(vma);
3264 list_del(&lut->obj_link);
3265 list_del(&lut->ctx_link);
3267 kmem_cache_free(i915->luts, lut);
3268 __i915_gem_object_release_unless_active(obj);
3271 mutex_unlock(&i915->drm.struct_mutex);
3274 static unsigned long to_wait_timeout(s64 timeout_ns)
3277 return MAX_SCHEDULE_TIMEOUT;
3279 if (timeout_ns == 0)
3282 return nsecs_to_jiffies_timeout(timeout_ns);
3286 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3287 * @dev: drm device pointer
3288 * @data: ioctl data blob
3289 * @file: drm file pointer
3291 * Returns 0 if successful, else an error is returned with the remaining time in
3292 * the timeout parameter.
3293 * -ETIME: object is still busy after timeout
3294 * -ERESTARTSYS: signal interrupted the wait
3295 * -ENONENT: object doesn't exist
3296 * Also possible, but rare:
3297 * -EAGAIN: incomplete, restart syscall
3299 * -ENODEV: Internal IRQ fail
3300 * -E?: The add request failed
3302 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3303 * non-zero timeout parameter the wait ioctl will wait for the given number of
3304 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3305 * without holding struct_mutex the object may become re-busied before this
3306 * function completes. A similar but shorter * race condition exists in the busy
3310 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3312 struct drm_i915_gem_wait *args = data;
3313 struct drm_i915_gem_object *obj;
3317 if (args->flags != 0)
3320 obj = i915_gem_object_lookup(file, args->bo_handle);
3324 start = ktime_get();
3326 ret = i915_gem_object_wait(obj,
3327 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3328 to_wait_timeout(args->timeout_ns),
3329 to_rps_client(file));
3331 if (args->timeout_ns > 0) {
3332 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3333 if (args->timeout_ns < 0)
3334 args->timeout_ns = 0;
3337 * Apparently ktime isn't accurate enough and occasionally has a
3338 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3339 * things up to make the test happy. We allow up to 1 jiffy.
3341 * This is a regression from the timespec->ktime conversion.
3343 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3344 args->timeout_ns = 0;
3346 /* Asked to wait beyond the jiffie/scheduler precision? */
3347 if (ret == -ETIME && args->timeout_ns)
3351 i915_gem_object_put(obj);
3355 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3359 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3360 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3368 static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
3370 return wait_for(intel_engine_is_idle(engine), timeout_ms);
3373 static int wait_for_engines(struct drm_i915_private *i915)
3375 struct intel_engine_cs *engine;
3376 enum intel_engine_id id;
3378 for_each_engine(engine, i915, id) {
3379 if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
3380 i915_gem_set_wedged(i915);
3384 GEM_BUG_ON(intel_engine_get_seqno(engine) !=
3385 intel_engine_last_submit(engine));
3391 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3395 /* If the device is asleep, we have no requests outstanding */
3396 if (!READ_ONCE(i915->gt.awake))
3399 if (flags & I915_WAIT_LOCKED) {
3400 struct i915_gem_timeline *tl;
3402 lockdep_assert_held(&i915->drm.struct_mutex);
3404 list_for_each_entry(tl, &i915->gt.timelines, link) {
3405 ret = wait_for_timeline(tl, flags);
3410 i915_gem_retire_requests(i915);
3411 GEM_BUG_ON(i915->gt.active_requests);
3413 ret = wait_for_engines(i915);
3415 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3421 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3424 * We manually flush the CPU domain so that we can override and
3425 * force the flush for the display, and perform it asyncrhonously.
3427 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3428 if (obj->cache_dirty)
3429 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3430 obj->base.write_domain = 0;
3433 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3435 if (!READ_ONCE(obj->pin_display))
3438 mutex_lock(&obj->base.dev->struct_mutex);
3439 __i915_gem_object_flush_for_display(obj);
3440 mutex_unlock(&obj->base.dev->struct_mutex);
3444 * Moves a single object to the WC read, and possibly write domain.
3445 * @obj: object to act on
3446 * @write: ask for write access or read only
3448 * This function returns when the move is complete, including waiting on
3452 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
3456 lockdep_assert_held(&obj->base.dev->struct_mutex);
3458 ret = i915_gem_object_wait(obj,
3459 I915_WAIT_INTERRUPTIBLE |
3461 (write ? I915_WAIT_ALL : 0),
3462 MAX_SCHEDULE_TIMEOUT,
3467 if (obj->base.write_domain == I915_GEM_DOMAIN_WC)
3470 /* Flush and acquire obj->pages so that we are coherent through
3471 * direct access in memory with previous cached writes through
3472 * shmemfs and that our cache domain tracking remains valid.
3473 * For example, if the obj->filp was moved to swap without us
3474 * being notified and releasing the pages, we would mistakenly
3475 * continue to assume that the obj remained out of the CPU cached
3478 ret = i915_gem_object_pin_pages(obj);
3482 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
3484 /* Serialise direct access to this object with the barriers for
3485 * coherent writes from the GPU, by effectively invalidating the
3486 * WC domain upon first access.
3488 if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0)
3491 /* It should now be out of any other write domains, and we can update
3492 * the domain values for our changes.
3494 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);
3495 obj->base.read_domains |= I915_GEM_DOMAIN_WC;
3497 obj->base.read_domains = I915_GEM_DOMAIN_WC;
3498 obj->base.write_domain = I915_GEM_DOMAIN_WC;
3499 obj->mm.dirty = true;
3502 i915_gem_object_unpin_pages(obj);
3507 * Moves a single object to the GTT read, and possibly write domain.
3508 * @obj: object to act on
3509 * @write: ask for write access or read only
3511 * This function returns when the move is complete, including waiting on
3515 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3519 lockdep_assert_held(&obj->base.dev->struct_mutex);
3521 ret = i915_gem_object_wait(obj,
3522 I915_WAIT_INTERRUPTIBLE |
3524 (write ? I915_WAIT_ALL : 0),
3525 MAX_SCHEDULE_TIMEOUT,
3530 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3533 /* Flush and acquire obj->pages so that we are coherent through
3534 * direct access in memory with previous cached writes through
3535 * shmemfs and that our cache domain tracking remains valid.
3536 * For example, if the obj->filp was moved to swap without us
3537 * being notified and releasing the pages, we would mistakenly
3538 * continue to assume that the obj remained out of the CPU cached
3541 ret = i915_gem_object_pin_pages(obj);
3545 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
3547 /* Serialise direct access to this object with the barriers for
3548 * coherent writes from the GPU, by effectively invalidating the
3549 * GTT domain upon first access.
3551 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3554 /* It should now be out of any other write domains, and we can update
3555 * the domain values for our changes.
3557 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3558 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3560 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3561 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3562 obj->mm.dirty = true;
3565 i915_gem_object_unpin_pages(obj);
3570 * Changes the cache-level of an object across all VMA.
3571 * @obj: object to act on
3572 * @cache_level: new cache level to set for the object
3574 * After this function returns, the object will be in the new cache-level
3575 * across all GTT and the contents of the backing storage will be coherent,
3576 * with respect to the new cache-level. In order to keep the backing storage
3577 * coherent for all users, we only allow a single cache level to be set
3578 * globally on the object and prevent it from being changed whilst the
3579 * hardware is reading from the object. That is if the object is currently
3580 * on the scanout it will be set to uncached (or equivalent display
3581 * cache coherency) and all non-MOCS GPU access will also be uncached so
3582 * that all direct access to the scanout remains coherent.
3584 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3585 enum i915_cache_level cache_level)
3587 struct i915_vma *vma;
3590 lockdep_assert_held(&obj->base.dev->struct_mutex);
3592 if (obj->cache_level == cache_level)
3595 /* Inspect the list of currently bound VMA and unbind any that would
3596 * be invalid given the new cache-level. This is principally to
3597 * catch the issue of the CS prefetch crossing page boundaries and
3598 * reading an invalid PTE on older architectures.
3601 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3602 if (!drm_mm_node_allocated(&vma->node))
3605 if (i915_vma_is_pinned(vma)) {
3606 DRM_DEBUG("can not change the cache level of pinned objects\n");
3610 if (i915_gem_valid_gtt_space(vma, cache_level))
3613 ret = i915_vma_unbind(vma);
3617 /* As unbinding may affect other elements in the
3618 * obj->vma_list (due to side-effects from retiring
3619 * an active vma), play safe and restart the iterator.
3624 /* We can reuse the existing drm_mm nodes but need to change the
3625 * cache-level on the PTE. We could simply unbind them all and
3626 * rebind with the correct cache-level on next use. However since
3627 * we already have a valid slot, dma mapping, pages etc, we may as
3628 * rewrite the PTE in the belief that doing so tramples upon less
3629 * state and so involves less work.
3631 if (obj->bind_count) {
3632 /* Before we change the PTE, the GPU must not be accessing it.
3633 * If we wait upon the object, we know that all the bound
3634 * VMA are no longer active.
3636 ret = i915_gem_object_wait(obj,
3637 I915_WAIT_INTERRUPTIBLE |
3640 MAX_SCHEDULE_TIMEOUT,
3645 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3646 cache_level != I915_CACHE_NONE) {
3647 /* Access to snoopable pages through the GTT is
3648 * incoherent and on some machines causes a hard
3649 * lockup. Relinquish the CPU mmaping to force
3650 * userspace to refault in the pages and we can
3651 * then double check if the GTT mapping is still
3652 * valid for that pointer access.
3654 i915_gem_release_mmap(obj);
3656 /* As we no longer need a fence for GTT access,
3657 * we can relinquish it now (and so prevent having
3658 * to steal a fence from someone else on the next
3659 * fence request). Note GPU activity would have
3660 * dropped the fence as all snoopable access is
3661 * supposed to be linear.
3663 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3664 ret = i915_vma_put_fence(vma);
3669 /* We either have incoherent backing store and
3670 * so no GTT access or the architecture is fully
3671 * coherent. In such cases, existing GTT mmaps
3672 * ignore the cache bit in the PTE and we can
3673 * rewrite it without confusing the GPU or having
3674 * to force userspace to fault back in its mmaps.
3678 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3679 if (!drm_mm_node_allocated(&vma->node))
3682 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3688 list_for_each_entry(vma, &obj->vma_list, obj_link)
3689 vma->node.color = cache_level;
3690 i915_gem_object_set_cache_coherency(obj, cache_level);
3691 obj->cache_dirty = true; /* Always invalidate stale cachelines */
3696 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3697 struct drm_file *file)
3699 struct drm_i915_gem_caching *args = data;
3700 struct drm_i915_gem_object *obj;
3704 obj = i915_gem_object_lookup_rcu(file, args->handle);
3710 switch (obj->cache_level) {
3711 case I915_CACHE_LLC:
3712 case I915_CACHE_L3_LLC:
3713 args->caching = I915_CACHING_CACHED;
3717 args->caching = I915_CACHING_DISPLAY;
3721 args->caching = I915_CACHING_NONE;
3729 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3730 struct drm_file *file)
3732 struct drm_i915_private *i915 = to_i915(dev);
3733 struct drm_i915_gem_caching *args = data;
3734 struct drm_i915_gem_object *obj;
3735 enum i915_cache_level level;
3738 switch (args->caching) {
3739 case I915_CACHING_NONE:
3740 level = I915_CACHE_NONE;
3742 case I915_CACHING_CACHED:
3744 * Due to a HW issue on BXT A stepping, GPU stores via a
3745 * snooped mapping may leave stale data in a corresponding CPU
3746 * cacheline, whereas normally such cachelines would get
3749 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3752 level = I915_CACHE_LLC;
3754 case I915_CACHING_DISPLAY:
3755 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3761 obj = i915_gem_object_lookup(file, args->handle);
3765 if (obj->cache_level == level)
3768 ret = i915_gem_object_wait(obj,
3769 I915_WAIT_INTERRUPTIBLE,
3770 MAX_SCHEDULE_TIMEOUT,
3771 to_rps_client(file));
3775 ret = i915_mutex_lock_interruptible(dev);
3779 ret = i915_gem_object_set_cache_level(obj, level);
3780 mutex_unlock(&dev->struct_mutex);
3783 i915_gem_object_put(obj);
3788 * Prepare buffer for display plane (scanout, cursors, etc).
3789 * Can be called from an uninterruptible phase (modesetting) and allows
3790 * any flushes to be pipelined (for pageflips).
3793 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3795 const struct i915_ggtt_view *view)
3797 struct i915_vma *vma;
3800 lockdep_assert_held(&obj->base.dev->struct_mutex);
3802 /* Mark the pin_display early so that we account for the
3803 * display coherency whilst setting up the cache domains.
3807 /* The display engine is not coherent with the LLC cache on gen6. As
3808 * a result, we make sure that the pinning that is about to occur is
3809 * done with uncached PTEs. This is lowest common denominator for all
3812 * However for gen6+, we could do better by using the GFDT bit instead
3813 * of uncaching, which would allow us to flush all the LLC-cached data
3814 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3816 ret = i915_gem_object_set_cache_level(obj,
3817 HAS_WT(to_i915(obj->base.dev)) ?
3818 I915_CACHE_WT : I915_CACHE_NONE);
3821 goto err_unpin_display;
3824 /* As the user may map the buffer once pinned in the display plane
3825 * (e.g. libkms for the bootup splash), we have to ensure that we
3826 * always use map_and_fenceable for all scanout buffers. However,
3827 * it may simply be too big to fit into mappable, in which case
3828 * put it anyway and hope that userspace can cope (but always first
3829 * try to preserve the existing ABI).
3831 vma = ERR_PTR(-ENOSPC);
3832 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3833 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3834 PIN_MAPPABLE | PIN_NONBLOCK);
3836 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3839 /* Valleyview is definitely limited to scanning out the first
3840 * 512MiB. Lets presume this behaviour was inherited from the
3841 * g4x display engine and that all earlier gen are similarly
3842 * limited. Testing suggests that it is a little more
3843 * complicated than this. For example, Cherryview appears quite
3844 * happy to scanout from anywhere within its global aperture.
3847 if (HAS_GMCH_DISPLAY(i915))
3848 flags = PIN_MAPPABLE;
3849 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3852 goto err_unpin_display;
3854 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3856 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3857 __i915_gem_object_flush_for_display(obj);
3858 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3860 /* It should now be out of any other write domains, and we can update
3861 * the domain values for our changes.
3863 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3873 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3875 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3877 if (WARN_ON(vma->obj->pin_display == 0))
3880 if (--vma->obj->pin_display == 0)
3881 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3883 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3884 i915_gem_object_bump_inactive_ggtt(vma->obj);
3886 i915_vma_unpin(vma);
3890 * Moves a single object to the CPU read, and possibly write domain.
3891 * @obj: object to act on
3892 * @write: requesting write or read-only access
3894 * This function returns when the move is complete, including waiting on
3898 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3902 lockdep_assert_held(&obj->base.dev->struct_mutex);
3904 ret = i915_gem_object_wait(obj,
3905 I915_WAIT_INTERRUPTIBLE |
3907 (write ? I915_WAIT_ALL : 0),
3908 MAX_SCHEDULE_TIMEOUT,
3913 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3915 /* Flush the CPU cache if it's still invalid. */
3916 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3917 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3918 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3921 /* It should now be out of any other write domains, and we can update
3922 * the domain values for our changes.
3924 GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3926 /* If we're writing through the CPU, then the GPU read domains will
3927 * need to be invalidated at next use.
3930 __start_cpu_write(obj);
3935 /* Throttle our rendering by waiting until the ring has completed our requests
3936 * emitted over 20 msec ago.
3938 * Note that if we were to use the current jiffies each time around the loop,
3939 * we wouldn't escape the function with any frames outstanding if the time to
3940 * render a frame was over 20ms.
3942 * This should get us reasonable parallelism between CPU and GPU but also
3943 * relatively low latency when blocking on a particular request to finish.
3946 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3948 struct drm_i915_private *dev_priv = to_i915(dev);
3949 struct drm_i915_file_private *file_priv = file->driver_priv;
3950 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3951 struct drm_i915_gem_request *request, *target = NULL;
3954 /* ABI: return -EIO if already wedged */
3955 if (i915_terminally_wedged(&dev_priv->gpu_error))
3958 spin_lock(&file_priv->mm.lock);
3959 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3960 if (time_after_eq(request->emitted_jiffies, recent_enough))
3964 list_del(&target->client_link);
3965 target->file_priv = NULL;
3971 i915_gem_request_get(target);
3972 spin_unlock(&file_priv->mm.lock);
3977 ret = i915_wait_request(target,
3978 I915_WAIT_INTERRUPTIBLE,
3979 MAX_SCHEDULE_TIMEOUT);
3980 i915_gem_request_put(target);
3982 return ret < 0 ? ret : 0;
3986 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3987 const struct i915_ggtt_view *view,
3992 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3993 struct i915_address_space *vm = &dev_priv->ggtt.base;
3994 struct i915_vma *vma;
3997 lockdep_assert_held(&obj->base.dev->struct_mutex);
3999 vma = i915_vma_instance(obj, vm, view);
4000 if (unlikely(IS_ERR(vma)))
4003 if (i915_vma_misplaced(vma, size, alignment, flags)) {
4004 if (flags & PIN_NONBLOCK &&
4005 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
4006 return ERR_PTR(-ENOSPC);
4008 if (flags & PIN_MAPPABLE) {
4009 /* If the required space is larger than the available
4010 * aperture, we will not able to find a slot for the
4011 * object and unbinding the object now will be in
4012 * vain. Worse, doing so may cause us to ping-pong
4013 * the object in and out of the Global GTT and
4014 * waste a lot of cycles under the mutex.
4016 if (vma->fence_size > dev_priv->ggtt.mappable_end)
4017 return ERR_PTR(-E2BIG);
4019 /* If NONBLOCK is set the caller is optimistically
4020 * trying to cache the full object within the mappable
4021 * aperture, and *must* have a fallback in place for
4022 * situations where we cannot bind the object. We
4023 * can be a little more lax here and use the fallback
4024 * more often to avoid costly migrations of ourselves
4025 * and other objects within the aperture.
4027 * Half-the-aperture is used as a simple heuristic.
4028 * More interesting would to do search for a free
4029 * block prior to making the commitment to unbind.
4030 * That caters for the self-harm case, and with a
4031 * little more heuristics (e.g. NOFAULT, NOEVICT)
4032 * we could try to minimise harm to others.
4034 if (flags & PIN_NONBLOCK &&
4035 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
4036 return ERR_PTR(-ENOSPC);
4039 WARN(i915_vma_is_pinned(vma),
4040 "bo is already pinned in ggtt with incorrect alignment:"
4041 " offset=%08x, req.alignment=%llx,"
4042 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4043 i915_ggtt_offset(vma), alignment,
4044 !!(flags & PIN_MAPPABLE),
4045 i915_vma_is_map_and_fenceable(vma));
4046 ret = i915_vma_unbind(vma);
4048 return ERR_PTR(ret);
4051 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
4053 return ERR_PTR(ret);
4058 static __always_inline unsigned int __busy_read_flag(unsigned int id)
4060 /* Note that we could alias engines in the execbuf API, but
4061 * that would be very unwise as it prevents userspace from
4062 * fine control over engine selection. Ahem.
4064 * This should be something like EXEC_MAX_ENGINE instead of
4067 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
4068 return 0x10000 << id;
4071 static __always_inline unsigned int __busy_write_id(unsigned int id)
4073 /* The uABI guarantees an active writer is also amongst the read
4074 * engines. This would be true if we accessed the activity tracking
4075 * under the lock, but as we perform the lookup of the object and
4076 * its activity locklessly we can not guarantee that the last_write
4077 * being active implies that we have set the same engine flag from
4078 * last_read - hence we always set both read and write busy for
4081 return id | __busy_read_flag(id);
4084 static __always_inline unsigned int
4085 __busy_set_if_active(const struct dma_fence *fence,
4086 unsigned int (*flag)(unsigned int id))
4088 struct drm_i915_gem_request *rq;
4090 /* We have to check the current hw status of the fence as the uABI
4091 * guarantees forward progress. We could rely on the idle worker
4092 * to eventually flush us, but to minimise latency just ask the
4095 * Note we only report on the status of native fences.
4097 if (!dma_fence_is_i915(fence))
4100 /* opencode to_request() in order to avoid const warnings */
4101 rq = container_of(fence, struct drm_i915_gem_request, fence);
4102 if (i915_gem_request_completed(rq))
4105 return flag(rq->engine->uabi_id);
4108 static __always_inline unsigned int
4109 busy_check_reader(const struct dma_fence *fence)
4111 return __busy_set_if_active(fence, __busy_read_flag);
4114 static __always_inline unsigned int
4115 busy_check_writer(const struct dma_fence *fence)
4120 return __busy_set_if_active(fence, __busy_write_id);
4124 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4125 struct drm_file *file)
4127 struct drm_i915_gem_busy *args = data;
4128 struct drm_i915_gem_object *obj;
4129 struct reservation_object_list *list;
4135 obj = i915_gem_object_lookup_rcu(file, args->handle);
4139 /* A discrepancy here is that we do not report the status of
4140 * non-i915 fences, i.e. even though we may report the object as idle,
4141 * a call to set-domain may still stall waiting for foreign rendering.
4142 * This also means that wait-ioctl may report an object as busy,
4143 * where busy-ioctl considers it idle.
4145 * We trade the ability to warn of foreign fences to report on which
4146 * i915 engines are active for the object.
4148 * Alternatively, we can trade that extra information on read/write
4151 * !reservation_object_test_signaled_rcu(obj->resv, true);
4152 * to report the overall busyness. This is what the wait-ioctl does.
4156 seq = raw_read_seqcount(&obj->resv->seq);
4158 /* Translate the exclusive fence to the READ *and* WRITE engine */
4159 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4161 /* Translate shared fences to READ set of engines */
4162 list = rcu_dereference(obj->resv->fence);
4164 unsigned int shared_count = list->shared_count, i;
4166 for (i = 0; i < shared_count; ++i) {
4167 struct dma_fence *fence =
4168 rcu_dereference(list->shared[i]);
4170 args->busy |= busy_check_reader(fence);
4174 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4184 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4185 struct drm_file *file_priv)
4187 return i915_gem_ring_throttle(dev, file_priv);
4191 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4192 struct drm_file *file_priv)
4194 struct drm_i915_private *dev_priv = to_i915(dev);
4195 struct drm_i915_gem_madvise *args = data;
4196 struct drm_i915_gem_object *obj;
4199 switch (args->madv) {
4200 case I915_MADV_DONTNEED:
4201 case I915_MADV_WILLNEED:
4207 obj = i915_gem_object_lookup(file_priv, args->handle);
4211 err = mutex_lock_interruptible(&obj->mm.lock);
4215 if (obj->mm.pages &&
4216 i915_gem_object_is_tiled(obj) &&
4217 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4218 if (obj->mm.madv == I915_MADV_WILLNEED) {
4219 GEM_BUG_ON(!obj->mm.quirked);
4220 __i915_gem_object_unpin_pages(obj);
4221 obj->mm.quirked = false;
4223 if (args->madv == I915_MADV_WILLNEED) {
4224 GEM_BUG_ON(obj->mm.quirked);
4225 __i915_gem_object_pin_pages(obj);
4226 obj->mm.quirked = true;
4230 if (obj->mm.madv != __I915_MADV_PURGED)
4231 obj->mm.madv = args->madv;
4233 /* if the object is no longer attached, discard its backing storage */
4234 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4235 i915_gem_object_truncate(obj);
4237 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4238 mutex_unlock(&obj->mm.lock);
4241 i915_gem_object_put(obj);
4246 frontbuffer_retire(struct i915_gem_active *active,
4247 struct drm_i915_gem_request *request)
4249 struct drm_i915_gem_object *obj =
4250 container_of(active, typeof(*obj), frontbuffer_write);
4252 intel_fb_obj_flush(obj, ORIGIN_CS);
4255 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4256 const struct drm_i915_gem_object_ops *ops)
4258 mutex_init(&obj->mm.lock);
4260 INIT_LIST_HEAD(&obj->global_link);
4261 INIT_LIST_HEAD(&obj->userfault_link);
4262 INIT_LIST_HEAD(&obj->vma_list);
4263 INIT_LIST_HEAD(&obj->lut_list);
4264 INIT_LIST_HEAD(&obj->batch_pool_link);
4268 reservation_object_init(&obj->__builtin_resv);
4269 obj->resv = &obj->__builtin_resv;
4271 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4272 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4274 obj->mm.madv = I915_MADV_WILLNEED;
4275 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4276 mutex_init(&obj->mm.get_page.lock);
4278 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4281 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4282 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4283 I915_GEM_OBJECT_IS_SHRINKABLE,
4285 .get_pages = i915_gem_object_get_pages_gtt,
4286 .put_pages = i915_gem_object_put_pages_gtt,
4288 .pwrite = i915_gem_object_pwrite_gtt,
4291 struct drm_i915_gem_object *
4292 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4294 struct drm_i915_gem_object *obj;
4295 struct address_space *mapping;
4296 unsigned int cache_level;
4300 /* There is a prevalence of the assumption that we fit the object's
4301 * page count inside a 32bit _signed_ variable. Let's document this and
4302 * catch if we ever need to fix it. In the meantime, if you do spot
4303 * such a local variable, please consider fixing!
4305 if (size >> PAGE_SHIFT > INT_MAX)
4306 return ERR_PTR(-E2BIG);
4308 if (overflows_type(size, obj->base.size))
4309 return ERR_PTR(-E2BIG);
4311 obj = i915_gem_object_alloc(dev_priv);
4313 return ERR_PTR(-ENOMEM);
4315 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4319 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4320 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4321 /* 965gm cannot relocate objects above 4GiB. */
4322 mask &= ~__GFP_HIGHMEM;
4323 mask |= __GFP_DMA32;
4326 mapping = obj->base.filp->f_mapping;
4327 mapping_set_gfp_mask(mapping, mask);
4328 GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
4330 i915_gem_object_init(obj, &i915_gem_object_ops);
4332 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4333 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4335 if (HAS_LLC(dev_priv))
4336 /* On some devices, we can have the GPU use the LLC (the CPU
4337 * cache) for about a 10% performance improvement
4338 * compared to uncached. Graphics requests other than
4339 * display scanout are coherent with the CPU in
4340 * accessing this cache. This means in this mode we
4341 * don't need to clflush on the CPU side, and on the
4342 * GPU side we only need to flush internal caches to
4343 * get data visible to the CPU.
4345 * However, we maintain the display planes as UC, and so
4346 * need to rebind when first used as such.
4348 cache_level = I915_CACHE_LLC;
4350 cache_level = I915_CACHE_NONE;
4352 i915_gem_object_set_cache_coherency(obj, cache_level);
4354 trace_i915_gem_object_create(obj);
4359 i915_gem_object_free(obj);
4360 return ERR_PTR(ret);
4363 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4365 /* If we are the last user of the backing storage (be it shmemfs
4366 * pages or stolen etc), we know that the pages are going to be
4367 * immediately released. In this case, we can then skip copying
4368 * back the contents from the GPU.
4371 if (obj->mm.madv != I915_MADV_WILLNEED)
4374 if (obj->base.filp == NULL)
4377 /* At first glance, this looks racy, but then again so would be
4378 * userspace racing mmap against close. However, the first external
4379 * reference to the filp can only be obtained through the
4380 * i915_gem_mmap_ioctl() which safeguards us against the user
4381 * acquiring such a reference whilst we are in the middle of
4382 * freeing the object.
4384 return atomic_long_read(&obj->base.filp->f_count) == 1;
4387 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4388 struct llist_node *freed)
4390 struct drm_i915_gem_object *obj, *on;
4392 mutex_lock(&i915->drm.struct_mutex);
4393 intel_runtime_pm_get(i915);
4394 llist_for_each_entry(obj, freed, freed) {
4395 struct i915_vma *vma, *vn;
4397 trace_i915_gem_object_destroy(obj);
4399 GEM_BUG_ON(i915_gem_object_is_active(obj));
4400 list_for_each_entry_safe(vma, vn,
4401 &obj->vma_list, obj_link) {
4402 GEM_BUG_ON(i915_vma_is_active(vma));
4403 vma->flags &= ~I915_VMA_PIN_MASK;
4404 i915_vma_close(vma);
4406 GEM_BUG_ON(!list_empty(&obj->vma_list));
4407 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4409 list_del(&obj->global_link);
4411 intel_runtime_pm_put(i915);
4412 mutex_unlock(&i915->drm.struct_mutex);
4416 llist_for_each_entry_safe(obj, on, freed, freed) {
4417 GEM_BUG_ON(obj->bind_count);
4418 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4420 if (obj->ops->release)
4421 obj->ops->release(obj);
4423 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4424 atomic_set(&obj->mm.pages_pin_count, 0);
4425 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4426 GEM_BUG_ON(obj->mm.pages);
4428 if (obj->base.import_attach)
4429 drm_prime_gem_destroy(&obj->base, NULL);
4431 reservation_object_fini(&obj->__builtin_resv);
4432 drm_gem_object_release(&obj->base);
4433 i915_gem_info_remove_obj(i915, obj->base.size);
4436 i915_gem_object_free(obj);
4440 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4442 struct llist_node *freed;
4444 freed = llist_del_all(&i915->mm.free_list);
4445 if (unlikely(freed))
4446 __i915_gem_free_objects(i915, freed);
4449 static void __i915_gem_free_work(struct work_struct *work)
4451 struct drm_i915_private *i915 =
4452 container_of(work, struct drm_i915_private, mm.free_work);
4453 struct llist_node *freed;
4455 /* All file-owned VMA should have been released by this point through
4456 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4457 * However, the object may also be bound into the global GTT (e.g.
4458 * older GPUs without per-process support, or for direct access through
4459 * the GTT either for the user or for scanout). Those VMA still need to
4463 while ((freed = llist_del_all(&i915->mm.free_list))) {
4464 __i915_gem_free_objects(i915, freed);
4470 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4472 struct drm_i915_gem_object *obj =
4473 container_of(head, typeof(*obj), rcu);
4474 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4476 /* We can't simply use call_rcu() from i915_gem_free_object()
4477 * as we need to block whilst unbinding, and the call_rcu
4478 * task may be called from softirq context. So we take a
4479 * detour through a worker.
4481 if (llist_add(&obj->freed, &i915->mm.free_list))
4482 schedule_work(&i915->mm.free_work);
4485 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4487 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4489 if (obj->mm.quirked)
4490 __i915_gem_object_unpin_pages(obj);
4492 if (discard_backing_storage(obj))
4493 obj->mm.madv = I915_MADV_DONTNEED;
4495 /* Before we free the object, make sure any pure RCU-only
4496 * read-side critical sections are complete, e.g.
4497 * i915_gem_busy_ioctl(). For the corresponding synchronized
4498 * lookup see i915_gem_object_lookup_rcu().
4500 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4503 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4505 lockdep_assert_held(&obj->base.dev->struct_mutex);
4507 if (!i915_gem_object_has_active_reference(obj) &&
4508 i915_gem_object_is_active(obj))
4509 i915_gem_object_set_active_reference(obj);
4511 i915_gem_object_put(obj);
4514 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4516 struct intel_engine_cs *engine;
4517 enum intel_engine_id id;
4519 for_each_engine(engine, dev_priv, id)
4520 GEM_BUG_ON(engine->last_retired_context &&
4521 !i915_gem_context_is_kernel(engine->last_retired_context));
4524 void i915_gem_sanitize(struct drm_i915_private *i915)
4527 * If we inherit context state from the BIOS or earlier occupants
4528 * of the GPU, the GPU may be in an inconsistent state when we
4529 * try to take over. The only way to remove the earlier state
4530 * is by resetting. However, resetting on earlier gen is tricky as
4531 * it may impact the display and we are uncertain about the stability
4532 * of the reset, so this could be applied to even earlier gen.
4534 if (INTEL_GEN(i915) >= 5) {
4535 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4536 WARN_ON(reset && reset != -ENODEV);
4540 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4542 struct drm_device *dev = &dev_priv->drm;
4545 intel_runtime_pm_get(dev_priv);
4546 intel_suspend_gt_powersave(dev_priv);
4548 mutex_lock(&dev->struct_mutex);
4550 /* We have to flush all the executing contexts to main memory so
4551 * that they can saved in the hibernation image. To ensure the last
4552 * context image is coherent, we have to switch away from it. That
4553 * leaves the dev_priv->kernel_context still active when
4554 * we actually suspend, and its image in memory may not match the GPU
4555 * state. Fortunately, the kernel_context is disposable and we do
4556 * not rely on its state.
4558 ret = i915_gem_switch_to_kernel_context(dev_priv);
4562 ret = i915_gem_wait_for_idle(dev_priv,
4563 I915_WAIT_INTERRUPTIBLE |
4568 assert_kernel_context_is_current(dev_priv);
4569 i915_gem_contexts_lost(dev_priv);
4570 mutex_unlock(&dev->struct_mutex);
4572 intel_guc_suspend(dev_priv);
4574 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4575 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4577 /* As the idle_work is rearming if it detects a race, play safe and
4578 * repeat the flush until it is definitely idle.
4580 while (flush_delayed_work(&dev_priv->gt.idle_work))
4583 /* Assert that we sucessfully flushed all the work and
4584 * reset the GPU back to its idle, low power state.
4586 WARN_ON(dev_priv->gt.awake);
4587 WARN_ON(!intel_engines_are_idle(dev_priv));
4590 * Neither the BIOS, ourselves or any other kernel
4591 * expects the system to be in execlists mode on startup,
4592 * so we need to reset the GPU back to legacy mode. And the only
4593 * known way to disable logical contexts is through a GPU reset.
4595 * So in order to leave the system in a known default configuration,
4596 * always reset the GPU upon unload and suspend. Afterwards we then
4597 * clean up the GEM state tracking, flushing off the requests and
4598 * leaving the system in a known idle state.
4600 * Note that is of the upmost importance that the GPU is idle and
4601 * all stray writes are flushed *before* we dismantle the backing
4602 * storage for the pinned objects.
4604 * However, since we are uncertain that resetting the GPU on older
4605 * machines is a good idea, we don't - just in case it leaves the
4606 * machine in an unusable condition.
4608 i915_gem_sanitize(dev_priv);
4612 mutex_unlock(&dev->struct_mutex);
4614 intel_runtime_pm_put(dev_priv);
4618 void i915_gem_resume(struct drm_i915_private *dev_priv)
4620 struct drm_device *dev = &dev_priv->drm;
4622 WARN_ON(dev_priv->gt.awake);
4624 mutex_lock(&dev->struct_mutex);
4625 i915_gem_restore_gtt_mappings(dev_priv);
4627 /* As we didn't flush the kernel context before suspend, we cannot
4628 * guarantee that the context image is complete. So let's just reset
4629 * it and start again.
4631 dev_priv->gt.resume(dev_priv);
4633 mutex_unlock(&dev->struct_mutex);
4636 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4638 if (INTEL_GEN(dev_priv) < 5 ||
4639 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4642 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4643 DISP_TILE_SURFACE_SWIZZLING);
4645 if (IS_GEN5(dev_priv))
4648 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4649 if (IS_GEN6(dev_priv))
4650 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4651 else if (IS_GEN7(dev_priv))
4652 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4653 else if (IS_GEN8(dev_priv))
4654 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4659 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4661 I915_WRITE(RING_CTL(base), 0);
4662 I915_WRITE(RING_HEAD(base), 0);
4663 I915_WRITE(RING_TAIL(base), 0);
4664 I915_WRITE(RING_START(base), 0);
4667 static void init_unused_rings(struct drm_i915_private *dev_priv)
4669 if (IS_I830(dev_priv)) {
4670 init_unused_ring(dev_priv, PRB1_BASE);
4671 init_unused_ring(dev_priv, SRB0_BASE);
4672 init_unused_ring(dev_priv, SRB1_BASE);
4673 init_unused_ring(dev_priv, SRB2_BASE);
4674 init_unused_ring(dev_priv, SRB3_BASE);
4675 } else if (IS_GEN2(dev_priv)) {
4676 init_unused_ring(dev_priv, SRB0_BASE);
4677 init_unused_ring(dev_priv, SRB1_BASE);
4678 } else if (IS_GEN3(dev_priv)) {
4679 init_unused_ring(dev_priv, PRB1_BASE);
4680 init_unused_ring(dev_priv, PRB2_BASE);
4684 static int __i915_gem_restart_engines(void *data)
4686 struct drm_i915_private *i915 = data;
4687 struct intel_engine_cs *engine;
4688 enum intel_engine_id id;
4691 for_each_engine(engine, i915, id) {
4692 err = engine->init_hw(engine);
4700 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4704 dev_priv->gt.last_init_time = ktime_get();
4706 /* Double layer security blanket, see i915_gem_init() */
4707 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4709 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4710 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4712 if (IS_HASWELL(dev_priv))
4713 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4714 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4716 if (HAS_PCH_NOP(dev_priv)) {
4717 if (IS_IVYBRIDGE(dev_priv)) {
4718 u32 temp = I915_READ(GEN7_MSG_CTL);
4719 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4720 I915_WRITE(GEN7_MSG_CTL, temp);
4721 } else if (INTEL_GEN(dev_priv) >= 7) {
4722 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4723 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4724 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4728 i915_gem_init_swizzling(dev_priv);
4731 * At least 830 can leave some of the unused rings
4732 * "active" (ie. head != tail) after resume which
4733 * will prevent c3 entry. Makes sure all unused rings
4736 init_unused_rings(dev_priv);
4738 BUG_ON(!dev_priv->kernel_context);
4740 ret = i915_ppgtt_init_hw(dev_priv);
4742 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4746 /* Need to do basic initialisation of all rings first: */
4747 ret = __i915_gem_restart_engines(dev_priv);
4751 intel_mocs_init_l3cc_table(dev_priv);
4753 /* We can't enable contexts until all firmware is loaded */
4754 ret = intel_uc_init_hw(dev_priv);
4759 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4763 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4765 if (INTEL_INFO(dev_priv)->gen < 6)
4768 /* TODO: make semaphores and Execlists play nicely together */
4769 if (i915.enable_execlists)
4775 /* Enable semaphores on SNB when IO remapping is off */
4776 if (IS_GEN6(dev_priv) && intel_vtd_active())
4782 int i915_gem_init(struct drm_i915_private *dev_priv)
4786 mutex_lock(&dev_priv->drm.struct_mutex);
4788 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
4790 if (!i915.enable_execlists) {
4791 dev_priv->gt.resume = intel_legacy_submission_resume;
4792 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4794 dev_priv->gt.resume = intel_lr_context_resume;
4795 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4798 /* This is just a security blanket to placate dragons.
4799 * On some systems, we very sporadically observe that the first TLBs
4800 * used by the CS may be stale, despite us poking the TLB reset. If
4801 * we hold the forcewake during initialisation these problems
4802 * just magically go away.
4804 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4806 ret = i915_gem_init_userptr(dev_priv);
4810 ret = i915_gem_init_ggtt(dev_priv);
4814 ret = i915_gem_contexts_init(dev_priv);
4818 ret = intel_engines_init(dev_priv);
4822 ret = i915_gem_init_hw(dev_priv);
4824 /* Allow engine initialisation to fail by marking the GPU as
4825 * wedged. But we only want to do this where the GPU is angry,
4826 * for all other failure, such as an allocation failure, bail.
4828 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4829 i915_gem_set_wedged(dev_priv);
4834 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4835 mutex_unlock(&dev_priv->drm.struct_mutex);
4840 void i915_gem_init_mmio(struct drm_i915_private *i915)
4842 i915_gem_sanitize(i915);
4846 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4848 struct intel_engine_cs *engine;
4849 enum intel_engine_id id;
4851 for_each_engine(engine, dev_priv, id)
4852 dev_priv->gt.cleanup_engine(engine);
4856 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4860 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4861 !IS_CHERRYVIEW(dev_priv))
4862 dev_priv->num_fence_regs = 32;
4863 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4864 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4865 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4866 dev_priv->num_fence_regs = 16;
4868 dev_priv->num_fence_regs = 8;
4870 if (intel_vgpu_active(dev_priv))
4871 dev_priv->num_fence_regs =
4872 I915_READ(vgtif_reg(avail_rs.fence_num));
4874 /* Initialize fence registers to zero */
4875 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4876 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4878 fence->i915 = dev_priv;
4880 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4882 i915_gem_restore_fences(dev_priv);
4884 i915_gem_detect_bit_6_swizzle(dev_priv);
4888 i915_gem_load_init(struct drm_i915_private *dev_priv)
4892 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4893 if (!dev_priv->objects)
4896 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4897 if (!dev_priv->vmas)
4900 dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0);
4901 if (!dev_priv->luts)
4904 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4905 SLAB_HWCACHE_ALIGN |
4906 SLAB_RECLAIM_ACCOUNT |
4907 SLAB_TYPESAFE_BY_RCU);
4908 if (!dev_priv->requests)
4911 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4912 SLAB_HWCACHE_ALIGN |
4913 SLAB_RECLAIM_ACCOUNT);
4914 if (!dev_priv->dependencies)
4917 dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
4918 if (!dev_priv->priorities)
4919 goto err_dependencies;
4921 mutex_lock(&dev_priv->drm.struct_mutex);
4922 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4923 err = i915_gem_timeline_init__global(dev_priv);
4924 mutex_unlock(&dev_priv->drm.struct_mutex);
4926 goto err_priorities;
4928 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4929 init_llist_head(&dev_priv->mm.free_list);
4930 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4931 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4932 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4933 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4934 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4935 i915_gem_retire_work_handler);
4936 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4937 i915_gem_idle_work_handler);
4938 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4939 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4941 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4943 spin_lock_init(&dev_priv->fb_tracking.lock);
4948 kmem_cache_destroy(dev_priv->priorities);
4950 kmem_cache_destroy(dev_priv->dependencies);
4952 kmem_cache_destroy(dev_priv->requests);
4954 kmem_cache_destroy(dev_priv->luts);
4956 kmem_cache_destroy(dev_priv->vmas);
4958 kmem_cache_destroy(dev_priv->objects);
4963 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4965 i915_gem_drain_freed_objects(dev_priv);
4966 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4967 WARN_ON(dev_priv->mm.object_count);
4969 mutex_lock(&dev_priv->drm.struct_mutex);
4970 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4971 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4972 mutex_unlock(&dev_priv->drm.struct_mutex);
4974 kmem_cache_destroy(dev_priv->priorities);
4975 kmem_cache_destroy(dev_priv->dependencies);
4976 kmem_cache_destroy(dev_priv->requests);
4977 kmem_cache_destroy(dev_priv->luts);
4978 kmem_cache_destroy(dev_priv->vmas);
4979 kmem_cache_destroy(dev_priv->objects);
4981 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4985 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4987 /* Discard all purgeable objects, let userspace recover those as
4988 * required after resuming.
4990 i915_gem_shrink_all(dev_priv);
4995 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4997 struct drm_i915_gem_object *obj;
4998 struct list_head *phases[] = {
4999 &dev_priv->mm.unbound_list,
5000 &dev_priv->mm.bound_list,
5004 /* Called just before we write the hibernation image.
5006 * We need to update the domain tracking to reflect that the CPU
5007 * will be accessing all the pages to create and restore from the
5008 * hibernation, and so upon restoration those pages will be in the
5011 * To make sure the hibernation image contains the latest state,
5012 * we update that state just before writing out the image.
5014 * To try and reduce the hibernation image, we manually shrink
5015 * the objects as well, see i915_gem_freeze()
5018 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
5019 i915_gem_drain_freed_objects(dev_priv);
5021 mutex_lock(&dev_priv->drm.struct_mutex);
5022 for (p = phases; *p; p++) {
5023 list_for_each_entry(obj, *p, global_link)
5024 __start_cpu_write(obj);
5026 mutex_unlock(&dev_priv->drm.struct_mutex);
5031 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5033 struct drm_i915_file_private *file_priv = file->driver_priv;
5034 struct drm_i915_gem_request *request;
5036 /* Clean up our request list when the client is going away, so that
5037 * later retire_requests won't dereference our soon-to-be-gone
5040 spin_lock(&file_priv->mm.lock);
5041 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
5042 request->file_priv = NULL;
5043 spin_unlock(&file_priv->mm.lock);
5046 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
5048 struct drm_i915_file_private *file_priv;
5053 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5057 file->driver_priv = file_priv;
5058 file_priv->dev_priv = i915;
5059 file_priv->file = file;
5061 spin_lock_init(&file_priv->mm.lock);
5062 INIT_LIST_HEAD(&file_priv->mm.request_list);
5064 file_priv->bsd_engine = -1;
5066 ret = i915_gem_context_open(i915, file);
5074 * i915_gem_track_fb - update frontbuffer tracking
5075 * @old: current GEM buffer for the frontbuffer slots
5076 * @new: new GEM buffer for the frontbuffer slots
5077 * @frontbuffer_bits: bitmask of frontbuffer slots
5079 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5080 * from @old and setting them in @new. Both @old and @new can be NULL.
5082 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5083 struct drm_i915_gem_object *new,
5084 unsigned frontbuffer_bits)
5086 /* Control of individual bits within the mask are guarded by
5087 * the owning plane->mutex, i.e. we can never see concurrent
5088 * manipulation of individual bits. But since the bitfield as a whole
5089 * is updated using RMW, we need to use atomics in order to update
5092 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
5093 sizeof(atomic_t) * BITS_PER_BYTE);
5096 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
5097 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
5101 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
5102 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
5106 /* Allocate a new GEM object and fill it with the supplied data */
5107 struct drm_i915_gem_object *
5108 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
5109 const void *data, size_t size)
5111 struct drm_i915_gem_object *obj;
5116 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
5120 GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
5122 file = obj->base.filp;
5125 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
5127 void *pgdata, *vaddr;
5129 err = pagecache_write_begin(file, file->f_mapping,
5136 memcpy(vaddr, data, len);
5139 err = pagecache_write_end(file, file->f_mapping,
5153 i915_gem_object_put(obj);
5154 return ERR_PTR(err);
5157 struct scatterlist *
5158 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
5160 unsigned int *offset)
5162 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
5163 struct scatterlist *sg;
5164 unsigned int idx, count;
5167 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
5168 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
5170 /* As we iterate forward through the sg, we record each entry in a
5171 * radixtree for quick repeated (backwards) lookups. If we have seen
5172 * this index previously, we will have an entry for it.
5174 * Initial lookup is O(N), but this is amortized to O(1) for
5175 * sequential page access (where each new request is consecutive
5176 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5177 * i.e. O(1) with a large constant!
5179 if (n < READ_ONCE(iter->sg_idx))
5182 mutex_lock(&iter->lock);
5184 /* We prefer to reuse the last sg so that repeated lookup of this
5185 * (or the subsequent) sg are fast - comparing against the last
5186 * sg is faster than going through the radixtree.
5191 count = __sg_page_count(sg);
5193 while (idx + count <= n) {
5194 unsigned long exception, i;
5197 /* If we cannot allocate and insert this entry, or the
5198 * individual pages from this range, cancel updating the
5199 * sg_idx so that on this lookup we are forced to linearly
5200 * scan onwards, but on future lookups we will try the
5201 * insertion again (in which case we need to be careful of
5202 * the error return reporting that we have already inserted
5205 ret = radix_tree_insert(&iter->radix, idx, sg);
5206 if (ret && ret != -EEXIST)
5210 RADIX_TREE_EXCEPTIONAL_ENTRY |
5211 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5212 for (i = 1; i < count; i++) {
5213 ret = radix_tree_insert(&iter->radix, idx + i,
5215 if (ret && ret != -EEXIST)
5220 sg = ____sg_next(sg);
5221 count = __sg_page_count(sg);
5228 mutex_unlock(&iter->lock);
5230 if (unlikely(n < idx)) /* insertion completed by another thread */
5233 /* In case we failed to insert the entry into the radixtree, we need
5234 * to look beyond the current sg.
5236 while (idx + count <= n) {
5238 sg = ____sg_next(sg);
5239 count = __sg_page_count(sg);
5248 sg = radix_tree_lookup(&iter->radix, n);
5251 /* If this index is in the middle of multi-page sg entry,
5252 * the radixtree will contain an exceptional entry that points
5253 * to the start of that range. We will return the pointer to
5254 * the base page and the offset of this page within the
5258 if (unlikely(radix_tree_exception(sg))) {
5259 unsigned long base =
5260 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5262 sg = radix_tree_lookup(&iter->radix, base);
5274 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5276 struct scatterlist *sg;
5277 unsigned int offset;
5279 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5281 sg = i915_gem_object_get_sg(obj, n, &offset);
5282 return nth_page(sg_page(sg), offset);
5285 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5287 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5292 page = i915_gem_object_get_page(obj, n);
5294 set_page_dirty(page);
5300 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5303 struct scatterlist *sg;
5304 unsigned int offset;
5306 sg = i915_gem_object_get_sg(obj, n, &offset);
5307 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5310 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
5312 struct sg_table *pages;
5315 if (align > obj->base.size)
5318 if (obj->ops == &i915_gem_phys_ops)
5321 if (obj->ops != &i915_gem_object_ops)
5324 err = i915_gem_object_unbind(obj);
5328 mutex_lock(&obj->mm.lock);
5330 if (obj->mm.madv != I915_MADV_WILLNEED) {
5335 if (obj->mm.quirked) {
5340 if (obj->mm.mapping) {
5345 pages = obj->mm.pages;
5346 obj->ops = &i915_gem_phys_ops;
5348 err = ____i915_gem_object_get_pages(obj);
5352 /* Perma-pin (until release) the physical set of pages */
5353 __i915_gem_object_pin_pages(obj);
5355 if (!IS_ERR_OR_NULL(pages))
5356 i915_gem_object_ops.put_pages(obj, pages);
5357 mutex_unlock(&obj->mm.lock);
5361 obj->ops = &i915_gem_object_ops;
5362 obj->mm.pages = pages;
5364 mutex_unlock(&obj->mm.lock);
5368 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5369 #include "selftests/scatterlist.c"
5370 #include "selftests/mock_gem_device.c"
5371 #include "selftests/huge_gem_object.c"
5372 #include "selftests/i915_gem_object.c"
5373 #include "selftests/i915_gem_coherency.c"