2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
55 if (!obj->cache_coherent)
58 return obj->pin_display;
62 insert_mappable_node(struct i915_ggtt *ggtt,
63 struct drm_mm_node *node, u32 size)
65 memset(node, 0, sizeof(*node));
66 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
67 size, 0, I915_COLOR_UNEVICTABLE,
68 0, ggtt->mappable_end,
73 remove_mappable_node(struct drm_mm_node *node)
75 drm_mm_remove_node(node);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
82 spin_lock(&dev_priv->mm.object_stat_lock);
83 dev_priv->mm.object_count++;
84 dev_priv->mm.object_memory += size;
85 spin_unlock(&dev_priv->mm.object_stat_lock);
88 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
91 spin_lock(&dev_priv->mm.object_stat_lock);
92 dev_priv->mm.object_count--;
93 dev_priv->mm.object_memory -= size;
94 spin_unlock(&dev_priv->mm.object_stat_lock);
98 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret = wait_event_interruptible_timeout(error->reset_queue,
110 !i915_reset_backoff(error),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret < 0) {
122 int i915_mutex_lock_interruptible(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = to_i915(dev);
127 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
131 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
142 struct drm_i915_private *dev_priv = to_i915(dev);
143 struct i915_ggtt *ggtt = &dev_priv->ggtt;
144 struct drm_i915_gem_get_aperture *args = data;
145 struct i915_vma *vma;
148 pinned = ggtt->base.reserved;
149 mutex_lock(&dev->struct_mutex);
150 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
151 if (i915_vma_is_pinned(vma))
152 pinned += vma->node.size;
153 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
154 if (i915_vma_is_pinned(vma))
155 pinned += vma->node.size;
156 mutex_unlock(&dev->struct_mutex);
158 args->aper_size = ggtt->base.total;
159 args->aper_available_size = args->aper_size - pinned;
164 static struct sg_table *
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
167 struct address_space *mapping = obj->base.filp->f_mapping;
168 drm_dma_handle_t *phys;
170 struct scatterlist *sg;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
175 return ERR_PTR(-EINVAL);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys = drm_pci_alloc(obj->base.dev,
183 roundup_pow_of_two(obj->base.size));
185 return ERR_PTR(-ENOMEM);
188 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
192 page = shmem_read_mapping_page(mapping, i);
198 src = kmap_atomic(page);
199 memcpy(vaddr, src, PAGE_SIZE);
200 drm_clflush_virt_range(vaddr, PAGE_SIZE);
207 i915_gem_chipset_flush(to_i915(obj->base.dev));
209 st = kmalloc(sizeof(*st), GFP_KERNEL);
211 st = ERR_PTR(-ENOMEM);
215 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
217 st = ERR_PTR(-ENOMEM);
223 sg->length = obj->base.size;
225 sg_dma_address(sg) = phys->busaddr;
226 sg_dma_len(sg) = obj->base.size;
228 obj->phys_handle = phys;
232 drm_pci_free(obj->base.dev, phys);
236 static void __start_cpu_write(struct drm_i915_gem_object *obj)
238 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
239 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
240 if (cpu_write_needs_clflush(obj))
241 obj->cache_dirty = true;
245 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
246 struct sg_table *pages,
249 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251 if (obj->mm.madv == I915_MADV_DONTNEED)
252 obj->mm.dirty = false;
255 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
256 !obj->cache_coherent)
257 drm_clflush_sg(pages);
259 __start_cpu_write(obj);
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
264 struct sg_table *pages)
266 __i915_gem_object_release_shmem(obj, pages, false);
269 struct address_space *mapping = obj->base.filp->f_mapping;
270 char *vaddr = obj->phys_handle->vaddr;
273 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
277 page = shmem_read_mapping_page(mapping, i);
281 dst = kmap_atomic(page);
282 drm_clflush_virt_range(vaddr, PAGE_SIZE);
283 memcpy(dst, vaddr, PAGE_SIZE);
286 set_page_dirty(page);
287 if (obj->mm.madv == I915_MADV_WILLNEED)
288 mark_page_accessed(page);
292 obj->mm.dirty = false;
295 sg_free_table(pages);
298 drm_pci_free(obj->base.dev, obj->phys_handle);
302 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
304 i915_gem_object_unpin_pages(obj);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
308 .get_pages = i915_gem_object_get_pages_phys,
309 .put_pages = i915_gem_object_put_pages_phys,
310 .release = i915_gem_object_release_phys,
313 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
315 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
317 struct i915_vma *vma;
318 LIST_HEAD(still_in_list);
321 lockdep_assert_held(&obj->base.dev->struct_mutex);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret = i915_gem_object_wait(obj,
329 I915_WAIT_INTERRUPTIBLE |
332 MAX_SCHEDULE_TIMEOUT,
337 i915_gem_retire_requests(to_i915(obj->base.dev));
339 while ((vma = list_first_entry_or_null(&obj->vma_list,
342 list_move_tail(&vma->obj_link, &still_in_list);
343 ret = i915_vma_unbind(vma);
347 list_splice(&still_in_list, &obj->vma_list);
353 i915_gem_object_wait_fence(struct dma_fence *fence,
356 struct intel_rps_client *rps)
358 struct drm_i915_gem_request *rq;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
365 if (!dma_fence_is_i915(fence))
366 return dma_fence_wait_timeout(fence,
367 flags & I915_WAIT_INTERRUPTIBLE,
370 rq = to_request(fence);
371 if (i915_gem_request_completed(rq))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq->i915) >= 6)
391 gen6_rps_boost(rq, rps);
396 timeout = i915_wait_request(rq, flags, timeout);
399 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
400 i915_gem_request_retire_upto(rq);
406 i915_gem_object_wait_reservation(struct reservation_object *resv,
409 struct intel_rps_client *rps)
411 unsigned int seq = __read_seqcount_begin(&resv->seq);
412 struct dma_fence *excl;
413 bool prune_fences = false;
415 if (flags & I915_WAIT_ALL) {
416 struct dma_fence **shared;
417 unsigned int count, i;
420 ret = reservation_object_get_fences_rcu(resv,
421 &excl, &count, &shared);
425 for (i = 0; i < count; i++) {
426 timeout = i915_gem_object_wait_fence(shared[i],
432 dma_fence_put(shared[i]);
435 for (; i < count; i++)
436 dma_fence_put(shared[i]);
439 prune_fences = count && timeout >= 0;
441 excl = reservation_object_get_excl_rcu(resv);
444 if (excl && timeout >= 0) {
445 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
446 prune_fences = timeout >= 0;
451 /* Oportunistically prune the fences iff we know they have *all* been
452 * signaled and that the reservation object has not been changed (i.e.
453 * no new fences have been added).
455 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
456 if (reservation_object_trylock(resv)) {
457 if (!__read_seqcount_retry(&resv->seq, seq))
458 reservation_object_add_excl_fence(resv, NULL);
459 reservation_object_unlock(resv);
466 static void __fence_set_priority(struct dma_fence *fence, int prio)
468 struct drm_i915_gem_request *rq;
469 struct intel_engine_cs *engine;
471 if (!dma_fence_is_i915(fence))
474 rq = to_request(fence);
476 if (!engine->schedule)
479 engine->schedule(rq, prio);
482 static void fence_set_priority(struct dma_fence *fence, int prio)
484 /* Recurse once into a fence-array */
485 if (dma_fence_is_array(fence)) {
486 struct dma_fence_array *array = to_dma_fence_array(fence);
489 for (i = 0; i < array->num_fences; i++)
490 __fence_set_priority(array->fences[i], prio);
492 __fence_set_priority(fence, prio);
497 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
501 struct dma_fence *excl;
503 if (flags & I915_WAIT_ALL) {
504 struct dma_fence **shared;
505 unsigned int count, i;
508 ret = reservation_object_get_fences_rcu(obj->resv,
509 &excl, &count, &shared);
513 for (i = 0; i < count; i++) {
514 fence_set_priority(shared[i], prio);
515 dma_fence_put(shared[i]);
520 excl = reservation_object_get_excl_rcu(obj->resv);
524 fence_set_priority(excl, prio);
531 * Waits for rendering to the object to be completed
532 * @obj: i915 gem object
533 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
534 * @timeout: how long to wait
535 * @rps: client (user process) to charge for any waitboosting
538 i915_gem_object_wait(struct drm_i915_gem_object *obj,
541 struct intel_rps_client *rps)
544 #if IS_ENABLED(CONFIG_LOCKDEP)
545 GEM_BUG_ON(debug_locks &&
546 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
547 !!(flags & I915_WAIT_LOCKED));
549 GEM_BUG_ON(timeout < 0);
551 timeout = i915_gem_object_wait_reservation(obj->resv,
554 return timeout < 0 ? timeout : 0;
557 static struct intel_rps_client *to_rps_client(struct drm_file *file)
559 struct drm_i915_file_private *fpriv = file->driver_priv;
565 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
570 if (align > obj->base.size)
573 if (obj->ops == &i915_gem_phys_ops)
576 if (obj->mm.madv != I915_MADV_WILLNEED)
579 if (obj->base.filp == NULL)
582 ret = i915_gem_object_unbind(obj);
586 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
590 GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
591 obj->ops = &i915_gem_phys_ops;
593 ret = i915_gem_object_pin_pages(obj);
600 obj->ops = &i915_gem_object_ops;
605 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
606 struct drm_i915_gem_pwrite *args,
607 struct drm_file *file)
609 void *vaddr = obj->phys_handle->vaddr + args->offset;
610 char __user *user_data = u64_to_user_ptr(args->data_ptr);
612 /* We manually control the domain here and pretend that it
613 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
615 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
616 if (copy_from_user(vaddr, user_data, args->size))
619 drm_clflush_virt_range(vaddr, args->size);
620 i915_gem_chipset_flush(to_i915(obj->base.dev));
622 intel_fb_obj_flush(obj, ORIGIN_CPU);
626 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
628 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
631 void i915_gem_object_free(struct drm_i915_gem_object *obj)
633 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
634 kmem_cache_free(dev_priv->objects, obj);
638 i915_gem_create(struct drm_file *file,
639 struct drm_i915_private *dev_priv,
643 struct drm_i915_gem_object *obj;
647 size = roundup(size, PAGE_SIZE);
651 /* Allocate the new object */
652 obj = i915_gem_object_create(dev_priv, size);
656 ret = drm_gem_handle_create(file, &obj->base, &handle);
657 /* drop reference from allocate - handle holds it now */
658 i915_gem_object_put(obj);
667 i915_gem_dumb_create(struct drm_file *file,
668 struct drm_device *dev,
669 struct drm_mode_create_dumb *args)
671 /* have to work out size/pitch and return them */
672 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
673 args->size = args->pitch * args->height;
674 return i915_gem_create(file, to_i915(dev),
675 args->size, &args->handle);
678 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
680 return !(obj->cache_level == I915_CACHE_NONE ||
681 obj->cache_level == I915_CACHE_WT);
685 * Creates a new mm object and returns a handle to it.
686 * @dev: drm device pointer
687 * @data: ioctl data blob
688 * @file: drm file pointer
691 i915_gem_create_ioctl(struct drm_device *dev, void *data,
692 struct drm_file *file)
694 struct drm_i915_private *dev_priv = to_i915(dev);
695 struct drm_i915_gem_create *args = data;
697 i915_gem_flush_free_objects(dev_priv);
699 return i915_gem_create(file, dev_priv,
700 args->size, &args->handle);
703 static inline enum fb_op_origin
704 fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
706 return (domain == I915_GEM_DOMAIN_GTT ?
707 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
711 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
713 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
715 if (!(obj->base.write_domain & flush_domains))
718 /* No actual flushing is required for the GTT write domain. Writes
719 * to it "immediately" go to main memory as far as we know, so there's
720 * no chipset flush. It also doesn't land in render cache.
722 * However, we do have to enforce the order so that all writes through
723 * the GTT land before any writes to the device, such as updates to
726 * We also have to wait a bit for the writes to land from the GTT.
727 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
728 * timing. This issue has only been observed when switching quickly
729 * between GTT writes and CPU reads from inside the kernel on recent hw,
730 * and it appears to only affect discrete GTT blocks (i.e. on LLC
731 * system agents we cannot reproduce this behaviour).
735 switch (obj->base.write_domain) {
736 case I915_GEM_DOMAIN_GTT:
737 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
738 if (intel_runtime_pm_get_if_in_use(dev_priv)) {
739 spin_lock_irq(&dev_priv->uncore.lock);
740 POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
741 spin_unlock_irq(&dev_priv->uncore.lock);
742 intel_runtime_pm_put(dev_priv);
746 intel_fb_obj_flush(obj,
747 fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
750 case I915_GEM_DOMAIN_CPU:
751 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
754 case I915_GEM_DOMAIN_RENDER:
755 if (gpu_write_needs_clflush(obj))
756 obj->cache_dirty = true;
760 obj->base.write_domain = 0;
764 __copy_to_user_swizzled(char __user *cpu_vaddr,
765 const char *gpu_vaddr, int gpu_offset,
768 int ret, cpu_offset = 0;
771 int cacheline_end = ALIGN(gpu_offset + 1, 64);
772 int this_length = min(cacheline_end - gpu_offset, length);
773 int swizzled_gpu_offset = gpu_offset ^ 64;
775 ret = __copy_to_user(cpu_vaddr + cpu_offset,
776 gpu_vaddr + swizzled_gpu_offset,
781 cpu_offset += this_length;
782 gpu_offset += this_length;
783 length -= this_length;
790 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
791 const char __user *cpu_vaddr,
794 int ret, cpu_offset = 0;
797 int cacheline_end = ALIGN(gpu_offset + 1, 64);
798 int this_length = min(cacheline_end - gpu_offset, length);
799 int swizzled_gpu_offset = gpu_offset ^ 64;
801 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
802 cpu_vaddr + cpu_offset,
807 cpu_offset += this_length;
808 gpu_offset += this_length;
809 length -= this_length;
816 * Pins the specified object's pages and synchronizes the object with
817 * GPU accesses. Sets needs_clflush to non-zero if the caller should
818 * flush the object from the CPU cache.
820 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
821 unsigned int *needs_clflush)
825 lockdep_assert_held(&obj->base.dev->struct_mutex);
828 if (!i915_gem_object_has_struct_page(obj))
831 ret = i915_gem_object_wait(obj,
832 I915_WAIT_INTERRUPTIBLE |
834 MAX_SCHEDULE_TIMEOUT,
839 ret = i915_gem_object_pin_pages(obj);
843 if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
844 ret = i915_gem_object_set_to_cpu_domain(obj, false);
851 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
853 /* If we're not in the cpu read domain, set ourself into the gtt
854 * read domain and manually flush cachelines (if required). This
855 * optimizes for the case when the gpu will dirty the data
856 * anyway again before the next pread happens.
858 if (!obj->cache_dirty &&
859 !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
860 *needs_clflush = CLFLUSH_BEFORE;
863 /* return with the pages pinned */
867 i915_gem_object_unpin_pages(obj);
871 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
872 unsigned int *needs_clflush)
876 lockdep_assert_held(&obj->base.dev->struct_mutex);
879 if (!i915_gem_object_has_struct_page(obj))
882 ret = i915_gem_object_wait(obj,
883 I915_WAIT_INTERRUPTIBLE |
886 MAX_SCHEDULE_TIMEOUT,
891 ret = i915_gem_object_pin_pages(obj);
895 if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
896 ret = i915_gem_object_set_to_cpu_domain(obj, true);
903 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
905 /* If we're not in the cpu write domain, set ourself into the
906 * gtt write domain and manually flush cachelines (as required).
907 * This optimizes for the case when the gpu will use the data
908 * right away and we therefore have to clflush anyway.
910 if (!obj->cache_dirty) {
911 *needs_clflush |= CLFLUSH_AFTER;
914 * Same trick applies to invalidate partially written
915 * cachelines read before writing.
917 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
918 *needs_clflush |= CLFLUSH_BEFORE;
922 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
923 obj->mm.dirty = true;
924 /* return with the pages pinned */
928 i915_gem_object_unpin_pages(obj);
933 shmem_clflush_swizzled_range(char *addr, unsigned long length,
936 if (unlikely(swizzled)) {
937 unsigned long start = (unsigned long) addr;
938 unsigned long end = (unsigned long) addr + length;
940 /* For swizzling simply ensure that we always flush both
941 * channels. Lame, but simple and it works. Swizzled
942 * pwrite/pread is far from a hotpath - current userspace
943 * doesn't use it at all. */
944 start = round_down(start, 128);
945 end = round_up(end, 128);
947 drm_clflush_virt_range((void *)start, end - start);
949 drm_clflush_virt_range(addr, length);
954 /* Only difference to the fast-path function is that this can handle bit17
955 * and uses non-atomic copy and kmap functions. */
957 shmem_pread_slow(struct page *page, int offset, int length,
958 char __user *user_data,
959 bool page_do_bit17_swizzling, bool needs_clflush)
966 shmem_clflush_swizzled_range(vaddr + offset, length,
967 page_do_bit17_swizzling);
969 if (page_do_bit17_swizzling)
970 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
972 ret = __copy_to_user(user_data, vaddr + offset, length);
975 return ret ? - EFAULT : 0;
979 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
980 bool page_do_bit17_swizzling, bool needs_clflush)
985 if (!page_do_bit17_swizzling) {
986 char *vaddr = kmap_atomic(page);
989 drm_clflush_virt_range(vaddr + offset, length);
990 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
991 kunmap_atomic(vaddr);
996 return shmem_pread_slow(page, offset, length, user_data,
997 page_do_bit17_swizzling, needs_clflush);
1001 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
1002 struct drm_i915_gem_pread *args)
1004 char __user *user_data;
1006 unsigned int obj_do_bit17_swizzling;
1007 unsigned int needs_clflush;
1008 unsigned int idx, offset;
1011 obj_do_bit17_swizzling = 0;
1012 if (i915_gem_object_needs_bit17_swizzle(obj))
1013 obj_do_bit17_swizzling = BIT(17);
1015 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
1019 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
1020 mutex_unlock(&obj->base.dev->struct_mutex);
1024 remain = args->size;
1025 user_data = u64_to_user_ptr(args->data_ptr);
1026 offset = offset_in_page(args->offset);
1027 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1028 struct page *page = i915_gem_object_get_page(obj, idx);
1032 if (offset + length > PAGE_SIZE)
1033 length = PAGE_SIZE - offset;
1035 ret = shmem_pread(page, offset, length, user_data,
1036 page_to_phys(page) & obj_do_bit17_swizzling,
1042 user_data += length;
1046 i915_gem_obj_finish_shmem_access(obj);
1051 gtt_user_read(struct io_mapping *mapping,
1052 loff_t base, int offset,
1053 char __user *user_data, int length)
1056 unsigned long unwritten;
1058 /* We can use the cpu mem copy function because this is X86. */
1059 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1060 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1061 io_mapping_unmap_atomic(vaddr);
1063 vaddr = (void __force *)
1064 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1065 unwritten = copy_to_user(user_data, vaddr + offset, length);
1066 io_mapping_unmap(vaddr);
1072 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1073 const struct drm_i915_gem_pread *args)
1075 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1076 struct i915_ggtt *ggtt = &i915->ggtt;
1077 struct drm_mm_node node;
1078 struct i915_vma *vma;
1079 void __user *user_data;
1083 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1087 intel_runtime_pm_get(i915);
1088 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1089 PIN_MAPPABLE | PIN_NONBLOCK);
1091 node.start = i915_ggtt_offset(vma);
1092 node.allocated = false;
1093 ret = i915_vma_put_fence(vma);
1095 i915_vma_unpin(vma);
1100 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1103 GEM_BUG_ON(!node.allocated);
1106 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1110 mutex_unlock(&i915->drm.struct_mutex);
1112 user_data = u64_to_user_ptr(args->data_ptr);
1113 remain = args->size;
1114 offset = args->offset;
1116 while (remain > 0) {
1117 /* Operation in this page
1119 * page_base = page offset within aperture
1120 * page_offset = offset within page
1121 * page_length = bytes to copy for this page
1123 u32 page_base = node.start;
1124 unsigned page_offset = offset_in_page(offset);
1125 unsigned page_length = PAGE_SIZE - page_offset;
1126 page_length = remain < page_length ? remain : page_length;
1127 if (node.allocated) {
1129 ggtt->base.insert_page(&ggtt->base,
1130 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1131 node.start, I915_CACHE_NONE, 0);
1134 page_base += offset & PAGE_MASK;
1137 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1138 user_data, page_length)) {
1143 remain -= page_length;
1144 user_data += page_length;
1145 offset += page_length;
1148 mutex_lock(&i915->drm.struct_mutex);
1150 if (node.allocated) {
1152 ggtt->base.clear_range(&ggtt->base,
1153 node.start, node.size);
1154 remove_mappable_node(&node);
1156 i915_vma_unpin(vma);
1159 intel_runtime_pm_put(i915);
1160 mutex_unlock(&i915->drm.struct_mutex);
1166 * Reads data from the object referenced by handle.
1167 * @dev: drm device pointer
1168 * @data: ioctl data blob
1169 * @file: drm file pointer
1171 * On error, the contents of *data are undefined.
1174 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1175 struct drm_file *file)
1177 struct drm_i915_gem_pread *args = data;
1178 struct drm_i915_gem_object *obj;
1181 if (args->size == 0)
1184 if (!access_ok(VERIFY_WRITE,
1185 u64_to_user_ptr(args->data_ptr),
1189 obj = i915_gem_object_lookup(file, args->handle);
1193 /* Bounds check source. */
1194 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1199 trace_i915_gem_object_pread(obj, args->offset, args->size);
1201 ret = i915_gem_object_wait(obj,
1202 I915_WAIT_INTERRUPTIBLE,
1203 MAX_SCHEDULE_TIMEOUT,
1204 to_rps_client(file));
1208 ret = i915_gem_object_pin_pages(obj);
1212 ret = i915_gem_shmem_pread(obj, args);
1213 if (ret == -EFAULT || ret == -ENODEV)
1214 ret = i915_gem_gtt_pread(obj, args);
1216 i915_gem_object_unpin_pages(obj);
1218 i915_gem_object_put(obj);
1222 /* This is the fast write path which cannot handle
1223 * page faults in the source data
1227 ggtt_write(struct io_mapping *mapping,
1228 loff_t base, int offset,
1229 char __user *user_data, int length)
1232 unsigned long unwritten;
1234 /* We can use the cpu mem copy function because this is X86. */
1235 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1236 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1238 io_mapping_unmap_atomic(vaddr);
1240 vaddr = (void __force *)
1241 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1242 unwritten = copy_from_user(vaddr + offset, user_data, length);
1243 io_mapping_unmap(vaddr);
1250 * This is the fast pwrite path, where we copy the data directly from the
1251 * user into the GTT, uncached.
1252 * @obj: i915 GEM object
1253 * @args: pwrite arguments structure
1256 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1257 const struct drm_i915_gem_pwrite *args)
1259 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1260 struct i915_ggtt *ggtt = &i915->ggtt;
1261 struct drm_mm_node node;
1262 struct i915_vma *vma;
1264 void __user *user_data;
1267 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1271 intel_runtime_pm_get(i915);
1272 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1273 PIN_MAPPABLE | PIN_NONBLOCK);
1275 node.start = i915_ggtt_offset(vma);
1276 node.allocated = false;
1277 ret = i915_vma_put_fence(vma);
1279 i915_vma_unpin(vma);
1284 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1287 GEM_BUG_ON(!node.allocated);
1290 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1294 mutex_unlock(&i915->drm.struct_mutex);
1296 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1298 user_data = u64_to_user_ptr(args->data_ptr);
1299 offset = args->offset;
1300 remain = args->size;
1302 /* Operation in this page
1304 * page_base = page offset within aperture
1305 * page_offset = offset within page
1306 * page_length = bytes to copy for this page
1308 u32 page_base = node.start;
1309 unsigned int page_offset = offset_in_page(offset);
1310 unsigned int page_length = PAGE_SIZE - page_offset;
1311 page_length = remain < page_length ? remain : page_length;
1312 if (node.allocated) {
1313 wmb(); /* flush the write before we modify the GGTT */
1314 ggtt->base.insert_page(&ggtt->base,
1315 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1316 node.start, I915_CACHE_NONE, 0);
1317 wmb(); /* flush modifications to the GGTT (insert_page) */
1319 page_base += offset & PAGE_MASK;
1321 /* If we get a fault while copying data, then (presumably) our
1322 * source page isn't available. Return the error and we'll
1323 * retry in the slow path.
1324 * If the object is non-shmem backed, we retry again with the
1325 * path that handles page fault.
1327 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1328 user_data, page_length)) {
1333 remain -= page_length;
1334 user_data += page_length;
1335 offset += page_length;
1337 intel_fb_obj_flush(obj, ORIGIN_CPU);
1339 mutex_lock(&i915->drm.struct_mutex);
1341 if (node.allocated) {
1343 ggtt->base.clear_range(&ggtt->base,
1344 node.start, node.size);
1345 remove_mappable_node(&node);
1347 i915_vma_unpin(vma);
1350 intel_runtime_pm_put(i915);
1351 mutex_unlock(&i915->drm.struct_mutex);
1356 shmem_pwrite_slow(struct page *page, int offset, int length,
1357 char __user *user_data,
1358 bool page_do_bit17_swizzling,
1359 bool needs_clflush_before,
1360 bool needs_clflush_after)
1366 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1367 shmem_clflush_swizzled_range(vaddr + offset, length,
1368 page_do_bit17_swizzling);
1369 if (page_do_bit17_swizzling)
1370 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1373 ret = __copy_from_user(vaddr + offset, user_data, length);
1374 if (needs_clflush_after)
1375 shmem_clflush_swizzled_range(vaddr + offset, length,
1376 page_do_bit17_swizzling);
1379 return ret ? -EFAULT : 0;
1382 /* Per-page copy function for the shmem pwrite fastpath.
1383 * Flushes invalid cachelines before writing to the target if
1384 * needs_clflush_before is set and flushes out any written cachelines after
1385 * writing if needs_clflush is set.
1388 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1389 bool page_do_bit17_swizzling,
1390 bool needs_clflush_before,
1391 bool needs_clflush_after)
1396 if (!page_do_bit17_swizzling) {
1397 char *vaddr = kmap_atomic(page);
1399 if (needs_clflush_before)
1400 drm_clflush_virt_range(vaddr + offset, len);
1401 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1402 if (needs_clflush_after)
1403 drm_clflush_virt_range(vaddr + offset, len);
1405 kunmap_atomic(vaddr);
1410 return shmem_pwrite_slow(page, offset, len, user_data,
1411 page_do_bit17_swizzling,
1412 needs_clflush_before,
1413 needs_clflush_after);
1417 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1418 const struct drm_i915_gem_pwrite *args)
1420 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1421 void __user *user_data;
1423 unsigned int obj_do_bit17_swizzling;
1424 unsigned int partial_cacheline_write;
1425 unsigned int needs_clflush;
1426 unsigned int offset, idx;
1429 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1433 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1434 mutex_unlock(&i915->drm.struct_mutex);
1438 obj_do_bit17_swizzling = 0;
1439 if (i915_gem_object_needs_bit17_swizzle(obj))
1440 obj_do_bit17_swizzling = BIT(17);
1442 /* If we don't overwrite a cacheline completely we need to be
1443 * careful to have up-to-date data by first clflushing. Don't
1444 * overcomplicate things and flush the entire patch.
1446 partial_cacheline_write = 0;
1447 if (needs_clflush & CLFLUSH_BEFORE)
1448 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1450 user_data = u64_to_user_ptr(args->data_ptr);
1451 remain = args->size;
1452 offset = offset_in_page(args->offset);
1453 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1454 struct page *page = i915_gem_object_get_page(obj, idx);
1458 if (offset + length > PAGE_SIZE)
1459 length = PAGE_SIZE - offset;
1461 ret = shmem_pwrite(page, offset, length, user_data,
1462 page_to_phys(page) & obj_do_bit17_swizzling,
1463 (offset | length) & partial_cacheline_write,
1464 needs_clflush & CLFLUSH_AFTER);
1469 user_data += length;
1473 intel_fb_obj_flush(obj, ORIGIN_CPU);
1474 i915_gem_obj_finish_shmem_access(obj);
1479 * Writes data to the object referenced by handle.
1481 * @data: ioctl data blob
1484 * On error, the contents of the buffer that were to be modified are undefined.
1487 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1488 struct drm_file *file)
1490 struct drm_i915_gem_pwrite *args = data;
1491 struct drm_i915_gem_object *obj;
1494 if (args->size == 0)
1497 if (!access_ok(VERIFY_READ,
1498 u64_to_user_ptr(args->data_ptr),
1502 obj = i915_gem_object_lookup(file, args->handle);
1506 /* Bounds check destination. */
1507 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1512 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1515 if (obj->ops->pwrite)
1516 ret = obj->ops->pwrite(obj, args);
1520 ret = i915_gem_object_wait(obj,
1521 I915_WAIT_INTERRUPTIBLE |
1523 MAX_SCHEDULE_TIMEOUT,
1524 to_rps_client(file));
1528 ret = i915_gem_object_pin_pages(obj);
1533 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1534 * it would end up going through the fenced access, and we'll get
1535 * different detiling behavior between reading and writing.
1536 * pread/pwrite currently are reading and writing from the CPU
1537 * perspective, requiring manual detiling by the client.
1539 if (!i915_gem_object_has_struct_page(obj) ||
1540 cpu_write_needs_clflush(obj))
1541 /* Note that the gtt paths might fail with non-page-backed user
1542 * pointers (e.g. gtt mappings when moving data between
1543 * textures). Fallback to the shmem path in that case.
1545 ret = i915_gem_gtt_pwrite_fast(obj, args);
1547 if (ret == -EFAULT || ret == -ENOSPC) {
1548 if (obj->phys_handle)
1549 ret = i915_gem_phys_pwrite(obj, args, file);
1551 ret = i915_gem_shmem_pwrite(obj, args);
1554 i915_gem_object_unpin_pages(obj);
1556 i915_gem_object_put(obj);
1560 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1562 struct drm_i915_private *i915;
1563 struct list_head *list;
1564 struct i915_vma *vma;
1566 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1567 if (!i915_vma_is_ggtt(vma))
1570 if (i915_vma_is_active(vma))
1573 if (!drm_mm_node_allocated(&vma->node))
1576 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1579 i915 = to_i915(obj->base.dev);
1580 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1581 list_move_tail(&obj->global_link, list);
1585 * Called when user space prepares to use an object with the CPU, either
1586 * through the mmap ioctl's mapping or a GTT mapping.
1588 * @data: ioctl data blob
1592 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1593 struct drm_file *file)
1595 struct drm_i915_gem_set_domain *args = data;
1596 struct drm_i915_gem_object *obj;
1597 uint32_t read_domains = args->read_domains;
1598 uint32_t write_domain = args->write_domain;
1601 /* Only handle setting domains to types used by the CPU. */
1602 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1605 /* Having something in the write domain implies it's in the read
1606 * domain, and only that read domain. Enforce that in the request.
1608 if (write_domain != 0 && read_domains != write_domain)
1611 obj = i915_gem_object_lookup(file, args->handle);
1615 /* Try to flush the object off the GPU without holding the lock.
1616 * We will repeat the flush holding the lock in the normal manner
1617 * to catch cases where we are gazumped.
1619 err = i915_gem_object_wait(obj,
1620 I915_WAIT_INTERRUPTIBLE |
1621 (write_domain ? I915_WAIT_ALL : 0),
1622 MAX_SCHEDULE_TIMEOUT,
1623 to_rps_client(file));
1627 /* Flush and acquire obj->pages so that we are coherent through
1628 * direct access in memory with previous cached writes through
1629 * shmemfs and that our cache domain tracking remains valid.
1630 * For example, if the obj->filp was moved to swap without us
1631 * being notified and releasing the pages, we would mistakenly
1632 * continue to assume that the obj remained out of the CPU cached
1635 err = i915_gem_object_pin_pages(obj);
1639 err = i915_mutex_lock_interruptible(dev);
1643 if (read_domains & I915_GEM_DOMAIN_WC)
1644 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
1645 else if (read_domains & I915_GEM_DOMAIN_GTT)
1646 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
1648 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
1650 /* And bump the LRU for this access */
1651 i915_gem_object_bump_inactive_ggtt(obj);
1653 mutex_unlock(&dev->struct_mutex);
1655 if (write_domain != 0)
1656 intel_fb_obj_invalidate(obj,
1657 fb_write_origin(obj, write_domain));
1660 i915_gem_object_unpin_pages(obj);
1662 i915_gem_object_put(obj);
1667 * Called when user space has done writes to this buffer
1669 * @data: ioctl data blob
1673 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file)
1676 struct drm_i915_gem_sw_finish *args = data;
1677 struct drm_i915_gem_object *obj;
1679 obj = i915_gem_object_lookup(file, args->handle);
1683 /* Pinned buffers may be scanout, so flush the cache */
1684 i915_gem_object_flush_if_display(obj);
1685 i915_gem_object_put(obj);
1691 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1694 * @data: ioctl data blob
1697 * While the mapping holds a reference on the contents of the object, it doesn't
1698 * imply a ref on the object itself.
1702 * DRM driver writers who look a this function as an example for how to do GEM
1703 * mmap support, please don't implement mmap support like here. The modern way
1704 * to implement DRM mmap support is with an mmap offset ioctl (like
1705 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1706 * That way debug tooling like valgrind will understand what's going on, hiding
1707 * the mmap call in a driver private ioctl will break that. The i915 driver only
1708 * does cpu mmaps this way because we didn't know better.
1711 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1712 struct drm_file *file)
1714 struct drm_i915_gem_mmap *args = data;
1715 struct drm_i915_gem_object *obj;
1718 if (args->flags & ~(I915_MMAP_WC))
1721 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1724 obj = i915_gem_object_lookup(file, args->handle);
1728 /* prime objects have no backing filp to GEM mmap
1731 if (!obj->base.filp) {
1732 i915_gem_object_put(obj);
1736 addr = vm_mmap(obj->base.filp, 0, args->size,
1737 PROT_READ | PROT_WRITE, MAP_SHARED,
1739 if (args->flags & I915_MMAP_WC) {
1740 struct mm_struct *mm = current->mm;
1741 struct vm_area_struct *vma;
1743 if (down_write_killable(&mm->mmap_sem)) {
1744 i915_gem_object_put(obj);
1747 vma = find_vma(mm, addr);
1750 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1753 up_write(&mm->mmap_sem);
1755 /* This may race, but that's ok, it only gets set */
1756 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1758 i915_gem_object_put(obj);
1759 if (IS_ERR((void *)addr))
1762 args->addr_ptr = (uint64_t) addr;
1767 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1769 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1773 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1775 * A history of the GTT mmap interface:
1777 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1778 * aligned and suitable for fencing, and still fit into the available
1779 * mappable space left by the pinned display objects. A classic problem
1780 * we called the page-fault-of-doom where we would ping-pong between
1781 * two objects that could not fit inside the GTT and so the memcpy
1782 * would page one object in at the expense of the other between every
1785 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1786 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1787 * object is too large for the available space (or simply too large
1788 * for the mappable aperture!), a view is created instead and faulted
1789 * into userspace. (This view is aligned and sized appropriately for
1792 * 2 - Recognise WC as a separate cache domain so that we can flush the
1793 * delayed writes via GTT before performing direct access via WC.
1797 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1798 * hangs on some architectures, corruption on others. An attempt to service
1799 * a GTT page fault from a snoopable object will generate a SIGBUS.
1801 * * the object must be able to fit into RAM (physical memory, though no
1802 * limited to the mappable aperture).
1807 * * a new GTT page fault will synchronize rendering from the GPU and flush
1808 * all data to system memory. Subsequent access will not be synchronized.
1810 * * all mappings are revoked on runtime device suspend.
1812 * * there are only 8, 16 or 32 fence registers to share between all users
1813 * (older machines require fence register for display and blitter access
1814 * as well). Contention of the fence registers will cause the previous users
1815 * to be unmapped and any new access will generate new page faults.
1817 * * running out of memory while servicing a fault may generate a SIGBUS,
1818 * rather than the expected SIGSEGV.
1820 int i915_gem_mmap_gtt_version(void)
1825 static inline struct i915_ggtt_view
1826 compute_partial_view(struct drm_i915_gem_object *obj,
1827 pgoff_t page_offset,
1830 struct i915_ggtt_view view;
1832 if (i915_gem_object_is_tiled(obj))
1833 chunk = roundup(chunk, tile_row_pages(obj));
1835 view.type = I915_GGTT_VIEW_PARTIAL;
1836 view.partial.offset = rounddown(page_offset, chunk);
1838 min_t(unsigned int, chunk,
1839 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1841 /* If the partial covers the entire object, just create a normal VMA. */
1842 if (chunk >= obj->base.size >> PAGE_SHIFT)
1843 view.type = I915_GGTT_VIEW_NORMAL;
1849 * i915_gem_fault - fault a page into the GTT
1852 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1853 * from userspace. The fault handler takes care of binding the object to
1854 * the GTT (if needed), allocating and programming a fence register (again,
1855 * only if needed based on whether the old reg is still valid or the object
1856 * is tiled) and inserting a new PTE into the faulting process.
1858 * Note that the faulting process may involve evicting existing objects
1859 * from the GTT and/or fence registers to make room. So performance may
1860 * suffer if the GTT working set is large or there are few fence registers
1863 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1864 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1866 int i915_gem_fault(struct vm_fault *vmf)
1868 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1869 struct vm_area_struct *area = vmf->vma;
1870 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1871 struct drm_device *dev = obj->base.dev;
1872 struct drm_i915_private *dev_priv = to_i915(dev);
1873 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1874 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1875 struct i915_vma *vma;
1876 pgoff_t page_offset;
1880 /* We don't use vmf->pgoff since that has the fake offset */
1881 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1883 trace_i915_gem_object_fault(obj, page_offset, true, write);
1885 /* Try to flush the object off the GPU first without holding the lock.
1886 * Upon acquiring the lock, we will perform our sanity checks and then
1887 * repeat the flush holding the lock in the normal manner to catch cases
1888 * where we are gazumped.
1890 ret = i915_gem_object_wait(obj,
1891 I915_WAIT_INTERRUPTIBLE,
1892 MAX_SCHEDULE_TIMEOUT,
1897 ret = i915_gem_object_pin_pages(obj);
1901 intel_runtime_pm_get(dev_priv);
1903 ret = i915_mutex_lock_interruptible(dev);
1907 /* Access to snoopable pages through the GTT is incoherent. */
1908 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1913 /* If the object is smaller than a couple of partial vma, it is
1914 * not worth only creating a single partial vma - we may as well
1915 * clear enough space for the full object.
1917 flags = PIN_MAPPABLE;
1918 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1919 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1921 /* Now pin it into the GTT as needed */
1922 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1924 /* Use a partial view if it is bigger than available space */
1925 struct i915_ggtt_view view =
1926 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1928 /* Userspace is now writing through an untracked VMA, abandon
1929 * all hope that the hardware is able to track future writes.
1931 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1933 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1940 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1944 ret = i915_vma_get_fence(vma);
1948 /* Mark as being mmapped into userspace for later revocation */
1949 assert_rpm_wakelock_held(dev_priv);
1950 if (list_empty(&obj->userfault_link))
1951 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1953 /* Finally, remap it using the new GTT offset */
1954 ret = remap_io_mapping(area,
1955 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1956 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1957 min_t(u64, vma->size, area->vm_end - area->vm_start),
1961 __i915_vma_unpin(vma);
1963 mutex_unlock(&dev->struct_mutex);
1965 intel_runtime_pm_put(dev_priv);
1966 i915_gem_object_unpin_pages(obj);
1971 * We eat errors when the gpu is terminally wedged to avoid
1972 * userspace unduly crashing (gl has no provisions for mmaps to
1973 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1974 * and so needs to be reported.
1976 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1977 ret = VM_FAULT_SIGBUS;
1982 * EAGAIN means the gpu is hung and we'll wait for the error
1983 * handler to reset everything when re-faulting in
1984 * i915_mutex_lock_interruptible.
1991 * EBUSY is ok: this just means that another thread
1992 * already did the job.
1994 ret = VM_FAULT_NOPAGE;
2001 ret = VM_FAULT_SIGBUS;
2004 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2005 ret = VM_FAULT_SIGBUS;
2012 * i915_gem_release_mmap - remove physical page mappings
2013 * @obj: obj in question
2015 * Preserve the reservation of the mmapping with the DRM core code, but
2016 * relinquish ownership of the pages back to the system.
2018 * It is vital that we remove the page mapping if we have mapped a tiled
2019 * object through the GTT and then lose the fence register due to
2020 * resource pressure. Similarly if the object has been moved out of the
2021 * aperture, than pages mapped into userspace must be revoked. Removing the
2022 * mapping will then trigger a page fault on the next user access, allowing
2023 * fixup by i915_gem_fault().
2026 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2028 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2030 /* Serialisation between user GTT access and our code depends upon
2031 * revoking the CPU's PTE whilst the mutex is held. The next user
2032 * pagefault then has to wait until we release the mutex.
2034 * Note that RPM complicates somewhat by adding an additional
2035 * requirement that operations to the GGTT be made holding the RPM
2038 lockdep_assert_held(&i915->drm.struct_mutex);
2039 intel_runtime_pm_get(i915);
2041 if (list_empty(&obj->userfault_link))
2044 list_del_init(&obj->userfault_link);
2045 drm_vma_node_unmap(&obj->base.vma_node,
2046 obj->base.dev->anon_inode->i_mapping);
2048 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2049 * memory transactions from userspace before we return. The TLB
2050 * flushing implied above by changing the PTE above *should* be
2051 * sufficient, an extra barrier here just provides us with a bit
2052 * of paranoid documentation about our requirement to serialise
2053 * memory writes before touching registers / GSM.
2058 intel_runtime_pm_put(i915);
2061 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2063 struct drm_i915_gem_object *obj, *on;
2067 * Only called during RPM suspend. All users of the userfault_list
2068 * must be holding an RPM wakeref to ensure that this can not
2069 * run concurrently with themselves (and use the struct_mutex for
2070 * protection between themselves).
2073 list_for_each_entry_safe(obj, on,
2074 &dev_priv->mm.userfault_list, userfault_link) {
2075 list_del_init(&obj->userfault_link);
2076 drm_vma_node_unmap(&obj->base.vma_node,
2077 obj->base.dev->anon_inode->i_mapping);
2080 /* The fence will be lost when the device powers down. If any were
2081 * in use by hardware (i.e. they are pinned), we should not be powering
2082 * down! All other fences will be reacquired by the user upon waking.
2084 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2085 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2087 /* Ideally we want to assert that the fence register is not
2088 * live at this point (i.e. that no piece of code will be
2089 * trying to write through fence + GTT, as that both violates
2090 * our tracking of activity and associated locking/barriers,
2091 * but also is illegal given that the hw is powered down).
2093 * Previously we used reg->pin_count as a "liveness" indicator.
2094 * That is not sufficient, and we need a more fine-grained
2095 * tool if we want to have a sanity check here.
2101 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2106 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2108 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2111 err = drm_gem_create_mmap_offset(&obj->base);
2115 /* Attempt to reap some mmap space from dead objects */
2117 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2121 i915_gem_drain_freed_objects(dev_priv);
2122 err = drm_gem_create_mmap_offset(&obj->base);
2126 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2131 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2133 drm_gem_free_mmap_offset(&obj->base);
2137 i915_gem_mmap_gtt(struct drm_file *file,
2138 struct drm_device *dev,
2142 struct drm_i915_gem_object *obj;
2145 obj = i915_gem_object_lookup(file, handle);
2149 ret = i915_gem_object_create_mmap_offset(obj);
2151 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2153 i915_gem_object_put(obj);
2158 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2160 * @data: GTT mapping ioctl data
2161 * @file: GEM object info
2163 * Simply returns the fake offset to userspace so it can mmap it.
2164 * The mmap call will end up in drm_gem_mmap(), which will set things
2165 * up so we can get faults in the handler above.
2167 * The fault handler will take care of binding the object into the GTT
2168 * (since it may have been evicted to make room for something), allocating
2169 * a fence register, and mapping the appropriate aperture address into
2173 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *file)
2176 struct drm_i915_gem_mmap_gtt *args = data;
2178 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2181 /* Immediately discard the backing storage */
2183 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2185 i915_gem_object_free_mmap_offset(obj);
2187 if (obj->base.filp == NULL)
2190 /* Our goal here is to return as much of the memory as
2191 * is possible back to the system as we are called from OOM.
2192 * To do this we must instruct the shmfs to drop all of its
2193 * backing pages, *now*.
2195 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2196 obj->mm.madv = __I915_MADV_PURGED;
2197 obj->mm.pages = ERR_PTR(-EFAULT);
2200 /* Try to discard unwanted pages */
2201 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2203 struct address_space *mapping;
2205 lockdep_assert_held(&obj->mm.lock);
2206 GEM_BUG_ON(obj->mm.pages);
2208 switch (obj->mm.madv) {
2209 case I915_MADV_DONTNEED:
2210 i915_gem_object_truncate(obj);
2211 case __I915_MADV_PURGED:
2215 if (obj->base.filp == NULL)
2218 mapping = obj->base.filp->f_mapping,
2219 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2223 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2224 struct sg_table *pages)
2226 struct sgt_iter sgt_iter;
2229 __i915_gem_object_release_shmem(obj, pages, true);
2231 i915_gem_gtt_finish_pages(obj, pages);
2233 if (i915_gem_object_needs_bit17_swizzle(obj))
2234 i915_gem_object_save_bit_17_swizzle(obj, pages);
2236 for_each_sgt_page(page, sgt_iter, pages) {
2238 set_page_dirty(page);
2240 if (obj->mm.madv == I915_MADV_WILLNEED)
2241 mark_page_accessed(page);
2245 obj->mm.dirty = false;
2247 sg_free_table(pages);
2251 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2253 struct radix_tree_iter iter;
2256 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2257 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2260 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2261 enum i915_mm_subclass subclass)
2263 struct sg_table *pages;
2265 if (i915_gem_object_has_pinned_pages(obj))
2268 GEM_BUG_ON(obj->bind_count);
2269 if (!READ_ONCE(obj->mm.pages))
2272 /* May be called by shrinker from within get_pages() (on another bo) */
2273 mutex_lock_nested(&obj->mm.lock, subclass);
2274 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2277 /* ->put_pages might need to allocate memory for the bit17 swizzle
2278 * array, hence protect them from being reaped by removing them from gtt
2280 pages = fetch_and_zero(&obj->mm.pages);
2283 if (obj->mm.mapping) {
2286 ptr = page_mask_bits(obj->mm.mapping);
2287 if (is_vmalloc_addr(ptr))
2290 kunmap(kmap_to_page(ptr));
2292 obj->mm.mapping = NULL;
2295 __i915_gem_object_reset_page_iter(obj);
2298 obj->ops->put_pages(obj, pages);
2301 mutex_unlock(&obj->mm.lock);
2304 static bool i915_sg_trim(struct sg_table *orig_st)
2306 struct sg_table new_st;
2307 struct scatterlist *sg, *new_sg;
2310 if (orig_st->nents == orig_st->orig_nents)
2313 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2316 new_sg = new_st.sgl;
2317 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2318 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2319 /* called before being DMA mapped, no need to copy sg->dma_* */
2320 new_sg = sg_next(new_sg);
2322 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2324 sg_free_table(orig_st);
2330 static struct sg_table *
2331 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2333 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2334 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2336 struct address_space *mapping;
2337 struct sg_table *st;
2338 struct scatterlist *sg;
2339 struct sgt_iter sgt_iter;
2341 unsigned long last_pfn = 0; /* suppress gcc warning */
2342 unsigned int max_segment;
2346 /* Assert that the object is not currently in any GPU domain. As it
2347 * wasn't in the GTT, there shouldn't be any way it could have been in
2350 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2351 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2353 max_segment = swiotlb_max_segment();
2355 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2357 st = kmalloc(sizeof(*st), GFP_KERNEL);
2359 return ERR_PTR(-ENOMEM);
2362 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2364 return ERR_PTR(-ENOMEM);
2367 /* Get the list of pages out of our struct file. They'll be pinned
2368 * at this point until we release them.
2370 * Fail silently without starting the shrinker
2372 mapping = obj->base.filp->f_mapping;
2373 noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
2374 noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
2378 for (i = 0; i < page_count; i++) {
2379 const unsigned int shrink[] = {
2380 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE,
2383 gfp_t gfp = noreclaim;
2386 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2387 if (likely(!IS_ERR(page)))
2391 ret = PTR_ERR(page);
2395 i915_gem_shrink(dev_priv, 2 * page_count, *s++);
2398 /* We've tried hard to allocate the memory by reaping
2399 * our own buffer, now let the real VM do its job and
2400 * go down in flames if truly OOM.
2402 * However, since graphics tend to be disposable,
2403 * defer the oom here by reporting the ENOMEM back
2407 /* reclaim and warn, but no oom */
2408 gfp = mapping_gfp_mask(mapping);
2410 /* Our bo are always dirty and so we require
2411 * kswapd to reclaim our pages (direct reclaim
2412 * does not effectively begin pageout of our
2413 * buffers on its own). However, direct reclaim
2414 * only waits for kswapd when under allocation
2415 * congestion. So as a result __GFP_RECLAIM is
2416 * unreliable and fails to actually reclaim our
2417 * dirty pages -- unless you try over and over
2418 * again with !__GFP_NORETRY. However, we still
2419 * want to fail this allocation rather than
2420 * trigger the out-of-memory killer and for
2421 * this we want __GFP_RETRY_MAYFAIL.
2423 gfp |= __GFP_RETRY_MAYFAIL;
2428 sg->length >= max_segment ||
2429 page_to_pfn(page) != last_pfn + 1) {
2433 sg_set_page(sg, page, PAGE_SIZE, 0);
2435 sg->length += PAGE_SIZE;
2437 last_pfn = page_to_pfn(page);
2439 /* Check that the i965g/gm workaround works. */
2440 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2442 if (sg) /* loop terminated early; short sg table */
2445 /* Trim unused sg entries to avoid wasting memory. */
2448 ret = i915_gem_gtt_prepare_pages(obj, st);
2450 /* DMA remapping failed? One possible cause is that
2451 * it could not reserve enough large entries, asking
2452 * for PAGE_SIZE chunks instead may be helpful.
2454 if (max_segment > PAGE_SIZE) {
2455 for_each_sgt_page(page, sgt_iter, st)
2459 max_segment = PAGE_SIZE;
2462 dev_warn(&dev_priv->drm.pdev->dev,
2463 "Failed to DMA remap %lu pages\n",
2469 if (i915_gem_object_needs_bit17_swizzle(obj))
2470 i915_gem_object_do_bit_17_swizzle(obj, st);
2477 for_each_sgt_page(page, sgt_iter, st)
2482 /* shmemfs first checks if there is enough memory to allocate the page
2483 * and reports ENOSPC should there be insufficient, along with the usual
2484 * ENOMEM for a genuine allocation failure.
2486 * We use ENOSPC in our driver to mean that we have run out of aperture
2487 * space and so want to translate the error from shmemfs back to our
2488 * usual understanding of ENOMEM.
2493 return ERR_PTR(ret);
2496 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2497 struct sg_table *pages)
2499 lockdep_assert_held(&obj->mm.lock);
2501 obj->mm.get_page.sg_pos = pages->sgl;
2502 obj->mm.get_page.sg_idx = 0;
2504 obj->mm.pages = pages;
2506 if (i915_gem_object_is_tiled(obj) &&
2507 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2508 GEM_BUG_ON(obj->mm.quirked);
2509 __i915_gem_object_pin_pages(obj);
2510 obj->mm.quirked = true;
2514 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2516 struct sg_table *pages;
2518 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2520 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2521 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2525 pages = obj->ops->get_pages(obj);
2526 if (unlikely(IS_ERR(pages)))
2527 return PTR_ERR(pages);
2529 __i915_gem_object_set_pages(obj, pages);
2533 /* Ensure that the associated pages are gathered from the backing storage
2534 * and pinned into our object. i915_gem_object_pin_pages() may be called
2535 * multiple times before they are released by a single call to
2536 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2537 * either as a result of memory pressure (reaping pages under the shrinker)
2538 * or as the object is itself released.
2540 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2544 err = mutex_lock_interruptible(&obj->mm.lock);
2548 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2549 err = ____i915_gem_object_get_pages(obj);
2553 smp_mb__before_atomic();
2555 atomic_inc(&obj->mm.pages_pin_count);
2558 mutex_unlock(&obj->mm.lock);
2562 /* The 'mapping' part of i915_gem_object_pin_map() below */
2563 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2564 enum i915_map_type type)
2566 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2567 struct sg_table *sgt = obj->mm.pages;
2568 struct sgt_iter sgt_iter;
2570 struct page *stack_pages[32];
2571 struct page **pages = stack_pages;
2572 unsigned long i = 0;
2576 /* A single page can always be kmapped */
2577 if (n_pages == 1 && type == I915_MAP_WB)
2578 return kmap(sg_page(sgt->sgl));
2580 if (n_pages > ARRAY_SIZE(stack_pages)) {
2581 /* Too big for stack -- allocate temporary array instead */
2582 pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY);
2587 for_each_sgt_page(page, sgt_iter, sgt)
2590 /* Check that we have the expected number of pages */
2591 GEM_BUG_ON(i != n_pages);
2595 pgprot = PAGE_KERNEL;
2598 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2601 addr = vmap(pages, n_pages, 0, pgprot);
2603 if (pages != stack_pages)
2609 /* get, pin, and map the pages of the object into kernel space */
2610 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2611 enum i915_map_type type)
2613 enum i915_map_type has_type;
2618 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2620 ret = mutex_lock_interruptible(&obj->mm.lock);
2622 return ERR_PTR(ret);
2625 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2626 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2627 ret = ____i915_gem_object_get_pages(obj);
2631 smp_mb__before_atomic();
2633 atomic_inc(&obj->mm.pages_pin_count);
2636 GEM_BUG_ON(!obj->mm.pages);
2638 ptr = page_unpack_bits(obj->mm.mapping, &has_type);
2639 if (ptr && has_type != type) {
2645 if (is_vmalloc_addr(ptr))
2648 kunmap(kmap_to_page(ptr));
2650 ptr = obj->mm.mapping = NULL;
2654 ptr = i915_gem_object_map(obj, type);
2660 obj->mm.mapping = page_pack_bits(ptr, type);
2664 mutex_unlock(&obj->mm.lock);
2668 atomic_dec(&obj->mm.pages_pin_count);
2675 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2676 const struct drm_i915_gem_pwrite *arg)
2678 struct address_space *mapping = obj->base.filp->f_mapping;
2679 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2683 /* Before we instantiate/pin the backing store for our use, we
2684 * can prepopulate the shmemfs filp efficiently using a write into
2685 * the pagecache. We avoid the penalty of instantiating all the
2686 * pages, important if the user is just writing to a few and never
2687 * uses the object on the GPU, and using a direct write into shmemfs
2688 * allows it to avoid the cost of retrieving a page (either swapin
2689 * or clearing-before-use) before it is overwritten.
2691 if (READ_ONCE(obj->mm.pages))
2694 /* Before the pages are instantiated the object is treated as being
2695 * in the CPU domain. The pages will be clflushed as required before
2696 * use, and we can freely write into the pages directly. If userspace
2697 * races pwrite with any other operation; corruption will ensue -
2698 * that is userspace's prerogative!
2702 offset = arg->offset;
2703 pg = offset_in_page(offset);
2706 unsigned int len, unwritten;
2711 len = PAGE_SIZE - pg;
2715 err = pagecache_write_begin(obj->base.filp, mapping,
2722 unwritten = copy_from_user(vaddr + pg, user_data, len);
2725 err = pagecache_write_end(obj->base.filp, mapping,
2726 offset, len, len - unwritten,
2743 static bool ban_context(const struct i915_gem_context *ctx,
2746 return (i915_gem_context_is_bannable(ctx) &&
2747 score >= CONTEXT_SCORE_BAN_THRESHOLD);
2750 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2755 atomic_inc(&ctx->guilty_count);
2757 score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
2758 banned = ban_context(ctx, score);
2759 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2760 ctx->name, score, yesno(banned));
2764 i915_gem_context_set_banned(ctx);
2765 if (!IS_ERR_OR_NULL(ctx->file_priv)) {
2766 atomic_inc(&ctx->file_priv->context_bans);
2767 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2768 ctx->name, atomic_read(&ctx->file_priv->context_bans));
2772 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2774 atomic_inc(&ctx->active_count);
2777 struct drm_i915_gem_request *
2778 i915_gem_find_active_request(struct intel_engine_cs *engine)
2780 struct drm_i915_gem_request *request, *active = NULL;
2781 unsigned long flags;
2783 /* We are called by the error capture and reset at a random
2784 * point in time. In particular, note that neither is crucially
2785 * ordered with an interrupt. After a hang, the GPU is dead and we
2786 * assume that no more writes can happen (we waited long enough for
2787 * all writes that were in transaction to be flushed) - adding an
2788 * extra delay for a recent interrupt is pointless. Hence, we do
2789 * not need an engine->irq_seqno_barrier() before the seqno reads.
2791 spin_lock_irqsave(&engine->timeline->lock, flags);
2792 list_for_each_entry(request, &engine->timeline->requests, link) {
2793 if (__i915_gem_request_completed(request,
2794 request->global_seqno))
2797 GEM_BUG_ON(request->engine != engine);
2798 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2799 &request->fence.flags));
2804 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2809 static bool engine_stalled(struct intel_engine_cs *engine)
2811 if (!engine->hangcheck.stalled)
2814 /* Check for possible seqno movement after hang declaration */
2815 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2816 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2824 * Ensure irq handler finishes, and not run again.
2825 * Also return the active request so that we only search for it once.
2827 struct drm_i915_gem_request *
2828 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
2830 struct drm_i915_gem_request *request = NULL;
2832 /* Prevent the signaler thread from updating the request
2833 * state (by calling dma_fence_signal) as we are processing
2834 * the reset. The write from the GPU of the seqno is
2835 * asynchronous and the signaler thread may see a different
2836 * value to us and declare the request complete, even though
2837 * the reset routine have picked that request as the active
2838 * (incomplete) request. This conflict is not handled
2841 kthread_park(engine->breadcrumbs.signaler);
2843 /* Prevent request submission to the hardware until we have
2844 * completed the reset in i915_gem_reset_finish(). If a request
2845 * is completed by one engine, it may then queue a request
2846 * to a second via its engine->irq_tasklet *just* as we are
2847 * calling engine->init_hw() and also writing the ELSP.
2848 * Turning off the engine->irq_tasklet until the reset is over
2849 * prevents the race.
2851 tasklet_kill(&engine->irq_tasklet);
2852 tasklet_disable(&engine->irq_tasklet);
2854 if (engine->irq_seqno_barrier)
2855 engine->irq_seqno_barrier(engine);
2857 request = i915_gem_find_active_request(engine);
2858 if (request && request->fence.error == -EIO)
2859 request = ERR_PTR(-EIO); /* Previous reset failed! */
2864 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2866 struct intel_engine_cs *engine;
2867 struct drm_i915_gem_request *request;
2868 enum intel_engine_id id;
2871 for_each_engine(engine, dev_priv, id) {
2872 request = i915_gem_reset_prepare_engine(engine);
2873 if (IS_ERR(request)) {
2874 err = PTR_ERR(request);
2878 engine->hangcheck.active_request = request;
2881 i915_gem_revoke_fences(dev_priv);
2886 static void skip_request(struct drm_i915_gem_request *request)
2888 void *vaddr = request->ring->vaddr;
2891 /* As this request likely depends on state from the lost
2892 * context, clear out all the user operations leaving the
2893 * breadcrumb at the end (so we get the fence notifications).
2895 head = request->head;
2896 if (request->postfix < head) {
2897 memset(vaddr + head, 0, request->ring->size - head);
2900 memset(vaddr + head, 0, request->postfix - head);
2902 dma_fence_set_error(&request->fence, -EIO);
2905 static void engine_skip_context(struct drm_i915_gem_request *request)
2907 struct intel_engine_cs *engine = request->engine;
2908 struct i915_gem_context *hung_ctx = request->ctx;
2909 struct intel_timeline *timeline;
2910 unsigned long flags;
2912 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2914 spin_lock_irqsave(&engine->timeline->lock, flags);
2915 spin_lock(&timeline->lock);
2917 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2918 if (request->ctx == hung_ctx)
2919 skip_request(request);
2921 list_for_each_entry(request, &timeline->requests, link)
2922 skip_request(request);
2924 spin_unlock(&timeline->lock);
2925 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2928 /* Returns the request if it was guilty of the hang */
2929 static struct drm_i915_gem_request *
2930 i915_gem_reset_request(struct intel_engine_cs *engine,
2931 struct drm_i915_gem_request *request)
2933 /* The guilty request will get skipped on a hung engine.
2935 * Users of client default contexts do not rely on logical
2936 * state preserved between batches so it is safe to execute
2937 * queued requests following the hang. Non default contexts
2938 * rely on preserved state, so skipping a batch loses the
2939 * evolution of the state and it needs to be considered corrupted.
2940 * Executing more queued batches on top of corrupted state is
2941 * risky. But we take the risk by trying to advance through
2942 * the queued requests in order to make the client behaviour
2943 * more predictable around resets, by not throwing away random
2944 * amount of batches it has prepared for execution. Sophisticated
2945 * clients can use gem_reset_stats_ioctl and dma fence status
2946 * (exported via sync_file info ioctl on explicit fences) to observe
2947 * when it loses the context state and should rebuild accordingly.
2949 * The context ban, and ultimately the client ban, mechanism are safety
2950 * valves if client submission ends up resulting in nothing more than
2954 if (engine_stalled(engine)) {
2955 i915_gem_context_mark_guilty(request->ctx);
2956 skip_request(request);
2958 /* If this context is now banned, skip all pending requests. */
2959 if (i915_gem_context_is_banned(request->ctx))
2960 engine_skip_context(request);
2963 * Since this is not the hung engine, it may have advanced
2964 * since the hang declaration. Double check by refinding
2965 * the active request at the time of the reset.
2967 request = i915_gem_find_active_request(engine);
2969 i915_gem_context_mark_innocent(request->ctx);
2970 dma_fence_set_error(&request->fence, -EAGAIN);
2972 /* Rewind the engine to replay the incomplete rq */
2973 spin_lock_irq(&engine->timeline->lock);
2974 request = list_prev_entry(request, link);
2975 if (&request->link == &engine->timeline->requests)
2977 spin_unlock_irq(&engine->timeline->lock);
2984 void i915_gem_reset_engine(struct intel_engine_cs *engine,
2985 struct drm_i915_gem_request *request)
2987 engine->irq_posted = 0;
2990 request = i915_gem_reset_request(engine, request);
2993 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2994 engine->name, request->global_seqno);
2997 /* Setup the CS to resume from the breadcrumb of the hung request */
2998 engine->reset_hw(engine, request);
3001 void i915_gem_reset(struct drm_i915_private *dev_priv)
3003 struct intel_engine_cs *engine;
3004 enum intel_engine_id id;
3006 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3008 i915_gem_retire_requests(dev_priv);
3010 for_each_engine(engine, dev_priv, id) {
3011 struct i915_gem_context *ctx;
3013 i915_gem_reset_engine(engine, engine->hangcheck.active_request);
3014 ctx = fetch_and_zero(&engine->last_retired_context);
3016 engine->context_unpin(engine, ctx);
3019 i915_gem_restore_fences(dev_priv);
3021 if (dev_priv->gt.awake) {
3022 intel_sanitize_gt_powersave(dev_priv);
3023 intel_enable_gt_powersave(dev_priv);
3024 if (INTEL_GEN(dev_priv) >= 6)
3025 gen6_rps_busy(dev_priv);
3029 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
3031 tasklet_enable(&engine->irq_tasklet);
3032 kthread_unpark(engine->breadcrumbs.signaler);
3035 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
3037 struct intel_engine_cs *engine;
3038 enum intel_engine_id id;
3040 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3042 for_each_engine(engine, dev_priv, id) {
3043 engine->hangcheck.active_request = NULL;
3044 i915_gem_reset_finish_engine(engine);
3048 static void nop_submit_request(struct drm_i915_gem_request *request)
3050 GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error));
3051 dma_fence_set_error(&request->fence, -EIO);
3052 i915_gem_request_submit(request);
3053 intel_engine_init_global_seqno(request->engine, request->global_seqno);
3056 static void engine_set_wedged(struct intel_engine_cs *engine)
3058 struct drm_i915_gem_request *request;
3059 unsigned long flags;
3061 /* We need to be sure that no thread is running the old callback as
3062 * we install the nop handler (otherwise we would submit a request
3063 * to hardware that will never complete). In order to prevent this
3064 * race, we wait until the machine is idle before making the swap
3065 * (using stop_machine()).
3067 engine->submit_request = nop_submit_request;
3069 /* Mark all executing requests as skipped */
3070 spin_lock_irqsave(&engine->timeline->lock, flags);
3071 list_for_each_entry(request, &engine->timeline->requests, link)
3072 if (!i915_gem_request_completed(request))
3073 dma_fence_set_error(&request->fence, -EIO);
3074 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3077 * Clear the execlists queue up before freeing the requests, as those
3078 * are the ones that keep the context and ringbuffer backing objects
3082 if (i915.enable_execlists) {
3083 struct execlist_port *port = engine->execlist_port;
3084 unsigned long flags;
3087 spin_lock_irqsave(&engine->timeline->lock, flags);
3089 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
3090 i915_gem_request_put(port_request(&port[n]));
3091 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
3092 engine->execlist_queue = RB_ROOT;
3093 engine->execlist_first = NULL;
3095 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3097 /* The port is checked prior to scheduling a tasklet, but
3098 * just in case we have suspended the tasklet to do the
3099 * wedging make sure that when it wakes, it decides there
3100 * is no work to do by clearing the irq_posted bit.
3102 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
3105 /* Mark all pending requests as complete so that any concurrent
3106 * (lockless) lookup doesn't try and wait upon the request as we
3109 intel_engine_init_global_seqno(engine,
3110 intel_engine_last_submit(engine));
3113 static int __i915_gem_set_wedged_BKL(void *data)
3115 struct drm_i915_private *i915 = data;
3116 struct intel_engine_cs *engine;
3117 enum intel_engine_id id;
3119 for_each_engine(engine, i915, id)
3120 engine_set_wedged(engine);
3122 set_bit(I915_WEDGED, &i915->gpu_error.flags);
3123 wake_up_all(&i915->gpu_error.reset_queue);
3128 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
3130 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
3133 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3135 struct i915_gem_timeline *tl;
3138 lockdep_assert_held(&i915->drm.struct_mutex);
3139 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3142 /* Before unwedging, make sure that all pending operations
3143 * are flushed and errored out - we may have requests waiting upon
3144 * third party fences. We marked all inflight requests as EIO, and
3145 * every execbuf since returned EIO, for consistency we want all
3146 * the currently pending requests to also be marked as EIO, which
3147 * is done inside our nop_submit_request - and so we must wait.
3149 * No more can be submitted until we reset the wedged bit.
3151 list_for_each_entry(tl, &i915->gt.timelines, link) {
3152 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3153 struct drm_i915_gem_request *rq;
3155 rq = i915_gem_active_peek(&tl->engine[i].last_request,
3156 &i915->drm.struct_mutex);
3160 /* We can't use our normal waiter as we want to
3161 * avoid recursively trying to handle the current
3162 * reset. The basic dma_fence_default_wait() installs
3163 * a callback for dma_fence_signal(), which is
3164 * triggered by our nop handler (indirectly, the
3165 * callback enables the signaler thread which is
3166 * woken by the nop_submit_request() advancing the seqno
3167 * and when the seqno passes the fence, the signaler
3168 * then signals the fence waking us up).
3170 if (dma_fence_default_wait(&rq->fence, true,
3171 MAX_SCHEDULE_TIMEOUT) < 0)
3176 /* Undo nop_submit_request. We prevent all new i915 requests from
3177 * being queued (by disallowing execbuf whilst wedged) so having
3178 * waited for all active requests above, we know the system is idle
3179 * and do not have to worry about a thread being inside
3180 * engine->submit_request() as we swap over. So unlike installing
3181 * the nop_submit_request on reset, we can do this from normal
3182 * context and do not require stop_machine().
3184 intel_engines_reset_default_submission(i915);
3185 i915_gem_contexts_lost(i915);
3187 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3188 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3194 i915_gem_retire_work_handler(struct work_struct *work)
3196 struct drm_i915_private *dev_priv =
3197 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3198 struct drm_device *dev = &dev_priv->drm;
3200 /* Come back later if the device is busy... */
3201 if (mutex_trylock(&dev->struct_mutex)) {
3202 i915_gem_retire_requests(dev_priv);
3203 mutex_unlock(&dev->struct_mutex);
3206 /* Keep the retire handler running until we are finally idle.
3207 * We do not need to do this test under locking as in the worst-case
3208 * we queue the retire worker once too often.
3210 if (READ_ONCE(dev_priv->gt.awake)) {
3211 i915_queue_hangcheck(dev_priv);
3212 queue_delayed_work(dev_priv->wq,
3213 &dev_priv->gt.retire_work,
3214 round_jiffies_up_relative(HZ));
3219 i915_gem_idle_work_handler(struct work_struct *work)
3221 struct drm_i915_private *dev_priv =
3222 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3223 struct drm_device *dev = &dev_priv->drm;
3224 bool rearm_hangcheck;
3226 if (!READ_ONCE(dev_priv->gt.awake))
3230 * Wait for last execlists context complete, but bail out in case a
3231 * new request is submitted.
3233 wait_for(intel_engines_are_idle(dev_priv), 10);
3234 if (READ_ONCE(dev_priv->gt.active_requests))
3238 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3240 if (!mutex_trylock(&dev->struct_mutex)) {
3241 /* Currently busy, come back later */
3242 mod_delayed_work(dev_priv->wq,
3243 &dev_priv->gt.idle_work,
3244 msecs_to_jiffies(50));
3249 * New request retired after this work handler started, extend active
3250 * period until next instance of the work.
3252 if (work_pending(work))
3255 if (dev_priv->gt.active_requests)
3258 if (wait_for(intel_engines_are_idle(dev_priv), 10))
3259 DRM_ERROR("Timeout waiting for engines to idle\n");
3261 intel_engines_mark_idle(dev_priv);
3262 i915_gem_timelines_mark_idle(dev_priv);
3264 GEM_BUG_ON(!dev_priv->gt.awake);
3265 dev_priv->gt.awake = false;
3266 rearm_hangcheck = false;
3268 if (INTEL_GEN(dev_priv) >= 6)
3269 gen6_rps_idle(dev_priv);
3270 intel_runtime_pm_put(dev_priv);
3272 mutex_unlock(&dev->struct_mutex);
3275 if (rearm_hangcheck) {
3276 GEM_BUG_ON(!dev_priv->gt.awake);
3277 i915_queue_hangcheck(dev_priv);
3281 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3283 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3284 struct drm_i915_file_private *fpriv = file->driver_priv;
3285 struct i915_vma *vma, *vn;
3287 mutex_lock(&obj->base.dev->struct_mutex);
3288 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3289 if (vma->vm->file == fpriv)
3290 i915_vma_close(vma);
3292 vma = obj->vma_hashed;
3293 if (vma && vma->ctx->file_priv == fpriv)
3294 i915_vma_unlink_ctx(vma);
3296 if (i915_gem_object_is_active(obj) &&
3297 !i915_gem_object_has_active_reference(obj)) {
3298 i915_gem_object_set_active_reference(obj);
3299 i915_gem_object_get(obj);
3301 mutex_unlock(&obj->base.dev->struct_mutex);
3304 static unsigned long to_wait_timeout(s64 timeout_ns)
3307 return MAX_SCHEDULE_TIMEOUT;
3309 if (timeout_ns == 0)
3312 return nsecs_to_jiffies_timeout(timeout_ns);
3316 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3317 * @dev: drm device pointer
3318 * @data: ioctl data blob
3319 * @file: drm file pointer
3321 * Returns 0 if successful, else an error is returned with the remaining time in
3322 * the timeout parameter.
3323 * -ETIME: object is still busy after timeout
3324 * -ERESTARTSYS: signal interrupted the wait
3325 * -ENONENT: object doesn't exist
3326 * Also possible, but rare:
3327 * -EAGAIN: GPU wedged
3329 * -ENODEV: Internal IRQ fail
3330 * -E?: The add request failed
3332 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3333 * non-zero timeout parameter the wait ioctl will wait for the given number of
3334 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3335 * without holding struct_mutex the object may become re-busied before this
3336 * function completes. A similar but shorter * race condition exists in the busy
3340 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3342 struct drm_i915_gem_wait *args = data;
3343 struct drm_i915_gem_object *obj;
3347 if (args->flags != 0)
3350 obj = i915_gem_object_lookup(file, args->bo_handle);
3354 start = ktime_get();
3356 ret = i915_gem_object_wait(obj,
3357 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3358 to_wait_timeout(args->timeout_ns),
3359 to_rps_client(file));
3361 if (args->timeout_ns > 0) {
3362 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3363 if (args->timeout_ns < 0)
3364 args->timeout_ns = 0;
3367 * Apparently ktime isn't accurate enough and occasionally has a
3368 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3369 * things up to make the test happy. We allow up to 1 jiffy.
3371 * This is a regression from the timespec->ktime conversion.
3373 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3374 args->timeout_ns = 0;
3377 i915_gem_object_put(obj);
3381 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3385 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3386 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3394 static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
3396 return wait_for(intel_engine_is_idle(engine), timeout_ms);
3399 static int wait_for_engines(struct drm_i915_private *i915)
3401 struct intel_engine_cs *engine;
3402 enum intel_engine_id id;
3404 for_each_engine(engine, i915, id) {
3405 if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
3406 i915_gem_set_wedged(i915);
3410 GEM_BUG_ON(intel_engine_get_seqno(engine) !=
3411 intel_engine_last_submit(engine));
3417 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3421 /* If the device is asleep, we have no requests outstanding */
3422 if (!READ_ONCE(i915->gt.awake))
3425 if (flags & I915_WAIT_LOCKED) {
3426 struct i915_gem_timeline *tl;
3428 lockdep_assert_held(&i915->drm.struct_mutex);
3430 list_for_each_entry(tl, &i915->gt.timelines, link) {
3431 ret = wait_for_timeline(tl, flags);
3436 i915_gem_retire_requests(i915);
3437 GEM_BUG_ON(i915->gt.active_requests);
3439 ret = wait_for_engines(i915);
3441 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3447 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3450 * We manually flush the CPU domain so that we can override and
3451 * force the flush for the display, and perform it asyncrhonously.
3453 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3454 if (obj->cache_dirty)
3455 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3456 obj->base.write_domain = 0;
3459 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3461 if (!READ_ONCE(obj->pin_display))
3464 mutex_lock(&obj->base.dev->struct_mutex);
3465 __i915_gem_object_flush_for_display(obj);
3466 mutex_unlock(&obj->base.dev->struct_mutex);
3470 * Moves a single object to the WC read, and possibly write domain.
3471 * @obj: object to act on
3472 * @write: ask for write access or read only
3474 * This function returns when the move is complete, including waiting on
3478 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
3482 lockdep_assert_held(&obj->base.dev->struct_mutex);
3484 ret = i915_gem_object_wait(obj,
3485 I915_WAIT_INTERRUPTIBLE |
3487 (write ? I915_WAIT_ALL : 0),
3488 MAX_SCHEDULE_TIMEOUT,
3493 if (obj->base.write_domain == I915_GEM_DOMAIN_WC)
3496 /* Flush and acquire obj->pages so that we are coherent through
3497 * direct access in memory with previous cached writes through
3498 * shmemfs and that our cache domain tracking remains valid.
3499 * For example, if the obj->filp was moved to swap without us
3500 * being notified and releasing the pages, we would mistakenly
3501 * continue to assume that the obj remained out of the CPU cached
3504 ret = i915_gem_object_pin_pages(obj);
3508 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
3510 /* Serialise direct access to this object with the barriers for
3511 * coherent writes from the GPU, by effectively invalidating the
3512 * WC domain upon first access.
3514 if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0)
3517 /* It should now be out of any other write domains, and we can update
3518 * the domain values for our changes.
3520 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);
3521 obj->base.read_domains |= I915_GEM_DOMAIN_WC;
3523 obj->base.read_domains = I915_GEM_DOMAIN_WC;
3524 obj->base.write_domain = I915_GEM_DOMAIN_WC;
3525 obj->mm.dirty = true;
3528 i915_gem_object_unpin_pages(obj);
3533 * Moves a single object to the GTT read, and possibly write domain.
3534 * @obj: object to act on
3535 * @write: ask for write access or read only
3537 * This function returns when the move is complete, including waiting on
3541 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3545 lockdep_assert_held(&obj->base.dev->struct_mutex);
3547 ret = i915_gem_object_wait(obj,
3548 I915_WAIT_INTERRUPTIBLE |
3550 (write ? I915_WAIT_ALL : 0),
3551 MAX_SCHEDULE_TIMEOUT,
3556 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3559 /* Flush and acquire obj->pages so that we are coherent through
3560 * direct access in memory with previous cached writes through
3561 * shmemfs and that our cache domain tracking remains valid.
3562 * For example, if the obj->filp was moved to swap without us
3563 * being notified and releasing the pages, we would mistakenly
3564 * continue to assume that the obj remained out of the CPU cached
3567 ret = i915_gem_object_pin_pages(obj);
3571 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
3573 /* Serialise direct access to this object with the barriers for
3574 * coherent writes from the GPU, by effectively invalidating the
3575 * GTT domain upon first access.
3577 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3580 /* It should now be out of any other write domains, and we can update
3581 * the domain values for our changes.
3583 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3584 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3586 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3587 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3588 obj->mm.dirty = true;
3591 i915_gem_object_unpin_pages(obj);
3596 * Changes the cache-level of an object across all VMA.
3597 * @obj: object to act on
3598 * @cache_level: new cache level to set for the object
3600 * After this function returns, the object will be in the new cache-level
3601 * across all GTT and the contents of the backing storage will be coherent,
3602 * with respect to the new cache-level. In order to keep the backing storage
3603 * coherent for all users, we only allow a single cache level to be set
3604 * globally on the object and prevent it from being changed whilst the
3605 * hardware is reading from the object. That is if the object is currently
3606 * on the scanout it will be set to uncached (or equivalent display
3607 * cache coherency) and all non-MOCS GPU access will also be uncached so
3608 * that all direct access to the scanout remains coherent.
3610 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3611 enum i915_cache_level cache_level)
3613 struct i915_vma *vma;
3616 lockdep_assert_held(&obj->base.dev->struct_mutex);
3618 if (obj->cache_level == cache_level)
3621 /* Inspect the list of currently bound VMA and unbind any that would
3622 * be invalid given the new cache-level. This is principally to
3623 * catch the issue of the CS prefetch crossing page boundaries and
3624 * reading an invalid PTE on older architectures.
3627 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3628 if (!drm_mm_node_allocated(&vma->node))
3631 if (i915_vma_is_pinned(vma)) {
3632 DRM_DEBUG("can not change the cache level of pinned objects\n");
3636 if (i915_gem_valid_gtt_space(vma, cache_level))
3639 ret = i915_vma_unbind(vma);
3643 /* As unbinding may affect other elements in the
3644 * obj->vma_list (due to side-effects from retiring
3645 * an active vma), play safe and restart the iterator.
3650 /* We can reuse the existing drm_mm nodes but need to change the
3651 * cache-level on the PTE. We could simply unbind them all and
3652 * rebind with the correct cache-level on next use. However since
3653 * we already have a valid slot, dma mapping, pages etc, we may as
3654 * rewrite the PTE in the belief that doing so tramples upon less
3655 * state and so involves less work.
3657 if (obj->bind_count) {
3658 /* Before we change the PTE, the GPU must not be accessing it.
3659 * If we wait upon the object, we know that all the bound
3660 * VMA are no longer active.
3662 ret = i915_gem_object_wait(obj,
3663 I915_WAIT_INTERRUPTIBLE |
3666 MAX_SCHEDULE_TIMEOUT,
3671 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3672 cache_level != I915_CACHE_NONE) {
3673 /* Access to snoopable pages through the GTT is
3674 * incoherent and on some machines causes a hard
3675 * lockup. Relinquish the CPU mmaping to force
3676 * userspace to refault in the pages and we can
3677 * then double check if the GTT mapping is still
3678 * valid for that pointer access.
3680 i915_gem_release_mmap(obj);
3682 /* As we no longer need a fence for GTT access,
3683 * we can relinquish it now (and so prevent having
3684 * to steal a fence from someone else on the next
3685 * fence request). Note GPU activity would have
3686 * dropped the fence as all snoopable access is
3687 * supposed to be linear.
3689 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3690 ret = i915_vma_put_fence(vma);
3695 /* We either have incoherent backing store and
3696 * so no GTT access or the architecture is fully
3697 * coherent. In such cases, existing GTT mmaps
3698 * ignore the cache bit in the PTE and we can
3699 * rewrite it without confusing the GPU or having
3700 * to force userspace to fault back in its mmaps.
3704 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3705 if (!drm_mm_node_allocated(&vma->node))
3708 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3714 list_for_each_entry(vma, &obj->vma_list, obj_link)
3715 vma->node.color = cache_level;
3716 obj->cache_level = cache_level;
3717 obj->cache_coherent = i915_gem_object_is_coherent(obj);
3718 obj->cache_dirty = true; /* Always invalidate stale cachelines */
3723 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3724 struct drm_file *file)
3726 struct drm_i915_gem_caching *args = data;
3727 struct drm_i915_gem_object *obj;
3731 obj = i915_gem_object_lookup_rcu(file, args->handle);
3737 switch (obj->cache_level) {
3738 case I915_CACHE_LLC:
3739 case I915_CACHE_L3_LLC:
3740 args->caching = I915_CACHING_CACHED;
3744 args->caching = I915_CACHING_DISPLAY;
3748 args->caching = I915_CACHING_NONE;
3756 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3757 struct drm_file *file)
3759 struct drm_i915_private *i915 = to_i915(dev);
3760 struct drm_i915_gem_caching *args = data;
3761 struct drm_i915_gem_object *obj;
3762 enum i915_cache_level level;
3765 switch (args->caching) {
3766 case I915_CACHING_NONE:
3767 level = I915_CACHE_NONE;
3769 case I915_CACHING_CACHED:
3771 * Due to a HW issue on BXT A stepping, GPU stores via a
3772 * snooped mapping may leave stale data in a corresponding CPU
3773 * cacheline, whereas normally such cachelines would get
3776 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3779 level = I915_CACHE_LLC;
3781 case I915_CACHING_DISPLAY:
3782 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3788 obj = i915_gem_object_lookup(file, args->handle);
3792 if (obj->cache_level == level)
3795 ret = i915_gem_object_wait(obj,
3796 I915_WAIT_INTERRUPTIBLE,
3797 MAX_SCHEDULE_TIMEOUT,
3798 to_rps_client(file));
3802 ret = i915_mutex_lock_interruptible(dev);
3806 ret = i915_gem_object_set_cache_level(obj, level);
3807 mutex_unlock(&dev->struct_mutex);
3810 i915_gem_object_put(obj);
3815 * Prepare buffer for display plane (scanout, cursors, etc).
3816 * Can be called from an uninterruptible phase (modesetting) and allows
3817 * any flushes to be pipelined (for pageflips).
3820 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3822 const struct i915_ggtt_view *view)
3824 struct i915_vma *vma;
3827 lockdep_assert_held(&obj->base.dev->struct_mutex);
3829 /* Mark the pin_display early so that we account for the
3830 * display coherency whilst setting up the cache domains.
3834 /* The display engine is not coherent with the LLC cache on gen6. As
3835 * a result, we make sure that the pinning that is about to occur is
3836 * done with uncached PTEs. This is lowest common denominator for all
3839 * However for gen6+, we could do better by using the GFDT bit instead
3840 * of uncaching, which would allow us to flush all the LLC-cached data
3841 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3843 ret = i915_gem_object_set_cache_level(obj,
3844 HAS_WT(to_i915(obj->base.dev)) ?
3845 I915_CACHE_WT : I915_CACHE_NONE);
3848 goto err_unpin_display;
3851 /* As the user may map the buffer once pinned in the display plane
3852 * (e.g. libkms for the bootup splash), we have to ensure that we
3853 * always use map_and_fenceable for all scanout buffers. However,
3854 * it may simply be too big to fit into mappable, in which case
3855 * put it anyway and hope that userspace can cope (but always first
3856 * try to preserve the existing ABI).
3858 vma = ERR_PTR(-ENOSPC);
3859 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3860 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3861 PIN_MAPPABLE | PIN_NONBLOCK);
3863 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3866 /* Valleyview is definitely limited to scanning out the first
3867 * 512MiB. Lets presume this behaviour was inherited from the
3868 * g4x display engine and that all earlier gen are similarly
3869 * limited. Testing suggests that it is a little more
3870 * complicated than this. For example, Cherryview appears quite
3871 * happy to scanout from anywhere within its global aperture.
3874 if (HAS_GMCH_DISPLAY(i915))
3875 flags = PIN_MAPPABLE;
3876 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3879 goto err_unpin_display;
3881 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3883 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3884 __i915_gem_object_flush_for_display(obj);
3885 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3887 /* It should now be out of any other write domains, and we can update
3888 * the domain values for our changes.
3890 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3900 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3902 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3904 if (WARN_ON(vma->obj->pin_display == 0))
3907 if (--vma->obj->pin_display == 0)
3908 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3910 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3911 i915_gem_object_bump_inactive_ggtt(vma->obj);
3913 i915_vma_unpin(vma);
3917 * Moves a single object to the CPU read, and possibly write domain.
3918 * @obj: object to act on
3919 * @write: requesting write or read-only access
3921 * This function returns when the move is complete, including waiting on
3925 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3929 lockdep_assert_held(&obj->base.dev->struct_mutex);
3931 ret = i915_gem_object_wait(obj,
3932 I915_WAIT_INTERRUPTIBLE |
3934 (write ? I915_WAIT_ALL : 0),
3935 MAX_SCHEDULE_TIMEOUT,
3940 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3942 /* Flush the CPU cache if it's still invalid. */
3943 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3944 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3945 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3948 /* It should now be out of any other write domains, and we can update
3949 * the domain values for our changes.
3951 GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3953 /* If we're writing through the CPU, then the GPU read domains will
3954 * need to be invalidated at next use.
3957 __start_cpu_write(obj);
3962 /* Throttle our rendering by waiting until the ring has completed our requests
3963 * emitted over 20 msec ago.
3965 * Note that if we were to use the current jiffies each time around the loop,
3966 * we wouldn't escape the function with any frames outstanding if the time to
3967 * render a frame was over 20ms.
3969 * This should get us reasonable parallelism between CPU and GPU but also
3970 * relatively low latency when blocking on a particular request to finish.
3973 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3975 struct drm_i915_private *dev_priv = to_i915(dev);
3976 struct drm_i915_file_private *file_priv = file->driver_priv;
3977 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3978 struct drm_i915_gem_request *request, *target = NULL;
3981 /* ABI: return -EIO if already wedged */
3982 if (i915_terminally_wedged(&dev_priv->gpu_error))
3985 spin_lock(&file_priv->mm.lock);
3986 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3987 if (time_after_eq(request->emitted_jiffies, recent_enough))
3991 list_del(&target->client_link);
3992 target->file_priv = NULL;
3998 i915_gem_request_get(target);
3999 spin_unlock(&file_priv->mm.lock);
4004 ret = i915_wait_request(target,
4005 I915_WAIT_INTERRUPTIBLE,
4006 MAX_SCHEDULE_TIMEOUT);
4007 i915_gem_request_put(target);
4009 return ret < 0 ? ret : 0;
4013 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4014 const struct i915_ggtt_view *view,
4019 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
4020 struct i915_address_space *vm = &dev_priv->ggtt.base;
4021 struct i915_vma *vma;
4024 lockdep_assert_held(&obj->base.dev->struct_mutex);
4026 vma = i915_vma_instance(obj, vm, view);
4027 if (unlikely(IS_ERR(vma)))
4030 if (i915_vma_misplaced(vma, size, alignment, flags)) {
4031 if (flags & PIN_NONBLOCK &&
4032 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
4033 return ERR_PTR(-ENOSPC);
4035 if (flags & PIN_MAPPABLE) {
4036 /* If the required space is larger than the available
4037 * aperture, we will not able to find a slot for the
4038 * object and unbinding the object now will be in
4039 * vain. Worse, doing so may cause us to ping-pong
4040 * the object in and out of the Global GTT and
4041 * waste a lot of cycles under the mutex.
4043 if (vma->fence_size > dev_priv->ggtt.mappable_end)
4044 return ERR_PTR(-E2BIG);
4046 /* If NONBLOCK is set the caller is optimistically
4047 * trying to cache the full object within the mappable
4048 * aperture, and *must* have a fallback in place for
4049 * situations where we cannot bind the object. We
4050 * can be a little more lax here and use the fallback
4051 * more often to avoid costly migrations of ourselves
4052 * and other objects within the aperture.
4054 * Half-the-aperture is used as a simple heuristic.
4055 * More interesting would to do search for a free
4056 * block prior to making the commitment to unbind.
4057 * That caters for the self-harm case, and with a
4058 * little more heuristics (e.g. NOFAULT, NOEVICT)
4059 * we could try to minimise harm to others.
4061 if (flags & PIN_NONBLOCK &&
4062 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
4063 return ERR_PTR(-ENOSPC);
4066 WARN(i915_vma_is_pinned(vma),
4067 "bo is already pinned in ggtt with incorrect alignment:"
4068 " offset=%08x, req.alignment=%llx,"
4069 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4070 i915_ggtt_offset(vma), alignment,
4071 !!(flags & PIN_MAPPABLE),
4072 i915_vma_is_map_and_fenceable(vma));
4073 ret = i915_vma_unbind(vma);
4075 return ERR_PTR(ret);
4078 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
4080 return ERR_PTR(ret);
4085 static __always_inline unsigned int __busy_read_flag(unsigned int id)
4087 /* Note that we could alias engines in the execbuf API, but
4088 * that would be very unwise as it prevents userspace from
4089 * fine control over engine selection. Ahem.
4091 * This should be something like EXEC_MAX_ENGINE instead of
4094 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
4095 return 0x10000 << id;
4098 static __always_inline unsigned int __busy_write_id(unsigned int id)
4100 /* The uABI guarantees an active writer is also amongst the read
4101 * engines. This would be true if we accessed the activity tracking
4102 * under the lock, but as we perform the lookup of the object and
4103 * its activity locklessly we can not guarantee that the last_write
4104 * being active implies that we have set the same engine flag from
4105 * last_read - hence we always set both read and write busy for
4108 return id | __busy_read_flag(id);
4111 static __always_inline unsigned int
4112 __busy_set_if_active(const struct dma_fence *fence,
4113 unsigned int (*flag)(unsigned int id))
4115 struct drm_i915_gem_request *rq;
4117 /* We have to check the current hw status of the fence as the uABI
4118 * guarantees forward progress. We could rely on the idle worker
4119 * to eventually flush us, but to minimise latency just ask the
4122 * Note we only report on the status of native fences.
4124 if (!dma_fence_is_i915(fence))
4127 /* opencode to_request() in order to avoid const warnings */
4128 rq = container_of(fence, struct drm_i915_gem_request, fence);
4129 if (i915_gem_request_completed(rq))
4132 return flag(rq->engine->uabi_id);
4135 static __always_inline unsigned int
4136 busy_check_reader(const struct dma_fence *fence)
4138 return __busy_set_if_active(fence, __busy_read_flag);
4141 static __always_inline unsigned int
4142 busy_check_writer(const struct dma_fence *fence)
4147 return __busy_set_if_active(fence, __busy_write_id);
4151 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4152 struct drm_file *file)
4154 struct drm_i915_gem_busy *args = data;
4155 struct drm_i915_gem_object *obj;
4156 struct reservation_object_list *list;
4162 obj = i915_gem_object_lookup_rcu(file, args->handle);
4166 /* A discrepancy here is that we do not report the status of
4167 * non-i915 fences, i.e. even though we may report the object as idle,
4168 * a call to set-domain may still stall waiting for foreign rendering.
4169 * This also means that wait-ioctl may report an object as busy,
4170 * where busy-ioctl considers it idle.
4172 * We trade the ability to warn of foreign fences to report on which
4173 * i915 engines are active for the object.
4175 * Alternatively, we can trade that extra information on read/write
4178 * !reservation_object_test_signaled_rcu(obj->resv, true);
4179 * to report the overall busyness. This is what the wait-ioctl does.
4183 seq = raw_read_seqcount(&obj->resv->seq);
4185 /* Translate the exclusive fence to the READ *and* WRITE engine */
4186 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4188 /* Translate shared fences to READ set of engines */
4189 list = rcu_dereference(obj->resv->fence);
4191 unsigned int shared_count = list->shared_count, i;
4193 for (i = 0; i < shared_count; ++i) {
4194 struct dma_fence *fence =
4195 rcu_dereference(list->shared[i]);
4197 args->busy |= busy_check_reader(fence);
4201 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4211 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4212 struct drm_file *file_priv)
4214 return i915_gem_ring_throttle(dev, file_priv);
4218 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4219 struct drm_file *file_priv)
4221 struct drm_i915_private *dev_priv = to_i915(dev);
4222 struct drm_i915_gem_madvise *args = data;
4223 struct drm_i915_gem_object *obj;
4226 switch (args->madv) {
4227 case I915_MADV_DONTNEED:
4228 case I915_MADV_WILLNEED:
4234 obj = i915_gem_object_lookup(file_priv, args->handle);
4238 err = mutex_lock_interruptible(&obj->mm.lock);
4242 if (obj->mm.pages &&
4243 i915_gem_object_is_tiled(obj) &&
4244 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4245 if (obj->mm.madv == I915_MADV_WILLNEED) {
4246 GEM_BUG_ON(!obj->mm.quirked);
4247 __i915_gem_object_unpin_pages(obj);
4248 obj->mm.quirked = false;
4250 if (args->madv == I915_MADV_WILLNEED) {
4251 GEM_BUG_ON(obj->mm.quirked);
4252 __i915_gem_object_pin_pages(obj);
4253 obj->mm.quirked = true;
4257 if (obj->mm.madv != __I915_MADV_PURGED)
4258 obj->mm.madv = args->madv;
4260 /* if the object is no longer attached, discard its backing storage */
4261 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4262 i915_gem_object_truncate(obj);
4264 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4265 mutex_unlock(&obj->mm.lock);
4268 i915_gem_object_put(obj);
4273 frontbuffer_retire(struct i915_gem_active *active,
4274 struct drm_i915_gem_request *request)
4276 struct drm_i915_gem_object *obj =
4277 container_of(active, typeof(*obj), frontbuffer_write);
4279 intel_fb_obj_flush(obj, ORIGIN_CS);
4282 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4283 const struct drm_i915_gem_object_ops *ops)
4285 mutex_init(&obj->mm.lock);
4287 INIT_LIST_HEAD(&obj->global_link);
4288 INIT_LIST_HEAD(&obj->userfault_link);
4289 INIT_LIST_HEAD(&obj->vma_list);
4290 INIT_LIST_HEAD(&obj->batch_pool_link);
4294 reservation_object_init(&obj->__builtin_resv);
4295 obj->resv = &obj->__builtin_resv;
4297 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4298 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4300 obj->mm.madv = I915_MADV_WILLNEED;
4301 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4302 mutex_init(&obj->mm.get_page.lock);
4304 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4307 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4308 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4309 I915_GEM_OBJECT_IS_SHRINKABLE,
4311 .get_pages = i915_gem_object_get_pages_gtt,
4312 .put_pages = i915_gem_object_put_pages_gtt,
4314 .pwrite = i915_gem_object_pwrite_gtt,
4317 struct drm_i915_gem_object *
4318 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4320 struct drm_i915_gem_object *obj;
4321 struct address_space *mapping;
4325 /* There is a prevalence of the assumption that we fit the object's
4326 * page count inside a 32bit _signed_ variable. Let's document this and
4327 * catch if we ever need to fix it. In the meantime, if you do spot
4328 * such a local variable, please consider fixing!
4330 if (size >> PAGE_SHIFT > INT_MAX)
4331 return ERR_PTR(-E2BIG);
4333 if (overflows_type(size, obj->base.size))
4334 return ERR_PTR(-E2BIG);
4336 obj = i915_gem_object_alloc(dev_priv);
4338 return ERR_PTR(-ENOMEM);
4340 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4344 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4345 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4346 /* 965gm cannot relocate objects above 4GiB. */
4347 mask &= ~__GFP_HIGHMEM;
4348 mask |= __GFP_DMA32;
4351 mapping = obj->base.filp->f_mapping;
4352 mapping_set_gfp_mask(mapping, mask);
4353 GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
4355 i915_gem_object_init(obj, &i915_gem_object_ops);
4357 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4358 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4360 if (HAS_LLC(dev_priv)) {
4361 /* On some devices, we can have the GPU use the LLC (the CPU
4362 * cache) for about a 10% performance improvement
4363 * compared to uncached. Graphics requests other than
4364 * display scanout are coherent with the CPU in
4365 * accessing this cache. This means in this mode we
4366 * don't need to clflush on the CPU side, and on the
4367 * GPU side we only need to flush internal caches to
4368 * get data visible to the CPU.
4370 * However, we maintain the display planes as UC, and so
4371 * need to rebind when first used as such.
4373 obj->cache_level = I915_CACHE_LLC;
4375 obj->cache_level = I915_CACHE_NONE;
4377 obj->cache_coherent = i915_gem_object_is_coherent(obj);
4378 obj->cache_dirty = !obj->cache_coherent;
4380 trace_i915_gem_object_create(obj);
4385 i915_gem_object_free(obj);
4386 return ERR_PTR(ret);
4389 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4391 /* If we are the last user of the backing storage (be it shmemfs
4392 * pages or stolen etc), we know that the pages are going to be
4393 * immediately released. In this case, we can then skip copying
4394 * back the contents from the GPU.
4397 if (obj->mm.madv != I915_MADV_WILLNEED)
4400 if (obj->base.filp == NULL)
4403 /* At first glance, this looks racy, but then again so would be
4404 * userspace racing mmap against close. However, the first external
4405 * reference to the filp can only be obtained through the
4406 * i915_gem_mmap_ioctl() which safeguards us against the user
4407 * acquiring such a reference whilst we are in the middle of
4408 * freeing the object.
4410 return atomic_long_read(&obj->base.filp->f_count) == 1;
4413 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4414 struct llist_node *freed)
4416 struct drm_i915_gem_object *obj, *on;
4418 mutex_lock(&i915->drm.struct_mutex);
4419 intel_runtime_pm_get(i915);
4420 llist_for_each_entry(obj, freed, freed) {
4421 struct i915_vma *vma, *vn;
4423 trace_i915_gem_object_destroy(obj);
4425 GEM_BUG_ON(i915_gem_object_is_active(obj));
4426 list_for_each_entry_safe(vma, vn,
4427 &obj->vma_list, obj_link) {
4428 GEM_BUG_ON(i915_vma_is_active(vma));
4429 vma->flags &= ~I915_VMA_PIN_MASK;
4430 i915_vma_close(vma);
4432 GEM_BUG_ON(!list_empty(&obj->vma_list));
4433 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4435 list_del(&obj->global_link);
4437 intel_runtime_pm_put(i915);
4438 mutex_unlock(&i915->drm.struct_mutex);
4442 llist_for_each_entry_safe(obj, on, freed, freed) {
4443 GEM_BUG_ON(obj->bind_count);
4444 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4446 if (obj->ops->release)
4447 obj->ops->release(obj);
4449 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4450 atomic_set(&obj->mm.pages_pin_count, 0);
4451 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4452 GEM_BUG_ON(obj->mm.pages);
4454 if (obj->base.import_attach)
4455 drm_prime_gem_destroy(&obj->base, NULL);
4457 reservation_object_fini(&obj->__builtin_resv);
4458 drm_gem_object_release(&obj->base);
4459 i915_gem_info_remove_obj(i915, obj->base.size);
4462 i915_gem_object_free(obj);
4466 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4468 struct llist_node *freed;
4470 freed = llist_del_all(&i915->mm.free_list);
4471 if (unlikely(freed))
4472 __i915_gem_free_objects(i915, freed);
4475 static void __i915_gem_free_work(struct work_struct *work)
4477 struct drm_i915_private *i915 =
4478 container_of(work, struct drm_i915_private, mm.free_work);
4479 struct llist_node *freed;
4481 /* All file-owned VMA should have been released by this point through
4482 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4483 * However, the object may also be bound into the global GTT (e.g.
4484 * older GPUs without per-process support, or for direct access through
4485 * the GTT either for the user or for scanout). Those VMA still need to
4489 while ((freed = llist_del_all(&i915->mm.free_list))) {
4490 __i915_gem_free_objects(i915, freed);
4496 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4498 struct drm_i915_gem_object *obj =
4499 container_of(head, typeof(*obj), rcu);
4500 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4502 /* We can't simply use call_rcu() from i915_gem_free_object()
4503 * as we need to block whilst unbinding, and the call_rcu
4504 * task may be called from softirq context. So we take a
4505 * detour through a worker.
4507 if (llist_add(&obj->freed, &i915->mm.free_list))
4508 schedule_work(&i915->mm.free_work);
4511 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4513 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4515 if (obj->mm.quirked)
4516 __i915_gem_object_unpin_pages(obj);
4518 if (discard_backing_storage(obj))
4519 obj->mm.madv = I915_MADV_DONTNEED;
4521 /* Before we free the object, make sure any pure RCU-only
4522 * read-side critical sections are complete, e.g.
4523 * i915_gem_busy_ioctl(). For the corresponding synchronized
4524 * lookup see i915_gem_object_lookup_rcu().
4526 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4529 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4531 lockdep_assert_held(&obj->base.dev->struct_mutex);
4533 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4534 if (i915_gem_object_is_active(obj))
4535 i915_gem_object_set_active_reference(obj);
4537 i915_gem_object_put(obj);
4540 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4542 struct intel_engine_cs *engine;
4543 enum intel_engine_id id;
4545 for_each_engine(engine, dev_priv, id)
4546 GEM_BUG_ON(engine->last_retired_context &&
4547 !i915_gem_context_is_kernel(engine->last_retired_context));
4550 void i915_gem_sanitize(struct drm_i915_private *i915)
4553 * If we inherit context state from the BIOS or earlier occupants
4554 * of the GPU, the GPU may be in an inconsistent state when we
4555 * try to take over. The only way to remove the earlier state
4556 * is by resetting. However, resetting on earlier gen is tricky as
4557 * it may impact the display and we are uncertain about the stability
4558 * of the reset, so this could be applied to even earlier gen.
4560 if (INTEL_GEN(i915) >= 5) {
4561 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4562 WARN_ON(reset && reset != -ENODEV);
4566 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4568 struct drm_device *dev = &dev_priv->drm;
4571 intel_runtime_pm_get(dev_priv);
4572 intel_suspend_gt_powersave(dev_priv);
4574 mutex_lock(&dev->struct_mutex);
4576 /* We have to flush all the executing contexts to main memory so
4577 * that they can saved in the hibernation image. To ensure the last
4578 * context image is coherent, we have to switch away from it. That
4579 * leaves the dev_priv->kernel_context still active when
4580 * we actually suspend, and its image in memory may not match the GPU
4581 * state. Fortunately, the kernel_context is disposable and we do
4582 * not rely on its state.
4584 ret = i915_gem_switch_to_kernel_context(dev_priv);
4588 ret = i915_gem_wait_for_idle(dev_priv,
4589 I915_WAIT_INTERRUPTIBLE |
4594 assert_kernel_context_is_current(dev_priv);
4595 i915_gem_contexts_lost(dev_priv);
4596 mutex_unlock(&dev->struct_mutex);
4598 intel_guc_suspend(dev_priv);
4600 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4601 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4603 /* As the idle_work is rearming if it detects a race, play safe and
4604 * repeat the flush until it is definitely idle.
4606 while (flush_delayed_work(&dev_priv->gt.idle_work))
4609 /* Assert that we sucessfully flushed all the work and
4610 * reset the GPU back to its idle, low power state.
4612 WARN_ON(dev_priv->gt.awake);
4613 WARN_ON(!intel_engines_are_idle(dev_priv));
4616 * Neither the BIOS, ourselves or any other kernel
4617 * expects the system to be in execlists mode on startup,
4618 * so we need to reset the GPU back to legacy mode. And the only
4619 * known way to disable logical contexts is through a GPU reset.
4621 * So in order to leave the system in a known default configuration,
4622 * always reset the GPU upon unload and suspend. Afterwards we then
4623 * clean up the GEM state tracking, flushing off the requests and
4624 * leaving the system in a known idle state.
4626 * Note that is of the upmost importance that the GPU is idle and
4627 * all stray writes are flushed *before* we dismantle the backing
4628 * storage for the pinned objects.
4630 * However, since we are uncertain that resetting the GPU on older
4631 * machines is a good idea, we don't - just in case it leaves the
4632 * machine in an unusable condition.
4634 i915_gem_sanitize(dev_priv);
4638 mutex_unlock(&dev->struct_mutex);
4640 intel_runtime_pm_put(dev_priv);
4644 void i915_gem_resume(struct drm_i915_private *dev_priv)
4646 struct drm_device *dev = &dev_priv->drm;
4648 WARN_ON(dev_priv->gt.awake);
4650 mutex_lock(&dev->struct_mutex);
4651 i915_gem_restore_gtt_mappings(dev_priv);
4653 /* As we didn't flush the kernel context before suspend, we cannot
4654 * guarantee that the context image is complete. So let's just reset
4655 * it and start again.
4657 dev_priv->gt.resume(dev_priv);
4659 mutex_unlock(&dev->struct_mutex);
4662 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4664 if (INTEL_GEN(dev_priv) < 5 ||
4665 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4668 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4669 DISP_TILE_SURFACE_SWIZZLING);
4671 if (IS_GEN5(dev_priv))
4674 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4675 if (IS_GEN6(dev_priv))
4676 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4677 else if (IS_GEN7(dev_priv))
4678 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4679 else if (IS_GEN8(dev_priv))
4680 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4685 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4687 I915_WRITE(RING_CTL(base), 0);
4688 I915_WRITE(RING_HEAD(base), 0);
4689 I915_WRITE(RING_TAIL(base), 0);
4690 I915_WRITE(RING_START(base), 0);
4693 static void init_unused_rings(struct drm_i915_private *dev_priv)
4695 if (IS_I830(dev_priv)) {
4696 init_unused_ring(dev_priv, PRB1_BASE);
4697 init_unused_ring(dev_priv, SRB0_BASE);
4698 init_unused_ring(dev_priv, SRB1_BASE);
4699 init_unused_ring(dev_priv, SRB2_BASE);
4700 init_unused_ring(dev_priv, SRB3_BASE);
4701 } else if (IS_GEN2(dev_priv)) {
4702 init_unused_ring(dev_priv, SRB0_BASE);
4703 init_unused_ring(dev_priv, SRB1_BASE);
4704 } else if (IS_GEN3(dev_priv)) {
4705 init_unused_ring(dev_priv, PRB1_BASE);
4706 init_unused_ring(dev_priv, PRB2_BASE);
4710 static int __i915_gem_restart_engines(void *data)
4712 struct drm_i915_private *i915 = data;
4713 struct intel_engine_cs *engine;
4714 enum intel_engine_id id;
4717 for_each_engine(engine, i915, id) {
4718 err = engine->init_hw(engine);
4726 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4730 dev_priv->gt.last_init_time = ktime_get();
4732 /* Double layer security blanket, see i915_gem_init() */
4733 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4735 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4736 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4738 if (IS_HASWELL(dev_priv))
4739 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4740 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4742 if (HAS_PCH_NOP(dev_priv)) {
4743 if (IS_IVYBRIDGE(dev_priv)) {
4744 u32 temp = I915_READ(GEN7_MSG_CTL);
4745 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4746 I915_WRITE(GEN7_MSG_CTL, temp);
4747 } else if (INTEL_GEN(dev_priv) >= 7) {
4748 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4749 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4750 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4754 i915_gem_init_swizzling(dev_priv);
4757 * At least 830 can leave some of the unused rings
4758 * "active" (ie. head != tail) after resume which
4759 * will prevent c3 entry. Makes sure all unused rings
4762 init_unused_rings(dev_priv);
4764 BUG_ON(!dev_priv->kernel_context);
4766 ret = i915_ppgtt_init_hw(dev_priv);
4768 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4772 /* Need to do basic initialisation of all rings first: */
4773 ret = __i915_gem_restart_engines(dev_priv);
4777 intel_mocs_init_l3cc_table(dev_priv);
4779 /* We can't enable contexts until all firmware is loaded */
4780 ret = intel_uc_init_hw(dev_priv);
4785 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4789 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4791 if (INTEL_INFO(dev_priv)->gen < 6)
4794 /* TODO: make semaphores and Execlists play nicely together */
4795 if (i915.enable_execlists)
4801 /* Enable semaphores on SNB when IO remapping is off */
4802 if (IS_GEN6(dev_priv) && intel_vtd_active())
4808 int i915_gem_init(struct drm_i915_private *dev_priv)
4812 mutex_lock(&dev_priv->drm.struct_mutex);
4814 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
4816 if (!i915.enable_execlists) {
4817 dev_priv->gt.resume = intel_legacy_submission_resume;
4818 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4820 dev_priv->gt.resume = intel_lr_context_resume;
4821 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4824 /* This is just a security blanket to placate dragons.
4825 * On some systems, we very sporadically observe that the first TLBs
4826 * used by the CS may be stale, despite us poking the TLB reset. If
4827 * we hold the forcewake during initialisation these problems
4828 * just magically go away.
4830 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4832 ret = i915_gem_init_userptr(dev_priv);
4836 ret = i915_gem_init_ggtt(dev_priv);
4840 ret = i915_gem_contexts_init(dev_priv);
4844 ret = intel_engines_init(dev_priv);
4848 ret = i915_gem_init_hw(dev_priv);
4850 /* Allow engine initialisation to fail by marking the GPU as
4851 * wedged. But we only want to do this where the GPU is angry,
4852 * for all other failure, such as an allocation failure, bail.
4854 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4855 i915_gem_set_wedged(dev_priv);
4860 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4861 mutex_unlock(&dev_priv->drm.struct_mutex);
4866 void i915_gem_init_mmio(struct drm_i915_private *i915)
4868 i915_gem_sanitize(i915);
4872 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4874 struct intel_engine_cs *engine;
4875 enum intel_engine_id id;
4877 for_each_engine(engine, dev_priv, id)
4878 dev_priv->gt.cleanup_engine(engine);
4882 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4886 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4887 !IS_CHERRYVIEW(dev_priv))
4888 dev_priv->num_fence_regs = 32;
4889 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4890 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4891 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4892 dev_priv->num_fence_regs = 16;
4894 dev_priv->num_fence_regs = 8;
4896 if (intel_vgpu_active(dev_priv))
4897 dev_priv->num_fence_regs =
4898 I915_READ(vgtif_reg(avail_rs.fence_num));
4900 /* Initialize fence registers to zero */
4901 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4902 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4904 fence->i915 = dev_priv;
4906 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4908 i915_gem_restore_fences(dev_priv);
4910 i915_gem_detect_bit_6_swizzle(dev_priv);
4914 i915_gem_load_init(struct drm_i915_private *dev_priv)
4918 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4919 if (!dev_priv->objects)
4922 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4923 if (!dev_priv->vmas)
4926 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4927 SLAB_HWCACHE_ALIGN |
4928 SLAB_RECLAIM_ACCOUNT |
4929 SLAB_TYPESAFE_BY_RCU);
4930 if (!dev_priv->requests)
4933 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4934 SLAB_HWCACHE_ALIGN |
4935 SLAB_RECLAIM_ACCOUNT);
4936 if (!dev_priv->dependencies)
4939 dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
4940 if (!dev_priv->priorities)
4941 goto err_dependencies;
4943 mutex_lock(&dev_priv->drm.struct_mutex);
4944 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4945 err = i915_gem_timeline_init__global(dev_priv);
4946 mutex_unlock(&dev_priv->drm.struct_mutex);
4948 goto err_priorities;
4950 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4951 init_llist_head(&dev_priv->mm.free_list);
4952 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4953 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4954 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4955 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4956 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4957 i915_gem_retire_work_handler);
4958 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4959 i915_gem_idle_work_handler);
4960 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4961 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4963 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4965 spin_lock_init(&dev_priv->fb_tracking.lock);
4970 kmem_cache_destroy(dev_priv->priorities);
4972 kmem_cache_destroy(dev_priv->dependencies);
4974 kmem_cache_destroy(dev_priv->requests);
4976 kmem_cache_destroy(dev_priv->vmas);
4978 kmem_cache_destroy(dev_priv->objects);
4983 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4985 i915_gem_drain_freed_objects(dev_priv);
4986 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4987 WARN_ON(dev_priv->mm.object_count);
4989 mutex_lock(&dev_priv->drm.struct_mutex);
4990 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4991 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4992 mutex_unlock(&dev_priv->drm.struct_mutex);
4994 kmem_cache_destroy(dev_priv->priorities);
4995 kmem_cache_destroy(dev_priv->dependencies);
4996 kmem_cache_destroy(dev_priv->requests);
4997 kmem_cache_destroy(dev_priv->vmas);
4998 kmem_cache_destroy(dev_priv->objects);
5000 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
5004 int i915_gem_freeze(struct drm_i915_private *dev_priv)
5006 /* Discard all purgeable objects, let userspace recover those as
5007 * required after resuming.
5009 i915_gem_shrink_all(dev_priv);
5014 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
5016 struct drm_i915_gem_object *obj;
5017 struct list_head *phases[] = {
5018 &dev_priv->mm.unbound_list,
5019 &dev_priv->mm.bound_list,
5023 /* Called just before we write the hibernation image.
5025 * We need to update the domain tracking to reflect that the CPU
5026 * will be accessing all the pages to create and restore from the
5027 * hibernation, and so upon restoration those pages will be in the
5030 * To make sure the hibernation image contains the latest state,
5031 * we update that state just before writing out the image.
5033 * To try and reduce the hibernation image, we manually shrink
5034 * the objects as well, see i915_gem_freeze()
5037 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
5038 i915_gem_drain_freed_objects(dev_priv);
5040 mutex_lock(&dev_priv->drm.struct_mutex);
5041 for (p = phases; *p; p++) {
5042 list_for_each_entry(obj, *p, global_link)
5043 __start_cpu_write(obj);
5045 mutex_unlock(&dev_priv->drm.struct_mutex);
5050 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5052 struct drm_i915_file_private *file_priv = file->driver_priv;
5053 struct drm_i915_gem_request *request;
5055 /* Clean up our request list when the client is going away, so that
5056 * later retire_requests won't dereference our soon-to-be-gone
5059 spin_lock(&file_priv->mm.lock);
5060 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
5061 request->file_priv = NULL;
5062 spin_unlock(&file_priv->mm.lock);
5065 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
5067 struct drm_i915_file_private *file_priv;
5072 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5076 file->driver_priv = file_priv;
5077 file_priv->dev_priv = i915;
5078 file_priv->file = file;
5080 spin_lock_init(&file_priv->mm.lock);
5081 INIT_LIST_HEAD(&file_priv->mm.request_list);
5083 file_priv->bsd_engine = -1;
5085 ret = i915_gem_context_open(i915, file);
5093 * i915_gem_track_fb - update frontbuffer tracking
5094 * @old: current GEM buffer for the frontbuffer slots
5095 * @new: new GEM buffer for the frontbuffer slots
5096 * @frontbuffer_bits: bitmask of frontbuffer slots
5098 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5099 * from @old and setting them in @new. Both @old and @new can be NULL.
5101 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5102 struct drm_i915_gem_object *new,
5103 unsigned frontbuffer_bits)
5105 /* Control of individual bits within the mask are guarded by
5106 * the owning plane->mutex, i.e. we can never see concurrent
5107 * manipulation of individual bits. But since the bitfield as a whole
5108 * is updated using RMW, we need to use atomics in order to update
5111 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
5112 sizeof(atomic_t) * BITS_PER_BYTE);
5115 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
5116 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
5120 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
5121 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
5125 /* Allocate a new GEM object and fill it with the supplied data */
5126 struct drm_i915_gem_object *
5127 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
5128 const void *data, size_t size)
5130 struct drm_i915_gem_object *obj;
5135 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
5139 GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
5141 file = obj->base.filp;
5144 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
5146 void *pgdata, *vaddr;
5148 err = pagecache_write_begin(file, file->f_mapping,
5155 memcpy(vaddr, data, len);
5158 err = pagecache_write_end(file, file->f_mapping,
5172 i915_gem_object_put(obj);
5173 return ERR_PTR(err);
5176 struct scatterlist *
5177 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
5179 unsigned int *offset)
5181 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
5182 struct scatterlist *sg;
5183 unsigned int idx, count;
5186 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
5187 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
5189 /* As we iterate forward through the sg, we record each entry in a
5190 * radixtree for quick repeated (backwards) lookups. If we have seen
5191 * this index previously, we will have an entry for it.
5193 * Initial lookup is O(N), but this is amortized to O(1) for
5194 * sequential page access (where each new request is consecutive
5195 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5196 * i.e. O(1) with a large constant!
5198 if (n < READ_ONCE(iter->sg_idx))
5201 mutex_lock(&iter->lock);
5203 /* We prefer to reuse the last sg so that repeated lookup of this
5204 * (or the subsequent) sg are fast - comparing against the last
5205 * sg is faster than going through the radixtree.
5210 count = __sg_page_count(sg);
5212 while (idx + count <= n) {
5213 unsigned long exception, i;
5216 /* If we cannot allocate and insert this entry, or the
5217 * individual pages from this range, cancel updating the
5218 * sg_idx so that on this lookup we are forced to linearly
5219 * scan onwards, but on future lookups we will try the
5220 * insertion again (in which case we need to be careful of
5221 * the error return reporting that we have already inserted
5224 ret = radix_tree_insert(&iter->radix, idx, sg);
5225 if (ret && ret != -EEXIST)
5229 RADIX_TREE_EXCEPTIONAL_ENTRY |
5230 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5231 for (i = 1; i < count; i++) {
5232 ret = radix_tree_insert(&iter->radix, idx + i,
5234 if (ret && ret != -EEXIST)
5239 sg = ____sg_next(sg);
5240 count = __sg_page_count(sg);
5247 mutex_unlock(&iter->lock);
5249 if (unlikely(n < idx)) /* insertion completed by another thread */
5252 /* In case we failed to insert the entry into the radixtree, we need
5253 * to look beyond the current sg.
5255 while (idx + count <= n) {
5257 sg = ____sg_next(sg);
5258 count = __sg_page_count(sg);
5267 sg = radix_tree_lookup(&iter->radix, n);
5270 /* If this index is in the middle of multi-page sg entry,
5271 * the radixtree will contain an exceptional entry that points
5272 * to the start of that range. We will return the pointer to
5273 * the base page and the offset of this page within the
5277 if (unlikely(radix_tree_exception(sg))) {
5278 unsigned long base =
5279 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5281 sg = radix_tree_lookup(&iter->radix, base);
5293 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5295 struct scatterlist *sg;
5296 unsigned int offset;
5298 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5300 sg = i915_gem_object_get_sg(obj, n, &offset);
5301 return nth_page(sg_page(sg), offset);
5304 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5306 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5311 page = i915_gem_object_get_page(obj, n);
5313 set_page_dirty(page);
5319 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5322 struct scatterlist *sg;
5323 unsigned int offset;
5325 sg = i915_gem_object_get_sg(obj, n, &offset);
5326 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5329 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5330 #include "selftests/scatterlist.c"
5331 #include "selftests/mock_gem_device.c"
5332 #include "selftests/huge_gem_object.c"
5333 #include "selftests/i915_gem_object.c"
5334 #include "selftests/i915_gem_coherency.c"