2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
55 if (!obj->cache_coherent)
58 return obj->pin_display;
62 insert_mappable_node(struct i915_ggtt *ggtt,
63 struct drm_mm_node *node, u32 size)
65 memset(node, 0, sizeof(*node));
66 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
67 size, 0, I915_COLOR_UNEVICTABLE,
68 0, ggtt->mappable_end,
73 remove_mappable_node(struct drm_mm_node *node)
75 drm_mm_remove_node(node);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
82 spin_lock(&dev_priv->mm.object_stat_lock);
83 dev_priv->mm.object_count++;
84 dev_priv->mm.object_memory += size;
85 spin_unlock(&dev_priv->mm.object_stat_lock);
88 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
91 spin_lock(&dev_priv->mm.object_stat_lock);
92 dev_priv->mm.object_count--;
93 dev_priv->mm.object_memory -= size;
94 spin_unlock(&dev_priv->mm.object_stat_lock);
98 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret = wait_event_interruptible_timeout(error->reset_queue,
110 !i915_reset_backoff(error),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret < 0) {
122 int i915_mutex_lock_interruptible(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = to_i915(dev);
127 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
131 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
142 struct drm_i915_private *dev_priv = to_i915(dev);
143 struct i915_ggtt *ggtt = &dev_priv->ggtt;
144 struct drm_i915_gem_get_aperture *args = data;
145 struct i915_vma *vma;
148 pinned = ggtt->base.reserved;
149 mutex_lock(&dev->struct_mutex);
150 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
151 if (i915_vma_is_pinned(vma))
152 pinned += vma->node.size;
153 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
154 if (i915_vma_is_pinned(vma))
155 pinned += vma->node.size;
156 mutex_unlock(&dev->struct_mutex);
158 args->aper_size = ggtt->base.total;
159 args->aper_available_size = args->aper_size - pinned;
164 static struct sg_table *
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
167 struct address_space *mapping = obj->base.filp->f_mapping;
168 drm_dma_handle_t *phys;
170 struct scatterlist *sg;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
175 return ERR_PTR(-EINVAL);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys = drm_pci_alloc(obj->base.dev,
183 roundup_pow_of_two(obj->base.size));
185 return ERR_PTR(-ENOMEM);
188 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
192 page = shmem_read_mapping_page(mapping, i);
198 src = kmap_atomic(page);
199 memcpy(vaddr, src, PAGE_SIZE);
200 drm_clflush_virt_range(vaddr, PAGE_SIZE);
207 i915_gem_chipset_flush(to_i915(obj->base.dev));
209 st = kmalloc(sizeof(*st), GFP_KERNEL);
211 st = ERR_PTR(-ENOMEM);
215 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
217 st = ERR_PTR(-ENOMEM);
223 sg->length = obj->base.size;
225 sg_dma_address(sg) = phys->busaddr;
226 sg_dma_len(sg) = obj->base.size;
228 obj->phys_handle = phys;
232 drm_pci_free(obj->base.dev, phys);
236 static void __start_cpu_write(struct drm_i915_gem_object *obj)
238 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
239 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
240 if (cpu_write_needs_clflush(obj))
241 obj->cache_dirty = true;
245 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
246 struct sg_table *pages,
249 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251 if (obj->mm.madv == I915_MADV_DONTNEED)
252 obj->mm.dirty = false;
255 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
256 !obj->cache_coherent)
257 drm_clflush_sg(pages);
259 __start_cpu_write(obj);
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
264 struct sg_table *pages)
266 __i915_gem_object_release_shmem(obj, pages, false);
269 struct address_space *mapping = obj->base.filp->f_mapping;
270 char *vaddr = obj->phys_handle->vaddr;
273 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
277 page = shmem_read_mapping_page(mapping, i);
281 dst = kmap_atomic(page);
282 drm_clflush_virt_range(vaddr, PAGE_SIZE);
283 memcpy(dst, vaddr, PAGE_SIZE);
286 set_page_dirty(page);
287 if (obj->mm.madv == I915_MADV_WILLNEED)
288 mark_page_accessed(page);
292 obj->mm.dirty = false;
295 sg_free_table(pages);
298 drm_pci_free(obj->base.dev, obj->phys_handle);
302 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
304 i915_gem_object_unpin_pages(obj);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
308 .get_pages = i915_gem_object_get_pages_phys,
309 .put_pages = i915_gem_object_put_pages_phys,
310 .release = i915_gem_object_release_phys,
313 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
315 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
317 struct i915_vma *vma;
318 LIST_HEAD(still_in_list);
321 lockdep_assert_held(&obj->base.dev->struct_mutex);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret = i915_gem_object_wait(obj,
329 I915_WAIT_INTERRUPTIBLE |
332 MAX_SCHEDULE_TIMEOUT,
337 i915_gem_retire_requests(to_i915(obj->base.dev));
339 while ((vma = list_first_entry_or_null(&obj->vma_list,
342 list_move_tail(&vma->obj_link, &still_in_list);
343 ret = i915_vma_unbind(vma);
347 list_splice(&still_in_list, &obj->vma_list);
353 i915_gem_object_wait_fence(struct dma_fence *fence,
356 struct intel_rps_client *rps)
358 struct drm_i915_gem_request *rq;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
365 if (!dma_fence_is_i915(fence))
366 return dma_fence_wait_timeout(fence,
367 flags & I915_WAIT_INTERRUPTIBLE,
370 rq = to_request(fence);
371 if (i915_gem_request_completed(rq))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq->i915) >= 6)
391 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
396 timeout = i915_wait_request(rq, flags, timeout);
399 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
400 i915_gem_request_retire_upto(rq);
402 if (rps && i915_gem_request_global_seqno(rq) == intel_engine_last_submit(rq->engine)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
413 spin_lock(&rq->i915->rps.client_lock);
414 list_del_init(&rps->link);
415 spin_unlock(&rq->i915->rps.client_lock);
422 i915_gem_object_wait_reservation(struct reservation_object *resv,
425 struct intel_rps_client *rps)
427 unsigned int seq = __read_seqcount_begin(&resv->seq);
428 struct dma_fence *excl;
429 bool prune_fences = false;
431 if (flags & I915_WAIT_ALL) {
432 struct dma_fence **shared;
433 unsigned int count, i;
436 ret = reservation_object_get_fences_rcu(resv,
437 &excl, &count, &shared);
441 for (i = 0; i < count; i++) {
442 timeout = i915_gem_object_wait_fence(shared[i],
448 dma_fence_put(shared[i]);
451 for (; i < count; i++)
452 dma_fence_put(shared[i]);
455 prune_fences = count && timeout >= 0;
457 excl = reservation_object_get_excl_rcu(resv);
460 if (excl && timeout >= 0) {
461 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
462 prune_fences = timeout >= 0;
467 /* Oportunistically prune the fences iff we know they have *all* been
468 * signaled and that the reservation object has not been changed (i.e.
469 * no new fences have been added).
471 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
472 if (reservation_object_trylock(resv)) {
473 if (!__read_seqcount_retry(&resv->seq, seq))
474 reservation_object_add_excl_fence(resv, NULL);
475 reservation_object_unlock(resv);
482 static void __fence_set_priority(struct dma_fence *fence, int prio)
484 struct drm_i915_gem_request *rq;
485 struct intel_engine_cs *engine;
487 if (!dma_fence_is_i915(fence))
490 rq = to_request(fence);
492 if (!engine->schedule)
495 engine->schedule(rq, prio);
498 static void fence_set_priority(struct dma_fence *fence, int prio)
500 /* Recurse once into a fence-array */
501 if (dma_fence_is_array(fence)) {
502 struct dma_fence_array *array = to_dma_fence_array(fence);
505 for (i = 0; i < array->num_fences; i++)
506 __fence_set_priority(array->fences[i], prio);
508 __fence_set_priority(fence, prio);
513 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
517 struct dma_fence *excl;
519 if (flags & I915_WAIT_ALL) {
520 struct dma_fence **shared;
521 unsigned int count, i;
524 ret = reservation_object_get_fences_rcu(obj->resv,
525 &excl, &count, &shared);
529 for (i = 0; i < count; i++) {
530 fence_set_priority(shared[i], prio);
531 dma_fence_put(shared[i]);
536 excl = reservation_object_get_excl_rcu(obj->resv);
540 fence_set_priority(excl, prio);
547 * Waits for rendering to the object to be completed
548 * @obj: i915 gem object
549 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
550 * @timeout: how long to wait
551 * @rps: client (user process) to charge for any waitboosting
554 i915_gem_object_wait(struct drm_i915_gem_object *obj,
557 struct intel_rps_client *rps)
560 #if IS_ENABLED(CONFIG_LOCKDEP)
561 GEM_BUG_ON(debug_locks &&
562 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
563 !!(flags & I915_WAIT_LOCKED));
565 GEM_BUG_ON(timeout < 0);
567 timeout = i915_gem_object_wait_reservation(obj->resv,
570 return timeout < 0 ? timeout : 0;
573 static struct intel_rps_client *to_rps_client(struct drm_file *file)
575 struct drm_i915_file_private *fpriv = file->driver_priv;
581 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
586 if (align > obj->base.size)
589 if (obj->ops == &i915_gem_phys_ops)
592 if (obj->mm.madv != I915_MADV_WILLNEED)
595 if (obj->base.filp == NULL)
598 ret = i915_gem_object_unbind(obj);
602 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
606 GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
607 obj->ops = &i915_gem_phys_ops;
609 ret = i915_gem_object_pin_pages(obj);
616 obj->ops = &i915_gem_object_ops;
621 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
622 struct drm_i915_gem_pwrite *args,
623 struct drm_file *file)
625 void *vaddr = obj->phys_handle->vaddr + args->offset;
626 char __user *user_data = u64_to_user_ptr(args->data_ptr);
628 /* We manually control the domain here and pretend that it
629 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
631 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
632 if (copy_from_user(vaddr, user_data, args->size))
635 drm_clflush_virt_range(vaddr, args->size);
636 i915_gem_chipset_flush(to_i915(obj->base.dev));
638 intel_fb_obj_flush(obj, ORIGIN_CPU);
642 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
644 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
647 void i915_gem_object_free(struct drm_i915_gem_object *obj)
649 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
650 kmem_cache_free(dev_priv->objects, obj);
654 i915_gem_create(struct drm_file *file,
655 struct drm_i915_private *dev_priv,
659 struct drm_i915_gem_object *obj;
663 size = roundup(size, PAGE_SIZE);
667 /* Allocate the new object */
668 obj = i915_gem_object_create(dev_priv, size);
672 ret = drm_gem_handle_create(file, &obj->base, &handle);
673 /* drop reference from allocate - handle holds it now */
674 i915_gem_object_put(obj);
683 i915_gem_dumb_create(struct drm_file *file,
684 struct drm_device *dev,
685 struct drm_mode_create_dumb *args)
687 /* have to work out size/pitch and return them */
688 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
689 args->size = args->pitch * args->height;
690 return i915_gem_create(file, to_i915(dev),
691 args->size, &args->handle);
694 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
696 return !(obj->cache_level == I915_CACHE_NONE ||
697 obj->cache_level == I915_CACHE_WT);
701 * Creates a new mm object and returns a handle to it.
702 * @dev: drm device pointer
703 * @data: ioctl data blob
704 * @file: drm file pointer
707 i915_gem_create_ioctl(struct drm_device *dev, void *data,
708 struct drm_file *file)
710 struct drm_i915_private *dev_priv = to_i915(dev);
711 struct drm_i915_gem_create *args = data;
713 i915_gem_flush_free_objects(dev_priv);
715 return i915_gem_create(file, dev_priv,
716 args->size, &args->handle);
719 static inline enum fb_op_origin
720 fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
722 return (domain == I915_GEM_DOMAIN_GTT ?
723 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
727 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
729 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
731 if (!(obj->base.write_domain & flush_domains))
734 /* No actual flushing is required for the GTT write domain. Writes
735 * to it "immediately" go to main memory as far as we know, so there's
736 * no chipset flush. It also doesn't land in render cache.
738 * However, we do have to enforce the order so that all writes through
739 * the GTT land before any writes to the device, such as updates to
742 * We also have to wait a bit for the writes to land from the GTT.
743 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
744 * timing. This issue has only been observed when switching quickly
745 * between GTT writes and CPU reads from inside the kernel on recent hw,
746 * and it appears to only affect discrete GTT blocks (i.e. on LLC
747 * system agents we cannot reproduce this behaviour).
751 switch (obj->base.write_domain) {
752 case I915_GEM_DOMAIN_GTT:
753 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
754 if (intel_runtime_pm_get_if_in_use(dev_priv)) {
755 spin_lock_irq(&dev_priv->uncore.lock);
756 POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
757 spin_unlock_irq(&dev_priv->uncore.lock);
758 intel_runtime_pm_put(dev_priv);
762 intel_fb_obj_flush(obj,
763 fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
766 case I915_GEM_DOMAIN_CPU:
767 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
770 case I915_GEM_DOMAIN_RENDER:
771 if (gpu_write_needs_clflush(obj))
772 obj->cache_dirty = true;
776 obj->base.write_domain = 0;
780 __copy_to_user_swizzled(char __user *cpu_vaddr,
781 const char *gpu_vaddr, int gpu_offset,
784 int ret, cpu_offset = 0;
787 int cacheline_end = ALIGN(gpu_offset + 1, 64);
788 int this_length = min(cacheline_end - gpu_offset, length);
789 int swizzled_gpu_offset = gpu_offset ^ 64;
791 ret = __copy_to_user(cpu_vaddr + cpu_offset,
792 gpu_vaddr + swizzled_gpu_offset,
797 cpu_offset += this_length;
798 gpu_offset += this_length;
799 length -= this_length;
806 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
807 const char __user *cpu_vaddr,
810 int ret, cpu_offset = 0;
813 int cacheline_end = ALIGN(gpu_offset + 1, 64);
814 int this_length = min(cacheline_end - gpu_offset, length);
815 int swizzled_gpu_offset = gpu_offset ^ 64;
817 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
818 cpu_vaddr + cpu_offset,
823 cpu_offset += this_length;
824 gpu_offset += this_length;
825 length -= this_length;
832 * Pins the specified object's pages and synchronizes the object with
833 * GPU accesses. Sets needs_clflush to non-zero if the caller should
834 * flush the object from the CPU cache.
836 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
837 unsigned int *needs_clflush)
841 lockdep_assert_held(&obj->base.dev->struct_mutex);
844 if (!i915_gem_object_has_struct_page(obj))
847 ret = i915_gem_object_wait(obj,
848 I915_WAIT_INTERRUPTIBLE |
850 MAX_SCHEDULE_TIMEOUT,
855 ret = i915_gem_object_pin_pages(obj);
859 if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
860 ret = i915_gem_object_set_to_cpu_domain(obj, false);
867 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
869 /* If we're not in the cpu read domain, set ourself into the gtt
870 * read domain and manually flush cachelines (if required). This
871 * optimizes for the case when the gpu will dirty the data
872 * anyway again before the next pread happens.
874 if (!obj->cache_dirty &&
875 !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
876 *needs_clflush = CLFLUSH_BEFORE;
879 /* return with the pages pinned */
883 i915_gem_object_unpin_pages(obj);
887 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
888 unsigned int *needs_clflush)
892 lockdep_assert_held(&obj->base.dev->struct_mutex);
895 if (!i915_gem_object_has_struct_page(obj))
898 ret = i915_gem_object_wait(obj,
899 I915_WAIT_INTERRUPTIBLE |
902 MAX_SCHEDULE_TIMEOUT,
907 ret = i915_gem_object_pin_pages(obj);
911 if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
912 ret = i915_gem_object_set_to_cpu_domain(obj, true);
919 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
921 /* If we're not in the cpu write domain, set ourself into the
922 * gtt write domain and manually flush cachelines (as required).
923 * This optimizes for the case when the gpu will use the data
924 * right away and we therefore have to clflush anyway.
926 if (!obj->cache_dirty) {
927 *needs_clflush |= CLFLUSH_AFTER;
930 * Same trick applies to invalidate partially written
931 * cachelines read before writing.
933 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
934 *needs_clflush |= CLFLUSH_BEFORE;
938 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
939 obj->mm.dirty = true;
940 /* return with the pages pinned */
944 i915_gem_object_unpin_pages(obj);
949 shmem_clflush_swizzled_range(char *addr, unsigned long length,
952 if (unlikely(swizzled)) {
953 unsigned long start = (unsigned long) addr;
954 unsigned long end = (unsigned long) addr + length;
956 /* For swizzling simply ensure that we always flush both
957 * channels. Lame, but simple and it works. Swizzled
958 * pwrite/pread is far from a hotpath - current userspace
959 * doesn't use it at all. */
960 start = round_down(start, 128);
961 end = round_up(end, 128);
963 drm_clflush_virt_range((void *)start, end - start);
965 drm_clflush_virt_range(addr, length);
970 /* Only difference to the fast-path function is that this can handle bit17
971 * and uses non-atomic copy and kmap functions. */
973 shmem_pread_slow(struct page *page, int offset, int length,
974 char __user *user_data,
975 bool page_do_bit17_swizzling, bool needs_clflush)
982 shmem_clflush_swizzled_range(vaddr + offset, length,
983 page_do_bit17_swizzling);
985 if (page_do_bit17_swizzling)
986 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
988 ret = __copy_to_user(user_data, vaddr + offset, length);
991 return ret ? - EFAULT : 0;
995 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
996 bool page_do_bit17_swizzling, bool needs_clflush)
1001 if (!page_do_bit17_swizzling) {
1002 char *vaddr = kmap_atomic(page);
1005 drm_clflush_virt_range(vaddr + offset, length);
1006 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1007 kunmap_atomic(vaddr);
1012 return shmem_pread_slow(page, offset, length, user_data,
1013 page_do_bit17_swizzling, needs_clflush);
1017 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
1018 struct drm_i915_gem_pread *args)
1020 char __user *user_data;
1022 unsigned int obj_do_bit17_swizzling;
1023 unsigned int needs_clflush;
1024 unsigned int idx, offset;
1027 obj_do_bit17_swizzling = 0;
1028 if (i915_gem_object_needs_bit17_swizzle(obj))
1029 obj_do_bit17_swizzling = BIT(17);
1031 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
1035 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
1036 mutex_unlock(&obj->base.dev->struct_mutex);
1040 remain = args->size;
1041 user_data = u64_to_user_ptr(args->data_ptr);
1042 offset = offset_in_page(args->offset);
1043 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1044 struct page *page = i915_gem_object_get_page(obj, idx);
1048 if (offset + length > PAGE_SIZE)
1049 length = PAGE_SIZE - offset;
1051 ret = shmem_pread(page, offset, length, user_data,
1052 page_to_phys(page) & obj_do_bit17_swizzling,
1058 user_data += length;
1062 i915_gem_obj_finish_shmem_access(obj);
1067 gtt_user_read(struct io_mapping *mapping,
1068 loff_t base, int offset,
1069 char __user *user_data, int length)
1072 unsigned long unwritten;
1074 /* We can use the cpu mem copy function because this is X86. */
1075 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1076 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1077 io_mapping_unmap_atomic(vaddr);
1079 vaddr = (void __force *)
1080 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1081 unwritten = copy_to_user(user_data, vaddr + offset, length);
1082 io_mapping_unmap(vaddr);
1088 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1089 const struct drm_i915_gem_pread *args)
1091 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1092 struct i915_ggtt *ggtt = &i915->ggtt;
1093 struct drm_mm_node node;
1094 struct i915_vma *vma;
1095 void __user *user_data;
1099 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1103 intel_runtime_pm_get(i915);
1104 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1105 PIN_MAPPABLE | PIN_NONBLOCK);
1107 node.start = i915_ggtt_offset(vma);
1108 node.allocated = false;
1109 ret = i915_vma_put_fence(vma);
1111 i915_vma_unpin(vma);
1116 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1119 GEM_BUG_ON(!node.allocated);
1122 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1126 mutex_unlock(&i915->drm.struct_mutex);
1128 user_data = u64_to_user_ptr(args->data_ptr);
1129 remain = args->size;
1130 offset = args->offset;
1132 while (remain > 0) {
1133 /* Operation in this page
1135 * page_base = page offset within aperture
1136 * page_offset = offset within page
1137 * page_length = bytes to copy for this page
1139 u32 page_base = node.start;
1140 unsigned page_offset = offset_in_page(offset);
1141 unsigned page_length = PAGE_SIZE - page_offset;
1142 page_length = remain < page_length ? remain : page_length;
1143 if (node.allocated) {
1145 ggtt->base.insert_page(&ggtt->base,
1146 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1147 node.start, I915_CACHE_NONE, 0);
1150 page_base += offset & PAGE_MASK;
1153 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1154 user_data, page_length)) {
1159 remain -= page_length;
1160 user_data += page_length;
1161 offset += page_length;
1164 mutex_lock(&i915->drm.struct_mutex);
1166 if (node.allocated) {
1168 ggtt->base.clear_range(&ggtt->base,
1169 node.start, node.size);
1170 remove_mappable_node(&node);
1172 i915_vma_unpin(vma);
1175 intel_runtime_pm_put(i915);
1176 mutex_unlock(&i915->drm.struct_mutex);
1182 * Reads data from the object referenced by handle.
1183 * @dev: drm device pointer
1184 * @data: ioctl data blob
1185 * @file: drm file pointer
1187 * On error, the contents of *data are undefined.
1190 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1191 struct drm_file *file)
1193 struct drm_i915_gem_pread *args = data;
1194 struct drm_i915_gem_object *obj;
1197 if (args->size == 0)
1200 if (!access_ok(VERIFY_WRITE,
1201 u64_to_user_ptr(args->data_ptr),
1205 obj = i915_gem_object_lookup(file, args->handle);
1209 /* Bounds check source. */
1210 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1215 trace_i915_gem_object_pread(obj, args->offset, args->size);
1217 ret = i915_gem_object_wait(obj,
1218 I915_WAIT_INTERRUPTIBLE,
1219 MAX_SCHEDULE_TIMEOUT,
1220 to_rps_client(file));
1224 ret = i915_gem_object_pin_pages(obj);
1228 ret = i915_gem_shmem_pread(obj, args);
1229 if (ret == -EFAULT || ret == -ENODEV)
1230 ret = i915_gem_gtt_pread(obj, args);
1232 i915_gem_object_unpin_pages(obj);
1234 i915_gem_object_put(obj);
1238 /* This is the fast write path which cannot handle
1239 * page faults in the source data
1243 ggtt_write(struct io_mapping *mapping,
1244 loff_t base, int offset,
1245 char __user *user_data, int length)
1248 unsigned long unwritten;
1250 /* We can use the cpu mem copy function because this is X86. */
1251 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1252 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1254 io_mapping_unmap_atomic(vaddr);
1256 vaddr = (void __force *)
1257 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1258 unwritten = copy_from_user(vaddr + offset, user_data, length);
1259 io_mapping_unmap(vaddr);
1266 * This is the fast pwrite path, where we copy the data directly from the
1267 * user into the GTT, uncached.
1268 * @obj: i915 GEM object
1269 * @args: pwrite arguments structure
1272 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1273 const struct drm_i915_gem_pwrite *args)
1275 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1276 struct i915_ggtt *ggtt = &i915->ggtt;
1277 struct drm_mm_node node;
1278 struct i915_vma *vma;
1280 void __user *user_data;
1283 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1287 intel_runtime_pm_get(i915);
1288 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1289 PIN_MAPPABLE | PIN_NONBLOCK);
1291 node.start = i915_ggtt_offset(vma);
1292 node.allocated = false;
1293 ret = i915_vma_put_fence(vma);
1295 i915_vma_unpin(vma);
1300 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1303 GEM_BUG_ON(!node.allocated);
1306 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1310 mutex_unlock(&i915->drm.struct_mutex);
1312 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1314 user_data = u64_to_user_ptr(args->data_ptr);
1315 offset = args->offset;
1316 remain = args->size;
1318 /* Operation in this page
1320 * page_base = page offset within aperture
1321 * page_offset = offset within page
1322 * page_length = bytes to copy for this page
1324 u32 page_base = node.start;
1325 unsigned int page_offset = offset_in_page(offset);
1326 unsigned int page_length = PAGE_SIZE - page_offset;
1327 page_length = remain < page_length ? remain : page_length;
1328 if (node.allocated) {
1329 wmb(); /* flush the write before we modify the GGTT */
1330 ggtt->base.insert_page(&ggtt->base,
1331 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1332 node.start, I915_CACHE_NONE, 0);
1333 wmb(); /* flush modifications to the GGTT (insert_page) */
1335 page_base += offset & PAGE_MASK;
1337 /* If we get a fault while copying data, then (presumably) our
1338 * source page isn't available. Return the error and we'll
1339 * retry in the slow path.
1340 * If the object is non-shmem backed, we retry again with the
1341 * path that handles page fault.
1343 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1344 user_data, page_length)) {
1349 remain -= page_length;
1350 user_data += page_length;
1351 offset += page_length;
1353 intel_fb_obj_flush(obj, ORIGIN_CPU);
1355 mutex_lock(&i915->drm.struct_mutex);
1357 if (node.allocated) {
1359 ggtt->base.clear_range(&ggtt->base,
1360 node.start, node.size);
1361 remove_mappable_node(&node);
1363 i915_vma_unpin(vma);
1366 intel_runtime_pm_put(i915);
1367 mutex_unlock(&i915->drm.struct_mutex);
1372 shmem_pwrite_slow(struct page *page, int offset, int length,
1373 char __user *user_data,
1374 bool page_do_bit17_swizzling,
1375 bool needs_clflush_before,
1376 bool needs_clflush_after)
1382 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1383 shmem_clflush_swizzled_range(vaddr + offset, length,
1384 page_do_bit17_swizzling);
1385 if (page_do_bit17_swizzling)
1386 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1389 ret = __copy_from_user(vaddr + offset, user_data, length);
1390 if (needs_clflush_after)
1391 shmem_clflush_swizzled_range(vaddr + offset, length,
1392 page_do_bit17_swizzling);
1395 return ret ? -EFAULT : 0;
1398 /* Per-page copy function for the shmem pwrite fastpath.
1399 * Flushes invalid cachelines before writing to the target if
1400 * needs_clflush_before is set and flushes out any written cachelines after
1401 * writing if needs_clflush is set.
1404 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1405 bool page_do_bit17_swizzling,
1406 bool needs_clflush_before,
1407 bool needs_clflush_after)
1412 if (!page_do_bit17_swizzling) {
1413 char *vaddr = kmap_atomic(page);
1415 if (needs_clflush_before)
1416 drm_clflush_virt_range(vaddr + offset, len);
1417 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1418 if (needs_clflush_after)
1419 drm_clflush_virt_range(vaddr + offset, len);
1421 kunmap_atomic(vaddr);
1426 return shmem_pwrite_slow(page, offset, len, user_data,
1427 page_do_bit17_swizzling,
1428 needs_clflush_before,
1429 needs_clflush_after);
1433 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1434 const struct drm_i915_gem_pwrite *args)
1436 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1437 void __user *user_data;
1439 unsigned int obj_do_bit17_swizzling;
1440 unsigned int partial_cacheline_write;
1441 unsigned int needs_clflush;
1442 unsigned int offset, idx;
1445 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1449 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1450 mutex_unlock(&i915->drm.struct_mutex);
1454 obj_do_bit17_swizzling = 0;
1455 if (i915_gem_object_needs_bit17_swizzle(obj))
1456 obj_do_bit17_swizzling = BIT(17);
1458 /* If we don't overwrite a cacheline completely we need to be
1459 * careful to have up-to-date data by first clflushing. Don't
1460 * overcomplicate things and flush the entire patch.
1462 partial_cacheline_write = 0;
1463 if (needs_clflush & CLFLUSH_BEFORE)
1464 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1466 user_data = u64_to_user_ptr(args->data_ptr);
1467 remain = args->size;
1468 offset = offset_in_page(args->offset);
1469 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1470 struct page *page = i915_gem_object_get_page(obj, idx);
1474 if (offset + length > PAGE_SIZE)
1475 length = PAGE_SIZE - offset;
1477 ret = shmem_pwrite(page, offset, length, user_data,
1478 page_to_phys(page) & obj_do_bit17_swizzling,
1479 (offset | length) & partial_cacheline_write,
1480 needs_clflush & CLFLUSH_AFTER);
1485 user_data += length;
1489 intel_fb_obj_flush(obj, ORIGIN_CPU);
1490 i915_gem_obj_finish_shmem_access(obj);
1495 * Writes data to the object referenced by handle.
1497 * @data: ioctl data blob
1500 * On error, the contents of the buffer that were to be modified are undefined.
1503 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1504 struct drm_file *file)
1506 struct drm_i915_gem_pwrite *args = data;
1507 struct drm_i915_gem_object *obj;
1510 if (args->size == 0)
1513 if (!access_ok(VERIFY_READ,
1514 u64_to_user_ptr(args->data_ptr),
1518 obj = i915_gem_object_lookup(file, args->handle);
1522 /* Bounds check destination. */
1523 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1528 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1531 if (obj->ops->pwrite)
1532 ret = obj->ops->pwrite(obj, args);
1536 ret = i915_gem_object_wait(obj,
1537 I915_WAIT_INTERRUPTIBLE |
1539 MAX_SCHEDULE_TIMEOUT,
1540 to_rps_client(file));
1544 ret = i915_gem_object_pin_pages(obj);
1549 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1550 * it would end up going through the fenced access, and we'll get
1551 * different detiling behavior between reading and writing.
1552 * pread/pwrite currently are reading and writing from the CPU
1553 * perspective, requiring manual detiling by the client.
1555 if (!i915_gem_object_has_struct_page(obj) ||
1556 cpu_write_needs_clflush(obj))
1557 /* Note that the gtt paths might fail with non-page-backed user
1558 * pointers (e.g. gtt mappings when moving data between
1559 * textures). Fallback to the shmem path in that case.
1561 ret = i915_gem_gtt_pwrite_fast(obj, args);
1563 if (ret == -EFAULT || ret == -ENOSPC) {
1564 if (obj->phys_handle)
1565 ret = i915_gem_phys_pwrite(obj, args, file);
1567 ret = i915_gem_shmem_pwrite(obj, args);
1570 i915_gem_object_unpin_pages(obj);
1572 i915_gem_object_put(obj);
1576 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1578 struct drm_i915_private *i915;
1579 struct list_head *list;
1580 struct i915_vma *vma;
1582 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1583 if (!i915_vma_is_ggtt(vma))
1586 if (i915_vma_is_active(vma))
1589 if (!drm_mm_node_allocated(&vma->node))
1592 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1595 i915 = to_i915(obj->base.dev);
1596 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1597 list_move_tail(&obj->global_link, list);
1601 * Called when user space prepares to use an object with the CPU, either
1602 * through the mmap ioctl's mapping or a GTT mapping.
1604 * @data: ioctl data blob
1608 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1609 struct drm_file *file)
1611 struct drm_i915_gem_set_domain *args = data;
1612 struct drm_i915_gem_object *obj;
1613 uint32_t read_domains = args->read_domains;
1614 uint32_t write_domain = args->write_domain;
1617 /* Only handle setting domains to types used by the CPU. */
1618 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1621 /* Having something in the write domain implies it's in the read
1622 * domain, and only that read domain. Enforce that in the request.
1624 if (write_domain != 0 && read_domains != write_domain)
1627 obj = i915_gem_object_lookup(file, args->handle);
1631 /* Try to flush the object off the GPU without holding the lock.
1632 * We will repeat the flush holding the lock in the normal manner
1633 * to catch cases where we are gazumped.
1635 err = i915_gem_object_wait(obj,
1636 I915_WAIT_INTERRUPTIBLE |
1637 (write_domain ? I915_WAIT_ALL : 0),
1638 MAX_SCHEDULE_TIMEOUT,
1639 to_rps_client(file));
1643 /* Flush and acquire obj->pages so that we are coherent through
1644 * direct access in memory with previous cached writes through
1645 * shmemfs and that our cache domain tracking remains valid.
1646 * For example, if the obj->filp was moved to swap without us
1647 * being notified and releasing the pages, we would mistakenly
1648 * continue to assume that the obj remained out of the CPU cached
1651 err = i915_gem_object_pin_pages(obj);
1655 err = i915_mutex_lock_interruptible(dev);
1659 if (read_domains & I915_GEM_DOMAIN_WC)
1660 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
1661 else if (read_domains & I915_GEM_DOMAIN_GTT)
1662 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
1664 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
1666 /* And bump the LRU for this access */
1667 i915_gem_object_bump_inactive_ggtt(obj);
1669 mutex_unlock(&dev->struct_mutex);
1671 if (write_domain != 0)
1672 intel_fb_obj_invalidate(obj,
1673 fb_write_origin(obj, write_domain));
1676 i915_gem_object_unpin_pages(obj);
1678 i915_gem_object_put(obj);
1683 * Called when user space has done writes to this buffer
1685 * @data: ioctl data blob
1689 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1690 struct drm_file *file)
1692 struct drm_i915_gem_sw_finish *args = data;
1693 struct drm_i915_gem_object *obj;
1695 obj = i915_gem_object_lookup(file, args->handle);
1699 /* Pinned buffers may be scanout, so flush the cache */
1700 i915_gem_object_flush_if_display(obj);
1701 i915_gem_object_put(obj);
1707 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1710 * @data: ioctl data blob
1713 * While the mapping holds a reference on the contents of the object, it doesn't
1714 * imply a ref on the object itself.
1718 * DRM driver writers who look a this function as an example for how to do GEM
1719 * mmap support, please don't implement mmap support like here. The modern way
1720 * to implement DRM mmap support is with an mmap offset ioctl (like
1721 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1722 * That way debug tooling like valgrind will understand what's going on, hiding
1723 * the mmap call in a driver private ioctl will break that. The i915 driver only
1724 * does cpu mmaps this way because we didn't know better.
1727 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1728 struct drm_file *file)
1730 struct drm_i915_gem_mmap *args = data;
1731 struct drm_i915_gem_object *obj;
1734 if (args->flags & ~(I915_MMAP_WC))
1737 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1740 obj = i915_gem_object_lookup(file, args->handle);
1744 /* prime objects have no backing filp to GEM mmap
1747 if (!obj->base.filp) {
1748 i915_gem_object_put(obj);
1752 addr = vm_mmap(obj->base.filp, 0, args->size,
1753 PROT_READ | PROT_WRITE, MAP_SHARED,
1755 if (args->flags & I915_MMAP_WC) {
1756 struct mm_struct *mm = current->mm;
1757 struct vm_area_struct *vma;
1759 if (down_write_killable(&mm->mmap_sem)) {
1760 i915_gem_object_put(obj);
1763 vma = find_vma(mm, addr);
1766 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1769 up_write(&mm->mmap_sem);
1771 /* This may race, but that's ok, it only gets set */
1772 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1774 i915_gem_object_put(obj);
1775 if (IS_ERR((void *)addr))
1778 args->addr_ptr = (uint64_t) addr;
1783 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1785 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1789 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1791 * A history of the GTT mmap interface:
1793 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1794 * aligned and suitable for fencing, and still fit into the available
1795 * mappable space left by the pinned display objects. A classic problem
1796 * we called the page-fault-of-doom where we would ping-pong between
1797 * two objects that could not fit inside the GTT and so the memcpy
1798 * would page one object in at the expense of the other between every
1801 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1802 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1803 * object is too large for the available space (or simply too large
1804 * for the mappable aperture!), a view is created instead and faulted
1805 * into userspace. (This view is aligned and sized appropriately for
1808 * 2 - Recognise WC as a separate cache domain so that we can flush the
1809 * delayed writes via GTT before performing direct access via WC.
1813 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1814 * hangs on some architectures, corruption on others. An attempt to service
1815 * a GTT page fault from a snoopable object will generate a SIGBUS.
1817 * * the object must be able to fit into RAM (physical memory, though no
1818 * limited to the mappable aperture).
1823 * * a new GTT page fault will synchronize rendering from the GPU and flush
1824 * all data to system memory. Subsequent access will not be synchronized.
1826 * * all mappings are revoked on runtime device suspend.
1828 * * there are only 8, 16 or 32 fence registers to share between all users
1829 * (older machines require fence register for display and blitter access
1830 * as well). Contention of the fence registers will cause the previous users
1831 * to be unmapped and any new access will generate new page faults.
1833 * * running out of memory while servicing a fault may generate a SIGBUS,
1834 * rather than the expected SIGSEGV.
1836 int i915_gem_mmap_gtt_version(void)
1841 static inline struct i915_ggtt_view
1842 compute_partial_view(struct drm_i915_gem_object *obj,
1843 pgoff_t page_offset,
1846 struct i915_ggtt_view view;
1848 if (i915_gem_object_is_tiled(obj))
1849 chunk = roundup(chunk, tile_row_pages(obj));
1851 view.type = I915_GGTT_VIEW_PARTIAL;
1852 view.partial.offset = rounddown(page_offset, chunk);
1854 min_t(unsigned int, chunk,
1855 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1857 /* If the partial covers the entire object, just create a normal VMA. */
1858 if (chunk >= obj->base.size >> PAGE_SHIFT)
1859 view.type = I915_GGTT_VIEW_NORMAL;
1865 * i915_gem_fault - fault a page into the GTT
1868 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1869 * from userspace. The fault handler takes care of binding the object to
1870 * the GTT (if needed), allocating and programming a fence register (again,
1871 * only if needed based on whether the old reg is still valid or the object
1872 * is tiled) and inserting a new PTE into the faulting process.
1874 * Note that the faulting process may involve evicting existing objects
1875 * from the GTT and/or fence registers to make room. So performance may
1876 * suffer if the GTT working set is large or there are few fence registers
1879 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1880 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1882 int i915_gem_fault(struct vm_fault *vmf)
1884 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1885 struct vm_area_struct *area = vmf->vma;
1886 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1887 struct drm_device *dev = obj->base.dev;
1888 struct drm_i915_private *dev_priv = to_i915(dev);
1889 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1890 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1891 struct i915_vma *vma;
1892 pgoff_t page_offset;
1896 /* We don't use vmf->pgoff since that has the fake offset */
1897 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1899 trace_i915_gem_object_fault(obj, page_offset, true, write);
1901 /* Try to flush the object off the GPU first without holding the lock.
1902 * Upon acquiring the lock, we will perform our sanity checks and then
1903 * repeat the flush holding the lock in the normal manner to catch cases
1904 * where we are gazumped.
1906 ret = i915_gem_object_wait(obj,
1907 I915_WAIT_INTERRUPTIBLE,
1908 MAX_SCHEDULE_TIMEOUT,
1913 ret = i915_gem_object_pin_pages(obj);
1917 intel_runtime_pm_get(dev_priv);
1919 ret = i915_mutex_lock_interruptible(dev);
1923 /* Access to snoopable pages through the GTT is incoherent. */
1924 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1929 /* If the object is smaller than a couple of partial vma, it is
1930 * not worth only creating a single partial vma - we may as well
1931 * clear enough space for the full object.
1933 flags = PIN_MAPPABLE;
1934 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1935 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1937 /* Now pin it into the GTT as needed */
1938 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1940 /* Use a partial view if it is bigger than available space */
1941 struct i915_ggtt_view view =
1942 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1944 /* Userspace is now writing through an untracked VMA, abandon
1945 * all hope that the hardware is able to track future writes.
1947 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1949 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1956 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1960 ret = i915_vma_get_fence(vma);
1964 /* Mark as being mmapped into userspace for later revocation */
1965 assert_rpm_wakelock_held(dev_priv);
1966 if (list_empty(&obj->userfault_link))
1967 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1969 /* Finally, remap it using the new GTT offset */
1970 ret = remap_io_mapping(area,
1971 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1972 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1973 min_t(u64, vma->size, area->vm_end - area->vm_start),
1977 __i915_vma_unpin(vma);
1979 mutex_unlock(&dev->struct_mutex);
1981 intel_runtime_pm_put(dev_priv);
1982 i915_gem_object_unpin_pages(obj);
1987 * We eat errors when the gpu is terminally wedged to avoid
1988 * userspace unduly crashing (gl has no provisions for mmaps to
1989 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1990 * and so needs to be reported.
1992 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1993 ret = VM_FAULT_SIGBUS;
1998 * EAGAIN means the gpu is hung and we'll wait for the error
1999 * handler to reset everything when re-faulting in
2000 * i915_mutex_lock_interruptible.
2007 * EBUSY is ok: this just means that another thread
2008 * already did the job.
2010 ret = VM_FAULT_NOPAGE;
2017 ret = VM_FAULT_SIGBUS;
2020 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2021 ret = VM_FAULT_SIGBUS;
2028 * i915_gem_release_mmap - remove physical page mappings
2029 * @obj: obj in question
2031 * Preserve the reservation of the mmapping with the DRM core code, but
2032 * relinquish ownership of the pages back to the system.
2034 * It is vital that we remove the page mapping if we have mapped a tiled
2035 * object through the GTT and then lose the fence register due to
2036 * resource pressure. Similarly if the object has been moved out of the
2037 * aperture, than pages mapped into userspace must be revoked. Removing the
2038 * mapping will then trigger a page fault on the next user access, allowing
2039 * fixup by i915_gem_fault().
2042 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2044 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2046 /* Serialisation between user GTT access and our code depends upon
2047 * revoking the CPU's PTE whilst the mutex is held. The next user
2048 * pagefault then has to wait until we release the mutex.
2050 * Note that RPM complicates somewhat by adding an additional
2051 * requirement that operations to the GGTT be made holding the RPM
2054 lockdep_assert_held(&i915->drm.struct_mutex);
2055 intel_runtime_pm_get(i915);
2057 if (list_empty(&obj->userfault_link))
2060 list_del_init(&obj->userfault_link);
2061 drm_vma_node_unmap(&obj->base.vma_node,
2062 obj->base.dev->anon_inode->i_mapping);
2064 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2065 * memory transactions from userspace before we return. The TLB
2066 * flushing implied above by changing the PTE above *should* be
2067 * sufficient, an extra barrier here just provides us with a bit
2068 * of paranoid documentation about our requirement to serialise
2069 * memory writes before touching registers / GSM.
2074 intel_runtime_pm_put(i915);
2077 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2079 struct drm_i915_gem_object *obj, *on;
2083 * Only called during RPM suspend. All users of the userfault_list
2084 * must be holding an RPM wakeref to ensure that this can not
2085 * run concurrently with themselves (and use the struct_mutex for
2086 * protection between themselves).
2089 list_for_each_entry_safe(obj, on,
2090 &dev_priv->mm.userfault_list, userfault_link) {
2091 list_del_init(&obj->userfault_link);
2092 drm_vma_node_unmap(&obj->base.vma_node,
2093 obj->base.dev->anon_inode->i_mapping);
2096 /* The fence will be lost when the device powers down. If any were
2097 * in use by hardware (i.e. they are pinned), we should not be powering
2098 * down! All other fences will be reacquired by the user upon waking.
2100 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2101 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2103 /* Ideally we want to assert that the fence register is not
2104 * live at this point (i.e. that no piece of code will be
2105 * trying to write through fence + GTT, as that both violates
2106 * our tracking of activity and associated locking/barriers,
2107 * but also is illegal given that the hw is powered down).
2109 * Previously we used reg->pin_count as a "liveness" indicator.
2110 * That is not sufficient, and we need a more fine-grained
2111 * tool if we want to have a sanity check here.
2117 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2122 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2124 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2127 err = drm_gem_create_mmap_offset(&obj->base);
2131 /* Attempt to reap some mmap space from dead objects */
2133 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2137 i915_gem_drain_freed_objects(dev_priv);
2138 err = drm_gem_create_mmap_offset(&obj->base);
2142 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2147 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2149 drm_gem_free_mmap_offset(&obj->base);
2153 i915_gem_mmap_gtt(struct drm_file *file,
2154 struct drm_device *dev,
2158 struct drm_i915_gem_object *obj;
2161 obj = i915_gem_object_lookup(file, handle);
2165 ret = i915_gem_object_create_mmap_offset(obj);
2167 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2169 i915_gem_object_put(obj);
2174 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2176 * @data: GTT mapping ioctl data
2177 * @file: GEM object info
2179 * Simply returns the fake offset to userspace so it can mmap it.
2180 * The mmap call will end up in drm_gem_mmap(), which will set things
2181 * up so we can get faults in the handler above.
2183 * The fault handler will take care of binding the object into the GTT
2184 * (since it may have been evicted to make room for something), allocating
2185 * a fence register, and mapping the appropriate aperture address into
2189 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2190 struct drm_file *file)
2192 struct drm_i915_gem_mmap_gtt *args = data;
2194 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2197 /* Immediately discard the backing storage */
2199 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2201 i915_gem_object_free_mmap_offset(obj);
2203 if (obj->base.filp == NULL)
2206 /* Our goal here is to return as much of the memory as
2207 * is possible back to the system as we are called from OOM.
2208 * To do this we must instruct the shmfs to drop all of its
2209 * backing pages, *now*.
2211 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2212 obj->mm.madv = __I915_MADV_PURGED;
2213 obj->mm.pages = ERR_PTR(-EFAULT);
2216 /* Try to discard unwanted pages */
2217 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2219 struct address_space *mapping;
2221 lockdep_assert_held(&obj->mm.lock);
2222 GEM_BUG_ON(obj->mm.pages);
2224 switch (obj->mm.madv) {
2225 case I915_MADV_DONTNEED:
2226 i915_gem_object_truncate(obj);
2227 case __I915_MADV_PURGED:
2231 if (obj->base.filp == NULL)
2234 mapping = obj->base.filp->f_mapping,
2235 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2239 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2240 struct sg_table *pages)
2242 struct sgt_iter sgt_iter;
2245 __i915_gem_object_release_shmem(obj, pages, true);
2247 i915_gem_gtt_finish_pages(obj, pages);
2249 if (i915_gem_object_needs_bit17_swizzle(obj))
2250 i915_gem_object_save_bit_17_swizzle(obj, pages);
2252 for_each_sgt_page(page, sgt_iter, pages) {
2254 set_page_dirty(page);
2256 if (obj->mm.madv == I915_MADV_WILLNEED)
2257 mark_page_accessed(page);
2261 obj->mm.dirty = false;
2263 sg_free_table(pages);
2267 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2269 struct radix_tree_iter iter;
2272 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2273 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2276 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2277 enum i915_mm_subclass subclass)
2279 struct sg_table *pages;
2281 if (i915_gem_object_has_pinned_pages(obj))
2284 GEM_BUG_ON(obj->bind_count);
2285 if (!READ_ONCE(obj->mm.pages))
2288 /* May be called by shrinker from within get_pages() (on another bo) */
2289 mutex_lock_nested(&obj->mm.lock, subclass);
2290 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2293 /* ->put_pages might need to allocate memory for the bit17 swizzle
2294 * array, hence protect them from being reaped by removing them from gtt
2296 pages = fetch_and_zero(&obj->mm.pages);
2299 if (obj->mm.mapping) {
2302 ptr = page_mask_bits(obj->mm.mapping);
2303 if (is_vmalloc_addr(ptr))
2306 kunmap(kmap_to_page(ptr));
2308 obj->mm.mapping = NULL;
2311 __i915_gem_object_reset_page_iter(obj);
2314 obj->ops->put_pages(obj, pages);
2317 mutex_unlock(&obj->mm.lock);
2320 static bool i915_sg_trim(struct sg_table *orig_st)
2322 struct sg_table new_st;
2323 struct scatterlist *sg, *new_sg;
2326 if (orig_st->nents == orig_st->orig_nents)
2329 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2332 new_sg = new_st.sgl;
2333 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2334 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2335 /* called before being DMA mapped, no need to copy sg->dma_* */
2336 new_sg = sg_next(new_sg);
2338 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2340 sg_free_table(orig_st);
2346 static struct sg_table *
2347 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2349 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2350 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2352 struct address_space *mapping;
2353 struct sg_table *st;
2354 struct scatterlist *sg;
2355 struct sgt_iter sgt_iter;
2357 unsigned long last_pfn = 0; /* suppress gcc warning */
2358 unsigned int max_segment;
2362 /* Assert that the object is not currently in any GPU domain. As it
2363 * wasn't in the GTT, there shouldn't be any way it could have been in
2366 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2367 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2369 max_segment = swiotlb_max_segment();
2371 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2373 st = kmalloc(sizeof(*st), GFP_KERNEL);
2375 return ERR_PTR(-ENOMEM);
2378 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2380 return ERR_PTR(-ENOMEM);
2383 /* Get the list of pages out of our struct file. They'll be pinned
2384 * at this point until we release them.
2386 * Fail silently without starting the shrinker
2388 mapping = obj->base.filp->f_mapping;
2389 noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
2390 noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
2394 for (i = 0; i < page_count; i++) {
2395 const unsigned int shrink[] = {
2396 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE,
2399 gfp_t gfp = noreclaim;
2402 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2403 if (likely(!IS_ERR(page)))
2407 ret = PTR_ERR(page);
2411 i915_gem_shrink(dev_priv, 2 * page_count, *s++);
2414 /* We've tried hard to allocate the memory by reaping
2415 * our own buffer, now let the real VM do its job and
2416 * go down in flames if truly OOM.
2418 * However, since graphics tend to be disposable,
2419 * defer the oom here by reporting the ENOMEM back
2423 /* reclaim and warn, but no oom */
2424 gfp = mapping_gfp_mask(mapping);
2426 /* Our bo are always dirty and so we require
2427 * kswapd to reclaim our pages (direct reclaim
2428 * does not effectively begin pageout of our
2429 * buffers on its own). However, direct reclaim
2430 * only waits for kswapd when under allocation
2431 * congestion. So as a result __GFP_RECLAIM is
2432 * unreliable and fails to actually reclaim our
2433 * dirty pages -- unless you try over and over
2434 * again with !__GFP_NORETRY. However, we still
2435 * want to fail this allocation rather than
2436 * trigger the out-of-memory killer and for
2437 * this we want the future __GFP_MAYFAIL.
2443 sg->length >= max_segment ||
2444 page_to_pfn(page) != last_pfn + 1) {
2448 sg_set_page(sg, page, PAGE_SIZE, 0);
2450 sg->length += PAGE_SIZE;
2452 last_pfn = page_to_pfn(page);
2454 /* Check that the i965g/gm workaround works. */
2455 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2457 if (sg) /* loop terminated early; short sg table */
2460 /* Trim unused sg entries to avoid wasting memory. */
2463 ret = i915_gem_gtt_prepare_pages(obj, st);
2465 /* DMA remapping failed? One possible cause is that
2466 * it could not reserve enough large entries, asking
2467 * for PAGE_SIZE chunks instead may be helpful.
2469 if (max_segment > PAGE_SIZE) {
2470 for_each_sgt_page(page, sgt_iter, st)
2474 max_segment = PAGE_SIZE;
2477 dev_warn(&dev_priv->drm.pdev->dev,
2478 "Failed to DMA remap %lu pages\n",
2484 if (i915_gem_object_needs_bit17_swizzle(obj))
2485 i915_gem_object_do_bit_17_swizzle(obj, st);
2492 for_each_sgt_page(page, sgt_iter, st)
2497 /* shmemfs first checks if there is enough memory to allocate the page
2498 * and reports ENOSPC should there be insufficient, along with the usual
2499 * ENOMEM for a genuine allocation failure.
2501 * We use ENOSPC in our driver to mean that we have run out of aperture
2502 * space and so want to translate the error from shmemfs back to our
2503 * usual understanding of ENOMEM.
2508 return ERR_PTR(ret);
2511 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2512 struct sg_table *pages)
2514 lockdep_assert_held(&obj->mm.lock);
2516 obj->mm.get_page.sg_pos = pages->sgl;
2517 obj->mm.get_page.sg_idx = 0;
2519 obj->mm.pages = pages;
2521 if (i915_gem_object_is_tiled(obj) &&
2522 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2523 GEM_BUG_ON(obj->mm.quirked);
2524 __i915_gem_object_pin_pages(obj);
2525 obj->mm.quirked = true;
2529 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2531 struct sg_table *pages;
2533 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2535 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2536 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2540 pages = obj->ops->get_pages(obj);
2541 if (unlikely(IS_ERR(pages)))
2542 return PTR_ERR(pages);
2544 __i915_gem_object_set_pages(obj, pages);
2548 /* Ensure that the associated pages are gathered from the backing storage
2549 * and pinned into our object. i915_gem_object_pin_pages() may be called
2550 * multiple times before they are released by a single call to
2551 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2552 * either as a result of memory pressure (reaping pages under the shrinker)
2553 * or as the object is itself released.
2555 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2559 err = mutex_lock_interruptible(&obj->mm.lock);
2563 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2564 err = ____i915_gem_object_get_pages(obj);
2568 smp_mb__before_atomic();
2570 atomic_inc(&obj->mm.pages_pin_count);
2573 mutex_unlock(&obj->mm.lock);
2577 /* The 'mapping' part of i915_gem_object_pin_map() below */
2578 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2579 enum i915_map_type type)
2581 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2582 struct sg_table *sgt = obj->mm.pages;
2583 struct sgt_iter sgt_iter;
2585 struct page *stack_pages[32];
2586 struct page **pages = stack_pages;
2587 unsigned long i = 0;
2591 /* A single page can always be kmapped */
2592 if (n_pages == 1 && type == I915_MAP_WB)
2593 return kmap(sg_page(sgt->sgl));
2595 if (n_pages > ARRAY_SIZE(stack_pages)) {
2596 /* Too big for stack -- allocate temporary array instead */
2597 pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY);
2602 for_each_sgt_page(page, sgt_iter, sgt)
2605 /* Check that we have the expected number of pages */
2606 GEM_BUG_ON(i != n_pages);
2610 pgprot = PAGE_KERNEL;
2613 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2616 addr = vmap(pages, n_pages, 0, pgprot);
2618 if (pages != stack_pages)
2624 /* get, pin, and map the pages of the object into kernel space */
2625 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2626 enum i915_map_type type)
2628 enum i915_map_type has_type;
2633 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2635 ret = mutex_lock_interruptible(&obj->mm.lock);
2637 return ERR_PTR(ret);
2640 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2641 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2642 ret = ____i915_gem_object_get_pages(obj);
2646 smp_mb__before_atomic();
2648 atomic_inc(&obj->mm.pages_pin_count);
2651 GEM_BUG_ON(!obj->mm.pages);
2653 ptr = page_unpack_bits(obj->mm.mapping, &has_type);
2654 if (ptr && has_type != type) {
2660 if (is_vmalloc_addr(ptr))
2663 kunmap(kmap_to_page(ptr));
2665 ptr = obj->mm.mapping = NULL;
2669 ptr = i915_gem_object_map(obj, type);
2675 obj->mm.mapping = page_pack_bits(ptr, type);
2679 mutex_unlock(&obj->mm.lock);
2683 atomic_dec(&obj->mm.pages_pin_count);
2690 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2691 const struct drm_i915_gem_pwrite *arg)
2693 struct address_space *mapping = obj->base.filp->f_mapping;
2694 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2698 /* Before we instantiate/pin the backing store for our use, we
2699 * can prepopulate the shmemfs filp efficiently using a write into
2700 * the pagecache. We avoid the penalty of instantiating all the
2701 * pages, important if the user is just writing to a few and never
2702 * uses the object on the GPU, and using a direct write into shmemfs
2703 * allows it to avoid the cost of retrieving a page (either swapin
2704 * or clearing-before-use) before it is overwritten.
2706 if (READ_ONCE(obj->mm.pages))
2709 /* Before the pages are instantiated the object is treated as being
2710 * in the CPU domain. The pages will be clflushed as required before
2711 * use, and we can freely write into the pages directly. If userspace
2712 * races pwrite with any other operation; corruption will ensue -
2713 * that is userspace's prerogative!
2717 offset = arg->offset;
2718 pg = offset_in_page(offset);
2721 unsigned int len, unwritten;
2726 len = PAGE_SIZE - pg;
2730 err = pagecache_write_begin(obj->base.filp, mapping,
2737 unwritten = copy_from_user(vaddr + pg, user_data, len);
2740 err = pagecache_write_end(obj->base.filp, mapping,
2741 offset, len, len - unwritten,
2758 static bool ban_context(const struct i915_gem_context *ctx)
2760 return (i915_gem_context_is_bannable(ctx) &&
2761 ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
2764 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2766 ctx->guilty_count++;
2767 ctx->ban_score += CONTEXT_SCORE_GUILTY;
2768 if (ban_context(ctx))
2769 i915_gem_context_set_banned(ctx);
2771 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2772 ctx->name, ctx->ban_score,
2773 yesno(i915_gem_context_is_banned(ctx)));
2775 if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
2778 ctx->file_priv->context_bans++;
2779 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2780 ctx->name, ctx->file_priv->context_bans);
2783 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2785 ctx->active_count++;
2788 struct drm_i915_gem_request *
2789 i915_gem_find_active_request(struct intel_engine_cs *engine)
2791 struct drm_i915_gem_request *request, *active = NULL;
2792 unsigned long flags;
2794 /* We are called by the error capture and reset at a random
2795 * point in time. In particular, note that neither is crucially
2796 * ordered with an interrupt. After a hang, the GPU is dead and we
2797 * assume that no more writes can happen (we waited long enough for
2798 * all writes that were in transaction to be flushed) - adding an
2799 * extra delay for a recent interrupt is pointless. Hence, we do
2800 * not need an engine->irq_seqno_barrier() before the seqno reads.
2802 spin_lock_irqsave(&engine->timeline->lock, flags);
2803 list_for_each_entry(request, &engine->timeline->requests, link) {
2804 if (__i915_gem_request_completed(request,
2805 request->global_seqno))
2808 GEM_BUG_ON(request->engine != engine);
2809 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2810 &request->fence.flags));
2815 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2820 static bool engine_stalled(struct intel_engine_cs *engine)
2822 if (!engine->hangcheck.stalled)
2825 /* Check for possible seqno movement after hang declaration */
2826 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2827 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2834 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2836 struct intel_engine_cs *engine;
2837 enum intel_engine_id id;
2840 /* Ensure irq handler finishes, and not run again. */
2841 for_each_engine(engine, dev_priv, id) {
2842 struct drm_i915_gem_request *request;
2844 /* Prevent the signaler thread from updating the request
2845 * state (by calling dma_fence_signal) as we are processing
2846 * the reset. The write from the GPU of the seqno is
2847 * asynchronous and the signaler thread may see a different
2848 * value to us and declare the request complete, even though
2849 * the reset routine have picked that request as the active
2850 * (incomplete) request. This conflict is not handled
2853 kthread_park(engine->breadcrumbs.signaler);
2855 /* Prevent request submission to the hardware until we have
2856 * completed the reset in i915_gem_reset_finish(). If a request
2857 * is completed by one engine, it may then queue a request
2858 * to a second via its engine->irq_tasklet *just* as we are
2859 * calling engine->init_hw() and also writing the ELSP.
2860 * Turning off the engine->irq_tasklet until the reset is over
2861 * prevents the race.
2863 tasklet_kill(&engine->irq_tasklet);
2864 tasklet_disable(&engine->irq_tasklet);
2866 if (engine->irq_seqno_barrier)
2867 engine->irq_seqno_barrier(engine);
2869 if (engine_stalled(engine)) {
2870 request = i915_gem_find_active_request(engine);
2871 if (request && request->fence.error == -EIO)
2872 err = -EIO; /* Previous reset failed! */
2876 i915_gem_revoke_fences(dev_priv);
2881 static void skip_request(struct drm_i915_gem_request *request)
2883 void *vaddr = request->ring->vaddr;
2886 /* As this request likely depends on state from the lost
2887 * context, clear out all the user operations leaving the
2888 * breadcrumb at the end (so we get the fence notifications).
2890 head = request->head;
2891 if (request->postfix < head) {
2892 memset(vaddr + head, 0, request->ring->size - head);
2895 memset(vaddr + head, 0, request->postfix - head);
2897 dma_fence_set_error(&request->fence, -EIO);
2900 static void engine_skip_context(struct drm_i915_gem_request *request)
2902 struct intel_engine_cs *engine = request->engine;
2903 struct i915_gem_context *hung_ctx = request->ctx;
2904 struct intel_timeline *timeline;
2905 unsigned long flags;
2907 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2909 spin_lock_irqsave(&engine->timeline->lock, flags);
2910 spin_lock(&timeline->lock);
2912 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2913 if (request->ctx == hung_ctx)
2914 skip_request(request);
2916 list_for_each_entry(request, &timeline->requests, link)
2917 skip_request(request);
2919 spin_unlock(&timeline->lock);
2920 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2923 /* Returns true if the request was guilty of hang */
2924 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
2926 /* Read once and return the resolution */
2927 const bool guilty = engine_stalled(request->engine);
2929 /* The guilty request will get skipped on a hung engine.
2931 * Users of client default contexts do not rely on logical
2932 * state preserved between batches so it is safe to execute
2933 * queued requests following the hang. Non default contexts
2934 * rely on preserved state, so skipping a batch loses the
2935 * evolution of the state and it needs to be considered corrupted.
2936 * Executing more queued batches on top of corrupted state is
2937 * risky. But we take the risk by trying to advance through
2938 * the queued requests in order to make the client behaviour
2939 * more predictable around resets, by not throwing away random
2940 * amount of batches it has prepared for execution. Sophisticated
2941 * clients can use gem_reset_stats_ioctl and dma fence status
2942 * (exported via sync_file info ioctl on explicit fences) to observe
2943 * when it loses the context state and should rebuild accordingly.
2945 * The context ban, and ultimately the client ban, mechanism are safety
2946 * valves if client submission ends up resulting in nothing more than
2951 i915_gem_context_mark_guilty(request->ctx);
2952 skip_request(request);
2954 i915_gem_context_mark_innocent(request->ctx);
2955 dma_fence_set_error(&request->fence, -EAGAIN);
2961 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2963 struct drm_i915_gem_request *request;
2965 request = i915_gem_find_active_request(engine);
2966 if (request && i915_gem_reset_request(request)) {
2967 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2968 engine->name, request->global_seqno);
2970 /* If this context is now banned, skip all pending requests. */
2971 if (i915_gem_context_is_banned(request->ctx))
2972 engine_skip_context(request);
2975 /* Setup the CS to resume from the breadcrumb of the hung request */
2976 engine->reset_hw(engine, request);
2979 void i915_gem_reset(struct drm_i915_private *dev_priv)
2981 struct intel_engine_cs *engine;
2982 enum intel_engine_id id;
2984 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2986 i915_gem_retire_requests(dev_priv);
2988 for_each_engine(engine, dev_priv, id) {
2989 struct i915_gem_context *ctx;
2991 i915_gem_reset_engine(engine);
2992 ctx = fetch_and_zero(&engine->last_retired_context);
2994 engine->context_unpin(engine, ctx);
2997 i915_gem_restore_fences(dev_priv);
2999 if (dev_priv->gt.awake) {
3000 intel_sanitize_gt_powersave(dev_priv);
3001 intel_enable_gt_powersave(dev_priv);
3002 if (INTEL_GEN(dev_priv) >= 6)
3003 gen6_rps_busy(dev_priv);
3007 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
3009 struct intel_engine_cs *engine;
3010 enum intel_engine_id id;
3012 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3014 for_each_engine(engine, dev_priv, id) {
3015 tasklet_enable(&engine->irq_tasklet);
3016 kthread_unpark(engine->breadcrumbs.signaler);
3020 static void nop_submit_request(struct drm_i915_gem_request *request)
3022 dma_fence_set_error(&request->fence, -EIO);
3023 i915_gem_request_submit(request);
3024 intel_engine_init_global_seqno(request->engine, request->global_seqno);
3027 static void engine_set_wedged(struct intel_engine_cs *engine)
3029 struct drm_i915_gem_request *request;
3030 unsigned long flags;
3032 /* We need to be sure that no thread is running the old callback as
3033 * we install the nop handler (otherwise we would submit a request
3034 * to hardware that will never complete). In order to prevent this
3035 * race, we wait until the machine is idle before making the swap
3036 * (using stop_machine()).
3038 engine->submit_request = nop_submit_request;
3040 /* Mark all executing requests as skipped */
3041 spin_lock_irqsave(&engine->timeline->lock, flags);
3042 list_for_each_entry(request, &engine->timeline->requests, link)
3043 dma_fence_set_error(&request->fence, -EIO);
3044 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3046 /* Mark all pending requests as complete so that any concurrent
3047 * (lockless) lookup doesn't try and wait upon the request as we
3050 intel_engine_init_global_seqno(engine,
3051 intel_engine_last_submit(engine));
3054 * Clear the execlists queue up before freeing the requests, as those
3055 * are the ones that keep the context and ringbuffer backing objects
3059 if (i915.enable_execlists) {
3060 struct execlist_port *port = engine->execlist_port;
3061 unsigned long flags;
3064 spin_lock_irqsave(&engine->timeline->lock, flags);
3066 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
3067 i915_gem_request_put(port_request(&port[n]));
3068 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
3069 engine->execlist_queue = RB_ROOT;
3070 engine->execlist_first = NULL;
3072 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3076 static int __i915_gem_set_wedged_BKL(void *data)
3078 struct drm_i915_private *i915 = data;
3079 struct intel_engine_cs *engine;
3080 enum intel_engine_id id;
3082 for_each_engine(engine, i915, id)
3083 engine_set_wedged(engine);
3088 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
3090 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3091 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
3093 /* Retire completed requests first so the list of inflight/incomplete
3094 * requests is accurate and we don't try and mark successful requests
3095 * as in error during __i915_gem_set_wedged_BKL().
3097 i915_gem_retire_requests(dev_priv);
3099 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
3101 i915_gem_context_lost(dev_priv);
3103 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
3106 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3108 struct i915_gem_timeline *tl;
3111 lockdep_assert_held(&i915->drm.struct_mutex);
3112 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3115 /* Before unwedging, make sure that all pending operations
3116 * are flushed and errored out - we may have requests waiting upon
3117 * third party fences. We marked all inflight requests as EIO, and
3118 * every execbuf since returned EIO, for consistency we want all
3119 * the currently pending requests to also be marked as EIO, which
3120 * is done inside our nop_submit_request - and so we must wait.
3122 * No more can be submitted until we reset the wedged bit.
3124 list_for_each_entry(tl, &i915->gt.timelines, link) {
3125 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3126 struct drm_i915_gem_request *rq;
3128 rq = i915_gem_active_peek(&tl->engine[i].last_request,
3129 &i915->drm.struct_mutex);
3133 /* We can't use our normal waiter as we want to
3134 * avoid recursively trying to handle the current
3135 * reset. The basic dma_fence_default_wait() installs
3136 * a callback for dma_fence_signal(), which is
3137 * triggered by our nop handler (indirectly, the
3138 * callback enables the signaler thread which is
3139 * woken by the nop_submit_request() advancing the seqno
3140 * and when the seqno passes the fence, the signaler
3141 * then signals the fence waking us up).
3143 if (dma_fence_default_wait(&rq->fence, true,
3144 MAX_SCHEDULE_TIMEOUT) < 0)
3149 /* Undo nop_submit_request. We prevent all new i915 requests from
3150 * being queued (by disallowing execbuf whilst wedged) so having
3151 * waited for all active requests above, we know the system is idle
3152 * and do not have to worry about a thread being inside
3153 * engine->submit_request() as we swap over. So unlike installing
3154 * the nop_submit_request on reset, we can do this from normal
3155 * context and do not require stop_machine().
3157 intel_engines_reset_default_submission(i915);
3159 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3160 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3166 i915_gem_retire_work_handler(struct work_struct *work)
3168 struct drm_i915_private *dev_priv =
3169 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3170 struct drm_device *dev = &dev_priv->drm;
3172 /* Come back later if the device is busy... */
3173 if (mutex_trylock(&dev->struct_mutex)) {
3174 i915_gem_retire_requests(dev_priv);
3175 mutex_unlock(&dev->struct_mutex);
3178 /* Keep the retire handler running until we are finally idle.
3179 * We do not need to do this test under locking as in the worst-case
3180 * we queue the retire worker once too often.
3182 if (READ_ONCE(dev_priv->gt.awake)) {
3183 i915_queue_hangcheck(dev_priv);
3184 queue_delayed_work(dev_priv->wq,
3185 &dev_priv->gt.retire_work,
3186 round_jiffies_up_relative(HZ));
3191 i915_gem_idle_work_handler(struct work_struct *work)
3193 struct drm_i915_private *dev_priv =
3194 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3195 struct drm_device *dev = &dev_priv->drm;
3196 bool rearm_hangcheck;
3198 if (!READ_ONCE(dev_priv->gt.awake))
3202 * Wait for last execlists context complete, but bail out in case a
3203 * new request is submitted.
3205 wait_for(intel_engines_are_idle(dev_priv), 10);
3206 if (READ_ONCE(dev_priv->gt.active_requests))
3210 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3212 if (!mutex_trylock(&dev->struct_mutex)) {
3213 /* Currently busy, come back later */
3214 mod_delayed_work(dev_priv->wq,
3215 &dev_priv->gt.idle_work,
3216 msecs_to_jiffies(50));
3221 * New request retired after this work handler started, extend active
3222 * period until next instance of the work.
3224 if (work_pending(work))
3227 if (dev_priv->gt.active_requests)
3230 if (wait_for(intel_engines_are_idle(dev_priv), 10))
3231 DRM_ERROR("Timeout waiting for engines to idle\n");
3233 intel_engines_mark_idle(dev_priv);
3234 i915_gem_timelines_mark_idle(dev_priv);
3236 GEM_BUG_ON(!dev_priv->gt.awake);
3237 dev_priv->gt.awake = false;
3238 rearm_hangcheck = false;
3240 if (INTEL_GEN(dev_priv) >= 6)
3241 gen6_rps_idle(dev_priv);
3242 intel_runtime_pm_put(dev_priv);
3244 mutex_unlock(&dev->struct_mutex);
3247 if (rearm_hangcheck) {
3248 GEM_BUG_ON(!dev_priv->gt.awake);
3249 i915_queue_hangcheck(dev_priv);
3253 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3255 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3256 struct drm_i915_file_private *fpriv = file->driver_priv;
3257 struct i915_vma *vma, *vn;
3259 mutex_lock(&obj->base.dev->struct_mutex);
3260 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3261 if (vma->vm->file == fpriv)
3262 i915_vma_close(vma);
3264 vma = obj->vma_hashed;
3265 if (vma && vma->ctx->file_priv == fpriv)
3266 i915_vma_unlink_ctx(vma);
3268 if (i915_gem_object_is_active(obj) &&
3269 !i915_gem_object_has_active_reference(obj)) {
3270 i915_gem_object_set_active_reference(obj);
3271 i915_gem_object_get(obj);
3273 mutex_unlock(&obj->base.dev->struct_mutex);
3276 static unsigned long to_wait_timeout(s64 timeout_ns)
3279 return MAX_SCHEDULE_TIMEOUT;
3281 if (timeout_ns == 0)
3284 return nsecs_to_jiffies_timeout(timeout_ns);
3288 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3289 * @dev: drm device pointer
3290 * @data: ioctl data blob
3291 * @file: drm file pointer
3293 * Returns 0 if successful, else an error is returned with the remaining time in
3294 * the timeout parameter.
3295 * -ETIME: object is still busy after timeout
3296 * -ERESTARTSYS: signal interrupted the wait
3297 * -ENONENT: object doesn't exist
3298 * Also possible, but rare:
3299 * -EAGAIN: GPU wedged
3301 * -ENODEV: Internal IRQ fail
3302 * -E?: The add request failed
3304 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3305 * non-zero timeout parameter the wait ioctl will wait for the given number of
3306 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3307 * without holding struct_mutex the object may become re-busied before this
3308 * function completes. A similar but shorter * race condition exists in the busy
3312 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3314 struct drm_i915_gem_wait *args = data;
3315 struct drm_i915_gem_object *obj;
3319 if (args->flags != 0)
3322 obj = i915_gem_object_lookup(file, args->bo_handle);
3326 start = ktime_get();
3328 ret = i915_gem_object_wait(obj,
3329 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3330 to_wait_timeout(args->timeout_ns),
3331 to_rps_client(file));
3333 if (args->timeout_ns > 0) {
3334 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3335 if (args->timeout_ns < 0)
3336 args->timeout_ns = 0;
3339 * Apparently ktime isn't accurate enough and occasionally has a
3340 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3341 * things up to make the test happy. We allow up to 1 jiffy.
3343 * This is a regression from the timespec->ktime conversion.
3345 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3346 args->timeout_ns = 0;
3349 i915_gem_object_put(obj);
3353 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3357 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3358 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3366 static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
3368 return wait_for(intel_engine_is_idle(engine), timeout_ms);
3371 static int wait_for_engines(struct drm_i915_private *i915)
3373 struct intel_engine_cs *engine;
3374 enum intel_engine_id id;
3376 for_each_engine(engine, i915, id) {
3377 if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
3378 i915_gem_set_wedged(i915);
3382 GEM_BUG_ON(intel_engine_get_seqno(engine) !=
3383 intel_engine_last_submit(engine));
3389 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3393 /* If the device is asleep, we have no requests outstanding */
3394 if (!READ_ONCE(i915->gt.awake))
3397 if (flags & I915_WAIT_LOCKED) {
3398 struct i915_gem_timeline *tl;
3400 lockdep_assert_held(&i915->drm.struct_mutex);
3402 list_for_each_entry(tl, &i915->gt.timelines, link) {
3403 ret = wait_for_timeline(tl, flags);
3408 i915_gem_retire_requests(i915);
3409 GEM_BUG_ON(i915->gt.active_requests);
3411 ret = wait_for_engines(i915);
3413 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3419 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3422 * We manually flush the CPU domain so that we can override and
3423 * force the flush for the display, and perform it asyncrhonously.
3425 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3426 if (obj->cache_dirty)
3427 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3428 obj->base.write_domain = 0;
3431 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3433 if (!READ_ONCE(obj->pin_display))
3436 mutex_lock(&obj->base.dev->struct_mutex);
3437 __i915_gem_object_flush_for_display(obj);
3438 mutex_unlock(&obj->base.dev->struct_mutex);
3442 * Moves a single object to the WC read, and possibly write domain.
3443 * @obj: object to act on
3444 * @write: ask for write access or read only
3446 * This function returns when the move is complete, including waiting on
3450 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
3454 lockdep_assert_held(&obj->base.dev->struct_mutex);
3456 ret = i915_gem_object_wait(obj,
3457 I915_WAIT_INTERRUPTIBLE |
3459 (write ? I915_WAIT_ALL : 0),
3460 MAX_SCHEDULE_TIMEOUT,
3465 if (obj->base.write_domain == I915_GEM_DOMAIN_WC)
3468 /* Flush and acquire obj->pages so that we are coherent through
3469 * direct access in memory with previous cached writes through
3470 * shmemfs and that our cache domain tracking remains valid.
3471 * For example, if the obj->filp was moved to swap without us
3472 * being notified and releasing the pages, we would mistakenly
3473 * continue to assume that the obj remained out of the CPU cached
3476 ret = i915_gem_object_pin_pages(obj);
3480 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
3482 /* Serialise direct access to this object with the barriers for
3483 * coherent writes from the GPU, by effectively invalidating the
3484 * WC domain upon first access.
3486 if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0)
3489 /* It should now be out of any other write domains, and we can update
3490 * the domain values for our changes.
3492 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);
3493 obj->base.read_domains |= I915_GEM_DOMAIN_WC;
3495 obj->base.read_domains = I915_GEM_DOMAIN_WC;
3496 obj->base.write_domain = I915_GEM_DOMAIN_WC;
3497 obj->mm.dirty = true;
3500 i915_gem_object_unpin_pages(obj);
3505 * Moves a single object to the GTT read, and possibly write domain.
3506 * @obj: object to act on
3507 * @write: ask for write access or read only
3509 * This function returns when the move is complete, including waiting on
3513 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3517 lockdep_assert_held(&obj->base.dev->struct_mutex);
3519 ret = i915_gem_object_wait(obj,
3520 I915_WAIT_INTERRUPTIBLE |
3522 (write ? I915_WAIT_ALL : 0),
3523 MAX_SCHEDULE_TIMEOUT,
3528 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3531 /* Flush and acquire obj->pages so that we are coherent through
3532 * direct access in memory with previous cached writes through
3533 * shmemfs and that our cache domain tracking remains valid.
3534 * For example, if the obj->filp was moved to swap without us
3535 * being notified and releasing the pages, we would mistakenly
3536 * continue to assume that the obj remained out of the CPU cached
3539 ret = i915_gem_object_pin_pages(obj);
3543 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
3545 /* Serialise direct access to this object with the barriers for
3546 * coherent writes from the GPU, by effectively invalidating the
3547 * GTT domain upon first access.
3549 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3552 /* It should now be out of any other write domains, and we can update
3553 * the domain values for our changes.
3555 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3556 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3558 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3559 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3560 obj->mm.dirty = true;
3563 i915_gem_object_unpin_pages(obj);
3568 * Changes the cache-level of an object across all VMA.
3569 * @obj: object to act on
3570 * @cache_level: new cache level to set for the object
3572 * After this function returns, the object will be in the new cache-level
3573 * across all GTT and the contents of the backing storage will be coherent,
3574 * with respect to the new cache-level. In order to keep the backing storage
3575 * coherent for all users, we only allow a single cache level to be set
3576 * globally on the object and prevent it from being changed whilst the
3577 * hardware is reading from the object. That is if the object is currently
3578 * on the scanout it will be set to uncached (or equivalent display
3579 * cache coherency) and all non-MOCS GPU access will also be uncached so
3580 * that all direct access to the scanout remains coherent.
3582 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3583 enum i915_cache_level cache_level)
3585 struct i915_vma *vma;
3588 lockdep_assert_held(&obj->base.dev->struct_mutex);
3590 if (obj->cache_level == cache_level)
3593 /* Inspect the list of currently bound VMA and unbind any that would
3594 * be invalid given the new cache-level. This is principally to
3595 * catch the issue of the CS prefetch crossing page boundaries and
3596 * reading an invalid PTE on older architectures.
3599 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3600 if (!drm_mm_node_allocated(&vma->node))
3603 if (i915_vma_is_pinned(vma)) {
3604 DRM_DEBUG("can not change the cache level of pinned objects\n");
3608 if (i915_gem_valid_gtt_space(vma, cache_level))
3611 ret = i915_vma_unbind(vma);
3615 /* As unbinding may affect other elements in the
3616 * obj->vma_list (due to side-effects from retiring
3617 * an active vma), play safe and restart the iterator.
3622 /* We can reuse the existing drm_mm nodes but need to change the
3623 * cache-level on the PTE. We could simply unbind them all and
3624 * rebind with the correct cache-level on next use. However since
3625 * we already have a valid slot, dma mapping, pages etc, we may as
3626 * rewrite the PTE in the belief that doing so tramples upon less
3627 * state and so involves less work.
3629 if (obj->bind_count) {
3630 /* Before we change the PTE, the GPU must not be accessing it.
3631 * If we wait upon the object, we know that all the bound
3632 * VMA are no longer active.
3634 ret = i915_gem_object_wait(obj,
3635 I915_WAIT_INTERRUPTIBLE |
3638 MAX_SCHEDULE_TIMEOUT,
3643 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3644 cache_level != I915_CACHE_NONE) {
3645 /* Access to snoopable pages through the GTT is
3646 * incoherent and on some machines causes a hard
3647 * lockup. Relinquish the CPU mmaping to force
3648 * userspace to refault in the pages and we can
3649 * then double check if the GTT mapping is still
3650 * valid for that pointer access.
3652 i915_gem_release_mmap(obj);
3654 /* As we no longer need a fence for GTT access,
3655 * we can relinquish it now (and so prevent having
3656 * to steal a fence from someone else on the next
3657 * fence request). Note GPU activity would have
3658 * dropped the fence as all snoopable access is
3659 * supposed to be linear.
3661 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3662 ret = i915_vma_put_fence(vma);
3667 /* We either have incoherent backing store and
3668 * so no GTT access or the architecture is fully
3669 * coherent. In such cases, existing GTT mmaps
3670 * ignore the cache bit in the PTE and we can
3671 * rewrite it without confusing the GPU or having
3672 * to force userspace to fault back in its mmaps.
3676 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3677 if (!drm_mm_node_allocated(&vma->node))
3680 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3686 list_for_each_entry(vma, &obj->vma_list, obj_link)
3687 vma->node.color = cache_level;
3688 obj->cache_level = cache_level;
3689 obj->cache_coherent = i915_gem_object_is_coherent(obj);
3690 obj->cache_dirty = true; /* Always invalidate stale cachelines */
3695 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3696 struct drm_file *file)
3698 struct drm_i915_gem_caching *args = data;
3699 struct drm_i915_gem_object *obj;
3703 obj = i915_gem_object_lookup_rcu(file, args->handle);
3709 switch (obj->cache_level) {
3710 case I915_CACHE_LLC:
3711 case I915_CACHE_L3_LLC:
3712 args->caching = I915_CACHING_CACHED;
3716 args->caching = I915_CACHING_DISPLAY;
3720 args->caching = I915_CACHING_NONE;
3728 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3729 struct drm_file *file)
3731 struct drm_i915_private *i915 = to_i915(dev);
3732 struct drm_i915_gem_caching *args = data;
3733 struct drm_i915_gem_object *obj;
3734 enum i915_cache_level level;
3737 switch (args->caching) {
3738 case I915_CACHING_NONE:
3739 level = I915_CACHE_NONE;
3741 case I915_CACHING_CACHED:
3743 * Due to a HW issue on BXT A stepping, GPU stores via a
3744 * snooped mapping may leave stale data in a corresponding CPU
3745 * cacheline, whereas normally such cachelines would get
3748 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3751 level = I915_CACHE_LLC;
3753 case I915_CACHING_DISPLAY:
3754 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3760 obj = i915_gem_object_lookup(file, args->handle);
3764 if (obj->cache_level == level)
3767 ret = i915_gem_object_wait(obj,
3768 I915_WAIT_INTERRUPTIBLE,
3769 MAX_SCHEDULE_TIMEOUT,
3770 to_rps_client(file));
3774 ret = i915_mutex_lock_interruptible(dev);
3778 ret = i915_gem_object_set_cache_level(obj, level);
3779 mutex_unlock(&dev->struct_mutex);
3782 i915_gem_object_put(obj);
3787 * Prepare buffer for display plane (scanout, cursors, etc).
3788 * Can be called from an uninterruptible phase (modesetting) and allows
3789 * any flushes to be pipelined (for pageflips).
3792 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3794 const struct i915_ggtt_view *view)
3796 struct i915_vma *vma;
3799 lockdep_assert_held(&obj->base.dev->struct_mutex);
3801 /* Mark the pin_display early so that we account for the
3802 * display coherency whilst setting up the cache domains.
3806 /* The display engine is not coherent with the LLC cache on gen6. As
3807 * a result, we make sure that the pinning that is about to occur is
3808 * done with uncached PTEs. This is lowest common denominator for all
3811 * However for gen6+, we could do better by using the GFDT bit instead
3812 * of uncaching, which would allow us to flush all the LLC-cached data
3813 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3815 ret = i915_gem_object_set_cache_level(obj,
3816 HAS_WT(to_i915(obj->base.dev)) ?
3817 I915_CACHE_WT : I915_CACHE_NONE);
3820 goto err_unpin_display;
3823 /* As the user may map the buffer once pinned in the display plane
3824 * (e.g. libkms for the bootup splash), we have to ensure that we
3825 * always use map_and_fenceable for all scanout buffers. However,
3826 * it may simply be too big to fit into mappable, in which case
3827 * put it anyway and hope that userspace can cope (but always first
3828 * try to preserve the existing ABI).
3830 vma = ERR_PTR(-ENOSPC);
3831 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3832 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3833 PIN_MAPPABLE | PIN_NONBLOCK);
3835 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3838 /* Valleyview is definitely limited to scanning out the first
3839 * 512MiB. Lets presume this behaviour was inherited from the
3840 * g4x display engine and that all earlier gen are similarly
3841 * limited. Testing suggests that it is a little more
3842 * complicated than this. For example, Cherryview appears quite
3843 * happy to scanout from anywhere within its global aperture.
3846 if (HAS_GMCH_DISPLAY(i915))
3847 flags = PIN_MAPPABLE;
3848 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3851 goto err_unpin_display;
3853 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3855 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3856 __i915_gem_object_flush_for_display(obj);
3857 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3859 /* It should now be out of any other write domains, and we can update
3860 * the domain values for our changes.
3862 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3872 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3874 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3876 if (WARN_ON(vma->obj->pin_display == 0))
3879 if (--vma->obj->pin_display == 0)
3880 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3882 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3883 i915_gem_object_bump_inactive_ggtt(vma->obj);
3885 i915_vma_unpin(vma);
3889 * Moves a single object to the CPU read, and possibly write domain.
3890 * @obj: object to act on
3891 * @write: requesting write or read-only access
3893 * This function returns when the move is complete, including waiting on
3897 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3901 lockdep_assert_held(&obj->base.dev->struct_mutex);
3903 ret = i915_gem_object_wait(obj,
3904 I915_WAIT_INTERRUPTIBLE |
3906 (write ? I915_WAIT_ALL : 0),
3907 MAX_SCHEDULE_TIMEOUT,
3912 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3914 /* Flush the CPU cache if it's still invalid. */
3915 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3916 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3917 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3920 /* It should now be out of any other write domains, and we can update
3921 * the domain values for our changes.
3923 GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3925 /* If we're writing through the CPU, then the GPU read domains will
3926 * need to be invalidated at next use.
3929 __start_cpu_write(obj);
3934 /* Throttle our rendering by waiting until the ring has completed our requests
3935 * emitted over 20 msec ago.
3937 * Note that if we were to use the current jiffies each time around the loop,
3938 * we wouldn't escape the function with any frames outstanding if the time to
3939 * render a frame was over 20ms.
3941 * This should get us reasonable parallelism between CPU and GPU but also
3942 * relatively low latency when blocking on a particular request to finish.
3945 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3947 struct drm_i915_private *dev_priv = to_i915(dev);
3948 struct drm_i915_file_private *file_priv = file->driver_priv;
3949 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3950 struct drm_i915_gem_request *request, *target = NULL;
3953 /* ABI: return -EIO if already wedged */
3954 if (i915_terminally_wedged(&dev_priv->gpu_error))
3957 spin_lock(&file_priv->mm.lock);
3958 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3959 if (time_after_eq(request->emitted_jiffies, recent_enough))
3963 list_del(&target->client_link);
3964 target->file_priv = NULL;
3970 i915_gem_request_get(target);
3971 spin_unlock(&file_priv->mm.lock);
3976 ret = i915_wait_request(target,
3977 I915_WAIT_INTERRUPTIBLE,
3978 MAX_SCHEDULE_TIMEOUT);
3979 i915_gem_request_put(target);
3981 return ret < 0 ? ret : 0;
3985 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3986 const struct i915_ggtt_view *view,
3991 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3992 struct i915_address_space *vm = &dev_priv->ggtt.base;
3993 struct i915_vma *vma;
3996 lockdep_assert_held(&obj->base.dev->struct_mutex);
3998 vma = i915_vma_instance(obj, vm, view);
3999 if (unlikely(IS_ERR(vma)))
4002 if (i915_vma_misplaced(vma, size, alignment, flags)) {
4003 if (flags & PIN_NONBLOCK &&
4004 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
4005 return ERR_PTR(-ENOSPC);
4007 if (flags & PIN_MAPPABLE) {
4008 /* If the required space is larger than the available
4009 * aperture, we will not able to find a slot for the
4010 * object and unbinding the object now will be in
4011 * vain. Worse, doing so may cause us to ping-pong
4012 * the object in and out of the Global GTT and
4013 * waste a lot of cycles under the mutex.
4015 if (vma->fence_size > dev_priv->ggtt.mappable_end)
4016 return ERR_PTR(-E2BIG);
4018 /* If NONBLOCK is set the caller is optimistically
4019 * trying to cache the full object within the mappable
4020 * aperture, and *must* have a fallback in place for
4021 * situations where we cannot bind the object. We
4022 * can be a little more lax here and use the fallback
4023 * more often to avoid costly migrations of ourselves
4024 * and other objects within the aperture.
4026 * Half-the-aperture is used as a simple heuristic.
4027 * More interesting would to do search for a free
4028 * block prior to making the commitment to unbind.
4029 * That caters for the self-harm case, and with a
4030 * little more heuristics (e.g. NOFAULT, NOEVICT)
4031 * we could try to minimise harm to others.
4033 if (flags & PIN_NONBLOCK &&
4034 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
4035 return ERR_PTR(-ENOSPC);
4038 WARN(i915_vma_is_pinned(vma),
4039 "bo is already pinned in ggtt with incorrect alignment:"
4040 " offset=%08x, req.alignment=%llx,"
4041 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4042 i915_ggtt_offset(vma), alignment,
4043 !!(flags & PIN_MAPPABLE),
4044 i915_vma_is_map_and_fenceable(vma));
4045 ret = i915_vma_unbind(vma);
4047 return ERR_PTR(ret);
4050 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
4052 return ERR_PTR(ret);
4057 static __always_inline unsigned int __busy_read_flag(unsigned int id)
4059 /* Note that we could alias engines in the execbuf API, but
4060 * that would be very unwise as it prevents userspace from
4061 * fine control over engine selection. Ahem.
4063 * This should be something like EXEC_MAX_ENGINE instead of
4066 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
4067 return 0x10000 << id;
4070 static __always_inline unsigned int __busy_write_id(unsigned int id)
4072 /* The uABI guarantees an active writer is also amongst the read
4073 * engines. This would be true if we accessed the activity tracking
4074 * under the lock, but as we perform the lookup of the object and
4075 * its activity locklessly we can not guarantee that the last_write
4076 * being active implies that we have set the same engine flag from
4077 * last_read - hence we always set both read and write busy for
4080 return id | __busy_read_flag(id);
4083 static __always_inline unsigned int
4084 __busy_set_if_active(const struct dma_fence *fence,
4085 unsigned int (*flag)(unsigned int id))
4087 struct drm_i915_gem_request *rq;
4089 /* We have to check the current hw status of the fence as the uABI
4090 * guarantees forward progress. We could rely on the idle worker
4091 * to eventually flush us, but to minimise latency just ask the
4094 * Note we only report on the status of native fences.
4096 if (!dma_fence_is_i915(fence))
4099 /* opencode to_request() in order to avoid const warnings */
4100 rq = container_of(fence, struct drm_i915_gem_request, fence);
4101 if (i915_gem_request_completed(rq))
4104 return flag(rq->engine->uabi_id);
4107 static __always_inline unsigned int
4108 busy_check_reader(const struct dma_fence *fence)
4110 return __busy_set_if_active(fence, __busy_read_flag);
4113 static __always_inline unsigned int
4114 busy_check_writer(const struct dma_fence *fence)
4119 return __busy_set_if_active(fence, __busy_write_id);
4123 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4124 struct drm_file *file)
4126 struct drm_i915_gem_busy *args = data;
4127 struct drm_i915_gem_object *obj;
4128 struct reservation_object_list *list;
4134 obj = i915_gem_object_lookup_rcu(file, args->handle);
4138 /* A discrepancy here is that we do not report the status of
4139 * non-i915 fences, i.e. even though we may report the object as idle,
4140 * a call to set-domain may still stall waiting for foreign rendering.
4141 * This also means that wait-ioctl may report an object as busy,
4142 * where busy-ioctl considers it idle.
4144 * We trade the ability to warn of foreign fences to report on which
4145 * i915 engines are active for the object.
4147 * Alternatively, we can trade that extra information on read/write
4150 * !reservation_object_test_signaled_rcu(obj->resv, true);
4151 * to report the overall busyness. This is what the wait-ioctl does.
4155 seq = raw_read_seqcount(&obj->resv->seq);
4157 /* Translate the exclusive fence to the READ *and* WRITE engine */
4158 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4160 /* Translate shared fences to READ set of engines */
4161 list = rcu_dereference(obj->resv->fence);
4163 unsigned int shared_count = list->shared_count, i;
4165 for (i = 0; i < shared_count; ++i) {
4166 struct dma_fence *fence =
4167 rcu_dereference(list->shared[i]);
4169 args->busy |= busy_check_reader(fence);
4173 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4183 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4184 struct drm_file *file_priv)
4186 return i915_gem_ring_throttle(dev, file_priv);
4190 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4191 struct drm_file *file_priv)
4193 struct drm_i915_private *dev_priv = to_i915(dev);
4194 struct drm_i915_gem_madvise *args = data;
4195 struct drm_i915_gem_object *obj;
4198 switch (args->madv) {
4199 case I915_MADV_DONTNEED:
4200 case I915_MADV_WILLNEED:
4206 obj = i915_gem_object_lookup(file_priv, args->handle);
4210 err = mutex_lock_interruptible(&obj->mm.lock);
4214 if (obj->mm.pages &&
4215 i915_gem_object_is_tiled(obj) &&
4216 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4217 if (obj->mm.madv == I915_MADV_WILLNEED) {
4218 GEM_BUG_ON(!obj->mm.quirked);
4219 __i915_gem_object_unpin_pages(obj);
4220 obj->mm.quirked = false;
4222 if (args->madv == I915_MADV_WILLNEED) {
4223 GEM_BUG_ON(obj->mm.quirked);
4224 __i915_gem_object_pin_pages(obj);
4225 obj->mm.quirked = true;
4229 if (obj->mm.madv != __I915_MADV_PURGED)
4230 obj->mm.madv = args->madv;
4232 /* if the object is no longer attached, discard its backing storage */
4233 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4234 i915_gem_object_truncate(obj);
4236 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4237 mutex_unlock(&obj->mm.lock);
4240 i915_gem_object_put(obj);
4245 frontbuffer_retire(struct i915_gem_active *active,
4246 struct drm_i915_gem_request *request)
4248 struct drm_i915_gem_object *obj =
4249 container_of(active, typeof(*obj), frontbuffer_write);
4251 intel_fb_obj_flush(obj, ORIGIN_CS);
4254 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4255 const struct drm_i915_gem_object_ops *ops)
4257 mutex_init(&obj->mm.lock);
4259 INIT_LIST_HEAD(&obj->global_link);
4260 INIT_LIST_HEAD(&obj->userfault_link);
4261 INIT_LIST_HEAD(&obj->vma_list);
4262 INIT_LIST_HEAD(&obj->batch_pool_link);
4266 reservation_object_init(&obj->__builtin_resv);
4267 obj->resv = &obj->__builtin_resv;
4269 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4270 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4272 obj->mm.madv = I915_MADV_WILLNEED;
4273 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4274 mutex_init(&obj->mm.get_page.lock);
4276 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4279 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4280 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4281 I915_GEM_OBJECT_IS_SHRINKABLE,
4283 .get_pages = i915_gem_object_get_pages_gtt,
4284 .put_pages = i915_gem_object_put_pages_gtt,
4286 .pwrite = i915_gem_object_pwrite_gtt,
4289 struct drm_i915_gem_object *
4290 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4292 struct drm_i915_gem_object *obj;
4293 struct address_space *mapping;
4297 /* There is a prevalence of the assumption that we fit the object's
4298 * page count inside a 32bit _signed_ variable. Let's document this and
4299 * catch if we ever need to fix it. In the meantime, if you do spot
4300 * such a local variable, please consider fixing!
4302 if (size >> PAGE_SHIFT > INT_MAX)
4303 return ERR_PTR(-E2BIG);
4305 if (overflows_type(size, obj->base.size))
4306 return ERR_PTR(-E2BIG);
4308 obj = i915_gem_object_alloc(dev_priv);
4310 return ERR_PTR(-ENOMEM);
4312 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4316 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4317 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4318 /* 965gm cannot relocate objects above 4GiB. */
4319 mask &= ~__GFP_HIGHMEM;
4320 mask |= __GFP_DMA32;
4323 mapping = obj->base.filp->f_mapping;
4324 mapping_set_gfp_mask(mapping, mask);
4325 GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
4327 i915_gem_object_init(obj, &i915_gem_object_ops);
4329 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4330 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4332 if (HAS_LLC(dev_priv)) {
4333 /* On some devices, we can have the GPU use the LLC (the CPU
4334 * cache) for about a 10% performance improvement
4335 * compared to uncached. Graphics requests other than
4336 * display scanout are coherent with the CPU in
4337 * accessing this cache. This means in this mode we
4338 * don't need to clflush on the CPU side, and on the
4339 * GPU side we only need to flush internal caches to
4340 * get data visible to the CPU.
4342 * However, we maintain the display planes as UC, and so
4343 * need to rebind when first used as such.
4345 obj->cache_level = I915_CACHE_LLC;
4347 obj->cache_level = I915_CACHE_NONE;
4349 obj->cache_coherent = i915_gem_object_is_coherent(obj);
4350 obj->cache_dirty = !obj->cache_coherent;
4352 trace_i915_gem_object_create(obj);
4357 i915_gem_object_free(obj);
4358 return ERR_PTR(ret);
4361 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4363 /* If we are the last user of the backing storage (be it shmemfs
4364 * pages or stolen etc), we know that the pages are going to be
4365 * immediately released. In this case, we can then skip copying
4366 * back the contents from the GPU.
4369 if (obj->mm.madv != I915_MADV_WILLNEED)
4372 if (obj->base.filp == NULL)
4375 /* At first glance, this looks racy, but then again so would be
4376 * userspace racing mmap against close. However, the first external
4377 * reference to the filp can only be obtained through the
4378 * i915_gem_mmap_ioctl() which safeguards us against the user
4379 * acquiring such a reference whilst we are in the middle of
4380 * freeing the object.
4382 return atomic_long_read(&obj->base.filp->f_count) == 1;
4385 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4386 struct llist_node *freed)
4388 struct drm_i915_gem_object *obj, *on;
4390 mutex_lock(&i915->drm.struct_mutex);
4391 intel_runtime_pm_get(i915);
4392 llist_for_each_entry(obj, freed, freed) {
4393 struct i915_vma *vma, *vn;
4395 trace_i915_gem_object_destroy(obj);
4397 GEM_BUG_ON(i915_gem_object_is_active(obj));
4398 list_for_each_entry_safe(vma, vn,
4399 &obj->vma_list, obj_link) {
4400 GEM_BUG_ON(i915_vma_is_active(vma));
4401 vma->flags &= ~I915_VMA_PIN_MASK;
4402 i915_vma_close(vma);
4404 GEM_BUG_ON(!list_empty(&obj->vma_list));
4405 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4407 list_del(&obj->global_link);
4409 intel_runtime_pm_put(i915);
4410 mutex_unlock(&i915->drm.struct_mutex);
4414 llist_for_each_entry_safe(obj, on, freed, freed) {
4415 GEM_BUG_ON(obj->bind_count);
4416 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4418 if (obj->ops->release)
4419 obj->ops->release(obj);
4421 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4422 atomic_set(&obj->mm.pages_pin_count, 0);
4423 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4424 GEM_BUG_ON(obj->mm.pages);
4426 if (obj->base.import_attach)
4427 drm_prime_gem_destroy(&obj->base, NULL);
4429 reservation_object_fini(&obj->__builtin_resv);
4430 drm_gem_object_release(&obj->base);
4431 i915_gem_info_remove_obj(i915, obj->base.size);
4434 i915_gem_object_free(obj);
4438 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4440 struct llist_node *freed;
4442 freed = llist_del_all(&i915->mm.free_list);
4443 if (unlikely(freed))
4444 __i915_gem_free_objects(i915, freed);
4447 static void __i915_gem_free_work(struct work_struct *work)
4449 struct drm_i915_private *i915 =
4450 container_of(work, struct drm_i915_private, mm.free_work);
4451 struct llist_node *freed;
4453 /* All file-owned VMA should have been released by this point through
4454 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4455 * However, the object may also be bound into the global GTT (e.g.
4456 * older GPUs without per-process support, or for direct access through
4457 * the GTT either for the user or for scanout). Those VMA still need to
4461 while ((freed = llist_del_all(&i915->mm.free_list))) {
4462 __i915_gem_free_objects(i915, freed);
4468 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4470 struct drm_i915_gem_object *obj =
4471 container_of(head, typeof(*obj), rcu);
4472 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4474 /* We can't simply use call_rcu() from i915_gem_free_object()
4475 * as we need to block whilst unbinding, and the call_rcu
4476 * task may be called from softirq context. So we take a
4477 * detour through a worker.
4479 if (llist_add(&obj->freed, &i915->mm.free_list))
4480 schedule_work(&i915->mm.free_work);
4483 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4485 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4487 if (obj->mm.quirked)
4488 __i915_gem_object_unpin_pages(obj);
4490 if (discard_backing_storage(obj))
4491 obj->mm.madv = I915_MADV_DONTNEED;
4493 /* Before we free the object, make sure any pure RCU-only
4494 * read-side critical sections are complete, e.g.
4495 * i915_gem_busy_ioctl(). For the corresponding synchronized
4496 * lookup see i915_gem_object_lookup_rcu().
4498 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4501 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4503 lockdep_assert_held(&obj->base.dev->struct_mutex);
4505 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4506 if (i915_gem_object_is_active(obj))
4507 i915_gem_object_set_active_reference(obj);
4509 i915_gem_object_put(obj);
4512 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4514 struct intel_engine_cs *engine;
4515 enum intel_engine_id id;
4517 for_each_engine(engine, dev_priv, id)
4518 GEM_BUG_ON(engine->last_retired_context &&
4519 !i915_gem_context_is_kernel(engine->last_retired_context));
4522 void i915_gem_sanitize(struct drm_i915_private *i915)
4525 * If we inherit context state from the BIOS or earlier occupants
4526 * of the GPU, the GPU may be in an inconsistent state when we
4527 * try to take over. The only way to remove the earlier state
4528 * is by resetting. However, resetting on earlier gen is tricky as
4529 * it may impact the display and we are uncertain about the stability
4530 * of the reset, so this could be applied to even earlier gen.
4532 if (INTEL_GEN(i915) >= 5) {
4533 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4534 WARN_ON(reset && reset != -ENODEV);
4538 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4540 struct drm_device *dev = &dev_priv->drm;
4543 intel_runtime_pm_get(dev_priv);
4544 intel_suspend_gt_powersave(dev_priv);
4546 mutex_lock(&dev->struct_mutex);
4548 /* We have to flush all the executing contexts to main memory so
4549 * that they can saved in the hibernation image. To ensure the last
4550 * context image is coherent, we have to switch away from it. That
4551 * leaves the dev_priv->kernel_context still active when
4552 * we actually suspend, and its image in memory may not match the GPU
4553 * state. Fortunately, the kernel_context is disposable and we do
4554 * not rely on its state.
4556 ret = i915_gem_switch_to_kernel_context(dev_priv);
4560 ret = i915_gem_wait_for_idle(dev_priv,
4561 I915_WAIT_INTERRUPTIBLE |
4566 assert_kernel_context_is_current(dev_priv);
4567 i915_gem_context_lost(dev_priv);
4568 mutex_unlock(&dev->struct_mutex);
4570 intel_guc_suspend(dev_priv);
4572 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4573 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4575 /* As the idle_work is rearming if it detects a race, play safe and
4576 * repeat the flush until it is definitely idle.
4578 while (flush_delayed_work(&dev_priv->gt.idle_work))
4581 i915_gem_drain_freed_objects(dev_priv);
4583 /* Assert that we sucessfully flushed all the work and
4584 * reset the GPU back to its idle, low power state.
4586 WARN_ON(dev_priv->gt.awake);
4587 WARN_ON(!intel_engines_are_idle(dev_priv));
4590 * Neither the BIOS, ourselves or any other kernel
4591 * expects the system to be in execlists mode on startup,
4592 * so we need to reset the GPU back to legacy mode. And the only
4593 * known way to disable logical contexts is through a GPU reset.
4595 * So in order to leave the system in a known default configuration,
4596 * always reset the GPU upon unload and suspend. Afterwards we then
4597 * clean up the GEM state tracking, flushing off the requests and
4598 * leaving the system in a known idle state.
4600 * Note that is of the upmost importance that the GPU is idle and
4601 * all stray writes are flushed *before* we dismantle the backing
4602 * storage for the pinned objects.
4604 * However, since we are uncertain that resetting the GPU on older
4605 * machines is a good idea, we don't - just in case it leaves the
4606 * machine in an unusable condition.
4608 i915_gem_sanitize(dev_priv);
4612 mutex_unlock(&dev->struct_mutex);
4614 intel_runtime_pm_put(dev_priv);
4618 void i915_gem_resume(struct drm_i915_private *dev_priv)
4620 struct drm_device *dev = &dev_priv->drm;
4622 WARN_ON(dev_priv->gt.awake);
4624 mutex_lock(&dev->struct_mutex);
4625 i915_gem_restore_gtt_mappings(dev_priv);
4627 /* As we didn't flush the kernel context before suspend, we cannot
4628 * guarantee that the context image is complete. So let's just reset
4629 * it and start again.
4631 dev_priv->gt.resume(dev_priv);
4633 mutex_unlock(&dev->struct_mutex);
4636 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4638 if (INTEL_GEN(dev_priv) < 5 ||
4639 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4642 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4643 DISP_TILE_SURFACE_SWIZZLING);
4645 if (IS_GEN5(dev_priv))
4648 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4649 if (IS_GEN6(dev_priv))
4650 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4651 else if (IS_GEN7(dev_priv))
4652 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4653 else if (IS_GEN8(dev_priv))
4654 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4659 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4661 I915_WRITE(RING_CTL(base), 0);
4662 I915_WRITE(RING_HEAD(base), 0);
4663 I915_WRITE(RING_TAIL(base), 0);
4664 I915_WRITE(RING_START(base), 0);
4667 static void init_unused_rings(struct drm_i915_private *dev_priv)
4669 if (IS_I830(dev_priv)) {
4670 init_unused_ring(dev_priv, PRB1_BASE);
4671 init_unused_ring(dev_priv, SRB0_BASE);
4672 init_unused_ring(dev_priv, SRB1_BASE);
4673 init_unused_ring(dev_priv, SRB2_BASE);
4674 init_unused_ring(dev_priv, SRB3_BASE);
4675 } else if (IS_GEN2(dev_priv)) {
4676 init_unused_ring(dev_priv, SRB0_BASE);
4677 init_unused_ring(dev_priv, SRB1_BASE);
4678 } else if (IS_GEN3(dev_priv)) {
4679 init_unused_ring(dev_priv, PRB1_BASE);
4680 init_unused_ring(dev_priv, PRB2_BASE);
4684 static int __i915_gem_restart_engines(void *data)
4686 struct drm_i915_private *i915 = data;
4687 struct intel_engine_cs *engine;
4688 enum intel_engine_id id;
4691 for_each_engine(engine, i915, id) {
4692 err = engine->init_hw(engine);
4700 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4704 dev_priv->gt.last_init_time = ktime_get();
4706 /* Double layer security blanket, see i915_gem_init() */
4707 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4709 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4710 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4712 if (IS_HASWELL(dev_priv))
4713 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4714 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4716 if (HAS_PCH_NOP(dev_priv)) {
4717 if (IS_IVYBRIDGE(dev_priv)) {
4718 u32 temp = I915_READ(GEN7_MSG_CTL);
4719 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4720 I915_WRITE(GEN7_MSG_CTL, temp);
4721 } else if (INTEL_GEN(dev_priv) >= 7) {
4722 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4723 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4724 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4728 i915_gem_init_swizzling(dev_priv);
4731 * At least 830 can leave some of the unused rings
4732 * "active" (ie. head != tail) after resume which
4733 * will prevent c3 entry. Makes sure all unused rings
4736 init_unused_rings(dev_priv);
4738 BUG_ON(!dev_priv->kernel_context);
4740 ret = i915_ppgtt_init_hw(dev_priv);
4742 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4746 /* Need to do basic initialisation of all rings first: */
4747 ret = __i915_gem_restart_engines(dev_priv);
4751 intel_mocs_init_l3cc_table(dev_priv);
4753 /* We can't enable contexts until all firmware is loaded */
4754 ret = intel_uc_init_hw(dev_priv);
4759 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4763 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4765 if (INTEL_INFO(dev_priv)->gen < 6)
4768 /* TODO: make semaphores and Execlists play nicely together */
4769 if (i915.enable_execlists)
4775 /* Enable semaphores on SNB when IO remapping is off */
4776 if (IS_GEN6(dev_priv) && intel_vtd_active())
4782 int i915_gem_init(struct drm_i915_private *dev_priv)
4786 mutex_lock(&dev_priv->drm.struct_mutex);
4788 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
4790 if (!i915.enable_execlists) {
4791 dev_priv->gt.resume = intel_legacy_submission_resume;
4792 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4794 dev_priv->gt.resume = intel_lr_context_resume;
4795 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4798 /* This is just a security blanket to placate dragons.
4799 * On some systems, we very sporadically observe that the first TLBs
4800 * used by the CS may be stale, despite us poking the TLB reset. If
4801 * we hold the forcewake during initialisation these problems
4802 * just magically go away.
4804 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4806 ret = i915_gem_init_userptr(dev_priv);
4810 ret = i915_gem_init_ggtt(dev_priv);
4814 ret = i915_gem_context_init(dev_priv);
4818 ret = intel_engines_init(dev_priv);
4822 ret = i915_gem_init_hw(dev_priv);
4824 /* Allow engine initialisation to fail by marking the GPU as
4825 * wedged. But we only want to do this where the GPU is angry,
4826 * for all other failure, such as an allocation failure, bail.
4828 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4829 i915_gem_set_wedged(dev_priv);
4834 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4835 mutex_unlock(&dev_priv->drm.struct_mutex);
4840 void i915_gem_init_mmio(struct drm_i915_private *i915)
4842 i915_gem_sanitize(i915);
4846 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4848 struct intel_engine_cs *engine;
4849 enum intel_engine_id id;
4851 for_each_engine(engine, dev_priv, id)
4852 dev_priv->gt.cleanup_engine(engine);
4856 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4860 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4861 !IS_CHERRYVIEW(dev_priv))
4862 dev_priv->num_fence_regs = 32;
4863 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4864 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4865 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4866 dev_priv->num_fence_regs = 16;
4868 dev_priv->num_fence_regs = 8;
4870 if (intel_vgpu_active(dev_priv))
4871 dev_priv->num_fence_regs =
4872 I915_READ(vgtif_reg(avail_rs.fence_num));
4874 /* Initialize fence registers to zero */
4875 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4876 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4878 fence->i915 = dev_priv;
4880 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4882 i915_gem_restore_fences(dev_priv);
4884 i915_gem_detect_bit_6_swizzle(dev_priv);
4888 i915_gem_load_init(struct drm_i915_private *dev_priv)
4892 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4893 if (!dev_priv->objects)
4896 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4897 if (!dev_priv->vmas)
4900 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4901 SLAB_HWCACHE_ALIGN |
4902 SLAB_RECLAIM_ACCOUNT |
4903 SLAB_TYPESAFE_BY_RCU);
4904 if (!dev_priv->requests)
4907 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4908 SLAB_HWCACHE_ALIGN |
4909 SLAB_RECLAIM_ACCOUNT);
4910 if (!dev_priv->dependencies)
4913 dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
4914 if (!dev_priv->priorities)
4915 goto err_dependencies;
4917 mutex_lock(&dev_priv->drm.struct_mutex);
4918 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4919 err = i915_gem_timeline_init__global(dev_priv);
4920 mutex_unlock(&dev_priv->drm.struct_mutex);
4922 goto err_priorities;
4924 INIT_LIST_HEAD(&dev_priv->context_list);
4925 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4926 init_llist_head(&dev_priv->mm.free_list);
4927 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4928 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4929 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4930 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4931 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4932 i915_gem_retire_work_handler);
4933 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4934 i915_gem_idle_work_handler);
4935 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4936 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4938 init_waitqueue_head(&dev_priv->pending_flip_queue);
4940 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4942 spin_lock_init(&dev_priv->fb_tracking.lock);
4947 kmem_cache_destroy(dev_priv->priorities);
4949 kmem_cache_destroy(dev_priv->dependencies);
4951 kmem_cache_destroy(dev_priv->requests);
4953 kmem_cache_destroy(dev_priv->vmas);
4955 kmem_cache_destroy(dev_priv->objects);
4960 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4962 i915_gem_drain_freed_objects(dev_priv);
4963 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4964 WARN_ON(dev_priv->mm.object_count);
4966 mutex_lock(&dev_priv->drm.struct_mutex);
4967 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4968 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4969 mutex_unlock(&dev_priv->drm.struct_mutex);
4971 kmem_cache_destroy(dev_priv->priorities);
4972 kmem_cache_destroy(dev_priv->dependencies);
4973 kmem_cache_destroy(dev_priv->requests);
4974 kmem_cache_destroy(dev_priv->vmas);
4975 kmem_cache_destroy(dev_priv->objects);
4977 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4981 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4983 /* Discard all purgeable objects, let userspace recover those as
4984 * required after resuming.
4986 i915_gem_shrink_all(dev_priv);
4991 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4993 struct drm_i915_gem_object *obj;
4994 struct list_head *phases[] = {
4995 &dev_priv->mm.unbound_list,
4996 &dev_priv->mm.bound_list,
5000 /* Called just before we write the hibernation image.
5002 * We need to update the domain tracking to reflect that the CPU
5003 * will be accessing all the pages to create and restore from the
5004 * hibernation, and so upon restoration those pages will be in the
5007 * To make sure the hibernation image contains the latest state,
5008 * we update that state just before writing out the image.
5010 * To try and reduce the hibernation image, we manually shrink
5011 * the objects as well, see i915_gem_freeze()
5014 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
5015 i915_gem_drain_freed_objects(dev_priv);
5017 mutex_lock(&dev_priv->drm.struct_mutex);
5018 for (p = phases; *p; p++) {
5019 list_for_each_entry(obj, *p, global_link)
5020 __start_cpu_write(obj);
5022 mutex_unlock(&dev_priv->drm.struct_mutex);
5027 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5029 struct drm_i915_file_private *file_priv = file->driver_priv;
5030 struct drm_i915_gem_request *request;
5032 /* Clean up our request list when the client is going away, so that
5033 * later retire_requests won't dereference our soon-to-be-gone
5036 spin_lock(&file_priv->mm.lock);
5037 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
5038 request->file_priv = NULL;
5039 spin_unlock(&file_priv->mm.lock);
5041 if (!list_empty(&file_priv->rps.link)) {
5042 spin_lock(&to_i915(dev)->rps.client_lock);
5043 list_del(&file_priv->rps.link);
5044 spin_unlock(&to_i915(dev)->rps.client_lock);
5048 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5050 struct drm_i915_file_private *file_priv;
5055 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5059 file->driver_priv = file_priv;
5060 file_priv->dev_priv = to_i915(dev);
5061 file_priv->file = file;
5062 INIT_LIST_HEAD(&file_priv->rps.link);
5064 spin_lock_init(&file_priv->mm.lock);
5065 INIT_LIST_HEAD(&file_priv->mm.request_list);
5067 file_priv->bsd_engine = -1;
5069 ret = i915_gem_context_open(dev, file);
5077 * i915_gem_track_fb - update frontbuffer tracking
5078 * @old: current GEM buffer for the frontbuffer slots
5079 * @new: new GEM buffer for the frontbuffer slots
5080 * @frontbuffer_bits: bitmask of frontbuffer slots
5082 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5083 * from @old and setting them in @new. Both @old and @new can be NULL.
5085 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5086 struct drm_i915_gem_object *new,
5087 unsigned frontbuffer_bits)
5089 /* Control of individual bits within the mask are guarded by
5090 * the owning plane->mutex, i.e. we can never see concurrent
5091 * manipulation of individual bits. But since the bitfield as a whole
5092 * is updated using RMW, we need to use atomics in order to update
5095 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
5096 sizeof(atomic_t) * BITS_PER_BYTE);
5099 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
5100 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
5104 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
5105 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
5109 /* Allocate a new GEM object and fill it with the supplied data */
5110 struct drm_i915_gem_object *
5111 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
5112 const void *data, size_t size)
5114 struct drm_i915_gem_object *obj;
5119 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
5123 GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
5125 file = obj->base.filp;
5128 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
5130 void *pgdata, *vaddr;
5132 err = pagecache_write_begin(file, file->f_mapping,
5139 memcpy(vaddr, data, len);
5142 err = pagecache_write_end(file, file->f_mapping,
5156 i915_gem_object_put(obj);
5157 return ERR_PTR(err);
5160 struct scatterlist *
5161 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
5163 unsigned int *offset)
5165 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
5166 struct scatterlist *sg;
5167 unsigned int idx, count;
5170 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
5171 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
5173 /* As we iterate forward through the sg, we record each entry in a
5174 * radixtree for quick repeated (backwards) lookups. If we have seen
5175 * this index previously, we will have an entry for it.
5177 * Initial lookup is O(N), but this is amortized to O(1) for
5178 * sequential page access (where each new request is consecutive
5179 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5180 * i.e. O(1) with a large constant!
5182 if (n < READ_ONCE(iter->sg_idx))
5185 mutex_lock(&iter->lock);
5187 /* We prefer to reuse the last sg so that repeated lookup of this
5188 * (or the subsequent) sg are fast - comparing against the last
5189 * sg is faster than going through the radixtree.
5194 count = __sg_page_count(sg);
5196 while (idx + count <= n) {
5197 unsigned long exception, i;
5200 /* If we cannot allocate and insert this entry, or the
5201 * individual pages from this range, cancel updating the
5202 * sg_idx so that on this lookup we are forced to linearly
5203 * scan onwards, but on future lookups we will try the
5204 * insertion again (in which case we need to be careful of
5205 * the error return reporting that we have already inserted
5208 ret = radix_tree_insert(&iter->radix, idx, sg);
5209 if (ret && ret != -EEXIST)
5213 RADIX_TREE_EXCEPTIONAL_ENTRY |
5214 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5215 for (i = 1; i < count; i++) {
5216 ret = radix_tree_insert(&iter->radix, idx + i,
5218 if (ret && ret != -EEXIST)
5223 sg = ____sg_next(sg);
5224 count = __sg_page_count(sg);
5231 mutex_unlock(&iter->lock);
5233 if (unlikely(n < idx)) /* insertion completed by another thread */
5236 /* In case we failed to insert the entry into the radixtree, we need
5237 * to look beyond the current sg.
5239 while (idx + count <= n) {
5241 sg = ____sg_next(sg);
5242 count = __sg_page_count(sg);
5251 sg = radix_tree_lookup(&iter->radix, n);
5254 /* If this index is in the middle of multi-page sg entry,
5255 * the radixtree will contain an exceptional entry that points
5256 * to the start of that range. We will return the pointer to
5257 * the base page and the offset of this page within the
5261 if (unlikely(radix_tree_exception(sg))) {
5262 unsigned long base =
5263 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5265 sg = radix_tree_lookup(&iter->radix, base);
5277 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5279 struct scatterlist *sg;
5280 unsigned int offset;
5282 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5284 sg = i915_gem_object_get_sg(obj, n, &offset);
5285 return nth_page(sg_page(sg), offset);
5288 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5290 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5295 page = i915_gem_object_get_page(obj, n);
5297 set_page_dirty(page);
5303 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5306 struct scatterlist *sg;
5307 unsigned int offset;
5309 sg = i915_gem_object_get_sg(obj, n, &offset);
5310 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5313 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5314 #include "selftests/scatterlist.c"
5315 #include "selftests/mock_gem_device.c"
5316 #include "selftests/huge_gem_object.c"
5317 #include "selftests/i915_gem_object.c"
5318 #include "selftests/i915_gem_coherency.c"