drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  65
  66 static bool cpu_cache_is_coherent(struct drm_device *dev,
  67                                   enum i915_cache_level level)
  68 {
  69         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  70 }
  71
  72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  73 {
  74         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  75                 return true;
  76
  77         return obj->pin_display;
  78 }
  79
  80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  81 {
  82         if (obj->tiling_mode)
  83                 i915_gem_release_mmap(obj);
  84
  85         /* As we do not have an associated fence register, we will force
  86          * a tiling change if we ever need to acquire one.
  87          */
  88         obj->fence_dirty = false;
  89         obj->fence_reg = I915_FENCE_REG_NONE;
  90 }
  91
  92 /* some bookkeeping */
  93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  94                                   size_t size)
  95 {
  96         spin_lock(&dev_priv->mm.object_stat_lock);
  97         dev_priv->mm.object_count++;
  98         dev_priv->mm.object_memory += size;
  99         spin_unlock(&dev_priv->mm.object_stat_lock);
 100 }
 101
 102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 103                                      size_t size)
 104 {
 105         spin_lock(&dev_priv->mm.object_stat_lock);
 106         dev_priv->mm.object_count--;
 107         dev_priv->mm.object_memory -= size;
 108         spin_unlock(&dev_priv->mm.object_stat_lock);
 109 }
 110
 111 static int
 112 i915_gem_wait_for_error(struct i915_gpu_error *error)
 113 {
 114         int ret;
 115
 116 #define EXIT_COND (!i915_reset_in_progress(error) || \
 117                    i915_terminally_wedged(error))
 118         if (EXIT_COND)
 119                 return 0;
 120
 121         /*
 122          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 123          * userspace. If it takes that long something really bad is going on and
 124          * we should simply try to bail out and fail as gracefully as possible.
 125          */
 126         ret = wait_event_interruptible_timeout(error->reset_queue,
 127                                                EXIT_COND,
 128                                                10*HZ);
 129         if (ret == 0) {
 130                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 131                 return -EIO;
 132         } else if (ret < 0) {
 133                 return ret;
 134         }
 135 #undef EXIT_COND
 136
 137         return 0;
 138 }
 139
 140 int i915_mutex_lock_interruptible(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         int ret;
 144
 145         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 146         if (ret)
 147                 return ret;
 148
 149         ret = mutex_lock_interruptible(&dev->struct_mutex);
 150         if (ret)
 151                 return ret;
 152
 153         WARN_ON(i915_verify_lists(dev));
 154         return 0;
 155 }
 156
 157 static inline bool
 158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 159 {
 160         return i915_gem_obj_bound_any(obj) && !obj->active;
 161 }
 162
 163 int
 164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 165                     struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_init *args = data;
 169
 170         if (drm_core_check_feature(dev, DRIVER_MODESET))
 171                 return -ENODEV;
 172
 173         if (args->gtt_start >= args->gtt_end ||
 174             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 175                 return -EINVAL;
 176
 177         /* GEM with user mode setting was never supported on ilk and later. */
 178         if (INTEL_INFO(dev)->gen >= 5)
 179                 return -ENODEV;
 180
 181         mutex_lock(&dev->struct_mutex);
 182         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 183                                   args->gtt_end);
 184         dev_priv->gtt.mappable_end = args->gtt_end;
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         return 0;
 188 }
 189
 190 int
 191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *file)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         struct drm_i915_gem_get_aperture *args = data;
 196         struct drm_i915_gem_object *obj;
 197         size_t pinned;
 198
 199         pinned = 0;
 200         mutex_lock(&dev->struct_mutex);
 201         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 202                 if (i915_gem_obj_is_pinned(obj))
 203                         pinned += i915_gem_obj_ggtt_size(obj);
 204         mutex_unlock(&dev->struct_mutex);
 205
 206         args->aper_size = dev_priv->gtt.base.total;
 207         args->aper_available_size = args->aper_size - pinned;
 208
 209         return 0;
 210 }
 211
 212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
 213 {
 214         drm_dma_handle_t *phys = obj->phys_handle;
 215
 216         if (!phys)
 217                 return;
 218
 219         if (obj->madv == I915_MADV_WILLNEED) {
 220                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 221                 char *vaddr = phys->vaddr;
 222                 int i;
 223
 224                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 225                         struct page *page = shmem_read_mapping_page(mapping, i);
 226                         if (!IS_ERR(page)) {
 227                                 char *dst = kmap_atomic(page);
 228                                 memcpy(dst, vaddr, PAGE_SIZE);
 229                                 drm_clflush_virt_range(dst, PAGE_SIZE);
 230                                 kunmap_atomic(dst);
 231
 232                                 set_page_dirty(page);
 233                                 mark_page_accessed(page);
 234                                 page_cache_release(page);
 235                         }
 236                         vaddr += PAGE_SIZE;
 237                 }
 238                 i915_gem_chipset_flush(obj->base.dev);
 239         }
 240
 241 #ifdef CONFIG_X86
 242         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 243 #endif
 244         drm_pci_free(obj->base.dev, phys);
 245         obj->phys_handle = NULL;
 246 }
 247
 248 int
 249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 250                             int align)
 251 {
 252         drm_dma_handle_t *phys;
 253         struct address_space *mapping;
 254         char *vaddr;
 255         int i;
 256
 257         if (obj->phys_handle) {
 258                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 259                         return -EBUSY;
 260
 261                 return 0;
 262         }
 263
 264         if (obj->madv != I915_MADV_WILLNEED)
 265                 return -EFAULT;
 266
 267         if (obj->base.filp == NULL)
 268                 return -EINVAL;
 269
 270         /* create a new object */
 271         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 272         if (!phys)
 273                 return -ENOMEM;
 274
 275         vaddr = phys->vaddr;
 276 #ifdef CONFIG_X86
 277         set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
 278 #endif
 279         mapping = file_inode(obj->base.filp)->i_mapping;
 280         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 281                 struct page *page;
 282                 char *src;
 283
 284                 page = shmem_read_mapping_page(mapping, i);
 285                 if (IS_ERR(page)) {
 286 #ifdef CONFIG_X86
 287                         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 288 #endif
 289                         drm_pci_free(obj->base.dev, phys);
 290                         return PTR_ERR(page);
 291                 }
 292
 293                 src = kmap_atomic(page);
 294                 memcpy(vaddr, src, PAGE_SIZE);
 295                 kunmap_atomic(src);
 296
 297                 mark_page_accessed(page);
 298                 page_cache_release(page);
 299
 300                 vaddr += PAGE_SIZE;
 301         }
 302
 303         obj->phys_handle = phys;
 304         return 0;
 305 }
 306
 307 static int
 308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 309                      struct drm_i915_gem_pwrite *args,
 310                      struct drm_file *file_priv)
 311 {
 312         struct drm_device *dev = obj->base.dev;
 313         void *vaddr = obj->phys_handle->vaddr + args->offset;
 314         char __user *user_data = to_user_ptr(args->data_ptr);
 315
 316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 317                 unsigned long unwritten;
 318
 319                 /* The physical object once assigned is fixed for the lifetime
 320                  * of the obj, so we can safely drop the lock and continue
 321                  * to access vaddr.
 322                  */
 323                 mutex_unlock(&dev->struct_mutex);
 324                 unwritten = copy_from_user(vaddr, user_data, args->size);
 325                 mutex_lock(&dev->struct_mutex);
 326                 if (unwritten)
 327                         return -EFAULT;
 328         }
 329
 330         i915_gem_chipset_flush(dev);
 331         return 0;
 332 }
 333
 334 void *i915_gem_object_alloc(struct drm_device *dev)
 335 {
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 338 }
 339
 340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 341 {
 342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 343         kmem_cache_free(dev_priv->slab, obj);
 344 }
 345
 346 static int
 347 i915_gem_create(struct drm_file *file,
 348                 struct drm_device *dev,
 349                 uint64_t size,
 350                 uint32_t *handle_p)
 351 {
 352         struct drm_i915_gem_object *obj;
 353         int ret;
 354         u32 handle;
 355
 356         size = roundup(size, PAGE_SIZE);
 357         if (size == 0)
 358                 return -EINVAL;
 359
 360         /* Allocate the new object */
 361         obj = i915_gem_alloc_object(dev, size);
 362         if (obj == NULL)
 363                 return -ENOMEM;
 364
 365         ret = drm_gem_handle_create(file, &obj->base, &handle);
 366         /* drop reference from allocate - handle holds it now */
 367         drm_gem_object_unreference_unlocked(&obj->base);
 368         if (ret)
 369                 return ret;
 370
 371         *handle_p = handle;
 372         return 0;
 373 }
 374
 375 int
 376 i915_gem_dumb_create(struct drm_file *file,
 377                      struct drm_device *dev,
 378                      struct drm_mode_create_dumb *args)
 379 {
 380         /* have to work out size/pitch and return them */
 381         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 382         args->size = args->pitch * args->height;
 383         return i915_gem_create(file, dev,
 384                                args->size, &args->handle);
 385 }
 386
 387 /**
 388  * Creates a new mm object and returns a handle to it.
 389  */
 390 int
 391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 392                       struct drm_file *file)
 393 {
 394         struct drm_i915_gem_create *args = data;
 395
 396         return i915_gem_create(file, dev,
 397                                args->size, &args->handle);
 398 }
 399
 400 static inline int
 401 __copy_to_user_swizzled(char __user *cpu_vaddr,
 402                         const char *gpu_vaddr, int gpu_offset,
 403                         int length)
 404 {
 405         int ret, cpu_offset = 0;
 406
 407         while (length > 0) {
 408                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 409                 int this_length = min(cacheline_end - gpu_offset, length);
 410                 int swizzled_gpu_offset = gpu_offset ^ 64;
 411
 412                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 413                                      gpu_vaddr + swizzled_gpu_offset,
 414                                      this_length);
 415                 if (ret)
 416                         return ret + length;
 417
 418                 cpu_offset += this_length;
 419                 gpu_offset += this_length;
 420                 length -= this_length;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static inline int
 427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 428                           const char __user *cpu_vaddr,
 429                           int length)
 430 {
 431         int ret, cpu_offset = 0;
 432
 433         while (length > 0) {
 434                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 435                 int this_length = min(cacheline_end - gpu_offset, length);
 436                 int swizzled_gpu_offset = gpu_offset ^ 64;
 437
 438                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 439                                        cpu_vaddr + cpu_offset,
 440                                        this_length);
 441                 if (ret)
 442                         return ret + length;
 443
 444                 cpu_offset += this_length;
 445                 gpu_offset += this_length;
 446                 length -= this_length;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * Pins the specified object's pages and synchronizes the object with
 454  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 455  * flush the object from the CPU cache.
 456  */
 457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 458                                     int *needs_clflush)
 459 {
 460         int ret;
 461
 462         *needs_clflush = 0;
 463
 464         if (!obj->base.filp)
 465                 return -EINVAL;
 466
 467         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 468                 /* If we're not in the cpu read domain, set ourself into the gtt
 469                  * read domain and manually flush cachelines (if required). This
 470                  * optimizes for the case when the gpu will dirty the data
 471                  * anyway again before the next pread happens. */
 472                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 473                                                         obj->cache_level);
 474                 ret = i915_gem_object_wait_rendering(obj, true);
 475                 if (ret)
 476                         return ret;
 477
 478                 i915_gem_object_retire(obj);
 479         }
 480
 481         ret = i915_gem_object_get_pages(obj);
 482         if (ret)
 483                 return ret;
 484
 485         i915_gem_object_pin_pages(obj);
 486
 487         return ret;
 488 }
 489
 490 /* Per-page copy function for the shmem pread fastpath.
 491  * Flushes invalid cachelines before reading the target if
 492  * needs_clflush is set. */
 493 static int
 494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 495                  char __user *user_data,
 496                  bool page_do_bit17_swizzling, bool needs_clflush)
 497 {
 498         char *vaddr;
 499         int ret;
 500
 501         if (unlikely(page_do_bit17_swizzling))
 502                 return -EINVAL;
 503
 504         vaddr = kmap_atomic(page);
 505         if (needs_clflush)
 506                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 507                                        page_length);
 508         ret = __copy_to_user_inatomic(user_data,
 509                                       vaddr + shmem_page_offset,
 510                                       page_length);
 511         kunmap_atomic(vaddr);
 512
 513         return ret ? -EFAULT : 0;
 514 }
 515
 516 static void
 517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 518                              bool swizzled)
 519 {
 520         if (unlikely(swizzled)) {
 521                 unsigned long start = (unsigned long) addr;
 522                 unsigned long end = (unsigned long) addr + length;
 523
 524                 /* For swizzling simply ensure that we always flush both
 525                  * channels. Lame, but simple and it works. Swizzled
 526                  * pwrite/pread is far from a hotpath - current userspace
 527                  * doesn't use it at all. */
 528                 start = round_down(start, 128);
 529                 end = round_up(end, 128);
 530
 531                 drm_clflush_virt_range((void *)start, end - start);
 532         } else {
 533                 drm_clflush_virt_range(addr, length);
 534         }
 535
 536 }
 537
 538 /* Only difference to the fast-path function is that this can handle bit17
 539  * and uses non-atomic copy and kmap functions. */
 540 static int
 541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         vaddr = kmap(page);
 549         if (needs_clflush)
 550                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 551                                              page_length,
 552                                              page_do_bit17_swizzling);
 553
 554         if (page_do_bit17_swizzling)
 555                 ret = __copy_to_user_swizzled(user_data,
 556                                               vaddr, shmem_page_offset,
 557                                               page_length);
 558         else
 559                 ret = __copy_to_user(user_data,
 560                                      vaddr + shmem_page_offset,
 561                                      page_length);
 562         kunmap(page);
 563
 564         return ret ? - EFAULT : 0;
 565 }
 566
 567 static int
 568 i915_gem_shmem_pread(struct drm_device *dev,
 569                      struct drm_i915_gem_object *obj,
 570                      struct drm_i915_gem_pread *args,
 571                      struct drm_file *file)
 572 {
 573         char __user *user_data;
 574         ssize_t remain;
 575         loff_t offset;
 576         int shmem_page_offset, page_length, ret = 0;
 577         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 578         int prefaulted = 0;
 579         int needs_clflush = 0;
 580         struct sg_page_iter sg_iter;
 581
 582         user_data = to_user_ptr(args->data_ptr);
 583         remain = args->size;
 584
 585         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 586
 587         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 588         if (ret)
 589                 return ret;
 590
 591         offset = args->offset;
 592
 593         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 594                          offset >> PAGE_SHIFT) {
 595                 struct page *page = sg_page_iter_page(&sg_iter);
 596
 597                 if (remain <= 0)
 598                         break;
 599
 600                 /* Operation in this page
 601                  *
 602                  * shmem_page_offset = offset within page in shmem file
 603                  * page_length = bytes to copy for this page
 604                  */
 605                 shmem_page_offset = offset_in_page(offset);
 606                 page_length = remain;
 607                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 608                         page_length = PAGE_SIZE - shmem_page_offset;
 609
 610                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 611                         (page_to_phys(page) & (1 << 17)) != 0;
 612
 613                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 614                                        user_data, page_do_bit17_swizzling,
 615                                        needs_clflush);
 616                 if (ret == 0)
 617                         goto next_page;
 618
 619                 mutex_unlock(&dev->struct_mutex);
 620
 621                 if (likely(!i915.prefault_disable) && !prefaulted) {
 622                         ret = fault_in_multipages_writeable(user_data, remain);
 623                         /* Userspace is tricking us, but we've already clobbered
 624                          * its pages with the prefault and promised to write the
 625                          * data up to the first fault. Hence ignore any errors
 626                          * and just continue. */
 627                         (void)ret;
 628                         prefaulted = 1;
 629                 }
 630
 631                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 632                                        user_data, page_do_bit17_swizzling,
 633                                        needs_clflush);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636
 637                 if (ret)
 638                         goto out;
 639
 640 next_page:
 641                 remain -= page_length;
 642                 user_data += page_length;
 643                 offset += page_length;
 644         }
 645
 646 out:
 647         i915_gem_object_unpin_pages(obj);
 648
 649         return ret;
 650 }
 651
 652 /**
 653  * Reads data from the object referenced by handle.
 654  *
 655  * On error, the contents of *data are undefined.
 656  */
 657 int
 658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 659                      struct drm_file *file)
 660 {
 661         struct drm_i915_gem_pread *args = data;
 662         struct drm_i915_gem_object *obj;
 663         int ret = 0;
 664
 665         if (args->size == 0)
 666                 return 0;
 667
 668         if (!access_ok(VERIFY_WRITE,
 669                        to_user_ptr(args->data_ptr),
 670                        args->size))
 671                 return -EFAULT;
 672
 673         ret = i915_mutex_lock_interruptible(dev);
 674         if (ret)
 675                 return ret;
 676
 677         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 678         if (&obj->base == NULL) {
 679                 ret = -ENOENT;
 680                 goto unlock;
 681         }
 682
 683         /* Bounds check source.  */
 684         if (args->offset > obj->base.size ||
 685             args->size > obj->base.size - args->offset) {
 686                 ret = -EINVAL;
 687                 goto out;
 688         }
 689
 690         /* prime objects have no backing filp to GEM pread/pwrite
 691          * pages from.
 692          */
 693         if (!obj->base.filp) {
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         trace_i915_gem_object_pread(obj, args->offset, args->size);
 699
 700         ret = i915_gem_shmem_pread(dev, obj, args, file);
 701
 702 out:
 703         drm_gem_object_unreference(&obj->base);
 704 unlock:
 705         mutex_unlock(&dev->struct_mutex);
 706         return ret;
 707 }
 708
 709 /* This is the fast write path which cannot handle
 710  * page faults in the source data
 711  */
 712
 713 static inline int
 714 fast_user_write(struct io_mapping *mapping,
 715                 loff_t page_base, int page_offset,
 716                 char __user *user_data,
 717                 int length)
 718 {
 719         void __iomem *vaddr_atomic;
 720         void *vaddr;
 721         unsigned long unwritten;
 722
 723         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 724         /* We can use the cpu mem copy function because this is X86. */
 725         vaddr = (void __force*)vaddr_atomic + page_offset;
 726         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 727                                                       user_data, length);
 728         io_mapping_unmap_atomic(vaddr_atomic);
 729         return unwritten;
 730 }
 731
 732 /**
 733  * This is the fast pwrite path, where we copy the data directly from the
 734  * user into the GTT, uncached.
 735  */
 736 static int
 737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 738                          struct drm_i915_gem_object *obj,
 739                          struct drm_i915_gem_pwrite *args,
 740                          struct drm_file *file)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         ssize_t remain;
 744         loff_t offset, page_base;
 745         char __user *user_data;
 746         int page_offset, page_length, ret;
 747
 748         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 749         if (ret)
 750                 goto out;
 751
 752         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 753         if (ret)
 754                 goto out_unpin;
 755
 756         ret = i915_gem_object_put_fence(obj);
 757         if (ret)
 758                 goto out_unpin;
 759
 760         user_data = to_user_ptr(args->data_ptr);
 761         remain = args->size;
 762
 763         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 764
 765         while (remain > 0) {
 766                 /* Operation in this page
 767                  *
 768                  * page_base = page offset within aperture
 769                  * page_offset = offset within page
 770                  * page_length = bytes to copy for this page
 771                  */
 772                 page_base = offset & PAGE_MASK;
 773                 page_offset = offset_in_page(offset);
 774                 page_length = remain;
 775                 if ((page_offset + remain) > PAGE_SIZE)
 776                         page_length = PAGE_SIZE - page_offset;
 777
 778                 /* If we get a fault while copying data, then (presumably) our
 779                  * source page isn't available.  Return the error and we'll
 780                  * retry in the slow path.
 781                  */
 782                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 783                                     page_offset, user_data, page_length)) {
 784                         ret = -EFAULT;
 785                         goto out_unpin;
 786                 }
 787
 788                 remain -= page_length;
 789                 user_data += page_length;
 790                 offset += page_length;
 791         }
 792
 793 out_unpin:
 794         i915_gem_object_ggtt_unpin(obj);
 795 out:
 796         return ret;
 797 }
 798
 799 /* Per-page copy function for the shmem pwrite fastpath.
 800  * Flushes invalid cachelines before writing to the target if
 801  * needs_clflush_before is set and flushes out any written cachelines after
 802  * writing if needs_clflush is set. */
 803 static int
 804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 805                   char __user *user_data,
 806                   bool page_do_bit17_swizzling,
 807                   bool needs_clflush_before,
 808                   bool needs_clflush_after)
 809 {
 810         char *vaddr;
 811         int ret;
 812
 813         if (unlikely(page_do_bit17_swizzling))
 814                 return -EINVAL;
 815
 816         vaddr = kmap_atomic(page);
 817         if (needs_clflush_before)
 818                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 819                                        page_length);
 820         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 821                                         user_data, page_length);
 822         if (needs_clflush_after)
 823                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 824                                        page_length);
 825         kunmap_atomic(vaddr);
 826
 827         return ret ? -EFAULT : 0;
 828 }
 829
 830 /* Only difference to the fast-path function is that this can handle bit17
 831  * and uses non-atomic copy and kmap functions. */
 832 static int
 833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 834                   char __user *user_data,
 835                   bool page_do_bit17_swizzling,
 836                   bool needs_clflush_before,
 837                   bool needs_clflush_after)
 838 {
 839         char *vaddr;
 840         int ret;
 841
 842         vaddr = kmap(page);
 843         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 844                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 845                                              page_length,
 846                                              page_do_bit17_swizzling);
 847         if (page_do_bit17_swizzling)
 848                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 849                                                 user_data,
 850                                                 page_length);
 851         else
 852                 ret = __copy_from_user(vaddr + shmem_page_offset,
 853                                        user_data,
 854                                        page_length);
 855         if (needs_clflush_after)
 856                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 857                                              page_length,
 858                                              page_do_bit17_swizzling);
 859         kunmap(page);
 860
 861         return ret ? -EFAULT : 0;
 862 }
 863
 864 static int
 865 i915_gem_shmem_pwrite(struct drm_device *dev,
 866                       struct drm_i915_gem_object *obj,
 867                       struct drm_i915_gem_pwrite *args,
 868                       struct drm_file *file)
 869 {
 870         ssize_t remain;
 871         loff_t offset;
 872         char __user *user_data;
 873         int shmem_page_offset, page_length, ret = 0;
 874         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 875         int hit_slowpath = 0;
 876         int needs_clflush_after = 0;
 877         int needs_clflush_before = 0;
 878         struct sg_page_iter sg_iter;
 879
 880         user_data = to_user_ptr(args->data_ptr);
 881         remain = args->size;
 882
 883         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 886                 /* If we're not in the cpu write domain, set ourself into the gtt
 887                  * write domain and manually flush cachelines (if required). This
 888                  * optimizes for the case when the gpu will use the data
 889                  * right away and we therefore have to clflush anyway. */
 890                 needs_clflush_after = cpu_write_needs_clflush(obj);
 891                 ret = i915_gem_object_wait_rendering(obj, false);
 892                 if (ret)
 893                         return ret;
 894
 895                 i915_gem_object_retire(obj);
 896         }
 897         /* Same trick applies to invalidate partially written cachelines read
 898          * before writing. */
 899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 900                 needs_clflush_before =
 901                         !cpu_cache_is_coherent(dev, obj->cache_level);
 902
 903         ret = i915_gem_object_get_pages(obj);
 904         if (ret)
 905                 return ret;
 906
 907         i915_gem_object_pin_pages(obj);
 908
 909         offset = args->offset;
 910         obj->dirty = 1;
 911
 912         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 913                          offset >> PAGE_SHIFT) {
 914                 struct page *page = sg_page_iter_page(&sg_iter);
 915                 int partial_cacheline_write;
 916
 917                 if (remain <= 0)
 918                         break;
 919
 920                 /* Operation in this page
 921                  *
 922                  * shmem_page_offset = offset within page in shmem file
 923                  * page_length = bytes to copy for this page
 924                  */
 925                 shmem_page_offset = offset_in_page(offset);
 926
 927                 page_length = remain;
 928                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 929                         page_length = PAGE_SIZE - shmem_page_offset;
 930
 931                 /* If we don't overwrite a cacheline completely we need to be
 932                  * careful to have up-to-date data by first clflushing. Don't
 933                  * overcomplicate things and flush the entire patch. */
 934                 partial_cacheline_write = needs_clflush_before &&
 935                         ((shmem_page_offset | page_length)
 936                                 & (boot_cpu_data.x86_clflush_size - 1));
 937
 938                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 939                         (page_to_phys(page) & (1 << 17)) != 0;
 940
 941                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 942                                         user_data, page_do_bit17_swizzling,
 943                                         partial_cacheline_write,
 944                                         needs_clflush_after);
 945                 if (ret == 0)
 946                         goto next_page;
 947
 948                 hit_slowpath = 1;
 949                 mutex_unlock(&dev->struct_mutex);
 950                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 951                                         user_data, page_do_bit17_swizzling,
 952                                         partial_cacheline_write,
 953                                         needs_clflush_after);
 954
 955                 mutex_lock(&dev->struct_mutex);
 956
 957                 if (ret)
 958                         goto out;
 959
 960 next_page:
 961                 remain -= page_length;
 962                 user_data += page_length;
 963                 offset += page_length;
 964         }
 965
 966 out:
 967         i915_gem_object_unpin_pages(obj);
 968
 969         if (hit_slowpath) {
 970                 /*
 971                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 972                  * cachelines in-line while writing and the object moved
 973                  * out of the cpu write domain while we've dropped the lock.
 974                  */
 975                 if (!needs_clflush_after &&
 976                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 977                         if (i915_gem_clflush_object(obj, obj->pin_display))
 978                                 i915_gem_chipset_flush(dev);
 979                 }
 980         }
 981
 982         if (needs_clflush_after)
 983                 i915_gem_chipset_flush(dev);
 984
 985         return ret;
 986 }
 987
 988 /**
 989  * Writes data to the object referenced by handle.
 990  *
 991  * On error, the contents of the buffer that were to be modified are undefined.
 992  */
 993 int
 994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 995                       struct drm_file *file)
 996 {
 997         struct drm_i915_gem_pwrite *args = data;
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         if (args->size == 0)
1002                 return 0;
1003
1004         if (!access_ok(VERIFY_READ,
1005                        to_user_ptr(args->data_ptr),
1006                        args->size))
1007                 return -EFAULT;
1008
1009         if (likely(!i915.prefault_disable)) {
1010                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1011                                                    args->size);
1012                 if (ret)
1013                         return -EFAULT;
1014         }
1015
1016         ret = i915_mutex_lock_interruptible(dev);
1017         if (ret)
1018                 return ret;
1019
1020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021         if (&obj->base == NULL) {
1022                 ret = -ENOENT;
1023                 goto unlock;
1024         }
1025
1026         /* Bounds check destination. */
1027         if (args->offset > obj->base.size ||
1028             args->size > obj->base.size - args->offset) {
1029                 ret = -EINVAL;
1030                 goto out;
1031         }
1032
1033         /* prime objects have no backing filp to GEM pread/pwrite
1034          * pages from.
1035          */
1036         if (!obj->base.filp) {
1037                 ret = -EINVAL;
1038                 goto out;
1039         }
1040
1041         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1042
1043         ret = -EFAULT;
1044         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045          * it would end up going through the fenced access, and we'll get
1046          * different detiling behavior between reading and writing.
1047          * pread/pwrite currently are reading and writing from the CPU
1048          * perspective, requiring manual detiling by the client.
1049          */
1050         if (obj->phys_handle) {
1051                 ret = i915_gem_phys_pwrite(obj, args, file);
1052                 goto out;
1053         }
1054
1055         if (obj->tiling_mode == I915_TILING_NONE &&
1056             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057             cpu_write_needs_clflush(obj)) {
1058                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059                 /* Note that the gtt paths might fail with non-page-backed user
1060                  * pointers (e.g. gtt mappings when moving data between
1061                  * textures). Fallback to the shmem path in that case. */
1062         }
1063
1064         if (ret == -EFAULT || ret == -ENOSPC)
1065                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1066
1067 out:
1068         drm_gem_object_unreference(&obj->base);
1069 unlock:
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 int
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1076                      bool interruptible)
1077 {
1078         if (i915_reset_in_progress(error)) {
1079                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080                  * -EIO unconditionally for these. */
1081                 if (!interruptible)
1082                         return -EIO;
1083
1084                 /* Recovery complete, but the reset failed ... */
1085                 if (i915_terminally_wedged(error))
1086                         return -EIO;
1087
1088                 return -EAGAIN;
1089         }
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Compare seqno against outstanding lazy request. Emit a request if they are
1096  * equal.
1097  */
1098 static int
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 {
1101         int ret;
1102
1103         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1104
1105         ret = 0;
1106         if (seqno == ring->outstanding_lazy_seqno)
1107                 ret = i915_add_request(ring, NULL);
1108
1109         return ret;
1110 }
1111
1112 static void fake_irq(unsigned long data)
1113 {
1114         wake_up_process((struct task_struct *)data);
1115 }
1116
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118                        struct intel_engine_cs *ring)
1119 {
1120         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1121 }
1122
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1124 {
1125         if (file_priv == NULL)
1126                 return true;
1127
1128         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 }
1130
1131 /**
1132  * __wait_seqno - wait until execution of seqno has finished
1133  * @ring: the ring expected to report seqno
1134  * @seqno: duh!
1135  * @reset_counter: reset sequence associated with the given seqno
1136  * @interruptible: do an interruptible wait (normally yes)
1137  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1138  *
1139  * Note: It is of utmost importance that the passed in seqno and reset_counter
1140  * values have been read by the caller in an smp safe manner. Where read-side
1141  * locks are involved, it is sufficient to read the reset_counter before
1142  * unlocking the lock that protects the seqno. For lockless tricks, the
1143  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1144  * inserted.
1145  *
1146  * Returns 0 if the seqno was found within the alloted time. Else returns the
1147  * errno with remaining time filled in timeout argument.
1148  */
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150                         unsigned reset_counter,
1151                         bool interruptible,
1152                         struct timespec *timeout,
1153                         struct drm_i915_file_private *file_priv)
1154 {
1155         struct drm_device *dev = ring->dev;
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         const bool irq_test_in_progress =
1158                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1159         struct timespec before, now;
1160         DEFINE_WAIT(wait);
1161         unsigned long timeout_expire;
1162         int ret;
1163
1164         WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1165
1166         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1167                 return 0;
1168
1169         timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1170
1171         if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1172                 gen6_rps_boost(dev_priv);
1173                 if (file_priv)
1174                         mod_delayed_work(dev_priv->wq,
1175                                          &file_priv->mm.idle_work,
1176                                          msecs_to_jiffies(100));
1177         }
1178
1179         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1180                 return -ENODEV;
1181
1182         /* Record current time in case interrupted by signal, or wedged */
1183         trace_i915_gem_request_wait_begin(ring, seqno);
1184         getrawmonotonic(&before);
1185         for (;;) {
1186                 struct timer_list timer;
1187
1188                 prepare_to_wait(&ring->irq_queue, &wait,
1189                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1190
1191                 /* We need to check whether any gpu reset happened in between
1192                  * the caller grabbing the seqno and now ... */
1193                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195                          * is truely gone. */
1196                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1197                         if (ret == 0)
1198                                 ret = -EAGAIN;
1199                         break;
1200                 }
1201
1202                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1203                         ret = 0;
1204                         break;
1205                 }
1206
1207                 if (interruptible && signal_pending(current)) {
1208                         ret = -ERESTARTSYS;
1209                         break;
1210                 }
1211
1212                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1213                         ret = -ETIME;
1214                         break;
1215                 }
1216
1217                 timer.function = NULL;
1218                 if (timeout || missed_irq(dev_priv, ring)) {
1219                         unsigned long expire;
1220
1221                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223                         mod_timer(&timer, expire);
1224                 }
1225
1226                 io_schedule();
1227
1228                 if (timer.function) {
1229                         del_singleshot_timer_sync(&timer);
1230                         destroy_timer_on_stack(&timer);
1231                 }
1232         }
1233         getrawmonotonic(&now);
1234         trace_i915_gem_request_wait_end(ring, seqno);
1235
1236         if (!irq_test_in_progress)
1237                 ring->irq_put(ring);
1238
1239         finish_wait(&ring->irq_queue, &wait);
1240
1241         if (timeout) {
1242                 struct timespec sleep_time = timespec_sub(now, before);
1243                 *timeout = timespec_sub(*timeout, sleep_time);
1244                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1245                         set_normalized_timespec(timeout, 0, 0);
1246         }
1247
1248         return ret;
1249 }
1250
1251 /**
1252  * Waits for a sequence number to be signaled, and cleans up the
1253  * request and object lists appropriately for that event.
1254  */
1255 int
1256 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1257 {
1258         struct drm_device *dev = ring->dev;
1259         struct drm_i915_private *dev_priv = dev->dev_private;
1260         bool interruptible = dev_priv->mm.interruptible;
1261         int ret;
1262
1263         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1264         BUG_ON(seqno == 0);
1265
1266         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1267         if (ret)
1268                 return ret;
1269
1270         ret = i915_gem_check_olr(ring, seqno);
1271         if (ret)
1272                 return ret;
1273
1274         return __wait_seqno(ring, seqno,
1275                             atomic_read(&dev_priv->gpu_error.reset_counter),
1276                             interruptible, NULL, NULL);
1277 }
1278
1279 static int
1280 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1281                                      struct intel_engine_cs *ring)
1282 {
1283         if (!obj->active)
1284                 return 0;
1285
1286         /* Manually manage the write flush as we may have not yet
1287          * retired the buffer.
1288          *
1289          * Note that the last_write_seqno is always the earlier of
1290          * the two (read/write) seqno, so if we haved successfully waited,
1291          * we know we have passed the last write.
1292          */
1293         obj->last_write_seqno = 0;
1294
1295         return 0;
1296 }
1297
1298 /**
1299  * Ensures that all rendering to the object has completed and the object is
1300  * safe to unbind from the GTT or access from the CPU.
1301  */
1302 static __must_check int
1303 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1304                                bool readonly)
1305 {
1306         struct intel_engine_cs *ring = obj->ring;
1307         u32 seqno;
1308         int ret;
1309
1310         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1311         if (seqno == 0)
1312                 return 0;
1313
1314         ret = i915_wait_seqno(ring, seqno);
1315         if (ret)
1316                 return ret;
1317
1318         return i915_gem_object_wait_rendering__tail(obj, ring);
1319 }
1320
1321 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1322  * as the object state may change during this call.
1323  */
1324 static __must_check int
1325 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1326                                             struct drm_i915_file_private *file_priv,
1327                                             bool readonly)
1328 {
1329         struct drm_device *dev = obj->base.dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         struct intel_engine_cs *ring = obj->ring;
1332         unsigned reset_counter;
1333         u32 seqno;
1334         int ret;
1335
1336         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1337         BUG_ON(!dev_priv->mm.interruptible);
1338
1339         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1340         if (seqno == 0)
1341                 return 0;
1342
1343         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1344         if (ret)
1345                 return ret;
1346
1347         ret = i915_gem_check_olr(ring, seqno);
1348         if (ret)
1349                 return ret;
1350
1351         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1352         mutex_unlock(&dev->struct_mutex);
1353         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1354         mutex_lock(&dev->struct_mutex);
1355         if (ret)
1356                 return ret;
1357
1358         return i915_gem_object_wait_rendering__tail(obj, ring);
1359 }
1360
1361 /**
1362  * Called when user space prepares to use an object with the CPU, either
1363  * through the mmap ioctl's mapping or a GTT mapping.
1364  */
1365 int
1366 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1367                           struct drm_file *file)
1368 {
1369         struct drm_i915_gem_set_domain *args = data;
1370         struct drm_i915_gem_object *obj;
1371         uint32_t read_domains = args->read_domains;
1372         uint32_t write_domain = args->write_domain;
1373         int ret;
1374
1375         /* Only handle setting domains to types used by the CPU. */
1376         if (write_domain & I915_GEM_GPU_DOMAINS)
1377                 return -EINVAL;
1378
1379         if (read_domains & I915_GEM_GPU_DOMAINS)
1380                 return -EINVAL;
1381
1382         /* Having something in the write domain implies it's in the read
1383          * domain, and only that read domain.  Enforce that in the request.
1384          */
1385         if (write_domain != 0 && read_domains != write_domain)
1386                 return -EINVAL;
1387
1388         ret = i915_mutex_lock_interruptible(dev);
1389         if (ret)
1390                 return ret;
1391
1392         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1393         if (&obj->base == NULL) {
1394                 ret = -ENOENT;
1395                 goto unlock;
1396         }
1397
1398         /* Try to flush the object off the GPU without holding the lock.
1399          * We will repeat the flush holding the lock in the normal manner
1400          * to catch cases where we are gazumped.
1401          */
1402         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1403                                                           file->driver_priv,
1404                                                           !write_domain);
1405         if (ret)
1406                 goto unref;
1407
1408         if (read_domains & I915_GEM_DOMAIN_GTT) {
1409                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1410
1411                 /* Silently promote "you're not bound, there was nothing to do"
1412                  * to success, since the client was just asking us to
1413                  * make sure everything was done.
1414                  */
1415                 if (ret == -EINVAL)
1416                         ret = 0;
1417         } else {
1418                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1419         }
1420
1421 unref:
1422         drm_gem_object_unreference(&obj->base);
1423 unlock:
1424         mutex_unlock(&dev->struct_mutex);
1425         return ret;
1426 }
1427
1428 /**
1429  * Called when user space has done writes to this buffer
1430  */
1431 int
1432 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1433                          struct drm_file *file)
1434 {
1435         struct drm_i915_gem_sw_finish *args = data;
1436         struct drm_i915_gem_object *obj;
1437         int ret = 0;
1438
1439         ret = i915_mutex_lock_interruptible(dev);
1440         if (ret)
1441                 return ret;
1442
1443         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1444         if (&obj->base == NULL) {
1445                 ret = -ENOENT;
1446                 goto unlock;
1447         }
1448
1449         /* Pinned buffers may be scanout, so flush the cache */
1450         if (obj->pin_display)
1451                 i915_gem_object_flush_cpu_write_domain(obj, true);
1452
1453         drm_gem_object_unreference(&obj->base);
1454 unlock:
1455         mutex_unlock(&dev->struct_mutex);
1456         return ret;
1457 }
1458
1459 /**
1460  * Maps the contents of an object, returning the address it is mapped
1461  * into.
1462  *
1463  * While the mapping holds a reference on the contents of the object, it doesn't
1464  * imply a ref on the object itself.
1465  */
1466 int
1467 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1468                     struct drm_file *file)
1469 {
1470         struct drm_i915_gem_mmap *args = data;
1471         struct drm_gem_object *obj;
1472         unsigned long addr;
1473
1474         obj = drm_gem_object_lookup(dev, file, args->handle);
1475         if (obj == NULL)
1476                 return -ENOENT;
1477
1478         /* prime objects have no backing filp to GEM mmap
1479          * pages from.
1480          */
1481         if (!obj->filp) {
1482                 drm_gem_object_unreference_unlocked(obj);
1483                 return -EINVAL;
1484         }
1485
1486         addr = vm_mmap(obj->filp, 0, args->size,
1487                        PROT_READ | PROT_WRITE, MAP_SHARED,
1488                        args->offset);
1489         drm_gem_object_unreference_unlocked(obj);
1490         if (IS_ERR((void *)addr))
1491                 return addr;
1492
1493         args->addr_ptr = (uint64_t) addr;
1494
1495         return 0;
1496 }
1497
1498 /**
1499  * i915_gem_fault - fault a page into the GTT
1500  * vma: VMA in question
1501  * vmf: fault info
1502  *
1503  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1504  * from userspace.  The fault handler takes care of binding the object to
1505  * the GTT (if needed), allocating and programming a fence register (again,
1506  * only if needed based on whether the old reg is still valid or the object
1507  * is tiled) and inserting a new PTE into the faulting process.
1508  *
1509  * Note that the faulting process may involve evicting existing objects
1510  * from the GTT and/or fence registers to make room.  So performance may
1511  * suffer if the GTT working set is large or there are few fence registers
1512  * left.
1513  */
1514 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1515 {
1516         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1517         struct drm_device *dev = obj->base.dev;
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         pgoff_t page_offset;
1520         unsigned long pfn;
1521         int ret = 0;
1522         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1523
1524         intel_runtime_pm_get(dev_priv);
1525
1526         /* We don't use vmf->pgoff since that has the fake offset */
1527         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1528                 PAGE_SHIFT;
1529
1530         ret = i915_mutex_lock_interruptible(dev);
1531         if (ret)
1532                 goto out;
1533
1534         trace_i915_gem_object_fault(obj, page_offset, true, write);
1535
1536         /* Try to flush the object off the GPU first without holding the lock.
1537          * Upon reacquiring the lock, we will perform our sanity checks and then
1538          * repeat the flush holding the lock in the normal manner to catch cases
1539          * where we are gazumped.
1540          */
1541         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1542         if (ret)
1543                 goto unlock;
1544
1545         /* Access to snoopable pages through the GTT is incoherent. */
1546         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1547                 ret = -EFAULT;
1548                 goto unlock;
1549         }
1550
1551         /* Now bind it into the GTT if needed */
1552         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1553         if (ret)
1554                 goto unlock;
1555
1556         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1557         if (ret)
1558                 goto unpin;
1559
1560         ret = i915_gem_object_get_fence(obj);
1561         if (ret)
1562                 goto unpin;
1563
1564         obj->fault_mappable = true;
1565
1566         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1567         pfn >>= PAGE_SHIFT;
1568         pfn += page_offset;
1569
1570         /* Finally, remap it using the new GTT offset */
1571         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1572 unpin:
1573         i915_gem_object_ggtt_unpin(obj);
1574 unlock:
1575         mutex_unlock(&dev->struct_mutex);
1576 out:
1577         switch (ret) {
1578         case -EIO:
1579                 /* If this -EIO is due to a gpu hang, give the reset code a
1580                  * chance to clean up the mess. Otherwise return the proper
1581                  * SIGBUS. */
1582                 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1583                         ret = VM_FAULT_SIGBUS;
1584                         break;
1585                 }
1586         case -EAGAIN:
1587                 /*
1588                  * EAGAIN means the gpu is hung and we'll wait for the error
1589                  * handler to reset everything when re-faulting in
1590                  * i915_mutex_lock_interruptible.
1591                  */
1592         case 0:
1593         case -ERESTARTSYS:
1594         case -EINTR:
1595         case -EBUSY:
1596                 /*
1597                  * EBUSY is ok: this just means that another thread
1598                  * already did the job.
1599                  */
1600                 ret = VM_FAULT_NOPAGE;
1601                 break;
1602         case -ENOMEM:
1603                 ret = VM_FAULT_OOM;
1604                 break;
1605         case -ENOSPC:
1606         case -EFAULT:
1607                 ret = VM_FAULT_SIGBUS;
1608                 break;
1609         default:
1610                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1611                 ret = VM_FAULT_SIGBUS;
1612                 break;
1613         }
1614
1615         intel_runtime_pm_put(dev_priv);
1616         return ret;
1617 }
1618
1619 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1620 {
1621         struct i915_vma *vma;
1622
1623         /*
1624          * Only the global gtt is relevant for gtt memory mappings, so restrict
1625          * list traversal to objects bound into the global address space. Note
1626          * that the active list should be empty, but better safe than sorry.
1627          */
1628         WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1629         list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1630                 i915_gem_release_mmap(vma->obj);
1631         list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1632                 i915_gem_release_mmap(vma->obj);
1633 }
1634
1635 /**
1636  * i915_gem_release_mmap - remove physical page mappings
1637  * @obj: obj in question
1638  *
1639  * Preserve the reservation of the mmapping with the DRM core code, but
1640  * relinquish ownership of the pages back to the system.
1641  *
1642  * It is vital that we remove the page mapping if we have mapped a tiled
1643  * object through the GTT and then lose the fence register due to
1644  * resource pressure. Similarly if the object has been moved out of the
1645  * aperture, than pages mapped into userspace must be revoked. Removing the
1646  * mapping will then trigger a page fault on the next user access, allowing
1647  * fixup by i915_gem_fault().
1648  */
1649 void
1650 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1651 {
1652         if (!obj->fault_mappable)
1653                 return;
1654
1655         drm_vma_node_unmap(&obj->base.vma_node,
1656                            obj->base.dev->anon_inode->i_mapping);
1657         obj->fault_mappable = false;
1658 }
1659
1660 uint32_t
1661 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1662 {
1663         uint32_t gtt_size;
1664
1665         if (INTEL_INFO(dev)->gen >= 4 ||
1666             tiling_mode == I915_TILING_NONE)
1667                 return size;
1668
1669         /* Previous chips need a power-of-two fence region when tiling */
1670         if (INTEL_INFO(dev)->gen == 3)
1671                 gtt_size = 1024*1024;
1672         else
1673                 gtt_size = 512*1024;
1674
1675         while (gtt_size < size)
1676                 gtt_size <<= 1;
1677
1678         return gtt_size;
1679 }
1680
1681 /**
1682  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1683  * @obj: object to check
1684  *
1685  * Return the required GTT alignment for an object, taking into account
1686  * potential fence register mapping.
1687  */
1688 uint32_t
1689 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1690                            int tiling_mode, bool fenced)
1691 {
1692         /*
1693          * Minimum alignment is 4k (GTT page size), but might be greater
1694          * if a fence register is needed for the object.
1695          */
1696         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1697             tiling_mode == I915_TILING_NONE)
1698                 return 4096;
1699
1700         /*
1701          * Previous chips need to be aligned to the size of the smallest
1702          * fence register that can contain the object.
1703          */
1704         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1705 }
1706
1707 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1708 {
1709         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1710         int ret;
1711
1712         if (drm_vma_node_has_offset(&obj->base.vma_node))
1713                 return 0;
1714
1715         dev_priv->mm.shrinker_no_lock_stealing = true;
1716
1717         ret = drm_gem_create_mmap_offset(&obj->base);
1718         if (ret != -ENOSPC)
1719                 goto out;
1720
1721         /* Badly fragmented mmap space? The only way we can recover
1722          * space is by destroying unwanted objects. We can't randomly release
1723          * mmap_offsets as userspace expects them to be persistent for the
1724          * lifetime of the objects. The closest we can is to release the
1725          * offsets on purgeable objects by truncating it and marking it purged,
1726          * which prevents userspace from ever using that object again.
1727          */
1728         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1729         ret = drm_gem_create_mmap_offset(&obj->base);
1730         if (ret != -ENOSPC)
1731                 goto out;
1732
1733         i915_gem_shrink_all(dev_priv);
1734         ret = drm_gem_create_mmap_offset(&obj->base);
1735 out:
1736         dev_priv->mm.shrinker_no_lock_stealing = false;
1737
1738         return ret;
1739 }
1740
1741 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1742 {
1743         drm_gem_free_mmap_offset(&obj->base);
1744 }
1745
1746 int
1747 i915_gem_mmap_gtt(struct drm_file *file,
1748                   struct drm_device *dev,
1749                   uint32_t handle,
1750                   uint64_t *offset)
1751 {
1752         struct drm_i915_private *dev_priv = dev->dev_private;
1753         struct drm_i915_gem_object *obj;
1754         int ret;
1755
1756         ret = i915_mutex_lock_interruptible(dev);
1757         if (ret)
1758                 return ret;
1759
1760         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1761         if (&obj->base == NULL) {
1762                 ret = -ENOENT;
1763                 goto unlock;
1764         }
1765
1766         if (obj->base.size > dev_priv->gtt.mappable_end) {
1767                 ret = -E2BIG;
1768                 goto out;
1769         }
1770
1771         if (obj->madv != I915_MADV_WILLNEED) {
1772                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1773                 ret = -EFAULT;
1774                 goto out;
1775         }
1776
1777         ret = i915_gem_object_create_mmap_offset(obj);
1778         if (ret)
1779                 goto out;
1780
1781         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1782
1783 out:
1784         drm_gem_object_unreference(&obj->base);
1785 unlock:
1786         mutex_unlock(&dev->struct_mutex);
1787         return ret;
1788 }
1789
1790 /**
1791  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1792  * @dev: DRM device
1793  * @data: GTT mapping ioctl data
1794  * @file: GEM object info
1795  *
1796  * Simply returns the fake offset to userspace so it can mmap it.
1797  * The mmap call will end up in drm_gem_mmap(), which will set things
1798  * up so we can get faults in the handler above.
1799  *
1800  * The fault handler will take care of binding the object into the GTT
1801  * (since it may have been evicted to make room for something), allocating
1802  * a fence register, and mapping the appropriate aperture address into
1803  * userspace.
1804  */
1805 int
1806 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1807                         struct drm_file *file)
1808 {
1809         struct drm_i915_gem_mmap_gtt *args = data;
1810
1811         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1812 }
1813
1814 static inline int
1815 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1816 {
1817         return obj->madv == I915_MADV_DONTNEED;
1818 }
1819
1820 /* Immediately discard the backing storage */
1821 static void
1822 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1823 {
1824         i915_gem_object_free_mmap_offset(obj);
1825
1826         if (obj->base.filp == NULL)
1827                 return;
1828
1829         /* Our goal here is to return as much of the memory as
1830          * is possible back to the system as we are called from OOM.
1831          * To do this we must instruct the shmfs to drop all of its
1832          * backing pages, *now*.
1833          */
1834         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1835         obj->madv = __I915_MADV_PURGED;
1836 }
1837
1838 /* Try to discard unwanted pages */
1839 static void
1840 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1841 {
1842         struct address_space *mapping;
1843
1844         switch (obj->madv) {
1845         case I915_MADV_DONTNEED:
1846                 i915_gem_object_truncate(obj);
1847         case __I915_MADV_PURGED:
1848                 return;
1849         }
1850
1851         if (obj->base.filp == NULL)
1852                 return;
1853
1854         mapping = file_inode(obj->base.filp)->i_mapping,
1855         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1856 }
1857
1858 static void
1859 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1860 {
1861         struct sg_page_iter sg_iter;
1862         int ret;
1863
1864         BUG_ON(obj->madv == __I915_MADV_PURGED);
1865
1866         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1867         if (ret) {
1868                 /* In the event of a disaster, abandon all caches and
1869                  * hope for the best.
1870                  */
1871                 WARN_ON(ret != -EIO);
1872                 i915_gem_clflush_object(obj, true);
1873                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1874         }
1875
1876         if (i915_gem_object_needs_bit17_swizzle(obj))
1877                 i915_gem_object_save_bit_17_swizzle(obj);
1878
1879         if (obj->madv == I915_MADV_DONTNEED)
1880                 obj->dirty = 0;
1881
1882         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1883                 struct page *page = sg_page_iter_page(&sg_iter);
1884
1885                 if (obj->dirty)
1886                         set_page_dirty(page);
1887
1888                 if (obj->madv == I915_MADV_WILLNEED)
1889                         mark_page_accessed(page);
1890
1891                 page_cache_release(page);
1892         }
1893         obj->dirty = 0;
1894
1895         sg_free_table(obj->pages);
1896         kfree(obj->pages);
1897 }
1898
1899 int
1900 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1901 {
1902         const struct drm_i915_gem_object_ops *ops = obj->ops;
1903
1904         if (obj->pages == NULL)
1905                 return 0;
1906
1907         if (obj->pages_pin_count)
1908                 return -EBUSY;
1909
1910         BUG_ON(i915_gem_obj_bound_any(obj));
1911
1912         /* ->put_pages might need to allocate memory for the bit17 swizzle
1913          * array, hence protect them from being reaped by removing them from gtt
1914          * lists early. */
1915         list_del(&obj->global_list);
1916
1917         ops->put_pages(obj);
1918         obj->pages = NULL;
1919
1920         i915_gem_object_invalidate(obj);
1921
1922         return 0;
1923 }
1924
1925 static unsigned long
1926 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1927                   bool purgeable_only)
1928 {
1929         struct list_head still_in_list;
1930         struct drm_i915_gem_object *obj;
1931         unsigned long count = 0;
1932
1933         /*
1934          * As we may completely rewrite the (un)bound list whilst unbinding
1935          * (due to retiring requests) we have to strictly process only
1936          * one element of the list at the time, and recheck the list
1937          * on every iteration.
1938          *
1939          * In particular, we must hold a reference whilst removing the
1940          * object as we may end up waiting for and/or retiring the objects.
1941          * This might release the final reference (held by the active list)
1942          * and result in the object being freed from under us. This is
1943          * similar to the precautions the eviction code must take whilst
1944          * removing objects.
1945          *
1946          * Also note that although these lists do not hold a reference to
1947          * the object we can safely grab one here: The final object
1948          * unreferencing and the bound_list are both protected by the
1949          * dev->struct_mutex and so we won't ever be able to observe an
1950          * object on the bound_list with a reference count equals 0.
1951          */
1952         INIT_LIST_HEAD(&still_in_list);
1953         while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1954                 obj = list_first_entry(&dev_priv->mm.unbound_list,
1955                                        typeof(*obj), global_list);
1956                 list_move_tail(&obj->global_list, &still_in_list);
1957
1958                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1959                         continue;
1960
1961                 drm_gem_object_reference(&obj->base);
1962
1963                 if (i915_gem_object_put_pages(obj) == 0)
1964                         count += obj->base.size >> PAGE_SHIFT;
1965
1966                 drm_gem_object_unreference(&obj->base);
1967         }
1968         list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1969
1970         INIT_LIST_HEAD(&still_in_list);
1971         while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1972                 struct i915_vma *vma, *v;
1973
1974                 obj = list_first_entry(&dev_priv->mm.bound_list,
1975                                        typeof(*obj), global_list);
1976                 list_move_tail(&obj->global_list, &still_in_list);
1977
1978                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1979                         continue;
1980
1981                 drm_gem_object_reference(&obj->base);
1982
1983                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1984                         if (i915_vma_unbind(vma))
1985                                 break;
1986
1987                 if (i915_gem_object_put_pages(obj) == 0)
1988                         count += obj->base.size >> PAGE_SHIFT;
1989
1990                 drm_gem_object_unreference(&obj->base);
1991         }
1992         list_splice(&still_in_list, &dev_priv->mm.bound_list);
1993
1994         return count;
1995 }
1996
1997 static unsigned long
1998 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1999 {
2000         return __i915_gem_shrink(dev_priv, target, true);
2001 }
2002
2003 static unsigned long
2004 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2005 {
2006         i915_gem_evict_everything(dev_priv->dev);
2007         return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2008 }
2009
2010 static int
2011 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2012 {
2013         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2014         int page_count, i;
2015         struct address_space *mapping;
2016         struct sg_table *st;
2017         struct scatterlist *sg;
2018         struct sg_page_iter sg_iter;
2019         struct page *page;
2020         unsigned long last_pfn = 0;     /* suppress gcc warning */
2021         gfp_t gfp;
2022
2023         /* Assert that the object is not currently in any GPU domain. As it
2024          * wasn't in the GTT, there shouldn't be any way it could have been in
2025          * a GPU cache
2026          */
2027         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2028         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2029
2030         st = kmalloc(sizeof(*st), GFP_KERNEL);
2031         if (st == NULL)
2032                 return -ENOMEM;
2033
2034         page_count = obj->base.size / PAGE_SIZE;
2035         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2036                 kfree(st);
2037                 return -ENOMEM;
2038         }
2039
2040         /* Get the list of pages out of our struct file.  They'll be pinned
2041          * at this point until we release them.
2042          *
2043          * Fail silently without starting the shrinker
2044          */
2045         mapping = file_inode(obj->base.filp)->i_mapping;
2046         gfp = mapping_gfp_mask(mapping);
2047         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2048         gfp &= ~(__GFP_IO | __GFP_WAIT);
2049         sg = st->sgl;
2050         st->nents = 0;
2051         for (i = 0; i < page_count; i++) {
2052                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2053                 if (IS_ERR(page)) {
2054                         i915_gem_purge(dev_priv, page_count);
2055                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2056                 }
2057                 if (IS_ERR(page)) {
2058                         /* We've tried hard to allocate the memory by reaping
2059                          * our own buffer, now let the real VM do its job and
2060                          * go down in flames if truly OOM.
2061                          */
2062                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
2063                         gfp |= __GFP_IO | __GFP_WAIT;
2064
2065                         i915_gem_shrink_all(dev_priv);
2066                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2067                         if (IS_ERR(page))
2068                                 goto err_pages;
2069
2070                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2071                         gfp &= ~(__GFP_IO | __GFP_WAIT);
2072                 }
2073 #ifdef CONFIG_SWIOTLB
2074                 if (swiotlb_nr_tbl()) {
2075                         st->nents++;
2076                         sg_set_page(sg, page, PAGE_SIZE, 0);
2077                         sg = sg_next(sg);
2078                         continue;
2079                 }
2080 #endif
2081                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2082                         if (i)
2083                                 sg = sg_next(sg);
2084                         st->nents++;
2085                         sg_set_page(sg, page, PAGE_SIZE, 0);
2086                 } else {
2087                         sg->length += PAGE_SIZE;
2088                 }
2089                 last_pfn = page_to_pfn(page);
2090
2091                 /* Check that the i965g/gm workaround works. */
2092                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2093         }
2094 #ifdef CONFIG_SWIOTLB
2095         if (!swiotlb_nr_tbl())
2096 #endif
2097                 sg_mark_end(sg);
2098         obj->pages = st;
2099
2100         if (i915_gem_object_needs_bit17_swizzle(obj))
2101                 i915_gem_object_do_bit_17_swizzle(obj);
2102
2103         return 0;
2104
2105 err_pages:
2106         sg_mark_end(sg);
2107         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2108                 page_cache_release(sg_page_iter_page(&sg_iter));
2109         sg_free_table(st);
2110         kfree(st);
2111
2112         /* shmemfs first checks if there is enough memory to allocate the page
2113          * and reports ENOSPC should there be insufficient, along with the usual
2114          * ENOMEM for a genuine allocation failure.
2115          *
2116          * We use ENOSPC in our driver to mean that we have run out of aperture
2117          * space and so want to translate the error from shmemfs back to our
2118          * usual understanding of ENOMEM.
2119          */
2120         if (PTR_ERR(page) == -ENOSPC)
2121                 return -ENOMEM;
2122         else
2123                 return PTR_ERR(page);
2124 }
2125
2126 /* Ensure that the associated pages are gathered from the backing storage
2127  * and pinned into our object. i915_gem_object_get_pages() may be called
2128  * multiple times before they are released by a single call to
2129  * i915_gem_object_put_pages() - once the pages are no longer referenced
2130  * either as a result of memory pressure (reaping pages under the shrinker)
2131  * or as the object is itself released.
2132  */
2133 int
2134 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2135 {
2136         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2137         const struct drm_i915_gem_object_ops *ops = obj->ops;
2138         int ret;
2139
2140         if (obj->pages)
2141                 return 0;
2142
2143         if (obj->madv != I915_MADV_WILLNEED) {
2144                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2145                 return -EFAULT;
2146         }
2147
2148         BUG_ON(obj->pages_pin_count);
2149
2150         ret = ops->get_pages(obj);
2151         if (ret)
2152                 return ret;
2153
2154         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2155         return 0;
2156 }
2157
2158 static void
2159 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2160                                struct intel_engine_cs *ring)
2161 {
2162         struct drm_device *dev = obj->base.dev;
2163         struct drm_i915_private *dev_priv = dev->dev_private;
2164         u32 seqno = intel_ring_get_seqno(ring);
2165
2166         BUG_ON(ring == NULL);
2167         if (obj->ring != ring && obj->last_write_seqno) {
2168                 /* Keep the seqno relative to the current ring */
2169                 obj->last_write_seqno = seqno;
2170         }
2171         obj->ring = ring;
2172
2173         /* Add a reference if we're newly entering the active list. */
2174         if (!obj->active) {
2175                 drm_gem_object_reference(&obj->base);
2176                 obj->active = 1;
2177         }
2178
2179         list_move_tail(&obj->ring_list, &ring->active_list);
2180
2181         obj->last_read_seqno = seqno;
2182
2183         if (obj->fenced_gpu_access) {
2184                 obj->last_fenced_seqno = seqno;
2185
2186                 /* Bump MRU to take account of the delayed flush */
2187                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2188                         struct drm_i915_fence_reg *reg;
2189
2190                         reg = &dev_priv->fence_regs[obj->fence_reg];
2191                         list_move_tail(&reg->lru_list,
2192                                        &dev_priv->mm.fence_list);
2193                 }
2194         }
2195 }
2196
2197 void i915_vma_move_to_active(struct i915_vma *vma,
2198                              struct intel_engine_cs *ring)
2199 {
2200         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2201         return i915_gem_object_move_to_active(vma->obj, ring);
2202 }
2203
2204 static void
2205 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2206 {
2207         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2208         struct i915_address_space *vm;
2209         struct i915_vma *vma;
2210
2211         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2212         BUG_ON(!obj->active);
2213
2214         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2215                 vma = i915_gem_obj_to_vma(obj, vm);
2216                 if (vma && !list_empty(&vma->mm_list))
2217                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2218         }
2219
2220         list_del_init(&obj->ring_list);
2221         obj->ring = NULL;
2222
2223         obj->last_read_seqno = 0;
2224         obj->last_write_seqno = 0;
2225         obj->base.write_domain = 0;
2226
2227         obj->last_fenced_seqno = 0;
2228         obj->fenced_gpu_access = false;
2229
2230         obj->active = 0;
2231         drm_gem_object_unreference(&obj->base);
2232
2233         WARN_ON(i915_verify_lists(dev));
2234 }
2235
2236 static void
2237 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2238 {
2239         struct intel_engine_cs *ring = obj->ring;
2240
2241         if (ring == NULL)
2242                 return;
2243
2244         if (i915_seqno_passed(ring->get_seqno(ring, true),
2245                               obj->last_read_seqno))
2246                 i915_gem_object_move_to_inactive(obj);
2247 }
2248
2249 static int
2250 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2251 {
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         struct intel_engine_cs *ring;
2254         int ret, i, j;
2255
2256         /* Carefully retire all requests without writing to the rings */
2257         for_each_ring(ring, dev_priv, i) {
2258                 ret = intel_ring_idle(ring);
2259                 if (ret)
2260                         return ret;
2261         }
2262         i915_gem_retire_requests(dev);
2263
2264         /* Finally reset hw state */
2265         for_each_ring(ring, dev_priv, i) {
2266                 intel_ring_init_seqno(ring, seqno);
2267
2268                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2269                         ring->semaphore.sync_seqno[j] = 0;
2270         }
2271
2272         return 0;
2273 }
2274
2275 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2276 {
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         int ret;
2279
2280         if (seqno == 0)
2281                 return -EINVAL;
2282
2283         /* HWS page needs to be set less than what we
2284          * will inject to ring
2285          */
2286         ret = i915_gem_init_seqno(dev, seqno - 1);
2287         if (ret)
2288                 return ret;
2289
2290         /* Carefully set the last_seqno value so that wrap
2291          * detection still works
2292          */
2293         dev_priv->next_seqno = seqno;
2294         dev_priv->last_seqno = seqno - 1;
2295         if (dev_priv->last_seqno == 0)
2296                 dev_priv->last_seqno--;
2297
2298         return 0;
2299 }
2300
2301 int
2302 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2303 {
2304         struct drm_i915_private *dev_priv = dev->dev_private;
2305
2306         /* reserve 0 for non-seqno */
2307         if (dev_priv->next_seqno == 0) {
2308                 int ret = i915_gem_init_seqno(dev, 0);
2309                 if (ret)
2310                         return ret;
2311
2312                 dev_priv->next_seqno = 1;
2313         }
2314
2315         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2316         return 0;
2317 }
2318
2319 int __i915_add_request(struct intel_engine_cs *ring,
2320                        struct drm_file *file,
2321                        struct drm_i915_gem_object *obj,
2322                        u32 *out_seqno)
2323 {
2324         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2325         struct drm_i915_gem_request *request;
2326         u32 request_ring_position, request_start;
2327         int ret;
2328
2329         request_start = intel_ring_get_tail(ring);
2330         /*
2331          * Emit any outstanding flushes - execbuf can fail to emit the flush
2332          * after having emitted the batchbuffer command. Hence we need to fix
2333          * things up similar to emitting the lazy request. The difference here
2334          * is that the flush _must_ happen before the next request, no matter
2335          * what.
2336          */
2337         ret = intel_ring_flush_all_caches(ring);
2338         if (ret)
2339                 return ret;
2340
2341         request = ring->preallocated_lazy_request;
2342         if (WARN_ON(request == NULL))
2343                 return -ENOMEM;
2344
2345         /* Record the position of the start of the request so that
2346          * should we detect the updated seqno part-way through the
2347          * GPU processing the request, we never over-estimate the
2348          * position of the head.
2349          */
2350         request_ring_position = intel_ring_get_tail(ring);
2351
2352         ret = ring->add_request(ring);
2353         if (ret)
2354                 return ret;
2355
2356         request->seqno = intel_ring_get_seqno(ring);
2357         request->ring = ring;
2358         request->head = request_start;
2359         request->tail = request_ring_position;
2360
2361         /* Whilst this request exists, batch_obj will be on the
2362          * active_list, and so will hold the active reference. Only when this
2363          * request is retired will the the batch_obj be moved onto the
2364          * inactive_list and lose its active reference. Hence we do not need
2365          * to explicitly hold another reference here.
2366          */
2367         request->batch_obj = obj;
2368
2369         /* Hold a reference to the current context so that we can inspect
2370          * it later in case a hangcheck error event fires.
2371          */
2372         request->ctx = ring->last_context;
2373         if (request->ctx)
2374                 i915_gem_context_reference(request->ctx);
2375
2376         request->emitted_jiffies = jiffies;
2377         list_add_tail(&request->list, &ring->request_list);
2378         request->file_priv = NULL;
2379
2380         if (file) {
2381                 struct drm_i915_file_private *file_priv = file->driver_priv;
2382
2383                 spin_lock(&file_priv->mm.lock);
2384                 request->file_priv = file_priv;
2385                 list_add_tail(&request->client_list,
2386                               &file_priv->mm.request_list);
2387                 spin_unlock(&file_priv->mm.lock);
2388         }
2389
2390         trace_i915_gem_request_add(ring, request->seqno);
2391         ring->outstanding_lazy_seqno = 0;
2392         ring->preallocated_lazy_request = NULL;
2393
2394         if (!dev_priv->ums.mm_suspended) {
2395                 i915_queue_hangcheck(ring->dev);
2396
2397                 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2398                 queue_delayed_work(dev_priv->wq,
2399                                    &dev_priv->mm.retire_work,
2400                                    round_jiffies_up_relative(HZ));
2401                 intel_mark_busy(dev_priv->dev);
2402         }
2403
2404         if (out_seqno)
2405                 *out_seqno = request->seqno;
2406         return 0;
2407 }
2408
2409 static inline void
2410 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2411 {
2412         struct drm_i915_file_private *file_priv = request->file_priv;
2413
2414         if (!file_priv)
2415                 return;
2416
2417         spin_lock(&file_priv->mm.lock);
2418         list_del(&request->client_list);
2419         request->file_priv = NULL;
2420         spin_unlock(&file_priv->mm.lock);
2421 }
2422
2423 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2424                                    const struct intel_context *ctx)
2425 {
2426         unsigned long elapsed;
2427
2428         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2429
2430         if (ctx->hang_stats.banned)
2431                 return true;
2432
2433         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2434                 if (!i915_gem_context_is_default(ctx)) {
2435                         DRM_DEBUG("context hanging too fast, banning!\n");
2436                         return true;
2437                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2438                         if (i915_stop_ring_allow_warn(dev_priv))
2439                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2440                         return true;
2441                 }
2442         }
2443
2444         return false;
2445 }
2446
2447 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2448                                   struct intel_context *ctx,
2449                                   const bool guilty)
2450 {
2451         struct i915_ctx_hang_stats *hs;
2452
2453         if (WARN_ON(!ctx))
2454                 return;
2455
2456         hs = &ctx->hang_stats;
2457
2458         if (guilty) {
2459                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2460                 hs->batch_active++;
2461                 hs->guilty_ts = get_seconds();
2462         } else {
2463                 hs->batch_pending++;
2464         }
2465 }
2466
2467 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2468 {
2469         list_del(&request->list);
2470         i915_gem_request_remove_from_client(request);
2471
2472         if (request->ctx)
2473                 i915_gem_context_unreference(request->ctx);
2474
2475         kfree(request);
2476 }
2477
2478 struct drm_i915_gem_request *
2479 i915_gem_find_active_request(struct intel_engine_cs *ring)
2480 {
2481         struct drm_i915_gem_request *request;
2482         u32 completed_seqno;
2483
2484         completed_seqno = ring->get_seqno(ring, false);
2485
2486         list_for_each_entry(request, &ring->request_list, list) {
2487                 if (i915_seqno_passed(completed_seqno, request->seqno))
2488                         continue;
2489
2490                 return request;
2491         }
2492
2493         return NULL;
2494 }
2495
2496 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2497                                        struct intel_engine_cs *ring)
2498 {
2499         struct drm_i915_gem_request *request;
2500         bool ring_hung;
2501
2502         request = i915_gem_find_active_request(ring);
2503
2504         if (request == NULL)
2505                 return;
2506
2507         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2508
2509         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2510
2511         list_for_each_entry_continue(request, &ring->request_list, list)
2512                 i915_set_reset_status(dev_priv, request->ctx, false);
2513 }
2514
2515 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2516                                         struct intel_engine_cs *ring)
2517 {
2518         while (!list_empty(&ring->active_list)) {
2519                 struct drm_i915_gem_object *obj;
2520
2521                 obj = list_first_entry(&ring->active_list,
2522                                        struct drm_i915_gem_object,
2523                                        ring_list);
2524
2525                 i915_gem_object_move_to_inactive(obj);
2526         }
2527
2528         /*
2529          * We must free the requests after all the corresponding objects have
2530          * been moved off active lists. Which is the same order as the normal
2531          * retire_requests function does. This is important if object hold
2532          * implicit references on things like e.g. ppgtt address spaces through
2533          * the request.
2534          */
2535         while (!list_empty(&ring->request_list)) {
2536                 struct drm_i915_gem_request *request;
2537
2538                 request = list_first_entry(&ring->request_list,
2539                                            struct drm_i915_gem_request,
2540                                            list);
2541
2542                 i915_gem_free_request(request);
2543         }
2544
2545         /* These may not have been flush before the reset, do so now */
2546         kfree(ring->preallocated_lazy_request);
2547         ring->preallocated_lazy_request = NULL;
2548         ring->outstanding_lazy_seqno = 0;
2549 }
2550
2551 void i915_gem_restore_fences(struct drm_device *dev)
2552 {
2553         struct drm_i915_private *dev_priv = dev->dev_private;
2554         int i;
2555
2556         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2557                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2558
2559                 /*
2560                  * Commit delayed tiling changes if we have an object still
2561                  * attached to the fence, otherwise just clear the fence.
2562                  */
2563                 if (reg->obj) {
2564                         i915_gem_object_update_fence(reg->obj, reg,
2565                                                      reg->obj->tiling_mode);
2566                 } else {
2567                         i915_gem_write_fence(dev, i, NULL);
2568                 }
2569         }
2570 }
2571
2572 void i915_gem_reset(struct drm_device *dev)
2573 {
2574         struct drm_i915_private *dev_priv = dev->dev_private;
2575         struct intel_engine_cs *ring;
2576         int i;
2577
2578         /*
2579          * Before we free the objects from the requests, we need to inspect
2580          * them for finding the guilty party. As the requests only borrow
2581          * their reference to the objects, the inspection must be done first.
2582          */
2583         for_each_ring(ring, dev_priv, i)
2584                 i915_gem_reset_ring_status(dev_priv, ring);
2585
2586         for_each_ring(ring, dev_priv, i)
2587                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2588
2589         i915_gem_context_reset(dev);
2590
2591         i915_gem_restore_fences(dev);
2592 }
2593
2594 /**
2595  * This function clears the request list as sequence numbers are passed.
2596  */
2597 void
2598 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2599 {
2600         uint32_t seqno;
2601
2602         if (list_empty(&ring->request_list))
2603                 return;
2604
2605         WARN_ON(i915_verify_lists(ring->dev));
2606
2607         seqno = ring->get_seqno(ring, true);
2608
2609         /* Move any buffers on the active list that are no longer referenced
2610          * by the ringbuffer to the flushing/inactive lists as appropriate,
2611          * before we free the context associated with the requests.
2612          */
2613         while (!list_empty(&ring->active_list)) {
2614                 struct drm_i915_gem_object *obj;
2615
2616                 obj = list_first_entry(&ring->active_list,
2617                                       struct drm_i915_gem_object,
2618                                       ring_list);
2619
2620                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2621                         break;
2622
2623                 i915_gem_object_move_to_inactive(obj);
2624         }
2625
2626
2627         while (!list_empty(&ring->request_list)) {
2628                 struct drm_i915_gem_request *request;
2629
2630                 request = list_first_entry(&ring->request_list,
2631                                            struct drm_i915_gem_request,
2632                                            list);
2633
2634                 if (!i915_seqno_passed(seqno, request->seqno))
2635                         break;
2636
2637                 trace_i915_gem_request_retire(ring, request->seqno);
2638                 /* We know the GPU must have read the request to have
2639                  * sent us the seqno + interrupt, so use the position
2640                  * of tail of the request to update the last known position
2641                  * of the GPU head.
2642                  */
2643                 ring->buffer->last_retired_head = request->tail;
2644
2645                 i915_gem_free_request(request);
2646         }
2647
2648         if (unlikely(ring->trace_irq_seqno &&
2649                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2650                 ring->irq_put(ring);
2651                 ring->trace_irq_seqno = 0;
2652         }
2653
2654         WARN_ON(i915_verify_lists(ring->dev));
2655 }
2656
2657 bool
2658 i915_gem_retire_requests(struct drm_device *dev)
2659 {
2660         struct drm_i915_private *dev_priv = dev->dev_private;
2661         struct intel_engine_cs *ring;
2662         bool idle = true;
2663         int i;
2664
2665         for_each_ring(ring, dev_priv, i) {
2666                 i915_gem_retire_requests_ring(ring);
2667                 idle &= list_empty(&ring->request_list);
2668         }
2669
2670         if (idle)
2671                 mod_delayed_work(dev_priv->wq,
2672                                    &dev_priv->mm.idle_work,
2673                                    msecs_to_jiffies(100));
2674
2675         return idle;
2676 }
2677
2678 static void
2679 i915_gem_retire_work_handler(struct work_struct *work)
2680 {
2681         struct drm_i915_private *dev_priv =
2682                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2683         struct drm_device *dev = dev_priv->dev;
2684         bool idle;
2685
2686         /* Come back later if the device is busy... */
2687         idle = false;
2688         if (mutex_trylock(&dev->struct_mutex)) {
2689                 idle = i915_gem_retire_requests(dev);
2690                 mutex_unlock(&dev->struct_mutex);
2691         }
2692         if (!idle)
2693                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2694                                    round_jiffies_up_relative(HZ));
2695 }
2696
2697 static void
2698 i915_gem_idle_work_handler(struct work_struct *work)
2699 {
2700         struct drm_i915_private *dev_priv =
2701                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2702
2703         intel_mark_idle(dev_priv->dev);
2704 }
2705
2706 /**
2707  * Ensures that an object will eventually get non-busy by flushing any required
2708  * write domains, emitting any outstanding lazy request and retiring and
2709  * completed requests.
2710  */
2711 static int
2712 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2713 {
2714         int ret;
2715
2716         if (obj->active) {
2717                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2718                 if (ret)
2719                         return ret;
2720
2721                 i915_gem_retire_requests_ring(obj->ring);
2722         }
2723
2724         return 0;
2725 }
2726
2727 /**
2728  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2729  * @DRM_IOCTL_ARGS: standard ioctl arguments
2730  *
2731  * Returns 0 if successful, else an error is returned with the remaining time in
2732  * the timeout parameter.
2733  *  -ETIME: object is still busy after timeout
2734  *  -ERESTARTSYS: signal interrupted the wait
2735  *  -ENONENT: object doesn't exist
2736  * Also possible, but rare:
2737  *  -EAGAIN: GPU wedged
2738  *  -ENOMEM: damn
2739  *  -ENODEV: Internal IRQ fail
2740  *  -E?: The add request failed
2741  *
2742  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2743  * non-zero timeout parameter the wait ioctl will wait for the given number of
2744  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2745  * without holding struct_mutex the object may become re-busied before this
2746  * function completes. A similar but shorter * race condition exists in the busy
2747  * ioctl
2748  */
2749 int
2750 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2751 {
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         struct drm_i915_gem_wait *args = data;
2754         struct drm_i915_gem_object *obj;
2755         struct intel_engine_cs *ring = NULL;
2756         struct timespec timeout_stack, *timeout = NULL;
2757         unsigned reset_counter;
2758         u32 seqno = 0;
2759         int ret = 0;
2760
2761         if (args->timeout_ns >= 0) {
2762                 timeout_stack = ns_to_timespec(args->timeout_ns);
2763                 timeout = &timeout_stack;
2764         }
2765
2766         ret = i915_mutex_lock_interruptible(dev);
2767         if (ret)
2768                 return ret;
2769
2770         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2771         if (&obj->base == NULL) {
2772                 mutex_unlock(&dev->struct_mutex);
2773                 return -ENOENT;
2774         }
2775
2776         /* Need to make sure the object gets inactive eventually. */
2777         ret = i915_gem_object_flush_active(obj);
2778         if (ret)
2779                 goto out;
2780
2781         if (obj->active) {
2782                 seqno = obj->last_read_seqno;
2783                 ring = obj->ring;
2784         }
2785
2786         if (seqno == 0)
2787                  goto out;
2788
2789         /* Do this after OLR check to make sure we make forward progress polling
2790          * on this IOCTL with a 0 timeout (like busy ioctl)
2791          */
2792         if (!args->timeout_ns) {
2793                 ret = -ETIME;
2794                 goto out;
2795         }
2796
2797         drm_gem_object_unreference(&obj->base);
2798         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2799         mutex_unlock(&dev->struct_mutex);
2800
2801         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2802         if (timeout)
2803                 args->timeout_ns = timespec_to_ns(timeout);
2804         return ret;
2805
2806 out:
2807         drm_gem_object_unreference(&obj->base);
2808         mutex_unlock(&dev->struct_mutex);
2809         return ret;
2810 }
2811
2812 /**
2813  * i915_gem_object_sync - sync an object to a ring.
2814  *
2815  * @obj: object which may be in use on another ring.
2816  * @to: ring we wish to use the object on. May be NULL.
2817  *
2818  * This code is meant to abstract object synchronization with the GPU.
2819  * Calling with NULL implies synchronizing the object with the CPU
2820  * rather than a particular GPU ring.
2821  *
2822  * Returns 0 if successful, else propagates up the lower layer error.
2823  */
2824 int
2825 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2826                      struct intel_engine_cs *to)
2827 {
2828         struct intel_engine_cs *from = obj->ring;
2829         u32 seqno;
2830         int ret, idx;
2831
2832         if (from == NULL || to == from)
2833                 return 0;
2834
2835         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2836                 return i915_gem_object_wait_rendering(obj, false);
2837
2838         idx = intel_ring_sync_index(from, to);
2839
2840         seqno = obj->last_read_seqno;
2841         if (seqno <= from->semaphore.sync_seqno[idx])
2842                 return 0;
2843
2844         ret = i915_gem_check_olr(obj->ring, seqno);
2845         if (ret)
2846                 return ret;
2847
2848         trace_i915_gem_ring_sync_to(from, to, seqno);
2849         ret = to->semaphore.sync_to(to, from, seqno);
2850         if (!ret)
2851                 /* We use last_read_seqno because sync_to()
2852                  * might have just caused seqno wrap under
2853                  * the radar.
2854                  */
2855                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2856
2857         return ret;
2858 }
2859
2860 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2861 {
2862         u32 old_write_domain, old_read_domains;
2863
2864         /* Force a pagefault for domain tracking on next user access */
2865         i915_gem_release_mmap(obj);
2866
2867         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2868                 return;
2869
2870         /* Wait for any direct GTT access to complete */
2871         mb();
2872
2873         old_read_domains = obj->base.read_domains;
2874         old_write_domain = obj->base.write_domain;
2875
2876         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2877         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2878
2879         trace_i915_gem_object_change_domain(obj,
2880                                             old_read_domains,
2881                                             old_write_domain);
2882 }
2883
2884 int i915_vma_unbind(struct i915_vma *vma)
2885 {
2886         struct drm_i915_gem_object *obj = vma->obj;
2887         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2888         int ret;
2889
2890         if (list_empty(&vma->vma_link))
2891                 return 0;
2892
2893         if (!drm_mm_node_allocated(&vma->node)) {
2894                 i915_gem_vma_destroy(vma);
2895                 return 0;
2896         }
2897
2898         if (vma->pin_count)
2899                 return -EBUSY;
2900
2901         BUG_ON(obj->pages == NULL);
2902
2903         ret = i915_gem_object_finish_gpu(obj);
2904         if (ret)
2905                 return ret;
2906         /* Continue on if we fail due to EIO, the GPU is hung so we
2907          * should be safe and we need to cleanup or else we might
2908          * cause memory corruption through use-after-free.
2909          */
2910
2911         if (i915_is_ggtt(vma->vm)) {
2912                 i915_gem_object_finish_gtt(obj);
2913
2914                 /* release the fence reg _after_ flushing */
2915                 ret = i915_gem_object_put_fence(obj);
2916                 if (ret)
2917                         return ret;
2918         }
2919
2920         trace_i915_vma_unbind(vma);
2921
2922         vma->unbind_vma(vma);
2923
2924         i915_gem_gtt_finish_object(obj);
2925
2926         list_del_init(&vma->mm_list);
2927         /* Avoid an unnecessary call to unbind on rebind. */
2928         if (i915_is_ggtt(vma->vm))
2929                 obj->map_and_fenceable = true;
2930
2931         drm_mm_remove_node(&vma->node);
2932         i915_gem_vma_destroy(vma);
2933
2934         /* Since the unbound list is global, only move to that list if
2935          * no more VMAs exist. */
2936         if (list_empty(&obj->vma_list))
2937                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2938
2939         /* And finally now the object is completely decoupled from this vma,
2940          * we can drop its hold on the backing storage and allow it to be
2941          * reaped by the shrinker.
2942          */
2943         i915_gem_object_unpin_pages(obj);
2944
2945         return 0;
2946 }
2947
2948 int i915_gpu_idle(struct drm_device *dev)
2949 {
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         struct intel_engine_cs *ring;
2952         int ret, i;
2953
2954         /* Flush everything onto the inactive list. */
2955         for_each_ring(ring, dev_priv, i) {
2956                 ret = i915_switch_context(ring, ring->default_context);
2957                 if (ret)
2958                         return ret;
2959
2960                 ret = intel_ring_idle(ring);
2961                 if (ret)
2962                         return ret;
2963         }
2964
2965         return 0;
2966 }
2967
2968 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2969                                  struct drm_i915_gem_object *obj)
2970 {
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         int fence_reg;
2973         int fence_pitch_shift;
2974
2975         if (INTEL_INFO(dev)->gen >= 6) {
2976                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2977                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2978         } else {
2979                 fence_reg = FENCE_REG_965_0;
2980                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2981         }
2982
2983         fence_reg += reg * 8;
2984
2985         /* To w/a incoherency with non-atomic 64-bit register updates,
2986          * we split the 64-bit update into two 32-bit writes. In order
2987          * for a partial fence not to be evaluated between writes, we
2988          * precede the update with write to turn off the fence register,
2989          * and only enable the fence as the last step.
2990          *
2991          * For extra levels of paranoia, we make sure each step lands
2992          * before applying the next step.
2993          */
2994         I915_WRITE(fence_reg, 0);
2995         POSTING_READ(fence_reg);
2996
2997         if (obj) {
2998                 u32 size = i915_gem_obj_ggtt_size(obj);
2999                 uint64_t val;
3000
3001                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3002                                  0xfffff000) << 32;
3003                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3004                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3005                 if (obj->tiling_mode == I915_TILING_Y)
3006                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3007                 val |= I965_FENCE_REG_VALID;
3008
3009                 I915_WRITE(fence_reg + 4, val >> 32);
3010                 POSTING_READ(fence_reg + 4);
3011
3012                 I915_WRITE(fence_reg + 0, val);
3013                 POSTING_READ(fence_reg);
3014         } else {
3015                 I915_WRITE(fence_reg + 4, 0);
3016                 POSTING_READ(fence_reg + 4);
3017         }
3018 }
3019
3020 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3021                                  struct drm_i915_gem_object *obj)
3022 {
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         u32 val;
3025
3026         if (obj) {
3027                 u32 size = i915_gem_obj_ggtt_size(obj);
3028                 int pitch_val;
3029                 int tile_width;
3030
3031                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3032                      (size & -size) != size ||
3033                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3034                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3035                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3036
3037                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3038                         tile_width = 128;
3039                 else
3040                         tile_width = 512;
3041
3042                 /* Note: pitch better be a power of two tile widths */
3043                 pitch_val = obj->stride / tile_width;
3044                 pitch_val = ffs(pitch_val) - 1;
3045
3046                 val = i915_gem_obj_ggtt_offset(obj);
3047                 if (obj->tiling_mode == I915_TILING_Y)
3048                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3049                 val |= I915_FENCE_SIZE_BITS(size);
3050                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3051                 val |= I830_FENCE_REG_VALID;
3052         } else
3053                 val = 0;
3054
3055         if (reg < 8)
3056                 reg = FENCE_REG_830_0 + reg * 4;
3057         else
3058                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3059
3060         I915_WRITE(reg, val);
3061         POSTING_READ(reg);
3062 }
3063
3064 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3065                                 struct drm_i915_gem_object *obj)
3066 {
3067         struct drm_i915_private *dev_priv = dev->dev_private;
3068         uint32_t val;
3069
3070         if (obj) {
3071                 u32 size = i915_gem_obj_ggtt_size(obj);
3072                 uint32_t pitch_val;
3073
3074                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3075                      (size & -size) != size ||
3076                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3077                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3078                      i915_gem_obj_ggtt_offset(obj), size);
3079
3080                 pitch_val = obj->stride / 128;
3081                 pitch_val = ffs(pitch_val) - 1;
3082
3083                 val = i915_gem_obj_ggtt_offset(obj);
3084                 if (obj->tiling_mode == I915_TILING_Y)
3085                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3086                 val |= I830_FENCE_SIZE_BITS(size);
3087                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3088                 val |= I830_FENCE_REG_VALID;
3089         } else
3090                 val = 0;
3091
3092         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3093         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3094 }
3095
3096 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3097 {
3098         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3099 }
3100
3101 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3102                                  struct drm_i915_gem_object *obj)
3103 {
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105
3106         /* Ensure that all CPU reads are completed before installing a fence
3107          * and all writes before removing the fence.
3108          */
3109         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3110                 mb();
3111
3112         WARN(obj && (!obj->stride || !obj->tiling_mode),
3113              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3114              obj->stride, obj->tiling_mode);
3115
3116         switch (INTEL_INFO(dev)->gen) {
3117         case 8:
3118         case 7:
3119         case 6:
3120         case 5:
3121         case 4: i965_write_fence_reg(dev, reg, obj); break;
3122         case 3: i915_write_fence_reg(dev, reg, obj); break;
3123         case 2: i830_write_fence_reg(dev, reg, obj); break;
3124         default: BUG();
3125         }
3126
3127         /* And similarly be paranoid that no direct access to this region
3128          * is reordered to before the fence is installed.
3129          */
3130         if (i915_gem_object_needs_mb(obj))
3131                 mb();
3132 }
3133
3134 static inline int fence_number(struct drm_i915_private *dev_priv,
3135                                struct drm_i915_fence_reg *fence)
3136 {
3137         return fence - dev_priv->fence_regs;
3138 }
3139
3140 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3141                                          struct drm_i915_fence_reg *fence,
3142                                          bool enable)
3143 {
3144         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3145         int reg = fence_number(dev_priv, fence);
3146
3147         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3148
3149         if (enable) {
3150                 obj->fence_reg = reg;
3151                 fence->obj = obj;
3152                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3153         } else {
3154                 obj->fence_reg = I915_FENCE_REG_NONE;
3155                 fence->obj = NULL;
3156                 list_del_init(&fence->lru_list);
3157         }
3158         obj->fence_dirty = false;
3159 }
3160
3161 static int
3162 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3163 {
3164         if (obj->last_fenced_seqno) {
3165                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3166                 if (ret)
3167                         return ret;
3168
3169                 obj->last_fenced_seqno = 0;
3170         }
3171
3172         obj->fenced_gpu_access = false;
3173         return 0;
3174 }
3175
3176 int
3177 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3178 {
3179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3180         struct drm_i915_fence_reg *fence;
3181         int ret;
3182
3183         ret = i915_gem_object_wait_fence(obj);
3184         if (ret)
3185                 return ret;
3186
3187         if (obj->fence_reg == I915_FENCE_REG_NONE)
3188                 return 0;
3189
3190         fence = &dev_priv->fence_regs[obj->fence_reg];
3191
3192         if (WARN_ON(fence->pin_count))
3193                 return -EBUSY;
3194
3195         i915_gem_object_fence_lost(obj);
3196         i915_gem_object_update_fence(obj, fence, false);
3197
3198         return 0;
3199 }
3200
3201 static struct drm_i915_fence_reg *
3202 i915_find_fence_reg(struct drm_device *dev)
3203 {
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         struct drm_i915_fence_reg *reg, *avail;
3206         int i;
3207
3208         /* First try to find a free reg */
3209         avail = NULL;
3210         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3211                 reg = &dev_priv->fence_regs[i];
3212                 if (!reg->obj)
3213                         return reg;
3214
3215                 if (!reg->pin_count)
3216                         avail = reg;
3217         }
3218
3219         if (avail == NULL)
3220                 goto deadlock;
3221
3222         /* None available, try to steal one or wait for a user to finish */
3223         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3224                 if (reg->pin_count)
3225                         continue;
3226
3227                 return reg;
3228         }
3229
3230 deadlock:
3231         /* Wait for completion of pending flips which consume fences */
3232         if (intel_has_pending_fb_unpin(dev))
3233                 return ERR_PTR(-EAGAIN);
3234
3235         return ERR_PTR(-EDEADLK);
3236 }
3237
3238 /**
3239  * i915_gem_object_get_fence - set up fencing for an object
3240  * @obj: object to map through a fence reg
3241  *
3242  * When mapping objects through the GTT, userspace wants to be able to write
3243  * to them without having to worry about swizzling if the object is tiled.
3244  * This function walks the fence regs looking for a free one for @obj,
3245  * stealing one if it can't find any.
3246  *
3247  * It then sets up the reg based on the object's properties: address, pitch
3248  * and tiling format.
3249  *
3250  * For an untiled surface, this removes any existing fence.
3251  */
3252 int
3253 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3254 {
3255         struct drm_device *dev = obj->base.dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         bool enable = obj->tiling_mode != I915_TILING_NONE;
3258         struct drm_i915_fence_reg *reg;
3259         int ret;
3260
3261         /* Have we updated the tiling parameters upon the object and so
3262          * will need to serialise the write to the associated fence register?
3263          */
3264         if (obj->fence_dirty) {
3265                 ret = i915_gem_object_wait_fence(obj);
3266                 if (ret)
3267                         return ret;
3268         }
3269
3270         /* Just update our place in the LRU if our fence is getting reused. */
3271         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3272                 reg = &dev_priv->fence_regs[obj->fence_reg];
3273                 if (!obj->fence_dirty) {
3274                         list_move_tail(&reg->lru_list,
3275                                        &dev_priv->mm.fence_list);
3276                         return 0;
3277                 }
3278         } else if (enable) {
3279                 reg = i915_find_fence_reg(dev);
3280                 if (IS_ERR(reg))
3281                         return PTR_ERR(reg);
3282
3283                 if (reg->obj) {
3284                         struct drm_i915_gem_object *old = reg->obj;
3285
3286                         ret = i915_gem_object_wait_fence(old);
3287                         if (ret)
3288                                 return ret;
3289
3290                         i915_gem_object_fence_lost(old);
3291                 }
3292         } else
3293                 return 0;
3294
3295         i915_gem_object_update_fence(obj, reg, enable);
3296
3297         return 0;
3298 }
3299
3300 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3301                                      struct drm_mm_node *gtt_space,
3302                                      unsigned long cache_level)
3303 {
3304         struct drm_mm_node *other;
3305
3306         /* On non-LLC machines we have to be careful when putting differing
3307          * types of snoopable memory together to avoid the prefetcher
3308          * crossing memory domains and dying.
3309          */
3310         if (HAS_LLC(dev))
3311                 return true;
3312
3313         if (!drm_mm_node_allocated(gtt_space))
3314                 return true;
3315
3316         if (list_empty(&gtt_space->node_list))
3317                 return true;
3318
3319         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3320         if (other->allocated && !other->hole_follows && other->color != cache_level)
3321                 return false;
3322
3323         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3324         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3325                 return false;
3326
3327         return true;
3328 }
3329
3330 static void i915_gem_verify_gtt(struct drm_device *dev)
3331 {
3332 #if WATCH_GTT
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334         struct drm_i915_gem_object *obj;
3335         int err = 0;
3336
3337         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3338                 if (obj->gtt_space == NULL) {
3339                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3340                         err++;
3341                         continue;
3342                 }
3343
3344                 if (obj->cache_level != obj->gtt_space->color) {
3345                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3346                                i915_gem_obj_ggtt_offset(obj),
3347                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3348                                obj->cache_level,
3349                                obj->gtt_space->color);
3350                         err++;
3351                         continue;
3352                 }
3353
3354                 if (!i915_gem_valid_gtt_space(dev,
3355                                               obj->gtt_space,
3356                                               obj->cache_level)) {
3357                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3358                                i915_gem_obj_ggtt_offset(obj),
3359                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3360                                obj->cache_level);
3361                         err++;
3362                         continue;
3363                 }
3364         }
3365
3366         WARN_ON(err);
3367 #endif
3368 }
3369
3370 /**
3371  * Finds free space in the GTT aperture and binds the object there.
3372  */
3373 static struct i915_vma *
3374 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3375                            struct i915_address_space *vm,
3376                            unsigned alignment,
3377                            uint64_t flags)
3378 {
3379         struct drm_device *dev = obj->base.dev;
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381         u32 size, fence_size, fence_alignment, unfenced_alignment;
3382         unsigned long start =
3383                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3384         unsigned long end =
3385                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3386         struct i915_vma *vma;
3387         int ret;
3388
3389         fence_size = i915_gem_get_gtt_size(dev,
3390                                            obj->base.size,
3391                                            obj->tiling_mode);
3392         fence_alignment = i915_gem_get_gtt_alignment(dev,
3393                                                      obj->base.size,
3394                                                      obj->tiling_mode, true);
3395         unfenced_alignment =
3396                 i915_gem_get_gtt_alignment(dev,
3397                                            obj->base.size,
3398                                            obj->tiling_mode, false);
3399
3400         if (alignment == 0)
3401                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3402                                                 unfenced_alignment;
3403         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3404                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3405                 return ERR_PTR(-EINVAL);
3406         }
3407
3408         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3409
3410         /* If the object is bigger than the entire aperture, reject it early
3411          * before evicting everything in a vain attempt to find space.
3412          */
3413         if (obj->base.size > end) {
3414                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3415                           obj->base.size,
3416                           flags & PIN_MAPPABLE ? "mappable" : "total",
3417                           end);
3418                 return ERR_PTR(-E2BIG);
3419         }
3420
3421         ret = i915_gem_object_get_pages(obj);
3422         if (ret)
3423                 return ERR_PTR(ret);
3424
3425         i915_gem_object_pin_pages(obj);
3426
3427         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3428         if (IS_ERR(vma))
3429                 goto err_unpin;
3430
3431 search_free:
3432         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3433                                                   size, alignment,
3434                                                   obj->cache_level,
3435                                                   start, end,
3436                                                   DRM_MM_SEARCH_DEFAULT,
3437                                                   DRM_MM_CREATE_DEFAULT);
3438         if (ret) {
3439                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3440                                                obj->cache_level,
3441                                                start, end,
3442                                                flags);
3443                 if (ret == 0)
3444                         goto search_free;
3445
3446                 goto err_free_vma;
3447         }
3448         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3449                                               obj->cache_level))) {
3450                 ret = -EINVAL;
3451                 goto err_remove_node;
3452         }
3453
3454         ret = i915_gem_gtt_prepare_object(obj);
3455         if (ret)
3456                 goto err_remove_node;
3457
3458         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3459         list_add_tail(&vma->mm_list, &vm->inactive_list);
3460
3461         if (i915_is_ggtt(vm)) {
3462                 bool mappable, fenceable;
3463
3464                 fenceable = (vma->node.size == fence_size &&
3465                              (vma->node.start & (fence_alignment - 1)) == 0);
3466
3467                 mappable = (vma->node.start + obj->base.size <=
3468                             dev_priv->gtt.mappable_end);
3469
3470                 obj->map_and_fenceable = mappable && fenceable;
3471         }
3472
3473         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3474
3475         trace_i915_vma_bind(vma, flags);
3476         vma->bind_vma(vma, obj->cache_level,
3477                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3478
3479         i915_gem_verify_gtt(dev);
3480         return vma;
3481
3482 err_remove_node:
3483         drm_mm_remove_node(&vma->node);
3484 err_free_vma:
3485         i915_gem_vma_destroy(vma);
3486         vma = ERR_PTR(ret);
3487 err_unpin:
3488         i915_gem_object_unpin_pages(obj);
3489         return vma;
3490 }
3491
3492 bool
3493 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3494                         bool force)
3495 {
3496         /* If we don't have a page list set up, then we're not pinned
3497          * to GPU, and we can ignore the cache flush because it'll happen
3498          * again at bind time.
3499          */
3500         if (obj->pages == NULL)
3501                 return false;
3502
3503         /*
3504          * Stolen memory is always coherent with the GPU as it is explicitly
3505          * marked as wc by the system, or the system is cache-coherent.
3506          */
3507         if (obj->stolen)
3508                 return false;
3509
3510         /* If the GPU is snooping the contents of the CPU cache,
3511          * we do not need to manually clear the CPU cache lines.  However,
3512          * the caches are only snooped when the render cache is
3513          * flushed/invalidated.  As we always have to emit invalidations
3514          * and flushes when moving into and out of the RENDER domain, correct
3515          * snooping behaviour occurs naturally as the result of our domain
3516          * tracking.
3517          */
3518         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3519                 return false;
3520
3521         trace_i915_gem_object_clflush(obj);
3522         drm_clflush_sg(obj->pages);
3523
3524         return true;
3525 }
3526
3527 /** Flushes the GTT write domain for the object if it's dirty. */
3528 static void
3529 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3530 {
3531         uint32_t old_write_domain;
3532
3533         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3534                 return;
3535
3536         /* No actual flushing is required for the GTT write domain.  Writes
3537          * to it immediately go to main memory as far as we know, so there's
3538          * no chipset flush.  It also doesn't land in render cache.
3539          *
3540          * However, we do have to enforce the order so that all writes through
3541          * the GTT land before any writes to the device, such as updates to
3542          * the GATT itself.
3543          */
3544         wmb();
3545
3546         old_write_domain = obj->base.write_domain;
3547         obj->base.write_domain = 0;
3548
3549         trace_i915_gem_object_change_domain(obj,
3550                                             obj->base.read_domains,
3551                                             old_write_domain);
3552 }
3553
3554 /** Flushes the CPU write domain for the object if it's dirty. */
3555 static void
3556 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3557                                        bool force)
3558 {
3559         uint32_t old_write_domain;
3560
3561         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3562                 return;
3563
3564         if (i915_gem_clflush_object(obj, force))
3565                 i915_gem_chipset_flush(obj->base.dev);
3566
3567         old_write_domain = obj->base.write_domain;
3568         obj->base.write_domain = 0;
3569
3570         trace_i915_gem_object_change_domain(obj,
3571                                             obj->base.read_domains,
3572                                             old_write_domain);
3573 }
3574
3575 /**
3576  * Moves a single object to the GTT read, and possibly write domain.
3577  *
3578  * This function returns when the move is complete, including waiting on
3579  * flushes to occur.
3580  */
3581 int
3582 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3583 {
3584         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3585         uint32_t old_write_domain, old_read_domains;
3586         int ret;
3587
3588         /* Not valid to be called on unbound objects. */
3589         if (!i915_gem_obj_bound_any(obj))
3590                 return -EINVAL;
3591
3592         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3593                 return 0;
3594
3595         ret = i915_gem_object_wait_rendering(obj, !write);
3596         if (ret)
3597                 return ret;
3598
3599         i915_gem_object_retire(obj);
3600         i915_gem_object_flush_cpu_write_domain(obj, false);
3601
3602         /* Serialise direct access to this object with the barriers for
3603          * coherent writes from the GPU, by effectively invalidating the
3604          * GTT domain upon first access.
3605          */
3606         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3607                 mb();
3608
3609         old_write_domain = obj->base.write_domain;
3610         old_read_domains = obj->base.read_domains;
3611
3612         /* It should now be out of any other write domains, and we can update
3613          * the domain values for our changes.
3614          */
3615         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3616         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3617         if (write) {
3618                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3619                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3620                 obj->dirty = 1;
3621         }
3622
3623         trace_i915_gem_object_change_domain(obj,
3624                                             old_read_domains,
3625                                             old_write_domain);
3626
3627         /* And bump the LRU for this access */
3628         if (i915_gem_object_is_inactive(obj)) {
3629                 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3630                 if (vma)
3631                         list_move_tail(&vma->mm_list,
3632                                        &dev_priv->gtt.base.inactive_list);
3633
3634         }
3635
3636         return 0;
3637 }
3638
3639 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3640                                     enum i915_cache_level cache_level)
3641 {
3642         struct drm_device *dev = obj->base.dev;
3643         struct i915_vma *vma, *next;
3644         int ret;
3645
3646         if (obj->cache_level == cache_level)
3647                 return 0;
3648
3649         if (i915_gem_obj_is_pinned(obj)) {
3650                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3651                 return -EBUSY;
3652         }
3653
3654         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3655                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3656                         ret = i915_vma_unbind(vma);
3657                         if (ret)
3658                                 return ret;
3659                 }
3660         }
3661
3662         if (i915_gem_obj_bound_any(obj)) {
3663                 ret = i915_gem_object_finish_gpu(obj);
3664                 if (ret)
3665                         return ret;
3666
3667                 i915_gem_object_finish_gtt(obj);
3668
3669                 /* Before SandyBridge, you could not use tiling or fence
3670                  * registers with snooped memory, so relinquish any fences
3671                  * currently pointing to our region in the aperture.
3672                  */
3673                 if (INTEL_INFO(dev)->gen < 6) {
3674                         ret = i915_gem_object_put_fence(obj);
3675                         if (ret)
3676                                 return ret;
3677                 }
3678
3679                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3680                         if (drm_mm_node_allocated(&vma->node))
3681                                 vma->bind_vma(vma, cache_level,
3682                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3683         }
3684
3685         list_for_each_entry(vma, &obj->vma_list, vma_link)
3686                 vma->node.color = cache_level;
3687         obj->cache_level = cache_level;
3688
3689         if (cpu_write_needs_clflush(obj)) {
3690                 u32 old_read_domains, old_write_domain;
3691
3692                 /* If we're coming from LLC cached, then we haven't
3693                  * actually been tracking whether the data is in the
3694                  * CPU cache or not, since we only allow one bit set
3695                  * in obj->write_domain and have been skipping the clflushes.
3696                  * Just set it to the CPU cache for now.
3697                  */
3698                 i915_gem_object_retire(obj);
3699                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3700
3701                 old_read_domains = obj->base.read_domains;
3702                 old_write_domain = obj->base.write_domain;
3703
3704                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3705                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3706
3707                 trace_i915_gem_object_change_domain(obj,
3708                                                     old_read_domains,
3709                                                     old_write_domain);
3710         }
3711
3712         i915_gem_verify_gtt(dev);
3713         return 0;
3714 }
3715
3716 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3717                                struct drm_file *file)
3718 {
3719         struct drm_i915_gem_caching *args = data;
3720         struct drm_i915_gem_object *obj;
3721         int ret;
3722
3723         ret = i915_mutex_lock_interruptible(dev);
3724         if (ret)
3725                 return ret;
3726
3727         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3728         if (&obj->base == NULL) {
3729                 ret = -ENOENT;
3730                 goto unlock;
3731         }
3732
3733         switch (obj->cache_level) {
3734         case I915_CACHE_LLC:
3735         case I915_CACHE_L3_LLC:
3736                 args->caching = I915_CACHING_CACHED;
3737                 break;
3738
3739         case I915_CACHE_WT:
3740                 args->caching = I915_CACHING_DISPLAY;
3741                 break;
3742
3743         default:
3744                 args->caching = I915_CACHING_NONE;
3745                 break;
3746         }
3747
3748         drm_gem_object_unreference(&obj->base);
3749 unlock:
3750         mutex_unlock(&dev->struct_mutex);
3751         return ret;
3752 }
3753
3754 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3755                                struct drm_file *file)
3756 {
3757         struct drm_i915_gem_caching *args = data;
3758         struct drm_i915_gem_object *obj;
3759         enum i915_cache_level level;
3760         int ret;
3761
3762         switch (args->caching) {
3763         case I915_CACHING_NONE:
3764                 level = I915_CACHE_NONE;
3765                 break;
3766         case I915_CACHING_CACHED:
3767                 level = I915_CACHE_LLC;
3768                 break;
3769         case I915_CACHING_DISPLAY:
3770                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3771                 break;
3772         default:
3773                 return -EINVAL;
3774         }
3775
3776         ret = i915_mutex_lock_interruptible(dev);
3777         if (ret)
3778                 return ret;
3779
3780         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3781         if (&obj->base == NULL) {
3782                 ret = -ENOENT;
3783                 goto unlock;
3784         }
3785
3786         ret = i915_gem_object_set_cache_level(obj, level);
3787
3788         drm_gem_object_unreference(&obj->base);
3789 unlock:
3790         mutex_unlock(&dev->struct_mutex);
3791         return ret;
3792 }
3793
3794 static bool is_pin_display(struct drm_i915_gem_object *obj)
3795 {
3796         struct i915_vma *vma;
3797
3798         if (list_empty(&obj->vma_list))
3799                 return false;
3800
3801         vma = i915_gem_obj_to_ggtt(obj);
3802         if (!vma)
3803                 return false;
3804
3805         /* There are 3 sources that pin objects:
3806          *   1. The display engine (scanouts, sprites, cursors);
3807          *   2. Reservations for execbuffer;
3808          *   3. The user.
3809          *
3810          * We can ignore reservations as we hold the struct_mutex and
3811          * are only called outside of the reservation path.  The user
3812          * can only increment pin_count once, and so if after
3813          * subtracting the potential reference by the user, any pin_count
3814          * remains, it must be due to another use by the display engine.
3815          */
3816         return vma->pin_count - !!obj->user_pin_count;
3817 }
3818
3819 /*
3820  * Prepare buffer for display plane (scanout, cursors, etc).
3821  * Can be called from an uninterruptible phase (modesetting) and allows
3822  * any flushes to be pipelined (for pageflips).
3823  */
3824 int
3825 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3826                                      u32 alignment,
3827                                      struct intel_engine_cs *pipelined)
3828 {
3829         u32 old_read_domains, old_write_domain;
3830         bool was_pin_display;
3831         int ret;
3832
3833         if (pipelined != obj->ring) {
3834                 ret = i915_gem_object_sync(obj, pipelined);
3835                 if (ret)
3836                         return ret;
3837         }
3838
3839         /* Mark the pin_display early so that we account for the
3840          * display coherency whilst setting up the cache domains.
3841          */
3842         was_pin_display = obj->pin_display;
3843         obj->pin_display = true;
3844
3845         /* The display engine is not coherent with the LLC cache on gen6.  As
3846          * a result, we make sure that the pinning that is about to occur is
3847          * done with uncached PTEs. This is lowest common denominator for all
3848          * chipsets.
3849          *
3850          * However for gen6+, we could do better by using the GFDT bit instead
3851          * of uncaching, which would allow us to flush all the LLC-cached data
3852          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3853          */
3854         ret = i915_gem_object_set_cache_level(obj,
3855                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3856         if (ret)
3857                 goto err_unpin_display;
3858
3859         /* As the user may map the buffer once pinned in the display plane
3860          * (e.g. libkms for the bootup splash), we have to ensure that we
3861          * always use map_and_fenceable for all scanout buffers.
3862          */
3863         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3864         if (ret)
3865                 goto err_unpin_display;
3866
3867         i915_gem_object_flush_cpu_write_domain(obj, true);
3868
3869         old_write_domain = obj->base.write_domain;
3870         old_read_domains = obj->base.read_domains;
3871
3872         /* It should now be out of any other write domains, and we can update
3873          * the domain values for our changes.
3874          */
3875         obj->base.write_domain = 0;
3876         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3877
3878         trace_i915_gem_object_change_domain(obj,
3879                                             old_read_domains,
3880                                             old_write_domain);
3881
3882         return 0;
3883
3884 err_unpin_display:
3885         WARN_ON(was_pin_display != is_pin_display(obj));
3886         obj->pin_display = was_pin_display;
3887         return ret;
3888 }
3889
3890 void
3891 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3892 {
3893         i915_gem_object_ggtt_unpin(obj);
3894         obj->pin_display = is_pin_display(obj);
3895 }
3896
3897 int
3898 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3899 {
3900         int ret;
3901
3902         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3903                 return 0;
3904
3905         ret = i915_gem_object_wait_rendering(obj, false);
3906         if (ret)
3907                 return ret;
3908
3909         /* Ensure that we invalidate the GPU's caches and TLBs. */
3910         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3911         return 0;
3912 }
3913
3914 /**
3915  * Moves a single object to the CPU read, and possibly write domain.
3916  *
3917  * This function returns when the move is complete, including waiting on
3918  * flushes to occur.
3919  */
3920 int
3921 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3922 {
3923         uint32_t old_write_domain, old_read_domains;
3924         int ret;
3925
3926         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3927                 return 0;
3928
3929         ret = i915_gem_object_wait_rendering(obj, !write);
3930         if (ret)
3931                 return ret;
3932
3933         i915_gem_object_retire(obj);
3934         i915_gem_object_flush_gtt_write_domain(obj);
3935
3936         old_write_domain = obj->base.write_domain;
3937         old_read_domains = obj->base.read_domains;
3938
3939         /* Flush the CPU cache if it's still invalid. */
3940         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3941                 i915_gem_clflush_object(obj, false);
3942
3943                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3944         }
3945
3946         /* It should now be out of any other write domains, and we can update
3947          * the domain values for our changes.
3948          */
3949         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3950
3951         /* If we're writing through the CPU, then the GPU read domains will
3952          * need to be invalidated at next use.
3953          */
3954         if (write) {
3955                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3956                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3957         }
3958
3959         trace_i915_gem_object_change_domain(obj,
3960                                             old_read_domains,
3961                                             old_write_domain);
3962
3963         return 0;
3964 }
3965
3966 /* Throttle our rendering by waiting until the ring has completed our requests
3967  * emitted over 20 msec ago.
3968  *
3969  * Note that if we were to use the current jiffies each time around the loop,
3970  * we wouldn't escape the function with any frames outstanding if the time to
3971  * render a frame was over 20ms.
3972  *
3973  * This should get us reasonable parallelism between CPU and GPU but also
3974  * relatively low latency when blocking on a particular request to finish.
3975  */
3976 static int
3977 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3978 {
3979         struct drm_i915_private *dev_priv = dev->dev_private;
3980         struct drm_i915_file_private *file_priv = file->driver_priv;
3981         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3982         struct drm_i915_gem_request *request;
3983         struct intel_engine_cs *ring = NULL;
3984         unsigned reset_counter;
3985         u32 seqno = 0;
3986         int ret;
3987
3988         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3989         if (ret)
3990                 return ret;
3991
3992         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3993         if (ret)
3994                 return ret;
3995
3996         spin_lock(&file_priv->mm.lock);
3997         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3998                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3999                         break;
4000
4001                 ring = request->ring;
4002                 seqno = request->seqno;
4003         }
4004         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4005         spin_unlock(&file_priv->mm.lock);
4006
4007         if (seqno == 0)
4008                 return 0;
4009
4010         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4011         if (ret == 0)
4012                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4013
4014         return ret;
4015 }
4016
4017 static bool
4018 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4019 {
4020         struct drm_i915_gem_object *obj = vma->obj;
4021
4022         if (alignment &&
4023             vma->node.start & (alignment - 1))
4024                 return true;
4025
4026         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4027                 return true;
4028
4029         if (flags & PIN_OFFSET_BIAS &&
4030             vma->node.start < (flags & PIN_OFFSET_MASK))
4031                 return true;
4032
4033         return false;
4034 }
4035
4036 int
4037 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4038                     struct i915_address_space *vm,
4039                     uint32_t alignment,
4040                     uint64_t flags)
4041 {
4042         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4043         struct i915_vma *vma;
4044         int ret;
4045
4046         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4047                 return -ENODEV;
4048
4049         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4050                 return -EINVAL;
4051
4052         vma = i915_gem_obj_to_vma(obj, vm);
4053         if (vma) {
4054                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4055                         return -EBUSY;
4056
4057                 if (i915_vma_misplaced(vma, alignment, flags)) {
4058                         WARN(vma->pin_count,
4059                              "bo is already pinned with incorrect alignment:"
4060                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4061                              " obj->map_and_fenceable=%d\n",
4062                              i915_gem_obj_offset(obj, vm), alignment,
4063                              !!(flags & PIN_MAPPABLE),
4064                              obj->map_and_fenceable);
4065                         ret = i915_vma_unbind(vma);
4066                         if (ret)
4067                                 return ret;
4068
4069                         vma = NULL;
4070                 }
4071         }
4072
4073         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4074                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4075                 if (IS_ERR(vma))
4076                         return PTR_ERR(vma);
4077         }
4078
4079         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4080                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4081
4082         vma->pin_count++;
4083         if (flags & PIN_MAPPABLE)
4084                 obj->pin_mappable |= true;
4085
4086         return 0;
4087 }
4088
4089 void
4090 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4091 {
4092         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4093
4094         BUG_ON(!vma);
4095         BUG_ON(vma->pin_count == 0);
4096         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4097
4098         if (--vma->pin_count == 0)
4099                 obj->pin_mappable = false;
4100 }
4101
4102 bool
4103 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4104 {
4105         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4106                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4107                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4108
4109                 WARN_ON(!ggtt_vma ||
4110                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4111                         ggtt_vma->pin_count);
4112                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4113                 return true;
4114         } else
4115                 return false;
4116 }
4117
4118 void
4119 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4120 {
4121         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4122                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4123                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4124                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4125         }
4126 }
4127
4128 int
4129 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4130                    struct drm_file *file)
4131 {
4132         struct drm_i915_gem_pin *args = data;
4133         struct drm_i915_gem_object *obj;
4134         int ret;
4135
4136         if (INTEL_INFO(dev)->gen >= 6)
4137                 return -ENODEV;
4138
4139         ret = i915_mutex_lock_interruptible(dev);
4140         if (ret)
4141                 return ret;
4142
4143         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4144         if (&obj->base == NULL) {
4145                 ret = -ENOENT;
4146                 goto unlock;
4147         }
4148
4149         if (obj->madv != I915_MADV_WILLNEED) {
4150                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4151                 ret = -EFAULT;
4152                 goto out;
4153         }
4154
4155         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4156                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4157                           args->handle);
4158                 ret = -EINVAL;
4159                 goto out;
4160         }
4161
4162         if (obj->user_pin_count == ULONG_MAX) {
4163                 ret = -EBUSY;
4164                 goto out;
4165         }
4166
4167         if (obj->user_pin_count == 0) {
4168                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4169                 if (ret)
4170                         goto out;
4171         }
4172
4173         obj->user_pin_count++;
4174         obj->pin_filp = file;
4175
4176         args->offset = i915_gem_obj_ggtt_offset(obj);
4177 out:
4178         drm_gem_object_unreference(&obj->base);
4179 unlock:
4180         mutex_unlock(&dev->struct_mutex);
4181         return ret;
4182 }
4183
4184 int
4185 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4186                      struct drm_file *file)
4187 {
4188         struct drm_i915_gem_pin *args = data;
4189         struct drm_i915_gem_object *obj;
4190         int ret;
4191
4192         ret = i915_mutex_lock_interruptible(dev);
4193         if (ret)
4194                 return ret;
4195
4196         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4197         if (&obj->base == NULL) {
4198                 ret = -ENOENT;
4199                 goto unlock;
4200         }
4201
4202         if (obj->pin_filp != file) {
4203                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4204                           args->handle);
4205                 ret = -EINVAL;
4206                 goto out;
4207         }
4208         obj->user_pin_count--;
4209         if (obj->user_pin_count == 0) {
4210                 obj->pin_filp = NULL;
4211                 i915_gem_object_ggtt_unpin(obj);
4212         }
4213
4214 out:
4215         drm_gem_object_unreference(&obj->base);
4216 unlock:
4217         mutex_unlock(&dev->struct_mutex);
4218         return ret;
4219 }
4220
4221 int
4222 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4223                     struct drm_file *file)
4224 {
4225         struct drm_i915_gem_busy *args = data;
4226         struct drm_i915_gem_object *obj;
4227         int ret;
4228
4229         ret = i915_mutex_lock_interruptible(dev);
4230         if (ret)
4231                 return ret;
4232
4233         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4234         if (&obj->base == NULL) {
4235                 ret = -ENOENT;
4236                 goto unlock;
4237         }
4238
4239         /* Count all active objects as busy, even if they are currently not used
4240          * by the gpu. Users of this interface expect objects to eventually
4241          * become non-busy without any further actions, therefore emit any
4242          * necessary flushes here.
4243          */
4244         ret = i915_gem_object_flush_active(obj);
4245
4246         args->busy = obj->active;
4247         if (obj->ring) {
4248                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4249                 args->busy |= intel_ring_flag(obj->ring) << 16;
4250         }
4251
4252         drm_gem_object_unreference(&obj->base);
4253 unlock:
4254         mutex_unlock(&dev->struct_mutex);
4255         return ret;
4256 }
4257
4258 int
4259 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4260                         struct drm_file *file_priv)
4261 {
4262         return i915_gem_ring_throttle(dev, file_priv);
4263 }
4264
4265 int
4266 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4267                        struct drm_file *file_priv)
4268 {
4269         struct drm_i915_gem_madvise *args = data;
4270         struct drm_i915_gem_object *obj;
4271         int ret;
4272
4273         switch (args->madv) {
4274         case I915_MADV_DONTNEED:
4275         case I915_MADV_WILLNEED:
4276             break;
4277         default:
4278             return -EINVAL;
4279         }
4280
4281         ret = i915_mutex_lock_interruptible(dev);
4282         if (ret)
4283                 return ret;
4284
4285         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4286         if (&obj->base == NULL) {
4287                 ret = -ENOENT;
4288                 goto unlock;
4289         }
4290
4291         if (i915_gem_obj_is_pinned(obj)) {
4292                 ret = -EINVAL;
4293                 goto out;
4294         }
4295
4296         if (obj->madv != __I915_MADV_PURGED)
4297                 obj->madv = args->madv;
4298
4299         /* if the object is no longer attached, discard its backing storage */
4300         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4301                 i915_gem_object_truncate(obj);
4302
4303         args->retained = obj->madv != __I915_MADV_PURGED;
4304
4305 out:
4306         drm_gem_object_unreference(&obj->base);
4307 unlock:
4308         mutex_unlock(&dev->struct_mutex);
4309         return ret;
4310 }
4311
4312 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4313                           const struct drm_i915_gem_object_ops *ops)
4314 {
4315         INIT_LIST_HEAD(&obj->global_list);
4316         INIT_LIST_HEAD(&obj->ring_list);
4317         INIT_LIST_HEAD(&obj->obj_exec_link);
4318         INIT_LIST_HEAD(&obj->vma_list);
4319
4320         obj->ops = ops;
4321
4322         obj->fence_reg = I915_FENCE_REG_NONE;
4323         obj->madv = I915_MADV_WILLNEED;
4324         /* Avoid an unnecessary call to unbind on the first bind. */
4325         obj->map_and_fenceable = true;
4326
4327         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4328 }
4329
4330 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4331         .get_pages = i915_gem_object_get_pages_gtt,
4332         .put_pages = i915_gem_object_put_pages_gtt,
4333 };
4334
4335 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4336                                                   size_t size)
4337 {
4338         struct drm_i915_gem_object *obj;
4339         struct address_space *mapping;
4340         gfp_t mask;
4341
4342         obj = i915_gem_object_alloc(dev);
4343         if (obj == NULL)
4344                 return NULL;
4345
4346         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4347                 i915_gem_object_free(obj);
4348                 return NULL;
4349         }
4350
4351         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4352         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4353                 /* 965gm cannot relocate objects above 4GiB. */
4354                 mask &= ~__GFP_HIGHMEM;
4355                 mask |= __GFP_DMA32;
4356         }
4357
4358         mapping = file_inode(obj->base.filp)->i_mapping;
4359         mapping_set_gfp_mask(mapping, mask);
4360
4361         i915_gem_object_init(obj, &i915_gem_object_ops);
4362
4363         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4364         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4365
4366         if (HAS_LLC(dev)) {
4367                 /* On some devices, we can have the GPU use the LLC (the CPU
4368                  * cache) for about a 10% performance improvement
4369                  * compared to uncached.  Graphics requests other than
4370                  * display scanout are coherent with the CPU in
4371                  * accessing this cache.  This means in this mode we
4372                  * don't need to clflush on the CPU side, and on the
4373                  * GPU side we only need to flush internal caches to
4374                  * get data visible to the CPU.
4375                  *
4376                  * However, we maintain the display planes as UC, and so
4377                  * need to rebind when first used as such.
4378                  */
4379                 obj->cache_level = I915_CACHE_LLC;
4380         } else
4381                 obj->cache_level = I915_CACHE_NONE;
4382
4383         trace_i915_gem_object_create(obj);
4384
4385         return obj;
4386 }
4387
4388 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4389 {
4390         /* If we are the last user of the backing storage (be it shmemfs
4391          * pages or stolen etc), we know that the pages are going to be
4392          * immediately released. In this case, we can then skip copying
4393          * back the contents from the GPU.
4394          */
4395
4396         if (obj->madv != I915_MADV_WILLNEED)
4397                 return false;
4398
4399         if (obj->base.filp == NULL)
4400                 return true;
4401
4402         /* At first glance, this looks racy, but then again so would be
4403          * userspace racing mmap against close. However, the first external
4404          * reference to the filp can only be obtained through the
4405          * i915_gem_mmap_ioctl() which safeguards us against the user
4406          * acquiring such a reference whilst we are in the middle of
4407          * freeing the object.
4408          */
4409         return atomic_long_read(&obj->base.filp->f_count) == 1;
4410 }
4411
4412 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4413 {
4414         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4415         struct drm_device *dev = obj->base.dev;
4416         struct drm_i915_private *dev_priv = dev->dev_private;
4417         struct i915_vma *vma, *next;
4418
4419         intel_runtime_pm_get(dev_priv);
4420
4421         trace_i915_gem_object_destroy(obj);
4422
4423         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4424                 int ret;
4425
4426                 vma->pin_count = 0;
4427                 ret = i915_vma_unbind(vma);
4428                 if (WARN_ON(ret == -ERESTARTSYS)) {
4429                         bool was_interruptible;
4430
4431                         was_interruptible = dev_priv->mm.interruptible;
4432                         dev_priv->mm.interruptible = false;
4433
4434                         WARN_ON(i915_vma_unbind(vma));
4435
4436                         dev_priv->mm.interruptible = was_interruptible;
4437                 }
4438         }
4439
4440         i915_gem_object_detach_phys(obj);
4441
4442         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4443          * before progressing. */
4444         if (obj->stolen)
4445                 i915_gem_object_unpin_pages(obj);
4446
4447         if (WARN_ON(obj->pages_pin_count))
4448                 obj->pages_pin_count = 0;
4449         if (discard_backing_storage(obj))
4450                 obj->madv = I915_MADV_DONTNEED;
4451         i915_gem_object_put_pages(obj);
4452         i915_gem_object_free_mmap_offset(obj);
4453         i915_gem_object_release_stolen(obj);
4454
4455         BUG_ON(obj->pages);
4456
4457         if (obj->base.import_attach)
4458                 drm_prime_gem_destroy(&obj->base, NULL);
4459
4460         if (obj->ops->release)
4461                 obj->ops->release(obj);
4462
4463         drm_gem_object_release(&obj->base);
4464         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4465
4466         kfree(obj->bit_17);
4467         i915_gem_object_free(obj);
4468
4469         intel_runtime_pm_put(dev_priv);
4470 }
4471
4472 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4473                                      struct i915_address_space *vm)
4474 {
4475         struct i915_vma *vma;
4476         list_for_each_entry(vma, &obj->vma_list, vma_link)
4477                 if (vma->vm == vm)
4478                         return vma;
4479
4480         return NULL;
4481 }
4482
4483 void i915_gem_vma_destroy(struct i915_vma *vma)
4484 {
4485         WARN_ON(vma->node.allocated);
4486
4487         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4488         if (!list_empty(&vma->exec_list))
4489                 return;
4490
4491         list_del(&vma->vma_link);
4492
4493         kfree(vma);
4494 }
4495
4496 static void
4497 i915_gem_stop_ringbuffers(struct drm_device *dev)
4498 {
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         struct intel_engine_cs *ring;
4501         int i;
4502
4503         for_each_ring(ring, dev_priv, i)
4504                 intel_stop_ring_buffer(ring);
4505 }
4506
4507 int
4508 i915_gem_suspend(struct drm_device *dev)
4509 {
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511         int ret = 0;
4512
4513         mutex_lock(&dev->struct_mutex);
4514         if (dev_priv->ums.mm_suspended)
4515                 goto err;
4516
4517         ret = i915_gpu_idle(dev);
4518         if (ret)
4519                 goto err;
4520
4521         i915_gem_retire_requests(dev);
4522
4523         /* Under UMS, be paranoid and evict. */
4524         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4525                 i915_gem_evict_everything(dev);
4526
4527         i915_kernel_lost_context(dev);
4528         i915_gem_stop_ringbuffers(dev);
4529
4530         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4531          * We need to replace this with a semaphore, or something.
4532          * And not confound ums.mm_suspended!
4533          */
4534         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4535                                                              DRIVER_MODESET);
4536         mutex_unlock(&dev->struct_mutex);
4537
4538         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4539         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4540         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4541
4542         return 0;
4543
4544 err:
4545         mutex_unlock(&dev->struct_mutex);
4546         return ret;
4547 }
4548
4549 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4550 {
4551         struct drm_device *dev = ring->dev;
4552         struct drm_i915_private *dev_priv = dev->dev_private;
4553         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4554         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4555         int i, ret;
4556
4557         if (!HAS_L3_DPF(dev) || !remap_info)
4558                 return 0;
4559
4560         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4561         if (ret)
4562                 return ret;
4563
4564         /*
4565          * Note: We do not worry about the concurrent register cacheline hang
4566          * here because no other code should access these registers other than
4567          * at initialization time.
4568          */
4569         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4570                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4571                 intel_ring_emit(ring, reg_base + i);
4572                 intel_ring_emit(ring, remap_info[i/4]);
4573         }
4574
4575         intel_ring_advance(ring);
4576
4577         return ret;
4578 }
4579
4580 void i915_gem_init_swizzling(struct drm_device *dev)
4581 {
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583
4584         if (INTEL_INFO(dev)->gen < 5 ||
4585             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4586                 return;
4587
4588         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4589                                  DISP_TILE_SURFACE_SWIZZLING);
4590
4591         if (IS_GEN5(dev))
4592                 return;
4593
4594         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4595         if (IS_GEN6(dev))
4596                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4597         else if (IS_GEN7(dev))
4598                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4599         else if (IS_GEN8(dev))
4600                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4601         else
4602                 BUG();
4603 }
4604
4605 static bool
4606 intel_enable_blt(struct drm_device *dev)
4607 {
4608         if (!HAS_BLT(dev))
4609                 return false;
4610
4611         /* The blitter was dysfunctional on early prototypes */
4612         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4613                 DRM_INFO("BLT not supported on this pre-production hardware;"
4614                          " graphics performance will be degraded.\n");
4615                 return false;
4616         }
4617
4618         return true;
4619 }
4620
4621 static int i915_gem_init_rings(struct drm_device *dev)
4622 {
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624         int ret;
4625
4626         ret = intel_init_render_ring_buffer(dev);
4627         if (ret)
4628                 return ret;
4629
4630         if (HAS_BSD(dev)) {
4631                 ret = intel_init_bsd_ring_buffer(dev);
4632                 if (ret)
4633                         goto cleanup_render_ring;
4634         }
4635
4636         if (intel_enable_blt(dev)) {
4637                 ret = intel_init_blt_ring_buffer(dev);
4638                 if (ret)
4639                         goto cleanup_bsd_ring;
4640         }
4641
4642         if (HAS_VEBOX(dev)) {
4643                 ret = intel_init_vebox_ring_buffer(dev);
4644                 if (ret)
4645                         goto cleanup_blt_ring;
4646         }
4647
4648         if (HAS_BSD2(dev)) {
4649                 ret = intel_init_bsd2_ring_buffer(dev);
4650                 if (ret)
4651                         goto cleanup_vebox_ring;
4652         }
4653
4654         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4655         if (ret)
4656                 goto cleanup_bsd2_ring;
4657
4658         return 0;
4659
4660 cleanup_bsd2_ring:
4661         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4662 cleanup_vebox_ring:
4663         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4664 cleanup_blt_ring:
4665         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4666 cleanup_bsd_ring:
4667         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4668 cleanup_render_ring:
4669         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4670
4671         return ret;
4672 }
4673
4674 int
4675 i915_gem_init_hw(struct drm_device *dev)
4676 {
4677         struct drm_i915_private *dev_priv = dev->dev_private;
4678         int ret, i;
4679
4680         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4681                 return -EIO;
4682
4683         if (dev_priv->ellc_size)
4684                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4685
4686         if (IS_HASWELL(dev))
4687                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4688                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4689
4690         if (HAS_PCH_NOP(dev)) {
4691                 if (IS_IVYBRIDGE(dev)) {
4692                         u32 temp = I915_READ(GEN7_MSG_CTL);
4693                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4694                         I915_WRITE(GEN7_MSG_CTL, temp);
4695                 } else if (INTEL_INFO(dev)->gen >= 7) {
4696                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4697                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4698                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4699                 }
4700         }
4701
4702         i915_gem_init_swizzling(dev);
4703
4704         ret = i915_gem_init_rings(dev);
4705         if (ret)
4706                 return ret;
4707
4708         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4709                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4710
4711         /*
4712          * XXX: Contexts should only be initialized once. Doing a switch to the
4713          * default context switch however is something we'd like to do after
4714          * reset or thaw (the latter may not actually be necessary for HW, but
4715          * goes with our code better). Context switching requires rings (for
4716          * the do_switch), but before enabling PPGTT. So don't move this.
4717          */
4718         ret = i915_gem_context_enable(dev_priv);
4719         if (ret && ret != -EIO) {
4720                 DRM_ERROR("Context enable failed %d\n", ret);
4721                 i915_gem_cleanup_ringbuffer(dev);
4722         }
4723
4724         return ret;
4725 }
4726
4727 int i915_gem_init(struct drm_device *dev)
4728 {
4729         struct drm_i915_private *dev_priv = dev->dev_private;
4730         int ret;
4731
4732         mutex_lock(&dev->struct_mutex);
4733
4734         if (IS_VALLEYVIEW(dev)) {
4735                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4736                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4737                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4738                               VLV_GTLC_ALLOWWAKEACK), 10))
4739                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4740         }
4741
4742         i915_gem_init_userptr(dev);
4743         i915_gem_init_global_gtt(dev);
4744
4745         ret = i915_gem_context_init(dev);
4746         if (ret) {
4747                 mutex_unlock(&dev->struct_mutex);
4748                 return ret;
4749         }
4750
4751         ret = i915_gem_init_hw(dev);
4752         if (ret == -EIO) {
4753                 /* Allow ring initialisation to fail by marking the GPU as
4754                  * wedged. But we only want to do this where the GPU is angry,
4755                  * for all other failure, such as an allocation failure, bail.
4756                  */
4757                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4758                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4759                 ret = 0;
4760         }
4761         mutex_unlock(&dev->struct_mutex);
4762
4763         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4764         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4765                 dev_priv->dri1.allow_batchbuffer = 1;
4766         return ret;
4767 }
4768
4769 void
4770 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4771 {
4772         struct drm_i915_private *dev_priv = dev->dev_private;
4773         struct intel_engine_cs *ring;
4774         int i;
4775
4776         for_each_ring(ring, dev_priv, i)
4777                 intel_cleanup_ring_buffer(ring);
4778 }
4779
4780 int
4781 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4782                        struct drm_file *file_priv)
4783 {
4784         struct drm_i915_private *dev_priv = dev->dev_private;
4785         int ret;
4786
4787         if (drm_core_check_feature(dev, DRIVER_MODESET))
4788                 return 0;
4789
4790         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4791                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4792                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4793         }
4794
4795         mutex_lock(&dev->struct_mutex);
4796         dev_priv->ums.mm_suspended = 0;
4797
4798         ret = i915_gem_init_hw(dev);
4799         if (ret != 0) {
4800                 mutex_unlock(&dev->struct_mutex);
4801                 return ret;
4802         }
4803
4804         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4805
4806         ret = drm_irq_install(dev, dev->pdev->irq);
4807         if (ret)
4808                 goto cleanup_ringbuffer;
4809         mutex_unlock(&dev->struct_mutex);
4810
4811         return 0;
4812
4813 cleanup_ringbuffer:
4814         i915_gem_cleanup_ringbuffer(dev);
4815         dev_priv->ums.mm_suspended = 1;
4816         mutex_unlock(&dev->struct_mutex);
4817
4818         return ret;
4819 }
4820
4821 int
4822 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4823                        struct drm_file *file_priv)
4824 {
4825         if (drm_core_check_feature(dev, DRIVER_MODESET))
4826                 return 0;
4827
4828         mutex_lock(&dev->struct_mutex);
4829         drm_irq_uninstall(dev);
4830         mutex_unlock(&dev->struct_mutex);
4831
4832         return i915_gem_suspend(dev);
4833 }
4834
4835 void
4836 i915_gem_lastclose(struct drm_device *dev)
4837 {
4838         int ret;
4839
4840         if (drm_core_check_feature(dev, DRIVER_MODESET))
4841                 return;
4842
4843         ret = i915_gem_suspend(dev);
4844         if (ret)
4845                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4846 }
4847
4848 static void
4849 init_ring_lists(struct intel_engine_cs *ring)
4850 {
4851         INIT_LIST_HEAD(&ring->active_list);
4852         INIT_LIST_HEAD(&ring->request_list);
4853 }
4854
4855 void i915_init_vm(struct drm_i915_private *dev_priv,
4856                   struct i915_address_space *vm)
4857 {
4858         if (!i915_is_ggtt(vm))
4859                 drm_mm_init(&vm->mm, vm->start, vm->total);
4860         vm->dev = dev_priv->dev;
4861         INIT_LIST_HEAD(&vm->active_list);
4862         INIT_LIST_HEAD(&vm->inactive_list);
4863         INIT_LIST_HEAD(&vm->global_link);
4864         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4865 }
4866
4867 void
4868 i915_gem_load(struct drm_device *dev)
4869 {
4870         struct drm_i915_private *dev_priv = dev->dev_private;
4871         int i;
4872
4873         dev_priv->slab =
4874                 kmem_cache_create("i915_gem_object",
4875                                   sizeof(struct drm_i915_gem_object), 0,
4876                                   SLAB_HWCACHE_ALIGN,
4877                                   NULL);
4878
4879         INIT_LIST_HEAD(&dev_priv->vm_list);
4880         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4881
4882         INIT_LIST_HEAD(&dev_priv->context_list);
4883         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4884         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4885         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4886         for (i = 0; i < I915_NUM_RINGS; i++)
4887                 init_ring_lists(&dev_priv->ring[i]);
4888         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4889                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4890         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4891                           i915_gem_retire_work_handler);
4892         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4893                           i915_gem_idle_work_handler);
4894         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4895
4896         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4897         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4898                 I915_WRITE(MI_ARB_STATE,
4899                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4900         }
4901
4902         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4903
4904         /* Old X drivers will take 0-2 for front, back, depth buffers */
4905         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4906                 dev_priv->fence_reg_start = 3;
4907
4908         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4909                 dev_priv->num_fence_regs = 32;
4910         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4911                 dev_priv->num_fence_regs = 16;
4912         else
4913                 dev_priv->num_fence_regs = 8;
4914
4915         /* Initialize fence registers to zero */
4916         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4917         i915_gem_restore_fences(dev);
4918
4919         i915_gem_detect_bit_6_swizzle(dev);
4920         init_waitqueue_head(&dev_priv->pending_flip_queue);
4921
4922         dev_priv->mm.interruptible = true;
4923
4924         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4925         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4926         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4927         register_shrinker(&dev_priv->mm.shrinker);
4928
4929         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4930         register_oom_notifier(&dev_priv->mm.oom_notifier);
4931 }
4932
4933 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4934 {
4935         struct drm_i915_file_private *file_priv = file->driver_priv;
4936
4937         cancel_delayed_work_sync(&file_priv->mm.idle_work);
4938
4939         /* Clean up our request list when the client is going away, so that
4940          * later retire_requests won't dereference our soon-to-be-gone
4941          * file_priv.
4942          */
4943         spin_lock(&file_priv->mm.lock);
4944         while (!list_empty(&file_priv->mm.request_list)) {
4945                 struct drm_i915_gem_request *request;
4946
4947                 request = list_first_entry(&file_priv->mm.request_list,
4948                                            struct drm_i915_gem_request,
4949                                            client_list);
4950                 list_del(&request->client_list);
4951                 request->file_priv = NULL;
4952         }
4953         spin_unlock(&file_priv->mm.lock);
4954 }
4955
4956 static void
4957 i915_gem_file_idle_work_handler(struct work_struct *work)
4958 {
4959         struct drm_i915_file_private *file_priv =
4960                 container_of(work, typeof(*file_priv), mm.idle_work.work);
4961
4962         atomic_set(&file_priv->rps_wait_boost, false);
4963 }
4964
4965 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4966 {
4967         struct drm_i915_file_private *file_priv;
4968         int ret;
4969
4970         DRM_DEBUG_DRIVER("\n");
4971
4972         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4973         if (!file_priv)
4974                 return -ENOMEM;
4975
4976         file->driver_priv = file_priv;
4977         file_priv->dev_priv = dev->dev_private;
4978         file_priv->file = file;
4979
4980         spin_lock_init(&file_priv->mm.lock);
4981         INIT_LIST_HEAD(&file_priv->mm.request_list);
4982         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4983                           i915_gem_file_idle_work_handler);
4984
4985         ret = i915_gem_context_open(dev, file);
4986         if (ret)
4987                 kfree(file_priv);
4988
4989         return ret;
4990 }
4991
4992 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4993 {
4994         if (!mutex_is_locked(mutex))
4995                 return false;
4996
4997 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4998         return mutex->owner == task;
4999 #else
5000         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5001         return false;
5002 #endif
5003 }
5004
5005 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5006 {
5007         if (!mutex_trylock(&dev->struct_mutex)) {
5008                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5009                         return false;
5010
5011                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5012                         return false;
5013
5014                 *unlock = false;
5015         } else
5016                 *unlock = true;
5017
5018         return true;
5019 }
5020
5021 static int num_vma_bound(struct drm_i915_gem_object *obj)
5022 {
5023         struct i915_vma *vma;
5024         int count = 0;
5025
5026         list_for_each_entry(vma, &obj->vma_list, vma_link)
5027                 if (drm_mm_node_allocated(&vma->node))
5028                         count++;
5029
5030         return count;
5031 }
5032
5033 static unsigned long
5034 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5035 {
5036         struct drm_i915_private *dev_priv =
5037                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5038         struct drm_device *dev = dev_priv->dev;
5039         struct drm_i915_gem_object *obj;
5040         unsigned long count;
5041         bool unlock;
5042
5043         if (!i915_gem_shrinker_lock(dev, &unlock))
5044                 return 0;
5045
5046         count = 0;
5047         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5048                 if (obj->pages_pin_count == 0)
5049                         count += obj->base.size >> PAGE_SHIFT;
5050
5051         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5052                 if (!i915_gem_obj_is_pinned(obj) &&
5053                     obj->pages_pin_count == num_vma_bound(obj))
5054                         count += obj->base.size >> PAGE_SHIFT;
5055         }
5056
5057         if (unlock)
5058                 mutex_unlock(&dev->struct_mutex);
5059
5060         return count;
5061 }
5062
5063 /* All the new VM stuff */
5064 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5065                                   struct i915_address_space *vm)
5066 {
5067         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5068         struct i915_vma *vma;
5069
5070         if (!dev_priv->mm.aliasing_ppgtt ||
5071             vm == &dev_priv->mm.aliasing_ppgtt->base)
5072                 vm = &dev_priv->gtt.base;
5073
5074         BUG_ON(list_empty(&o->vma_list));
5075         list_for_each_entry(vma, &o->vma_list, vma_link) {
5076                 if (vma->vm == vm)
5077                         return vma->node.start;
5078
5079         }
5080         return -1;
5081 }
5082
5083 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5084                         struct i915_address_space *vm)
5085 {
5086         struct i915_vma *vma;
5087
5088         list_for_each_entry(vma, &o->vma_list, vma_link)
5089                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5090                         return true;
5091
5092         return false;
5093 }
5094
5095 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5096 {
5097         struct i915_vma *vma;
5098
5099         list_for_each_entry(vma, &o->vma_list, vma_link)
5100                 if (drm_mm_node_allocated(&vma->node))
5101                         return true;
5102
5103         return false;
5104 }
5105
5106 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5107                                 struct i915_address_space *vm)
5108 {
5109         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5110         struct i915_vma *vma;
5111
5112         if (!dev_priv->mm.aliasing_ppgtt ||
5113             vm == &dev_priv->mm.aliasing_ppgtt->base)
5114                 vm = &dev_priv->gtt.base;
5115
5116         BUG_ON(list_empty(&o->vma_list));
5117
5118         list_for_each_entry(vma, &o->vma_list, vma_link)
5119                 if (vma->vm == vm)
5120                         return vma->node.size;
5121
5122         return 0;
5123 }
5124
5125 static unsigned long
5126 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5127 {
5128         struct drm_i915_private *dev_priv =
5129                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5130         struct drm_device *dev = dev_priv->dev;
5131         unsigned long freed;
5132         bool unlock;
5133
5134         if (!i915_gem_shrinker_lock(dev, &unlock))
5135                 return SHRINK_STOP;
5136
5137         freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5138         if (freed < sc->nr_to_scan)
5139                 freed += __i915_gem_shrink(dev_priv,
5140                                            sc->nr_to_scan - freed,
5141                                            false);
5142         if (unlock)
5143                 mutex_unlock(&dev->struct_mutex);
5144
5145         return freed;
5146 }
5147
5148 static int
5149 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5150 {
5151         struct drm_i915_private *dev_priv =
5152                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5153         struct drm_device *dev = dev_priv->dev;
5154         struct drm_i915_gem_object *obj;
5155         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5156         unsigned long pinned, bound, unbound, freed;
5157         bool was_interruptible;
5158         bool unlock;
5159
5160         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout)
5161                 schedule_timeout_killable(1);
5162         if (timeout == 0) {
5163                 pr_err("Unable to purge GPU memory due lock contention.\n");
5164                 return NOTIFY_DONE;
5165         }
5166
5167         was_interruptible = dev_priv->mm.interruptible;
5168         dev_priv->mm.interruptible = false;
5169
5170         freed = i915_gem_shrink_all(dev_priv);
5171
5172         dev_priv->mm.interruptible = was_interruptible;
5173
5174         /* Because we may be allocating inside our own driver, we cannot
5175          * assert that there are no objects with pinned pages that are not
5176          * being pointed to by hardware.
5177          */
5178         unbound = bound = pinned = 0;
5179         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5180                 if (!obj->base.filp) /* not backed by a freeable object */
5181                         continue;
5182
5183                 if (obj->pages_pin_count)
5184                         pinned += obj->base.size;
5185                 else
5186                         unbound += obj->base.size;
5187         }
5188         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5189                 if (!obj->base.filp)
5190                         continue;
5191
5192                 if (obj->pages_pin_count)
5193                         pinned += obj->base.size;
5194                 else
5195                         bound += obj->base.size;
5196         }
5197
5198         if (unlock)
5199                 mutex_unlock(&dev->struct_mutex);
5200
5201         pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5202                 freed, pinned);
5203         if (unbound || bound)
5204                 pr_err("%lu and %lu bytes still available in the "
5205                        "bound and unbound GPU page lists.\n",
5206                        bound, unbound);
5207
5208         *(unsigned long *)ptr += freed;
5209         return NOTIFY_DONE;
5210 }
5211
5212 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5213 {
5214         struct i915_vma *vma;
5215
5216         /* This WARN has probably outlived its usefulness (callers already
5217          * WARN if they don't find the GGTT vma they expect). When removing,
5218          * remember to remove the pre-check in is_pin_display() as well */
5219         if (WARN_ON(list_empty(&obj->vma_list)))
5220                 return NULL;
5221
5222         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5223         if (vma->vm != obj_to_ggtt(obj))
5224                 return NULL;
5225
5226         return vma;
5227 }