1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/perf_event.h>
44 #include <linux/pm_qos.h>
45 #include <linux/reservation.h>
46 #include <linux/shmem_fs.h>
49 #include <drm/intel-gtt.h>
50 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
51 #include <drm/drm_gem.h>
52 #include <drm/drm_auth.h>
53 #include <drm/drm_cache.h>
55 #include "i915_params.h"
57 #include "i915_utils.h"
59 #include "intel_bios.h"
60 #include "intel_device_info.h"
61 #include "intel_display.h"
62 #include "intel_dpll_mgr.h"
63 #include "intel_lrc.h"
64 #include "intel_opregion.h"
65 #include "intel_ringbuffer.h"
66 #include "intel_uncore.h"
67 #include "intel_wopcm.h"
71 #include "i915_gem_context.h"
72 #include "i915_gem_fence_reg.h"
73 #include "i915_gem_object.h"
74 #include "i915_gem_gtt.h"
75 #include "i915_gem_timeline.h"
76 #include "i915_gpu_error.h"
77 #include "i915_request.h"
78 #include "i915_scheduler.h"
81 #include "intel_gvt.h"
83 /* General customization:
86 #define DRIVER_NAME "i915"
87 #define DRIVER_DESC "Intel Graphics"
88 #define DRIVER_DATE "20180413"
89 #define DRIVER_TIMESTAMP 1523611258
91 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
92 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
93 * which may not necessarily be a user visible problem. This will either
94 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
95 * enable distros and users to tailor their preferred amount of i915 abrt
98 #define I915_STATE_WARN(condition, format...) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) \
101 if (!WARN(i915_modparams.verbose_state_checks, format)) \
103 unlikely(__ret_warn_on); \
106 #define I915_STATE_WARN_ON(x) \
107 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
109 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
110 bool __i915_inject_load_failure(const char *func, int line);
111 #define i915_inject_load_failure() \
112 __i915_inject_load_failure(__func__, __LINE__)
114 #define i915_inject_load_failure() false
119 } uint_fixed_16_16_t;
121 #define FP_16_16_MAX ({ \
122 uint_fixed_16_16_t fp; \
127 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
134 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
136 uint_fixed_16_16_t fp;
138 WARN_ON(val > U16_MAX);
144 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
146 return DIV_ROUND_UP(fp.val, 1 << 16);
149 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
154 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
155 uint_fixed_16_16_t min2)
157 uint_fixed_16_16_t min;
159 min.val = min(min1.val, min2.val);
163 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
164 uint_fixed_16_16_t max2)
166 uint_fixed_16_16_t max;
168 max.val = max(max1.val, max2.val);
172 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
174 uint_fixed_16_16_t fp;
175 WARN_ON(val > U32_MAX);
176 fp.val = (uint32_t) val;
180 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
181 uint_fixed_16_16_t d)
183 return DIV_ROUND_UP(val.val, d.val);
186 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
187 uint_fixed_16_16_t mul)
189 uint64_t intermediate_val;
191 intermediate_val = (uint64_t) val * mul.val;
192 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
193 WARN_ON(intermediate_val > U32_MAX);
194 return (uint32_t) intermediate_val;
197 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
198 uint_fixed_16_16_t mul)
200 uint64_t intermediate_val;
202 intermediate_val = (uint64_t) val.val * mul.val;
203 intermediate_val = intermediate_val >> 16;
204 return clamp_u64_to_fixed16(intermediate_val);
207 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
211 interm_val = (uint64_t)val << 16;
212 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
213 return clamp_u64_to_fixed16(interm_val);
216 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
217 uint_fixed_16_16_t d)
221 interm_val = (uint64_t)val << 16;
222 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
223 WARN_ON(interm_val > U32_MAX);
224 return (uint32_t) interm_val;
227 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
228 uint_fixed_16_16_t mul)
230 uint64_t intermediate_val;
232 intermediate_val = (uint64_t) val * mul.val;
233 return clamp_u64_to_fixed16(intermediate_val);
236 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
237 uint_fixed_16_16_t add2)
241 interm_sum = (uint64_t) add1.val + add2.val;
242 return clamp_u64_to_fixed16(interm_sum);
245 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
249 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
251 interm_sum = (uint64_t) add1.val + interm_add2.val;
252 return clamp_u64_to_fixed16(interm_sum);
257 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
270 #define for_each_hpd_pin(__pin) \
271 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
273 #define HPD_STORM_DEFAULT_THRESHOLD 5
275 struct i915_hotplug {
276 struct work_struct hotplug_work;
279 unsigned long last_jiffies;
284 HPD_MARK_DISABLED = 2
286 } stats[HPD_NUM_PINS];
288 struct delayed_work reenable_work;
290 struct intel_digital_port *irq_port[I915_MAX_PORTS];
293 struct work_struct dig_port_work;
295 struct work_struct poll_init_work;
298 unsigned int hpd_storm_threshold;
301 * if we get a HPD irq from DP and a HPD irq from non-DP
302 * the non-DP HPD could block the workqueue on a mode config
303 * mutex getting, that userspace may have taken. However
304 * userspace is waiting on the DP workqueue to run which is
305 * blocked behind the non-DP one.
307 struct workqueue_struct *dp_wq;
310 #define I915_GEM_GPU_DOMAINS \
311 (I915_GEM_DOMAIN_RENDER | \
312 I915_GEM_DOMAIN_SAMPLER | \
313 I915_GEM_DOMAIN_COMMAND | \
314 I915_GEM_DOMAIN_INSTRUCTION | \
315 I915_GEM_DOMAIN_VERTEX)
317 struct drm_i915_private;
318 struct i915_mm_struct;
319 struct i915_mmu_object;
321 struct drm_i915_file_private {
322 struct drm_i915_private *dev_priv;
323 struct drm_file *file;
327 struct list_head request_list;
328 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
329 * chosen to prevent the CPU getting more than a frame ahead of the GPU
330 * (when using lax throttling for the frontbuffer). We also use it to
331 * offer free GPU waitboosts for severely congested workloads.
333 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
335 struct idr context_idr;
337 struct intel_rps_client {
341 unsigned int bsd_engine;
343 /* Client can have a maximum of 3 contexts banned before
344 * it is denied of creating new contexts. As one context
345 * ban needs 4 consecutive hangs, and more if there is
346 * progress in between, this is a last resort stop gap measure
347 * to limit the badly behaving clients access to gpu.
349 #define I915_MAX_CLIENT_CONTEXT_BANS 3
350 atomic_t context_bans;
353 /* Interface history:
356 * 1.2: Add Power Management
357 * 1.3: Add vblank support
358 * 1.4: Fix cmdbuffer path, add heap destroy
359 * 1.5: Add vblank pipe configuration
360 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
361 * - Support vertical blank on secondary display pipe
363 #define DRIVER_MAJOR 1
364 #define DRIVER_MINOR 6
365 #define DRIVER_PATCHLEVEL 0
367 struct intel_overlay;
368 struct intel_overlay_error_state;
370 struct sdvo_device_mapping {
379 struct intel_connector;
380 struct intel_encoder;
381 struct intel_atomic_state;
382 struct intel_crtc_state;
383 struct intel_initial_plane_config;
387 struct intel_cdclk_state;
389 struct drm_i915_display_funcs {
390 void (*get_cdclk)(struct drm_i915_private *dev_priv,
391 struct intel_cdclk_state *cdclk_state);
392 void (*set_cdclk)(struct drm_i915_private *dev_priv,
393 const struct intel_cdclk_state *cdclk_state);
394 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
395 enum i9xx_plane_id i9xx_plane);
396 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
397 int (*compute_intermediate_wm)(struct drm_device *dev,
398 struct intel_crtc *intel_crtc,
399 struct intel_crtc_state *newstate);
400 void (*initial_watermarks)(struct intel_atomic_state *state,
401 struct intel_crtc_state *cstate);
402 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
403 struct intel_crtc_state *cstate);
404 void (*optimize_watermarks)(struct intel_atomic_state *state,
405 struct intel_crtc_state *cstate);
406 int (*compute_global_watermarks)(struct drm_atomic_state *state);
407 void (*update_wm)(struct intel_crtc *crtc);
408 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
409 /* Returns the active state of the crtc, and if the crtc is active,
410 * fills out the pipe-config with the hw state. */
411 bool (*get_pipe_config)(struct intel_crtc *,
412 struct intel_crtc_state *);
413 void (*get_initial_plane_config)(struct intel_crtc *,
414 struct intel_initial_plane_config *);
415 int (*crtc_compute_clock)(struct intel_crtc *crtc,
416 struct intel_crtc_state *crtc_state);
417 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
418 struct drm_atomic_state *old_state);
419 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
420 struct drm_atomic_state *old_state);
421 void (*update_crtcs)(struct drm_atomic_state *state);
422 void (*audio_codec_enable)(struct intel_encoder *encoder,
423 const struct intel_crtc_state *crtc_state,
424 const struct drm_connector_state *conn_state);
425 void (*audio_codec_disable)(struct intel_encoder *encoder,
426 const struct intel_crtc_state *old_crtc_state,
427 const struct drm_connector_state *old_conn_state);
428 void (*fdi_link_train)(struct intel_crtc *crtc,
429 const struct intel_crtc_state *crtc_state);
430 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
431 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
432 /* clock updates for mode set */
434 /* render clock increase/decrease */
435 /* display clock increase/decrease */
436 /* pll clock increase/decrease */
438 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
439 void (*load_luts)(struct drm_crtc_state *crtc_state);
442 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
443 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
444 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
447 struct work_struct work;
449 uint32_t *dmc_payload;
450 uint32_t dmc_fw_size;
453 i915_reg_t mmioaddr[8];
454 uint32_t mmiodata[8];
456 uint32_t allowed_dc_mask;
459 enum i915_cache_level {
461 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
462 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
463 caches, eg sampler/render caches, and the
464 large Last-Level-Cache. LLC is coherent with
465 the CPU, but L3 is only visible to the GPU. */
466 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
469 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
480 /* This is always the inner lock when overlapping with struct_mutex and
481 * it's the outer lock when overlapping with stolen_lock. */
484 unsigned int possible_framebuffer_bits;
485 unsigned int busy_bits;
486 unsigned int visible_pipes_mask;
487 struct intel_crtc *crtc;
489 struct drm_mm_node compressed_fb;
490 struct drm_mm_node *compressed_llb;
497 bool underrun_detected;
498 struct work_struct underrun_work;
501 * Due to the atomic rules we can't access some structures without the
502 * appropriate locking, so we cache information here in order to avoid
505 struct intel_fbc_state_cache {
506 struct i915_vma *vma;
510 unsigned int mode_flags;
511 uint32_t hsw_bdw_pixel_rate;
515 unsigned int rotation;
520 * Display surface base address adjustement for
521 * pageflips. Note that on gen4+ this only adjusts up
522 * to a tile, offsets within a tile are handled in
523 * the hw itself (with the TILEOFF register).
532 const struct drm_format_info *format;
538 * This structure contains everything that's relevant to program the
539 * hardware registers. When we want to figure out if we need to disable
540 * and re-enable FBC for a new configuration we just check if there's
541 * something different in the struct. The genx_fbc_activate functions
542 * are supposed to read from it in order to program the registers.
544 struct intel_fbc_reg_params {
545 struct i915_vma *vma;
550 enum i9xx_plane_id i9xx_plane;
551 unsigned int fence_y_offset;
555 const struct drm_format_info *format;
560 unsigned int gen9_wa_cfb_stride;
563 struct intel_fbc_work {
565 u64 scheduled_vblank;
566 struct work_struct work;
569 const char *no_fbc_reason;
573 * HIGH_RR is the highest eDP panel refresh rate read from EDID
574 * LOW_RR is the lowest eDP panel refresh rate found from EDID
575 * parsing for same resolution.
577 enum drrs_refresh_rate_type {
580 DRRS_MAX_RR, /* RR count */
583 enum drrs_support_type {
584 DRRS_NOT_SUPPORTED = 0,
585 STATIC_DRRS_SUPPORT = 1,
586 SEAMLESS_DRRS_SUPPORT = 2
592 struct delayed_work work;
594 unsigned busy_frontbuffer_bits;
595 enum drrs_refresh_rate_type refresh_rate_type;
596 enum drrs_support_type type;
602 struct intel_dp *enabled;
604 struct delayed_work work;
605 unsigned busy_frontbuffer_bits;
606 bool sink_psr2_support;
608 bool colorimetry_support;
610 bool has_hw_tracking;
612 u8 sink_sync_latency;
614 ktime_t last_entry_attempt;
617 void (*enable_source)(struct intel_dp *,
618 const struct intel_crtc_state *);
619 void (*disable_source)(struct intel_dp *,
620 const struct intel_crtc_state *);
621 void (*enable_sink)(struct intel_dp *);
622 void (*activate)(struct intel_dp *);
623 void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
627 PCH_NONE = 0, /* No PCH present */
628 PCH_IBX, /* Ibexpeak PCH */
629 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
630 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
631 PCH_SPT, /* Sunrisepoint PCH */
632 PCH_KBP, /* Kaby Lake PCH */
633 PCH_CNP, /* Cannon Lake PCH */
634 PCH_ICP, /* Ice Lake PCH */
638 enum intel_sbi_destination {
643 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
644 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
645 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
646 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
647 #define QUIRK_INCREASE_T12_DELAY (1<<6)
650 struct intel_fbc_work;
653 struct i2c_adapter adapter;
654 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
658 struct i2c_algo_bit_data bit_algo;
659 struct drm_i915_private *dev_priv;
662 struct i915_suspend_saved_registers {
665 u32 saveCACHE_MODE_0;
666 u32 saveMI_ARB_STATE;
670 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
671 u32 savePCH_PORT_HOTPLUG;
675 struct vlv_s0ix_state {
682 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
683 u32 media_max_req_count;
684 u32 gfx_max_req_count;
716 /* Display 1 CZ domain */
721 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
723 /* GT SA CZ domain */
730 /* Display 2 CZ domain */
737 struct intel_rps_ei {
745 * work, interrupts_enabled and pm_iir are protected by
748 struct work_struct work;
749 bool interrupts_enabled;
752 /* PM interrupt bits that should never be masked */
755 /* Frequencies are stored in potentially platform dependent multiples.
756 * In other words, *_freq needs to be multiplied by X to be interesting.
757 * Soft limits are those which are used for the dynamic reclocking done
758 * by the driver (raise frequencies under heavy loads, and lower for
759 * lighter loads). Hard limits are those imposed by the hardware.
761 * A distinction is made for overclocking, which is never enabled by
762 * default, and is considered to be above the hard limit if it's
765 u8 cur_freq; /* Current frequency (cached, may not == HW) */
766 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
767 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
768 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
769 u8 min_freq; /* AKA RPn. Minimum frequency */
770 u8 boost_freq; /* Frequency to request when wait boosting */
771 u8 idle_freq; /* Frequency to request when we are idle */
772 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
773 u8 rp1_freq; /* "less than" RP0 power/freqency */
774 u8 rp0_freq; /* Non-overclocked max frequency. */
775 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
777 u8 up_threshold; /* Current %busy required to uplock */
778 u8 down_threshold; /* Current %busy required to downclock */
781 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
784 atomic_t num_waiters;
787 /* manual wa residency calculations */
788 struct intel_rps_ei ei;
793 u64 prev_hw_residency[4];
794 u64 cur_residency[4];
797 struct intel_llc_pstate {
801 struct intel_gen6_power_mgmt {
802 struct intel_rps rps;
803 struct intel_rc6 rc6;
804 struct intel_llc_pstate llc_pstate;
807 /* defined intel_pm.c */
808 extern spinlock_t mchdev_lock;
810 struct intel_ilk_power_mgmt {
818 unsigned long last_time1;
819 unsigned long chipset_power;
822 unsigned long gfx_power;
829 struct drm_i915_private;
830 struct i915_power_well;
832 struct i915_power_well_ops {
834 * Synchronize the well's hw state to match the current sw state, for
835 * example enable/disable it based on the current refcount. Called
836 * during driver init and resume time, possibly after first calling
837 * the enable/disable handlers.
839 void (*sync_hw)(struct drm_i915_private *dev_priv,
840 struct i915_power_well *power_well);
842 * Enable the well and resources that depend on it (for example
843 * interrupts located on the well). Called after the 0->1 refcount
846 void (*enable)(struct drm_i915_private *dev_priv,
847 struct i915_power_well *power_well);
849 * Disable the well and resources that depend on it. Called after
850 * the 1->0 refcount transition.
852 void (*disable)(struct drm_i915_private *dev_priv,
853 struct i915_power_well *power_well);
854 /* Returns the hw enabled state. */
855 bool (*is_enabled)(struct drm_i915_private *dev_priv,
856 struct i915_power_well *power_well);
859 /* Power well structure for haswell */
860 struct i915_power_well {
863 /* power well enable/disable usage count */
865 /* cached hw enabled state */
868 /* unique identifier for this power well */
869 enum i915_power_well_id id;
871 * Arbitraty data associated with this power well. Platform and power
879 /* Mask of pipes whose IRQ logic is backed by the pw */
881 /* The pw is backing the VGA functionality */
886 const struct i915_power_well_ops *ops;
889 struct i915_power_domains {
891 * Power wells needed for initialization at driver init and suspend
892 * time are on. They are kept on until after the first modeset.
896 int power_well_count;
899 int domain_use_count[POWER_DOMAIN_NUM];
900 struct i915_power_well *power_wells;
903 #define MAX_L3_SLICES 2
904 struct intel_l3_parity {
905 u32 *remap_info[MAX_L3_SLICES];
906 struct work_struct error_work;
911 /** Memory allocator for GTT stolen memory */
912 struct drm_mm stolen;
913 /** Protects the usage of the GTT stolen memory allocator. This is
914 * always the inner lock when overlapping with struct_mutex. */
915 struct mutex stolen_lock;
917 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
920 /** List of all objects in gtt_space. Used to restore gtt
921 * mappings on resume */
922 struct list_head bound_list;
924 * List of objects which are not bound to the GTT (thus
925 * are idle and not used by the GPU). These objects may or may
926 * not actually have any pages attached.
928 struct list_head unbound_list;
930 /** List of all objects in gtt_space, currently mmaped by userspace.
931 * All objects within this list must also be on bound_list.
933 struct list_head userfault_list;
936 * List of objects which are pending destruction.
938 struct llist_head free_list;
939 struct work_struct free_work;
940 spinlock_t free_lock;
942 * Count of objects pending destructions. Used to skip needlessly
943 * waiting on an RCU barrier if no objects are waiting to be freed.
948 * Small stash of WC pages
950 struct pagevec wc_stash;
953 * tmpfs instance used for shmem backed objects
955 struct vfsmount *gemfs;
957 /** PPGTT used for aliasing the PPGTT with the GTT */
958 struct i915_hw_ppgtt *aliasing_ppgtt;
960 struct notifier_block oom_notifier;
961 struct notifier_block vmap_notifier;
962 struct shrinker shrinker;
964 /** LRU list of objects with fence regs on them. */
965 struct list_head fence_list;
968 * Workqueue to fault in userptr pages, flushed by the execbuf
969 * when required but otherwise left to userspace to try again
972 struct workqueue_struct *userptr_wq;
974 u64 unordered_timeline;
976 /* the indicator for dispatch video commands on two BSD rings */
977 atomic_t bsd_engine_dispatch_index;
979 /** Bit 6 swizzling required for X tiling */
980 uint32_t bit_6_swizzle_x;
981 /** Bit 6 swizzling required for Y tiling */
982 uint32_t bit_6_swizzle_y;
984 /* accounting, useful for userland debugging */
985 spinlock_t object_stat_lock;
990 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
992 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
993 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
995 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
996 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
998 enum modeset_restore {
1004 #define DP_AUX_A 0x40
1005 #define DP_AUX_B 0x10
1006 #define DP_AUX_C 0x20
1007 #define DP_AUX_D 0x30
1008 #define DP_AUX_F 0x60
1010 #define DDC_PIN_B 0x05
1011 #define DDC_PIN_C 0x04
1012 #define DDC_PIN_D 0x06
1014 struct ddi_vbt_port_info {
1018 * This is an index in the HDMI/DVI DDI buffer translation table.
1019 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1020 * populate this field.
1022 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1023 uint8_t hdmi_level_shift;
1025 uint8_t supports_dvi:1;
1026 uint8_t supports_hdmi:1;
1027 uint8_t supports_dp:1;
1028 uint8_t supports_edp:1;
1030 uint8_t alternate_aux_channel;
1031 uint8_t alternate_ddc_pin;
1033 uint8_t dp_boost_level;
1034 uint8_t hdmi_boost_level;
1035 int dp_max_link_rate; /* 0 for not limited by VBT */
1038 enum psr_lines_to_wait {
1039 PSR_0_LINES_TO_WAIT = 0,
1041 PSR_4_LINES_TO_WAIT,
1045 struct intel_vbt_data {
1046 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1047 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1050 unsigned int int_tv_support:1;
1051 unsigned int lvds_dither:1;
1052 unsigned int lvds_vbt:1;
1053 unsigned int int_crt_support:1;
1054 unsigned int lvds_use_ssc:1;
1055 unsigned int display_clock_mode:1;
1056 unsigned int fdi_rx_polarity_inverted:1;
1057 unsigned int panel_type:4;
1059 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1061 enum drrs_support_type drrs_type;
1072 struct edp_power_seq pps;
1077 bool require_aux_wakeup;
1079 enum psr_lines_to_wait lines_to_wait;
1080 int tp1_wakeup_time;
1081 int tp2_tp3_wakeup_time;
1087 bool active_low_pwm;
1088 u8 min_brightness; /* min_brightness/255 of max */
1089 u8 controller; /* brightness controller number */
1090 enum intel_backlight_type type;
1096 struct mipi_config *config;
1097 struct mipi_pps_data *pps;
1103 const u8 *sequence[MIPI_SEQ_MAX];
1104 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1110 struct child_device_config *child_dev;
1112 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1113 struct sdvo_device_mapping sdvo_mappings[2];
1116 enum intel_ddb_partitioning {
1118 INTEL_DDB_PART_5_6, /* IVB+ */
1121 struct intel_wm_level {
1129 struct ilk_wm_values {
1130 uint32_t wm_pipe[3];
1132 uint32_t wm_lp_spr[3];
1133 uint32_t wm_linetime[3];
1135 enum intel_ddb_partitioning partitioning;
1138 struct g4x_pipe_wm {
1139 uint16_t plane[I915_MAX_PLANES];
1149 struct vlv_wm_ddl_values {
1150 uint8_t plane[I915_MAX_PLANES];
1153 struct vlv_wm_values {
1154 struct g4x_pipe_wm pipe[3];
1155 struct g4x_sr_wm sr;
1156 struct vlv_wm_ddl_values ddl[3];
1161 struct g4x_wm_values {
1162 struct g4x_pipe_wm pipe[2];
1163 struct g4x_sr_wm sr;
1164 struct g4x_sr_wm hpll;
1170 struct skl_ddb_entry {
1171 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1174 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1176 return entry->end - entry->start;
1179 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1180 const struct skl_ddb_entry *e2)
1182 if (e1->start == e2->start && e1->end == e2->end)
1188 struct skl_ddb_allocation {
1190 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1191 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1192 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1195 struct skl_ddb_values {
1196 unsigned dirty_pipes;
1197 struct skl_ddb_allocation ddb;
1200 struct skl_wm_level {
1202 uint16_t plane_res_b;
1203 uint8_t plane_res_l;
1206 /* Stores plane specific WM parameters */
1207 struct skl_wm_params {
1208 bool x_tiled, y_tiled;
1213 uint32_t plane_pixel_rate;
1214 uint32_t y_min_scanlines;
1215 uint32_t plane_bytes_per_line;
1216 uint_fixed_16_16_t plane_blocks_per_line;
1217 uint_fixed_16_16_t y_tile_minimum;
1218 uint32_t linetime_us;
1219 uint32_t dbuf_block_size;
1223 * This struct helps tracking the state needed for runtime PM, which puts the
1224 * device in PCI D3 state. Notice that when this happens, nothing on the
1225 * graphics device works, even register access, so we don't get interrupts nor
1228 * Every piece of our code that needs to actually touch the hardware needs to
1229 * either call intel_runtime_pm_get or call intel_display_power_get with the
1230 * appropriate power domain.
1232 * Our driver uses the autosuspend delay feature, which means we'll only really
1233 * suspend if we stay with zero refcount for a certain amount of time. The
1234 * default value is currently very conservative (see intel_runtime_pm_enable), but
1235 * it can be changed with the standard runtime PM files from sysfs.
1237 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1238 * goes back to false exactly before we reenable the IRQs. We use this variable
1239 * to check if someone is trying to enable/disable IRQs while they're supposed
1240 * to be disabled. This shouldn't happen and we'll print some error messages in
1243 * For more, read the Documentation/power/runtime_pm.txt.
1245 struct i915_runtime_pm {
1246 atomic_t wakeref_count;
1251 enum intel_pipe_crc_source {
1252 INTEL_PIPE_CRC_SOURCE_NONE,
1253 INTEL_PIPE_CRC_SOURCE_PLANE1,
1254 INTEL_PIPE_CRC_SOURCE_PLANE2,
1255 INTEL_PIPE_CRC_SOURCE_PF,
1256 INTEL_PIPE_CRC_SOURCE_PIPE,
1257 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1258 INTEL_PIPE_CRC_SOURCE_TV,
1259 INTEL_PIPE_CRC_SOURCE_DP_B,
1260 INTEL_PIPE_CRC_SOURCE_DP_C,
1261 INTEL_PIPE_CRC_SOURCE_DP_D,
1262 INTEL_PIPE_CRC_SOURCE_AUTO,
1263 INTEL_PIPE_CRC_SOURCE_MAX,
1266 struct intel_pipe_crc_entry {
1271 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1272 struct intel_pipe_crc {
1274 bool opened; /* exclusive access to the result file */
1275 struct intel_pipe_crc_entry *entries;
1276 enum intel_pipe_crc_source source;
1278 wait_queue_head_t wq;
1282 struct i915_frontbuffer_tracking {
1286 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1293 struct i915_wa_reg {
1296 /* bitmask representing WA bits */
1300 #define I915_MAX_WA_REGS 16
1302 struct i915_workarounds {
1303 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1307 struct i915_virtual_gpu {
1312 /* used in computing the new watermarks state */
1313 struct intel_wm_config {
1314 unsigned int num_pipes_active;
1315 bool sprites_enabled;
1316 bool sprites_scaled;
1319 struct i915_oa_format {
1324 struct i915_oa_reg {
1329 struct i915_oa_config {
1330 char uuid[UUID_STRING_LEN + 1];
1333 const struct i915_oa_reg *mux_regs;
1335 const struct i915_oa_reg *b_counter_regs;
1336 u32 b_counter_regs_len;
1337 const struct i915_oa_reg *flex_regs;
1340 struct attribute_group sysfs_metric;
1341 struct attribute *attrs[2];
1342 struct device_attribute sysfs_metric_id;
1347 struct i915_perf_stream;
1350 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1352 struct i915_perf_stream_ops {
1354 * @enable: Enables the collection of HW samples, either in response to
1355 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1356 * without `I915_PERF_FLAG_DISABLED`.
1358 void (*enable)(struct i915_perf_stream *stream);
1361 * @disable: Disables the collection of HW samples, either in response
1362 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1365 void (*disable)(struct i915_perf_stream *stream);
1368 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1369 * once there is something ready to read() for the stream
1371 void (*poll_wait)(struct i915_perf_stream *stream,
1376 * @wait_unlocked: For handling a blocking read, wait until there is
1377 * something to ready to read() for the stream. E.g. wait on the same
1378 * wait queue that would be passed to poll_wait().
1380 int (*wait_unlocked)(struct i915_perf_stream *stream);
1383 * @read: Copy buffered metrics as records to userspace
1384 * **buf**: the userspace, destination buffer
1385 * **count**: the number of bytes to copy, requested by userspace
1386 * **offset**: zero at the start of the read, updated as the read
1387 * proceeds, it represents how many bytes have been copied so far and
1388 * the buffer offset for copying the next record.
1390 * Copy as many buffered i915 perf samples and records for this stream
1391 * to userspace as will fit in the given buffer.
1393 * Only write complete records; returning -%ENOSPC if there isn't room
1394 * for a complete record.
1396 * Return any error condition that results in a short read such as
1397 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1398 * returning to userspace.
1400 int (*read)(struct i915_perf_stream *stream,
1406 * @destroy: Cleanup any stream specific resources.
1408 * The stream will always be disabled before this is called.
1410 void (*destroy)(struct i915_perf_stream *stream);
1414 * struct i915_perf_stream - state for a single open stream FD
1416 struct i915_perf_stream {
1418 * @dev_priv: i915 drm device
1420 struct drm_i915_private *dev_priv;
1423 * @link: Links the stream into ``&drm_i915_private->streams``
1425 struct list_head link;
1428 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1429 * properties given when opening a stream, representing the contents
1430 * of a single sample as read() by userspace.
1435 * @sample_size: Considering the configured contents of a sample
1436 * combined with the required header size, this is the total size
1437 * of a single sample record.
1442 * @ctx: %NULL if measuring system-wide across all contexts or a
1443 * specific context that is being monitored.
1445 struct i915_gem_context *ctx;
1448 * @enabled: Whether the stream is currently enabled, considering
1449 * whether the stream was opened in a disabled state and based
1450 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1455 * @ops: The callbacks providing the implementation of this specific
1456 * type of configured stream.
1458 const struct i915_perf_stream_ops *ops;
1461 * @oa_config: The OA configuration used by the stream.
1463 struct i915_oa_config *oa_config;
1467 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1469 struct i915_oa_ops {
1471 * @is_valid_b_counter_reg: Validates register's address for
1472 * programming boolean counters for a particular platform.
1474 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1478 * @is_valid_mux_reg: Validates register's address for programming mux
1479 * for a particular platform.
1481 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1484 * @is_valid_flex_reg: Validates register's address for programming
1485 * flex EU filtering for a particular platform.
1487 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1490 * @init_oa_buffer: Resets the head and tail pointers of the
1491 * circular buffer for periodic OA reports.
1493 * Called when first opening a stream for OA metrics, but also may be
1494 * called in response to an OA buffer overflow or other error
1497 * Note it may be necessary to clear the full OA buffer here as part of
1498 * maintaining the invariable that new reports must be written to
1499 * zeroed memory for us to be able to reliable detect if an expected
1500 * report has not yet landed in memory. (At least on Haswell the OA
1501 * buffer tail pointer is not synchronized with reports being visible
1504 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1507 * @enable_metric_set: Selects and applies any MUX configuration to set
1508 * up the Boolean and Custom (B/C) counters that are part of the
1509 * counter reports being sampled. May apply system constraints such as
1510 * disabling EU clock gating as required.
1512 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1513 const struct i915_oa_config *oa_config);
1516 * @disable_metric_set: Remove system constraints associated with using
1519 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1522 * @oa_enable: Enable periodic sampling
1524 void (*oa_enable)(struct drm_i915_private *dev_priv);
1527 * @oa_disable: Disable periodic sampling
1529 void (*oa_disable)(struct drm_i915_private *dev_priv);
1532 * @read: Copy data from the circular OA buffer into a given userspace
1535 int (*read)(struct i915_perf_stream *stream,
1541 * @oa_hw_tail_read: read the OA tail pointer register
1543 * In particular this enables us to share all the fiddly code for
1544 * handling the OA unit tail pointer race that affects multiple
1547 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1550 struct intel_cdclk_state {
1551 unsigned int cdclk, vco, ref, bypass;
1555 struct drm_i915_private {
1556 struct drm_device drm;
1558 struct kmem_cache *objects;
1559 struct kmem_cache *vmas;
1560 struct kmem_cache *luts;
1561 struct kmem_cache *requests;
1562 struct kmem_cache *dependencies;
1563 struct kmem_cache *priorities;
1565 const struct intel_device_info info;
1566 struct intel_driver_caps caps;
1569 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1570 * end of stolen which we can optionally use to create GEM objects
1571 * backed by stolen memory. Note that stolen_usable_size tells us
1572 * exactly how much of this we are actually allowed to use, given that
1573 * some portion of it is in fact reserved for use by hardware functions.
1575 struct resource dsm;
1577 * Reseved portion of Data Stolen Memory
1579 struct resource dsm_reserved;
1582 * Stolen memory is segmented in hardware with different portions
1583 * offlimits to certain functions.
1585 * The drm_mm is initialised to the total accessible range, as found
1586 * from the PCI config. On Broadwell+, this is further restricted to
1587 * avoid the first page! The upper end of stolen memory is reserved for
1588 * hardware functions and similarly removed from the accessible range.
1590 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1594 struct intel_uncore uncore;
1596 struct i915_virtual_gpu vgpu;
1598 struct intel_gvt *gvt;
1600 struct intel_wopcm wopcm;
1602 struct intel_huc huc;
1603 struct intel_guc guc;
1605 struct intel_csr csr;
1607 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1609 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1610 * controller on different i2c buses. */
1611 struct mutex gmbus_mutex;
1614 * Base address of the gmbus and gpio block.
1616 uint32_t gpio_mmio_base;
1618 /* MMIO base address for MIPI regs */
1619 uint32_t mipi_mmio_base;
1621 uint32_t psr_mmio_base;
1623 uint32_t pps_mmio_base;
1625 wait_queue_head_t gmbus_wait_queue;
1627 struct pci_dev *bridge_dev;
1628 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1629 /* Context used internally to idle the GPU and setup initial state */
1630 struct i915_gem_context *kernel_context;
1631 /* Context only to be used for injecting preemption commands */
1632 struct i915_gem_context *preempt_context;
1633 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1634 [MAX_ENGINE_INSTANCE + 1];
1636 struct drm_dma_handle *status_page_dmah;
1637 struct resource mch_res;
1639 /* protects the irq masks */
1640 spinlock_t irq_lock;
1642 bool display_irqs_enabled;
1644 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1645 struct pm_qos_request pm_qos;
1647 /* Sideband mailbox protection */
1648 struct mutex sb_lock;
1650 /** Cached value of IMR to avoid reads in updating the bitfield */
1653 u32 de_irq_mask[I915_MAX_PIPES];
1660 u32 pipestat_irq_mask[I915_MAX_PIPES];
1662 struct i915_hotplug hotplug;
1663 struct intel_fbc fbc;
1664 struct i915_drrs drrs;
1665 struct intel_opregion opregion;
1666 struct intel_vbt_data vbt;
1668 bool preserve_bios_swizzle;
1671 struct intel_overlay *overlay;
1673 /* backlight registers and fields in struct intel_panel */
1674 struct mutex backlight_lock;
1677 bool no_aux_handshake;
1679 /* protects panel power sequencer state */
1680 struct mutex pps_mutex;
1682 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1683 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1685 unsigned int fsb_freq, mem_freq, is_ddr3;
1686 unsigned int skl_preferred_vco_freq;
1687 unsigned int max_cdclk_freq;
1689 unsigned int max_dotclk_freq;
1690 unsigned int rawclk_freq;
1691 unsigned int hpll_freq;
1692 unsigned int fdi_pll_freq;
1693 unsigned int czclk_freq;
1697 * The current logical cdclk state.
1698 * See intel_atomic_state.cdclk.logical
1700 * For reading holding any crtc lock is sufficient,
1701 * for writing must hold all of them.
1703 struct intel_cdclk_state logical;
1705 * The current actual cdclk state.
1706 * See intel_atomic_state.cdclk.actual
1708 struct intel_cdclk_state actual;
1709 /* The current hardware cdclk state */
1710 struct intel_cdclk_state hw;
1714 * wq - Driver workqueue for GEM.
1716 * NOTE: Work items scheduled here are not allowed to grab any modeset
1717 * locks, for otherwise the flushing done in the pageflip code will
1718 * result in deadlocks.
1720 struct workqueue_struct *wq;
1722 /* ordered wq for modesets */
1723 struct workqueue_struct *modeset_wq;
1725 /* Display functions */
1726 struct drm_i915_display_funcs display;
1728 /* PCH chipset type */
1729 enum intel_pch pch_type;
1730 unsigned short pch_id;
1732 unsigned long quirks;
1734 enum modeset_restore modeset_restore;
1735 struct mutex modeset_restore_lock;
1736 struct drm_atomic_state *modeset_restore_state;
1737 struct drm_modeset_acquire_ctx reset_ctx;
1739 struct list_head vm_list; /* Global list of all address spaces */
1740 struct i915_ggtt ggtt; /* VM representing the global address space */
1742 struct i915_gem_mm mm;
1743 DECLARE_HASHTABLE(mm_structs, 7);
1744 struct mutex mm_lock;
1746 struct intel_ppat ppat;
1748 /* Kernel Modesetting */
1750 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1751 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1753 #ifdef CONFIG_DEBUG_FS
1754 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1757 /* dpll and cdclk state is protected by connection_mutex */
1758 int num_shared_dpll;
1759 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1760 const struct intel_dpll_mgr *dpll_mgr;
1763 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1764 * Must be global rather than per dpll, because on some platforms
1765 * plls share registers.
1767 struct mutex dpll_lock;
1769 unsigned int active_crtcs;
1770 /* minimum acceptable cdclk for each pipe */
1771 int min_cdclk[I915_MAX_PIPES];
1772 /* minimum acceptable voltage level for each pipe */
1773 u8 min_voltage_level[I915_MAX_PIPES];
1775 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1777 struct i915_workarounds workarounds;
1779 struct i915_frontbuffer_tracking fb_tracking;
1781 struct intel_atomic_helper {
1782 struct llist_head free_list;
1783 struct work_struct free_work;
1788 bool mchbar_need_disable;
1790 struct intel_l3_parity l3_parity;
1792 /* Cannot be determined by PCIID. You must always read a register. */
1796 * Protects RPS/RC6 register access and PCU communication.
1797 * Must be taken after struct_mutex if nested. Note that
1798 * this lock may be held for long periods of time when
1799 * talking to hw - so only take it when talking to hw!
1801 struct mutex pcu_lock;
1803 /* gen6+ GT PM state */
1804 struct intel_gen6_power_mgmt gt_pm;
1806 /* ilk-only ips/rps state. Everything in here is protected by the global
1807 * mchdev_lock in intel_pm.c */
1808 struct intel_ilk_power_mgmt ips;
1810 struct i915_power_domains power_domains;
1812 struct i915_psr psr;
1814 struct i915_gpu_error gpu_error;
1816 struct drm_i915_gem_object *vlv_pctx;
1818 /* list of fbdev register on this device */
1819 struct intel_fbdev *fbdev;
1820 struct work_struct fbdev_suspend_work;
1822 struct drm_property *broadcast_rgb_property;
1823 struct drm_property *force_audio_property;
1825 /* hda/i915 audio component */
1826 struct i915_audio_component *audio_component;
1827 bool audio_component_registered;
1829 * av_mutex - mutex for audio/video sync
1832 struct mutex av_mutex;
1835 struct list_head list;
1836 struct llist_head free_list;
1837 struct work_struct free_work;
1839 /* The hw wants to have a stable context identifier for the
1840 * lifetime of the context (for OA, PASID, faults, etc).
1841 * This is limited in execlists to 21 bits.
1844 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1845 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1850 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1851 u32 chv_phy_control;
1853 * Shadows for CHV DPLL_MD regs to keep the state
1854 * checker somewhat working in the presence hardware
1855 * crappiness (can't read out DPLL_MD for pipes B & C).
1857 u32 chv_dpll_md[I915_MAX_PIPES];
1861 bool power_domains_suspended;
1862 struct i915_suspend_saved_registers regfile;
1863 struct vlv_s0ix_state vlv_s0ix_state;
1866 I915_SAGV_UNKNOWN = 0,
1869 I915_SAGV_NOT_CONTROLLED
1874 * Raw watermark latency values:
1875 * in 0.1us units for WM0,
1876 * in 0.5us units for WM1+.
1879 uint16_t pri_latency[5];
1881 uint16_t spr_latency[5];
1883 uint16_t cur_latency[5];
1885 * Raw watermark memory latency values
1886 * for SKL for all 8 levels
1889 uint16_t skl_latency[8];
1891 /* current hardware state */
1893 struct ilk_wm_values hw;
1894 struct skl_ddb_values skl_hw;
1895 struct vlv_wm_values vlv;
1896 struct g4x_wm_values g4x;
1902 * Should be held around atomic WM register writing; also
1903 * protects * intel_crtc->wm.active and
1904 * cstate->wm.need_postvbl_update.
1906 struct mutex wm_mutex;
1909 * Set during HW readout of watermarks/DDB. Some platforms
1910 * need to know when we're still using BIOS-provided values
1911 * (which we don't fully trust).
1913 bool distrust_bios_wm;
1916 struct i915_runtime_pm runtime_pm;
1921 struct kobject *metrics_kobj;
1922 struct ctl_table_header *sysctl_header;
1925 * Lock associated with adding/modifying/removing OA configs
1926 * in dev_priv->perf.metrics_idr.
1928 struct mutex metrics_lock;
1931 * List of dynamic configurations, you need to hold
1932 * dev_priv->perf.metrics_lock to access it.
1934 struct idr metrics_idr;
1937 * Lock associated with anything below within this structure
1938 * except exclusive_stream.
1941 struct list_head streams;
1945 * The stream currently using the OA unit. If accessed
1946 * outside a syscall associated to its file
1947 * descriptor, you need to hold
1948 * dev_priv->drm.struct_mutex.
1950 struct i915_perf_stream *exclusive_stream;
1952 u32 specific_ctx_id;
1954 struct hrtimer poll_check_timer;
1955 wait_queue_head_t poll_wq;
1959 * For rate limiting any notifications of spurious
1960 * invalid OA reports
1962 struct ratelimit_state spurious_report_rs;
1965 int period_exponent;
1967 struct i915_oa_config test_config;
1970 struct i915_vma *vma;
1977 * Locks reads and writes to all head/tail state
1979 * Consider: the head and tail pointer state
1980 * needs to be read consistently from a hrtimer
1981 * callback (atomic context) and read() fop
1982 * (user context) with tail pointer updates
1983 * happening in atomic context and head updates
1984 * in user context and the (unlikely)
1985 * possibility of read() errors needing to
1986 * reset all head/tail state.
1988 * Note: Contention or performance aren't
1989 * currently a significant concern here
1990 * considering the relatively low frequency of
1991 * hrtimer callbacks (5ms period) and that
1992 * reads typically only happen in response to a
1993 * hrtimer event and likely complete before the
1996 * Note: This lock is not held *while* reading
1997 * and copying data to userspace so the value
1998 * of head observed in htrimer callbacks won't
1999 * represent any partial consumption of data.
2001 spinlock_t ptr_lock;
2004 * One 'aging' tail pointer and one 'aged'
2005 * tail pointer ready to used for reading.
2007 * Initial values of 0xffffffff are invalid
2008 * and imply that an update is required
2009 * (and should be ignored by an attempted
2017 * Index for the aged tail ready to read()
2020 unsigned int aged_tail_idx;
2023 * A monotonic timestamp for when the current
2024 * aging tail pointer was read; used to
2025 * determine when it is old enough to trust.
2027 u64 aging_timestamp;
2030 * Although we can always read back the head
2031 * pointer register, we prefer to avoid
2032 * trusting the HW state, just to avoid any
2033 * risk that some hardware condition could
2034 * somehow bump the head pointer unpredictably
2035 * and cause us to forward the wrong OA buffer
2036 * data to userspace.
2041 u32 gen7_latched_oastatus1;
2042 u32 ctx_oactxctrl_offset;
2043 u32 ctx_flexeu0_offset;
2046 * The RPT_ID/reason field for Gen8+ includes a bit
2047 * to determine if the CTX ID in the report is valid
2048 * but the specific bit differs between Gen 8 and 9
2050 u32 gen8_valid_ctx_bit;
2052 struct i915_oa_ops ops;
2053 const struct i915_oa_format *oa_formats;
2057 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2059 void (*resume)(struct drm_i915_private *);
2060 void (*cleanup_engine)(struct intel_engine_cs *engine);
2062 struct i915_gem_timeline global_timeline;
2063 struct list_head timelines;
2065 struct list_head active_rings;
2066 u32 active_requests;
2070 * Is the GPU currently considered idle, or busy executing
2071 * userspace requests? Whilst idle, we allow runtime power
2072 * management to power down the hardware and display clocks.
2073 * In order to reduce the effect on performance, there
2074 * is a slight delay before we do so.
2079 * The number of times we have woken up.
2082 #define I915_EPOCH_INVALID 0
2085 * We leave the user IRQ off as much as possible,
2086 * but this means that requests will finish and never
2087 * be retired once the system goes idle. Set a timer to
2088 * fire periodically while the ring is running. When it
2089 * fires, go retire requests.
2091 struct delayed_work retire_work;
2094 * When we detect an idle GPU, we want to turn on
2095 * powersaving features. So once we see that there
2096 * are no more requests outstanding and no more
2097 * arrive within a small period of time, we fire
2098 * off the idle_work.
2100 struct delayed_work idle_work;
2102 ktime_t last_init_time;
2105 /* perform PHY state sanity checks? */
2106 bool chv_phy_assert[2];
2110 /* Used to save the pipe-to-encoder mapping for audio */
2111 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2113 /* necessary resource sharing with HDMI LPE audio driver. */
2115 struct platform_device *platdev;
2119 struct i915_pmu pmu;
2122 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2123 * will be rejected. Instead look for a better place.
2127 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2129 return container_of(dev, struct drm_i915_private, drm);
2132 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2134 return to_i915(dev_get_drvdata(kdev));
2137 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2139 return container_of(wopcm, struct drm_i915_private, wopcm);
2142 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2144 return container_of(guc, struct drm_i915_private, guc);
2147 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2149 return container_of(huc, struct drm_i915_private, huc);
2152 /* Simple iterator over all initialised engines */
2153 #define for_each_engine(engine__, dev_priv__, id__) \
2155 (id__) < I915_NUM_ENGINES; \
2157 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2159 /* Iterator over subset of engines selected by mask */
2160 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2161 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2163 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2166 enum hdmi_force_audio {
2167 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2168 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2169 HDMI_AUDIO_AUTO, /* trust EDID */
2170 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2173 #define I915_GTT_OFFSET_NONE ((u32)-1)
2176 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2177 * considered to be the frontbuffer for the given plane interface-wise. This
2178 * doesn't mean that the hw necessarily already scans it out, but that any
2179 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2181 * We have one bit per pipe and per scanout plane type.
2183 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2184 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2185 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2186 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2187 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2189 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2190 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2191 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2192 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2193 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2196 * Optimised SGL iterator for GEM objects
2198 static __always_inline struct sgt_iter {
2199 struct scatterlist *sgp;
2206 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2207 struct sgt_iter s = { .sgp = sgl };
2210 s.max = s.curr = s.sgp->offset;
2211 s.max += s.sgp->length;
2213 s.dma = sg_dma_address(s.sgp);
2215 s.pfn = page_to_pfn(sg_page(s.sgp));
2221 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2224 if (unlikely(sg_is_chain(sg)))
2225 sg = sg_chain_ptr(sg);
2230 * __sg_next - return the next scatterlist entry in a list
2231 * @sg: The current sg entry
2234 * If the entry is the last, return NULL; otherwise, step to the next
2235 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2236 * otherwise just return the pointer to the current element.
2238 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2240 #ifdef CONFIG_DEBUG_SG
2241 BUG_ON(sg->sg_magic != SG_MAGIC);
2243 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2247 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2248 * @__dmap: DMA address (output)
2249 * @__iter: 'struct sgt_iter' (iterator state, internal)
2250 * @__sgt: sg_table to iterate over (input)
2252 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2253 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2254 ((__dmap) = (__iter).dma + (__iter).curr); \
2255 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2256 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2259 * for_each_sgt_page - iterate over the pages of the given sg_table
2260 * @__pp: page pointer (output)
2261 * @__iter: 'struct sgt_iter' (iterator state, internal)
2262 * @__sgt: sg_table to iterate over (input)
2264 #define for_each_sgt_page(__pp, __iter, __sgt) \
2265 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2266 ((__pp) = (__iter).pfn == 0 ? NULL : \
2267 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2268 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2269 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2271 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2273 unsigned int page_sizes;
2277 GEM_BUG_ON(sg->offset);
2278 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2279 page_sizes |= sg->length;
2286 static inline unsigned int i915_sg_segment_size(void)
2288 unsigned int size = swiotlb_max_segment();
2291 return SCATTERLIST_MAX_SEGMENT;
2293 size = rounddown(size, PAGE_SIZE);
2294 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2295 if (size < PAGE_SIZE)
2301 static inline const struct intel_device_info *
2302 intel_info(const struct drm_i915_private *dev_priv)
2304 return &dev_priv->info;
2307 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2309 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2310 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2312 #define REVID_FOREVER 0xff
2313 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2315 #define GEN_FOREVER (0)
2317 #define INTEL_GEN_MASK(s, e) ( \
2318 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2319 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2320 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2321 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2325 * Returns true if Gen is in inclusive range [Start, End].
2327 * Use GEN_FOREVER for unbound start and or end.
2329 #define IS_GEN(dev_priv, s, e) \
2330 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2333 * Return true if revision is in range [since,until] inclusive.
2335 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2337 #define IS_REVID(p, since, until) \
2338 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2340 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2342 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2343 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2344 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2345 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2346 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2347 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2348 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2349 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2350 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2351 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2352 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2353 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2354 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2355 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2356 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2357 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2358 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2359 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2360 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2361 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2362 (dev_priv)->info.gt == 1)
2363 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2364 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2365 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2366 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2367 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2368 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2369 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2370 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2371 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2372 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2373 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2374 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2375 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2376 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2377 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2378 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2379 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2380 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2381 /* ULX machines are also considered ULT. */
2382 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2383 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2384 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2385 (dev_priv)->info.gt == 3)
2386 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2387 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2388 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2389 (dev_priv)->info.gt == 3)
2390 /* ULX machines are also considered ULT. */
2391 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2392 INTEL_DEVID(dev_priv) == 0x0A1E)
2393 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2394 INTEL_DEVID(dev_priv) == 0x1913 || \
2395 INTEL_DEVID(dev_priv) == 0x1916 || \
2396 INTEL_DEVID(dev_priv) == 0x1921 || \
2397 INTEL_DEVID(dev_priv) == 0x1926)
2398 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2399 INTEL_DEVID(dev_priv) == 0x1915 || \
2400 INTEL_DEVID(dev_priv) == 0x191E)
2401 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2402 INTEL_DEVID(dev_priv) == 0x5913 || \
2403 INTEL_DEVID(dev_priv) == 0x5916 || \
2404 INTEL_DEVID(dev_priv) == 0x5921 || \
2405 INTEL_DEVID(dev_priv) == 0x5926)
2406 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2407 INTEL_DEVID(dev_priv) == 0x5915 || \
2408 INTEL_DEVID(dev_priv) == 0x591E)
2409 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2410 (dev_priv)->info.gt == 2)
2411 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2412 (dev_priv)->info.gt == 3)
2413 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2414 (dev_priv)->info.gt == 4)
2415 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2416 (dev_priv)->info.gt == 2)
2417 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2418 (dev_priv)->info.gt == 3)
2419 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2420 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2421 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2422 (dev_priv)->info.gt == 2)
2423 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2424 (dev_priv)->info.gt == 3)
2425 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2426 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2428 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2430 #define SKL_REVID_A0 0x0
2431 #define SKL_REVID_B0 0x1
2432 #define SKL_REVID_C0 0x2
2433 #define SKL_REVID_D0 0x3
2434 #define SKL_REVID_E0 0x4
2435 #define SKL_REVID_F0 0x5
2436 #define SKL_REVID_G0 0x6
2437 #define SKL_REVID_H0 0x7
2439 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2441 #define BXT_REVID_A0 0x0
2442 #define BXT_REVID_A1 0x1
2443 #define BXT_REVID_B0 0x3
2444 #define BXT_REVID_B_LAST 0x8
2445 #define BXT_REVID_C0 0x9
2447 #define IS_BXT_REVID(dev_priv, since, until) \
2448 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2450 #define KBL_REVID_A0 0x0
2451 #define KBL_REVID_B0 0x1
2452 #define KBL_REVID_C0 0x2
2453 #define KBL_REVID_D0 0x3
2454 #define KBL_REVID_E0 0x4
2456 #define IS_KBL_REVID(dev_priv, since, until) \
2457 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2459 #define GLK_REVID_A0 0x0
2460 #define GLK_REVID_A1 0x1
2462 #define IS_GLK_REVID(dev_priv, since, until) \
2463 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2465 #define CNL_REVID_A0 0x0
2466 #define CNL_REVID_B0 0x1
2467 #define CNL_REVID_C0 0x2
2469 #define IS_CNL_REVID(p, since, until) \
2470 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2473 * The genX designation typically refers to the render engine, so render
2474 * capability related checks should use IS_GEN, while display and other checks
2475 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2478 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2479 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2480 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2481 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2482 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2483 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2484 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2485 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2486 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2487 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2489 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2490 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2491 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2493 #define ENGINE_MASK(id) BIT(id)
2494 #define RENDER_RING ENGINE_MASK(RCS)
2495 #define BSD_RING ENGINE_MASK(VCS)
2496 #define BLT_RING ENGINE_MASK(BCS)
2497 #define VEBOX_RING ENGINE_MASK(VECS)
2498 #define BSD2_RING ENGINE_MASK(VCS2)
2499 #define BSD3_RING ENGINE_MASK(VCS3)
2500 #define BSD4_RING ENGINE_MASK(VCS4)
2501 #define VEBOX2_RING ENGINE_MASK(VECS2)
2502 #define ALL_ENGINES (~0)
2504 #define HAS_ENGINE(dev_priv, id) \
2505 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2507 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2508 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2509 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2510 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2512 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2514 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2515 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2516 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2517 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2518 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2520 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2522 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2523 ((dev_priv)->info.has_logical_ring_contexts)
2524 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2525 ((dev_priv)->info.has_logical_ring_elsq)
2526 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2527 ((dev_priv)->info.has_logical_ring_preemption)
2529 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2531 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2532 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2533 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2534 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2535 GEM_BUG_ON((sizes) == 0); \
2536 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2539 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2540 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2541 ((dev_priv)->info.overlay_needs_physical)
2543 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2544 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2546 /* WaRsDisableCoarsePowerGating:skl,cnl */
2547 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2548 (IS_CANNONLAKE(dev_priv) || \
2549 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2552 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2553 * even when in MSI mode. This results in spurious interrupt warnings if the
2554 * legacy irq no. is shared with another device. The kernel then disables that
2555 * interrupt source and so prevents the other device from working properly.
2557 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
2560 #define HAS_AUX_IRQ(dev_priv) true
2561 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2563 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2564 * rows, which changed the alignment requirements and fence programming.
2566 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2567 !(IS_I915G(dev_priv) || \
2568 IS_I915GM(dev_priv)))
2569 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2570 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2572 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2573 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2574 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2576 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2578 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2580 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2581 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2582 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2584 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2585 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2586 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2588 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2590 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2591 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2593 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2596 * For now, anything with a GuC requires uCode loading, and then supports
2597 * command submission once loaded. But these are logically independent
2598 * properties, so we have separate macros to test them.
2600 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2601 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2602 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2603 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2605 /* For now, anything with a GuC has also HuC */
2606 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2607 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2609 /* Having a GuC is not the same as using a GuC */
2610 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2611 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2612 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2614 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2616 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2618 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2619 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2620 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2621 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2622 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2623 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2624 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2625 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2626 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2627 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2628 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2629 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2630 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2631 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2632 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2633 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2634 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2636 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2637 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2638 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2639 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2640 #define HAS_PCH_CNP_LP(dev_priv) \
2641 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2642 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2643 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2644 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2645 #define HAS_PCH_LPT_LP(dev_priv) \
2646 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2647 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2648 #define HAS_PCH_LPT_H(dev_priv) \
2649 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2650 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2651 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2652 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2653 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2654 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2656 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2658 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2660 /* DPF == dynamic parity feature */
2661 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2662 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2663 2 : HAS_L3_DPF(dev_priv))
2665 #define GT_FREQUENCY_MULTIPLIER 50
2666 #define GEN9_FREQ_SCALER 3
2668 #include "i915_trace.h"
2670 static inline bool intel_vtd_active(void)
2672 #ifdef CONFIG_INTEL_IOMMU
2673 if (intel_iommu_gfx_mapped)
2679 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2681 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2685 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2687 return IS_BROXTON(dev_priv) && intel_vtd_active();
2690 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2695 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2696 const char *fmt, ...);
2698 #define i915_report_error(dev_priv, fmt, ...) \
2699 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2701 #ifdef CONFIG_COMPAT
2702 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2705 #define i915_compat_ioctl NULL
2707 extern const struct dev_pm_ops i915_pm_ops;
2709 extern int i915_driver_load(struct pci_dev *pdev,
2710 const struct pci_device_id *ent);
2711 extern void i915_driver_unload(struct drm_device *dev);
2712 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2713 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2715 extern void i915_reset(struct drm_i915_private *i915,
2716 unsigned int stalled_mask,
2717 const char *reason);
2718 extern int i915_reset_engine(struct intel_engine_cs *engine,
2719 const char *reason);
2721 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2722 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2723 extern int intel_guc_reset_engine(struct intel_guc *guc,
2724 struct intel_engine_cs *engine);
2725 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2726 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2727 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2728 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2729 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2730 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2731 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2733 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2734 int intel_engines_init(struct drm_i915_private *dev_priv);
2736 /* intel_hotplug.c */
2737 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2738 u32 pin_mask, u32 long_mask);
2739 void intel_hpd_init(struct drm_i915_private *dev_priv);
2740 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2741 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2742 enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
2744 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2746 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2747 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2750 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2752 unsigned long delay;
2754 if (unlikely(!i915_modparams.enable_hangcheck))
2757 /* Don't continually defer the hangcheck so that it is always run at
2758 * least once after work has been scheduled on any ring. Otherwise,
2759 * we will ignore a hung ring if a second ring is kept busy.
2762 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2763 queue_delayed_work(system_long_wq,
2764 &dev_priv->gpu_error.hangcheck_work, delay);
2768 void i915_handle_error(struct drm_i915_private *dev_priv,
2770 unsigned long flags,
2771 const char *fmt, ...);
2772 #define I915_ERROR_CAPTURE BIT(0)
2774 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2775 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2776 int intel_irq_install(struct drm_i915_private *dev_priv);
2777 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2779 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2781 return dev_priv->gvt;
2784 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2786 return dev_priv->vgpu.active;
2789 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2792 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2796 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2799 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2800 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2801 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2804 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2805 uint32_t interrupt_mask,
2806 uint32_t enabled_irq_mask);
2808 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2810 ilk_update_display_irq(dev_priv, bits, bits);
2813 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2815 ilk_update_display_irq(dev_priv, bits, 0);
2817 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2819 uint32_t interrupt_mask,
2820 uint32_t enabled_irq_mask);
2821 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2822 enum pipe pipe, uint32_t bits)
2824 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2826 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2827 enum pipe pipe, uint32_t bits)
2829 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2831 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2832 uint32_t interrupt_mask,
2833 uint32_t enabled_irq_mask);
2835 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2837 ibx_display_interrupt_update(dev_priv, bits, bits);
2840 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2842 ibx_display_interrupt_update(dev_priv, bits, 0);
2846 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2847 struct drm_file *file_priv);
2848 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2849 struct drm_file *file_priv);
2850 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2851 struct drm_file *file_priv);
2852 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2853 struct drm_file *file_priv);
2854 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2855 struct drm_file *file_priv);
2856 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2857 struct drm_file *file_priv);
2858 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2859 struct drm_file *file_priv);
2860 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2861 struct drm_file *file_priv);
2862 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2863 struct drm_file *file_priv);
2864 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2865 struct drm_file *file_priv);
2866 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2867 struct drm_file *file);
2868 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2869 struct drm_file *file);
2870 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2871 struct drm_file *file_priv);
2872 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2873 struct drm_file *file_priv);
2874 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2875 struct drm_file *file_priv);
2876 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2877 struct drm_file *file_priv);
2878 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2879 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2880 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2881 struct drm_file *file);
2882 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2883 struct drm_file *file_priv);
2884 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2885 struct drm_file *file_priv);
2886 void i915_gem_sanitize(struct drm_i915_private *i915);
2887 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2888 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2889 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2890 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2891 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2893 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2894 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2895 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2896 const struct drm_i915_gem_object_ops *ops);
2897 struct drm_i915_gem_object *
2898 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2899 struct drm_i915_gem_object *
2900 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2901 const void *data, size_t size);
2902 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2903 void i915_gem_free_object(struct drm_gem_object *obj);
2905 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2907 if (!atomic_read(&i915->mm.free_count))
2910 /* A single pass should suffice to release all the freed objects (along
2911 * most call paths) , but be a little more paranoid in that freeing
2912 * the objects does take a little amount of time, during which the rcu
2913 * callbacks could have added new objects into the freed list, and
2914 * armed the work again.
2918 } while (flush_work(&i915->mm.free_work));
2921 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2924 * Similar to objects above (see i915_gem_drain_freed-objects), in
2925 * general we have workers that are armed by RCU and then rearm
2926 * themselves in their callbacks. To be paranoid, we need to
2927 * drain the workqueue a second time after waiting for the RCU
2928 * grace period so that we catch work queued via RCU from the first
2929 * pass. As neither drain_workqueue() nor flush_workqueue() report
2930 * a result, we make an assumption that we only don't require more
2931 * than 2 passes to catch all recursive RCU delayed work.
2937 drain_workqueue(i915->wq);
2941 struct i915_vma * __must_check
2942 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2943 const struct i915_ggtt_view *view,
2948 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2949 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2951 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2953 static inline int __sg_page_count(const struct scatterlist *sg)
2955 return sg->length >> PAGE_SHIFT;
2958 struct scatterlist *
2959 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2960 unsigned int n, unsigned int *offset);
2963 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2967 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2971 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2974 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2975 struct sg_table *pages,
2976 unsigned int sg_page_sizes);
2977 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2979 static inline int __must_check
2980 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2982 might_lock(&obj->mm.lock);
2984 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2987 return __i915_gem_object_get_pages(obj);
2991 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2993 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2997 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2999 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3001 atomic_inc(&obj->mm.pages_pin_count);
3005 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3007 return atomic_read(&obj->mm.pages_pin_count);
3011 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3013 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3014 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3016 atomic_dec(&obj->mm.pages_pin_count);
3020 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3022 __i915_gem_object_unpin_pages(obj);
3025 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3030 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3031 enum i915_mm_subclass subclass);
3032 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3034 enum i915_map_type {
3037 #define I915_MAP_OVERRIDE BIT(31)
3038 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3039 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3043 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3044 * @obj: the object to map into kernel address space
3045 * @type: the type of mapping, used to select pgprot_t
3047 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3048 * pages and then returns a contiguous mapping of the backing storage into
3049 * the kernel address space. Based on the @type of mapping, the PTE will be
3050 * set to either WriteBack or WriteCombine (via pgprot_t).
3052 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3053 * mapping is no longer required.
3055 * Returns the pointer through which to access the mapped object, or an
3056 * ERR_PTR() on error.
3058 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3059 enum i915_map_type type);
3062 * i915_gem_object_unpin_map - releases an earlier mapping
3063 * @obj: the object to unmap
3065 * After pinning the object and mapping its pages, once you are finished
3066 * with your access, call i915_gem_object_unpin_map() to release the pin
3067 * upon the mapping. Once the pin count reaches zero, that mapping may be
3070 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3072 i915_gem_object_unpin_pages(obj);
3075 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3076 unsigned int *needs_clflush);
3077 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3078 unsigned int *needs_clflush);
3079 #define CLFLUSH_BEFORE BIT(0)
3080 #define CLFLUSH_AFTER BIT(1)
3081 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3084 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3086 i915_gem_object_unpin_pages(obj);
3089 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3090 void i915_vma_move_to_active(struct i915_vma *vma,
3091 struct i915_request *rq,
3092 unsigned int flags);
3093 int i915_gem_dumb_create(struct drm_file *file_priv,
3094 struct drm_device *dev,
3095 struct drm_mode_create_dumb *args);
3096 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3097 uint32_t handle, uint64_t *offset);
3098 int i915_gem_mmap_gtt_version(void);
3100 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3101 struct drm_i915_gem_object *new,
3102 unsigned frontbuffer_bits);
3104 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3106 struct i915_request *
3107 i915_gem_find_active_request(struct intel_engine_cs *engine);
3109 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3111 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3114 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3116 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3119 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3121 return unlikely(test_bit(I915_WEDGED, &error->flags));
3124 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3126 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3129 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3131 return READ_ONCE(error->reset_count);
3134 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3135 struct intel_engine_cs *engine)
3137 return READ_ONCE(error->reset_engine_count[engine->id]);
3140 struct i915_request *
3141 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3142 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3143 void i915_gem_reset(struct drm_i915_private *dev_priv,
3144 unsigned int stalled_mask);
3145 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3146 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3147 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3148 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3149 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3150 struct i915_request *request,
3153 void i915_gem_init_mmio(struct drm_i915_private *i915);
3154 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3155 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3156 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3157 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3158 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3159 unsigned int flags);
3160 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3161 void i915_gem_resume(struct drm_i915_private *dev_priv);
3162 int i915_gem_fault(struct vm_fault *vmf);
3163 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3166 struct intel_rps_client *rps);
3167 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3169 const struct i915_sched_attr *attr);
3170 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3173 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3175 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3177 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3178 struct i915_vma * __must_check
3179 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3181 const struct i915_ggtt_view *view,
3182 unsigned int flags);
3183 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3184 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3186 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3187 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3189 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3190 enum i915_cache_level cache_level);
3192 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3193 struct dma_buf *dma_buf);
3195 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3196 struct drm_gem_object *gem_obj, int flags);
3198 static inline struct i915_hw_ppgtt *
3199 i915_vm_to_ppgtt(struct i915_address_space *vm)
3201 return container_of(vm, struct i915_hw_ppgtt, base);
3204 /* i915_gem_fence_reg.c */
3205 struct drm_i915_fence_reg *
3206 i915_reserve_fence(struct drm_i915_private *dev_priv);
3207 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3209 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3210 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3212 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3213 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3214 struct sg_table *pages);
3215 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3216 struct sg_table *pages);
3218 static inline struct i915_gem_context *
3219 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3221 return idr_find(&file_priv->context_idr, id);
3224 static inline struct i915_gem_context *
3225 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3227 struct i915_gem_context *ctx;
3230 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3231 if (ctx && !kref_get_unless_zero(&ctx->ref))
3238 static inline struct intel_timeline *
3239 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3240 struct intel_engine_cs *engine)
3242 struct i915_address_space *vm;
3244 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3245 return &vm->timeline.engine[engine->id];
3248 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3249 struct drm_file *file);
3250 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3251 struct drm_file *file);
3252 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3253 struct drm_file *file);
3254 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3255 struct i915_gem_context *ctx,
3256 uint32_t *reg_state);
3258 /* i915_gem_evict.c */
3259 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3260 u64 min_size, u64 alignment,
3261 unsigned cache_level,
3264 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3265 struct drm_mm_node *node,
3266 unsigned int flags);
3267 int i915_gem_evict_vm(struct i915_address_space *vm);
3269 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3271 /* belongs in i915_gem_gtt.h */
3272 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3275 if (INTEL_GEN(dev_priv) < 6)
3276 intel_gtt_chipset_flush();
3279 /* i915_gem_stolen.c */
3280 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3281 struct drm_mm_node *node, u64 size,
3282 unsigned alignment);
3283 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3284 struct drm_mm_node *node, u64 size,
3285 unsigned alignment, u64 start,
3287 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3288 struct drm_mm_node *node);
3289 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3290 void i915_gem_cleanup_stolen(struct drm_device *dev);
3291 struct drm_i915_gem_object *
3292 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3293 resource_size_t size);
3294 struct drm_i915_gem_object *
3295 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3296 resource_size_t stolen_offset,
3297 resource_size_t gtt_offset,
3298 resource_size_t size);
3300 /* i915_gem_internal.c */
3301 struct drm_i915_gem_object *
3302 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3305 /* i915_gem_shrinker.c */
3306 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3307 unsigned long target,
3308 unsigned long *nr_scanned,
3310 #define I915_SHRINK_PURGEABLE 0x1
3311 #define I915_SHRINK_UNBOUND 0x2
3312 #define I915_SHRINK_BOUND 0x4
3313 #define I915_SHRINK_ACTIVE 0x8
3314 #define I915_SHRINK_VMAPS 0x10
3315 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3316 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3317 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3320 /* i915_gem_tiling.c */
3321 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3323 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3325 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3326 i915_gem_object_is_tiled(obj);
3329 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3330 unsigned int tiling, unsigned int stride);
3331 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3332 unsigned int tiling, unsigned int stride);
3334 /* i915_debugfs.c */
3335 #ifdef CONFIG_DEBUG_FS
3336 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3337 int i915_debugfs_connector_add(struct drm_connector *connector);
3338 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3340 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3341 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3343 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3346 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3348 /* i915_cmd_parser.c */
3349 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3350 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3351 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3352 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3353 struct drm_i915_gem_object *batch_obj,
3354 struct drm_i915_gem_object *shadow_batch_obj,
3355 u32 batch_start_offset,
3360 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3361 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3362 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3363 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3365 /* i915_suspend.c */
3366 extern int i915_save_state(struct drm_i915_private *dev_priv);
3367 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3370 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3371 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3373 /* intel_lpe_audio.c */
3374 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3375 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3376 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3377 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3378 enum pipe pipe, enum port port,
3379 const void *eld, int ls_clock, bool dp_output);
3382 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3383 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3384 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3386 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3388 extern struct i2c_adapter *
3389 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3390 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3391 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3392 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3394 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3396 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3399 void intel_bios_init(struct drm_i915_private *dev_priv);
3400 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3401 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3402 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3403 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3404 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3405 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3406 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3407 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3408 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3410 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3415 extern void intel_register_dsm_handler(void);
3416 extern void intel_unregister_dsm_handler(void);
3418 static inline void intel_register_dsm_handler(void) { return; }
3419 static inline void intel_unregister_dsm_handler(void) { return; }
3420 #endif /* CONFIG_ACPI */
3422 /* intel_device_info.c */
3423 static inline struct intel_device_info *
3424 mkwrite_device_info(struct drm_i915_private *dev_priv)
3426 return (struct intel_device_info *)&dev_priv->info;
3430 extern void intel_modeset_init_hw(struct drm_device *dev);
3431 extern int intel_modeset_init(struct drm_device *dev);
3432 extern void intel_modeset_cleanup(struct drm_device *dev);
3433 extern int intel_connector_register(struct drm_connector *);
3434 extern void intel_connector_unregister(struct drm_connector *);
3435 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3437 extern void intel_display_resume(struct drm_device *dev);
3438 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3439 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3440 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3441 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3442 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3443 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3446 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3447 struct drm_file *file);
3450 extern struct intel_overlay_error_state *
3451 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3452 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3453 struct intel_overlay_error_state *error);
3455 extern struct intel_display_error_state *
3456 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3457 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3458 struct intel_display_error_state *error);
3460 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3461 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3462 u32 val, int fast_timeout_us,
3463 int slow_timeout_ms);
3464 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3465 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3467 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3468 u32 reply_mask, u32 reply, int timeout_base_ms);
3470 /* intel_sideband.c */
3471 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3472 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3473 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3474 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3475 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3476 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3477 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3478 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3479 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3480 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3481 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3482 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3483 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3484 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3485 enum intel_sbi_destination destination);
3486 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3487 enum intel_sbi_destination destination);
3488 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3489 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3491 /* intel_dpio_phy.c */
3492 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3493 enum dpio_phy *phy, enum dpio_channel *ch);
3494 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3495 enum port port, u32 margin, u32 scale,
3496 u32 enable, u32 deemphasis);
3497 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3498 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3499 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3501 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3503 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3504 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3505 uint8_t lane_lat_optim_mask);
3506 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3508 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3509 u32 deemph_reg_value, u32 margin_reg_value,
3510 bool uniq_trans_scale);
3511 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3512 const struct intel_crtc_state *crtc_state,
3514 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3515 const struct intel_crtc_state *crtc_state);
3516 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3517 const struct intel_crtc_state *crtc_state);
3518 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3519 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3520 const struct intel_crtc_state *old_crtc_state);
3522 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3523 u32 demph_reg_value, u32 preemph_reg_value,
3524 u32 uniqtranscale_reg_value, u32 tx3_demph);
3525 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3526 const struct intel_crtc_state *crtc_state);
3527 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3528 const struct intel_crtc_state *crtc_state);
3529 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3530 const struct intel_crtc_state *old_crtc_state);
3532 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3533 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3534 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3535 const i915_reg_t reg);
3537 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3539 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3540 const i915_reg_t reg)
3542 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3545 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3546 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3548 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3549 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3550 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3551 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3553 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3554 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3555 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3556 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3558 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3559 * will be implemented using 2 32-bit writes in an arbitrary order with
3560 * an arbitrary delay between them. This can cause the hardware to
3561 * act upon the intermediate value, possibly leading to corruption and
3562 * machine death. For this reason we do not support I915_WRITE64, or
3563 * dev_priv->uncore.funcs.mmio_writeq.
3565 * When reading a 64-bit value as two 32-bit values, the delay may cause
3566 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3567 * occasionally a 64-bit register does not actualy support a full readq
3568 * and must be read using two 32-bit reads.
3570 * You have been warned.
3572 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3574 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3575 u32 upper, lower, old_upper, loop = 0; \
3576 upper = I915_READ(upper_reg); \
3578 old_upper = upper; \
3579 lower = I915_READ(lower_reg); \
3580 upper = I915_READ(upper_reg); \
3581 } while (upper != old_upper && loop++ < 2); \
3582 (u64)upper << 32 | lower; })
3584 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3585 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3587 #define __raw_read(x, s) \
3588 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3591 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3594 #define __raw_write(x, s) \
3595 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3596 i915_reg_t reg, uint##x##_t val) \
3598 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3613 /* These are untraced mmio-accessors that are only valid to be used inside
3614 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3617 * Think twice, and think again, before using these.
3619 * As an example, these accessors can possibly be used between:
3621 * spin_lock_irq(&dev_priv->uncore.lock);
3622 * intel_uncore_forcewake_get__locked();
3626 * intel_uncore_forcewake_put__locked();
3627 * spin_unlock_irq(&dev_priv->uncore.lock);
3630 * Note: some registers may not need forcewake held, so
3631 * intel_uncore_forcewake_{get,put} can be omitted, see
3632 * intel_uncore_forcewake_for_reg().
3634 * Certain architectures will die if the same cacheline is concurrently accessed
3635 * by different clients (e.g. on Ivybridge). Access to registers should
3636 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3637 * a more localised lock guarding all access to that bank of registers.
3639 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3640 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3641 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3642 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3644 /* "Broadcast RGB" property */
3645 #define INTEL_BROADCAST_RGB_AUTO 0
3646 #define INTEL_BROADCAST_RGB_FULL 1
3647 #define INTEL_BROADCAST_RGB_LIMITED 2
3649 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3651 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3652 return VLV_VGACNTRL;
3653 else if (INTEL_GEN(dev_priv) >= 5)
3654 return CPU_VGACNTRL;
3659 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3661 unsigned long j = msecs_to_jiffies(m);
3663 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3666 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3668 /* nsecs_to_jiffies64() does not guard against overflow */
3669 if (NSEC_PER_SEC % HZ &&
3670 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3671 return MAX_JIFFY_OFFSET;
3673 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3676 static inline unsigned long
3677 timespec_to_jiffies_timeout(const struct timespec *value)
3679 unsigned long j = timespec_to_jiffies(value);
3681 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3685 * If you need to wait X milliseconds between events A and B, but event B
3686 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3687 * when event A happened, then just before event B you call this function and
3688 * pass the timestamp as the first argument, and X as the second argument.
3691 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3693 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3696 * Don't re-read the value of "jiffies" every time since it may change
3697 * behind our back and break the math.
3699 tmp_jiffies = jiffies;
3700 target_jiffies = timestamp_jiffies +
3701 msecs_to_jiffies_timeout(to_wait_ms);
3703 if (time_after(target_jiffies, tmp_jiffies)) {
3704 remaining_jiffies = target_jiffies - tmp_jiffies;
3705 while (remaining_jiffies)
3707 schedule_timeout_uninterruptible(remaining_jiffies);
3712 __i915_request_irq_complete(const struct i915_request *rq)
3714 struct intel_engine_cs *engine = rq->engine;
3717 /* Note that the engine may have wrapped around the seqno, and
3718 * so our request->global_seqno will be ahead of the hardware,
3719 * even though it completed the request before wrapping. We catch
3720 * this by kicking all the waiters before resetting the seqno
3721 * in hardware, and also signal the fence.
3723 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3726 /* The request was dequeued before we were awoken. We check after
3727 * inspecting the hw to confirm that this was the same request
3728 * that generated the HWS update. The memory barriers within
3729 * the request execution are sufficient to ensure that a check
3730 * after reading the value from hw matches this request.
3732 seqno = i915_request_global_seqno(rq);
3736 /* Before we do the heavier coherent read of the seqno,
3737 * check the value (hopefully) in the CPU cacheline.
3739 if (__i915_request_completed(rq, seqno))
3742 /* Ensure our read of the seqno is coherent so that we
3743 * do not "miss an interrupt" (i.e. if this is the last
3744 * request and the seqno write from the GPU is not visible
3745 * by the time the interrupt fires, we will see that the
3746 * request is incomplete and go back to sleep awaiting
3747 * another interrupt that will never come.)
3749 * Strictly, we only need to do this once after an interrupt,
3750 * but it is easier and safer to do it every time the waiter
3753 if (engine->irq_seqno_barrier &&
3754 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3755 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3757 /* The ordering of irq_posted versus applying the barrier
3758 * is crucial. The clearing of the current irq_posted must
3759 * be visible before we perform the barrier operation,
3760 * such that if a subsequent interrupt arrives, irq_posted
3761 * is reasserted and our task rewoken (which causes us to
3762 * do another __i915_request_irq_complete() immediately
3763 * and reapply the barrier). Conversely, if the clear
3764 * occurs after the barrier, then an interrupt that arrived
3765 * whilst we waited on the barrier would not trigger a
3766 * barrier on the next pass, and the read may not see the
3769 engine->irq_seqno_barrier(engine);
3771 /* If we consume the irq, but we are no longer the bottom-half,
3772 * the real bottom-half may not have serialised their own
3773 * seqno check with the irq-barrier (i.e. may have inspected
3774 * the seqno before we believe it coherent since they see
3775 * irq_posted == false but we are still running).
3777 spin_lock_irq(&b->irq_lock);
3778 if (b->irq_wait && b->irq_wait->tsk != current)
3779 /* Note that if the bottom-half is changed as we
3780 * are sending the wake-up, the new bottom-half will
3781 * be woken by whomever made the change. We only have
3782 * to worry about when we steal the irq-posted for
3785 wake_up_process(b->irq_wait->tsk);
3786 spin_unlock_irq(&b->irq_lock);
3788 if (__i915_request_completed(rq, seqno))
3795 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3796 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3798 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3799 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3800 * perform the operation. To check beforehand, pass in the parameters to
3801 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3802 * you only need to pass in the minor offsets, page-aligned pointers are
3805 * For just checking for SSE4.1, in the foreknowledge that the future use
3806 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3808 #define i915_can_memcpy_from_wc(dst, src, len) \
3809 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3811 #define i915_has_memcpy_from_wc() \
3812 i915_memcpy_from_wc(NULL, NULL, 0)
3815 int remap_io_mapping(struct vm_area_struct *vma,
3816 unsigned long addr, unsigned long pfn, unsigned long size,
3817 struct io_mapping *iomap);
3819 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3821 if (INTEL_GEN(i915) >= 10)
3822 return CNL_HWS_CSB_WRITE_INDEX;
3824 return I915_HWS_CSB_WRITE_INDEX;