drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hashtable.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/pm_qos.h>
  44 #include <linux/reservation.h>
  45 #include <linux/shmem_fs.h>
  46
  47 #include <drm/drmP.h>
  48 #include <drm/intel-gtt.h>
  49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  50 #include <drm/drm_gem.h>
  51 #include <drm/drm_auth.h>
  52 #include <drm/drm_cache.h>
  53
  54 #include "i915_params.h"
  55 #include "i915_reg.h"
  56 #include "i915_utils.h"
  57
  58 #include "intel_bios.h"
  59 #include "intel_dpll_mgr.h"
  60 #include "intel_uc.h"
  61 #include "intel_lrc.h"
  62 #include "intel_ringbuffer.h"
  63
  64 #include "i915_gem.h"
  65 #include "i915_gem_context.h"
  66 #include "i915_gem_fence_reg.h"
  67 #include "i915_gem_object.h"
  68 #include "i915_gem_gtt.h"
  69 #include "i915_gem_render_state.h"
  70 #include "i915_gem_request.h"
  71 #include "i915_gem_timeline.h"
  72
  73 #include "i915_vma.h"
  74
  75 #include "intel_gvt.h"
  76
  77 /* General customization:
  78  */
  79
  80 #define DRIVER_NAME             "i915"
  81 #define DRIVER_DESC             "Intel Graphics"
  82 #define DRIVER_DATE             "20170123"
  83 #define DRIVER_TIMESTAMP        1485156432
  84
  85 #undef WARN_ON
  86 /* Many gcc seem to no see through this and fall over :( */
  87 #if 0
  88 #define WARN_ON(x) ({ \
  89         bool __i915_warn_cond = (x); \
  90         if (__builtin_constant_p(__i915_warn_cond)) \
  91                 BUILD_BUG_ON(__i915_warn_cond); \
  92         WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
  93 #else
  94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
  95 #endif
  96
  97 #undef WARN_ON_ONCE
  98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
  99
 100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
 101                              (long) (x), __func__);
 102
 103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 104  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 105  * which may not necessarily be a user visible problem.  This will either
 106  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 107  * enable distros and users to tailor their preferred amount of i915 abrt
 108  * spam.
 109  */
 110 #define I915_STATE_WARN(condition, format...) ({                        \
 111         int __ret_warn_on = !!(condition);                              \
 112         if (unlikely(__ret_warn_on))                                    \
 113                 if (!WARN(i915.verbose_state_checks, format))           \
 114                         DRM_ERROR(format);                              \
 115         unlikely(__ret_warn_on);                                        \
 116 })
 117
 118 #define I915_STATE_WARN_ON(x)                                           \
 119         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 120
 121 bool __i915_inject_load_failure(const char *func, int line);
 122 #define i915_inject_load_failure() \
 123         __i915_inject_load_failure(__func__, __LINE__)
 124
 125 typedef struct {
 126         uint32_t val;
 127 } uint_fixed_16_16_t;
 128
 129 #define FP_16_16_MAX ({ \
 130         uint_fixed_16_16_t fp; \
 131         fp.val = UINT_MAX; \
 132         fp; \
 133 })
 134
 135 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
 136 {
 137         uint_fixed_16_16_t fp;
 138
 139         WARN_ON(val >> 16);
 140
 141         fp.val = val << 16;
 142         return fp;
 143 }
 144
 145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
 146 {
 147         return DIV_ROUND_UP(fp.val, 1 << 16);
 148 }
 149
 150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
 151 {
 152         return fp.val >> 16;
 153 }
 154
 155 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
 156                                                  uint_fixed_16_16_t min2)
 157 {
 158         uint_fixed_16_16_t min;
 159
 160         min.val = min(min1.val, min2.val);
 161         return min;
 162 }
 163
 164 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
 165                                                  uint_fixed_16_16_t max2)
 166 {
 167         uint_fixed_16_16_t max;
 168
 169         max.val = max(max1.val, max2.val);
 170         return max;
 171 }
 172
 173 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
 174                                                           uint32_t d)
 175 {
 176         uint_fixed_16_16_t fp, res;
 177
 178         fp = u32_to_fixed_16_16(val);
 179         res.val = DIV_ROUND_UP(fp.val, d);
 180         return res;
 181 }
 182
 183 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
 184                                                               uint32_t d)
 185 {
 186         uint_fixed_16_16_t res;
 187         uint64_t interm_val;
 188
 189         interm_val = (uint64_t)val << 16;
 190         interm_val = DIV_ROUND_UP_ULL(interm_val, d);
 191         WARN_ON(interm_val >> 32);
 192         res.val = (uint32_t) interm_val;
 193
 194         return res;
 195 }
 196
 197 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
 198                                                      uint_fixed_16_16_t mul)
 199 {
 200         uint64_t intermediate_val;
 201         uint_fixed_16_16_t fp;
 202
 203         intermediate_val = (uint64_t) val * mul.val;
 204         WARN_ON(intermediate_val >> 32);
 205         fp.val = (uint32_t) intermediate_val;
 206         return fp;
 207 }
 208
 209 static inline const char *yesno(bool v)
 210 {
 211         return v ? "yes" : "no";
 212 }
 213
 214 static inline const char *onoff(bool v)
 215 {
 216         return v ? "on" : "off";
 217 }
 218
 219 static inline const char *enableddisabled(bool v)
 220 {
 221         return v ? "enabled" : "disabled";
 222 }
 223
 224 enum pipe {
 225         INVALID_PIPE = -1,
 226         PIPE_A = 0,
 227         PIPE_B,
 228         PIPE_C,
 229         _PIPE_EDP,
 230         I915_MAX_PIPES = _PIPE_EDP
 231 };
 232 #define pipe_name(p) ((p) + 'A')
 233
 234 enum transcoder {
 235         TRANSCODER_A = 0,
 236         TRANSCODER_B,
 237         TRANSCODER_C,
 238         TRANSCODER_EDP,
 239         TRANSCODER_DSI_A,
 240         TRANSCODER_DSI_C,
 241         I915_MAX_TRANSCODERS
 242 };
 243
 244 static inline const char *transcoder_name(enum transcoder transcoder)
 245 {
 246         switch (transcoder) {
 247         case TRANSCODER_A:
 248                 return "A";
 249         case TRANSCODER_B:
 250                 return "B";
 251         case TRANSCODER_C:
 252                 return "C";
 253         case TRANSCODER_EDP:
 254                 return "EDP";
 255         case TRANSCODER_DSI_A:
 256                 return "DSI A";
 257         case TRANSCODER_DSI_C:
 258                 return "DSI C";
 259         default:
 260                 return "<invalid>";
 261         }
 262 }
 263
 264 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 265 {
 266         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 267 }
 268
 269 /*
 270  * Global legacy plane identifier. Valid only for primary/sprite
 271  * planes on pre-g4x, and only for primary planes on g4x+.
 272  */
 273 enum plane {
 274         PLANE_A,
 275         PLANE_B,
 276         PLANE_C,
 277 };
 278 #define plane_name(p) ((p) + 'A')
 279
 280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 281
 282 /*
 283  * Per-pipe plane identifier.
 284  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 285  * number of planes per CRTC.  Not all platforms really have this many planes,
 286  * which means some arrays of size I915_MAX_PLANES may have unused entries
 287  * between the topmost sprite plane and the cursor plane.
 288  *
 289  * This is expected to be passed to various register macros
 290  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 291  */
 292 enum plane_id {
 293         PLANE_PRIMARY,
 294         PLANE_SPRITE0,
 295         PLANE_SPRITE1,
 296         PLANE_SPRITE2,
 297         PLANE_CURSOR,
 298         I915_MAX_PLANES,
 299 };
 300
 301 #define for_each_plane_id_on_crtc(__crtc, __p) \
 302         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 303                 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
 304
 305 enum port {
 306         PORT_NONE = -1,
 307         PORT_A = 0,
 308         PORT_B,
 309         PORT_C,
 310         PORT_D,
 311         PORT_E,
 312         I915_MAX_PORTS
 313 };
 314 #define port_name(p) ((p) + 'A')
 315
 316 #define I915_NUM_PHYS_VLV 2
 317
 318 enum dpio_channel {
 319         DPIO_CH0,
 320         DPIO_CH1
 321 };
 322
 323 enum dpio_phy {
 324         DPIO_PHY0,
 325         DPIO_PHY1,
 326         DPIO_PHY2,
 327 };
 328
 329 enum intel_display_power_domain {
 330         POWER_DOMAIN_PIPE_A,
 331         POWER_DOMAIN_PIPE_B,
 332         POWER_DOMAIN_PIPE_C,
 333         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 334         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 335         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 336         POWER_DOMAIN_TRANSCODER_A,
 337         POWER_DOMAIN_TRANSCODER_B,
 338         POWER_DOMAIN_TRANSCODER_C,
 339         POWER_DOMAIN_TRANSCODER_EDP,
 340         POWER_DOMAIN_TRANSCODER_DSI_A,
 341         POWER_DOMAIN_TRANSCODER_DSI_C,
 342         POWER_DOMAIN_PORT_DDI_A_LANES,
 343         POWER_DOMAIN_PORT_DDI_B_LANES,
 344         POWER_DOMAIN_PORT_DDI_C_LANES,
 345         POWER_DOMAIN_PORT_DDI_D_LANES,
 346         POWER_DOMAIN_PORT_DDI_E_LANES,
 347         POWER_DOMAIN_PORT_DSI,
 348         POWER_DOMAIN_PORT_CRT,
 349         POWER_DOMAIN_PORT_OTHER,
 350         POWER_DOMAIN_VGA,
 351         POWER_DOMAIN_AUDIO,
 352         POWER_DOMAIN_PLLS,
 353         POWER_DOMAIN_AUX_A,
 354         POWER_DOMAIN_AUX_B,
 355         POWER_DOMAIN_AUX_C,
 356         POWER_DOMAIN_AUX_D,
 357         POWER_DOMAIN_GMBUS,
 358         POWER_DOMAIN_MODESET,
 359         POWER_DOMAIN_INIT,
 360
 361         POWER_DOMAIN_NUM,
 362 };
 363
 364 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 365 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 366                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 367 #define POWER_DOMAIN_TRANSCODER(tran) \
 368         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 369          (tran) + POWER_DOMAIN_TRANSCODER_A)
 370
 371 enum hpd_pin {
 372         HPD_NONE = 0,
 373         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 374         HPD_CRT,
 375         HPD_SDVO_B,
 376         HPD_SDVO_C,
 377         HPD_PORT_A,
 378         HPD_PORT_B,
 379         HPD_PORT_C,
 380         HPD_PORT_D,
 381         HPD_PORT_E,
 382         HPD_NUM_PINS
 383 };
 384
 385 #define for_each_hpd_pin(__pin) \
 386         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 387
 388 struct i915_hotplug {
 389         struct work_struct hotplug_work;
 390
 391         struct {
 392                 unsigned long last_jiffies;
 393                 int count;
 394                 enum {
 395                         HPD_ENABLED = 0,
 396                         HPD_DISABLED = 1,
 397                         HPD_MARK_DISABLED = 2
 398                 } state;
 399         } stats[HPD_NUM_PINS];
 400         u32 event_bits;
 401         struct delayed_work reenable_work;
 402
 403         struct intel_digital_port *irq_port[I915_MAX_PORTS];
 404         u32 long_port_mask;
 405         u32 short_port_mask;
 406         struct work_struct dig_port_work;
 407
 408         struct work_struct poll_init_work;
 409         bool poll_enabled;
 410
 411         /*
 412          * if we get a HPD irq from DP and a HPD irq from non-DP
 413          * the non-DP HPD could block the workqueue on a mode config
 414          * mutex getting, that userspace may have taken. However
 415          * userspace is waiting on the DP workqueue to run which is
 416          * blocked behind the non-DP one.
 417          */
 418         struct workqueue_struct *dp_wq;
 419 };
 420
 421 #define I915_GEM_GPU_DOMAINS \
 422         (I915_GEM_DOMAIN_RENDER | \
 423          I915_GEM_DOMAIN_SAMPLER | \
 424          I915_GEM_DOMAIN_COMMAND | \
 425          I915_GEM_DOMAIN_INSTRUCTION | \
 426          I915_GEM_DOMAIN_VERTEX)
 427
 428 #define for_each_pipe(__dev_priv, __p) \
 429         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 430 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 431         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 432                 for_each_if ((__mask) & (1 << (__p)))
 433 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 434         for ((__p) = 0;                                                 \
 435              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
 436              (__p)++)
 437 #define for_each_sprite(__dev_priv, __p, __s)                           \
 438         for ((__s) = 0;                                                 \
 439              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
 440              (__s)++)
 441
 442 #define for_each_port_masked(__port, __ports_mask) \
 443         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 444                 for_each_if ((__ports_mask) & (1 << (__port)))
 445
 446 #define for_each_crtc(dev, crtc) \
 447         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 448
 449 #define for_each_intel_plane(dev, intel_plane) \
 450         list_for_each_entry(intel_plane,                        \
 451                             &(dev)->mode_config.plane_list,     \
 452                             base.head)
 453
 454 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 455         list_for_each_entry(intel_plane,                                \
 456                             &(dev)->mode_config.plane_list,             \
 457                             base.head)                                  \
 458                 for_each_if ((plane_mask) &                             \
 459                              (1 << drm_plane_index(&intel_plane->base)))
 460
 461 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 462         list_for_each_entry(intel_plane,                                \
 463                             &(dev)->mode_config.plane_list,             \
 464                             base.head)                                  \
 465                 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
 466
 467 #define for_each_intel_crtc(dev, intel_crtc)                            \
 468         list_for_each_entry(intel_crtc,                                 \
 469                             &(dev)->mode_config.crtc_list,              \
 470                             base.head)
 471
 472 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 473         list_for_each_entry(intel_crtc,                                 \
 474                             &(dev)->mode_config.crtc_list,              \
 475                             base.head)                                  \
 476                 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
 477
 478 #define for_each_intel_encoder(dev, intel_encoder)              \
 479         list_for_each_entry(intel_encoder,                      \
 480                             &(dev)->mode_config.encoder_list,   \
 481                             base.head)
 482
 483 #define for_each_intel_connector(dev, intel_connector)          \
 484         list_for_each_entry(intel_connector,                    \
 485                             &(dev)->mode_config.connector_list, \
 486                             base.head)
 487
 488 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 489         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 490                 for_each_if ((intel_encoder)->base.crtc == (__crtc))
 491
 492 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 493         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 494                 for_each_if ((intel_connector)->base.encoder == (__encoder))
 495
 496 #define for_each_power_domain(domain, mask)                             \
 497         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 498                 for_each_if ((1 << (domain)) & (mask))
 499
 500 struct drm_i915_private;
 501 struct i915_mm_struct;
 502 struct i915_mmu_object;
 503
 504 struct drm_i915_file_private {
 505         struct drm_i915_private *dev_priv;
 506         struct drm_file *file;
 507
 508         struct {
 509                 spinlock_t lock;
 510                 struct list_head request_list;
 511 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
 512  * chosen to prevent the CPU getting more than a frame ahead of the GPU
 513  * (when using lax throttling for the frontbuffer). We also use it to
 514  * offer free GPU waitboosts for severely congested workloads.
 515  */
 516 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
 517         } mm;
 518         struct idr context_idr;
 519
 520         struct intel_rps_client {
 521                 struct list_head link;
 522                 unsigned boosts;
 523         } rps;
 524
 525         unsigned int bsd_engine;
 526
 527 /* Client can have a maximum of 3 contexts banned before
 528  * it is denied of creating new contexts. As one context
 529  * ban needs 4 consecutive hangs, and more if there is
 530  * progress in between, this is a last resort stop gap measure
 531  * to limit the badly behaving clients access to gpu.
 532  */
 533 #define I915_MAX_CLIENT_CONTEXT_BANS 3
 534         int context_bans;
 535 };
 536
 537 /* Used by dp and fdi links */
 538 struct intel_link_m_n {
 539         uint32_t        tu;
 540         uint32_t        gmch_m;
 541         uint32_t        gmch_n;
 542         uint32_t        link_m;
 543         uint32_t        link_n;
 544 };
 545
 546 void intel_link_compute_m_n(int bpp, int nlanes,
 547                             int pixel_clock, int link_clock,
 548                             struct intel_link_m_n *m_n);
 549
 550 /* Interface history:
 551  *
 552  * 1.1: Original.
 553  * 1.2: Add Power Management
 554  * 1.3: Add vblank support
 555  * 1.4: Fix cmdbuffer path, add heap destroy
 556  * 1.5: Add vblank pipe configuration
 557  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 558  *      - Support vertical blank on secondary display pipe
 559  */
 560 #define DRIVER_MAJOR            1
 561 #define DRIVER_MINOR            6
 562 #define DRIVER_PATCHLEVEL       0
 563
 564 struct opregion_header;
 565 struct opregion_acpi;
 566 struct opregion_swsci;
 567 struct opregion_asle;
 568
 569 struct intel_opregion {
 570         struct opregion_header *header;
 571         struct opregion_acpi *acpi;
 572         struct opregion_swsci *swsci;
 573         u32 swsci_gbda_sub_functions;
 574         u32 swsci_sbcb_sub_functions;
 575         struct opregion_asle *asle;
 576         void *rvda;
 577         const void *vbt;
 578         u32 vbt_size;
 579         u32 *lid_state;
 580         struct work_struct asle_work;
 581 };
 582 #define OPREGION_SIZE            (8*1024)
 583
 584 struct intel_overlay;
 585 struct intel_overlay_error_state;
 586
 587 struct sdvo_device_mapping {
 588         u8 initialized;
 589         u8 dvo_port;
 590         u8 slave_addr;
 591         u8 dvo_wiring;
 592         u8 i2c_pin;
 593         u8 ddc_pin;
 594 };
 595
 596 struct intel_connector;
 597 struct intel_encoder;
 598 struct intel_atomic_state;
 599 struct intel_crtc_state;
 600 struct intel_initial_plane_config;
 601 struct intel_crtc;
 602 struct intel_limit;
 603 struct dpll;
 604
 605 struct drm_i915_display_funcs {
 606         int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
 607         int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
 608         int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
 609         int (*compute_intermediate_wm)(struct drm_device *dev,
 610                                        struct intel_crtc *intel_crtc,
 611                                        struct intel_crtc_state *newstate);
 612         void (*initial_watermarks)(struct intel_atomic_state *state,
 613                                    struct intel_crtc_state *cstate);
 614         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 615                                          struct intel_crtc_state *cstate);
 616         void (*optimize_watermarks)(struct intel_atomic_state *state,
 617                                     struct intel_crtc_state *cstate);
 618         int (*compute_global_watermarks)(struct drm_atomic_state *state);
 619         void (*update_wm)(struct intel_crtc *crtc);
 620         int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 621         void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
 622         /* Returns the active state of the crtc, and if the crtc is active,
 623          * fills out the pipe-config with the hw state. */
 624         bool (*get_pipe_config)(struct intel_crtc *,
 625                                 struct intel_crtc_state *);
 626         void (*get_initial_plane_config)(struct intel_crtc *,
 627                                          struct intel_initial_plane_config *);
 628         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 629                                   struct intel_crtc_state *crtc_state);
 630         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 631                             struct drm_atomic_state *old_state);
 632         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 633                              struct drm_atomic_state *old_state);
 634         void (*update_crtcs)(struct drm_atomic_state *state,
 635                              unsigned int *crtc_vblank_mask);
 636         void (*audio_codec_enable)(struct drm_connector *connector,
 637                                    struct intel_encoder *encoder,
 638                                    const struct drm_display_mode *adjusted_mode);
 639         void (*audio_codec_disable)(struct intel_encoder *encoder);
 640         void (*fdi_link_train)(struct drm_crtc *crtc);
 641         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 642         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 643                           struct drm_framebuffer *fb,
 644                           struct drm_i915_gem_object *obj,
 645                           struct drm_i915_gem_request *req,
 646                           uint32_t flags);
 647         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 648         /* clock updates for mode set */
 649         /* cursor updates */
 650         /* render clock increase/decrease */
 651         /* display clock increase/decrease */
 652         /* pll clock increase/decrease */
 653
 654         void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
 655         void (*load_luts)(struct drm_crtc_state *crtc_state);
 656 };
 657
 658 enum forcewake_domain_id {
 659         FW_DOMAIN_ID_RENDER = 0,
 660         FW_DOMAIN_ID_BLITTER,
 661         FW_DOMAIN_ID_MEDIA,
 662
 663         FW_DOMAIN_ID_COUNT
 664 };
 665
 666 enum forcewake_domains {
 667         FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
 668         FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
 669         FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
 670         FORCEWAKE_ALL = (FORCEWAKE_RENDER |
 671                          FORCEWAKE_BLITTER |
 672                          FORCEWAKE_MEDIA)
 673 };
 674
 675 #define FW_REG_READ  (1)
 676 #define FW_REG_WRITE (2)
 677
 678 enum decoupled_power_domain {
 679         GEN9_DECOUPLED_PD_BLITTER = 0,
 680         GEN9_DECOUPLED_PD_RENDER,
 681         GEN9_DECOUPLED_PD_MEDIA,
 682         GEN9_DECOUPLED_PD_ALL
 683 };
 684
 685 enum decoupled_ops {
 686         GEN9_DECOUPLED_OP_WRITE = 0,
 687         GEN9_DECOUPLED_OP_READ
 688 };
 689
 690 enum forcewake_domains
 691 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 692                                i915_reg_t reg, unsigned int op);
 693
 694 struct intel_uncore_funcs {
 695         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 696                                                         enum forcewake_domains domains);
 697         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 698                                                         enum forcewake_domains domains);
 699
 700         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 701         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 702         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 703         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 704
 705         void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
 706                                 uint8_t val, bool trace);
 707         void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
 708                                 uint16_t val, bool trace);
 709         void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
 710                                 uint32_t val, bool trace);
 711 };
 712
 713 struct intel_forcewake_range {
 714         u32 start;
 715         u32 end;
 716
 717         enum forcewake_domains domains;
 718 };
 719
 720 struct intel_uncore {
 721         spinlock_t lock; /** lock is also taken in irq contexts. */
 722
 723         const struct intel_forcewake_range *fw_domains_table;
 724         unsigned int fw_domains_table_entries;
 725
 726         struct intel_uncore_funcs funcs;
 727
 728         unsigned fifo_count;
 729
 730         enum forcewake_domains fw_domains;
 731         enum forcewake_domains fw_domains_active;
 732
 733         struct intel_uncore_forcewake_domain {
 734                 struct drm_i915_private *i915;
 735                 enum forcewake_domain_id id;
 736                 enum forcewake_domains mask;
 737                 unsigned wake_count;
 738                 struct hrtimer timer;
 739                 i915_reg_t reg_set;
 740                 u32 val_set;
 741                 u32 val_clear;
 742                 i915_reg_t reg_ack;
 743                 i915_reg_t reg_post;
 744                 u32 val_reset;
 745         } fw_domain[FW_DOMAIN_ID_COUNT];
 746
 747         int unclaimed_mmio_check;
 748 };
 749
 750 /* Iterate over initialised fw domains */
 751 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
 752         for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
 753              (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
 754              (domain__)++) \
 755                 for_each_if ((mask__) & (domain__)->mask)
 756
 757 #define for_each_fw_domain(domain__, dev_priv__) \
 758         for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
 759
 760 #define CSR_VERSION(major, minor)       ((major) << 16 | (minor))
 761 #define CSR_VERSION_MAJOR(version)      ((version) >> 16)
 762 #define CSR_VERSION_MINOR(version)      ((version) & 0xffff)
 763
 764 struct intel_csr {
 765         struct work_struct work;
 766         const char *fw_path;
 767         uint32_t *dmc_payload;
 768         uint32_t dmc_fw_size;
 769         uint32_t version;
 770         uint32_t mmio_count;
 771         i915_reg_t mmioaddr[8];
 772         uint32_t mmiodata[8];
 773         uint32_t dc_state;
 774         uint32_t allowed_dc_mask;
 775 };
 776
 777 #define DEV_INFO_FOR_EACH_FLAG(func) \
 778         func(is_mobile); \
 779         func(is_lp); \
 780         func(is_alpha_support); \
 781         /* Keep has_* in alphabetical order */ \
 782         func(has_64bit_reloc); \
 783         func(has_aliasing_ppgtt); \
 784         func(has_csr); \
 785         func(has_ddi); \
 786         func(has_decoupled_mmio); \
 787         func(has_dp_mst); \
 788         func(has_fbc); \
 789         func(has_fpga_dbg); \
 790         func(has_full_ppgtt); \
 791         func(has_full_48bit_ppgtt); \
 792         func(has_gmbus_irq); \
 793         func(has_gmch_display); \
 794         func(has_guc); \
 795         func(has_hotplug); \
 796         func(has_hw_contexts); \
 797         func(has_l3_dpf); \
 798         func(has_llc); \
 799         func(has_logical_ring_contexts); \
 800         func(has_overlay); \
 801         func(has_pipe_cxsr); \
 802         func(has_pooled_eu); \
 803         func(has_psr); \
 804         func(has_rc6); \
 805         func(has_rc6p); \
 806         func(has_resource_streamer); \
 807         func(has_runtime_pm); \
 808         func(has_snoop); \
 809         func(unfenced_needs_alignment); \
 810         func(cursor_needs_physical); \
 811         func(hws_needs_physical); \
 812         func(overlay_needs_physical); \
 813         func(supports_tv);
 814
 815 struct sseu_dev_info {
 816         u8 slice_mask;
 817         u8 subslice_mask;
 818         u8 eu_total;
 819         u8 eu_per_subslice;
 820         u8 min_eu_in_pool;
 821         /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 822         u8 subslice_7eu[3];
 823         u8 has_slice_pg:1;
 824         u8 has_subslice_pg:1;
 825         u8 has_eu_pg:1;
 826 };
 827
 828 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
 829 {
 830         return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
 831 }
 832
 833 /* Keep in gen based order, and chronological order within a gen */
 834 enum intel_platform {
 835         INTEL_PLATFORM_UNINITIALIZED = 0,
 836         INTEL_I830,
 837         INTEL_I845G,
 838         INTEL_I85X,
 839         INTEL_I865G,
 840         INTEL_I915G,
 841         INTEL_I915GM,
 842         INTEL_I945G,
 843         INTEL_I945GM,
 844         INTEL_G33,
 845         INTEL_PINEVIEW,
 846         INTEL_I965G,
 847         INTEL_I965GM,
 848         INTEL_G45,
 849         INTEL_GM45,
 850         INTEL_IRONLAKE,
 851         INTEL_SANDYBRIDGE,
 852         INTEL_IVYBRIDGE,
 853         INTEL_VALLEYVIEW,
 854         INTEL_HASWELL,
 855         INTEL_BROADWELL,
 856         INTEL_CHERRYVIEW,
 857         INTEL_SKYLAKE,
 858         INTEL_BROXTON,
 859         INTEL_KABYLAKE,
 860         INTEL_GEMINILAKE,
 861 };
 862
 863 struct intel_device_info {
 864         u32 display_mmio_offset;
 865         u16 device_id;
 866         u8 num_pipes;
 867         u8 num_sprites[I915_MAX_PIPES];
 868         u8 num_scalers[I915_MAX_PIPES];
 869         u8 gen;
 870         u16 gen_mask;
 871         enum intel_platform platform;
 872         u8 ring_mask; /* Rings supported by the HW */
 873         u8 num_rings;
 874 #define DEFINE_FLAG(name) u8 name:1
 875         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 876 #undef DEFINE_FLAG
 877         u16 ddb_size; /* in blocks */
 878         /* Register offsets for the various display pipes and transcoders */
 879         int pipe_offsets[I915_MAX_TRANSCODERS];
 880         int trans_offsets[I915_MAX_TRANSCODERS];
 881         int palette_offsets[I915_MAX_PIPES];
 882         int cursor_offsets[I915_MAX_PIPES];
 883
 884         /* Slice/subslice/EU info */
 885         struct sseu_dev_info sseu;
 886
 887         struct color_luts {
 888                 u16 degamma_lut_size;
 889                 u16 gamma_lut_size;
 890         } color;
 891 };
 892
 893 struct intel_display_error_state;
 894
 895 struct drm_i915_error_state {
 896         struct kref ref;
 897         struct timeval time;
 898         struct timeval boottime;
 899         struct timeval uptime;
 900
 901         struct drm_i915_private *i915;
 902
 903         char error_msg[128];
 904         bool simulated;
 905         int iommu;
 906         u32 reset_count;
 907         u32 suspend_count;
 908         struct intel_device_info device_info;
 909
 910         /* Generic register state */
 911         u32 eir;
 912         u32 pgtbl_er;
 913         u32 ier;
 914         u32 gtier[4];
 915         u32 ccid;
 916         u32 derrmr;
 917         u32 forcewake;
 918         u32 error; /* gen6+ */
 919         u32 err_int; /* gen7 */
 920         u32 fault_data0; /* gen8, gen9 */
 921         u32 fault_data1; /* gen8, gen9 */
 922         u32 done_reg;
 923         u32 gac_eco;
 924         u32 gam_ecochk;
 925         u32 gab_ctl;
 926         u32 gfx_mode;
 927
 928         u64 fence[I915_MAX_NUM_FENCES];
 929         struct intel_overlay_error_state *overlay;
 930         struct intel_display_error_state *display;
 931         struct drm_i915_error_object *semaphore;
 932         struct drm_i915_error_object *guc_log;
 933
 934         struct drm_i915_error_engine {
 935                 int engine_id;
 936                 /* Software tracked state */
 937                 bool waiting;
 938                 int num_waiters;
 939                 unsigned long hangcheck_timestamp;
 940                 bool hangcheck_stalled;
 941                 enum intel_engine_hangcheck_action hangcheck_action;
 942                 struct i915_address_space *vm;
 943                 int num_requests;
 944
 945                 /* position of active request inside the ring */
 946                 u32 rq_head, rq_post, rq_tail;
 947
 948                 /* our own tracking of ring head and tail */
 949                 u32 cpu_ring_head;
 950                 u32 cpu_ring_tail;
 951
 952                 u32 last_seqno;
 953
 954                 /* Register state */
 955                 u32 start;
 956                 u32 tail;
 957                 u32 head;
 958                 u32 ctl;
 959                 u32 mode;
 960                 u32 hws;
 961                 u32 ipeir;
 962                 u32 ipehr;
 963                 u32 bbstate;
 964                 u32 instpm;
 965                 u32 instps;
 966                 u32 seqno;
 967                 u64 bbaddr;
 968                 u64 acthd;
 969                 u32 fault_reg;
 970                 u64 faddr;
 971                 u32 rc_psmi; /* sleep state */
 972                 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
 973                 struct intel_instdone instdone;
 974
 975                 struct drm_i915_error_object {
 976                         u64 gtt_offset;
 977                         u64 gtt_size;
 978                         int page_count;
 979                         int unused;
 980                         u32 *pages[0];
 981                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 982
 983                 struct drm_i915_error_object *wa_ctx;
 984
 985                 struct drm_i915_error_request {
 986                         long jiffies;
 987                         pid_t pid;
 988                         u32 context;
 989                         int ban_score;
 990                         u32 seqno;
 991                         u32 head;
 992                         u32 tail;
 993                 } *requests, execlist[2];
 994
 995                 struct drm_i915_error_waiter {
 996                         char comm[TASK_COMM_LEN];
 997                         pid_t pid;
 998                         u32 seqno;
 999                 } *waiters;
1000
1001                 struct {
1002                         u32 gfx_mode;
1003                         union {
1004                                 u64 pdp[4];
1005                                 u32 pp_dir_base;
1006                         };
1007                 } vm_info;
1008
1009                 pid_t pid;
1010                 char comm[TASK_COMM_LEN];
1011                 int context_bans;
1012         } engine[I915_NUM_ENGINES];
1013
1014         struct drm_i915_error_buffer {
1015                 u32 size;
1016                 u32 name;
1017                 u32 rseqno[I915_NUM_ENGINES], wseqno;
1018                 u64 gtt_offset;
1019                 u32 read_domains;
1020                 u32 write_domain;
1021                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1022                 u32 tiling:2;
1023                 u32 dirty:1;
1024                 u32 purgeable:1;
1025                 u32 userptr:1;
1026                 s32 engine:4;
1027                 u32 cache_level:3;
1028         } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1029         u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1030         struct i915_address_space *active_vm[I915_NUM_ENGINES];
1031 };
1032
1033 enum i915_cache_level {
1034         I915_CACHE_NONE = 0,
1035         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1036         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1037                               caches, eg sampler/render caches, and the
1038                               large Last-Level-Cache. LLC is coherent with
1039                               the CPU, but L3 is only visible to the GPU. */
1040         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1041 };
1042
1043 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1044
1045 enum fb_op_origin {
1046         ORIGIN_GTT,
1047         ORIGIN_CPU,
1048         ORIGIN_CS,
1049         ORIGIN_FLIP,
1050         ORIGIN_DIRTYFB,
1051 };
1052
1053 struct intel_fbc {
1054         /* This is always the inner lock when overlapping with struct_mutex and
1055          * it's the outer lock when overlapping with stolen_lock. */
1056         struct mutex lock;
1057         unsigned threshold;
1058         unsigned int possible_framebuffer_bits;
1059         unsigned int busy_bits;
1060         unsigned int visible_pipes_mask;
1061         struct intel_crtc *crtc;
1062
1063         struct drm_mm_node compressed_fb;
1064         struct drm_mm_node *compressed_llb;
1065
1066         bool false_color;
1067
1068         bool enabled;
1069         bool active;
1070
1071         bool underrun_detected;
1072         struct work_struct underrun_work;
1073
1074         struct intel_fbc_state_cache {
1075                 struct i915_vma *vma;
1076
1077                 struct {
1078                         unsigned int mode_flags;
1079                         uint32_t hsw_bdw_pixel_rate;
1080                 } crtc;
1081
1082                 struct {
1083                         unsigned int rotation;
1084                         int src_w;
1085                         int src_h;
1086                         bool visible;
1087                 } plane;
1088
1089                 struct {
1090                         const struct drm_format_info *format;
1091                         unsigned int stride;
1092                 } fb;
1093         } state_cache;
1094
1095         struct intel_fbc_reg_params {
1096                 struct i915_vma *vma;
1097
1098                 struct {
1099                         enum pipe pipe;
1100                         enum plane plane;
1101                         unsigned int fence_y_offset;
1102                 } crtc;
1103
1104                 struct {
1105                         const struct drm_format_info *format;
1106                         unsigned int stride;
1107                 } fb;
1108
1109                 int cfb_size;
1110         } params;
1111
1112         struct intel_fbc_work {
1113                 bool scheduled;
1114                 u32 scheduled_vblank;
1115                 struct work_struct work;
1116         } work;
1117
1118         const char *no_fbc_reason;
1119 };
1120
1121 /*
1122  * HIGH_RR is the highest eDP panel refresh rate read from EDID
1123  * LOW_RR is the lowest eDP panel refresh rate found from EDID
1124  * parsing for same resolution.
1125  */
1126 enum drrs_refresh_rate_type {
1127         DRRS_HIGH_RR,
1128         DRRS_LOW_RR,
1129         DRRS_MAX_RR, /* RR count */
1130 };
1131
1132 enum drrs_support_type {
1133         DRRS_NOT_SUPPORTED = 0,
1134         STATIC_DRRS_SUPPORT = 1,
1135         SEAMLESS_DRRS_SUPPORT = 2
1136 };
1137
1138 struct intel_dp;
1139 struct i915_drrs {
1140         struct mutex mutex;
1141         struct delayed_work work;
1142         struct intel_dp *dp;
1143         unsigned busy_frontbuffer_bits;
1144         enum drrs_refresh_rate_type refresh_rate_type;
1145         enum drrs_support_type type;
1146 };
1147
1148 struct i915_psr {
1149         struct mutex lock;
1150         bool sink_support;
1151         bool source_ok;
1152         struct intel_dp *enabled;
1153         bool active;
1154         struct delayed_work work;
1155         unsigned busy_frontbuffer_bits;
1156         bool psr2_support;
1157         bool aux_frame_sync;
1158         bool link_standby;
1159         bool y_cord_support;
1160         bool colorimetry_support;
1161         bool alpm;
1162 };
1163
1164 enum intel_pch {
1165         PCH_NONE = 0,   /* No PCH present */
1166         PCH_IBX,        /* Ibexpeak PCH */
1167         PCH_CPT,        /* Cougarpoint PCH */
1168         PCH_LPT,        /* Lynxpoint PCH */
1169         PCH_SPT,        /* Sunrisepoint PCH */
1170         PCH_KBP,        /* Kabypoint PCH */
1171         PCH_NOP,
1172 };
1173
1174 enum intel_sbi_destination {
1175         SBI_ICLK,
1176         SBI_MPHY,
1177 };
1178
1179 #define QUIRK_PIPEA_FORCE (1<<0)
1180 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1181 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1182 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1183 #define QUIRK_PIPEB_FORCE (1<<4)
1184 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1185
1186 struct intel_fbdev;
1187 struct intel_fbc_work;
1188
1189 struct intel_gmbus {
1190         struct i2c_adapter adapter;
1191 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1192         u32 force_bit;
1193         u32 reg0;
1194         i915_reg_t gpio_reg;
1195         struct i2c_algo_bit_data bit_algo;
1196         struct drm_i915_private *dev_priv;
1197 };
1198
1199 struct i915_suspend_saved_registers {
1200         u32 saveDSPARB;
1201         u32 saveFBC_CONTROL;
1202         u32 saveCACHE_MODE_0;
1203         u32 saveMI_ARB_STATE;
1204         u32 saveSWF0[16];
1205         u32 saveSWF1[16];
1206         u32 saveSWF3[3];
1207         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1208         u32 savePCH_PORT_HOTPLUG;
1209         u16 saveGCDGMBUS;
1210 };
1211
1212 struct vlv_s0ix_state {
1213         /* GAM */
1214         u32 wr_watermark;
1215         u32 gfx_prio_ctrl;
1216         u32 arb_mode;
1217         u32 gfx_pend_tlb0;
1218         u32 gfx_pend_tlb1;
1219         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1220         u32 media_max_req_count;
1221         u32 gfx_max_req_count;
1222         u32 render_hwsp;
1223         u32 ecochk;
1224         u32 bsd_hwsp;
1225         u32 blt_hwsp;
1226         u32 tlb_rd_addr;
1227
1228         /* MBC */
1229         u32 g3dctl;
1230         u32 gsckgctl;
1231         u32 mbctl;
1232
1233         /* GCP */
1234         u32 ucgctl1;
1235         u32 ucgctl3;
1236         u32 rcgctl1;
1237         u32 rcgctl2;
1238         u32 rstctl;
1239         u32 misccpctl;
1240
1241         /* GPM */
1242         u32 gfxpause;
1243         u32 rpdeuhwtc;
1244         u32 rpdeuc;
1245         u32 ecobus;
1246         u32 pwrdwnupctl;
1247         u32 rp_down_timeout;
1248         u32 rp_deucsw;
1249         u32 rcubmabdtmr;
1250         u32 rcedata;
1251         u32 spare2gh;
1252
1253         /* Display 1 CZ domain */
1254         u32 gt_imr;
1255         u32 gt_ier;
1256         u32 pm_imr;
1257         u32 pm_ier;
1258         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1259
1260         /* GT SA CZ domain */
1261         u32 tilectl;
1262         u32 gt_fifoctl;
1263         u32 gtlc_wake_ctrl;
1264         u32 gtlc_survive;
1265         u32 pmwgicz;
1266
1267         /* Display 2 CZ domain */
1268         u32 gu_ctl0;
1269         u32 gu_ctl1;
1270         u32 pcbr;
1271         u32 clock_gate_dis2;
1272 };
1273
1274 struct intel_rps_ei {
1275         u32 cz_clock;
1276         u32 render_c0;
1277         u32 media_c0;
1278 };
1279
1280 struct intel_gen6_power_mgmt {
1281         /*
1282          * work, interrupts_enabled and pm_iir are protected by
1283          * dev_priv->irq_lock
1284          */
1285         struct work_struct work;
1286         bool interrupts_enabled;
1287         u32 pm_iir;
1288
1289         /* PM interrupt bits that should never be masked */
1290         u32 pm_intr_keep;
1291
1292         /* Frequencies are stored in potentially platform dependent multiples.
1293          * In other words, *_freq needs to be multiplied by X to be interesting.
1294          * Soft limits are those which are used for the dynamic reclocking done
1295          * by the driver (raise frequencies under heavy loads, and lower for
1296          * lighter loads). Hard limits are those imposed by the hardware.
1297          *
1298          * A distinction is made for overclocking, which is never enabled by
1299          * default, and is considered to be above the hard limit if it's
1300          * possible at all.
1301          */
1302         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
1303         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
1304         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
1305         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
1306         u8 min_freq;            /* AKA RPn. Minimum frequency */
1307         u8 boost_freq;          /* Frequency to request when wait boosting */
1308         u8 idle_freq;           /* Frequency to request when we are idle */
1309         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1310         u8 rp1_freq;            /* "less than" RP0 power/freqency */
1311         u8 rp0_freq;            /* Non-overclocked max frequency. */
1312         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
1313
1314         u8 up_threshold; /* Current %busy required to uplock */
1315         u8 down_threshold; /* Current %busy required to downclock */
1316
1317         int last_adj;
1318         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1319
1320         spinlock_t client_lock;
1321         struct list_head clients;
1322         bool client_boost;
1323
1324         bool enabled;
1325         struct delayed_work autoenable_work;
1326         unsigned boosts;
1327
1328         /* manual wa residency calculations */
1329         struct intel_rps_ei ei;
1330
1331         /*
1332          * Protects RPS/RC6 register access and PCU communication.
1333          * Must be taken after struct_mutex if nested. Note that
1334          * this lock may be held for long periods of time when
1335          * talking to hw - so only take it when talking to hw!
1336          */
1337         struct mutex hw_lock;
1338 };
1339
1340 /* defined intel_pm.c */
1341 extern spinlock_t mchdev_lock;
1342
1343 struct intel_ilk_power_mgmt {
1344         u8 cur_delay;
1345         u8 min_delay;
1346         u8 max_delay;
1347         u8 fmax;
1348         u8 fstart;
1349
1350         u64 last_count1;
1351         unsigned long last_time1;
1352         unsigned long chipset_power;
1353         u64 last_count2;
1354         u64 last_time2;
1355         unsigned long gfx_power;
1356         u8 corr;
1357
1358         int c_m;
1359         int r_t;
1360 };
1361
1362 struct drm_i915_private;
1363 struct i915_power_well;
1364
1365 struct i915_power_well_ops {
1366         /*
1367          * Synchronize the well's hw state to match the current sw state, for
1368          * example enable/disable it based on the current refcount. Called
1369          * during driver init and resume time, possibly after first calling
1370          * the enable/disable handlers.
1371          */
1372         void (*sync_hw)(struct drm_i915_private *dev_priv,
1373                         struct i915_power_well *power_well);
1374         /*
1375          * Enable the well and resources that depend on it (for example
1376          * interrupts located on the well). Called after the 0->1 refcount
1377          * transition.
1378          */
1379         void (*enable)(struct drm_i915_private *dev_priv,
1380                        struct i915_power_well *power_well);
1381         /*
1382          * Disable the well and resources that depend on it. Called after
1383          * the 1->0 refcount transition.
1384          */
1385         void (*disable)(struct drm_i915_private *dev_priv,
1386                         struct i915_power_well *power_well);
1387         /* Returns the hw enabled state. */
1388         bool (*is_enabled)(struct drm_i915_private *dev_priv,
1389                            struct i915_power_well *power_well);
1390 };
1391
1392 /* Power well structure for haswell */
1393 struct i915_power_well {
1394         const char *name;
1395         bool always_on;
1396         /* power well enable/disable usage count */
1397         int count;
1398         /* cached hw enabled state */
1399         bool hw_enabled;
1400         unsigned long domains;
1401         /* unique identifier for this power well */
1402         unsigned long id;
1403         /*
1404          * Arbitraty data associated with this power well. Platform and power
1405          * well specific.
1406          */
1407         unsigned long data;
1408         const struct i915_power_well_ops *ops;
1409 };
1410
1411 struct i915_power_domains {
1412         /*
1413          * Power wells needed for initialization at driver init and suspend
1414          * time are on. They are kept on until after the first modeset.
1415          */
1416         bool init_power_on;
1417         bool initializing;
1418         int power_well_count;
1419
1420         struct mutex lock;
1421         int domain_use_count[POWER_DOMAIN_NUM];
1422         struct i915_power_well *power_wells;
1423 };
1424
1425 #define MAX_L3_SLICES 2
1426 struct intel_l3_parity {
1427         u32 *remap_info[MAX_L3_SLICES];
1428         struct work_struct error_work;
1429         int which_slice;
1430 };
1431
1432 struct i915_gem_mm {
1433         /** Memory allocator for GTT stolen memory */
1434         struct drm_mm stolen;
1435         /** Protects the usage of the GTT stolen memory allocator. This is
1436          * always the inner lock when overlapping with struct_mutex. */
1437         struct mutex stolen_lock;
1438
1439         /** List of all objects in gtt_space. Used to restore gtt
1440          * mappings on resume */
1441         struct list_head bound_list;
1442         /**
1443          * List of objects which are not bound to the GTT (thus
1444          * are idle and not used by the GPU). These objects may or may
1445          * not actually have any pages attached.
1446          */
1447         struct list_head unbound_list;
1448
1449         /** List of all objects in gtt_space, currently mmaped by userspace.
1450          * All objects within this list must also be on bound_list.
1451          */
1452         struct list_head userfault_list;
1453
1454         /**
1455          * List of objects which are pending destruction.
1456          */
1457         struct llist_head free_list;
1458         struct work_struct free_work;
1459
1460         /** Usable portion of the GTT for GEM */
1461         phys_addr_t stolen_base; /* limited to low memory (32-bit) */
1462
1463         /** PPGTT used for aliasing the PPGTT with the GTT */
1464         struct i915_hw_ppgtt *aliasing_ppgtt;
1465
1466         struct notifier_block oom_notifier;
1467         struct notifier_block vmap_notifier;
1468         struct shrinker shrinker;
1469
1470         /** LRU list of objects with fence regs on them. */
1471         struct list_head fence_list;
1472
1473         /**
1474          * Are we in a non-interruptible section of code like
1475          * modesetting?
1476          */
1477         bool interruptible;
1478
1479         /* the indicator for dispatch video commands on two BSD rings */
1480         atomic_t bsd_engine_dispatch_index;
1481
1482         /** Bit 6 swizzling required for X tiling */
1483         uint32_t bit_6_swizzle_x;
1484         /** Bit 6 swizzling required for Y tiling */
1485         uint32_t bit_6_swizzle_y;
1486
1487         /* accounting, useful for userland debugging */
1488         spinlock_t object_stat_lock;
1489         u64 object_memory;
1490         u32 object_count;
1491 };
1492
1493 struct drm_i915_error_state_buf {
1494         struct drm_i915_private *i915;
1495         unsigned bytes;
1496         unsigned size;
1497         int err;
1498         u8 *buf;
1499         loff_t start;
1500         loff_t pos;
1501 };
1502
1503 struct i915_error_state_file_priv {
1504         struct drm_i915_private *i915;
1505         struct drm_i915_error_state *error;
1506 };
1507
1508 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1509 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1510
1511 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
1512 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
1513
1514 struct i915_gpu_error {
1515         /* For hangcheck timer */
1516 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1517 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1518
1519         struct delayed_work hangcheck_work;
1520
1521         /* For reset and error_state handling. */
1522         spinlock_t lock;
1523         /* Protected by the above dev->gpu_error.lock. */
1524         struct drm_i915_error_state *first_error;
1525
1526         unsigned long missed_irq_rings;
1527
1528         /**
1529          * State variable controlling the reset flow and count
1530          *
1531          * This is a counter which gets incremented when reset is triggered,
1532          *
1533          * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1534          * meaning that any waiters holding onto the struct_mutex should
1535          * relinquish the lock immediately in order for the reset to start.
1536          *
1537          * If reset is not completed succesfully, the I915_WEDGE bit is
1538          * set meaning that hardware is terminally sour and there is no
1539          * recovery. All waiters on the reset_queue will be woken when
1540          * that happens.
1541          *
1542          * This counter is used by the wait_seqno code to notice that reset
1543          * event happened and it needs to restart the entire ioctl (since most
1544          * likely the seqno it waited for won't ever signal anytime soon).
1545          *
1546          * This is important for lock-free wait paths, where no contended lock
1547          * naturally enforces the correct ordering between the bail-out of the
1548          * waiter and the gpu reset work code.
1549          */
1550         unsigned long reset_count;
1551
1552         unsigned long flags;
1553 #define I915_RESET_IN_PROGRESS  0
1554 #define I915_WEDGED             (BITS_PER_LONG - 1)
1555
1556         /**
1557          * Waitqueue to signal when a hang is detected. Used to for waiters
1558          * to release the struct_mutex for the reset to procede.
1559          */
1560         wait_queue_head_t wait_queue;
1561
1562         /**
1563          * Waitqueue to signal when the reset has completed. Used by clients
1564          * that wait for dev_priv->mm.wedged to settle.
1565          */
1566         wait_queue_head_t reset_queue;
1567
1568         /* For missed irq/seqno simulation. */
1569         unsigned long test_irq_rings;
1570 };
1571
1572 enum modeset_restore {
1573         MODESET_ON_LID_OPEN,
1574         MODESET_DONE,
1575         MODESET_SUSPENDED,
1576 };
1577
1578 #define DP_AUX_A 0x40
1579 #define DP_AUX_B 0x10
1580 #define DP_AUX_C 0x20
1581 #define DP_AUX_D 0x30
1582
1583 #define DDC_PIN_B  0x05
1584 #define DDC_PIN_C  0x04
1585 #define DDC_PIN_D  0x06
1586
1587 struct ddi_vbt_port_info {
1588         /*
1589          * This is an index in the HDMI/DVI DDI buffer translation table.
1590          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1591          * populate this field.
1592          */
1593 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1594         uint8_t hdmi_level_shift;
1595
1596         uint8_t supports_dvi:1;
1597         uint8_t supports_hdmi:1;
1598         uint8_t supports_dp:1;
1599         uint8_t supports_edp:1;
1600
1601         uint8_t alternate_aux_channel;
1602         uint8_t alternate_ddc_pin;
1603
1604         uint8_t dp_boost_level;
1605         uint8_t hdmi_boost_level;
1606 };
1607
1608 enum psr_lines_to_wait {
1609         PSR_0_LINES_TO_WAIT = 0,
1610         PSR_1_LINE_TO_WAIT,
1611         PSR_4_LINES_TO_WAIT,
1612         PSR_8_LINES_TO_WAIT
1613 };
1614
1615 struct intel_vbt_data {
1616         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1617         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1618
1619         /* Feature bits */
1620         unsigned int int_tv_support:1;
1621         unsigned int lvds_dither:1;
1622         unsigned int lvds_vbt:1;
1623         unsigned int int_crt_support:1;
1624         unsigned int lvds_use_ssc:1;
1625         unsigned int display_clock_mode:1;
1626         unsigned int fdi_rx_polarity_inverted:1;
1627         unsigned int panel_type:4;
1628         int lvds_ssc_freq;
1629         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1630
1631         enum drrs_support_type drrs_type;
1632
1633         struct {
1634                 int rate;
1635                 int lanes;
1636                 int preemphasis;
1637                 int vswing;
1638                 bool low_vswing;
1639                 bool initialized;
1640                 bool support;
1641                 int bpp;
1642                 struct edp_power_seq pps;
1643         } edp;
1644
1645         struct {
1646                 bool full_link;
1647                 bool require_aux_wakeup;
1648                 int idle_frames;
1649                 enum psr_lines_to_wait lines_to_wait;
1650                 int tp1_wakeup_time;
1651                 int tp2_tp3_wakeup_time;
1652         } psr;
1653
1654         struct {
1655                 u16 pwm_freq_hz;
1656                 bool present;
1657                 bool active_low_pwm;
1658                 u8 min_brightness;      /* min_brightness/255 of max */
1659                 u8 controller;          /* brightness controller number */
1660                 enum intel_backlight_type type;
1661         } backlight;
1662
1663         /* MIPI DSI */
1664         struct {
1665                 u16 panel_id;
1666                 struct mipi_config *config;
1667                 struct mipi_pps_data *pps;
1668                 u8 seq_version;
1669                 u32 size;
1670                 u8 *data;
1671                 const u8 *sequence[MIPI_SEQ_MAX];
1672         } dsi;
1673
1674         int crt_ddc_pin;
1675
1676         int child_dev_num;
1677         union child_device_config *child_dev;
1678
1679         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1680         struct sdvo_device_mapping sdvo_mappings[2];
1681 };
1682
1683 enum intel_ddb_partitioning {
1684         INTEL_DDB_PART_1_2,
1685         INTEL_DDB_PART_5_6, /* IVB+ */
1686 };
1687
1688 struct intel_wm_level {
1689         bool enable;
1690         uint32_t pri_val;
1691         uint32_t spr_val;
1692         uint32_t cur_val;
1693         uint32_t fbc_val;
1694 };
1695
1696 struct ilk_wm_values {
1697         uint32_t wm_pipe[3];
1698         uint32_t wm_lp[3];
1699         uint32_t wm_lp_spr[3];
1700         uint32_t wm_linetime[3];
1701         bool enable_fbc_wm;
1702         enum intel_ddb_partitioning partitioning;
1703 };
1704
1705 struct vlv_pipe_wm {
1706         uint16_t plane[I915_MAX_PLANES];
1707 };
1708
1709 struct vlv_sr_wm {
1710         uint16_t plane;
1711         uint16_t cursor;
1712 };
1713
1714 struct vlv_wm_ddl_values {
1715         uint8_t plane[I915_MAX_PLANES];
1716 };
1717
1718 struct vlv_wm_values {
1719         struct vlv_pipe_wm pipe[3];
1720         struct vlv_sr_wm sr;
1721         struct vlv_wm_ddl_values ddl[3];
1722         uint8_t level;
1723         bool cxsr;
1724 };
1725
1726 struct skl_ddb_entry {
1727         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1728 };
1729
1730 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1731 {
1732         return entry->end - entry->start;
1733 }
1734
1735 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1736                                        const struct skl_ddb_entry *e2)
1737 {
1738         if (e1->start == e2->start && e1->end == e2->end)
1739                 return true;
1740
1741         return false;
1742 }
1743
1744 struct skl_ddb_allocation {
1745         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1746         struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1747 };
1748
1749 struct skl_wm_values {
1750         unsigned dirty_pipes;
1751         struct skl_ddb_allocation ddb;
1752 };
1753
1754 struct skl_wm_level {
1755         bool plane_en;
1756         uint16_t plane_res_b;
1757         uint8_t plane_res_l;
1758 };
1759
1760 /*
1761  * This struct helps tracking the state needed for runtime PM, which puts the
1762  * device in PCI D3 state. Notice that when this happens, nothing on the
1763  * graphics device works, even register access, so we don't get interrupts nor
1764  * anything else.
1765  *
1766  * Every piece of our code that needs to actually touch the hardware needs to
1767  * either call intel_runtime_pm_get or call intel_display_power_get with the
1768  * appropriate power domain.
1769  *
1770  * Our driver uses the autosuspend delay feature, which means we'll only really
1771  * suspend if we stay with zero refcount for a certain amount of time. The
1772  * default value is currently very conservative (see intel_runtime_pm_enable), but
1773  * it can be changed with the standard runtime PM files from sysfs.
1774  *
1775  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1776  * goes back to false exactly before we reenable the IRQs. We use this variable
1777  * to check if someone is trying to enable/disable IRQs while they're supposed
1778  * to be disabled. This shouldn't happen and we'll print some error messages in
1779  * case it happens.
1780  *
1781  * For more, read the Documentation/power/runtime_pm.txt.
1782  */
1783 struct i915_runtime_pm {
1784         atomic_t wakeref_count;
1785         bool suspended;
1786         bool irqs_enabled;
1787 };
1788
1789 enum intel_pipe_crc_source {
1790         INTEL_PIPE_CRC_SOURCE_NONE,
1791         INTEL_PIPE_CRC_SOURCE_PLANE1,
1792         INTEL_PIPE_CRC_SOURCE_PLANE2,
1793         INTEL_PIPE_CRC_SOURCE_PF,
1794         INTEL_PIPE_CRC_SOURCE_PIPE,
1795         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1796         INTEL_PIPE_CRC_SOURCE_TV,
1797         INTEL_PIPE_CRC_SOURCE_DP_B,
1798         INTEL_PIPE_CRC_SOURCE_DP_C,
1799         INTEL_PIPE_CRC_SOURCE_DP_D,
1800         INTEL_PIPE_CRC_SOURCE_AUTO,
1801         INTEL_PIPE_CRC_SOURCE_MAX,
1802 };
1803
1804 struct intel_pipe_crc_entry {
1805         uint32_t frame;
1806         uint32_t crc[5];
1807 };
1808
1809 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1810 struct intel_pipe_crc {
1811         spinlock_t lock;
1812         bool opened;            /* exclusive access to the result file */
1813         struct intel_pipe_crc_entry *entries;
1814         enum intel_pipe_crc_source source;
1815         int head, tail;
1816         wait_queue_head_t wq;
1817         int skipped;
1818 };
1819
1820 struct i915_frontbuffer_tracking {
1821         spinlock_t lock;
1822
1823         /*
1824          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1825          * scheduled flips.
1826          */
1827         unsigned busy_bits;
1828         unsigned flip_bits;
1829 };
1830
1831 struct i915_wa_reg {
1832         i915_reg_t addr;
1833         u32 value;
1834         /* bitmask representing WA bits */
1835         u32 mask;
1836 };
1837
1838 /*
1839  * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1840  * allowing it for RCS as we don't foresee any requirement of having
1841  * a whitelist for other engines. When it is really required for
1842  * other engines then the limit need to be increased.
1843  */
1844 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1845
1846 struct i915_workarounds {
1847         struct i915_wa_reg reg[I915_MAX_WA_REGS];
1848         u32 count;
1849         u32 hw_whitelist_count[I915_NUM_ENGINES];
1850 };
1851
1852 struct i915_virtual_gpu {
1853         bool active;
1854 };
1855
1856 /* used in computing the new watermarks state */
1857 struct intel_wm_config {
1858         unsigned int num_pipes_active;
1859         bool sprites_enabled;
1860         bool sprites_scaled;
1861 };
1862
1863 struct i915_oa_format {
1864         u32 format;
1865         int size;
1866 };
1867
1868 struct i915_oa_reg {
1869         i915_reg_t addr;
1870         u32 value;
1871 };
1872
1873 struct i915_perf_stream;
1874
1875 /**
1876  * struct i915_perf_stream_ops - the OPs to support a specific stream type
1877  */
1878 struct i915_perf_stream_ops {
1879         /**
1880          * @enable: Enables the collection of HW samples, either in response to
1881          * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1882          * without `I915_PERF_FLAG_DISABLED`.
1883          */
1884         void (*enable)(struct i915_perf_stream *stream);
1885
1886         /**
1887          * @disable: Disables the collection of HW samples, either in response
1888          * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1889          * the stream.
1890          */
1891         void (*disable)(struct i915_perf_stream *stream);
1892
1893         /**
1894          * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1895          * once there is something ready to read() for the stream
1896          */
1897         void (*poll_wait)(struct i915_perf_stream *stream,
1898                           struct file *file,
1899                           poll_table *wait);
1900
1901         /**
1902          * @wait_unlocked: For handling a blocking read, wait until there is
1903          * something to ready to read() for the stream. E.g. wait on the same
1904          * wait queue that would be passed to poll_wait().
1905          */
1906         int (*wait_unlocked)(struct i915_perf_stream *stream);
1907
1908         /**
1909          * @read: Copy buffered metrics as records to userspace
1910          * **buf**: the userspace, destination buffer
1911          * **count**: the number of bytes to copy, requested by userspace
1912          * **offset**: zero at the start of the read, updated as the read
1913          * proceeds, it represents how many bytes have been copied so far and
1914          * the buffer offset for copying the next record.
1915          *
1916          * Copy as many buffered i915 perf samples and records for this stream
1917          * to userspace as will fit in the given buffer.
1918          *
1919          * Only write complete records; returning -%ENOSPC if there isn't room
1920          * for a complete record.
1921          *
1922          * Return any error condition that results in a short read such as
1923          * -%ENOSPC or -%EFAULT, even though these may be squashed before
1924          * returning to userspace.
1925          */
1926         int (*read)(struct i915_perf_stream *stream,
1927                     char __user *buf,
1928                     size_t count,
1929                     size_t *offset);
1930
1931         /**
1932          * @destroy: Cleanup any stream specific resources.
1933          *
1934          * The stream will always be disabled before this is called.
1935          */
1936         void (*destroy)(struct i915_perf_stream *stream);
1937 };
1938
1939 /**
1940  * struct i915_perf_stream - state for a single open stream FD
1941  */
1942 struct i915_perf_stream {
1943         /**
1944          * @dev_priv: i915 drm device
1945          */
1946         struct drm_i915_private *dev_priv;
1947
1948         /**
1949          * @link: Links the stream into ``&drm_i915_private->streams``
1950          */
1951         struct list_head link;
1952
1953         /**
1954          * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1955          * properties given when opening a stream, representing the contents
1956          * of a single sample as read() by userspace.
1957          */
1958         u32 sample_flags;
1959
1960         /**
1961          * @sample_size: Considering the configured contents of a sample
1962          * combined with the required header size, this is the total size
1963          * of a single sample record.
1964          */
1965         int sample_size;
1966
1967         /**
1968          * @ctx: %NULL if measuring system-wide across all contexts or a
1969          * specific context that is being monitored.
1970          */
1971         struct i915_gem_context *ctx;
1972
1973         /**
1974          * @enabled: Whether the stream is currently enabled, considering
1975          * whether the stream was opened in a disabled state and based
1976          * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1977          */
1978         bool enabled;
1979
1980         /**
1981          * @ops: The callbacks providing the implementation of this specific
1982          * type of configured stream.
1983          */
1984         const struct i915_perf_stream_ops *ops;
1985 };
1986
1987 /**
1988  * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1989  */
1990 struct i915_oa_ops {
1991         /**
1992          * @init_oa_buffer: Resets the head and tail pointers of the
1993          * circular buffer for periodic OA reports.
1994          *
1995          * Called when first opening a stream for OA metrics, but also may be
1996          * called in response to an OA buffer overflow or other error
1997          * condition.
1998          *
1999          * Note it may be necessary to clear the full OA buffer here as part of
2000          * maintaining the invariable that new reports must be written to
2001          * zeroed memory for us to be able to reliable detect if an expected
2002          * report has not yet landed in memory.  (At least on Haswell the OA
2003          * buffer tail pointer is not synchronized with reports being visible
2004          * to the CPU)
2005          */
2006         void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2007
2008         /**
2009          * @enable_metric_set: Applies any MUX configuration to set up the
2010          * Boolean and Custom (B/C) counters that are part of the counter
2011          * reports being sampled. May apply system constraints such as
2012          * disabling EU clock gating as required.
2013          */
2014         int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2015
2016         /**
2017          * @disable_metric_set: Remove system constraints associated with using
2018          * the OA unit.
2019          */
2020         void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2021
2022         /**
2023          * @oa_enable: Enable periodic sampling
2024          */
2025         void (*oa_enable)(struct drm_i915_private *dev_priv);
2026
2027         /**
2028          * @oa_disable: Disable periodic sampling
2029          */
2030         void (*oa_disable)(struct drm_i915_private *dev_priv);
2031
2032         /**
2033          * @read: Copy data from the circular OA buffer into a given userspace
2034          * buffer.
2035          */
2036         int (*read)(struct i915_perf_stream *stream,
2037                     char __user *buf,
2038                     size_t count,
2039                     size_t *offset);
2040
2041         /**
2042          * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2043          *
2044          * This is either called via fops or the poll check hrtimer (atomic
2045          * ctx) without any locks taken.
2046          *
2047          * It's safe to read OA config state here unlocked, assuming that this
2048          * is only called while the stream is enabled, while the global OA
2049          * configuration can't be modified.
2050          *
2051          * Efficiency is more important than avoiding some false positives
2052          * here, which will be handled gracefully - likely resulting in an
2053          * %EAGAIN error for userspace.
2054          */
2055         bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2056 };
2057
2058 struct drm_i915_private {
2059         struct drm_device drm;
2060
2061         struct kmem_cache *objects;
2062         struct kmem_cache *vmas;
2063         struct kmem_cache *requests;
2064         struct kmem_cache *dependencies;
2065
2066         const struct intel_device_info info;
2067
2068         void __iomem *regs;
2069
2070         struct intel_uncore uncore;
2071
2072         struct i915_virtual_gpu vgpu;
2073
2074         struct intel_gvt *gvt;
2075
2076         struct intel_huc huc;
2077         struct intel_guc guc;
2078
2079         struct intel_csr csr;
2080
2081         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2082
2083         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2084          * controller on different i2c buses. */
2085         struct mutex gmbus_mutex;
2086
2087         /**
2088          * Base address of the gmbus and gpio block.
2089          */
2090         uint32_t gpio_mmio_base;
2091
2092         /* MMIO base address for MIPI regs */
2093         uint32_t mipi_mmio_base;
2094
2095         uint32_t psr_mmio_base;
2096
2097         uint32_t pps_mmio_base;
2098
2099         wait_queue_head_t gmbus_wait_queue;
2100
2101         struct pci_dev *bridge_dev;
2102         struct i915_gem_context *kernel_context;
2103         struct intel_engine_cs *engine[I915_NUM_ENGINES];
2104         struct i915_vma *semaphore;
2105
2106         struct drm_dma_handle *status_page_dmah;
2107         struct resource mch_res;
2108
2109         /* protects the irq masks */
2110         spinlock_t irq_lock;
2111
2112         /* protects the mmio flip data */
2113         spinlock_t mmio_flip_lock;
2114
2115         bool display_irqs_enabled;
2116
2117         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2118         struct pm_qos_request pm_qos;
2119
2120         /* Sideband mailbox protection */
2121         struct mutex sb_lock;
2122
2123         /** Cached value of IMR to avoid reads in updating the bitfield */
2124         union {
2125                 u32 irq_mask;
2126                 u32 de_irq_mask[I915_MAX_PIPES];
2127         };
2128         u32 gt_irq_mask;
2129         u32 pm_imr;
2130         u32 pm_ier;
2131         u32 pm_rps_events;
2132         u32 pm_guc_events;
2133         u32 pipestat_irq_mask[I915_MAX_PIPES];
2134
2135         struct i915_hotplug hotplug;
2136         struct intel_fbc fbc;
2137         struct i915_drrs drrs;
2138         struct intel_opregion opregion;
2139         struct intel_vbt_data vbt;
2140
2141         bool preserve_bios_swizzle;
2142
2143         /* overlay */
2144         struct intel_overlay *overlay;
2145
2146         /* backlight registers and fields in struct intel_panel */
2147         struct mutex backlight_lock;
2148
2149         /* LVDS info */
2150         bool no_aux_handshake;
2151
2152         /* protects panel power sequencer state */
2153         struct mutex pps_mutex;
2154
2155         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2156         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2157
2158         unsigned int fsb_freq, mem_freq, is_ddr3;
2159         unsigned int skl_preferred_vco_freq;
2160         unsigned int cdclk_freq, max_cdclk_freq;
2161
2162         /*
2163          * For reading holding any crtc lock is sufficient,
2164          * for writing must hold all of them.
2165          */
2166         unsigned int atomic_cdclk_freq;
2167
2168         unsigned int max_dotclk_freq;
2169         unsigned int rawclk_freq;
2170         unsigned int hpll_freq;
2171         unsigned int czclk_freq;
2172
2173         struct {
2174                 unsigned int vco, ref;
2175         } cdclk_pll;
2176
2177         /**
2178          * wq - Driver workqueue for GEM.
2179          *
2180          * NOTE: Work items scheduled here are not allowed to grab any modeset
2181          * locks, for otherwise the flushing done in the pageflip code will
2182          * result in deadlocks.
2183          */
2184         struct workqueue_struct *wq;
2185
2186         /* Display functions */
2187         struct drm_i915_display_funcs display;
2188
2189         /* PCH chipset type */
2190         enum intel_pch pch_type;
2191         unsigned short pch_id;
2192
2193         unsigned long quirks;
2194
2195         enum modeset_restore modeset_restore;
2196         struct mutex modeset_restore_lock;
2197         struct drm_atomic_state *modeset_restore_state;
2198         struct drm_modeset_acquire_ctx reset_ctx;
2199
2200         struct list_head vm_list; /* Global list of all address spaces */
2201         struct i915_ggtt ggtt; /* VM representing the global address space */
2202
2203         struct i915_gem_mm mm;
2204         DECLARE_HASHTABLE(mm_structs, 7);
2205         struct mutex mm_lock;
2206
2207         /* The hw wants to have a stable context identifier for the lifetime
2208          * of the context (for OA, PASID, faults, etc). This is limited
2209          * in execlists to 21 bits.
2210          */
2211         struct ida context_hw_ida;
2212 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2213
2214         /* Kernel Modesetting */
2215
2216         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2217         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2218         wait_queue_head_t pending_flip_queue;
2219
2220 #ifdef CONFIG_DEBUG_FS
2221         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2222 #endif
2223
2224         /* dpll and cdclk state is protected by connection_mutex */
2225         int num_shared_dpll;
2226         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2227         const struct intel_dpll_mgr *dpll_mgr;
2228
2229         /*
2230          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2231          * Must be global rather than per dpll, because on some platforms
2232          * plls share registers.
2233          */
2234         struct mutex dpll_lock;
2235
2236         unsigned int active_crtcs;
2237         unsigned int min_pixclk[I915_MAX_PIPES];
2238
2239         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2240
2241         struct i915_workarounds workarounds;
2242
2243         struct i915_frontbuffer_tracking fb_tracking;
2244
2245         struct intel_atomic_helper {
2246                 struct llist_head free_list;
2247                 struct work_struct free_work;
2248         } atomic_helper;
2249
2250         u16 orig_clock;
2251
2252         bool mchbar_need_disable;
2253
2254         struct intel_l3_parity l3_parity;
2255
2256         /* Cannot be determined by PCIID. You must always read a register. */
2257         u32 edram_cap;
2258
2259         /* gen6+ rps state */
2260         struct intel_gen6_power_mgmt rps;
2261
2262         /* ilk-only ips/rps state. Everything in here is protected by the global
2263          * mchdev_lock in intel_pm.c */
2264         struct intel_ilk_power_mgmt ips;
2265
2266         struct i915_power_domains power_domains;
2267
2268         struct i915_psr psr;
2269
2270         struct i915_gpu_error gpu_error;
2271
2272         struct drm_i915_gem_object *vlv_pctx;
2273
2274 #ifdef CONFIG_DRM_FBDEV_EMULATION
2275         /* list of fbdev register on this device */
2276         struct intel_fbdev *fbdev;
2277         struct work_struct fbdev_suspend_work;
2278 #endif
2279
2280         struct drm_property *broadcast_rgb_property;
2281         struct drm_property *force_audio_property;
2282
2283         /* hda/i915 audio component */
2284         struct i915_audio_component *audio_component;
2285         bool audio_component_registered;
2286         /**
2287          * av_mutex - mutex for audio/video sync
2288          *
2289          */
2290         struct mutex av_mutex;
2291
2292         uint32_t hw_context_size;
2293         struct list_head context_list;
2294
2295         u32 fdi_rx_config;
2296
2297         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2298         u32 chv_phy_control;
2299         /*
2300          * Shadows for CHV DPLL_MD regs to keep the state
2301          * checker somewhat working in the presence hardware
2302          * crappiness (can't read out DPLL_MD for pipes B & C).
2303          */
2304         u32 chv_dpll_md[I915_MAX_PIPES];
2305         u32 bxt_phy_grc;
2306
2307         u32 suspend_count;
2308         bool suspended_to_idle;
2309         struct i915_suspend_saved_registers regfile;
2310         struct vlv_s0ix_state vlv_s0ix_state;
2311
2312         enum {
2313                 I915_SAGV_UNKNOWN = 0,
2314                 I915_SAGV_DISABLED,
2315                 I915_SAGV_ENABLED,
2316                 I915_SAGV_NOT_CONTROLLED
2317         } sagv_status;
2318
2319         struct {
2320                 /* protects DSPARB registers on pre-g4x/vlv/chv */
2321                 spinlock_t dsparb_lock;
2322
2323                 /*
2324                  * Raw watermark latency values:
2325                  * in 0.1us units for WM0,
2326                  * in 0.5us units for WM1+.
2327                  */
2328                 /* primary */
2329                 uint16_t pri_latency[5];
2330                 /* sprite */
2331                 uint16_t spr_latency[5];
2332                 /* cursor */
2333                 uint16_t cur_latency[5];
2334                 /*
2335                  * Raw watermark memory latency values
2336                  * for SKL for all 8 levels
2337                  * in 1us units.
2338                  */
2339                 uint16_t skl_latency[8];
2340
2341                 /* current hardware state */
2342                 union {
2343                         struct ilk_wm_values hw;
2344                         struct skl_wm_values skl_hw;
2345                         struct vlv_wm_values vlv;
2346                 };
2347
2348                 uint8_t max_level;
2349
2350                 /*
2351                  * Should be held around atomic WM register writing; also
2352                  * protects * intel_crtc->wm.active and
2353                  * cstate->wm.need_postvbl_update.
2354                  */
2355                 struct mutex wm_mutex;
2356
2357                 /*
2358                  * Set during HW readout of watermarks/DDB.  Some platforms
2359                  * need to know when we're still using BIOS-provided values
2360                  * (which we don't fully trust).
2361                  */
2362                 bool distrust_bios_wm;
2363         } wm;
2364
2365         struct i915_runtime_pm pm;
2366
2367         struct {
2368                 bool initialized;
2369
2370                 struct kobject *metrics_kobj;
2371                 struct ctl_table_header *sysctl_header;
2372
2373                 struct mutex lock;
2374                 struct list_head streams;
2375
2376                 spinlock_t hook_lock;
2377
2378                 struct {
2379                         struct i915_perf_stream *exclusive_stream;
2380
2381                         u32 specific_ctx_id;
2382
2383                         struct hrtimer poll_check_timer;
2384                         wait_queue_head_t poll_wq;
2385                         bool pollin;
2386
2387                         bool periodic;
2388                         int period_exponent;
2389                         int timestamp_frequency;
2390
2391                         int tail_margin;
2392
2393                         int metrics_set;
2394
2395                         const struct i915_oa_reg *mux_regs;
2396                         int mux_regs_len;
2397                         const struct i915_oa_reg *b_counter_regs;
2398                         int b_counter_regs_len;
2399
2400                         struct {
2401                                 struct i915_vma *vma;
2402                                 u8 *vaddr;
2403                                 int format;
2404                                 int format_size;
2405                         } oa_buffer;
2406
2407                         u32 gen7_latched_oastatus1;
2408
2409                         struct i915_oa_ops ops;
2410                         const struct i915_oa_format *oa_formats;
2411                         int n_builtin_sets;
2412                 } oa;
2413         } perf;
2414
2415         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2416         struct {
2417                 void (*resume)(struct drm_i915_private *);
2418                 void (*cleanup_engine)(struct intel_engine_cs *engine);
2419
2420                 struct list_head timelines;
2421                 struct i915_gem_timeline global_timeline;
2422                 u32 active_requests;
2423
2424                 /**
2425                  * Is the GPU currently considered idle, or busy executing
2426                  * userspace requests? Whilst idle, we allow runtime power
2427                  * management to power down the hardware and display clocks.
2428                  * In order to reduce the effect on performance, there
2429                  * is a slight delay before we do so.
2430                  */
2431                 bool awake;
2432
2433                 /**
2434                  * We leave the user IRQ off as much as possible,
2435                  * but this means that requests will finish and never
2436                  * be retired once the system goes idle. Set a timer to
2437                  * fire periodically while the ring is running. When it
2438                  * fires, go retire requests.
2439                  */
2440                 struct delayed_work retire_work;
2441
2442                 /**
2443                  * When we detect an idle GPU, we want to turn on
2444                  * powersaving features. So once we see that there
2445                  * are no more requests outstanding and no more
2446                  * arrive within a small period of time, we fire
2447                  * off the idle_work.
2448                  */
2449                 struct delayed_work idle_work;
2450
2451                 ktime_t last_init_time;
2452         } gt;
2453
2454         /* perform PHY state sanity checks? */
2455         bool chv_phy_assert[2];
2456
2457         bool ipc_enabled;
2458
2459         /* Used to save the pipe-to-encoder mapping for audio */
2460         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2461
2462         /* necessary resource sharing with HDMI LPE audio driver. */
2463         struct {
2464                 struct platform_device *platdev;
2465                 int     irq;
2466         } lpe_audio;
2467
2468         /*
2469          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2470          * will be rejected. Instead look for a better place.
2471          */
2472 };
2473
2474 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2475 {
2476         return container_of(dev, struct drm_i915_private, drm);
2477 }
2478
2479 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2480 {
2481         return to_i915(dev_get_drvdata(kdev));
2482 }
2483
2484 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2485 {
2486         return container_of(guc, struct drm_i915_private, guc);
2487 }
2488
2489 /* Simple iterator over all initialised engines */
2490 #define for_each_engine(engine__, dev_priv__, id__) \
2491         for ((id__) = 0; \
2492              (id__) < I915_NUM_ENGINES; \
2493              (id__)++) \
2494                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2495
2496 #define __mask_next_bit(mask) ({                                        \
2497         int __idx = ffs(mask) - 1;                                      \
2498         mask &= ~BIT(__idx);                                            \
2499         __idx;                                                          \
2500 })
2501
2502 /* Iterator over subset of engines selected by mask */
2503 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2504         for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;        \
2505              tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2506
2507 enum hdmi_force_audio {
2508         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
2509         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
2510         HDMI_AUDIO_AUTO,                /* trust EDID */
2511         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
2512 };
2513
2514 #define I915_GTT_OFFSET_NONE ((u32)-1)
2515
2516 /*
2517  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2518  * considered to be the frontbuffer for the given plane interface-wise. This
2519  * doesn't mean that the hw necessarily already scans it out, but that any
2520  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2521  *
2522  * We have one bit per pipe and per scanout plane type.
2523  */
2524 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2525 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2526 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2527         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2528 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2529         (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2530 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2531         (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2532 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2533         (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2534 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2535         (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2536
2537 /*
2538  * Optimised SGL iterator for GEM objects
2539  */
2540 static __always_inline struct sgt_iter {
2541         struct scatterlist *sgp;
2542         union {
2543                 unsigned long pfn;
2544                 dma_addr_t dma;
2545         };
2546         unsigned int curr;
2547         unsigned int max;
2548 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2549         struct sgt_iter s = { .sgp = sgl };
2550
2551         if (s.sgp) {
2552                 s.max = s.curr = s.sgp->offset;
2553                 s.max += s.sgp->length;
2554                 if (dma)
2555                         s.dma = sg_dma_address(s.sgp);
2556                 else
2557                         s.pfn = page_to_pfn(sg_page(s.sgp));
2558         }
2559
2560         return s;
2561 }
2562
2563 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2564 {
2565         ++sg;
2566         if (unlikely(sg_is_chain(sg)))
2567                 sg = sg_chain_ptr(sg);
2568         return sg;
2569 }
2570
2571 /**
2572  * __sg_next - return the next scatterlist entry in a list
2573  * @sg:         The current sg entry
2574  *
2575  * Description:
2576  *   If the entry is the last, return NULL; otherwise, step to the next
2577  *   element in the array (@sg@+1). If that's a chain pointer, follow it;
2578  *   otherwise just return the pointer to the current element.
2579  **/
2580 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2581 {
2582 #ifdef CONFIG_DEBUG_SG
2583         BUG_ON(sg->sg_magic != SG_MAGIC);
2584 #endif
2585         return sg_is_last(sg) ? NULL : ____sg_next(sg);
2586 }
2587
2588 /**
2589  * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2590  * @__dmap:     DMA address (output)
2591  * @__iter:     'struct sgt_iter' (iterator state, internal)
2592  * @__sgt:      sg_table to iterate over (input)
2593  */
2594 #define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
2595         for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
2596              ((__dmap) = (__iter).dma + (__iter).curr);                 \
2597              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2598              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2599
2600 /**
2601  * for_each_sgt_page - iterate over the pages of the given sg_table
2602  * @__pp:       page pointer (output)
2603  * @__iter:     'struct sgt_iter' (iterator state, internal)
2604  * @__sgt:      sg_table to iterate over (input)
2605  */
2606 #define for_each_sgt_page(__pp, __iter, __sgt)                          \
2607         for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
2608              ((__pp) = (__iter).pfn == 0 ? NULL :                       \
2609               pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2610              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2611              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2612
2613 static inline const struct intel_device_info *
2614 intel_info(const struct drm_i915_private *dev_priv)
2615 {
2616         return &dev_priv->info;
2617 }
2618
2619 #define INTEL_INFO(dev_priv)    intel_info((dev_priv))
2620
2621 #define INTEL_GEN(dev_priv)     ((dev_priv)->info.gen)
2622 #define INTEL_DEVID(dev_priv)   ((dev_priv)->info.device_id)
2623
2624 #define REVID_FOREVER           0xff
2625 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
2626
2627 #define GEN_FOREVER (0)
2628 /*
2629  * Returns true if Gen is in inclusive range [Start, End].
2630  *
2631  * Use GEN_FOREVER for unbound start and or end.
2632  */
2633 #define IS_GEN(dev_priv, s, e) ({ \
2634         unsigned int __s = (s), __e = (e); \
2635         BUILD_BUG_ON(!__builtin_constant_p(s)); \
2636         BUILD_BUG_ON(!__builtin_constant_p(e)); \
2637         if ((__s) != GEN_FOREVER) \
2638                 __s = (s) - 1; \
2639         if ((__e) == GEN_FOREVER) \
2640                 __e = BITS_PER_LONG - 1; \
2641         else \
2642                 __e = (e) - 1; \
2643         !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2644 })
2645
2646 /*
2647  * Return true if revision is in range [since,until] inclusive.
2648  *
2649  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2650  */
2651 #define IS_REVID(p, since, until) \
2652         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2653
2654 #define IS_I830(dev_priv)       ((dev_priv)->info.platform == INTEL_I830)
2655 #define IS_I845G(dev_priv)      ((dev_priv)->info.platform == INTEL_I845G)
2656 #define IS_I85X(dev_priv)       ((dev_priv)->info.platform == INTEL_I85X)
2657 #define IS_I865G(dev_priv)      ((dev_priv)->info.platform == INTEL_I865G)
2658 #define IS_I915G(dev_priv)      ((dev_priv)->info.platform == INTEL_I915G)
2659 #define IS_I915GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I915GM)
2660 #define IS_I945G(dev_priv)      ((dev_priv)->info.platform == INTEL_I945G)
2661 #define IS_I945GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I945GM)
2662 #define IS_I965G(dev_priv)      ((dev_priv)->info.platform == INTEL_I965G)
2663 #define IS_I965GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I965GM)
2664 #define IS_G45(dev_priv)        ((dev_priv)->info.platform == INTEL_G45)
2665 #define IS_GM45(dev_priv)       ((dev_priv)->info.platform == INTEL_GM45)
2666 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
2667 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2668 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2669 #define IS_PINEVIEW(dev_priv)   ((dev_priv)->info.platform == INTEL_PINEVIEW)
2670 #define IS_G33(dev_priv)        ((dev_priv)->info.platform == INTEL_G33)
2671 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2672 #define IS_IVYBRIDGE(dev_priv)  ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2673 #define IS_IVB_GT1(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0156 || \
2674                                  INTEL_DEVID(dev_priv) == 0x0152 || \
2675                                  INTEL_DEVID(dev_priv) == 0x015a)
2676 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2677 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2678 #define IS_HASWELL(dev_priv)    ((dev_priv)->info.platform == INTEL_HASWELL)
2679 #define IS_BROADWELL(dev_priv)  ((dev_priv)->info.platform == INTEL_BROADWELL)
2680 #define IS_SKYLAKE(dev_priv)    ((dev_priv)->info.platform == INTEL_SKYLAKE)
2681 #define IS_BROXTON(dev_priv)    ((dev_priv)->info.platform == INTEL_BROXTON)
2682 #define IS_KABYLAKE(dev_priv)   ((dev_priv)->info.platform == INTEL_KABYLAKE)
2683 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2684 #define IS_MOBILE(dev_priv)     ((dev_priv)->info.is_mobile)
2685 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2686                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2687 #define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
2688                                  ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||       \
2689                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||        \
2690                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2691 /* ULX machines are also considered ULT. */
2692 #define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
2693                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2694 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
2695                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2696 #define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
2697                                  (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2698 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
2699                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2700 /* ULX machines are also considered ULT. */
2701 #define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
2702                                  INTEL_DEVID(dev_priv) == 0x0A1E)
2703 #define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
2704                                  INTEL_DEVID(dev_priv) == 0x1913 || \
2705                                  INTEL_DEVID(dev_priv) == 0x1916 || \
2706                                  INTEL_DEVID(dev_priv) == 0x1921 || \
2707                                  INTEL_DEVID(dev_priv) == 0x1926)
2708 #define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
2709                                  INTEL_DEVID(dev_priv) == 0x1915 || \
2710                                  INTEL_DEVID(dev_priv) == 0x191E)
2711 #define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
2712                                  INTEL_DEVID(dev_priv) == 0x5913 || \
2713                                  INTEL_DEVID(dev_priv) == 0x5916 || \
2714                                  INTEL_DEVID(dev_priv) == 0x5921 || \
2715                                  INTEL_DEVID(dev_priv) == 0x5926)
2716 #define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
2717                                  INTEL_DEVID(dev_priv) == 0x5915 || \
2718                                  INTEL_DEVID(dev_priv) == 0x591E)
2719 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2720                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2721 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2722                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2723
2724 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2725
2726 #define SKL_REVID_A0            0x0
2727 #define SKL_REVID_B0            0x1
2728 #define SKL_REVID_C0            0x2
2729 #define SKL_REVID_D0            0x3
2730 #define SKL_REVID_E0            0x4
2731 #define SKL_REVID_F0            0x5
2732 #define SKL_REVID_G0            0x6
2733 #define SKL_REVID_H0            0x7
2734
2735 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2736
2737 #define BXT_REVID_A0            0x0
2738 #define BXT_REVID_A1            0x1
2739 #define BXT_REVID_B0            0x3
2740 #define BXT_REVID_B_LAST        0x8
2741 #define BXT_REVID_C0            0x9
2742
2743 #define IS_BXT_REVID(dev_priv, since, until) \
2744         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2745
2746 #define KBL_REVID_A0            0x0
2747 #define KBL_REVID_B0            0x1
2748 #define KBL_REVID_C0            0x2
2749 #define KBL_REVID_D0            0x3
2750 #define KBL_REVID_E0            0x4
2751
2752 #define IS_KBL_REVID(dev_priv, since, until) \
2753         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2754
2755 /*
2756  * The genX designation typically refers to the render engine, so render
2757  * capability related checks should use IS_GEN, while display and other checks
2758  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2759  * chips, etc.).
2760  */
2761 #define IS_GEN2(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(1)))
2762 #define IS_GEN3(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(2)))
2763 #define IS_GEN4(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(3)))
2764 #define IS_GEN5(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(4)))
2765 #define IS_GEN6(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(5)))
2766 #define IS_GEN7(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(6)))
2767 #define IS_GEN8(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(7)))
2768 #define IS_GEN9(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(8)))
2769
2770 #define IS_GEN9_LP(dev_priv)    (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2771 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2772
2773 #define ENGINE_MASK(id) BIT(id)
2774 #define RENDER_RING     ENGINE_MASK(RCS)
2775 #define BSD_RING        ENGINE_MASK(VCS)
2776 #define BLT_RING        ENGINE_MASK(BCS)
2777 #define VEBOX_RING      ENGINE_MASK(VECS)
2778 #define BSD2_RING       ENGINE_MASK(VCS2)
2779 #define ALL_ENGINES     (~0)
2780
2781 #define HAS_ENGINE(dev_priv, id) \
2782         (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2783
2784 #define HAS_BSD(dev_priv)       HAS_ENGINE(dev_priv, VCS)
2785 #define HAS_BSD2(dev_priv)      HAS_ENGINE(dev_priv, VCS2)
2786 #define HAS_BLT(dev_priv)       HAS_ENGINE(dev_priv, BCS)
2787 #define HAS_VEBOX(dev_priv)     HAS_ENGINE(dev_priv, VECS)
2788
2789 #define HAS_LLC(dev_priv)       ((dev_priv)->info.has_llc)
2790 #define HAS_SNOOP(dev_priv)     ((dev_priv)->info.has_snoop)
2791 #define HAS_EDRAM(dev_priv)     (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2792 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
2793                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2794
2795 #define HWS_NEEDS_PHYSICAL(dev_priv)    ((dev_priv)->info.hws_needs_physical)
2796
2797 #define HAS_HW_CONTEXTS(dev_priv)           ((dev_priv)->info.has_hw_contexts)
2798 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2799                 ((dev_priv)->info.has_logical_ring_contexts)
2800 #define USES_PPGTT(dev_priv)            (i915.enable_ppgtt)
2801 #define USES_FULL_PPGTT(dev_priv)       (i915.enable_ppgtt >= 2)
2802 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2803
2804 #define HAS_OVERLAY(dev_priv)            ((dev_priv)->info.has_overlay)
2805 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2806                 ((dev_priv)->info.overlay_needs_physical)
2807
2808 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2809 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
2810
2811 /* WaRsDisableCoarsePowerGating:skl,bxt */
2812 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2813         (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2814          IS_SKL_GT3(dev_priv) || \
2815          IS_SKL_GT4(dev_priv))
2816
2817 /*
2818  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2819  * even when in MSI mode. This results in spurious interrupt warnings if the
2820  * legacy irq no. is shared with another device. The kernel then disables that
2821  * interrupt source and so prevents the other device from working properly.
2822  */
2823 #define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
2824 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2825
2826 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2827  * rows, which changed the alignment requirements and fence programming.
2828  */
2829 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2830                                          !(IS_I915G(dev_priv) || \
2831                                          IS_I915GM(dev_priv)))
2832 #define SUPPORTS_TV(dev_priv)           ((dev_priv)->info.supports_tv)
2833 #define I915_HAS_HOTPLUG(dev_priv)      ((dev_priv)->info.has_hotplug)
2834
2835 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
2836 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2837 #define HAS_FBC(dev_priv)       ((dev_priv)->info.has_fbc)
2838
2839 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2840
2841 #define HAS_DP_MST(dev_priv)    ((dev_priv)->info.has_dp_mst)
2842
2843 #define HAS_DDI(dev_priv)                ((dev_priv)->info.has_ddi)
2844 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2845 #define HAS_PSR(dev_priv)                ((dev_priv)->info.has_psr)
2846 #define HAS_RC6(dev_priv)                ((dev_priv)->info.has_rc6)
2847 #define HAS_RC6p(dev_priv)               ((dev_priv)->info.has_rc6p)
2848
2849 #define HAS_CSR(dev_priv)       ((dev_priv)->info.has_csr)
2850
2851 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2852 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2853
2854 /*
2855  * For now, anything with a GuC requires uCode loading, and then supports
2856  * command submission once loaded. But these are logically independent
2857  * properties, so we have separate macros to test them.
2858  */
2859 #define HAS_GUC(dev_priv)       ((dev_priv)->info.has_guc)
2860 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2861 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2862 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2863
2864 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2865
2866 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2867
2868 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
2869 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2870 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2871 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2872 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2873 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2874 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2875 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2876 #define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA200
2877 #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2878 #define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
2879 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2880
2881 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2882 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2883 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2884 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2885 #define HAS_PCH_LPT_LP(dev_priv) \
2886         ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2887 #define HAS_PCH_LPT_H(dev_priv) \
2888         ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2889 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2890 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2891 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2892 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2893
2894 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2895
2896 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2897
2898 /* DPF == dynamic parity feature */
2899 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2900 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2901                                  2 : HAS_L3_DPF(dev_priv))
2902
2903 #define GT_FREQUENCY_MULTIPLIER 50
2904 #define GEN9_FREQ_SCALER 3
2905
2906 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2907
2908 #include "i915_trace.h"
2909
2910 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2911 {
2912 #ifdef CONFIG_INTEL_IOMMU
2913         if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2914                 return true;
2915 #endif
2916         return false;
2917 }
2918
2919 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2920                                 int enable_ppgtt);
2921
2922 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2923
2924 /* i915_drv.c */
2925 void __printf(3, 4)
2926 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2927               const char *fmt, ...);
2928
2929 #define i915_report_error(dev_priv, fmt, ...)                              \
2930         __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2931
2932 #ifdef CONFIG_COMPAT
2933 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2934                               unsigned long arg);
2935 #else
2936 #define i915_compat_ioctl NULL
2937 #endif
2938 extern const struct dev_pm_ops i915_pm_ops;
2939
2940 extern int i915_driver_load(struct pci_dev *pdev,
2941                             const struct pci_device_id *ent);
2942 extern void i915_driver_unload(struct drm_device *dev);
2943 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2944 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2945 extern void i915_reset(struct drm_i915_private *dev_priv);
2946 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2947 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2948 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2949 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2950 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2951 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2952 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2953 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2954
2955 /* intel_hotplug.c */
2956 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2957                            u32 pin_mask, u32 long_mask);
2958 void intel_hpd_init(struct drm_i915_private *dev_priv);
2959 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2960 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2961 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2962 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2963 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2964
2965 /* i915_irq.c */
2966 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2967 {
2968         unsigned long delay;
2969
2970         if (unlikely(!i915.enable_hangcheck))
2971                 return;
2972
2973         /* Don't continually defer the hangcheck so that it is always run at
2974          * least once after work has been scheduled on any ring. Otherwise,
2975          * we will ignore a hung ring if a second ring is kept busy.
2976          */
2977
2978         delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2979         queue_delayed_work(system_long_wq,
2980                            &dev_priv->gpu_error.hangcheck_work, delay);
2981 }
2982
2983 __printf(3, 4)
2984 void i915_handle_error(struct drm_i915_private *dev_priv,
2985                        u32 engine_mask,
2986                        const char *fmt, ...);
2987
2988 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2989 int intel_irq_install(struct drm_i915_private *dev_priv);
2990 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2991
2992 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2993 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2994                                         bool restore_forcewake);
2995 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2996 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2997 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2998 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2999 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3000                                          bool restore);
3001 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3002 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3003                                 enum forcewake_domains domains);
3004 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3005                                 enum forcewake_domains domains);
3006 /* Like above but the caller must manage the uncore.lock itself.
3007  * Must be used with I915_READ_FW and friends.
3008  */
3009 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3010                                         enum forcewake_domains domains);
3011 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3012                                         enum forcewake_domains domains);
3013 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3014
3015 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3016
3017 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3018                             i915_reg_t reg,
3019                             const u32 mask,
3020                             const u32 value,
3021                             const unsigned long timeout_ms);
3022 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3023                                i915_reg_t reg,
3024                                const u32 mask,
3025                                const u32 value,
3026                                const unsigned long timeout_ms);
3027
3028 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3029 {
3030         return dev_priv->gvt;
3031 }
3032
3033 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3034 {
3035         return dev_priv->vgpu.active;
3036 }
3037
3038 void
3039 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3040                      u32 status_mask);
3041
3042 void
3043 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3044                       u32 status_mask);
3045
3046 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3047 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3048 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3049                                    uint32_t mask,
3050                                    uint32_t bits);
3051 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3052                             uint32_t interrupt_mask,
3053                             uint32_t enabled_irq_mask);
3054 static inline void
3055 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3056 {
3057         ilk_update_display_irq(dev_priv, bits, bits);
3058 }
3059 static inline void
3060 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3061 {
3062         ilk_update_display_irq(dev_priv, bits, 0);
3063 }
3064 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3065                          enum pipe pipe,
3066                          uint32_t interrupt_mask,
3067                          uint32_t enabled_irq_mask);
3068 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3069                                        enum pipe pipe, uint32_t bits)
3070 {
3071         bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3072 }
3073 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3074                                         enum pipe pipe, uint32_t bits)
3075 {
3076         bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3077 }
3078 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3079                                   uint32_t interrupt_mask,
3080                                   uint32_t enabled_irq_mask);
3081 static inline void
3082 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3083 {
3084         ibx_display_interrupt_update(dev_priv, bits, bits);
3085 }
3086 static inline void
3087 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3088 {
3089         ibx_display_interrupt_update(dev_priv, bits, 0);
3090 }
3091
3092 /* i915_gem.c */
3093 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3094                           struct drm_file *file_priv);
3095 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3096                          struct drm_file *file_priv);
3097 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3098                           struct drm_file *file_priv);
3099 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3100                         struct drm_file *file_priv);
3101 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3102                         struct drm_file *file_priv);
3103 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3104                               struct drm_file *file_priv);
3105 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3106                              struct drm_file *file_priv);
3107 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3108                         struct drm_file *file_priv);
3109 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3110                          struct drm_file *file_priv);
3111 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3112                         struct drm_file *file_priv);
3113 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3114                                struct drm_file *file);
3115 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3116                                struct drm_file *file);
3117 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3118                             struct drm_file *file_priv);
3119 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3120                            struct drm_file *file_priv);
3121 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3122                               struct drm_file *file_priv);
3123 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3124                               struct drm_file *file_priv);
3125 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3126 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3127                            struct drm_file *file);
3128 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3129                                 struct drm_file *file_priv);
3130 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3131                         struct drm_file *file_priv);
3132 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3133 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3134 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3135 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3136 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3137
3138 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3139 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3140 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3141                          const struct drm_i915_gem_object_ops *ops);
3142 struct drm_i915_gem_object *
3143 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3144 struct drm_i915_gem_object *
3145 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3146                                  const void *data, size_t size);
3147 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3148 void i915_gem_free_object(struct drm_gem_object *obj);
3149
3150 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3151 {
3152         /* A single pass should suffice to release all the freed objects (along
3153          * most call paths) , but be a little more paranoid in that freeing
3154          * the objects does take a little amount of time, during which the rcu
3155          * callbacks could have added new objects into the freed list, and
3156          * armed the work again.
3157          */
3158         do {
3159                 rcu_barrier();
3160         } while (flush_work(&i915->mm.free_work));
3161 }
3162
3163 struct i915_vma * __must_check
3164 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3165                          const struct i915_ggtt_view *view,
3166                          u64 size,
3167                          u64 alignment,
3168                          u64 flags);
3169
3170 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3171 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3172
3173 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3174
3175 static inline int __sg_page_count(const struct scatterlist *sg)
3176 {
3177         return sg->length >> PAGE_SHIFT;
3178 }
3179
3180 struct scatterlist *
3181 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3182                        unsigned int n, unsigned int *offset);
3183
3184 struct page *
3185 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3186                          unsigned int n);
3187
3188 struct page *
3189 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3190                                unsigned int n);
3191
3192 dma_addr_t
3193 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3194                                 unsigned long n);
3195
3196 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3197                                  struct sg_table *pages);
3198 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3199
3200 static inline int __must_check
3201 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3202 {
3203         might_lock(&obj->mm.lock);
3204
3205         if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3206                 return 0;
3207
3208         return __i915_gem_object_get_pages(obj);
3209 }
3210
3211 static inline void
3212 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3213 {
3214         GEM_BUG_ON(!obj->mm.pages);
3215
3216         atomic_inc(&obj->mm.pages_pin_count);
3217 }
3218
3219 static inline bool
3220 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3221 {
3222         return atomic_read(&obj->mm.pages_pin_count);
3223 }
3224
3225 static inline void
3226 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3227 {
3228         GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3229         GEM_BUG_ON(!obj->mm.pages);
3230
3231         atomic_dec(&obj->mm.pages_pin_count);
3232 }
3233
3234 static inline void
3235 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3236 {
3237         __i915_gem_object_unpin_pages(obj);
3238 }
3239
3240 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3241         I915_MM_NORMAL = 0,
3242         I915_MM_SHRINKER
3243 };
3244
3245 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3246                                  enum i915_mm_subclass subclass);
3247 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3248
3249 enum i915_map_type {
3250         I915_MAP_WB = 0,
3251         I915_MAP_WC,
3252 };
3253
3254 /**
3255  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3256  * @obj: the object to map into kernel address space
3257  * @type: the type of mapping, used to select pgprot_t
3258  *
3259  * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3260  * pages and then returns a contiguous mapping of the backing storage into
3261  * the kernel address space. Based on the @type of mapping, the PTE will be
3262  * set to either WriteBack or WriteCombine (via pgprot_t).
3263  *
3264  * The caller is responsible for calling i915_gem_object_unpin_map() when the
3265  * mapping is no longer required.
3266  *
3267  * Returns the pointer through which to access the mapped object, or an
3268  * ERR_PTR() on error.
3269  */
3270 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3271                                            enum i915_map_type type);
3272
3273 /**
3274  * i915_gem_object_unpin_map - releases an earlier mapping
3275  * @obj: the object to unmap
3276  *
3277  * After pinning the object and mapping its pages, once you are finished
3278  * with your access, call i915_gem_object_unpin_map() to release the pin
3279  * upon the mapping. Once the pin count reaches zero, that mapping may be
3280  * removed.
3281  */
3282 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3283 {
3284         i915_gem_object_unpin_pages(obj);
3285 }
3286
3287 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3288                                     unsigned int *needs_clflush);
3289 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3290                                      unsigned int *needs_clflush);
3291 #define CLFLUSH_BEFORE 0x1
3292 #define CLFLUSH_AFTER 0x2
3293 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3294
3295 static inline void
3296 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3297 {
3298         i915_gem_object_unpin_pages(obj);
3299 }
3300
3301 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3302 void i915_vma_move_to_active(struct i915_vma *vma,
3303                              struct drm_i915_gem_request *req,
3304                              unsigned int flags);
3305 int i915_gem_dumb_create(struct drm_file *file_priv,
3306                          struct drm_device *dev,
3307                          struct drm_mode_create_dumb *args);
3308 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3309                       uint32_t handle, uint64_t *offset);
3310 int i915_gem_mmap_gtt_version(void);
3311
3312 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3313                        struct drm_i915_gem_object *new,
3314                        unsigned frontbuffer_bits);
3315
3316 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3317
3318 struct drm_i915_gem_request *
3319 i915_gem_find_active_request(struct intel_engine_cs *engine);
3320
3321 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3322
3323 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3324 {
3325         return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3326 }
3327
3328 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3329 {
3330         return unlikely(test_bit(I915_WEDGED, &error->flags));
3331 }
3332
3333 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3334 {
3335         return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3336 }
3337
3338 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3339 {
3340         return READ_ONCE(error->reset_count);
3341 }
3342
3343 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3344 void i915_gem_reset(struct drm_i915_private *dev_priv);
3345 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3346 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3347 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3348 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3349 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3350 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3351 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3352 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3353                                         unsigned int flags);
3354 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3355 void i915_gem_resume(struct drm_i915_private *dev_priv);
3356 int i915_gem_fault(struct vm_fault *vmf);
3357 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3358                          unsigned int flags,
3359                          long timeout,
3360                          struct intel_rps_client *rps);
3361 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3362                                   unsigned int flags,
3363                                   int priority);
3364 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3365
3366 int __must_check
3367 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3368                                   bool write);
3369 int __must_check
3370 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3371 struct i915_vma * __must_check
3372 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3373                                      u32 alignment,
3374                                      const struct i915_ggtt_view *view);
3375 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3376 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3377                                 int align);
3378 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3379 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3380
3381 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3382                                     enum i915_cache_level cache_level);
3383
3384 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3385                                 struct dma_buf *dma_buf);
3386
3387 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3388                                 struct drm_gem_object *gem_obj, int flags);
3389
3390 static inline struct i915_hw_ppgtt *
3391 i915_vm_to_ppgtt(struct i915_address_space *vm)
3392 {
3393         return container_of(vm, struct i915_hw_ppgtt, base);
3394 }
3395
3396 /* i915_gem_fence_reg.c */
3397 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3398 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3399
3400 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3401 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3402
3403 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3404 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3405                                        struct sg_table *pages);
3406 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3407                                          struct sg_table *pages);
3408
3409 static inline struct i915_gem_context *
3410 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3411 {
3412         struct i915_gem_context *ctx;
3413
3414         lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3415
3416         ctx = idr_find(&file_priv->context_idr, id);
3417         if (!ctx)
3418                 return ERR_PTR(-ENOENT);
3419
3420         return ctx;
3421 }
3422
3423 static inline struct i915_gem_context *
3424 i915_gem_context_get(struct i915_gem_context *ctx)
3425 {
3426         kref_get(&ctx->ref);
3427         return ctx;
3428 }
3429
3430 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3431 {
3432         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3433         kref_put(&ctx->ref, i915_gem_context_free);
3434 }
3435
3436 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3437 {
3438         struct mutex *lock = &ctx->i915->drm.struct_mutex;
3439
3440         if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3441                 mutex_unlock(lock);
3442 }
3443
3444 static inline struct intel_timeline *
3445 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3446                                  struct intel_engine_cs *engine)
3447 {
3448         struct i915_address_space *vm;
3449
3450         vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3451         return &vm->timeline.engine[engine->id];
3452 }
3453
3454 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3455                          struct drm_file *file);
3456
3457 /* i915_gem_evict.c */
3458 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3459                                           u64 min_size, u64 alignment,
3460                                           unsigned cache_level,
3461                                           u64 start, u64 end,
3462                                           unsigned flags);
3463 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3464                                          struct drm_mm_node *node,
3465                                          unsigned int flags);
3466 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3467
3468 /* belongs in i915_gem_gtt.h */
3469 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3470 {
3471         wmb();
3472         if (INTEL_GEN(dev_priv) < 6)
3473                 intel_gtt_chipset_flush();
3474 }
3475
3476 /* i915_gem_stolen.c */
3477 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3478                                 struct drm_mm_node *node, u64 size,
3479                                 unsigned alignment);
3480 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3481                                          struct drm_mm_node *node, u64 size,
3482                                          unsigned alignment, u64 start,
3483                                          u64 end);
3484 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3485                                  struct drm_mm_node *node);
3486 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3487 void i915_gem_cleanup_stolen(struct drm_device *dev);
3488 struct drm_i915_gem_object *
3489 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3490 struct drm_i915_gem_object *
3491 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3492                                                u32 stolen_offset,
3493                                                u32 gtt_offset,
3494                                                u32 size);
3495
3496 /* i915_gem_internal.c */
3497 struct drm_i915_gem_object *
3498 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3499                                 phys_addr_t size);
3500
3501 /* i915_gem_shrinker.c */
3502 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3503                               unsigned long target,
3504                               unsigned flags);
3505 #define I915_SHRINK_PURGEABLE 0x1
3506 #define I915_SHRINK_UNBOUND 0x2
3507 #define I915_SHRINK_BOUND 0x4
3508 #define I915_SHRINK_ACTIVE 0x8
3509 #define I915_SHRINK_VMAPS 0x10
3510 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3511 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3512 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3513
3514
3515 /* i915_gem_tiling.c */
3516 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3517 {
3518         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3519
3520         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3521                 i915_gem_object_is_tiled(obj);
3522 }
3523
3524 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3525                         unsigned int tiling, unsigned int stride);
3526 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3527                              unsigned int tiling, unsigned int stride);
3528
3529 /* i915_debugfs.c */
3530 #ifdef CONFIG_DEBUG_FS
3531 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3532 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3533 int i915_debugfs_connector_add(struct drm_connector *connector);
3534 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3535 #else
3536 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3537 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3538 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3539 { return 0; }
3540 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3541 #endif
3542
3543 /* i915_gpu_error.c */
3544 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3545
3546 __printf(2, 3)
3547 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3548 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3549                             const struct i915_error_state_file_priv *error);
3550 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3551                               struct drm_i915_private *i915,
3552                               size_t count, loff_t pos);
3553 static inline void i915_error_state_buf_release(
3554         struct drm_i915_error_state_buf *eb)
3555 {
3556         kfree(eb->buf);
3557 }
3558 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3559                               u32 engine_mask,
3560                               const char *error_msg);
3561 void i915_error_state_get(struct drm_device *dev,
3562                           struct i915_error_state_file_priv *error_priv);
3563 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3564 void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3565
3566 #else
3567
3568 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3569                                             u32 engine_mask,
3570                                             const char *error_msg)
3571 {
3572 }
3573
3574 static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3575 {
3576 }
3577
3578 #endif
3579
3580 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3581
3582 /* i915_cmd_parser.c */
3583 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3584 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3585 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3586 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3587                             struct drm_i915_gem_object *batch_obj,
3588                             struct drm_i915_gem_object *shadow_batch_obj,
3589                             u32 batch_start_offset,
3590                             u32 batch_len,
3591                             bool is_master);
3592
3593 /* i915_perf.c */
3594 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3595 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3596 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3597 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3598
3599 /* i915_suspend.c */
3600 extern int i915_save_state(struct drm_i915_private *dev_priv);
3601 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3602
3603 /* i915_sysfs.c */
3604 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3605 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3606
3607 /* intel_lpe_audio.c */
3608 int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3609 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3610 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3611 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3612                             void *eld, int port, int pipe, int tmds_clk_speed,
3613                             bool dp_output, int link_rate);
3614
3615 /* intel_i2c.c */
3616 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3617 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3618 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3619                                      unsigned int pin);
3620
3621 extern struct i2c_adapter *
3622 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3623 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3624 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3625 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3626 {
3627         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3628 }
3629 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3630
3631 /* intel_bios.c */
3632 int intel_bios_init(struct drm_i915_private *dev_priv);
3633 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3634 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3635 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3636 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3637 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3638 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3639 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3640 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3641                                      enum port port);
3642 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3643                                 enum port port);
3644
3645
3646 /* intel_opregion.c */
3647 #ifdef CONFIG_ACPI
3648 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3649 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3650 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3651 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3652 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3653                                          bool enable);
3654 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3655                                          pci_power_t state);
3656 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3657 #else
3658 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3659 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3660 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3661 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3662 {
3663 }
3664 static inline int
3665 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3666 {
3667         return 0;
3668 }
3669 static inline int
3670 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3671 {
3672         return 0;
3673 }
3674 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3675 {
3676         return -ENODEV;
3677 }
3678 #endif
3679
3680 /* intel_acpi.c */
3681 #ifdef CONFIG_ACPI
3682 extern void intel_register_dsm_handler(void);
3683 extern void intel_unregister_dsm_handler(void);
3684 #else
3685 static inline void intel_register_dsm_handler(void) { return; }
3686 static inline void intel_unregister_dsm_handler(void) { return; }
3687 #endif /* CONFIG_ACPI */
3688
3689 /* intel_device_info.c */
3690 static inline struct intel_device_info *
3691 mkwrite_device_info(struct drm_i915_private *dev_priv)
3692 {
3693         return (struct intel_device_info *)&dev_priv->info;
3694 }
3695
3696 const char *intel_platform_name(enum intel_platform platform);
3697 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3698 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3699
3700 /* modesetting */
3701 extern void intel_modeset_init_hw(struct drm_device *dev);
3702 extern int intel_modeset_init(struct drm_device *dev);
3703 extern void intel_modeset_gem_init(struct drm_device *dev);
3704 extern void intel_modeset_cleanup(struct drm_device *dev);
3705 extern int intel_connector_register(struct drm_connector *);
3706 extern void intel_connector_unregister(struct drm_connector *);
3707 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3708                                        bool state);
3709 extern void intel_display_resume(struct drm_device *dev);
3710 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3711 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3712 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3713 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3714 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3715 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3716                                   bool enable);
3717
3718 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3719                         struct drm_file *file);
3720
3721 /* overlay */
3722 extern struct intel_overlay_error_state *
3723 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3724 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3725                                             struct intel_overlay_error_state *error);
3726
3727 extern struct intel_display_error_state *
3728 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3729 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3730                                             struct drm_i915_private *dev_priv,
3731                                             struct intel_display_error_state *error);
3732
3733 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3734 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3735 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3736                       u32 reply_mask, u32 reply, int timeout_base_ms);
3737
3738 /* intel_sideband.c */
3739 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3740 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3741 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3742 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3743 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3744 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3745 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3746 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3747 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3748 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3749 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3750 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3751 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3752 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3753                    enum intel_sbi_destination destination);
3754 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3755                      enum intel_sbi_destination destination);
3756 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3757 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3758
3759 /* intel_dpio_phy.c */
3760 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3761                              enum dpio_phy *phy, enum dpio_channel *ch);
3762 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3763                                   enum port port, u32 margin, u32 scale,
3764                                   u32 enable, u32 deemphasis);
3765 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3766 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3767 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3768                             enum dpio_phy phy);
3769 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3770                               enum dpio_phy phy);
3771 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3772                                              uint8_t lane_count);
3773 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3774                                      uint8_t lane_lat_optim_mask);
3775 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3776
3777 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3778                               u32 deemph_reg_value, u32 margin_reg_value,
3779                               bool uniq_trans_scale);
3780 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3781                               bool reset);
3782 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3783 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3784 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3785 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3786
3787 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3788                               u32 demph_reg_value, u32 preemph_reg_value,
3789                               u32 uniqtranscale_reg_value, u32 tx3_demph);
3790 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3791 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3792 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3793
3794 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3795 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3796
3797 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3798 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3799
3800 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3801 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3802 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3803 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3804
3805 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3806 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3807 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3808 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3809
3810 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3811  * will be implemented using 2 32-bit writes in an arbitrary order with
3812  * an arbitrary delay between them. This can cause the hardware to
3813  * act upon the intermediate value, possibly leading to corruption and
3814  * machine death. For this reason we do not support I915_WRITE64, or
3815  * dev_priv->uncore.funcs.mmio_writeq.
3816  *
3817  * When reading a 64-bit value as two 32-bit values, the delay may cause
3818  * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3819  * occasionally a 64-bit register does not actualy support a full readq
3820  * and must be read using two 32-bit reads.
3821  *
3822  * You have been warned.
3823  */
3824 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3825
3826 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3827         u32 upper, lower, old_upper, loop = 0;                          \
3828         upper = I915_READ(upper_reg);                                   \
3829         do {                                                            \
3830                 old_upper = upper;                                      \
3831                 lower = I915_READ(lower_reg);                           \
3832                 upper = I915_READ(upper_reg);                           \
3833         } while (upper != old_upper && loop++ < 2);                     \
3834         (u64)upper << 32 | lower; })
3835
3836 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3837 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3838
3839 #define __raw_read(x, s) \
3840 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3841                                              i915_reg_t reg) \
3842 { \
3843         return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3844 }
3845
3846 #define __raw_write(x, s) \
3847 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3848                                        i915_reg_t reg, uint##x##_t val) \
3849 { \
3850         write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3851 }
3852 __raw_read(8, b)
3853 __raw_read(16, w)
3854 __raw_read(32, l)
3855 __raw_read(64, q)
3856
3857 __raw_write(8, b)
3858 __raw_write(16, w)
3859 __raw_write(32, l)
3860 __raw_write(64, q)
3861
3862 #undef __raw_read
3863 #undef __raw_write
3864
3865 /* These are untraced mmio-accessors that are only valid to be used inside
3866  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3867  * controlled.
3868  *
3869  * Think twice, and think again, before using these.
3870  *
3871  * As an example, these accessors can possibly be used between:
3872  *
3873  * spin_lock_irq(&dev_priv->uncore.lock);
3874  * intel_uncore_forcewake_get__locked();
3875  *
3876  * and
3877  *
3878  * intel_uncore_forcewake_put__locked();
3879  * spin_unlock_irq(&dev_priv->uncore.lock);
3880  *
3881  *
3882  * Note: some registers may not need forcewake held, so
3883  * intel_uncore_forcewake_{get,put} can be omitted, see
3884  * intel_uncore_forcewake_for_reg().
3885  *
3886  * Certain architectures will die if the same cacheline is concurrently accessed
3887  * by different clients (e.g. on Ivybridge). Access to registers should
3888  * therefore generally be serialised, by either the dev_priv->uncore.lock or
3889  * a more localised lock guarding all access to that bank of registers.
3890  */
3891 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3892 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3893 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3894 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3895
3896 /* "Broadcast RGB" property */
3897 #define INTEL_BROADCAST_RGB_AUTO 0
3898 #define INTEL_BROADCAST_RGB_FULL 1
3899 #define INTEL_BROADCAST_RGB_LIMITED 2
3900
3901 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3902 {
3903         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3904                 return VLV_VGACNTRL;
3905         else if (INTEL_GEN(dev_priv) >= 5)
3906                 return CPU_VGACNTRL;
3907         else
3908                 return VGACNTRL;
3909 }
3910
3911 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3912 {
3913         unsigned long j = msecs_to_jiffies(m);
3914
3915         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3916 }
3917
3918 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3919 {
3920         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3921 }
3922
3923 static inline unsigned long
3924 timespec_to_jiffies_timeout(const struct timespec *value)
3925 {
3926         unsigned long j = timespec_to_jiffies(value);
3927
3928         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3929 }
3930
3931 /*
3932  * If you need to wait X milliseconds between events A and B, but event B
3933  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3934  * when event A happened, then just before event B you call this function and
3935  * pass the timestamp as the first argument, and X as the second argument.
3936  */
3937 static inline void
3938 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3939 {
3940         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3941
3942         /*
3943          * Don't re-read the value of "jiffies" every time since it may change
3944          * behind our back and break the math.
3945          */
3946         tmp_jiffies = jiffies;
3947         target_jiffies = timestamp_jiffies +
3948                          msecs_to_jiffies_timeout(to_wait_ms);
3949
3950         if (time_after(target_jiffies, tmp_jiffies)) {
3951                 remaining_jiffies = target_jiffies - tmp_jiffies;
3952                 while (remaining_jiffies)
3953                         remaining_jiffies =
3954                             schedule_timeout_uninterruptible(remaining_jiffies);
3955         }
3956 }
3957
3958 static inline bool
3959 __i915_request_irq_complete(struct drm_i915_gem_request *req)
3960 {
3961         struct intel_engine_cs *engine = req->engine;
3962
3963         /* Before we do the heavier coherent read of the seqno,
3964          * check the value (hopefully) in the CPU cacheline.
3965          */
3966         if (__i915_gem_request_completed(req))
3967                 return true;
3968
3969         /* Ensure our read of the seqno is coherent so that we
3970          * do not "miss an interrupt" (i.e. if this is the last
3971          * request and the seqno write from the GPU is not visible
3972          * by the time the interrupt fires, we will see that the
3973          * request is incomplete and go back to sleep awaiting
3974          * another interrupt that will never come.)
3975          *
3976          * Strictly, we only need to do this once after an interrupt,
3977          * but it is easier and safer to do it every time the waiter
3978          * is woken.
3979          */
3980         if (engine->irq_seqno_barrier &&
3981             rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3982             cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3983                 struct task_struct *tsk;
3984
3985                 /* The ordering of irq_posted versus applying the barrier
3986                  * is crucial. The clearing of the current irq_posted must
3987                  * be visible before we perform the barrier operation,
3988                  * such that if a subsequent interrupt arrives, irq_posted
3989                  * is reasserted and our task rewoken (which causes us to
3990                  * do another __i915_request_irq_complete() immediately
3991                  * and reapply the barrier). Conversely, if the clear
3992                  * occurs after the barrier, then an interrupt that arrived
3993                  * whilst we waited on the barrier would not trigger a
3994                  * barrier on the next pass, and the read may not see the
3995                  * seqno update.
3996                  */
3997                 engine->irq_seqno_barrier(engine);
3998
3999                 /* If we consume the irq, but we are no longer the bottom-half,
4000                  * the real bottom-half may not have serialised their own
4001                  * seqno check with the irq-barrier (i.e. may have inspected
4002                  * the seqno before we believe it coherent since they see
4003                  * irq_posted == false but we are still running).
4004                  */
4005                 rcu_read_lock();
4006                 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
4007                 if (tsk && tsk != current)
4008                         /* Note that if the bottom-half is changed as we
4009                          * are sending the wake-up, the new bottom-half will
4010                          * be woken by whomever made the change. We only have
4011                          * to worry about when we steal the irq-posted for
4012                          * ourself.
4013                          */
4014                         wake_up_process(tsk);
4015                 rcu_read_unlock();
4016
4017                 if (__i915_gem_request_completed(req))
4018                         return true;
4019         }
4020
4021         return false;
4022 }
4023
4024 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4025 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4026
4027 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4028  * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4029  * perform the operation. To check beforehand, pass in the parameters to
4030  * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4031  * you only need to pass in the minor offsets, page-aligned pointers are
4032  * always valid.
4033  *
4034  * For just checking for SSE4.1, in the foreknowledge that the future use
4035  * will be correctly aligned, just use i915_has_memcpy_from_wc().
4036  */
4037 #define i915_can_memcpy_from_wc(dst, src, len) \
4038         i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4039
4040 #define i915_has_memcpy_from_wc() \
4041         i915_memcpy_from_wc(NULL, NULL, 0)
4042
4043 /* i915_mm.c */
4044 int remap_io_mapping(struct vm_area_struct *vma,
4045                      unsigned long addr, unsigned long pfn, unsigned long size,
4046                      struct io_mapping *iomap);
4047
4048 #endif