drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_vgpu.h"
  53 #include "intel_drv.h"
  54 #include "intel_uc.h"
  55
  56 static struct drm_driver driver;
  57
  58 static unsigned int i915_load_fail_count;
  59
  60 bool __i915_inject_load_failure(const char *func, int line)
  61 {
  62         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  63                 return false;
  64
  65         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  66                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  67                          i915_modparams.inject_load_failure, func, line);
  68                 return true;
  69         }
  70
  71         return false;
  72 }
  73
  74 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  75 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  76                     "providing the dmesg log by booting with drm.debug=0xf"
  77
  78 void
  79 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  80               const char *fmt, ...)
  81 {
  82         static bool shown_bug_once;
  83         struct device *kdev = dev_priv->drm.dev;
  84         bool is_error = level[1] <= KERN_ERR[1];
  85         bool is_debug = level[1] == KERN_DEBUG[1];
  86         struct va_format vaf;
  87         va_list args;
  88
  89         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  90                 return;
  91
  92         va_start(args, fmt);
  93
  94         vaf.fmt = fmt;
  95         vaf.va = &args;
  96
  97         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  98                    __builtin_return_address(0), &vaf);
  99
 100         if (is_error && !shown_bug_once) {
 101                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 102                 shown_bug_once = true;
 103         }
 104
 105         va_end(args);
 106 }
 107
 108 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 109 {
 110         return i915_modparams.inject_load_failure &&
 111                i915_load_fail_count == i915_modparams.inject_load_failure;
 112 }
 113
 114 #define i915_load_error(dev_priv, fmt, ...)                                  \
 115         __i915_printk(dev_priv,                                              \
 116                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 117                       fmt, ##__VA_ARGS__)
 118
 119
 120 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 121 {
 122         enum intel_pch ret = PCH_NOP;
 123
 124         /*
 125          * In a virtualized passthrough environment we can be in a
 126          * setup where the ISA bridge is not able to be passed through.
 127          * In this case, a south bridge can be emulated and we have to
 128          * make an educated guess as to which PCH is really there.
 129          */
 130
 131         if (IS_GEN5(dev_priv)) {
 132                 ret = PCH_IBX;
 133                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 134         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 135                 ret = PCH_CPT;
 136                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
 137         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 138                 ret = PCH_LPT;
 139                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 140                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 141                 else
 142                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 143                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 144         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 145                 ret = PCH_SPT;
 146                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 147         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 148                 ret = PCH_CNP;
 149                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 150         }
 151
 152         return ret;
 153 }
 154
 155 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 156 {
 157         struct pci_dev *pch = NULL;
 158
 159         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 160          * (which really amounts to a PCH but no South Display).
 161          */
 162         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 163                 dev_priv->pch_type = PCH_NOP;
 164                 return;
 165         }
 166
 167         /*
 168          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 169          * make graphics device passthrough work easy for VMM, that only
 170          * need to expose ISA bridge to let driver know the real hardware
 171          * underneath. This is a requirement from virtualization team.
 172          *
 173          * In some virtualized environments (e.g. XEN), there is irrelevant
 174          * ISA bridge in the system. To work reliably, we should scan trhough
 175          * all the ISA bridge devices and check for the first match, instead
 176          * of only checking the first one.
 177          */
 178         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 179                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 180                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 181
 182                         dev_priv->pch_id = id;
 183
 184                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 185                                 dev_priv->pch_type = PCH_IBX;
 186                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 187                                 WARN_ON(!IS_GEN5(dev_priv));
 188                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 189                                 dev_priv->pch_type = PCH_CPT;
 190                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 191                                 WARN_ON(!IS_GEN6(dev_priv) &&
 192                                         !IS_IVYBRIDGE(dev_priv));
 193                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 194                                 /* PantherPoint is CPT compatible */
 195                                 dev_priv->pch_type = PCH_CPT;
 196                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 197                                 WARN_ON(!IS_GEN6(dev_priv) &&
 198                                         !IS_IVYBRIDGE(dev_priv));
 199                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 200                                 dev_priv->pch_type = PCH_LPT;
 201                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 202                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 203                                         !IS_BROADWELL(dev_priv));
 204                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 205                                         IS_BDW_ULT(dev_priv));
 206                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 207                                 dev_priv->pch_type = PCH_LPT;
 208                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 209                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 210                                         !IS_BROADWELL(dev_priv));
 211                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 212                                         !IS_BDW_ULT(dev_priv));
 213                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
 214                                 /* WildcatPoint is LPT compatible */
 215                                 dev_priv->pch_type = PCH_LPT;
 216                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 217                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 218                                         !IS_BROADWELL(dev_priv));
 219                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 220                                         IS_BDW_ULT(dev_priv));
 221                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
 222                                 /* WildcatPoint is LPT compatible */
 223                                 dev_priv->pch_type = PCH_LPT;
 224                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 225                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 226                                         !IS_BROADWELL(dev_priv));
 227                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 228                                         !IS_BDW_ULT(dev_priv));
 229                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 230                                 dev_priv->pch_type = PCH_SPT;
 231                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 232                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 233                                         !IS_KABYLAKE(dev_priv));
 234                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 235                                 dev_priv->pch_type = PCH_SPT;
 236                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 237                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 238                                         !IS_KABYLAKE(dev_priv));
 239                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 240                                 dev_priv->pch_type = PCH_KBP;
 241                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 242                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 243                                         !IS_KABYLAKE(dev_priv) &&
 244                                         !IS_COFFEELAKE(dev_priv));
 245                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 246                                 dev_priv->pch_type = PCH_CNP;
 247                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 248                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 249                                         !IS_COFFEELAKE(dev_priv));
 250                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 251                                 dev_priv->pch_type = PCH_CNP;
 252                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 253                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 254                                         !IS_COFFEELAKE(dev_priv));
 255                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 256                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 257                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 258                                     pch->subsystem_vendor ==
 259                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 260                                     pch->subsystem_device ==
 261                                             PCI_SUBDEVICE_ID_QEMU)) {
 262                                 dev_priv->pch_type =
 263                                         intel_virt_detect_pch(dev_priv);
 264                         } else
 265                                 continue;
 266
 267                         break;
 268                 }
 269         }
 270         if (!pch)
 271                 DRM_DEBUG_KMS("No PCH found.\n");
 272
 273         pci_dev_put(pch);
 274 }
 275
 276 static int i915_getparam(struct drm_device *dev, void *data,
 277                          struct drm_file *file_priv)
 278 {
 279         struct drm_i915_private *dev_priv = to_i915(dev);
 280         struct pci_dev *pdev = dev_priv->drm.pdev;
 281         drm_i915_getparam_t *param = data;
 282         int value;
 283
 284         switch (param->param) {
 285         case I915_PARAM_IRQ_ACTIVE:
 286         case I915_PARAM_ALLOW_BATCHBUFFER:
 287         case I915_PARAM_LAST_DISPATCH:
 288         case I915_PARAM_HAS_EXEC_CONSTANTS:
 289                 /* Reject all old ums/dri params. */
 290                 return -ENODEV;
 291         case I915_PARAM_CHIPSET_ID:
 292                 value = pdev->device;
 293                 break;
 294         case I915_PARAM_REVISION:
 295                 value = pdev->revision;
 296                 break;
 297         case I915_PARAM_NUM_FENCES_AVAIL:
 298                 value = dev_priv->num_fence_regs;
 299                 break;
 300         case I915_PARAM_HAS_OVERLAY:
 301                 value = dev_priv->overlay ? 1 : 0;
 302                 break;
 303         case I915_PARAM_HAS_BSD:
 304                 value = !!dev_priv->engine[VCS];
 305                 break;
 306         case I915_PARAM_HAS_BLT:
 307                 value = !!dev_priv->engine[BCS];
 308                 break;
 309         case I915_PARAM_HAS_VEBOX:
 310                 value = !!dev_priv->engine[VECS];
 311                 break;
 312         case I915_PARAM_HAS_BSD2:
 313                 value = !!dev_priv->engine[VCS2];
 314                 break;
 315         case I915_PARAM_HAS_LLC:
 316                 value = HAS_LLC(dev_priv);
 317                 break;
 318         case I915_PARAM_HAS_WT:
 319                 value = HAS_WT(dev_priv);
 320                 break;
 321         case I915_PARAM_HAS_ALIASING_PPGTT:
 322                 value = USES_PPGTT(dev_priv);
 323                 break;
 324         case I915_PARAM_HAS_SEMAPHORES:
 325                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 326                 break;
 327         case I915_PARAM_HAS_SECURE_BATCHES:
 328                 value = capable(CAP_SYS_ADMIN);
 329                 break;
 330         case I915_PARAM_CMD_PARSER_VERSION:
 331                 value = i915_cmd_parser_get_version(dev_priv);
 332                 break;
 333         case I915_PARAM_SUBSLICE_TOTAL:
 334                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 335                 if (!value)
 336                         return -ENODEV;
 337                 break;
 338         case I915_PARAM_EU_TOTAL:
 339                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 340                 if (!value)
 341                         return -ENODEV;
 342                 break;
 343         case I915_PARAM_HAS_GPU_RESET:
 344                 value = i915_modparams.enable_hangcheck &&
 345                         intel_has_gpu_reset(dev_priv);
 346                 if (value && intel_has_reset_engine(dev_priv))
 347                         value = 2;
 348                 break;
 349         case I915_PARAM_HAS_RESOURCE_STREAMER:
 350                 value = HAS_RESOURCE_STREAMER(dev_priv);
 351                 break;
 352         case I915_PARAM_HAS_POOLED_EU:
 353                 value = HAS_POOLED_EU(dev_priv);
 354                 break;
 355         case I915_PARAM_MIN_EU_IN_POOL:
 356                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 357                 break;
 358         case I915_PARAM_HUC_STATUS:
 359                 intel_runtime_pm_get(dev_priv);
 360                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 361                 intel_runtime_pm_put(dev_priv);
 362                 break;
 363         case I915_PARAM_MMAP_GTT_VERSION:
 364                 /* Though we've started our numbering from 1, and so class all
 365                  * earlier versions as 0, in effect their value is undefined as
 366                  * the ioctl will report EINVAL for the unknown param!
 367                  */
 368                 value = i915_gem_mmap_gtt_version();
 369                 break;
 370         case I915_PARAM_HAS_SCHEDULER:
 371                 value = 0;
 372                 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
 373                         value |= I915_SCHEDULER_CAP_ENABLED;
 374                         value |= I915_SCHEDULER_CAP_PRIORITY;
 375                         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv))
 376                                 value |= I915_SCHEDULER_CAP_PREEMPTION;
 377                 }
 378                 break;
 379
 380         case I915_PARAM_MMAP_VERSION:
 381                 /* Remember to bump this if the version changes! */
 382         case I915_PARAM_HAS_GEM:
 383         case I915_PARAM_HAS_PAGEFLIPPING:
 384         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 385         case I915_PARAM_HAS_RELAXED_FENCING:
 386         case I915_PARAM_HAS_COHERENT_RINGS:
 387         case I915_PARAM_HAS_RELAXED_DELTA:
 388         case I915_PARAM_HAS_GEN7_SOL_RESET:
 389         case I915_PARAM_HAS_WAIT_TIMEOUT:
 390         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 391         case I915_PARAM_HAS_PINNED_BATCHES:
 392         case I915_PARAM_HAS_EXEC_NO_RELOC:
 393         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 394         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 395         case I915_PARAM_HAS_EXEC_SOFTPIN:
 396         case I915_PARAM_HAS_EXEC_ASYNC:
 397         case I915_PARAM_HAS_EXEC_FENCE:
 398         case I915_PARAM_HAS_EXEC_CAPTURE:
 399         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 400         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 401                 /* For the time being all of these are always true;
 402                  * if some supported hardware does not have one of these
 403                  * features this value needs to be provided from
 404                  * INTEL_INFO(), a feature macro, or similar.
 405                  */
 406                 value = 1;
 407                 break;
 408         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 409                 value = intel_engines_has_context_isolation(dev_priv);
 410                 break;
 411         case I915_PARAM_SLICE_MASK:
 412                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 413                 if (!value)
 414                         return -ENODEV;
 415                 break;
 416         case I915_PARAM_SUBSLICE_MASK:
 417                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 418                 if (!value)
 419                         return -ENODEV;
 420                 break;
 421         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 422                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 423                 break;
 424         default:
 425                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 426                 return -EINVAL;
 427         }
 428
 429         if (put_user(value, param->value))
 430                 return -EFAULT;
 431
 432         return 0;
 433 }
 434
 435 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 436 {
 437         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 438         if (!dev_priv->bridge_dev) {
 439                 DRM_ERROR("bridge device not found\n");
 440                 return -1;
 441         }
 442         return 0;
 443 }
 444
 445 /* Allocate space for the MCH regs if needed, return nonzero on error */
 446 static int
 447 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 448 {
 449         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 450         u32 temp_lo, temp_hi = 0;
 451         u64 mchbar_addr;
 452         int ret;
 453
 454         if (INTEL_GEN(dev_priv) >= 4)
 455                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 456         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 457         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 458
 459         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 460 #ifdef CONFIG_PNP
 461         if (mchbar_addr &&
 462             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 463                 return 0;
 464 #endif
 465
 466         /* Get some space for it */
 467         dev_priv->mch_res.name = "i915 MCHBAR";
 468         dev_priv->mch_res.flags = IORESOURCE_MEM;
 469         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 470                                      &dev_priv->mch_res,
 471                                      MCHBAR_SIZE, MCHBAR_SIZE,
 472                                      PCIBIOS_MIN_MEM,
 473                                      0, pcibios_align_resource,
 474                                      dev_priv->bridge_dev);
 475         if (ret) {
 476                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 477                 dev_priv->mch_res.start = 0;
 478                 return ret;
 479         }
 480
 481         if (INTEL_GEN(dev_priv) >= 4)
 482                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 483                                        upper_32_bits(dev_priv->mch_res.start));
 484
 485         pci_write_config_dword(dev_priv->bridge_dev, reg,
 486                                lower_32_bits(dev_priv->mch_res.start));
 487         return 0;
 488 }
 489
 490 /* Setup MCHBAR if possible, return true if we should disable it again */
 491 static void
 492 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 493 {
 494         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 495         u32 temp;
 496         bool enabled;
 497
 498         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 499                 return;
 500
 501         dev_priv->mchbar_need_disable = false;
 502
 503         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 504                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 505                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 506         } else {
 507                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 508                 enabled = temp & 1;
 509         }
 510
 511         /* If it's already enabled, don't have to do anything */
 512         if (enabled)
 513                 return;
 514
 515         if (intel_alloc_mchbar_resource(dev_priv))
 516                 return;
 517
 518         dev_priv->mchbar_need_disable = true;
 519
 520         /* Space is allocated or reserved, so enable it. */
 521         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 522                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 523                                        temp | DEVEN_MCHBAR_EN);
 524         } else {
 525                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 526                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 527         }
 528 }
 529
 530 static void
 531 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 532 {
 533         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 534
 535         if (dev_priv->mchbar_need_disable) {
 536                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 537                         u32 deven_val;
 538
 539                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 540                                               &deven_val);
 541                         deven_val &= ~DEVEN_MCHBAR_EN;
 542                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 543                                                deven_val);
 544                 } else {
 545                         u32 mchbar_val;
 546
 547                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 548                                               &mchbar_val);
 549                         mchbar_val &= ~1;
 550                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 551                                                mchbar_val);
 552                 }
 553         }
 554
 555         if (dev_priv->mch_res.start)
 556                 release_resource(&dev_priv->mch_res);
 557 }
 558
 559 /* true = enable decode, false = disable decoder */
 560 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 561 {
 562         struct drm_i915_private *dev_priv = cookie;
 563
 564         intel_modeset_vga_set_state(dev_priv, state);
 565         if (state)
 566                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 567                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 568         else
 569                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 570 }
 571
 572 static int i915_resume_switcheroo(struct drm_device *dev);
 573 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 574
 575 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 576 {
 577         struct drm_device *dev = pci_get_drvdata(pdev);
 578         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 579
 580         if (state == VGA_SWITCHEROO_ON) {
 581                 pr_info("switched on\n");
 582                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 583                 /* i915 resume handler doesn't set to D0 */
 584                 pci_set_power_state(pdev, PCI_D0);
 585                 i915_resume_switcheroo(dev);
 586                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 587         } else {
 588                 pr_info("switched off\n");
 589                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 590                 i915_suspend_switcheroo(dev, pmm);
 591                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 592         }
 593 }
 594
 595 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 596 {
 597         struct drm_device *dev = pci_get_drvdata(pdev);
 598
 599         /*
 600          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 601          * locking inversion with the driver load path. And the access here is
 602          * completely racy anyway. So don't bother with locking for now.
 603          */
 604         return dev->open_count == 0;
 605 }
 606
 607 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 608         .set_gpu_state = i915_switcheroo_set_state,
 609         .reprobe = NULL,
 610         .can_switch = i915_switcheroo_can_switch,
 611 };
 612
 613 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 614 {
 615         /* Flush any outstanding unpin_work. */
 616         i915_gem_drain_workqueue(dev_priv);
 617
 618         mutex_lock(&dev_priv->drm.struct_mutex);
 619         intel_uc_fini_hw(dev_priv);
 620         intel_uc_fini(dev_priv);
 621         i915_gem_cleanup_engines(dev_priv);
 622         i915_gem_contexts_fini(dev_priv);
 623         mutex_unlock(&dev_priv->drm.struct_mutex);
 624
 625         intel_uc_fini_wq(dev_priv);
 626         i915_gem_cleanup_userptr(dev_priv);
 627
 628         i915_gem_drain_freed_objects(dev_priv);
 629
 630         WARN_ON(!list_empty(&dev_priv->contexts.list));
 631 }
 632
 633 static int i915_load_modeset_init(struct drm_device *dev)
 634 {
 635         struct drm_i915_private *dev_priv = to_i915(dev);
 636         struct pci_dev *pdev = dev_priv->drm.pdev;
 637         int ret;
 638
 639         if (i915_inject_load_failure())
 640                 return -ENODEV;
 641
 642         intel_bios_init(dev_priv);
 643
 644         /* If we have > 1 VGA cards, then we need to arbitrate access
 645          * to the common VGA resources.
 646          *
 647          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 648          * then we do not take part in VGA arbitration and the
 649          * vga_client_register() fails with -ENODEV.
 650          */
 651         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 652         if (ret && ret != -ENODEV)
 653                 goto out;
 654
 655         intel_register_dsm_handler();
 656
 657         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 658         if (ret)
 659                 goto cleanup_vga_client;
 660
 661         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 662         intel_update_rawclk(dev_priv);
 663
 664         intel_power_domains_init_hw(dev_priv, false);
 665
 666         intel_csr_ucode_init(dev_priv);
 667
 668         ret = intel_irq_install(dev_priv);
 669         if (ret)
 670                 goto cleanup_csr;
 671
 672         intel_setup_gmbus(dev_priv);
 673
 674         /* Important: The output setup functions called by modeset_init need
 675          * working irqs for e.g. gmbus and dp aux transfers. */
 676         ret = intel_modeset_init(dev);
 677         if (ret)
 678                 goto cleanup_irq;
 679
 680         intel_uc_init_fw(dev_priv);
 681
 682         ret = i915_gem_init(dev_priv);
 683         if (ret)
 684                 goto cleanup_uc;
 685
 686         intel_setup_overlay(dev_priv);
 687
 688         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 689                 return 0;
 690
 691         ret = intel_fbdev_init(dev);
 692         if (ret)
 693                 goto cleanup_gem;
 694
 695         /* Only enable hotplug handling once the fbdev is fully set up. */
 696         intel_hpd_init(dev_priv);
 697
 698         return 0;
 699
 700 cleanup_gem:
 701         if (i915_gem_suspend(dev_priv))
 702                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 703         i915_gem_fini(dev_priv);
 704 cleanup_uc:
 705         intel_uc_fini_fw(dev_priv);
 706 cleanup_irq:
 707         drm_irq_uninstall(dev);
 708         intel_teardown_gmbus(dev_priv);
 709 cleanup_csr:
 710         intel_csr_ucode_fini(dev_priv);
 711         intel_power_domains_fini(dev_priv);
 712         vga_switcheroo_unregister_client(pdev);
 713 cleanup_vga_client:
 714         vga_client_register(pdev, NULL, NULL, NULL);
 715 out:
 716         return ret;
 717 }
 718
 719 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 720 {
 721         struct apertures_struct *ap;
 722         struct pci_dev *pdev = dev_priv->drm.pdev;
 723         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 724         bool primary;
 725         int ret;
 726
 727         ap = alloc_apertures(1);
 728         if (!ap)
 729                 return -ENOMEM;
 730
 731         ap->ranges[0].base = ggtt->gmadr.start;
 732         ap->ranges[0].size = ggtt->mappable_end;
 733
 734         primary =
 735                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 736
 737         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 738
 739         kfree(ap);
 740
 741         return ret;
 742 }
 743
 744 #if !defined(CONFIG_VGA_CONSOLE)
 745 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 746 {
 747         return 0;
 748 }
 749 #elif !defined(CONFIG_DUMMY_CONSOLE)
 750 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 751 {
 752         return -ENODEV;
 753 }
 754 #else
 755 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 756 {
 757         int ret = 0;
 758
 759         DRM_INFO("Replacing VGA console driver\n");
 760
 761         console_lock();
 762         if (con_is_bound(&vga_con))
 763                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 764         if (ret == 0) {
 765                 ret = do_unregister_con_driver(&vga_con);
 766
 767                 /* Ignore "already unregistered". */
 768                 if (ret == -ENODEV)
 769                         ret = 0;
 770         }
 771         console_unlock();
 772
 773         return ret;
 774 }
 775 #endif
 776
 777 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 778 {
 779         /*
 780          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 781          * CHV x1 PHY (DP/HDMI D)
 782          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 783          */
 784         if (IS_CHERRYVIEW(dev_priv)) {
 785                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 786                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 787         } else if (IS_VALLEYVIEW(dev_priv)) {
 788                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 789         }
 790 }
 791
 792 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 793 {
 794         /*
 795          * The i915 workqueue is primarily used for batched retirement of
 796          * requests (and thus managing bo) once the task has been completed
 797          * by the GPU. i915_gem_retire_requests() is called directly when we
 798          * need high-priority retirement, such as waiting for an explicit
 799          * bo.
 800          *
 801          * It is also used for periodic low-priority events, such as
 802          * idle-timers and recording error state.
 803          *
 804          * All tasks on the workqueue are expected to acquire the dev mutex
 805          * so there is no point in running more than one instance of the
 806          * workqueue at any time.  Use an ordered one.
 807          */
 808         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 809         if (dev_priv->wq == NULL)
 810                 goto out_err;
 811
 812         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 813         if (dev_priv->hotplug.dp_wq == NULL)
 814                 goto out_free_wq;
 815
 816         return 0;
 817
 818 out_free_wq:
 819         destroy_workqueue(dev_priv->wq);
 820 out_err:
 821         DRM_ERROR("Failed to allocate workqueues.\n");
 822
 823         return -ENOMEM;
 824 }
 825
 826 static void i915_engines_cleanup(struct drm_i915_private *i915)
 827 {
 828         struct intel_engine_cs *engine;
 829         enum intel_engine_id id;
 830
 831         for_each_engine(engine, i915, id)
 832                 kfree(engine);
 833 }
 834
 835 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 836 {
 837         destroy_workqueue(dev_priv->hotplug.dp_wq);
 838         destroy_workqueue(dev_priv->wq);
 839 }
 840
 841 /*
 842  * We don't keep the workarounds for pre-production hardware, so we expect our
 843  * driver to fail on these machines in one way or another. A little warning on
 844  * dmesg may help both the user and the bug triagers.
 845  *
 846  * Our policy for removing pre-production workarounds is to keep the
 847  * current gen workarounds as a guide to the bring-up of the next gen
 848  * (workarounds have a habit of persisting!). Anything older than that
 849  * should be removed along with the complications they introduce.
 850  */
 851 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 852 {
 853         bool pre = false;
 854
 855         pre |= IS_HSW_EARLY_SDV(dev_priv);
 856         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 857         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 858
 859         if (pre) {
 860                 DRM_ERROR("This is a pre-production stepping. "
 861                           "It may not be fully functional.\n");
 862                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 863         }
 864 }
 865
 866 /**
 867  * i915_driver_init_early - setup state not requiring device access
 868  * @dev_priv: device private
 869  *
 870  * Initialize everything that is a "SW-only" state, that is state not
 871  * requiring accessing the device or exposing the driver via kernel internal
 872  * or userspace interfaces. Example steps belonging here: lock initialization,
 873  * system memory allocation, setting up device specific attributes and
 874  * function hooks not requiring accessing the device.
 875  */
 876 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 877                                   const struct pci_device_id *ent)
 878 {
 879         const struct intel_device_info *match_info =
 880                 (struct intel_device_info *)ent->driver_data;
 881         struct intel_device_info *device_info;
 882         int ret = 0;
 883
 884         if (i915_inject_load_failure())
 885                 return -ENODEV;
 886
 887         /* Setup the write-once "constant" device info */
 888         device_info = mkwrite_device_info(dev_priv);
 889         memcpy(device_info, match_info, sizeof(*device_info));
 890         device_info->device_id = dev_priv->drm.pdev->device;
 891
 892         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 893                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 894         device_info->platform_mask = BIT(device_info->platform);
 895
 896         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 897         device_info->gen_mask = BIT(device_info->gen - 1);
 898
 899         spin_lock_init(&dev_priv->irq_lock);
 900         spin_lock_init(&dev_priv->gpu_error.lock);
 901         mutex_init(&dev_priv->backlight_lock);
 902         spin_lock_init(&dev_priv->uncore.lock);
 903
 904         mutex_init(&dev_priv->sb_lock);
 905         mutex_init(&dev_priv->modeset_restore_lock);
 906         mutex_init(&dev_priv->av_mutex);
 907         mutex_init(&dev_priv->wm.wm_mutex);
 908         mutex_init(&dev_priv->pps_mutex);
 909
 910         intel_uc_init_early(dev_priv);
 911         i915_memcpy_init_early(dev_priv);
 912
 913         ret = i915_workqueues_init(dev_priv);
 914         if (ret < 0)
 915                 goto err_engines;
 916
 917         /* This must be called before any calls to HAS_PCH_* */
 918         intel_detect_pch(dev_priv);
 919
 920         intel_pm_setup(dev_priv);
 921         intel_init_dpio(dev_priv);
 922         intel_power_domains_init(dev_priv);
 923         intel_irq_init(dev_priv);
 924         intel_hangcheck_init(dev_priv);
 925         intel_init_display_hooks(dev_priv);
 926         intel_init_clock_gating_hooks(dev_priv);
 927         intel_init_audio_hooks(dev_priv);
 928         ret = i915_gem_load_init(dev_priv);
 929         if (ret < 0)
 930                 goto err_irq;
 931
 932         intel_display_crc_init(dev_priv);
 933
 934         intel_detect_preproduction_hw(dev_priv);
 935
 936         return 0;
 937
 938 err_irq:
 939         intel_irq_fini(dev_priv);
 940         i915_workqueues_cleanup(dev_priv);
 941 err_engines:
 942         i915_engines_cleanup(dev_priv);
 943         return ret;
 944 }
 945
 946 /**
 947  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 948  * @dev_priv: device private
 949  */
 950 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 951 {
 952         i915_gem_load_cleanup(dev_priv);
 953         intel_irq_fini(dev_priv);
 954         i915_workqueues_cleanup(dev_priv);
 955         i915_engines_cleanup(dev_priv);
 956 }
 957
 958 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 959 {
 960         struct pci_dev *pdev = dev_priv->drm.pdev;
 961         int mmio_bar;
 962         int mmio_size;
 963
 964         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 965         /*
 966          * Before gen4, the registers and the GTT are behind different BARs.
 967          * However, from gen4 onwards, the registers and the GTT are shared
 968          * in the same BAR, so we want to restrict this ioremap from
 969          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 970          * the register BAR remains the same size for all the earlier
 971          * generations up to Ironlake.
 972          */
 973         if (INTEL_GEN(dev_priv) < 5)
 974                 mmio_size = 512 * 1024;
 975         else
 976                 mmio_size = 2 * 1024 * 1024;
 977         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 978         if (dev_priv->regs == NULL) {
 979                 DRM_ERROR("failed to map registers\n");
 980
 981                 return -EIO;
 982         }
 983
 984         /* Try to make sure MCHBAR is enabled before poking at it */
 985         intel_setup_mchbar(dev_priv);
 986
 987         return 0;
 988 }
 989
 990 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 991 {
 992         struct pci_dev *pdev = dev_priv->drm.pdev;
 993
 994         intel_teardown_mchbar(dev_priv);
 995         pci_iounmap(pdev, dev_priv->regs);
 996 }
 997
 998 /**
 999  * i915_driver_init_mmio - setup device MMIO
1000  * @dev_priv: device private
1001  *
1002  * Setup minimal device state necessary for MMIO accesses later in the
1003  * initialization sequence. The setup here should avoid any other device-wide
1004  * side effects or exposing the driver via kernel internal or user space
1005  * interfaces.
1006  */
1007 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1008 {
1009         int ret;
1010
1011         if (i915_inject_load_failure())
1012                 return -ENODEV;
1013
1014         if (i915_get_bridge_dev(dev_priv))
1015                 return -EIO;
1016
1017         ret = i915_mmio_setup(dev_priv);
1018         if (ret < 0)
1019                 goto err_bridge;
1020
1021         intel_uncore_init(dev_priv);
1022
1023         intel_uc_init_mmio(dev_priv);
1024
1025         ret = intel_engines_init_mmio(dev_priv);
1026         if (ret)
1027                 goto err_uncore;
1028
1029         i915_gem_init_mmio(dev_priv);
1030
1031         return 0;
1032
1033 err_uncore:
1034         intel_uncore_fini(dev_priv);
1035 err_bridge:
1036         pci_dev_put(dev_priv->bridge_dev);
1037
1038         return ret;
1039 }
1040
1041 /**
1042  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1043  * @dev_priv: device private
1044  */
1045 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1046 {
1047         intel_uncore_fini(dev_priv);
1048         i915_mmio_cleanup(dev_priv);
1049         pci_dev_put(dev_priv->bridge_dev);
1050 }
1051
1052 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1053 {
1054         /*
1055          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1056          * user's requested state against the hardware/driver capabilities.  We
1057          * do this now so that we can print out any log messages once rather
1058          * than every time we check intel_enable_ppgtt().
1059          */
1060         i915_modparams.enable_ppgtt =
1061                 intel_sanitize_enable_ppgtt(dev_priv,
1062                                             i915_modparams.enable_ppgtt);
1063         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1064
1065         intel_uc_sanitize_options(dev_priv);
1066
1067         intel_gvt_sanitize_options(dev_priv);
1068 }
1069
1070 /**
1071  * i915_driver_init_hw - setup state requiring device access
1072  * @dev_priv: device private
1073  *
1074  * Setup state that requires accessing the device, but doesn't require
1075  * exposing the driver via kernel internal or userspace interfaces.
1076  */
1077 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1078 {
1079         struct pci_dev *pdev = dev_priv->drm.pdev;
1080         int ret;
1081
1082         if (i915_inject_load_failure())
1083                 return -ENODEV;
1084
1085         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1086
1087         intel_sanitize_options(dev_priv);
1088
1089         i915_perf_init(dev_priv);
1090
1091         ret = i915_ggtt_probe_hw(dev_priv);
1092         if (ret)
1093                 return ret;
1094
1095         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1096          * otherwise the vga fbdev driver falls over. */
1097         ret = i915_kick_out_firmware_fb(dev_priv);
1098         if (ret) {
1099                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1100                 goto out_ggtt;
1101         }
1102
1103         ret = i915_kick_out_vgacon(dev_priv);
1104         if (ret) {
1105                 DRM_ERROR("failed to remove conflicting VGA console\n");
1106                 goto out_ggtt;
1107         }
1108
1109         ret = i915_ggtt_init_hw(dev_priv);
1110         if (ret)
1111                 return ret;
1112
1113         ret = i915_ggtt_enable_hw(dev_priv);
1114         if (ret) {
1115                 DRM_ERROR("failed to enable GGTT\n");
1116                 goto out_ggtt;
1117         }
1118
1119         pci_set_master(pdev);
1120
1121         /* overlay on gen2 is broken and can't address above 1G */
1122         if (IS_GEN2(dev_priv)) {
1123                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1124                 if (ret) {
1125                         DRM_ERROR("failed to set DMA mask\n");
1126
1127                         goto out_ggtt;
1128                 }
1129         }
1130
1131         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1132          * using 32bit addressing, overwriting memory if HWS is located
1133          * above 4GB.
1134          *
1135          * The documentation also mentions an issue with undefined
1136          * behaviour if any general state is accessed within a page above 4GB,
1137          * which also needs to be handled carefully.
1138          */
1139         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1140                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1141
1142                 if (ret) {
1143                         DRM_ERROR("failed to set DMA mask\n");
1144
1145                         goto out_ggtt;
1146                 }
1147         }
1148
1149         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1150                            PM_QOS_DEFAULT_VALUE);
1151
1152         intel_uncore_sanitize(dev_priv);
1153
1154         intel_opregion_setup(dev_priv);
1155
1156         i915_gem_load_init_fences(dev_priv);
1157
1158         /* On the 945G/GM, the chipset reports the MSI capability on the
1159          * integrated graphics even though the support isn't actually there
1160          * according to the published specs.  It doesn't appear to function
1161          * correctly in testing on 945G.
1162          * This may be a side effect of MSI having been made available for PEG
1163          * and the registers being closely associated.
1164          *
1165          * According to chipset errata, on the 965GM, MSI interrupts may
1166          * be lost or delayed, and was defeatured. MSI interrupts seem to
1167          * get lost on g4x as well, and interrupt delivery seems to stay
1168          * properly dead afterwards. So we'll just disable them for all
1169          * pre-gen5 chipsets.
1170          */
1171         if (INTEL_GEN(dev_priv) >= 5) {
1172                 if (pci_enable_msi(pdev) < 0)
1173                         DRM_DEBUG_DRIVER("can't enable MSI");
1174         }
1175
1176         ret = intel_gvt_init(dev_priv);
1177         if (ret)
1178                 goto out_ggtt;
1179
1180         return 0;
1181
1182 out_ggtt:
1183         i915_ggtt_cleanup_hw(dev_priv);
1184
1185         return ret;
1186 }
1187
1188 /**
1189  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1190  * @dev_priv: device private
1191  */
1192 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1193 {
1194         struct pci_dev *pdev = dev_priv->drm.pdev;
1195
1196         i915_perf_fini(dev_priv);
1197
1198         if (pdev->msi_enabled)
1199                 pci_disable_msi(pdev);
1200
1201         pm_qos_remove_request(&dev_priv->pm_qos);
1202         i915_ggtt_cleanup_hw(dev_priv);
1203 }
1204
1205 /**
1206  * i915_driver_register - register the driver with the rest of the system
1207  * @dev_priv: device private
1208  *
1209  * Perform any steps necessary to make the driver available via kernel
1210  * internal or userspace interfaces.
1211  */
1212 static void i915_driver_register(struct drm_i915_private *dev_priv)
1213 {
1214         struct drm_device *dev = &dev_priv->drm;
1215
1216         i915_gem_shrinker_register(dev_priv);
1217         i915_pmu_register(dev_priv);
1218
1219         /*
1220          * Notify a valid surface after modesetting,
1221          * when running inside a VM.
1222          */
1223         if (intel_vgpu_active(dev_priv))
1224                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1225
1226         /* Reveal our presence to userspace */
1227         if (drm_dev_register(dev, 0) == 0) {
1228                 i915_debugfs_register(dev_priv);
1229                 i915_guc_log_register(dev_priv);
1230                 i915_setup_sysfs(dev_priv);
1231
1232                 /* Depends on sysfs having been initialized */
1233                 i915_perf_register(dev_priv);
1234         } else
1235                 DRM_ERROR("Failed to register driver for userspace access!\n");
1236
1237         if (INTEL_INFO(dev_priv)->num_pipes) {
1238                 /* Must be done after probing outputs */
1239                 intel_opregion_register(dev_priv);
1240                 acpi_video_register();
1241         }
1242
1243         if (IS_GEN5(dev_priv))
1244                 intel_gpu_ips_init(dev_priv);
1245
1246         intel_audio_init(dev_priv);
1247
1248         /*
1249          * Some ports require correctly set-up hpd registers for detection to
1250          * work properly (leading to ghost connected connector status), e.g. VGA
1251          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1252          * irqs are fully enabled. We do it last so that the async config
1253          * cannot run before the connectors are registered.
1254          */
1255         intel_fbdev_initial_config_async(dev);
1256
1257         /*
1258          * We need to coordinate the hotplugs with the asynchronous fbdev
1259          * configuration, for which we use the fbdev->async_cookie.
1260          */
1261         if (INTEL_INFO(dev_priv)->num_pipes)
1262                 drm_kms_helper_poll_init(dev);
1263 }
1264
1265 /**
1266  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1267  * @dev_priv: device private
1268  */
1269 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1270 {
1271         intel_fbdev_unregister(dev_priv);
1272         intel_audio_deinit(dev_priv);
1273
1274         /*
1275          * After flushing the fbdev (incl. a late async config which will
1276          * have delayed queuing of a hotplug event), then flush the hotplug
1277          * events.
1278          */
1279         drm_kms_helper_poll_fini(&dev_priv->drm);
1280
1281         intel_gpu_ips_teardown();
1282         acpi_video_unregister();
1283         intel_opregion_unregister(dev_priv);
1284
1285         i915_perf_unregister(dev_priv);
1286         i915_pmu_unregister(dev_priv);
1287
1288         i915_teardown_sysfs(dev_priv);
1289         i915_guc_log_unregister(dev_priv);
1290         drm_dev_unregister(&dev_priv->drm);
1291
1292         i915_gem_shrinker_unregister(dev_priv);
1293 }
1294
1295 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1296 {
1297         if (drm_debug & DRM_UT_DRIVER) {
1298                 struct drm_printer p = drm_debug_printer("i915 device info:");
1299
1300                 intel_device_info_dump(&dev_priv->info, &p);
1301                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1302         }
1303
1304         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1305                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1306         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1307                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1308 }
1309
1310 /**
1311  * i915_driver_load - setup chip and create an initial config
1312  * @pdev: PCI device
1313  * @ent: matching PCI ID entry
1314  *
1315  * The driver load routine has to do several things:
1316  *   - drive output discovery via intel_modeset_init()
1317  *   - initialize the memory manager
1318  *   - allocate initial config memory
1319  *   - setup the DRM framebuffer with the allocated memory
1320  */
1321 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1322 {
1323         const struct intel_device_info *match_info =
1324                 (struct intel_device_info *)ent->driver_data;
1325         struct drm_i915_private *dev_priv;
1326         int ret;
1327
1328         /* Enable nuclear pageflip on ILK+ */
1329         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1330                 driver.driver_features &= ~DRIVER_ATOMIC;
1331
1332         ret = -ENOMEM;
1333         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1334         if (dev_priv)
1335                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1336         if (ret) {
1337                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1338                 goto out_free;
1339         }
1340
1341         dev_priv->drm.pdev = pdev;
1342         dev_priv->drm.dev_private = dev_priv;
1343
1344         ret = pci_enable_device(pdev);
1345         if (ret)
1346                 goto out_fini;
1347
1348         pci_set_drvdata(pdev, &dev_priv->drm);
1349         /*
1350          * Disable the system suspend direct complete optimization, which can
1351          * leave the device suspended skipping the driver's suspend handlers
1352          * if the device was already runtime suspended. This is needed due to
1353          * the difference in our runtime and system suspend sequence and
1354          * becaue the HDA driver may require us to enable the audio power
1355          * domain during system suspend.
1356          */
1357         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1358
1359         ret = i915_driver_init_early(dev_priv, ent);
1360         if (ret < 0)
1361                 goto out_pci_disable;
1362
1363         intel_runtime_pm_get(dev_priv);
1364
1365         ret = i915_driver_init_mmio(dev_priv);
1366         if (ret < 0)
1367                 goto out_runtime_pm_put;
1368
1369         ret = i915_driver_init_hw(dev_priv);
1370         if (ret < 0)
1371                 goto out_cleanup_mmio;
1372
1373         /*
1374          * TODO: move the vblank init and parts of modeset init steps into one
1375          * of the i915_driver_init_/i915_driver_register functions according
1376          * to the role/effect of the given init step.
1377          */
1378         if (INTEL_INFO(dev_priv)->num_pipes) {
1379                 ret = drm_vblank_init(&dev_priv->drm,
1380                                       INTEL_INFO(dev_priv)->num_pipes);
1381                 if (ret)
1382                         goto out_cleanup_hw;
1383         }
1384
1385         ret = i915_load_modeset_init(&dev_priv->drm);
1386         if (ret < 0)
1387                 goto out_cleanup_hw;
1388
1389         i915_driver_register(dev_priv);
1390
1391         intel_runtime_pm_enable(dev_priv);
1392
1393         intel_init_ipc(dev_priv);
1394
1395         intel_runtime_pm_put(dev_priv);
1396
1397         i915_welcome_messages(dev_priv);
1398
1399         return 0;
1400
1401 out_cleanup_hw:
1402         i915_driver_cleanup_hw(dev_priv);
1403 out_cleanup_mmio:
1404         i915_driver_cleanup_mmio(dev_priv);
1405 out_runtime_pm_put:
1406         intel_runtime_pm_put(dev_priv);
1407         i915_driver_cleanup_early(dev_priv);
1408 out_pci_disable:
1409         pci_disable_device(pdev);
1410 out_fini:
1411         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1412         drm_dev_fini(&dev_priv->drm);
1413 out_free:
1414         kfree(dev_priv);
1415         return ret;
1416 }
1417
1418 void i915_driver_unload(struct drm_device *dev)
1419 {
1420         struct drm_i915_private *dev_priv = to_i915(dev);
1421         struct pci_dev *pdev = dev_priv->drm.pdev;
1422
1423         i915_driver_unregister(dev_priv);
1424
1425         if (i915_gem_suspend(dev_priv))
1426                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1427
1428         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1429
1430         drm_atomic_helper_shutdown(dev);
1431
1432         intel_gvt_cleanup(dev_priv);
1433
1434         intel_modeset_cleanup(dev);
1435
1436         /*
1437          * free the memory space allocated for the child device
1438          * config parsed from VBT
1439          */
1440         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1441                 kfree(dev_priv->vbt.child_dev);
1442                 dev_priv->vbt.child_dev = NULL;
1443                 dev_priv->vbt.child_dev_num = 0;
1444         }
1445         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1446         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1447         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1448         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1449
1450         vga_switcheroo_unregister_client(pdev);
1451         vga_client_register(pdev, NULL, NULL, NULL);
1452
1453         intel_csr_ucode_fini(dev_priv);
1454
1455         /* Free error state after interrupts are fully disabled. */
1456         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1457         i915_reset_error_state(dev_priv);
1458
1459         i915_gem_fini(dev_priv);
1460         intel_uc_fini_fw(dev_priv);
1461         intel_fbc_cleanup_cfb(dev_priv);
1462
1463         intel_power_domains_fini(dev_priv);
1464
1465         i915_driver_cleanup_hw(dev_priv);
1466         i915_driver_cleanup_mmio(dev_priv);
1467
1468         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1469 }
1470
1471 static void i915_driver_release(struct drm_device *dev)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(dev);
1474
1475         i915_driver_cleanup_early(dev_priv);
1476         drm_dev_fini(&dev_priv->drm);
1477
1478         kfree(dev_priv);
1479 }
1480
1481 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1482 {
1483         struct drm_i915_private *i915 = to_i915(dev);
1484         int ret;
1485
1486         ret = i915_gem_open(i915, file);
1487         if (ret)
1488                 return ret;
1489
1490         return 0;
1491 }
1492
1493 /**
1494  * i915_driver_lastclose - clean up after all DRM clients have exited
1495  * @dev: DRM device
1496  *
1497  * Take care of cleaning up after all DRM clients have exited.  In the
1498  * mode setting case, we want to restore the kernel's initial mode (just
1499  * in case the last client left us in a bad state).
1500  *
1501  * Additionally, in the non-mode setting case, we'll tear down the GTT
1502  * and DMA structures, since the kernel won't be using them, and clea
1503  * up any GEM state.
1504  */
1505 static void i915_driver_lastclose(struct drm_device *dev)
1506 {
1507         intel_fbdev_restore_mode(dev);
1508         vga_switcheroo_process_delayed_switch();
1509 }
1510
1511 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1512 {
1513         struct drm_i915_file_private *file_priv = file->driver_priv;
1514
1515         mutex_lock(&dev->struct_mutex);
1516         i915_gem_context_close(file);
1517         i915_gem_release(dev, file);
1518         mutex_unlock(&dev->struct_mutex);
1519
1520         kfree(file_priv);
1521 }
1522
1523 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1524 {
1525         struct drm_device *dev = &dev_priv->drm;
1526         struct intel_encoder *encoder;
1527
1528         drm_modeset_lock_all(dev);
1529         for_each_intel_encoder(dev, encoder)
1530                 if (encoder->suspend)
1531                         encoder->suspend(encoder);
1532         drm_modeset_unlock_all(dev);
1533 }
1534
1535 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1536                               bool rpm_resume);
1537 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1538
1539 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1540 {
1541 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1542         if (acpi_target_system_state() < ACPI_STATE_S3)
1543                 return true;
1544 #endif
1545         return false;
1546 }
1547
1548 static int i915_drm_suspend(struct drm_device *dev)
1549 {
1550         struct drm_i915_private *dev_priv = to_i915(dev);
1551         struct pci_dev *pdev = dev_priv->drm.pdev;
1552         pci_power_t opregion_target_state;
1553         int error;
1554
1555         /* ignore lid events during suspend */
1556         mutex_lock(&dev_priv->modeset_restore_lock);
1557         dev_priv->modeset_restore = MODESET_SUSPENDED;
1558         mutex_unlock(&dev_priv->modeset_restore_lock);
1559
1560         disable_rpm_wakeref_asserts(dev_priv);
1561
1562         /* We do a lot of poking in a lot of registers, make sure they work
1563          * properly. */
1564         intel_display_set_init_power(dev_priv, true);
1565
1566         drm_kms_helper_poll_disable(dev);
1567
1568         pci_save_state(pdev);
1569
1570         error = i915_gem_suspend(dev_priv);
1571         if (error) {
1572                 dev_err(&pdev->dev,
1573                         "GEM idle failed, resume might fail\n");
1574                 goto out;
1575         }
1576
1577         intel_display_suspend(dev);
1578
1579         intel_dp_mst_suspend(dev);
1580
1581         intel_runtime_pm_disable_interrupts(dev_priv);
1582         intel_hpd_cancel_work(dev_priv);
1583
1584         intel_suspend_encoders(dev_priv);
1585
1586         intel_suspend_hw(dev_priv);
1587
1588         i915_gem_suspend_gtt_mappings(dev_priv);
1589
1590         i915_save_state(dev_priv);
1591
1592         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1593         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1594
1595         intel_uncore_suspend(dev_priv);
1596         intel_opregion_unregister(dev_priv);
1597
1598         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1599
1600         dev_priv->suspend_count++;
1601
1602         intel_csr_ucode_suspend(dev_priv);
1603
1604 out:
1605         enable_rpm_wakeref_asserts(dev_priv);
1606
1607         return error;
1608 }
1609
1610 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1611 {
1612         struct drm_i915_private *dev_priv = to_i915(dev);
1613         struct pci_dev *pdev = dev_priv->drm.pdev;
1614         bool fw_csr;
1615         int ret;
1616
1617         disable_rpm_wakeref_asserts(dev_priv);
1618
1619         intel_display_set_init_power(dev_priv, false);
1620
1621         fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1622                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1623         /*
1624          * In case of firmware assisted context save/restore don't manually
1625          * deinit the power domains. This also means the CSR/DMC firmware will
1626          * stay active, it will power down any HW resources as required and
1627          * also enable deeper system power states that would be blocked if the
1628          * firmware was inactive.
1629          */
1630         if (!fw_csr)
1631                 intel_power_domains_suspend(dev_priv);
1632
1633         ret = 0;
1634         if (IS_GEN9_LP(dev_priv))
1635                 bxt_enable_dc9(dev_priv);
1636         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1637                 hsw_enable_pc8(dev_priv);
1638         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1639                 ret = vlv_suspend_complete(dev_priv);
1640
1641         if (ret) {
1642                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1643                 if (!fw_csr)
1644                         intel_power_domains_init_hw(dev_priv, true);
1645
1646                 goto out;
1647         }
1648
1649         pci_disable_device(pdev);
1650         /*
1651          * During hibernation on some platforms the BIOS may try to access
1652          * the device even though it's already in D3 and hang the machine. So
1653          * leave the device in D0 on those platforms and hope the BIOS will
1654          * power down the device properly. The issue was seen on multiple old
1655          * GENs with different BIOS vendors, so having an explicit blacklist
1656          * is inpractical; apply the workaround on everything pre GEN6. The
1657          * platforms where the issue was seen:
1658          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1659          * Fujitsu FSC S7110
1660          * Acer Aspire 1830T
1661          */
1662         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1663                 pci_set_power_state(pdev, PCI_D3hot);
1664
1665         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1666
1667 out:
1668         enable_rpm_wakeref_asserts(dev_priv);
1669
1670         return ret;
1671 }
1672
1673 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1674 {
1675         int error;
1676
1677         if (!dev) {
1678                 DRM_ERROR("dev: %p\n", dev);
1679                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1680                 return -ENODEV;
1681         }
1682
1683         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1684                          state.event != PM_EVENT_FREEZE))
1685                 return -EINVAL;
1686
1687         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1688                 return 0;
1689
1690         error = i915_drm_suspend(dev);
1691         if (error)
1692                 return error;
1693
1694         return i915_drm_suspend_late(dev, false);
1695 }
1696
1697 static int i915_drm_resume(struct drm_device *dev)
1698 {
1699         struct drm_i915_private *dev_priv = to_i915(dev);
1700         int ret;
1701
1702         disable_rpm_wakeref_asserts(dev_priv);
1703         intel_sanitize_gt_powersave(dev_priv);
1704
1705         ret = i915_ggtt_enable_hw(dev_priv);
1706         if (ret)
1707                 DRM_ERROR("failed to re-enable GGTT\n");
1708
1709         intel_csr_ucode_resume(dev_priv);
1710
1711         i915_restore_state(dev_priv);
1712         intel_pps_unlock_regs_wa(dev_priv);
1713         intel_opregion_setup(dev_priv);
1714
1715         intel_init_pch_refclk(dev_priv);
1716
1717         /*
1718          * Interrupts have to be enabled before any batches are run. If not the
1719          * GPU will hang. i915_gem_init_hw() will initiate batches to
1720          * update/restore the context.
1721          *
1722          * drm_mode_config_reset() needs AUX interrupts.
1723          *
1724          * Modeset enabling in intel_modeset_init_hw() also needs working
1725          * interrupts.
1726          */
1727         intel_runtime_pm_enable_interrupts(dev_priv);
1728
1729         drm_mode_config_reset(dev);
1730
1731         i915_gem_resume(dev_priv);
1732
1733         intel_modeset_init_hw(dev);
1734         intel_init_clock_gating(dev_priv);
1735
1736         spin_lock_irq(&dev_priv->irq_lock);
1737         if (dev_priv->display.hpd_irq_setup)
1738                 dev_priv->display.hpd_irq_setup(dev_priv);
1739         spin_unlock_irq(&dev_priv->irq_lock);
1740
1741         intel_dp_mst_resume(dev);
1742
1743         intel_display_resume(dev);
1744
1745         drm_kms_helper_poll_enable(dev);
1746
1747         /*
1748          * ... but also need to make sure that hotplug processing
1749          * doesn't cause havoc. Like in the driver load code we don't
1750          * bother with the tiny race here where we might loose hotplug
1751          * notifications.
1752          * */
1753         intel_hpd_init(dev_priv);
1754
1755         intel_opregion_register(dev_priv);
1756
1757         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1758
1759         mutex_lock(&dev_priv->modeset_restore_lock);
1760         dev_priv->modeset_restore = MODESET_DONE;
1761         mutex_unlock(&dev_priv->modeset_restore_lock);
1762
1763         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1764
1765         enable_rpm_wakeref_asserts(dev_priv);
1766
1767         return 0;
1768 }
1769
1770 static int i915_drm_resume_early(struct drm_device *dev)
1771 {
1772         struct drm_i915_private *dev_priv = to_i915(dev);
1773         struct pci_dev *pdev = dev_priv->drm.pdev;
1774         int ret;
1775
1776         /*
1777          * We have a resume ordering issue with the snd-hda driver also
1778          * requiring our device to be power up. Due to the lack of a
1779          * parent/child relationship we currently solve this with an early
1780          * resume hook.
1781          *
1782          * FIXME: This should be solved with a special hdmi sink device or
1783          * similar so that power domains can be employed.
1784          */
1785
1786         /*
1787          * Note that we need to set the power state explicitly, since we
1788          * powered off the device during freeze and the PCI core won't power
1789          * it back up for us during thaw. Powering off the device during
1790          * freeze is not a hard requirement though, and during the
1791          * suspend/resume phases the PCI core makes sure we get here with the
1792          * device powered on. So in case we change our freeze logic and keep
1793          * the device powered we can also remove the following set power state
1794          * call.
1795          */
1796         ret = pci_set_power_state(pdev, PCI_D0);
1797         if (ret) {
1798                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1799                 goto out;
1800         }
1801
1802         /*
1803          * Note that pci_enable_device() first enables any parent bridge
1804          * device and only then sets the power state for this device. The
1805          * bridge enabling is a nop though, since bridge devices are resumed
1806          * first. The order of enabling power and enabling the device is
1807          * imposed by the PCI core as described above, so here we preserve the
1808          * same order for the freeze/thaw phases.
1809          *
1810          * TODO: eventually we should remove pci_disable_device() /
1811          * pci_enable_enable_device() from suspend/resume. Due to how they
1812          * depend on the device enable refcount we can't anyway depend on them
1813          * disabling/enabling the device.
1814          */
1815         if (pci_enable_device(pdev)) {
1816                 ret = -EIO;
1817                 goto out;
1818         }
1819
1820         pci_set_master(pdev);
1821
1822         disable_rpm_wakeref_asserts(dev_priv);
1823
1824         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1825                 ret = vlv_resume_prepare(dev_priv, false);
1826         if (ret)
1827                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1828                           ret);
1829
1830         intel_uncore_resume_early(dev_priv);
1831
1832         if (IS_GEN9_LP(dev_priv)) {
1833                 if (!dev_priv->suspended_to_idle)
1834                         gen9_sanitize_dc_state(dev_priv);
1835                 bxt_disable_dc9(dev_priv);
1836         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1837                 hsw_disable_pc8(dev_priv);
1838         }
1839
1840         intel_uncore_sanitize(dev_priv);
1841
1842         if (IS_GEN9_LP(dev_priv) ||
1843             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1844                 intel_power_domains_init_hw(dev_priv, true);
1845
1846         i915_gem_sanitize(dev_priv);
1847
1848         enable_rpm_wakeref_asserts(dev_priv);
1849
1850 out:
1851         dev_priv->suspended_to_idle = false;
1852
1853         return ret;
1854 }
1855
1856 static int i915_resume_switcheroo(struct drm_device *dev)
1857 {
1858         int ret;
1859
1860         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1861                 return 0;
1862
1863         ret = i915_drm_resume_early(dev);
1864         if (ret)
1865                 return ret;
1866
1867         return i915_drm_resume(dev);
1868 }
1869
1870 /**
1871  * i915_reset - reset chip after a hang
1872  * @i915: #drm_i915_private to reset
1873  * @flags: Instructions
1874  *
1875  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1876  * on failure.
1877  *
1878  * Caller must hold the struct_mutex.
1879  *
1880  * Procedure is fairly simple:
1881  *   - reset the chip using the reset reg
1882  *   - re-init context state
1883  *   - re-init hardware status page
1884  *   - re-init ring buffer
1885  *   - re-init interrupt state
1886  *   - re-init display
1887  */
1888 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1889 {
1890         struct i915_gpu_error *error = &i915->gpu_error;
1891         int ret;
1892         int i;
1893
1894         might_sleep();
1895         lockdep_assert_held(&i915->drm.struct_mutex);
1896         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1897
1898         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1899                 return;
1900
1901         /* Clear any previous failed attempts at recovery. Time to try again. */
1902         if (!i915_gem_unset_wedged(i915))
1903                 goto wakeup;
1904
1905         if (!(flags & I915_RESET_QUIET))
1906                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1907         error->reset_count++;
1908
1909         disable_irq(i915->drm.irq);
1910         ret = i915_gem_reset_prepare(i915);
1911         if (ret) {
1912                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1913                 intel_gpu_reset(i915, ALL_ENGINES);
1914                 goto taint;
1915         }
1916
1917         if (!intel_has_gpu_reset(i915)) {
1918                 if (i915_modparams.reset)
1919                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1920                 else
1921                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1922                 goto error;
1923         }
1924
1925         for (i = 0; i < 3; i++) {
1926                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1927                 if (ret == 0)
1928                         break;
1929
1930                 msleep(100);
1931         }
1932         if (ret) {
1933                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1934                 goto taint;
1935         }
1936
1937         /* Ok, now get things going again... */
1938
1939         /*
1940          * Everything depends on having the GTT running, so we need to start
1941          * there.
1942          */
1943         ret = i915_ggtt_enable_hw(i915);
1944         if (ret) {
1945                 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1946                 goto error;
1947         }
1948
1949         i915_gem_reset(i915);
1950         intel_overlay_reset(i915);
1951
1952         /*
1953          * Next we need to restore the context, but we don't use those
1954          * yet either...
1955          *
1956          * Ring buffer needs to be re-initialized in the KMS case, or if X
1957          * was running at the time of the reset (i.e. we weren't VT
1958          * switched away).
1959          */
1960         ret = i915_gem_init_hw(i915);
1961         if (ret) {
1962                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1963                 goto error;
1964         }
1965
1966         i915_queue_hangcheck(i915);
1967
1968 finish:
1969         i915_gem_reset_finish(i915);
1970         enable_irq(i915->drm.irq);
1971
1972 wakeup:
1973         clear_bit(I915_RESET_HANDOFF, &error->flags);
1974         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1975         return;
1976
1977 taint:
1978         /*
1979          * History tells us that if we cannot reset the GPU now, we
1980          * never will. This then impacts everything that is run
1981          * subsequently. On failing the reset, we mark the driver
1982          * as wedged, preventing further execution on the GPU.
1983          * We also want to go one step further and add a taint to the
1984          * kernel so that any subsequent faults can be traced back to
1985          * this failure. This is important for CI, where if the
1986          * GPU/driver fails we would like to reboot and restart testing
1987          * rather than continue on into oblivion. For everyone else,
1988          * the system should still plod along, but they have been warned!
1989          */
1990         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1991 error:
1992         i915_gem_set_wedged(i915);
1993         i915_gem_retire_requests(i915);
1994         goto finish;
1995 }
1996
1997 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
1998                                         struct intel_engine_cs *engine)
1999 {
2000         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2001 }
2002
2003 /**
2004  * i915_reset_engine - reset GPU engine to recover from a hang
2005  * @engine: engine to reset
2006  * @flags: options
2007  *
2008  * Reset a specific GPU engine. Useful if a hang is detected.
2009  * Returns zero on successful reset or otherwise an error code.
2010  *
2011  * Procedure is:
2012  *  - identifies the request that caused the hang and it is dropped
2013  *  - reset engine (which will force the engine to idle)
2014  *  - re-init/configure engine
2015  */
2016 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2017 {
2018         struct i915_gpu_error *error = &engine->i915->gpu_error;
2019         struct drm_i915_gem_request *active_request;
2020         int ret;
2021
2022         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2023
2024         active_request = i915_gem_reset_prepare_engine(engine);
2025         if (IS_ERR_OR_NULL(active_request)) {
2026                 /* Either the previous reset failed, or we pardon the reset. */
2027                 ret = PTR_ERR(active_request);
2028                 goto out;
2029         }
2030
2031         if (!(flags & I915_RESET_QUIET)) {
2032                 dev_notice(engine->i915->drm.dev,
2033                            "Resetting %s after gpu hang\n", engine->name);
2034         }
2035         error->reset_engine_count[engine->id]++;
2036
2037         if (!engine->i915->guc.execbuf_client)
2038                 ret = intel_gt_reset_engine(engine->i915, engine);
2039         else
2040                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2041         if (ret) {
2042                 /* If we fail here, we expect to fallback to a global reset */
2043                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2044                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2045                                  engine->name, ret);
2046                 goto out;
2047         }
2048
2049         /*
2050          * The request that caused the hang is stuck on elsp, we know the
2051          * active request and can drop it, adjust head to skip the offending
2052          * request to resume executing remaining requests in the queue.
2053          */
2054         i915_gem_reset_engine(engine, active_request);
2055
2056         /*
2057          * The engine and its registers (and workarounds in case of render)
2058          * have been reset to their default values. Follow the init_ring
2059          * process to program RING_MODE, HWSP and re-enable submission.
2060          */
2061         ret = engine->init_hw(engine);
2062         if (ret)
2063                 goto out;
2064
2065 out:
2066         i915_gem_reset_finish_engine(engine);
2067         return ret;
2068 }
2069
2070 static int i915_pm_suspend(struct device *kdev)
2071 {
2072         struct pci_dev *pdev = to_pci_dev(kdev);
2073         struct drm_device *dev = pci_get_drvdata(pdev);
2074
2075         if (!dev) {
2076                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2077                 return -ENODEV;
2078         }
2079
2080         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2081                 return 0;
2082
2083         return i915_drm_suspend(dev);
2084 }
2085
2086 static int i915_pm_suspend_late(struct device *kdev)
2087 {
2088         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2089
2090         /*
2091          * We have a suspend ordering issue with the snd-hda driver also
2092          * requiring our device to be power up. Due to the lack of a
2093          * parent/child relationship we currently solve this with an late
2094          * suspend hook.
2095          *
2096          * FIXME: This should be solved with a special hdmi sink device or
2097          * similar so that power domains can be employed.
2098          */
2099         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2100                 return 0;
2101
2102         return i915_drm_suspend_late(dev, false);
2103 }
2104
2105 static int i915_pm_poweroff_late(struct device *kdev)
2106 {
2107         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2108
2109         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2110                 return 0;
2111
2112         return i915_drm_suspend_late(dev, true);
2113 }
2114
2115 static int i915_pm_resume_early(struct device *kdev)
2116 {
2117         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2118
2119         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2120                 return 0;
2121
2122         return i915_drm_resume_early(dev);
2123 }
2124
2125 static int i915_pm_resume(struct device *kdev)
2126 {
2127         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2128
2129         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2130                 return 0;
2131
2132         return i915_drm_resume(dev);
2133 }
2134
2135 /* freeze: before creating the hibernation_image */
2136 static int i915_pm_freeze(struct device *kdev)
2137 {
2138         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2139         int ret;
2140
2141         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2142                 ret = i915_drm_suspend(dev);
2143                 if (ret)
2144                         return ret;
2145         }
2146
2147         ret = i915_gem_freeze(kdev_to_i915(kdev));
2148         if (ret)
2149                 return ret;
2150
2151         return 0;
2152 }
2153
2154 static int i915_pm_freeze_late(struct device *kdev)
2155 {
2156         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2157         int ret;
2158
2159         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2160                 ret = i915_drm_suspend_late(dev, true);
2161                 if (ret)
2162                         return ret;
2163         }
2164
2165         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2166         if (ret)
2167                 return ret;
2168
2169         return 0;
2170 }
2171
2172 /* thaw: called after creating the hibernation image, but before turning off. */
2173 static int i915_pm_thaw_early(struct device *kdev)
2174 {
2175         return i915_pm_resume_early(kdev);
2176 }
2177
2178 static int i915_pm_thaw(struct device *kdev)
2179 {
2180         return i915_pm_resume(kdev);
2181 }
2182
2183 /* restore: called after loading the hibernation image. */
2184 static int i915_pm_restore_early(struct device *kdev)
2185 {
2186         return i915_pm_resume_early(kdev);
2187 }
2188
2189 static int i915_pm_restore(struct device *kdev)
2190 {
2191         return i915_pm_resume(kdev);
2192 }
2193
2194 /*
2195  * Save all Gunit registers that may be lost after a D3 and a subsequent
2196  * S0i[R123] transition. The list of registers needing a save/restore is
2197  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2198  * registers in the following way:
2199  * - Driver: saved/restored by the driver
2200  * - Punit : saved/restored by the Punit firmware
2201  * - No, w/o marking: no need to save/restore, since the register is R/O or
2202  *                    used internally by the HW in a way that doesn't depend
2203  *                    keeping the content across a suspend/resume.
2204  * - Debug : used for debugging
2205  *
2206  * We save/restore all registers marked with 'Driver', with the following
2207  * exceptions:
2208  * - Registers out of use, including also registers marked with 'Debug'.
2209  *   These have no effect on the driver's operation, so we don't save/restore
2210  *   them to reduce the overhead.
2211  * - Registers that are fully setup by an initialization function called from
2212  *   the resume path. For example many clock gating and RPS/RC6 registers.
2213  * - Registers that provide the right functionality with their reset defaults.
2214  *
2215  * TODO: Except for registers that based on the above 3 criteria can be safely
2216  * ignored, we save/restore all others, practically treating the HW context as
2217  * a black-box for the driver. Further investigation is needed to reduce the
2218  * saved/restored registers even further, by following the same 3 criteria.
2219  */
2220 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2221 {
2222         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2223         int i;
2224
2225         /* GAM 0x4000-0x4770 */
2226         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2227         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2228         s->arb_mode             = I915_READ(ARB_MODE);
2229         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2230         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2231
2232         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2233                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2234
2235         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2236         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2237
2238         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2239         s->ecochk               = I915_READ(GAM_ECOCHK);
2240         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2241         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2242
2243         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2244
2245         /* MBC 0x9024-0x91D0, 0x8500 */
2246         s->g3dctl               = I915_READ(VLV_G3DCTL);
2247         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2248         s->mbctl                = I915_READ(GEN6_MBCTL);
2249
2250         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2251         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2252         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2253         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2254         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2255         s->rstctl               = I915_READ(GEN6_RSTCTL);
2256         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2257
2258         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2259         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2260         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2261         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2262         s->ecobus               = I915_READ(ECOBUS);
2263         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2264         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2265         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2266         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2267         s->rcedata              = I915_READ(VLV_RCEDATA);
2268         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2269
2270         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2271         s->gt_imr               = I915_READ(GTIMR);
2272         s->gt_ier               = I915_READ(GTIER);
2273         s->pm_imr               = I915_READ(GEN6_PMIMR);
2274         s->pm_ier               = I915_READ(GEN6_PMIER);
2275
2276         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2277                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2278
2279         /* GT SA CZ domain, 0x100000-0x138124 */
2280         s->tilectl              = I915_READ(TILECTL);
2281         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2282         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2283         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2284         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2285
2286         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2287         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2288         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2289         s->pcbr                 = I915_READ(VLV_PCBR);
2290         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2291
2292         /*
2293          * Not saving any of:
2294          * DFT,         0x9800-0x9EC0
2295          * SARB,        0xB000-0xB1FC
2296          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2297          * PCI CFG
2298          */
2299 }
2300
2301 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2302 {
2303         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2304         u32 val;
2305         int i;
2306
2307         /* GAM 0x4000-0x4770 */
2308         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2309         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2310         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2311         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2312         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2313
2314         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2315                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2316
2317         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2318         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2319
2320         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2321         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2322         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2323         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2324
2325         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2326
2327         /* MBC 0x9024-0x91D0, 0x8500 */
2328         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2329         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2330         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2331
2332         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2333         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2334         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2335         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2336         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2337         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2338         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2339
2340         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2341         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2342         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2343         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2344         I915_WRITE(ECOBUS,              s->ecobus);
2345         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2346         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2347         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2348         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2349         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2350         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2351
2352         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2353         I915_WRITE(GTIMR,               s->gt_imr);
2354         I915_WRITE(GTIER,               s->gt_ier);
2355         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2356         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2357
2358         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2359                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2360
2361         /* GT SA CZ domain, 0x100000-0x138124 */
2362         I915_WRITE(TILECTL,                     s->tilectl);
2363         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2364         /*
2365          * Preserve the GT allow wake and GFX force clock bit, they are not
2366          * be restored, as they are used to control the s0ix suspend/resume
2367          * sequence by the caller.
2368          */
2369         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2370         val &= VLV_GTLC_ALLOWWAKEREQ;
2371         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2372         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2373
2374         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2375         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2376         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2377         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2378
2379         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2380
2381         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2382         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2383         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2384         I915_WRITE(VLV_PCBR,                    s->pcbr);
2385         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2386 }
2387
2388 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2389                                   u32 mask, u32 val)
2390 {
2391         /* The HW does not like us polling for PW_STATUS frequently, so
2392          * use the sleeping loop rather than risk the busy spin within
2393          * intel_wait_for_register().
2394          *
2395          * Transitioning between RC6 states should be at most 2ms (see
2396          * valleyview_enable_rps) so use a 3ms timeout.
2397          */
2398         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2399                         3);
2400 }
2401
2402 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2403 {
2404         u32 val;
2405         int err;
2406
2407         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2408         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2409         if (force_on)
2410                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2411         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2412
2413         if (!force_on)
2414                 return 0;
2415
2416         err = intel_wait_for_register(dev_priv,
2417                                       VLV_GTLC_SURVIVABILITY_REG,
2418                                       VLV_GFX_CLK_STATUS_BIT,
2419                                       VLV_GFX_CLK_STATUS_BIT,
2420                                       20);
2421         if (err)
2422                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2423                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2424
2425         return err;
2426 }
2427
2428 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2429 {
2430         u32 mask;
2431         u32 val;
2432         int err;
2433
2434         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2435         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2436         if (allow)
2437                 val |= VLV_GTLC_ALLOWWAKEREQ;
2438         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2439         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2440
2441         mask = VLV_GTLC_ALLOWWAKEACK;
2442         val = allow ? mask : 0;
2443
2444         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2445         if (err)
2446                 DRM_ERROR("timeout disabling GT waking\n");
2447
2448         return err;
2449 }
2450
2451 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2452                                   bool wait_for_on)
2453 {
2454         u32 mask;
2455         u32 val;
2456
2457         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2458         val = wait_for_on ? mask : 0;
2459
2460         /*
2461          * RC6 transitioning can be delayed up to 2 msec (see
2462          * valleyview_enable_rps), use 3 msec for safety.
2463          */
2464         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2465                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2466                           onoff(wait_for_on));
2467 }
2468
2469 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2470 {
2471         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2472                 return;
2473
2474         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2475         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2476 }
2477
2478 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2479 {
2480         u32 mask;
2481         int err;
2482
2483         /*
2484          * Bspec defines the following GT well on flags as debug only, so
2485          * don't treat them as hard failures.
2486          */
2487         vlv_wait_for_gt_wells(dev_priv, false);
2488
2489         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2490         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2491
2492         vlv_check_no_gt_access(dev_priv);
2493
2494         err = vlv_force_gfx_clock(dev_priv, true);
2495         if (err)
2496                 goto err1;
2497
2498         err = vlv_allow_gt_wake(dev_priv, false);
2499         if (err)
2500                 goto err2;
2501
2502         if (!IS_CHERRYVIEW(dev_priv))
2503                 vlv_save_gunit_s0ix_state(dev_priv);
2504
2505         err = vlv_force_gfx_clock(dev_priv, false);
2506         if (err)
2507                 goto err2;
2508
2509         return 0;
2510
2511 err2:
2512         /* For safety always re-enable waking and disable gfx clock forcing */
2513         vlv_allow_gt_wake(dev_priv, true);
2514 err1:
2515         vlv_force_gfx_clock(dev_priv, false);
2516
2517         return err;
2518 }
2519
2520 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2521                                 bool rpm_resume)
2522 {
2523         int err;
2524         int ret;
2525
2526         /*
2527          * If any of the steps fail just try to continue, that's the best we
2528          * can do at this point. Return the first error code (which will also
2529          * leave RPM permanently disabled).
2530          */
2531         ret = vlv_force_gfx_clock(dev_priv, true);
2532
2533         if (!IS_CHERRYVIEW(dev_priv))
2534                 vlv_restore_gunit_s0ix_state(dev_priv);
2535
2536         err = vlv_allow_gt_wake(dev_priv, true);
2537         if (!ret)
2538                 ret = err;
2539
2540         err = vlv_force_gfx_clock(dev_priv, false);
2541         if (!ret)
2542                 ret = err;
2543
2544         vlv_check_no_gt_access(dev_priv);
2545
2546         if (rpm_resume)
2547                 intel_init_clock_gating(dev_priv);
2548
2549         return ret;
2550 }
2551
2552 static int intel_runtime_suspend(struct device *kdev)
2553 {
2554         struct pci_dev *pdev = to_pci_dev(kdev);
2555         struct drm_device *dev = pci_get_drvdata(pdev);
2556         struct drm_i915_private *dev_priv = to_i915(dev);
2557         int ret;
2558
2559         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2560                 return -ENODEV;
2561
2562         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2563                 return -ENODEV;
2564
2565         DRM_DEBUG_KMS("Suspending device\n");
2566
2567         disable_rpm_wakeref_asserts(dev_priv);
2568
2569         /*
2570          * We are safe here against re-faults, since the fault handler takes
2571          * an RPM reference.
2572          */
2573         i915_gem_runtime_suspend(dev_priv);
2574
2575         intel_guc_suspend(dev_priv);
2576
2577         intel_runtime_pm_disable_interrupts(dev_priv);
2578
2579         intel_uncore_suspend(dev_priv);
2580
2581         ret = 0;
2582         if (IS_GEN9_LP(dev_priv)) {
2583                 bxt_display_core_uninit(dev_priv);
2584                 bxt_enable_dc9(dev_priv);
2585         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2586                 hsw_enable_pc8(dev_priv);
2587         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2588                 ret = vlv_suspend_complete(dev_priv);
2589         }
2590
2591         if (ret) {
2592                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2593                 intel_uncore_runtime_resume(dev_priv);
2594
2595                 intel_runtime_pm_enable_interrupts(dev_priv);
2596
2597                 enable_rpm_wakeref_asserts(dev_priv);
2598
2599                 return ret;
2600         }
2601
2602         enable_rpm_wakeref_asserts(dev_priv);
2603         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2604
2605         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2606                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2607
2608         dev_priv->runtime_pm.suspended = true;
2609
2610         /*
2611          * FIXME: We really should find a document that references the arguments
2612          * used below!
2613          */
2614         if (IS_BROADWELL(dev_priv)) {
2615                 /*
2616                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2617                  * being detected, and the call we do at intel_runtime_resume()
2618                  * won't be able to restore them. Since PCI_D3hot matches the
2619                  * actual specification and appears to be working, use it.
2620                  */
2621                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2622         } else {
2623                 /*
2624                  * current versions of firmware which depend on this opregion
2625                  * notification have repurposed the D1 definition to mean
2626                  * "runtime suspended" vs. what you would normally expect (D3)
2627                  * to distinguish it from notifications that might be sent via
2628                  * the suspend path.
2629                  */
2630                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2631         }
2632
2633         assert_forcewakes_inactive(dev_priv);
2634
2635         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2636                 intel_hpd_poll_init(dev_priv);
2637
2638         DRM_DEBUG_KMS("Device suspended\n");
2639         return 0;
2640 }
2641
2642 static int intel_runtime_resume(struct device *kdev)
2643 {
2644         struct pci_dev *pdev = to_pci_dev(kdev);
2645         struct drm_device *dev = pci_get_drvdata(pdev);
2646         struct drm_i915_private *dev_priv = to_i915(dev);
2647         int ret = 0;
2648
2649         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2650                 return -ENODEV;
2651
2652         DRM_DEBUG_KMS("Resuming device\n");
2653
2654         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2655         disable_rpm_wakeref_asserts(dev_priv);
2656
2657         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2658         dev_priv->runtime_pm.suspended = false;
2659         if (intel_uncore_unclaimed_mmio(dev_priv))
2660                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2661
2662         intel_guc_resume(dev_priv);
2663
2664         if (IS_GEN9_LP(dev_priv)) {
2665                 bxt_disable_dc9(dev_priv);
2666                 bxt_display_core_init(dev_priv, true);
2667                 if (dev_priv->csr.dmc_payload &&
2668                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2669                         gen9_enable_dc5(dev_priv);
2670         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2671                 hsw_disable_pc8(dev_priv);
2672         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2673                 ret = vlv_resume_prepare(dev_priv, true);
2674         }
2675
2676         intel_uncore_runtime_resume(dev_priv);
2677
2678         /*
2679          * No point of rolling back things in case of an error, as the best
2680          * we can do is to hope that things will still work (and disable RPM).
2681          */
2682         i915_gem_init_swizzling(dev_priv);
2683         i915_gem_restore_fences(dev_priv);
2684
2685         intel_runtime_pm_enable_interrupts(dev_priv);
2686
2687         /*
2688          * On VLV/CHV display interrupts are part of the display
2689          * power well, so hpd is reinitialized from there. For
2690          * everyone else do it here.
2691          */
2692         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2693                 intel_hpd_init(dev_priv);
2694
2695         intel_enable_ipc(dev_priv);
2696
2697         enable_rpm_wakeref_asserts(dev_priv);
2698
2699         if (ret)
2700                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2701         else
2702                 DRM_DEBUG_KMS("Device resumed\n");
2703
2704         return ret;
2705 }
2706
2707 const struct dev_pm_ops i915_pm_ops = {
2708         /*
2709          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2710          * PMSG_RESUME]
2711          */
2712         .suspend = i915_pm_suspend,
2713         .suspend_late = i915_pm_suspend_late,
2714         .resume_early = i915_pm_resume_early,
2715         .resume = i915_pm_resume,
2716
2717         /*
2718          * S4 event handlers
2719          * @freeze, @freeze_late    : called (1) before creating the
2720          *                            hibernation image [PMSG_FREEZE] and
2721          *                            (2) after rebooting, before restoring
2722          *                            the image [PMSG_QUIESCE]
2723          * @thaw, @thaw_early       : called (1) after creating the hibernation
2724          *                            image, before writing it [PMSG_THAW]
2725          *                            and (2) after failing to create or
2726          *                            restore the image [PMSG_RECOVER]
2727          * @poweroff, @poweroff_late: called after writing the hibernation
2728          *                            image, before rebooting [PMSG_HIBERNATE]
2729          * @restore, @restore_early : called after rebooting and restoring the
2730          *                            hibernation image [PMSG_RESTORE]
2731          */
2732         .freeze = i915_pm_freeze,
2733         .freeze_late = i915_pm_freeze_late,
2734         .thaw_early = i915_pm_thaw_early,
2735         .thaw = i915_pm_thaw,
2736         .poweroff = i915_pm_suspend,
2737         .poweroff_late = i915_pm_poweroff_late,
2738         .restore_early = i915_pm_restore_early,
2739         .restore = i915_pm_restore,
2740
2741         /* S0ix (via runtime suspend) event handlers */
2742         .runtime_suspend = intel_runtime_suspend,
2743         .runtime_resume = intel_runtime_resume,
2744 };
2745
2746 static const struct vm_operations_struct i915_gem_vm_ops = {
2747         .fault = i915_gem_fault,
2748         .open = drm_gem_vm_open,
2749         .close = drm_gem_vm_close,
2750 };
2751
2752 static const struct file_operations i915_driver_fops = {
2753         .owner = THIS_MODULE,
2754         .open = drm_open,
2755         .release = drm_release,
2756         .unlocked_ioctl = drm_ioctl,
2757         .mmap = drm_gem_mmap,
2758         .poll = drm_poll,
2759         .read = drm_read,
2760         .compat_ioctl = i915_compat_ioctl,
2761         .llseek = noop_llseek,
2762 };
2763
2764 static int
2765 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2766                           struct drm_file *file)
2767 {
2768         return -ENODEV;
2769 }
2770
2771 static const struct drm_ioctl_desc i915_ioctls[] = {
2772         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2773         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2774         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2775         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2776         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2777         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2778         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2779         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2780         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2781         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2782         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2783         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2784         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2785         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2786         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2787         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2788         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2789         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2790         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2791         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2792         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2793         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2794         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2795         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2796         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2797         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2798         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2799         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2800         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2801         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2802         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2803         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2804         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2805         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2806         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2807         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2808         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2809         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2810         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2812         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2813         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2815         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2818         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2821         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2822         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2827 };
2828
2829 static struct drm_driver driver = {
2830         /* Don't use MTRRs here; the Xserver or userspace app should
2831          * deal with them for Intel hardware.
2832          */
2833         .driver_features =
2834             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2835             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2836         .release = i915_driver_release,
2837         .open = i915_driver_open,
2838         .lastclose = i915_driver_lastclose,
2839         .postclose = i915_driver_postclose,
2840
2841         .gem_close_object = i915_gem_close_object,
2842         .gem_free_object_unlocked = i915_gem_free_object,
2843         .gem_vm_ops = &i915_gem_vm_ops,
2844
2845         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2846         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2847         .gem_prime_export = i915_gem_prime_export,
2848         .gem_prime_import = i915_gem_prime_import,
2849
2850         .dumb_create = i915_gem_dumb_create,
2851         .dumb_map_offset = i915_gem_mmap_gtt,
2852         .ioctls = i915_ioctls,
2853         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2854         .fops = &i915_driver_fops,
2855         .name = DRIVER_NAME,
2856         .desc = DRIVER_DESC,
2857         .date = DRIVER_DATE,
2858         .major = DRIVER_MAJOR,
2859         .minor = DRIVER_MINOR,
2860         .patchlevel = DRIVER_PATCHLEVEL,
2861 };
2862
2863 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2864 #include "selftests/mock_drm.c"
2865 #endif