drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 139                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 140                 else
 141                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 142                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 143         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 144                 ret = PCH_SPT;
 145                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 146         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 147                 ret = PCH_CNP;
 148                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 149         }
 150
 151         return ret;
 152 }
 153
 154 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 155 {
 156         struct pci_dev *pch = NULL;
 157
 158         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 159          * (which really amounts to a PCH but no South Display).
 160          */
 161         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 162                 dev_priv->pch_type = PCH_NOP;
 163                 return;
 164         }
 165
 166         /*
 167          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 168          * make graphics device passthrough work easy for VMM, that only
 169          * need to expose ISA bridge to let driver know the real hardware
 170          * underneath. This is a requirement from virtualization team.
 171          *
 172          * In some virtualized environments (e.g. XEN), there is irrelevant
 173          * ISA bridge in the system. To work reliably, we should scan trhough
 174          * all the ISA bridge devices and check for the first match, instead
 175          * of only checking the first one.
 176          */
 177         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 178                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 179                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 180
 181                         dev_priv->pch_id = id;
 182
 183                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 184                                 dev_priv->pch_type = PCH_IBX;
 185                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 186                                 WARN_ON(!IS_GEN5(dev_priv));
 187                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_CPT;
 189                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 190                                 WARN_ON(!IS_GEN6(dev_priv) &&
 191                                         !IS_IVYBRIDGE(dev_priv));
 192                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 193                                 /* PantherPoint is CPT compatible */
 194                                 dev_priv->pch_type = PCH_CPT;
 195                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 196                                 WARN_ON(!IS_GEN6(dev_priv) &&
 197                                         !IS_IVYBRIDGE(dev_priv));
 198                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 199                                 dev_priv->pch_type = PCH_LPT;
 200                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 201                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 202                                         !IS_BROADWELL(dev_priv));
 203                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 204                                         IS_BDW_ULT(dev_priv));
 205                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 206                                 dev_priv->pch_type = PCH_LPT;
 207                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 208                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 209                                         !IS_BROADWELL(dev_priv));
 210                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 211                                         !IS_BDW_ULT(dev_priv));
 212                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
 213                                 /* WildcatPoint is LPT compatible */
 214                                 dev_priv->pch_type = PCH_LPT;
 215                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 216                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 217                                         !IS_BROADWELL(dev_priv));
 218                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 219                                         IS_BDW_ULT(dev_priv));
 220                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
 221                                 /* WildcatPoint is LPT compatible */
 222                                 dev_priv->pch_type = PCH_LPT;
 223                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 224                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 225                                         !IS_BROADWELL(dev_priv));
 226                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 227                                         !IS_BDW_ULT(dev_priv));
 228                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 229                                 dev_priv->pch_type = PCH_SPT;
 230                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 231                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 232                                         !IS_KABYLAKE(dev_priv));
 233                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 234                                 dev_priv->pch_type = PCH_SPT;
 235                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 236                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 237                                         !IS_KABYLAKE(dev_priv));
 238                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 239                                 dev_priv->pch_type = PCH_KBP;
 240                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 241                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 242                                         !IS_KABYLAKE(dev_priv));
 243                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 244                                 dev_priv->pch_type = PCH_CNP;
 245                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 246                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 247                                         !IS_COFFEELAKE(dev_priv));
 248                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 249                                 dev_priv->pch_type = PCH_CNP;
 250                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 251                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 252                                         !IS_COFFEELAKE(dev_priv));
 253                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 254                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 255                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 256                                     pch->subsystem_vendor ==
 257                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 258                                     pch->subsystem_device ==
 259                                             PCI_SUBDEVICE_ID_QEMU)) {
 260                                 dev_priv->pch_type =
 261                                         intel_virt_detect_pch(dev_priv);
 262                         } else
 263                                 continue;
 264
 265                         break;
 266                 }
 267         }
 268         if (!pch)
 269                 DRM_DEBUG_KMS("No PCH found.\n");
 270
 271         pci_dev_put(pch);
 272 }
 273
 274 static int i915_getparam(struct drm_device *dev, void *data,
 275                          struct drm_file *file_priv)
 276 {
 277         struct drm_i915_private *dev_priv = to_i915(dev);
 278         struct pci_dev *pdev = dev_priv->drm.pdev;
 279         drm_i915_getparam_t *param = data;
 280         int value;
 281
 282         switch (param->param) {
 283         case I915_PARAM_IRQ_ACTIVE:
 284         case I915_PARAM_ALLOW_BATCHBUFFER:
 285         case I915_PARAM_LAST_DISPATCH:
 286         case I915_PARAM_HAS_EXEC_CONSTANTS:
 287                 /* Reject all old ums/dri params. */
 288                 return -ENODEV;
 289         case I915_PARAM_CHIPSET_ID:
 290                 value = pdev->device;
 291                 break;
 292         case I915_PARAM_REVISION:
 293                 value = pdev->revision;
 294                 break;
 295         case I915_PARAM_NUM_FENCES_AVAIL:
 296                 value = dev_priv->num_fence_regs;
 297                 break;
 298         case I915_PARAM_HAS_OVERLAY:
 299                 value = dev_priv->overlay ? 1 : 0;
 300                 break;
 301         case I915_PARAM_HAS_BSD:
 302                 value = !!dev_priv->engine[VCS];
 303                 break;
 304         case I915_PARAM_HAS_BLT:
 305                 value = !!dev_priv->engine[BCS];
 306                 break;
 307         case I915_PARAM_HAS_VEBOX:
 308                 value = !!dev_priv->engine[VECS];
 309                 break;
 310         case I915_PARAM_HAS_BSD2:
 311                 value = !!dev_priv->engine[VCS2];
 312                 break;
 313         case I915_PARAM_HAS_LLC:
 314                 value = HAS_LLC(dev_priv);
 315                 break;
 316         case I915_PARAM_HAS_WT:
 317                 value = HAS_WT(dev_priv);
 318                 break;
 319         case I915_PARAM_HAS_ALIASING_PPGTT:
 320                 value = USES_PPGTT(dev_priv);
 321                 break;
 322         case I915_PARAM_HAS_SEMAPHORES:
 323                 value = i915.semaphores;
 324                 break;
 325         case I915_PARAM_HAS_SECURE_BATCHES:
 326                 value = capable(CAP_SYS_ADMIN);
 327                 break;
 328         case I915_PARAM_CMD_PARSER_VERSION:
 329                 value = i915_cmd_parser_get_version(dev_priv);
 330                 break;
 331         case I915_PARAM_SUBSLICE_TOTAL:
 332                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 333                 if (!value)
 334                         return -ENODEV;
 335                 break;
 336         case I915_PARAM_EU_TOTAL:
 337                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 338                 if (!value)
 339                         return -ENODEV;
 340                 break;
 341         case I915_PARAM_HAS_GPU_RESET:
 342                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 343                 if (value && intel_has_reset_engine(dev_priv))
 344                         value = 2;
 345                 break;
 346         case I915_PARAM_HAS_RESOURCE_STREAMER:
 347                 value = HAS_RESOURCE_STREAMER(dev_priv);
 348                 break;
 349         case I915_PARAM_HAS_POOLED_EU:
 350                 value = HAS_POOLED_EU(dev_priv);
 351                 break;
 352         case I915_PARAM_MIN_EU_IN_POOL:
 353                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 354                 break;
 355         case I915_PARAM_HUC_STATUS:
 356                 intel_runtime_pm_get(dev_priv);
 357                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 358                 intel_runtime_pm_put(dev_priv);
 359                 break;
 360         case I915_PARAM_MMAP_GTT_VERSION:
 361                 /* Though we've started our numbering from 1, and so class all
 362                  * earlier versions as 0, in effect their value is undefined as
 363                  * the ioctl will report EINVAL for the unknown param!
 364                  */
 365                 value = i915_gem_mmap_gtt_version();
 366                 break;
 367         case I915_PARAM_HAS_SCHEDULER:
 368                 value = dev_priv->engine[RCS] &&
 369                         dev_priv->engine[RCS]->schedule;
 370                 break;
 371         case I915_PARAM_MMAP_VERSION:
 372                 /* Remember to bump this if the version changes! */
 373         case I915_PARAM_HAS_GEM:
 374         case I915_PARAM_HAS_PAGEFLIPPING:
 375         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 376         case I915_PARAM_HAS_RELAXED_FENCING:
 377         case I915_PARAM_HAS_COHERENT_RINGS:
 378         case I915_PARAM_HAS_RELAXED_DELTA:
 379         case I915_PARAM_HAS_GEN7_SOL_RESET:
 380         case I915_PARAM_HAS_WAIT_TIMEOUT:
 381         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 382         case I915_PARAM_HAS_PINNED_BATCHES:
 383         case I915_PARAM_HAS_EXEC_NO_RELOC:
 384         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 385         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 386         case I915_PARAM_HAS_EXEC_SOFTPIN:
 387         case I915_PARAM_HAS_EXEC_ASYNC:
 388         case I915_PARAM_HAS_EXEC_FENCE:
 389         case I915_PARAM_HAS_EXEC_CAPTURE:
 390         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 391         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 392                 /* For the time being all of these are always true;
 393                  * if some supported hardware does not have one of these
 394                  * features this value needs to be provided from
 395                  * INTEL_INFO(), a feature macro, or similar.
 396                  */
 397                 value = 1;
 398                 break;
 399         case I915_PARAM_SLICE_MASK:
 400                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 401                 if (!value)
 402                         return -ENODEV;
 403                 break;
 404         case I915_PARAM_SUBSLICE_MASK:
 405                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 406                 if (!value)
 407                         return -ENODEV;
 408                 break;
 409         default:
 410                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 411                 return -EINVAL;
 412         }
 413
 414         if (put_user(value, param->value))
 415                 return -EFAULT;
 416
 417         return 0;
 418 }
 419
 420 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 421 {
 422         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 423         if (!dev_priv->bridge_dev) {
 424                 DRM_ERROR("bridge device not found\n");
 425                 return -1;
 426         }
 427         return 0;
 428 }
 429
 430 /* Allocate space for the MCH regs if needed, return nonzero on error */
 431 static int
 432 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 433 {
 434         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 435         u32 temp_lo, temp_hi = 0;
 436         u64 mchbar_addr;
 437         int ret;
 438
 439         if (INTEL_GEN(dev_priv) >= 4)
 440                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 441         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 442         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 443
 444         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 445 #ifdef CONFIG_PNP
 446         if (mchbar_addr &&
 447             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 448                 return 0;
 449 #endif
 450
 451         /* Get some space for it */
 452         dev_priv->mch_res.name = "i915 MCHBAR";
 453         dev_priv->mch_res.flags = IORESOURCE_MEM;
 454         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 455                                      &dev_priv->mch_res,
 456                                      MCHBAR_SIZE, MCHBAR_SIZE,
 457                                      PCIBIOS_MIN_MEM,
 458                                      0, pcibios_align_resource,
 459                                      dev_priv->bridge_dev);
 460         if (ret) {
 461                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 462                 dev_priv->mch_res.start = 0;
 463                 return ret;
 464         }
 465
 466         if (INTEL_GEN(dev_priv) >= 4)
 467                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 468                                        upper_32_bits(dev_priv->mch_res.start));
 469
 470         pci_write_config_dword(dev_priv->bridge_dev, reg,
 471                                lower_32_bits(dev_priv->mch_res.start));
 472         return 0;
 473 }
 474
 475 /* Setup MCHBAR if possible, return true if we should disable it again */
 476 static void
 477 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 478 {
 479         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 480         u32 temp;
 481         bool enabled;
 482
 483         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 484                 return;
 485
 486         dev_priv->mchbar_need_disable = false;
 487
 488         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 489                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 490                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 491         } else {
 492                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 493                 enabled = temp & 1;
 494         }
 495
 496         /* If it's already enabled, don't have to do anything */
 497         if (enabled)
 498                 return;
 499
 500         if (intel_alloc_mchbar_resource(dev_priv))
 501                 return;
 502
 503         dev_priv->mchbar_need_disable = true;
 504
 505         /* Space is allocated or reserved, so enable it. */
 506         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 507                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 508                                        temp | DEVEN_MCHBAR_EN);
 509         } else {
 510                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 511                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 512         }
 513 }
 514
 515 static void
 516 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 517 {
 518         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 519
 520         if (dev_priv->mchbar_need_disable) {
 521                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 522                         u32 deven_val;
 523
 524                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 525                                               &deven_val);
 526                         deven_val &= ~DEVEN_MCHBAR_EN;
 527                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 528                                                deven_val);
 529                 } else {
 530                         u32 mchbar_val;
 531
 532                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 533                                               &mchbar_val);
 534                         mchbar_val &= ~1;
 535                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 536                                                mchbar_val);
 537                 }
 538         }
 539
 540         if (dev_priv->mch_res.start)
 541                 release_resource(&dev_priv->mch_res);
 542 }
 543
 544 /* true = enable decode, false = disable decoder */
 545 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 546 {
 547         struct drm_i915_private *dev_priv = cookie;
 548
 549         intel_modeset_vga_set_state(dev_priv, state);
 550         if (state)
 551                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 552                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 553         else
 554                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 555 }
 556
 557 static int i915_resume_switcheroo(struct drm_device *dev);
 558 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 559
 560 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 561 {
 562         struct drm_device *dev = pci_get_drvdata(pdev);
 563         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 564
 565         if (state == VGA_SWITCHEROO_ON) {
 566                 pr_info("switched on\n");
 567                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 568                 /* i915 resume handler doesn't set to D0 */
 569                 pci_set_power_state(pdev, PCI_D0);
 570                 i915_resume_switcheroo(dev);
 571                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 572         } else {
 573                 pr_info("switched off\n");
 574                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 575                 i915_suspend_switcheroo(dev, pmm);
 576                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 577         }
 578 }
 579
 580 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 581 {
 582         struct drm_device *dev = pci_get_drvdata(pdev);
 583
 584         /*
 585          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 586          * locking inversion with the driver load path. And the access here is
 587          * completely racy anyway. So don't bother with locking for now.
 588          */
 589         return dev->open_count == 0;
 590 }
 591
 592 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 593         .set_gpu_state = i915_switcheroo_set_state,
 594         .reprobe = NULL,
 595         .can_switch = i915_switcheroo_can_switch,
 596 };
 597
 598 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 599 {
 600         /* Flush any outstanding unpin_work. */
 601         i915_gem_drain_workqueue(dev_priv);
 602
 603         mutex_lock(&dev_priv->drm.struct_mutex);
 604         intel_uc_fini_hw(dev_priv);
 605         i915_gem_cleanup_engines(dev_priv);
 606         i915_gem_contexts_fini(dev_priv);
 607         i915_gem_cleanup_userptr(dev_priv);
 608         mutex_unlock(&dev_priv->drm.struct_mutex);
 609
 610         i915_gem_drain_freed_objects(dev_priv);
 611
 612         WARN_ON(!list_empty(&dev_priv->contexts.list));
 613 }
 614
 615 static int i915_load_modeset_init(struct drm_device *dev)
 616 {
 617         struct drm_i915_private *dev_priv = to_i915(dev);
 618         struct pci_dev *pdev = dev_priv->drm.pdev;
 619         int ret;
 620
 621         if (i915_inject_load_failure())
 622                 return -ENODEV;
 623
 624         intel_bios_init(dev_priv);
 625
 626         /* If we have > 1 VGA cards, then we need to arbitrate access
 627          * to the common VGA resources.
 628          *
 629          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 630          * then we do not take part in VGA arbitration and the
 631          * vga_client_register() fails with -ENODEV.
 632          */
 633         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 634         if (ret && ret != -ENODEV)
 635                 goto out;
 636
 637         intel_register_dsm_handler();
 638
 639         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 640         if (ret)
 641                 goto cleanup_vga_client;
 642
 643         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 644         intel_update_rawclk(dev_priv);
 645
 646         intel_power_domains_init_hw(dev_priv, false);
 647
 648         intel_csr_ucode_init(dev_priv);
 649
 650         ret = intel_irq_install(dev_priv);
 651         if (ret)
 652                 goto cleanup_csr;
 653
 654         intel_setup_gmbus(dev_priv);
 655
 656         /* Important: The output setup functions called by modeset_init need
 657          * working irqs for e.g. gmbus and dp aux transfers. */
 658         ret = intel_modeset_init(dev);
 659         if (ret)
 660                 goto cleanup_irq;
 661
 662         intel_uc_init_fw(dev_priv);
 663
 664         ret = i915_gem_init(dev_priv);
 665         if (ret)
 666                 goto cleanup_uc;
 667
 668         intel_modeset_gem_init(dev);
 669
 670         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 671                 return 0;
 672
 673         ret = intel_fbdev_init(dev);
 674         if (ret)
 675                 goto cleanup_gem;
 676
 677         /* Only enable hotplug handling once the fbdev is fully set up. */
 678         intel_hpd_init(dev_priv);
 679
 680         drm_kms_helper_poll_init(dev);
 681
 682         return 0;
 683
 684 cleanup_gem:
 685         if (i915_gem_suspend(dev_priv))
 686                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 687         i915_gem_fini(dev_priv);
 688 cleanup_uc:
 689         intel_uc_fini_fw(dev_priv);
 690 cleanup_irq:
 691         drm_irq_uninstall(dev);
 692         intel_teardown_gmbus(dev_priv);
 693 cleanup_csr:
 694         intel_csr_ucode_fini(dev_priv);
 695         intel_power_domains_fini(dev_priv);
 696         vga_switcheroo_unregister_client(pdev);
 697 cleanup_vga_client:
 698         vga_client_register(pdev, NULL, NULL, NULL);
 699 out:
 700         return ret;
 701 }
 702
 703 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 704 {
 705         struct apertures_struct *ap;
 706         struct pci_dev *pdev = dev_priv->drm.pdev;
 707         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 708         bool primary;
 709         int ret;
 710
 711         ap = alloc_apertures(1);
 712         if (!ap)
 713                 return -ENOMEM;
 714
 715         ap->ranges[0].base = ggtt->mappable_base;
 716         ap->ranges[0].size = ggtt->mappable_end;
 717
 718         primary =
 719                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 720
 721         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 722
 723         kfree(ap);
 724
 725         return ret;
 726 }
 727
 728 #if !defined(CONFIG_VGA_CONSOLE)
 729 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 730 {
 731         return 0;
 732 }
 733 #elif !defined(CONFIG_DUMMY_CONSOLE)
 734 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 735 {
 736         return -ENODEV;
 737 }
 738 #else
 739 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 740 {
 741         int ret = 0;
 742
 743         DRM_INFO("Replacing VGA console driver\n");
 744
 745         console_lock();
 746         if (con_is_bound(&vga_con))
 747                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 748         if (ret == 0) {
 749                 ret = do_unregister_con_driver(&vga_con);
 750
 751                 /* Ignore "already unregistered". */
 752                 if (ret == -ENODEV)
 753                         ret = 0;
 754         }
 755         console_unlock();
 756
 757         return ret;
 758 }
 759 #endif
 760
 761 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 762 {
 763         /*
 764          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 765          * CHV x1 PHY (DP/HDMI D)
 766          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 767          */
 768         if (IS_CHERRYVIEW(dev_priv)) {
 769                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 770                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 771         } else if (IS_VALLEYVIEW(dev_priv)) {
 772                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 773         }
 774 }
 775
 776 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 777 {
 778         /*
 779          * The i915 workqueue is primarily used for batched retirement of
 780          * requests (and thus managing bo) once the task has been completed
 781          * by the GPU. i915_gem_retire_requests() is called directly when we
 782          * need high-priority retirement, such as waiting for an explicit
 783          * bo.
 784          *
 785          * It is also used for periodic low-priority events, such as
 786          * idle-timers and recording error state.
 787          *
 788          * All tasks on the workqueue are expected to acquire the dev mutex
 789          * so there is no point in running more than one instance of the
 790          * workqueue at any time.  Use an ordered one.
 791          */
 792         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 793         if (dev_priv->wq == NULL)
 794                 goto out_err;
 795
 796         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 797         if (dev_priv->hotplug.dp_wq == NULL)
 798                 goto out_free_wq;
 799
 800         return 0;
 801
 802 out_free_wq:
 803         destroy_workqueue(dev_priv->wq);
 804 out_err:
 805         DRM_ERROR("Failed to allocate workqueues.\n");
 806
 807         return -ENOMEM;
 808 }
 809
 810 static void i915_engines_cleanup(struct drm_i915_private *i915)
 811 {
 812         struct intel_engine_cs *engine;
 813         enum intel_engine_id id;
 814
 815         for_each_engine(engine, i915, id)
 816                 kfree(engine);
 817 }
 818
 819 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 820 {
 821         destroy_workqueue(dev_priv->hotplug.dp_wq);
 822         destroy_workqueue(dev_priv->wq);
 823 }
 824
 825 /*
 826  * We don't keep the workarounds for pre-production hardware, so we expect our
 827  * driver to fail on these machines in one way or another. A little warning on
 828  * dmesg may help both the user and the bug triagers.
 829  */
 830 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 831 {
 832         bool pre = false;
 833
 834         pre |= IS_HSW_EARLY_SDV(dev_priv);
 835         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 836         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 837
 838         if (pre) {
 839                 DRM_ERROR("This is a pre-production stepping. "
 840                           "It may not be fully functional.\n");
 841                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 842         }
 843 }
 844
 845 /**
 846  * i915_driver_init_early - setup state not requiring device access
 847  * @dev_priv: device private
 848  *
 849  * Initialize everything that is a "SW-only" state, that is state not
 850  * requiring accessing the device or exposing the driver via kernel internal
 851  * or userspace interfaces. Example steps belonging here: lock initialization,
 852  * system memory allocation, setting up device specific attributes and
 853  * function hooks not requiring accessing the device.
 854  */
 855 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 856                                   const struct pci_device_id *ent)
 857 {
 858         const struct intel_device_info *match_info =
 859                 (struct intel_device_info *)ent->driver_data;
 860         struct intel_device_info *device_info;
 861         int ret = 0;
 862
 863         if (i915_inject_load_failure())
 864                 return -ENODEV;
 865
 866         /* Setup the write-once "constant" device info */
 867         device_info = mkwrite_device_info(dev_priv);
 868         memcpy(device_info, match_info, sizeof(*device_info));
 869         device_info->device_id = dev_priv->drm.pdev->device;
 870
 871         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 872         device_info->gen_mask = BIT(device_info->gen - 1);
 873
 874         spin_lock_init(&dev_priv->irq_lock);
 875         spin_lock_init(&dev_priv->gpu_error.lock);
 876         mutex_init(&dev_priv->backlight_lock);
 877         spin_lock_init(&dev_priv->uncore.lock);
 878
 879         spin_lock_init(&dev_priv->mm.object_stat_lock);
 880         mutex_init(&dev_priv->sb_lock);
 881         mutex_init(&dev_priv->modeset_restore_lock);
 882         mutex_init(&dev_priv->av_mutex);
 883         mutex_init(&dev_priv->wm.wm_mutex);
 884         mutex_init(&dev_priv->pps_mutex);
 885
 886         intel_uc_init_early(dev_priv);
 887         i915_memcpy_init_early(dev_priv);
 888
 889         ret = i915_workqueues_init(dev_priv);
 890         if (ret < 0)
 891                 goto err_engines;
 892
 893         /* This must be called before any calls to HAS_PCH_* */
 894         intel_detect_pch(dev_priv);
 895
 896         intel_pm_setup(dev_priv);
 897         intel_init_dpio(dev_priv);
 898         intel_power_domains_init(dev_priv);
 899         intel_irq_init(dev_priv);
 900         intel_hangcheck_init(dev_priv);
 901         intel_init_display_hooks(dev_priv);
 902         intel_init_clock_gating_hooks(dev_priv);
 903         intel_init_audio_hooks(dev_priv);
 904         ret = i915_gem_load_init(dev_priv);
 905         if (ret < 0)
 906                 goto err_irq;
 907
 908         intel_display_crc_init(dev_priv);
 909
 910         intel_device_info_dump(dev_priv);
 911
 912         intel_detect_preproduction_hw(dev_priv);
 913
 914         i915_perf_init(dev_priv);
 915
 916         return 0;
 917
 918 err_irq:
 919         intel_irq_fini(dev_priv);
 920         i915_workqueues_cleanup(dev_priv);
 921 err_engines:
 922         i915_engines_cleanup(dev_priv);
 923         return ret;
 924 }
 925
 926 /**
 927  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 928  * @dev_priv: device private
 929  */
 930 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 931 {
 932         i915_perf_fini(dev_priv);
 933         i915_gem_load_cleanup(dev_priv);
 934         intel_irq_fini(dev_priv);
 935         i915_workqueues_cleanup(dev_priv);
 936         i915_engines_cleanup(dev_priv);
 937 }
 938
 939 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 940 {
 941         struct pci_dev *pdev = dev_priv->drm.pdev;
 942         int mmio_bar;
 943         int mmio_size;
 944
 945         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 946         /*
 947          * Before gen4, the registers and the GTT are behind different BARs.
 948          * However, from gen4 onwards, the registers and the GTT are shared
 949          * in the same BAR, so we want to restrict this ioremap from
 950          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 951          * the register BAR remains the same size for all the earlier
 952          * generations up to Ironlake.
 953          */
 954         if (INTEL_GEN(dev_priv) < 5)
 955                 mmio_size = 512 * 1024;
 956         else
 957                 mmio_size = 2 * 1024 * 1024;
 958         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 959         if (dev_priv->regs == NULL) {
 960                 DRM_ERROR("failed to map registers\n");
 961
 962                 return -EIO;
 963         }
 964
 965         /* Try to make sure MCHBAR is enabled before poking at it */
 966         intel_setup_mchbar(dev_priv);
 967
 968         return 0;
 969 }
 970
 971 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 972 {
 973         struct pci_dev *pdev = dev_priv->drm.pdev;
 974
 975         intel_teardown_mchbar(dev_priv);
 976         pci_iounmap(pdev, dev_priv->regs);
 977 }
 978
 979 /**
 980  * i915_driver_init_mmio - setup device MMIO
 981  * @dev_priv: device private
 982  *
 983  * Setup minimal device state necessary for MMIO accesses later in the
 984  * initialization sequence. The setup here should avoid any other device-wide
 985  * side effects or exposing the driver via kernel internal or user space
 986  * interfaces.
 987  */
 988 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 989 {
 990         int ret;
 991
 992         if (i915_inject_load_failure())
 993                 return -ENODEV;
 994
 995         if (i915_get_bridge_dev(dev_priv))
 996                 return -EIO;
 997
 998         ret = i915_mmio_setup(dev_priv);
 999         if (ret < 0)
1000                 goto err_bridge;
1001
1002         intel_uncore_init(dev_priv);
1003
1004         ret = intel_engines_init_mmio(dev_priv);
1005         if (ret)
1006                 goto err_uncore;
1007
1008         i915_gem_init_mmio(dev_priv);
1009
1010         return 0;
1011
1012 err_uncore:
1013         intel_uncore_fini(dev_priv);
1014 err_bridge:
1015         pci_dev_put(dev_priv->bridge_dev);
1016
1017         return ret;
1018 }
1019
1020 /**
1021  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1022  * @dev_priv: device private
1023  */
1024 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1025 {
1026         intel_uncore_fini(dev_priv);
1027         i915_mmio_cleanup(dev_priv);
1028         pci_dev_put(dev_priv->bridge_dev);
1029 }
1030
1031 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1032 {
1033         i915.enable_execlists =
1034                 intel_sanitize_enable_execlists(dev_priv,
1035                                                 i915.enable_execlists);
1036
1037         /*
1038          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1039          * user's requested state against the hardware/driver capabilities.  We
1040          * do this now so that we can print out any log messages once rather
1041          * than every time we check intel_enable_ppgtt().
1042          */
1043         i915.enable_ppgtt =
1044                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1045         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1046
1047         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1048         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1049
1050         intel_uc_sanitize_options(dev_priv);
1051
1052         intel_gvt_sanitize_options(dev_priv);
1053 }
1054
1055 /**
1056  * i915_driver_init_hw - setup state requiring device access
1057  * @dev_priv: device private
1058  *
1059  * Setup state that requires accessing the device, but doesn't require
1060  * exposing the driver via kernel internal or userspace interfaces.
1061  */
1062 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1063 {
1064         struct pci_dev *pdev = dev_priv->drm.pdev;
1065         int ret;
1066
1067         if (i915_inject_load_failure())
1068                 return -ENODEV;
1069
1070         intel_device_info_runtime_init(dev_priv);
1071
1072         intel_sanitize_options(dev_priv);
1073
1074         ret = i915_ggtt_probe_hw(dev_priv);
1075         if (ret)
1076                 return ret;
1077
1078         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1079          * otherwise the vga fbdev driver falls over. */
1080         ret = i915_kick_out_firmware_fb(dev_priv);
1081         if (ret) {
1082                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1083                 goto out_ggtt;
1084         }
1085
1086         ret = i915_kick_out_vgacon(dev_priv);
1087         if (ret) {
1088                 DRM_ERROR("failed to remove conflicting VGA console\n");
1089                 goto out_ggtt;
1090         }
1091
1092         ret = i915_ggtt_init_hw(dev_priv);
1093         if (ret)
1094                 return ret;
1095
1096         ret = i915_ggtt_enable_hw(dev_priv);
1097         if (ret) {
1098                 DRM_ERROR("failed to enable GGTT\n");
1099                 goto out_ggtt;
1100         }
1101
1102         pci_set_master(pdev);
1103
1104         /* overlay on gen2 is broken and can't address above 1G */
1105         if (IS_GEN2(dev_priv)) {
1106                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1107                 if (ret) {
1108                         DRM_ERROR("failed to set DMA mask\n");
1109
1110                         goto out_ggtt;
1111                 }
1112         }
1113
1114         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1115          * using 32bit addressing, overwriting memory if HWS is located
1116          * above 4GB.
1117          *
1118          * The documentation also mentions an issue with undefined
1119          * behaviour if any general state is accessed within a page above 4GB,
1120          * which also needs to be handled carefully.
1121          */
1122         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1123                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1124
1125                 if (ret) {
1126                         DRM_ERROR("failed to set DMA mask\n");
1127
1128                         goto out_ggtt;
1129                 }
1130         }
1131
1132         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1133                            PM_QOS_DEFAULT_VALUE);
1134
1135         intel_uncore_sanitize(dev_priv);
1136
1137         intel_opregion_setup(dev_priv);
1138
1139         i915_gem_load_init_fences(dev_priv);
1140
1141         /* On the 945G/GM, the chipset reports the MSI capability on the
1142          * integrated graphics even though the support isn't actually there
1143          * according to the published specs.  It doesn't appear to function
1144          * correctly in testing on 945G.
1145          * This may be a side effect of MSI having been made available for PEG
1146          * and the registers being closely associated.
1147          *
1148          * According to chipset errata, on the 965GM, MSI interrupts may
1149          * be lost or delayed, and was defeatured. MSI interrupts seem to
1150          * get lost on g4x as well, and interrupt delivery seems to stay
1151          * properly dead afterwards. So we'll just disable them for all
1152          * pre-gen5 chipsets.
1153          */
1154         if (INTEL_GEN(dev_priv) >= 5) {
1155                 if (pci_enable_msi(pdev) < 0)
1156                         DRM_DEBUG_DRIVER("can't enable MSI");
1157         }
1158
1159         ret = intel_gvt_init(dev_priv);
1160         if (ret)
1161                 goto out_ggtt;
1162
1163         return 0;
1164
1165 out_ggtt:
1166         i915_ggtt_cleanup_hw(dev_priv);
1167
1168         return ret;
1169 }
1170
1171 /**
1172  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1173  * @dev_priv: device private
1174  */
1175 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1176 {
1177         struct pci_dev *pdev = dev_priv->drm.pdev;
1178
1179         if (pdev->msi_enabled)
1180                 pci_disable_msi(pdev);
1181
1182         pm_qos_remove_request(&dev_priv->pm_qos);
1183         i915_ggtt_cleanup_hw(dev_priv);
1184 }
1185
1186 /**
1187  * i915_driver_register - register the driver with the rest of the system
1188  * @dev_priv: device private
1189  *
1190  * Perform any steps necessary to make the driver available via kernel
1191  * internal or userspace interfaces.
1192  */
1193 static void i915_driver_register(struct drm_i915_private *dev_priv)
1194 {
1195         struct drm_device *dev = &dev_priv->drm;
1196
1197         i915_gem_shrinker_init(dev_priv);
1198
1199         /*
1200          * Notify a valid surface after modesetting,
1201          * when running inside a VM.
1202          */
1203         if (intel_vgpu_active(dev_priv))
1204                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1205
1206         /* Reveal our presence to userspace */
1207         if (drm_dev_register(dev, 0) == 0) {
1208                 i915_debugfs_register(dev_priv);
1209                 i915_guc_log_register(dev_priv);
1210                 i915_setup_sysfs(dev_priv);
1211
1212                 /* Depends on sysfs having been initialized */
1213                 i915_perf_register(dev_priv);
1214         } else
1215                 DRM_ERROR("Failed to register driver for userspace access!\n");
1216
1217         if (INTEL_INFO(dev_priv)->num_pipes) {
1218                 /* Must be done after probing outputs */
1219                 intel_opregion_register(dev_priv);
1220                 acpi_video_register();
1221         }
1222
1223         if (IS_GEN5(dev_priv))
1224                 intel_gpu_ips_init(dev_priv);
1225
1226         intel_audio_init(dev_priv);
1227
1228         /*
1229          * Some ports require correctly set-up hpd registers for detection to
1230          * work properly (leading to ghost connected connector status), e.g. VGA
1231          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1232          * irqs are fully enabled. We do it last so that the async config
1233          * cannot run before the connectors are registered.
1234          */
1235         intel_fbdev_initial_config_async(dev);
1236 }
1237
1238 /**
1239  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1240  * @dev_priv: device private
1241  */
1242 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1243 {
1244         intel_fbdev_unregister(dev_priv);
1245         intel_audio_deinit(dev_priv);
1246
1247         intel_gpu_ips_teardown();
1248         acpi_video_unregister();
1249         intel_opregion_unregister(dev_priv);
1250
1251         i915_perf_unregister(dev_priv);
1252
1253         i915_teardown_sysfs(dev_priv);
1254         i915_guc_log_unregister(dev_priv);
1255         drm_dev_unregister(&dev_priv->drm);
1256
1257         i915_gem_shrinker_cleanup(dev_priv);
1258 }
1259
1260 /**
1261  * i915_driver_load - setup chip and create an initial config
1262  * @pdev: PCI device
1263  * @ent: matching PCI ID entry
1264  *
1265  * The driver load routine has to do several things:
1266  *   - drive output discovery via intel_modeset_init()
1267  *   - initialize the memory manager
1268  *   - allocate initial config memory
1269  *   - setup the DRM framebuffer with the allocated memory
1270  */
1271 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1272 {
1273         const struct intel_device_info *match_info =
1274                 (struct intel_device_info *)ent->driver_data;
1275         struct drm_i915_private *dev_priv;
1276         int ret;
1277
1278         /* Enable nuclear pageflip on ILK+ */
1279         if (!i915.nuclear_pageflip && match_info->gen < 5)
1280                 driver.driver_features &= ~DRIVER_ATOMIC;
1281
1282         ret = -ENOMEM;
1283         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1284         if (dev_priv)
1285                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1286         if (ret) {
1287                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1288                 goto out_free;
1289         }
1290
1291         dev_priv->drm.pdev = pdev;
1292         dev_priv->drm.dev_private = dev_priv;
1293
1294         ret = pci_enable_device(pdev);
1295         if (ret)
1296                 goto out_fini;
1297
1298         pci_set_drvdata(pdev, &dev_priv->drm);
1299         /*
1300          * Disable the system suspend direct complete optimization, which can
1301          * leave the device suspended skipping the driver's suspend handlers
1302          * if the device was already runtime suspended. This is needed due to
1303          * the difference in our runtime and system suspend sequence and
1304          * becaue the HDA driver may require us to enable the audio power
1305          * domain during system suspend.
1306          */
1307         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1308
1309         ret = i915_driver_init_early(dev_priv, ent);
1310         if (ret < 0)
1311                 goto out_pci_disable;
1312
1313         intel_runtime_pm_get(dev_priv);
1314
1315         ret = i915_driver_init_mmio(dev_priv);
1316         if (ret < 0)
1317                 goto out_runtime_pm_put;
1318
1319         ret = i915_driver_init_hw(dev_priv);
1320         if (ret < 0)
1321                 goto out_cleanup_mmio;
1322
1323         /*
1324          * TODO: move the vblank init and parts of modeset init steps into one
1325          * of the i915_driver_init_/i915_driver_register functions according
1326          * to the role/effect of the given init step.
1327          */
1328         if (INTEL_INFO(dev_priv)->num_pipes) {
1329                 ret = drm_vblank_init(&dev_priv->drm,
1330                                       INTEL_INFO(dev_priv)->num_pipes);
1331                 if (ret)
1332                         goto out_cleanup_hw;
1333         }
1334
1335         ret = i915_load_modeset_init(&dev_priv->drm);
1336         if (ret < 0)
1337                 goto out_cleanup_hw;
1338
1339         i915_driver_register(dev_priv);
1340
1341         intel_runtime_pm_enable(dev_priv);
1342
1343         dev_priv->ipc_enabled = false;
1344
1345         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1346                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1347         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1348                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1349
1350         intel_runtime_pm_put(dev_priv);
1351
1352         return 0;
1353
1354 out_cleanup_hw:
1355         i915_driver_cleanup_hw(dev_priv);
1356 out_cleanup_mmio:
1357         i915_driver_cleanup_mmio(dev_priv);
1358 out_runtime_pm_put:
1359         intel_runtime_pm_put(dev_priv);
1360         i915_driver_cleanup_early(dev_priv);
1361 out_pci_disable:
1362         pci_disable_device(pdev);
1363 out_fini:
1364         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1365         drm_dev_fini(&dev_priv->drm);
1366 out_free:
1367         kfree(dev_priv);
1368         return ret;
1369 }
1370
1371 void i915_driver_unload(struct drm_device *dev)
1372 {
1373         struct drm_i915_private *dev_priv = to_i915(dev);
1374         struct pci_dev *pdev = dev_priv->drm.pdev;
1375
1376         i915_driver_unregister(dev_priv);
1377
1378         if (i915_gem_suspend(dev_priv))
1379                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1380
1381         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1382
1383         drm_atomic_helper_shutdown(dev);
1384
1385         intel_gvt_cleanup(dev_priv);
1386
1387         intel_modeset_cleanup(dev);
1388
1389         /*
1390          * free the memory space allocated for the child device
1391          * config parsed from VBT
1392          */
1393         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1394                 kfree(dev_priv->vbt.child_dev);
1395                 dev_priv->vbt.child_dev = NULL;
1396                 dev_priv->vbt.child_dev_num = 0;
1397         }
1398         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1399         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1400         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1401         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1402
1403         vga_switcheroo_unregister_client(pdev);
1404         vga_client_register(pdev, NULL, NULL, NULL);
1405
1406         intel_csr_ucode_fini(dev_priv);
1407
1408         /* Free error state after interrupts are fully disabled. */
1409         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1410         i915_reset_error_state(dev_priv);
1411
1412         i915_gem_fini(dev_priv);
1413         intel_uc_fini_fw(dev_priv);
1414         intel_fbc_cleanup_cfb(dev_priv);
1415
1416         intel_power_domains_fini(dev_priv);
1417
1418         i915_driver_cleanup_hw(dev_priv);
1419         i915_driver_cleanup_mmio(dev_priv);
1420
1421         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1422 }
1423
1424 static void i915_driver_release(struct drm_device *dev)
1425 {
1426         struct drm_i915_private *dev_priv = to_i915(dev);
1427
1428         i915_driver_cleanup_early(dev_priv);
1429         drm_dev_fini(&dev_priv->drm);
1430
1431         kfree(dev_priv);
1432 }
1433
1434 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1435 {
1436         struct drm_i915_private *i915 = to_i915(dev);
1437         int ret;
1438
1439         ret = i915_gem_open(i915, file);
1440         if (ret)
1441                 return ret;
1442
1443         return 0;
1444 }
1445
1446 /**
1447  * i915_driver_lastclose - clean up after all DRM clients have exited
1448  * @dev: DRM device
1449  *
1450  * Take care of cleaning up after all DRM clients have exited.  In the
1451  * mode setting case, we want to restore the kernel's initial mode (just
1452  * in case the last client left us in a bad state).
1453  *
1454  * Additionally, in the non-mode setting case, we'll tear down the GTT
1455  * and DMA structures, since the kernel won't be using them, and clea
1456  * up any GEM state.
1457  */
1458 static void i915_driver_lastclose(struct drm_device *dev)
1459 {
1460         intel_fbdev_restore_mode(dev);
1461         vga_switcheroo_process_delayed_switch();
1462 }
1463
1464 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1465 {
1466         struct drm_i915_file_private *file_priv = file->driver_priv;
1467
1468         mutex_lock(&dev->struct_mutex);
1469         i915_gem_context_close(file);
1470         i915_gem_release(dev, file);
1471         mutex_unlock(&dev->struct_mutex);
1472
1473         kfree(file_priv);
1474 }
1475
1476 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1477 {
1478         struct drm_device *dev = &dev_priv->drm;
1479         struct intel_encoder *encoder;
1480
1481         drm_modeset_lock_all(dev);
1482         for_each_intel_encoder(dev, encoder)
1483                 if (encoder->suspend)
1484                         encoder->suspend(encoder);
1485         drm_modeset_unlock_all(dev);
1486 }
1487
1488 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1489                               bool rpm_resume);
1490 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1491
1492 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1493 {
1494 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1495         if (acpi_target_system_state() < ACPI_STATE_S3)
1496                 return true;
1497 #endif
1498         return false;
1499 }
1500
1501 static int i915_drm_suspend(struct drm_device *dev)
1502 {
1503         struct drm_i915_private *dev_priv = to_i915(dev);
1504         struct pci_dev *pdev = dev_priv->drm.pdev;
1505         pci_power_t opregion_target_state;
1506         int error;
1507
1508         /* ignore lid events during suspend */
1509         mutex_lock(&dev_priv->modeset_restore_lock);
1510         dev_priv->modeset_restore = MODESET_SUSPENDED;
1511         mutex_unlock(&dev_priv->modeset_restore_lock);
1512
1513         disable_rpm_wakeref_asserts(dev_priv);
1514
1515         /* We do a lot of poking in a lot of registers, make sure they work
1516          * properly. */
1517         intel_display_set_init_power(dev_priv, true);
1518
1519         drm_kms_helper_poll_disable(dev);
1520
1521         pci_save_state(pdev);
1522
1523         error = i915_gem_suspend(dev_priv);
1524         if (error) {
1525                 dev_err(&pdev->dev,
1526                         "GEM idle failed, resume might fail\n");
1527                 goto out;
1528         }
1529
1530         intel_display_suspend(dev);
1531
1532         intel_dp_mst_suspend(dev);
1533
1534         intel_runtime_pm_disable_interrupts(dev_priv);
1535         intel_hpd_cancel_work(dev_priv);
1536
1537         intel_suspend_encoders(dev_priv);
1538
1539         intel_suspend_hw(dev_priv);
1540
1541         i915_gem_suspend_gtt_mappings(dev_priv);
1542
1543         i915_save_state(dev_priv);
1544
1545         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1546         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1547
1548         intel_uncore_suspend(dev_priv);
1549         intel_opregion_unregister(dev_priv);
1550
1551         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1552
1553         dev_priv->suspend_count++;
1554
1555         intel_csr_ucode_suspend(dev_priv);
1556
1557 out:
1558         enable_rpm_wakeref_asserts(dev_priv);
1559
1560         return error;
1561 }
1562
1563 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(dev);
1566         struct pci_dev *pdev = dev_priv->drm.pdev;
1567         bool fw_csr;
1568         int ret;
1569
1570         disable_rpm_wakeref_asserts(dev_priv);
1571
1572         intel_display_set_init_power(dev_priv, false);
1573
1574         fw_csr = !IS_GEN9_LP(dev_priv) &&
1575                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1576         /*
1577          * In case of firmware assisted context save/restore don't manually
1578          * deinit the power domains. This also means the CSR/DMC firmware will
1579          * stay active, it will power down any HW resources as required and
1580          * also enable deeper system power states that would be blocked if the
1581          * firmware was inactive.
1582          */
1583         if (!fw_csr)
1584                 intel_power_domains_suspend(dev_priv);
1585
1586         ret = 0;
1587         if (IS_GEN9_LP(dev_priv))
1588                 bxt_enable_dc9(dev_priv);
1589         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1590                 hsw_enable_pc8(dev_priv);
1591         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1592                 ret = vlv_suspend_complete(dev_priv);
1593
1594         if (ret) {
1595                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1596                 if (!fw_csr)
1597                         intel_power_domains_init_hw(dev_priv, true);
1598
1599                 goto out;
1600         }
1601
1602         pci_disable_device(pdev);
1603         /*
1604          * During hibernation on some platforms the BIOS may try to access
1605          * the device even though it's already in D3 and hang the machine. So
1606          * leave the device in D0 on those platforms and hope the BIOS will
1607          * power down the device properly. The issue was seen on multiple old
1608          * GENs with different BIOS vendors, so having an explicit blacklist
1609          * is inpractical; apply the workaround on everything pre GEN6. The
1610          * platforms where the issue was seen:
1611          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1612          * Fujitsu FSC S7110
1613          * Acer Aspire 1830T
1614          */
1615         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1616                 pci_set_power_state(pdev, PCI_D3hot);
1617
1618         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1619
1620 out:
1621         enable_rpm_wakeref_asserts(dev_priv);
1622
1623         return ret;
1624 }
1625
1626 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1627 {
1628         int error;
1629
1630         if (!dev) {
1631                 DRM_ERROR("dev: %p\n", dev);
1632                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1633                 return -ENODEV;
1634         }
1635
1636         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1637                          state.event != PM_EVENT_FREEZE))
1638                 return -EINVAL;
1639
1640         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1641                 return 0;
1642
1643         error = i915_drm_suspend(dev);
1644         if (error)
1645                 return error;
1646
1647         return i915_drm_suspend_late(dev, false);
1648 }
1649
1650 static int i915_drm_resume(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = to_i915(dev);
1653         int ret;
1654
1655         disable_rpm_wakeref_asserts(dev_priv);
1656         intel_sanitize_gt_powersave(dev_priv);
1657
1658         ret = i915_ggtt_enable_hw(dev_priv);
1659         if (ret)
1660                 DRM_ERROR("failed to re-enable GGTT\n");
1661
1662         intel_csr_ucode_resume(dev_priv);
1663
1664         i915_gem_resume(dev_priv);
1665
1666         i915_restore_state(dev_priv);
1667         intel_pps_unlock_regs_wa(dev_priv);
1668         intel_opregion_setup(dev_priv);
1669
1670         intel_init_pch_refclk(dev_priv);
1671
1672         /*
1673          * Interrupts have to be enabled before any batches are run. If not the
1674          * GPU will hang. i915_gem_init_hw() will initiate batches to
1675          * update/restore the context.
1676          *
1677          * drm_mode_config_reset() needs AUX interrupts.
1678          *
1679          * Modeset enabling in intel_modeset_init_hw() also needs working
1680          * interrupts.
1681          */
1682         intel_runtime_pm_enable_interrupts(dev_priv);
1683
1684         drm_mode_config_reset(dev);
1685
1686         mutex_lock(&dev->struct_mutex);
1687         if (i915_gem_init_hw(dev_priv)) {
1688                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1689                 i915_gem_set_wedged(dev_priv);
1690         }
1691         mutex_unlock(&dev->struct_mutex);
1692
1693         intel_guc_resume(dev_priv);
1694
1695         intel_modeset_init_hw(dev);
1696
1697         spin_lock_irq(&dev_priv->irq_lock);
1698         if (dev_priv->display.hpd_irq_setup)
1699                 dev_priv->display.hpd_irq_setup(dev_priv);
1700         spin_unlock_irq(&dev_priv->irq_lock);
1701
1702         intel_dp_mst_resume(dev);
1703
1704         intel_display_resume(dev);
1705
1706         drm_kms_helper_poll_enable(dev);
1707
1708         /*
1709          * ... but also need to make sure that hotplug processing
1710          * doesn't cause havoc. Like in the driver load code we don't
1711          * bother with the tiny race here where we might loose hotplug
1712          * notifications.
1713          * */
1714         intel_hpd_init(dev_priv);
1715
1716         intel_opregion_register(dev_priv);
1717
1718         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1719
1720         mutex_lock(&dev_priv->modeset_restore_lock);
1721         dev_priv->modeset_restore = MODESET_DONE;
1722         mutex_unlock(&dev_priv->modeset_restore_lock);
1723
1724         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1725
1726         intel_autoenable_gt_powersave(dev_priv);
1727
1728         enable_rpm_wakeref_asserts(dev_priv);
1729
1730         return 0;
1731 }
1732
1733 static int i915_drm_resume_early(struct drm_device *dev)
1734 {
1735         struct drm_i915_private *dev_priv = to_i915(dev);
1736         struct pci_dev *pdev = dev_priv->drm.pdev;
1737         int ret;
1738
1739         /*
1740          * We have a resume ordering issue with the snd-hda driver also
1741          * requiring our device to be power up. Due to the lack of a
1742          * parent/child relationship we currently solve this with an early
1743          * resume hook.
1744          *
1745          * FIXME: This should be solved with a special hdmi sink device or
1746          * similar so that power domains can be employed.
1747          */
1748
1749         /*
1750          * Note that we need to set the power state explicitly, since we
1751          * powered off the device during freeze and the PCI core won't power
1752          * it back up for us during thaw. Powering off the device during
1753          * freeze is not a hard requirement though, and during the
1754          * suspend/resume phases the PCI core makes sure we get here with the
1755          * device powered on. So in case we change our freeze logic and keep
1756          * the device powered we can also remove the following set power state
1757          * call.
1758          */
1759         ret = pci_set_power_state(pdev, PCI_D0);
1760         if (ret) {
1761                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1762                 goto out;
1763         }
1764
1765         /*
1766          * Note that pci_enable_device() first enables any parent bridge
1767          * device and only then sets the power state for this device. The
1768          * bridge enabling is a nop though, since bridge devices are resumed
1769          * first. The order of enabling power and enabling the device is
1770          * imposed by the PCI core as described above, so here we preserve the
1771          * same order for the freeze/thaw phases.
1772          *
1773          * TODO: eventually we should remove pci_disable_device() /
1774          * pci_enable_enable_device() from suspend/resume. Due to how they
1775          * depend on the device enable refcount we can't anyway depend on them
1776          * disabling/enabling the device.
1777          */
1778         if (pci_enable_device(pdev)) {
1779                 ret = -EIO;
1780                 goto out;
1781         }
1782
1783         pci_set_master(pdev);
1784
1785         disable_rpm_wakeref_asserts(dev_priv);
1786
1787         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1788                 ret = vlv_resume_prepare(dev_priv, false);
1789         if (ret)
1790                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1791                           ret);
1792
1793         intel_uncore_resume_early(dev_priv);
1794
1795         if (IS_GEN9_LP(dev_priv)) {
1796                 if (!dev_priv->suspended_to_idle)
1797                         gen9_sanitize_dc_state(dev_priv);
1798                 bxt_disable_dc9(dev_priv);
1799         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1800                 hsw_disable_pc8(dev_priv);
1801         }
1802
1803         intel_uncore_sanitize(dev_priv);
1804
1805         if (IS_GEN9_LP(dev_priv) ||
1806             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1807                 intel_power_domains_init_hw(dev_priv, true);
1808
1809         i915_gem_sanitize(dev_priv);
1810
1811         enable_rpm_wakeref_asserts(dev_priv);
1812
1813 out:
1814         dev_priv->suspended_to_idle = false;
1815
1816         return ret;
1817 }
1818
1819 static int i915_resume_switcheroo(struct drm_device *dev)
1820 {
1821         int ret;
1822
1823         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1824                 return 0;
1825
1826         ret = i915_drm_resume_early(dev);
1827         if (ret)
1828                 return ret;
1829
1830         return i915_drm_resume(dev);
1831 }
1832
1833 /**
1834  * i915_reset - reset chip after a hang
1835  * @i915: #drm_i915_private to reset
1836  * @flags: Instructions
1837  *
1838  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1839  * on failure.
1840  *
1841  * Caller must hold the struct_mutex.
1842  *
1843  * Procedure is fairly simple:
1844  *   - reset the chip using the reset reg
1845  *   - re-init context state
1846  *   - re-init hardware status page
1847  *   - re-init ring buffer
1848  *   - re-init interrupt state
1849  *   - re-init display
1850  */
1851 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1852 {
1853         struct i915_gpu_error *error = &i915->gpu_error;
1854         int ret;
1855
1856         lockdep_assert_held(&i915->drm.struct_mutex);
1857         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1858
1859         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1860                 return;
1861
1862         /* Clear any previous failed attempts at recovery. Time to try again. */
1863         if (!i915_gem_unset_wedged(i915))
1864                 goto wakeup;
1865
1866         if (!(flags & I915_RESET_QUIET))
1867                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1868         error->reset_count++;
1869
1870         disable_irq(i915->drm.irq);
1871         ret = i915_gem_reset_prepare(i915);
1872         if (ret) {
1873                 DRM_ERROR("GPU recovery failed\n");
1874                 intel_gpu_reset(i915, ALL_ENGINES);
1875                 goto error;
1876         }
1877
1878         ret = intel_gpu_reset(i915, ALL_ENGINES);
1879         if (ret) {
1880                 if (ret != -ENODEV)
1881                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1882                 else
1883                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1884                 goto error;
1885         }
1886
1887         i915_gem_reset(i915);
1888         intel_overlay_reset(i915);
1889
1890         /* Ok, now get things going again... */
1891
1892         /*
1893          * Everything depends on having the GTT running, so we need to start
1894          * there.
1895          */
1896         ret = i915_ggtt_enable_hw(i915);
1897         if (ret) {
1898                 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1899                 goto error;
1900         }
1901
1902         /*
1903          * Next we need to restore the context, but we don't use those
1904          * yet either...
1905          *
1906          * Ring buffer needs to be re-initialized in the KMS case, or if X
1907          * was running at the time of the reset (i.e. we weren't VT
1908          * switched away).
1909          */
1910         ret = i915_gem_init_hw(i915);
1911         if (ret) {
1912                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1913                 goto error;
1914         }
1915
1916         i915_queue_hangcheck(i915);
1917
1918 finish:
1919         i915_gem_reset_finish(i915);
1920         enable_irq(i915->drm.irq);
1921
1922 wakeup:
1923         clear_bit(I915_RESET_HANDOFF, &error->flags);
1924         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1925         return;
1926
1927 error:
1928         i915_gem_set_wedged(i915);
1929         i915_gem_retire_requests(i915);
1930         goto finish;
1931 }
1932
1933 /**
1934  * i915_reset_engine - reset GPU engine to recover from a hang
1935  * @engine: engine to reset
1936  * @flags: options
1937  *
1938  * Reset a specific GPU engine. Useful if a hang is detected.
1939  * Returns zero on successful reset or otherwise an error code.
1940  *
1941  * Procedure is:
1942  *  - identifies the request that caused the hang and it is dropped
1943  *  - reset engine (which will force the engine to idle)
1944  *  - re-init/configure engine
1945  */
1946 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1947 {
1948         struct i915_gpu_error *error = &engine->i915->gpu_error;
1949         struct drm_i915_gem_request *active_request;
1950         int ret;
1951
1952         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1953
1954         if (!(flags & I915_RESET_QUIET)) {
1955                 dev_notice(engine->i915->drm.dev,
1956                            "Resetting %s after gpu hang\n", engine->name);
1957         }
1958         error->reset_engine_count[engine->id]++;
1959
1960         active_request = i915_gem_reset_prepare_engine(engine);
1961         if (IS_ERR(active_request)) {
1962                 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1963                 ret = PTR_ERR(active_request);
1964                 goto out;
1965         }
1966
1967         ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
1968         if (ret) {
1969                 /* If we fail here, we expect to fallback to a global reset */
1970                 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1971                                  engine->name, ret);
1972                 goto out;
1973         }
1974
1975         /*
1976          * The request that caused the hang is stuck on elsp, we know the
1977          * active request and can drop it, adjust head to skip the offending
1978          * request to resume executing remaining requests in the queue.
1979          */
1980         i915_gem_reset_engine(engine, active_request);
1981
1982         /*
1983          * The engine and its registers (and workarounds in case of render)
1984          * have been reset to their default values. Follow the init_ring
1985          * process to program RING_MODE, HWSP and re-enable submission.
1986          */
1987         ret = engine->init_hw(engine);
1988         if (ret)
1989                 goto out;
1990
1991 out:
1992         i915_gem_reset_finish_engine(engine);
1993         return ret;
1994 }
1995
1996 static int i915_pm_suspend(struct device *kdev)
1997 {
1998         struct pci_dev *pdev = to_pci_dev(kdev);
1999         struct drm_device *dev = pci_get_drvdata(pdev);
2000
2001         if (!dev) {
2002                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2003                 return -ENODEV;
2004         }
2005
2006         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2007                 return 0;
2008
2009         return i915_drm_suspend(dev);
2010 }
2011
2012 static int i915_pm_suspend_late(struct device *kdev)
2013 {
2014         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2015
2016         /*
2017          * We have a suspend ordering issue with the snd-hda driver also
2018          * requiring our device to be power up. Due to the lack of a
2019          * parent/child relationship we currently solve this with an late
2020          * suspend hook.
2021          *
2022          * FIXME: This should be solved with a special hdmi sink device or
2023          * similar so that power domains can be employed.
2024          */
2025         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2026                 return 0;
2027
2028         return i915_drm_suspend_late(dev, false);
2029 }
2030
2031 static int i915_pm_poweroff_late(struct device *kdev)
2032 {
2033         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2034
2035         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2036                 return 0;
2037
2038         return i915_drm_suspend_late(dev, true);
2039 }
2040
2041 static int i915_pm_resume_early(struct device *kdev)
2042 {
2043         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2044
2045         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2046                 return 0;
2047
2048         return i915_drm_resume_early(dev);
2049 }
2050
2051 static int i915_pm_resume(struct device *kdev)
2052 {
2053         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2054
2055         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2056                 return 0;
2057
2058         return i915_drm_resume(dev);
2059 }
2060
2061 /* freeze: before creating the hibernation_image */
2062 static int i915_pm_freeze(struct device *kdev)
2063 {
2064         int ret;
2065
2066         ret = i915_pm_suspend(kdev);
2067         if (ret)
2068                 return ret;
2069
2070         ret = i915_gem_freeze(kdev_to_i915(kdev));
2071         if (ret)
2072                 return ret;
2073
2074         return 0;
2075 }
2076
2077 static int i915_pm_freeze_late(struct device *kdev)
2078 {
2079         int ret;
2080
2081         ret = i915_pm_suspend_late(kdev);
2082         if (ret)
2083                 return ret;
2084
2085         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2086         if (ret)
2087                 return ret;
2088
2089         return 0;
2090 }
2091
2092 /* thaw: called after creating the hibernation image, but before turning off. */
2093 static int i915_pm_thaw_early(struct device *kdev)
2094 {
2095         return i915_pm_resume_early(kdev);
2096 }
2097
2098 static int i915_pm_thaw(struct device *kdev)
2099 {
2100         return i915_pm_resume(kdev);
2101 }
2102
2103 /* restore: called after loading the hibernation image. */
2104 static int i915_pm_restore_early(struct device *kdev)
2105 {
2106         return i915_pm_resume_early(kdev);
2107 }
2108
2109 static int i915_pm_restore(struct device *kdev)
2110 {
2111         return i915_pm_resume(kdev);
2112 }
2113
2114 /*
2115  * Save all Gunit registers that may be lost after a D3 and a subsequent
2116  * S0i[R123] transition. The list of registers needing a save/restore is
2117  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2118  * registers in the following way:
2119  * - Driver: saved/restored by the driver
2120  * - Punit : saved/restored by the Punit firmware
2121  * - No, w/o marking: no need to save/restore, since the register is R/O or
2122  *                    used internally by the HW in a way that doesn't depend
2123  *                    keeping the content across a suspend/resume.
2124  * - Debug : used for debugging
2125  *
2126  * We save/restore all registers marked with 'Driver', with the following
2127  * exceptions:
2128  * - Registers out of use, including also registers marked with 'Debug'.
2129  *   These have no effect on the driver's operation, so we don't save/restore
2130  *   them to reduce the overhead.
2131  * - Registers that are fully setup by an initialization function called from
2132  *   the resume path. For example many clock gating and RPS/RC6 registers.
2133  * - Registers that provide the right functionality with their reset defaults.
2134  *
2135  * TODO: Except for registers that based on the above 3 criteria can be safely
2136  * ignored, we save/restore all others, practically treating the HW context as
2137  * a black-box for the driver. Further investigation is needed to reduce the
2138  * saved/restored registers even further, by following the same 3 criteria.
2139  */
2140 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2141 {
2142         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2143         int i;
2144
2145         /* GAM 0x4000-0x4770 */
2146         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2147         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2148         s->arb_mode             = I915_READ(ARB_MODE);
2149         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2150         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2151
2152         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2153                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2154
2155         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2156         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2157
2158         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2159         s->ecochk               = I915_READ(GAM_ECOCHK);
2160         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2161         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2162
2163         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2164
2165         /* MBC 0x9024-0x91D0, 0x8500 */
2166         s->g3dctl               = I915_READ(VLV_G3DCTL);
2167         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2168         s->mbctl                = I915_READ(GEN6_MBCTL);
2169
2170         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2171         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2172         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2173         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2174         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2175         s->rstctl               = I915_READ(GEN6_RSTCTL);
2176         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2177
2178         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2179         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2180         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2181         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2182         s->ecobus               = I915_READ(ECOBUS);
2183         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2184         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2185         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2186         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2187         s->rcedata              = I915_READ(VLV_RCEDATA);
2188         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2189
2190         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2191         s->gt_imr               = I915_READ(GTIMR);
2192         s->gt_ier               = I915_READ(GTIER);
2193         s->pm_imr               = I915_READ(GEN6_PMIMR);
2194         s->pm_ier               = I915_READ(GEN6_PMIER);
2195
2196         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2197                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2198
2199         /* GT SA CZ domain, 0x100000-0x138124 */
2200         s->tilectl              = I915_READ(TILECTL);
2201         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2202         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2203         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2204         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2205
2206         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2207         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2208         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2209         s->pcbr                 = I915_READ(VLV_PCBR);
2210         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2211
2212         /*
2213          * Not saving any of:
2214          * DFT,         0x9800-0x9EC0
2215          * SARB,        0xB000-0xB1FC
2216          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2217          * PCI CFG
2218          */
2219 }
2220
2221 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2222 {
2223         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2224         u32 val;
2225         int i;
2226
2227         /* GAM 0x4000-0x4770 */
2228         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2229         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2230         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2231         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2232         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2233
2234         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2235                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2236
2237         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2238         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2239
2240         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2241         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2242         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2243         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2244
2245         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2246
2247         /* MBC 0x9024-0x91D0, 0x8500 */
2248         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2249         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2250         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2251
2252         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2253         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2254         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2255         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2256         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2257         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2258         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2259
2260         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2261         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2262         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2263         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2264         I915_WRITE(ECOBUS,              s->ecobus);
2265         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2266         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2267         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2268         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2269         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2270         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2271
2272         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2273         I915_WRITE(GTIMR,               s->gt_imr);
2274         I915_WRITE(GTIER,               s->gt_ier);
2275         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2276         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2277
2278         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2279                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2280
2281         /* GT SA CZ domain, 0x100000-0x138124 */
2282         I915_WRITE(TILECTL,                     s->tilectl);
2283         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2284         /*
2285          * Preserve the GT allow wake and GFX force clock bit, they are not
2286          * be restored, as they are used to control the s0ix suspend/resume
2287          * sequence by the caller.
2288          */
2289         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2290         val &= VLV_GTLC_ALLOWWAKEREQ;
2291         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2292         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2293
2294         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2295         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2296         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2297         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2298
2299         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2300
2301         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2302         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2303         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2304         I915_WRITE(VLV_PCBR,                    s->pcbr);
2305         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2306 }
2307
2308 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2309                                   u32 mask, u32 val)
2310 {
2311         /* The HW does not like us polling for PW_STATUS frequently, so
2312          * use the sleeping loop rather than risk the busy spin within
2313          * intel_wait_for_register().
2314          *
2315          * Transitioning between RC6 states should be at most 2ms (see
2316          * valleyview_enable_rps) so use a 3ms timeout.
2317          */
2318         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2319                         3);
2320 }
2321
2322 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2323 {
2324         u32 val;
2325         int err;
2326
2327         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2328         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2329         if (force_on)
2330                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2331         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2332
2333         if (!force_on)
2334                 return 0;
2335
2336         err = intel_wait_for_register(dev_priv,
2337                                       VLV_GTLC_SURVIVABILITY_REG,
2338                                       VLV_GFX_CLK_STATUS_BIT,
2339                                       VLV_GFX_CLK_STATUS_BIT,
2340                                       20);
2341         if (err)
2342                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2343                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2344
2345         return err;
2346 }
2347
2348 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2349 {
2350         u32 mask;
2351         u32 val;
2352         int err;
2353
2354         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2355         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2356         if (allow)
2357                 val |= VLV_GTLC_ALLOWWAKEREQ;
2358         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2359         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2360
2361         mask = VLV_GTLC_ALLOWWAKEACK;
2362         val = allow ? mask : 0;
2363
2364         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2365         if (err)
2366                 DRM_ERROR("timeout disabling GT waking\n");
2367
2368         return err;
2369 }
2370
2371 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2372                                   bool wait_for_on)
2373 {
2374         u32 mask;
2375         u32 val;
2376
2377         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2378         val = wait_for_on ? mask : 0;
2379
2380         /*
2381          * RC6 transitioning can be delayed up to 2 msec (see
2382          * valleyview_enable_rps), use 3 msec for safety.
2383          */
2384         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2385                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2386                           onoff(wait_for_on));
2387 }
2388
2389 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2390 {
2391         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2392                 return;
2393
2394         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2395         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2396 }
2397
2398 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2399 {
2400         u32 mask;
2401         int err;
2402
2403         /*
2404          * Bspec defines the following GT well on flags as debug only, so
2405          * don't treat them as hard failures.
2406          */
2407         vlv_wait_for_gt_wells(dev_priv, false);
2408
2409         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2410         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2411
2412         vlv_check_no_gt_access(dev_priv);
2413
2414         err = vlv_force_gfx_clock(dev_priv, true);
2415         if (err)
2416                 goto err1;
2417
2418         err = vlv_allow_gt_wake(dev_priv, false);
2419         if (err)
2420                 goto err2;
2421
2422         if (!IS_CHERRYVIEW(dev_priv))
2423                 vlv_save_gunit_s0ix_state(dev_priv);
2424
2425         err = vlv_force_gfx_clock(dev_priv, false);
2426         if (err)
2427                 goto err2;
2428
2429         return 0;
2430
2431 err2:
2432         /* For safety always re-enable waking and disable gfx clock forcing */
2433         vlv_allow_gt_wake(dev_priv, true);
2434 err1:
2435         vlv_force_gfx_clock(dev_priv, false);
2436
2437         return err;
2438 }
2439
2440 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2441                                 bool rpm_resume)
2442 {
2443         int err;
2444         int ret;
2445
2446         /*
2447          * If any of the steps fail just try to continue, that's the best we
2448          * can do at this point. Return the first error code (which will also
2449          * leave RPM permanently disabled).
2450          */
2451         ret = vlv_force_gfx_clock(dev_priv, true);
2452
2453         if (!IS_CHERRYVIEW(dev_priv))
2454                 vlv_restore_gunit_s0ix_state(dev_priv);
2455
2456         err = vlv_allow_gt_wake(dev_priv, true);
2457         if (!ret)
2458                 ret = err;
2459
2460         err = vlv_force_gfx_clock(dev_priv, false);
2461         if (!ret)
2462                 ret = err;
2463
2464         vlv_check_no_gt_access(dev_priv);
2465
2466         if (rpm_resume)
2467                 intel_init_clock_gating(dev_priv);
2468
2469         return ret;
2470 }
2471
2472 static int intel_runtime_suspend(struct device *kdev)
2473 {
2474         struct pci_dev *pdev = to_pci_dev(kdev);
2475         struct drm_device *dev = pci_get_drvdata(pdev);
2476         struct drm_i915_private *dev_priv = to_i915(dev);
2477         int ret;
2478
2479         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2480                 return -ENODEV;
2481
2482         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2483                 return -ENODEV;
2484
2485         DRM_DEBUG_KMS("Suspending device\n");
2486
2487         disable_rpm_wakeref_asserts(dev_priv);
2488
2489         /*
2490          * We are safe here against re-faults, since the fault handler takes
2491          * an RPM reference.
2492          */
2493         i915_gem_runtime_suspend(dev_priv);
2494
2495         intel_guc_suspend(dev_priv);
2496
2497         intel_runtime_pm_disable_interrupts(dev_priv);
2498
2499         ret = 0;
2500         if (IS_GEN9_LP(dev_priv)) {
2501                 bxt_display_core_uninit(dev_priv);
2502                 bxt_enable_dc9(dev_priv);
2503         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2504                 hsw_enable_pc8(dev_priv);
2505         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2506                 ret = vlv_suspend_complete(dev_priv);
2507         }
2508
2509         if (ret) {
2510                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2511                 intel_runtime_pm_enable_interrupts(dev_priv);
2512
2513                 enable_rpm_wakeref_asserts(dev_priv);
2514
2515                 return ret;
2516         }
2517
2518         intel_uncore_suspend(dev_priv);
2519
2520         enable_rpm_wakeref_asserts(dev_priv);
2521         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2522
2523         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2524                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2525
2526         dev_priv->pm.suspended = true;
2527
2528         /*
2529          * FIXME: We really should find a document that references the arguments
2530          * used below!
2531          */
2532         if (IS_BROADWELL(dev_priv)) {
2533                 /*
2534                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2535                  * being detected, and the call we do at intel_runtime_resume()
2536                  * won't be able to restore them. Since PCI_D3hot matches the
2537                  * actual specification and appears to be working, use it.
2538                  */
2539                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2540         } else {
2541                 /*
2542                  * current versions of firmware which depend on this opregion
2543                  * notification have repurposed the D1 definition to mean
2544                  * "runtime suspended" vs. what you would normally expect (D3)
2545                  * to distinguish it from notifications that might be sent via
2546                  * the suspend path.
2547                  */
2548                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2549         }
2550
2551         assert_forcewakes_inactive(dev_priv);
2552
2553         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2554                 intel_hpd_poll_init(dev_priv);
2555
2556         DRM_DEBUG_KMS("Device suspended\n");
2557         return 0;
2558 }
2559
2560 static int intel_runtime_resume(struct device *kdev)
2561 {
2562         struct pci_dev *pdev = to_pci_dev(kdev);
2563         struct drm_device *dev = pci_get_drvdata(pdev);
2564         struct drm_i915_private *dev_priv = to_i915(dev);
2565         int ret = 0;
2566
2567         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2568                 return -ENODEV;
2569
2570         DRM_DEBUG_KMS("Resuming device\n");
2571
2572         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2573         disable_rpm_wakeref_asserts(dev_priv);
2574
2575         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2576         dev_priv->pm.suspended = false;
2577         if (intel_uncore_unclaimed_mmio(dev_priv))
2578                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2579
2580         intel_guc_resume(dev_priv);
2581
2582         if (IS_GEN9_LP(dev_priv)) {
2583                 bxt_disable_dc9(dev_priv);
2584                 bxt_display_core_init(dev_priv, true);
2585                 if (dev_priv->csr.dmc_payload &&
2586                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2587                         gen9_enable_dc5(dev_priv);
2588         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2589                 hsw_disable_pc8(dev_priv);
2590         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2591                 ret = vlv_resume_prepare(dev_priv, true);
2592         }
2593
2594         /*
2595          * No point of rolling back things in case of an error, as the best
2596          * we can do is to hope that things will still work (and disable RPM).
2597          */
2598         i915_gem_init_swizzling(dev_priv);
2599         i915_gem_restore_fences(dev_priv);
2600
2601         intel_runtime_pm_enable_interrupts(dev_priv);
2602
2603         /*
2604          * On VLV/CHV display interrupts are part of the display
2605          * power well, so hpd is reinitialized from there. For
2606          * everyone else do it here.
2607          */
2608         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2609                 intel_hpd_init(dev_priv);
2610
2611         enable_rpm_wakeref_asserts(dev_priv);
2612
2613         if (ret)
2614                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2615         else
2616                 DRM_DEBUG_KMS("Device resumed\n");
2617
2618         return ret;
2619 }
2620
2621 const struct dev_pm_ops i915_pm_ops = {
2622         /*
2623          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2624          * PMSG_RESUME]
2625          */
2626         .suspend = i915_pm_suspend,
2627         .suspend_late = i915_pm_suspend_late,
2628         .resume_early = i915_pm_resume_early,
2629         .resume = i915_pm_resume,
2630
2631         /*
2632          * S4 event handlers
2633          * @freeze, @freeze_late    : called (1) before creating the
2634          *                            hibernation image [PMSG_FREEZE] and
2635          *                            (2) after rebooting, before restoring
2636          *                            the image [PMSG_QUIESCE]
2637          * @thaw, @thaw_early       : called (1) after creating the hibernation
2638          *                            image, before writing it [PMSG_THAW]
2639          *                            and (2) after failing to create or
2640          *                            restore the image [PMSG_RECOVER]
2641          * @poweroff, @poweroff_late: called after writing the hibernation
2642          *                            image, before rebooting [PMSG_HIBERNATE]
2643          * @restore, @restore_early : called after rebooting and restoring the
2644          *                            hibernation image [PMSG_RESTORE]
2645          */
2646         .freeze = i915_pm_freeze,
2647         .freeze_late = i915_pm_freeze_late,
2648         .thaw_early = i915_pm_thaw_early,
2649         .thaw = i915_pm_thaw,
2650         .poweroff = i915_pm_suspend,
2651         .poweroff_late = i915_pm_poweroff_late,
2652         .restore_early = i915_pm_restore_early,
2653         .restore = i915_pm_restore,
2654
2655         /* S0ix (via runtime suspend) event handlers */
2656         .runtime_suspend = intel_runtime_suspend,
2657         .runtime_resume = intel_runtime_resume,
2658 };
2659
2660 static const struct vm_operations_struct i915_gem_vm_ops = {
2661         .fault = i915_gem_fault,
2662         .open = drm_gem_vm_open,
2663         .close = drm_gem_vm_close,
2664 };
2665
2666 static const struct file_operations i915_driver_fops = {
2667         .owner = THIS_MODULE,
2668         .open = drm_open,
2669         .release = drm_release,
2670         .unlocked_ioctl = drm_ioctl,
2671         .mmap = drm_gem_mmap,
2672         .poll = drm_poll,
2673         .read = drm_read,
2674         .compat_ioctl = i915_compat_ioctl,
2675         .llseek = noop_llseek,
2676 };
2677
2678 static int
2679 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2680                           struct drm_file *file)
2681 {
2682         return -ENODEV;
2683 }
2684
2685 static const struct drm_ioctl_desc i915_ioctls[] = {
2686         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2687         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2688         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2689         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2690         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2691         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2692         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2693         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2694         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2695         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2696         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2697         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2698         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2699         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2700         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2701         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2702         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2703         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2704         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2705         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2706         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2707         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2708         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2709         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2710         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2711         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2712         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2713         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2714         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2715         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2716         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2717         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2718         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2719         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2720         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2721         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2722         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2723         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2724         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2725         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2726         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2727         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2728         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2729         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2730         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2731         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2732         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2733         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2734         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2735         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2736         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2737         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2738         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2739         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2740         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2741 };
2742
2743 static struct drm_driver driver = {
2744         /* Don't use MTRRs here; the Xserver or userspace app should
2745          * deal with them for Intel hardware.
2746          */
2747         .driver_features =
2748             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2749             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2750         .release = i915_driver_release,
2751         .open = i915_driver_open,
2752         .lastclose = i915_driver_lastclose,
2753         .postclose = i915_driver_postclose,
2754
2755         .gem_close_object = i915_gem_close_object,
2756         .gem_free_object_unlocked = i915_gem_free_object,
2757         .gem_vm_ops = &i915_gem_vm_ops,
2758
2759         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2760         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2761         .gem_prime_export = i915_gem_prime_export,
2762         .gem_prime_import = i915_gem_prime_import,
2763
2764         .dumb_create = i915_gem_dumb_create,
2765         .dumb_map_offset = i915_gem_mmap_gtt,
2766         .ioctls = i915_ioctls,
2767         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2768         .fops = &i915_driver_fops,
2769         .name = DRIVER_NAME,
2770         .desc = DRIVER_DESC,
2771         .date = DRIVER_DATE,
2772         .major = DRIVER_MAJOR,
2773         .minor = DRIVER_MINOR,
2774         .patchlevel = DRIVER_PATCHLEVEL,
2775 };
2776
2777 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2778 #include "selftests/mock_drm.c"
2779 #endif