drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/vgaarb.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pnp.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/slab.h>
  42
  43 /**
  44  * Sets up the hardware status page for devices that need a physical address
  45  * in the register.
  46  */
  47 static int i915_init_phys_hws(struct drm_device *dev)
  48 {
  49         drm_i915_private_t *dev_priv = dev->dev_private;
  50         /* Program Hardware Status Page */
  51         dev_priv->status_page_dmah =
  52                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  53
  54         if (!dev_priv->status_page_dmah) {
  55                 DRM_ERROR("Can not allocate hardware status page\n");
  56                 return -ENOMEM;
  57         }
  58         dev_priv->render_ring.status_page.page_addr
  59                 = dev_priv->status_page_dmah->vaddr;
  60         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  61
  62         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  63
  64         if (IS_I965G(dev))
  65                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  66                                              0xf0;
  67
  68         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  69         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  70         return 0;
  71 }
  72
  73 /**
  74  * Frees the hardware status page, whether it's a physical address or a virtual
  75  * address set up by the X Server.
  76  */
  77 static void i915_free_hws(struct drm_device *dev)
  78 {
  79         drm_i915_private_t *dev_priv = dev->dev_private;
  80         if (dev_priv->status_page_dmah) {
  81                 drm_pci_free(dev, dev_priv->status_page_dmah);
  82                 dev_priv->status_page_dmah = NULL;
  83         }
  84
  85         if (dev_priv->render_ring.status_page.gfx_addr) {
  86                 dev_priv->render_ring.status_page.gfx_addr = 0;
  87                 dev_priv->status_gfx_addr = 0;
  88                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  89         }
  90
  91         /* Need to rewrite hardware status page */
  92         I915_WRITE(HWS_PGA, 0x1ffff000);
  93 }
  94
  95 void i915_kernel_lost_context(struct drm_device * dev)
  96 {
  97         drm_i915_private_t *dev_priv = dev->dev_private;
  98         struct drm_i915_master_private *master_priv;
  99         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 100
 101         /*
 102          * We should never lose context on the ring with modesetting
 103          * as we don't expose it to userspace
 104          */
 105         if (drm_core_check_feature(dev, DRIVER_MODESET))
 106                 return;
 107
 108         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 109         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 110         ring->space = ring->head - (ring->tail + 8);
 111         if (ring->space < 0)
 112                 ring->space += ring->size;
 113
 114         if (!dev->primary->master)
 115                 return;
 116
 117         master_priv = dev->primary->master->driver_priv;
 118         if (ring->head == ring->tail && master_priv->sarea_priv)
 119                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 120 }
 121
 122 static int i915_dma_cleanup(struct drm_device * dev)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125         /* Make sure interrupts are disabled here because the uninstall ioctl
 126          * may not have been called from userspace and after dev_private
 127          * is freed, it's too late.
 128          */
 129         if (dev->irq_enabled)
 130                 drm_irq_uninstall(dev);
 131
 132         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 133         if (HAS_BSD(dev))
 134                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 135
 136         /* Clear the HWS virtual address at teardown */
 137         if (I915_NEED_GFX_HWS(dev))
 138                 i915_free_hws(dev);
 139
 140         return 0;
 141 }
 142
 143 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 144 {
 145         drm_i915_private_t *dev_priv = dev->dev_private;
 146         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 147
 148         master_priv->sarea = drm_getsarea(dev);
 149         if (master_priv->sarea) {
 150                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 151                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 152         } else {
 153                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 154         }
 155
 156         if (init->ring_size != 0) {
 157                 if (dev_priv->render_ring.gem_object != NULL) {
 158                         i915_dma_cleanup(dev);
 159                         DRM_ERROR("Client tried to initialize ringbuffer in "
 160                                   "GEM mode\n");
 161                         return -EINVAL;
 162                 }
 163
 164                 dev_priv->render_ring.size = init->ring_size;
 165
 166                 dev_priv->render_ring.map.offset = init->ring_start;
 167                 dev_priv->render_ring.map.size = init->ring_size;
 168                 dev_priv->render_ring.map.type = 0;
 169                 dev_priv->render_ring.map.flags = 0;
 170                 dev_priv->render_ring.map.mtrr = 0;
 171
 172                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 173
 174                 if (dev_priv->render_ring.map.handle == NULL) {
 175                         i915_dma_cleanup(dev);
 176                         DRM_ERROR("can not ioremap virtual address for"
 177                                   " ring buffer\n");
 178                         return -ENOMEM;
 179                 }
 180         }
 181
 182         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 183
 184         dev_priv->cpp = init->cpp;
 185         dev_priv->back_offset = init->back_offset;
 186         dev_priv->front_offset = init->front_offset;
 187         dev_priv->current_page = 0;
 188         if (master_priv->sarea_priv)
 189                 master_priv->sarea_priv->pf_current_page = 0;
 190
 191         /* Allow hardware batchbuffers unless told otherwise.
 192          */
 193         dev_priv->allow_batchbuffer = 1;
 194
 195         return 0;
 196 }
 197
 198 static int i915_dma_resume(struct drm_device * dev)
 199 {
 200         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 201
 202         struct intel_ring_buffer *ring;
 203         DRM_DEBUG_DRIVER("%s\n", __func__);
 204
 205         ring = &dev_priv->render_ring;
 206
 207         if (ring->map.handle == NULL) {
 208                 DRM_ERROR("can not ioremap virtual address for"
 209                           " ring buffer\n");
 210                 return -ENOMEM;
 211         }
 212
 213         /* Program Hardware Status Page */
 214         if (!ring->status_page.page_addr) {
 215                 DRM_ERROR("Can not find hardware status page\n");
 216                 return -EINVAL;
 217         }
 218         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 219                                 ring->status_page.page_addr);
 220         if (ring->status_page.gfx_addr != 0)
 221                 ring->setup_status_page(dev, ring);
 222         else
 223                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 224
 225         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 226
 227         return 0;
 228 }
 229
 230 static int i915_dma_init(struct drm_device *dev, void *data,
 231                          struct drm_file *file_priv)
 232 {
 233         drm_i915_init_t *init = data;
 234         int retcode = 0;
 235
 236         switch (init->func) {
 237         case I915_INIT_DMA:
 238                 retcode = i915_initialize(dev, init);
 239                 break;
 240         case I915_CLEANUP_DMA:
 241                 retcode = i915_dma_cleanup(dev);
 242                 break;
 243         case I915_RESUME_DMA:
 244                 retcode = i915_dma_resume(dev);
 245                 break;
 246         default:
 247                 retcode = -EINVAL;
 248                 break;
 249         }
 250
 251         return retcode;
 252 }
 253
 254 /* Implement basically the same security restrictions as hardware does
 255  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 256  *
 257  * Most of the calculations below involve calculating the size of a
 258  * particular instruction.  It's important to get the size right as
 259  * that tells us where the next instruction to check is.  Any illegal
 260  * instruction detected will be given a size of zero, which is a
 261  * signal to abort the rest of the buffer.
 262  */
 263 static int do_validate_cmd(int cmd)
 264 {
 265         switch (((cmd >> 29) & 0x7)) {
 266         case 0x0:
 267                 switch ((cmd >> 23) & 0x3f) {
 268                 case 0x0:
 269                         return 1;       /* MI_NOOP */
 270                 case 0x4:
 271                         return 1;       /* MI_FLUSH */
 272                 default:
 273                         return 0;       /* disallow everything else */
 274                 }
 275                 break;
 276         case 0x1:
 277                 return 0;       /* reserved */
 278         case 0x2:
 279                 return (cmd & 0xff) + 2;        /* 2d commands */
 280         case 0x3:
 281                 if (((cmd >> 24) & 0x1f) <= 0x18)
 282                         return 1;
 283
 284                 switch ((cmd >> 24) & 0x1f) {
 285                 case 0x1c:
 286                         return 1;
 287                 case 0x1d:
 288                         switch ((cmd >> 16) & 0xff) {
 289                         case 0x3:
 290                                 return (cmd & 0x1f) + 2;
 291                         case 0x4:
 292                                 return (cmd & 0xf) + 2;
 293                         default:
 294                                 return (cmd & 0xffff) + 2;
 295                         }
 296                 case 0x1e:
 297                         if (cmd & (1 << 23))
 298                                 return (cmd & 0xffff) + 1;
 299                         else
 300                                 return 1;
 301                 case 0x1f:
 302                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 303                                 return (cmd & 0x1ffff) + 2;
 304                         else if (cmd & (1 << 17))       /* indirect random */
 305                                 if ((cmd & 0xffff) == 0)
 306                                         return 0;       /* unknown length, too hard */
 307                                 else
 308                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 309                         else
 310                                 return 2;       /* indirect sequential */
 311                 default:
 312                         return 0;
 313                 }
 314         default:
 315                 return 0;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static int validate_cmd(int cmd)
 322 {
 323         int ret = do_validate_cmd(cmd);
 324
 325 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 326
 327         return ret;
 328 }
 329
 330 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 331 {
 332         drm_i915_private_t *dev_priv = dev->dev_private;
 333         int i;
 334
 335         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 336                 return -EINVAL;
 337
 338         BEGIN_LP_RING((dwords+1)&~1);
 339
 340         for (i = 0; i < dwords;) {
 341                 int cmd, sz;
 342
 343                 cmd = buffer[i];
 344
 345                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 346                         return -EINVAL;
 347
 348                 OUT_RING(cmd);
 349
 350                 while (++i, --sz) {
 351                         OUT_RING(buffer[i]);
 352                 }
 353         }
 354
 355         if (dwords & 1)
 356                 OUT_RING(0);
 357
 358         ADVANCE_LP_RING();
 359
 360         return 0;
 361 }
 362
 363 int
 364 i915_emit_box(struct drm_device *dev,
 365               struct drm_clip_rect *boxes,
 366               int i, int DR1, int DR4)
 367 {
 368         struct drm_clip_rect box = boxes[i];
 369
 370         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 371                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 372                           box.x1, box.y1, box.x2, box.y2);
 373                 return -EINVAL;
 374         }
 375
 376         if (IS_I965G(dev)) {
 377                 BEGIN_LP_RING(4);
 378                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 379                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 380                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 381                 OUT_RING(DR4);
 382                 ADVANCE_LP_RING();
 383         } else {
 384                 BEGIN_LP_RING(6);
 385                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 386                 OUT_RING(DR1);
 387                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 388                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 389                 OUT_RING(DR4);
 390                 OUT_RING(0);
 391                 ADVANCE_LP_RING();
 392         }
 393
 394         return 0;
 395 }
 396
 397 /* XXX: Emitting the counter should really be moved to part of the IRQ
 398  * emit. For now, do it in both places:
 399  */
 400
 401 static void i915_emit_breadcrumb(struct drm_device *dev)
 402 {
 403         drm_i915_private_t *dev_priv = dev->dev_private;
 404         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 405
 406         dev_priv->counter++;
 407         if (dev_priv->counter > 0x7FFFFFFFUL)
 408                 dev_priv->counter = 0;
 409         if (master_priv->sarea_priv)
 410                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 411
 412         BEGIN_LP_RING(4);
 413         OUT_RING(MI_STORE_DWORD_INDEX);
 414         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 415         OUT_RING(dev_priv->counter);
 416         OUT_RING(0);
 417         ADVANCE_LP_RING();
 418 }
 419
 420 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 421                                    drm_i915_cmdbuffer_t *cmd,
 422                                    struct drm_clip_rect *cliprects,
 423                                    void *cmdbuf)
 424 {
 425         int nbox = cmd->num_cliprects;
 426         int i = 0, count, ret;
 427
 428         if (cmd->sz & 0x3) {
 429                 DRM_ERROR("alignment");
 430                 return -EINVAL;
 431         }
 432
 433         i915_kernel_lost_context(dev);
 434
 435         count = nbox ? nbox : 1;
 436
 437         for (i = 0; i < count; i++) {
 438                 if (i < nbox) {
 439                         ret = i915_emit_box(dev, cliprects, i,
 440                                             cmd->DR1, cmd->DR4);
 441                         if (ret)
 442                                 return ret;
 443                 }
 444
 445                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 446                 if (ret)
 447                         return ret;
 448         }
 449
 450         i915_emit_breadcrumb(dev);
 451         return 0;
 452 }
 453
 454 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 455                                      drm_i915_batchbuffer_t * batch,
 456                                      struct drm_clip_rect *cliprects)
 457 {
 458         int nbox = batch->num_cliprects;
 459         int i = 0, count;
 460
 461         if ((batch->start | batch->used) & 0x7) {
 462                 DRM_ERROR("alignment");
 463                 return -EINVAL;
 464         }
 465
 466         i915_kernel_lost_context(dev);
 467
 468         count = nbox ? nbox : 1;
 469
 470         for (i = 0; i < count; i++) {
 471                 if (i < nbox) {
 472                         int ret = i915_emit_box(dev, cliprects, i,
 473                                                 batch->DR1, batch->DR4);
 474                         if (ret)
 475                                 return ret;
 476                 }
 477
 478                 if (!IS_I830(dev) && !IS_845G(dev)) {
 479                         BEGIN_LP_RING(2);
 480                         if (IS_I965G(dev)) {
 481                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 482                                 OUT_RING(batch->start);
 483                         } else {
 484                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 485                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 486                         }
 487                         ADVANCE_LP_RING();
 488                 } else {
 489                         BEGIN_LP_RING(4);
 490                         OUT_RING(MI_BATCH_BUFFER);
 491                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 492                         OUT_RING(batch->start + batch->used - 4);
 493                         OUT_RING(0);
 494                         ADVANCE_LP_RING();
 495                 }
 496         }
 497
 498         i915_emit_breadcrumb(dev);
 499
 500         return 0;
 501 }
 502
 503 static int i915_dispatch_flip(struct drm_device * dev)
 504 {
 505         drm_i915_private_t *dev_priv = dev->dev_private;
 506         struct drm_i915_master_private *master_priv =
 507                 dev->primary->master->driver_priv;
 508
 509         if (!master_priv->sarea_priv)
 510                 return -EINVAL;
 511
 512         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 513                           __func__,
 514                          dev_priv->current_page,
 515                          master_priv->sarea_priv->pf_current_page);
 516
 517         i915_kernel_lost_context(dev);
 518
 519         BEGIN_LP_RING(2);
 520         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 521         OUT_RING(0);
 522         ADVANCE_LP_RING();
 523
 524         BEGIN_LP_RING(6);
 525         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 526         OUT_RING(0);
 527         if (dev_priv->current_page == 0) {
 528                 OUT_RING(dev_priv->back_offset);
 529                 dev_priv->current_page = 1;
 530         } else {
 531                 OUT_RING(dev_priv->front_offset);
 532                 dev_priv->current_page = 0;
 533         }
 534         OUT_RING(0);
 535         ADVANCE_LP_RING();
 536
 537         BEGIN_LP_RING(2);
 538         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 539         OUT_RING(0);
 540         ADVANCE_LP_RING();
 541
 542         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 543
 544         BEGIN_LP_RING(4);
 545         OUT_RING(MI_STORE_DWORD_INDEX);
 546         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 547         OUT_RING(dev_priv->counter);
 548         OUT_RING(0);
 549         ADVANCE_LP_RING();
 550
 551         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 552         return 0;
 553 }
 554
 555 static int i915_quiescent(struct drm_device * dev)
 556 {
 557         drm_i915_private_t *dev_priv = dev->dev_private;
 558
 559         i915_kernel_lost_context(dev);
 560         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 561                                       dev_priv->render_ring.size - 8);
 562 }
 563
 564 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 565                             struct drm_file *file_priv)
 566 {
 567         int ret;
 568
 569         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 570
 571         mutex_lock(&dev->struct_mutex);
 572         ret = i915_quiescent(dev);
 573         mutex_unlock(&dev->struct_mutex);
 574
 575         return ret;
 576 }
 577
 578 static int i915_batchbuffer(struct drm_device *dev, void *data,
 579                             struct drm_file *file_priv)
 580 {
 581         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 582         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 583         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 584             master_priv->sarea_priv;
 585         drm_i915_batchbuffer_t *batch = data;
 586         int ret;
 587         struct drm_clip_rect *cliprects = NULL;
 588
 589         if (!dev_priv->allow_batchbuffer) {
 590                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 591                 return -EINVAL;
 592         }
 593
 594         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 595                         batch->start, batch->used, batch->num_cliprects);
 596
 597         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 598
 599         if (batch->num_cliprects < 0)
 600                 return -EINVAL;
 601
 602         if (batch->num_cliprects) {
 603                 cliprects = kcalloc(batch->num_cliprects,
 604                                     sizeof(struct drm_clip_rect),
 605                                     GFP_KERNEL);
 606                 if (cliprects == NULL)
 607                         return -ENOMEM;
 608
 609                 ret = copy_from_user(cliprects, batch->cliprects,
 610                                      batch->num_cliprects *
 611                                      sizeof(struct drm_clip_rect));
 612                 if (ret != 0)
 613                         goto fail_free;
 614         }
 615
 616         mutex_lock(&dev->struct_mutex);
 617         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 618         mutex_unlock(&dev->struct_mutex);
 619
 620         if (sarea_priv)
 621                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 622
 623 fail_free:
 624         kfree(cliprects);
 625
 626         return ret;
 627 }
 628
 629 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 630                           struct drm_file *file_priv)
 631 {
 632         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 633         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 634         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 635             master_priv->sarea_priv;
 636         drm_i915_cmdbuffer_t *cmdbuf = data;
 637         struct drm_clip_rect *cliprects = NULL;
 638         void *batch_data;
 639         int ret;
 640
 641         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 642                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 643
 644         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 645
 646         if (cmdbuf->num_cliprects < 0)
 647                 return -EINVAL;
 648
 649         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 650         if (batch_data == NULL)
 651                 return -ENOMEM;
 652
 653         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 654         if (ret != 0)
 655                 goto fail_batch_free;
 656
 657         if (cmdbuf->num_cliprects) {
 658                 cliprects = kcalloc(cmdbuf->num_cliprects,
 659                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 660                 if (cliprects == NULL) {
 661                         ret = -ENOMEM;
 662                         goto fail_batch_free;
 663                 }
 664
 665                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 666                                      cmdbuf->num_cliprects *
 667                                      sizeof(struct drm_clip_rect));
 668                 if (ret != 0)
 669                         goto fail_clip_free;
 670         }
 671
 672         mutex_lock(&dev->struct_mutex);
 673         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 674         mutex_unlock(&dev->struct_mutex);
 675         if (ret) {
 676                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 677                 goto fail_clip_free;
 678         }
 679
 680         if (sarea_priv)
 681                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 682
 683 fail_clip_free:
 684         kfree(cliprects);
 685 fail_batch_free:
 686         kfree(batch_data);
 687
 688         return ret;
 689 }
 690
 691 static int i915_flip_bufs(struct drm_device *dev, void *data,
 692                           struct drm_file *file_priv)
 693 {
 694         int ret;
 695
 696         DRM_DEBUG_DRIVER("%s\n", __func__);
 697
 698         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 699
 700         mutex_lock(&dev->struct_mutex);
 701         ret = i915_dispatch_flip(dev);
 702         mutex_unlock(&dev->struct_mutex);
 703
 704         return ret;
 705 }
 706
 707 static int i915_getparam(struct drm_device *dev, void *data,
 708                          struct drm_file *file_priv)
 709 {
 710         drm_i915_private_t *dev_priv = dev->dev_private;
 711         drm_i915_getparam_t *param = data;
 712         int value;
 713
 714         if (!dev_priv) {
 715                 DRM_ERROR("called with no initialization\n");
 716                 return -EINVAL;
 717         }
 718
 719         switch (param->param) {
 720         case I915_PARAM_IRQ_ACTIVE:
 721                 value = dev->pdev->irq ? 1 : 0;
 722                 break;
 723         case I915_PARAM_ALLOW_BATCHBUFFER:
 724                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 725                 break;
 726         case I915_PARAM_LAST_DISPATCH:
 727                 value = READ_BREADCRUMB(dev_priv);
 728                 break;
 729         case I915_PARAM_CHIPSET_ID:
 730                 value = dev->pci_device;
 731                 break;
 732         case I915_PARAM_HAS_GEM:
 733                 value = dev_priv->has_gem;
 734                 break;
 735         case I915_PARAM_NUM_FENCES_AVAIL:
 736                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 737                 break;
 738         case I915_PARAM_HAS_OVERLAY:
 739                 value = dev_priv->overlay ? 1 : 0;
 740                 break;
 741         case I915_PARAM_HAS_PAGEFLIPPING:
 742                 value = 1;
 743                 break;
 744         case I915_PARAM_HAS_EXECBUF2:
 745                 /* depends on GEM */
 746                 value = dev_priv->has_gem;
 747                 break;
 748         default:
 749                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 750                                  param->param);
 751                 return -EINVAL;
 752         }
 753
 754         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 755                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 756                 return -EFAULT;
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int i915_setparam(struct drm_device *dev, void *data,
 763                          struct drm_file *file_priv)
 764 {
 765         drm_i915_private_t *dev_priv = dev->dev_private;
 766         drm_i915_setparam_t *param = data;
 767
 768         if (!dev_priv) {
 769                 DRM_ERROR("called with no initialization\n");
 770                 return -EINVAL;
 771         }
 772
 773         switch (param->param) {
 774         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 775                 break;
 776         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 777                 dev_priv->tex_lru_log_granularity = param->value;
 778                 break;
 779         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 780                 dev_priv->allow_batchbuffer = param->value;
 781                 break;
 782         case I915_SETPARAM_NUM_USED_FENCES:
 783                 if (param->value > dev_priv->num_fence_regs ||
 784                     param->value < 0)
 785                         return -EINVAL;
 786                 /* Userspace can use first N regs */
 787                 dev_priv->fence_reg_start = param->value;
 788                 break;
 789         default:
 790                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 791                                         param->param);
 792                 return -EINVAL;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int i915_set_status_page(struct drm_device *dev, void *data,
 799                                 struct drm_file *file_priv)
 800 {
 801         drm_i915_private_t *dev_priv = dev->dev_private;
 802         drm_i915_hws_addr_t *hws = data;
 803         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 804
 805         if (!I915_NEED_GFX_HWS(dev))
 806                 return -EINVAL;
 807
 808         if (!dev_priv) {
 809                 DRM_ERROR("called with no initialization\n");
 810                 return -EINVAL;
 811         }
 812
 813         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 814                 WARN(1, "tried to set status page when mode setting active\n");
 815                 return 0;
 816         }
 817
 818         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 819
 820         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 821
 822         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 823         dev_priv->hws_map.size = 4*1024;
 824         dev_priv->hws_map.type = 0;
 825         dev_priv->hws_map.flags = 0;
 826         dev_priv->hws_map.mtrr = 0;
 827
 828         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 829         if (dev_priv->hws_map.handle == NULL) {
 830                 i915_dma_cleanup(dev);
 831                 dev_priv->status_gfx_addr = 0;
 832                 DRM_ERROR("can not ioremap virtual address for"
 833                                 " G33 hw status page\n");
 834                 return -ENOMEM;
 835         }
 836         ring->status_page.page_addr = dev_priv->hws_map.handle;
 837         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 838         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 839
 840         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 841                         dev_priv->status_gfx_addr);
 842         DRM_DEBUG_DRIVER("load hws at %p\n",
 843                         dev_priv->hw_status_page);
 844         return 0;
 845 }
 846
 847 static int i915_get_bridge_dev(struct drm_device *dev)
 848 {
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850
 851         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 852         if (!dev_priv->bridge_dev) {
 853                 DRM_ERROR("bridge device not found\n");
 854                 return -1;
 855         }
 856         return 0;
 857 }
 858
 859 #define MCHBAR_I915 0x44
 860 #define MCHBAR_I965 0x48
 861 #define MCHBAR_SIZE (4*4096)
 862
 863 #define DEVEN_REG 0x54
 864 #define   DEVEN_MCHBAR_EN (1 << 28)
 865
 866 /* Allocate space for the MCH regs if needed, return nonzero on error */
 867 static int
 868 intel_alloc_mchbar_resource(struct drm_device *dev)
 869 {
 870         drm_i915_private_t *dev_priv = dev->dev_private;
 871         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 872         u32 temp_lo, temp_hi = 0;
 873         u64 mchbar_addr;
 874         int ret = 0;
 875
 876         if (IS_I965G(dev))
 877                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 878         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 879         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 880
 881         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 882 #ifdef CONFIG_PNP
 883         if (mchbar_addr &&
 884             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 885                 ret = 0;
 886                 goto out;
 887         }
 888 #endif
 889
 890         /* Get some space for it */
 891         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 892                                      MCHBAR_SIZE, MCHBAR_SIZE,
 893                                      PCIBIOS_MIN_MEM,
 894                                      0,   pcibios_align_resource,
 895                                      dev_priv->bridge_dev);
 896         if (ret) {
 897                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 898                 dev_priv->mch_res.start = 0;
 899                 goto out;
 900         }
 901
 902         if (IS_I965G(dev))
 903                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 904                                        upper_32_bits(dev_priv->mch_res.start));
 905
 906         pci_write_config_dword(dev_priv->bridge_dev, reg,
 907                                lower_32_bits(dev_priv->mch_res.start));
 908 out:
 909         return ret;
 910 }
 911
 912 /* Setup MCHBAR if possible, return true if we should disable it again */
 913 static void
 914 intel_setup_mchbar(struct drm_device *dev)
 915 {
 916         drm_i915_private_t *dev_priv = dev->dev_private;
 917         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 918         u32 temp;
 919         bool enabled;
 920
 921         dev_priv->mchbar_need_disable = false;
 922
 923         if (IS_I915G(dev) || IS_I915GM(dev)) {
 924                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 925                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 926         } else {
 927                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 928                 enabled = temp & 1;
 929         }
 930
 931         /* If it's already enabled, don't have to do anything */
 932         if (enabled)
 933                 return;
 934
 935         if (intel_alloc_mchbar_resource(dev))
 936                 return;
 937
 938         dev_priv->mchbar_need_disable = true;
 939
 940         /* Space is allocated or reserved, so enable it. */
 941         if (IS_I915G(dev) || IS_I915GM(dev)) {
 942                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 943                                        temp | DEVEN_MCHBAR_EN);
 944         } else {
 945                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 946                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 947         }
 948 }
 949
 950 static void
 951 intel_teardown_mchbar(struct drm_device *dev)
 952 {
 953         drm_i915_private_t *dev_priv = dev->dev_private;
 954         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 955         u32 temp;
 956
 957         if (dev_priv->mchbar_need_disable) {
 958                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 959                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 960                         temp &= ~DEVEN_MCHBAR_EN;
 961                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 962                 } else {
 963                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 964                         temp &= ~1;
 965                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 966                 }
 967         }
 968
 969         if (dev_priv->mch_res.start)
 970                 release_resource(&dev_priv->mch_res);
 971 }
 972
 973 /**
 974  * i915_probe_agp - get AGP bootup configuration
 975  * @pdev: PCI device
 976  * @aperture_size: returns AGP aperture configured size
 977  * @preallocated_size: returns size of BIOS preallocated AGP space
 978  *
 979  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 980  * some RAM for the framebuffer at early boot.  This code figures out
 981  * how much was set aside so we can use it for our own purposes.
 982  */
 983 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 984                           uint32_t *preallocated_size,
 985                           uint32_t *start)
 986 {
 987         struct drm_i915_private *dev_priv = dev->dev_private;
 988         u16 tmp = 0;
 989         unsigned long overhead;
 990         unsigned long stolen;
 991
 992         /* Get the fb aperture size and "stolen" memory amount. */
 993         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 994
 995         *aperture_size = 1024 * 1024;
 996         *preallocated_size = 1024 * 1024;
 997
 998         switch (dev->pdev->device) {
 999         case PCI_DEVICE_ID_INTEL_82830_CGC:
1000         case PCI_DEVICE_ID_INTEL_82845G_IG:
1001         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1002         case PCI_DEVICE_ID_INTEL_82865_IG:
1003                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1004                         *aperture_size *= 64;
1005                 else
1006                         *aperture_size *= 128;
1007                 break;
1008         default:
1009                 /* 9xx supports large sizes, just look at the length */
1010                 *aperture_size = pci_resource_len(dev->pdev, 2);
1011                 break;
1012         }
1013
1014         /*
1015          * Some of the preallocated space is taken by the GTT
1016          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1017          */
1018         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1019                 overhead = 4096;
1020         else
1021                 overhead = (*aperture_size / 1024) + 4096;
1022
1023         if (IS_GEN6(dev)) {
1024                 /* SNB has memory control reg at 0x50.w */
1025                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1026
1027                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1028                 case INTEL_855_GMCH_GMS_DISABLED:
1029                         DRM_ERROR("video memory is disabled\n");
1030                         return -1;
1031                 case SNB_GMCH_GMS_STOLEN_32M:
1032                         stolen = 32 * 1024 * 1024;
1033                         break;
1034                 case SNB_GMCH_GMS_STOLEN_64M:
1035                         stolen = 64 * 1024 * 1024;
1036                         break;
1037                 case SNB_GMCH_GMS_STOLEN_96M:
1038                         stolen = 96 * 1024 * 1024;
1039                         break;
1040                 case SNB_GMCH_GMS_STOLEN_128M:
1041                         stolen = 128 * 1024 * 1024;
1042                         break;
1043                 case SNB_GMCH_GMS_STOLEN_160M:
1044                         stolen = 160 * 1024 * 1024;
1045                         break;
1046                 case SNB_GMCH_GMS_STOLEN_192M:
1047                         stolen = 192 * 1024 * 1024;
1048                         break;
1049                 case SNB_GMCH_GMS_STOLEN_224M:
1050                         stolen = 224 * 1024 * 1024;
1051                         break;
1052                 case SNB_GMCH_GMS_STOLEN_256M:
1053                         stolen = 256 * 1024 * 1024;
1054                         break;
1055                 case SNB_GMCH_GMS_STOLEN_288M:
1056                         stolen = 288 * 1024 * 1024;
1057                         break;
1058                 case SNB_GMCH_GMS_STOLEN_320M:
1059                         stolen = 320 * 1024 * 1024;
1060                         break;
1061                 case SNB_GMCH_GMS_STOLEN_352M:
1062                         stolen = 352 * 1024 * 1024;
1063                         break;
1064                 case SNB_GMCH_GMS_STOLEN_384M:
1065                         stolen = 384 * 1024 * 1024;
1066                         break;
1067                 case SNB_GMCH_GMS_STOLEN_416M:
1068                         stolen = 416 * 1024 * 1024;
1069                         break;
1070                 case SNB_GMCH_GMS_STOLEN_448M:
1071                         stolen = 448 * 1024 * 1024;
1072                         break;
1073                 case SNB_GMCH_GMS_STOLEN_480M:
1074                         stolen = 480 * 1024 * 1024;
1075                         break;
1076                 case SNB_GMCH_GMS_STOLEN_512M:
1077                         stolen = 512 * 1024 * 1024;
1078                         break;
1079                 default:
1080                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1081                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1082                         return -1;
1083                 }
1084         } else {
1085                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1086                 case INTEL_855_GMCH_GMS_DISABLED:
1087                         DRM_ERROR("video memory is disabled\n");
1088                         return -1;
1089                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1090                         stolen = 1 * 1024 * 1024;
1091                         break;
1092                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1093                         stolen = 4 * 1024 * 1024;
1094                         break;
1095                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1096                         stolen = 8 * 1024 * 1024;
1097                         break;
1098                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1099                         stolen = 16 * 1024 * 1024;
1100                         break;
1101                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1102                         stolen = 32 * 1024 * 1024;
1103                         break;
1104                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1105                         stolen = 48 * 1024 * 1024;
1106                         break;
1107                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1108                         stolen = 64 * 1024 * 1024;
1109                         break;
1110                 case INTEL_GMCH_GMS_STOLEN_128M:
1111                         stolen = 128 * 1024 * 1024;
1112                         break;
1113                 case INTEL_GMCH_GMS_STOLEN_256M:
1114                         stolen = 256 * 1024 * 1024;
1115                         break;
1116                 case INTEL_GMCH_GMS_STOLEN_96M:
1117                         stolen = 96 * 1024 * 1024;
1118                         break;
1119                 case INTEL_GMCH_GMS_STOLEN_160M:
1120                         stolen = 160 * 1024 * 1024;
1121                         break;
1122                 case INTEL_GMCH_GMS_STOLEN_224M:
1123                         stolen = 224 * 1024 * 1024;
1124                         break;
1125                 case INTEL_GMCH_GMS_STOLEN_352M:
1126                         stolen = 352 * 1024 * 1024;
1127                         break;
1128                 default:
1129                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1130                                   tmp & INTEL_GMCH_GMS_MASK);
1131                         return -1;
1132                 }
1133         }
1134
1135         *preallocated_size = stolen - overhead;
1136         *start = overhead;
1137
1138         return 0;
1139 }
1140
1141 #define PTE_ADDRESS_MASK                0xfffff000
1142 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1143 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1144 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1145 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1146 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1147 #define PTE_VALID                       (1 << 0)
1148
1149 /**
1150  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1151  * @dev: drm device
1152  * @gtt_addr: address to translate
1153  *
1154  * Some chip functions require allocations from stolen space but need the
1155  * physical address of the memory in question.  We use this routine
1156  * to get a physical address suitable for register programming from a given
1157  * GTT address.
1158  */
1159 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1160                                       unsigned long gtt_addr)
1161 {
1162         unsigned long *gtt;
1163         unsigned long entry, phys;
1164         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1165         int gtt_offset, gtt_size;
1166
1167         if (IS_I965G(dev)) {
1168                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1169                         gtt_offset = 2*1024*1024;
1170                         gtt_size = 2*1024*1024;
1171                 } else {
1172                         gtt_offset = 512*1024;
1173                         gtt_size = 512*1024;
1174                 }
1175         } else {
1176                 gtt_bar = 3;
1177                 gtt_offset = 0;
1178                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1179         }
1180
1181         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1182                          gtt_size);
1183         if (!gtt) {
1184                 DRM_ERROR("ioremap of GTT failed\n");
1185                 return 0;
1186         }
1187
1188         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1189
1190         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1191
1192         /* Mask out these reserved bits on this hardware. */
1193         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1194             IS_I945G(dev) || IS_I945GM(dev)) {
1195                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1196         }
1197
1198         /* If it's not a mapping type we know, then bail. */
1199         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1200             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1201                 iounmap(gtt);
1202                 return 0;
1203         }
1204
1205         if (!(entry & PTE_VALID)) {
1206                 DRM_ERROR("bad GTT entry in stolen space\n");
1207                 iounmap(gtt);
1208                 return 0;
1209         }
1210
1211         iounmap(gtt);
1212
1213         phys =(entry & PTE_ADDRESS_MASK) |
1214                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1215
1216         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1217
1218         return phys;
1219 }
1220
1221 static void i915_warn_stolen(struct drm_device *dev)
1222 {
1223         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1224         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1225 }
1226
1227 static void i915_setup_compression(struct drm_device *dev, int size)
1228 {
1229         struct drm_i915_private *dev_priv = dev->dev_private;
1230         struct drm_mm_node *compressed_fb, *compressed_llb;
1231         unsigned long cfb_base;
1232         unsigned long ll_base = 0;
1233
1234         /* Leave 1M for line length buffer & misc. */
1235         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1236         if (!compressed_fb) {
1237                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1238                 i915_warn_stolen(dev);
1239                 return;
1240         }
1241
1242         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1243         if (!compressed_fb) {
1244                 i915_warn_stolen(dev);
1245                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1246                 return;
1247         }
1248
1249         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1250         if (!cfb_base) {
1251                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1252                 drm_mm_put_block(compressed_fb);
1253         }
1254
1255         if (!IS_GM45(dev)) {
1256                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1257                                                     4096, 0);
1258                 if (!compressed_llb) {
1259                         i915_warn_stolen(dev);
1260                         return;
1261                 }
1262
1263                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1264                 if (!compressed_llb) {
1265                         i915_warn_stolen(dev);
1266                         return;
1267                 }
1268
1269                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1270                 if (!ll_base) {
1271                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1272                         drm_mm_put_block(compressed_fb);
1273                         drm_mm_put_block(compressed_llb);
1274                 }
1275         }
1276
1277         dev_priv->cfb_size = size;
1278
1279         intel_disable_fbc(dev);
1280         dev_priv->compressed_fb = compressed_fb;
1281
1282         if (IS_GM45(dev)) {
1283                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1284         } else {
1285                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1286                 I915_WRITE(FBC_LL_BASE, ll_base);
1287                 dev_priv->compressed_llb = compressed_llb;
1288         }
1289
1290         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1291                   ll_base, size >> 20);
1292 }
1293
1294 static void i915_cleanup_compression(struct drm_device *dev)
1295 {
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297
1298         drm_mm_put_block(dev_priv->compressed_fb);
1299         if (!IS_GM45(dev))
1300                 drm_mm_put_block(dev_priv->compressed_llb);
1301 }
1302
1303 /* true = enable decode, false = disable decoder */
1304 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1305 {
1306         struct drm_device *dev = cookie;
1307
1308         intel_modeset_vga_set_state(dev, state);
1309         if (state)
1310                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1311                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1312         else
1313                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1314 }
1315
1316 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1317 {
1318         struct drm_device *dev = pci_get_drvdata(pdev);
1319         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1320         if (state == VGA_SWITCHEROO_ON) {
1321                 printk(KERN_INFO "i915: switched off\n");
1322                 /* i915 resume handler doesn't set to D0 */
1323                 pci_set_power_state(dev->pdev, PCI_D0);
1324                 i915_resume(dev);
1325         } else {
1326                 printk(KERN_ERR "i915: switched off\n");
1327                 i915_suspend(dev, pmm);
1328         }
1329 }
1330
1331 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1332 {
1333         struct drm_device *dev = pci_get_drvdata(pdev);
1334         bool can_switch;
1335
1336         spin_lock(&dev->count_lock);
1337         can_switch = (dev->open_count == 0);
1338         spin_unlock(&dev->count_lock);
1339         return can_switch;
1340 }
1341
1342 static int i915_load_modeset_init(struct drm_device *dev,
1343                                   unsigned long prealloc_start,
1344                                   unsigned long prealloc_size,
1345                                   unsigned long agp_size)
1346 {
1347         struct drm_i915_private *dev_priv = dev->dev_private;
1348         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1349         int ret = 0;
1350
1351         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1352                 0xff000000;
1353
1354         /* Basic memrange allocator for stolen space (aka vram) */
1355         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1356         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1357
1358         /* We're off and running w/KMS */
1359         dev_priv->mm.suspended = 0;
1360
1361         /* Let GEM Manage from end of prealloc space to end of aperture.
1362          *
1363          * However, leave one page at the end still bound to the scratch page.
1364          * There are a number of places where the hardware apparently
1365          * prefetches past the end of the object, and we've seen multiple
1366          * hangs with the GPU head pointer stuck in a batchbuffer bound
1367          * at the last page of the aperture.  One page should be enough to
1368          * keep any prefetching inside of the aperture.
1369          */
1370         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1371
1372         mutex_lock(&dev->struct_mutex);
1373         ret = i915_gem_init_ringbuffer(dev);
1374         mutex_unlock(&dev->struct_mutex);
1375         if (ret)
1376                 goto out;
1377
1378         /* Try to set up FBC with a reasonable compressed buffer size */
1379         if (I915_HAS_FBC(dev) && i915_powersave) {
1380                 int cfb_size;
1381
1382                 /* Try to get an 8M buffer... */
1383                 if (prealloc_size > (9*1024*1024))
1384                         cfb_size = 8*1024*1024;
1385                 else /* fall back to 7/8 of the stolen space */
1386                         cfb_size = prealloc_size * 7 / 8;
1387                 i915_setup_compression(dev, cfb_size);
1388         }
1389
1390         /* Allow hardware batchbuffers unless told otherwise.
1391          */
1392         dev_priv->allow_batchbuffer = 1;
1393
1394         ret = intel_init_bios(dev);
1395         if (ret)
1396                 DRM_INFO("failed to find VBIOS tables\n");
1397
1398         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1399         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1400         if (ret)
1401                 goto destroy_ringbuffer;
1402
1403         ret = vga_switcheroo_register_client(dev->pdev,
1404                                              i915_switcheroo_set_state,
1405                                              i915_switcheroo_can_switch);
1406         if (ret)
1407                 goto destroy_ringbuffer;
1408
1409         intel_modeset_init(dev);
1410
1411         ret = drm_irq_install(dev);
1412         if (ret)
1413                 goto destroy_ringbuffer;
1414
1415         /* Always safe in the mode setting case. */
1416         /* FIXME: do pre/post-mode set stuff in core KMS code */
1417         dev->vblank_disable_allowed = 1;
1418
1419         /*
1420          * Initialize the hardware status page IRQ location.
1421          */
1422
1423         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1424
1425         intel_fbdev_init(dev);
1426         drm_kms_helper_poll_init(dev);
1427         return 0;
1428
1429 destroy_ringbuffer:
1430         mutex_lock(&dev->struct_mutex);
1431         i915_gem_cleanup_ringbuffer(dev);
1432         mutex_unlock(&dev->struct_mutex);
1433 out:
1434         return ret;
1435 }
1436
1437 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1438 {
1439         struct drm_i915_master_private *master_priv;
1440
1441         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1442         if (!master_priv)
1443                 return -ENOMEM;
1444
1445         master->driver_priv = master_priv;
1446         return 0;
1447 }
1448
1449 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1450 {
1451         struct drm_i915_master_private *master_priv = master->driver_priv;
1452
1453         if (!master_priv)
1454                 return;
1455
1456         kfree(master_priv);
1457
1458         master->driver_priv = NULL;
1459 }
1460
1461 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1462 {
1463         drm_i915_private_t *dev_priv = dev->dev_private;
1464         u32 tmp;
1465
1466         tmp = I915_READ(CLKCFG);
1467
1468         switch (tmp & CLKCFG_FSB_MASK) {
1469         case CLKCFG_FSB_533:
1470                 dev_priv->fsb_freq = 533; /* 133*4 */
1471                 break;
1472         case CLKCFG_FSB_800:
1473                 dev_priv->fsb_freq = 800; /* 200*4 */
1474                 break;
1475         case CLKCFG_FSB_667:
1476                 dev_priv->fsb_freq =  667; /* 167*4 */
1477                 break;
1478         case CLKCFG_FSB_400:
1479                 dev_priv->fsb_freq = 400; /* 100*4 */
1480                 break;
1481         }
1482
1483         switch (tmp & CLKCFG_MEM_MASK) {
1484         case CLKCFG_MEM_533:
1485                 dev_priv->mem_freq = 533;
1486                 break;
1487         case CLKCFG_MEM_667:
1488                 dev_priv->mem_freq = 667;
1489                 break;
1490         case CLKCFG_MEM_800:
1491                 dev_priv->mem_freq = 800;
1492                 break;
1493         }
1494
1495         /* detect pineview DDR3 setting */
1496         tmp = I915_READ(CSHRDDR3CTL);
1497         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1498 }
1499
1500 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1501 {
1502         drm_i915_private_t *dev_priv = dev->dev_private;
1503         u16 ddrpll, csipll;
1504
1505         ddrpll = I915_READ16(DDRMPLL1);
1506         csipll = I915_READ16(CSIPLL0);
1507
1508         switch (ddrpll & 0xff) {
1509         case 0xc:
1510                 dev_priv->mem_freq = 800;
1511                 break;
1512         case 0x10:
1513                 dev_priv->mem_freq = 1066;
1514                 break;
1515         case 0x14:
1516                 dev_priv->mem_freq = 1333;
1517                 break;
1518         case 0x18:
1519                 dev_priv->mem_freq = 1600;
1520                 break;
1521         default:
1522                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1523                                  ddrpll & 0xff);
1524                 dev_priv->mem_freq = 0;
1525                 break;
1526         }
1527
1528         dev_priv->r_t = dev_priv->mem_freq;
1529
1530         switch (csipll & 0x3ff) {
1531         case 0x00c:
1532                 dev_priv->fsb_freq = 3200;
1533                 break;
1534         case 0x00e:
1535                 dev_priv->fsb_freq = 3733;
1536                 break;
1537         case 0x010:
1538                 dev_priv->fsb_freq = 4266;
1539                 break;
1540         case 0x012:
1541                 dev_priv->fsb_freq = 4800;
1542                 break;
1543         case 0x014:
1544                 dev_priv->fsb_freq = 5333;
1545                 break;
1546         case 0x016:
1547                 dev_priv->fsb_freq = 5866;
1548                 break;
1549         case 0x018:
1550                 dev_priv->fsb_freq = 6400;
1551                 break;
1552         default:
1553                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1554                                  csipll & 0x3ff);
1555                 dev_priv->fsb_freq = 0;
1556                 break;
1557         }
1558
1559         if (dev_priv->fsb_freq == 3200) {
1560                 dev_priv->c_m = 0;
1561         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1562                 dev_priv->c_m = 1;
1563         } else {
1564                 dev_priv->c_m = 2;
1565         }
1566 }
1567
1568 struct v_table {
1569         u8 vid;
1570         unsigned long vd; /* in .1 mil */
1571         unsigned long vm; /* in .1 mil */
1572         u8 pvid;
1573 };
1574
1575 static struct v_table v_table[] = {
1576         { 0, 16125, 15000, 0x7f, },
1577         { 1, 16000, 14875, 0x7e, },
1578         { 2, 15875, 14750, 0x7d, },
1579         { 3, 15750, 14625, 0x7c, },
1580         { 4, 15625, 14500, 0x7b, },
1581         { 5, 15500, 14375, 0x7a, },
1582         { 6, 15375, 14250, 0x79, },
1583         { 7, 15250, 14125, 0x78, },
1584         { 8, 15125, 14000, 0x77, },
1585         { 9, 15000, 13875, 0x76, },
1586         { 10, 14875, 13750, 0x75, },
1587         { 11, 14750, 13625, 0x74, },
1588         { 12, 14625, 13500, 0x73, },
1589         { 13, 14500, 13375, 0x72, },
1590         { 14, 14375, 13250, 0x71, },
1591         { 15, 14250, 13125, 0x70, },
1592         { 16, 14125, 13000, 0x6f, },
1593         { 17, 14000, 12875, 0x6e, },
1594         { 18, 13875, 12750, 0x6d, },
1595         { 19, 13750, 12625, 0x6c, },
1596         { 20, 13625, 12500, 0x6b, },
1597         { 21, 13500, 12375, 0x6a, },
1598         { 22, 13375, 12250, 0x69, },
1599         { 23, 13250, 12125, 0x68, },
1600         { 24, 13125, 12000, 0x67, },
1601         { 25, 13000, 11875, 0x66, },
1602         { 26, 12875, 11750, 0x65, },
1603         { 27, 12750, 11625, 0x64, },
1604         { 28, 12625, 11500, 0x63, },
1605         { 29, 12500, 11375, 0x62, },
1606         { 30, 12375, 11250, 0x61, },
1607         { 31, 12250, 11125, 0x60, },
1608         { 32, 12125, 11000, 0x5f, },
1609         { 33, 12000, 10875, 0x5e, },
1610         { 34, 11875, 10750, 0x5d, },
1611         { 35, 11750, 10625, 0x5c, },
1612         { 36, 11625, 10500, 0x5b, },
1613         { 37, 11500, 10375, 0x5a, },
1614         { 38, 11375, 10250, 0x59, },
1615         { 39, 11250, 10125, 0x58, },
1616         { 40, 11125, 10000, 0x57, },
1617         { 41, 11000, 9875, 0x56, },
1618         { 42, 10875, 9750, 0x55, },
1619         { 43, 10750, 9625, 0x54, },
1620         { 44, 10625, 9500, 0x53, },
1621         { 45, 10500, 9375, 0x52, },
1622         { 46, 10375, 9250, 0x51, },
1623         { 47, 10250, 9125, 0x50, },
1624         { 48, 10125, 9000, 0x4f, },
1625         { 49, 10000, 8875, 0x4e, },
1626         { 50, 9875, 8750, 0x4d, },
1627         { 51, 9750, 8625, 0x4c, },
1628         { 52, 9625, 8500, 0x4b, },
1629         { 53, 9500, 8375, 0x4a, },
1630         { 54, 9375, 8250, 0x49, },
1631         { 55, 9250, 8125, 0x48, },
1632         { 56, 9125, 8000, 0x47, },
1633         { 57, 9000, 7875, 0x46, },
1634         { 58, 8875, 7750, 0x45, },
1635         { 59, 8750, 7625, 0x44, },
1636         { 60, 8625, 7500, 0x43, },
1637         { 61, 8500, 7375, 0x42, },
1638         { 62, 8375, 7250, 0x41, },
1639         { 63, 8250, 7125, 0x40, },
1640         { 64, 8125, 7000, 0x3f, },
1641         { 65, 8000, 6875, 0x3e, },
1642         { 66, 7875, 6750, 0x3d, },
1643         { 67, 7750, 6625, 0x3c, },
1644         { 68, 7625, 6500, 0x3b, },
1645         { 69, 7500, 6375, 0x3a, },
1646         { 70, 7375, 6250, 0x39, },
1647         { 71, 7250, 6125, 0x38, },
1648         { 72, 7125, 6000, 0x37, },
1649         { 73, 7000, 5875, 0x36, },
1650         { 74, 6875, 5750, 0x35, },
1651         { 75, 6750, 5625, 0x34, },
1652         { 76, 6625, 5500, 0x33, },
1653         { 77, 6500, 5375, 0x32, },
1654         { 78, 6375, 5250, 0x31, },
1655         { 79, 6250, 5125, 0x30, },
1656         { 80, 6125, 5000, 0x2f, },
1657         { 81, 6000, 4875, 0x2e, },
1658         { 82, 5875, 4750, 0x2d, },
1659         { 83, 5750, 4625, 0x2c, },
1660         { 84, 5625, 4500, 0x2b, },
1661         { 85, 5500, 4375, 0x2a, },
1662         { 86, 5375, 4250, 0x29, },
1663         { 87, 5250, 4125, 0x28, },
1664         { 88, 5125, 4000, 0x27, },
1665         { 89, 5000, 3875, 0x26, },
1666         { 90, 4875, 3750, 0x25, },
1667         { 91, 4750, 3625, 0x24, },
1668         { 92, 4625, 3500, 0x23, },
1669         { 93, 4500, 3375, 0x22, },
1670         { 94, 4375, 3250, 0x21, },
1671         { 95, 4250, 3125, 0x20, },
1672         { 96, 4125, 3000, 0x1f, },
1673         { 97, 4125, 3000, 0x1e, },
1674         { 98, 4125, 3000, 0x1d, },
1675         { 99, 4125, 3000, 0x1c, },
1676         { 100, 4125, 3000, 0x1b, },
1677         { 101, 4125, 3000, 0x1a, },
1678         { 102, 4125, 3000, 0x19, },
1679         { 103, 4125, 3000, 0x18, },
1680         { 104, 4125, 3000, 0x17, },
1681         { 105, 4125, 3000, 0x16, },
1682         { 106, 4125, 3000, 0x15, },
1683         { 107, 4125, 3000, 0x14, },
1684         { 108, 4125, 3000, 0x13, },
1685         { 109, 4125, 3000, 0x12, },
1686         { 110, 4125, 3000, 0x11, },
1687         { 111, 4125, 3000, 0x10, },
1688         { 112, 4125, 3000, 0x0f, },
1689         { 113, 4125, 3000, 0x0e, },
1690         { 114, 4125, 3000, 0x0d, },
1691         { 115, 4125, 3000, 0x0c, },
1692         { 116, 4125, 3000, 0x0b, },
1693         { 117, 4125, 3000, 0x0a, },
1694         { 118, 4125, 3000, 0x09, },
1695         { 119, 4125, 3000, 0x08, },
1696         { 120, 1125, 0, 0x07, },
1697         { 121, 1000, 0, 0x06, },
1698         { 122, 875, 0, 0x05, },
1699         { 123, 750, 0, 0x04, },
1700         { 124, 625, 0, 0x03, },
1701         { 125, 500, 0, 0x02, },
1702         { 126, 375, 0, 0x01, },
1703         { 127, 0, 0, 0x00, },
1704 };
1705
1706 struct cparams {
1707         int i;
1708         int t;
1709         int m;
1710         int c;
1711 };
1712
1713 static struct cparams cparams[] = {
1714         { 1, 1333, 301, 28664 },
1715         { 1, 1066, 294, 24460 },
1716         { 1, 800, 294, 25192 },
1717         { 0, 1333, 276, 27605 },
1718         { 0, 1066, 276, 27605 },
1719         { 0, 800, 231, 23784 },
1720 };
1721
1722 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1723 {
1724         u64 total_count, diff, ret;
1725         u32 count1, count2, count3, m = 0, c = 0;
1726         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1727         int i;
1728
1729         diff1 = now - dev_priv->last_time1;
1730
1731         count1 = I915_READ(DMIEC);
1732         count2 = I915_READ(DDREC);
1733         count3 = I915_READ(CSIEC);
1734
1735         total_count = count1 + count2 + count3;
1736
1737         /* FIXME: handle per-counter overflow */
1738         if (total_count < dev_priv->last_count1) {
1739                 diff = ~0UL - dev_priv->last_count1;
1740                 diff += total_count;
1741         } else {
1742                 diff = total_count - dev_priv->last_count1;
1743         }
1744
1745         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1746                 if (cparams[i].i == dev_priv->c_m &&
1747                     cparams[i].t == dev_priv->r_t) {
1748                         m = cparams[i].m;
1749                         c = cparams[i].c;
1750                         break;
1751                 }
1752         }
1753
1754         div_u64(diff, diff1);
1755         ret = ((m * diff) + c);
1756         div_u64(ret, 10);
1757
1758         dev_priv->last_count1 = total_count;
1759         dev_priv->last_time1 = now;
1760
1761         return ret;
1762 }
1763
1764 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1765 {
1766         unsigned long m, x, b;
1767         u32 tsfs;
1768
1769         tsfs = I915_READ(TSFS);
1770
1771         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1772         x = I915_READ8(TR1);
1773
1774         b = tsfs & TSFS_INTR_MASK;
1775
1776         return ((m * x) / 127) - b;
1777 }
1778
1779 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1780 {
1781         unsigned long val = 0;
1782         int i;
1783
1784         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1785                 if (v_table[i].pvid == pxvid) {
1786                         if (IS_MOBILE(dev_priv->dev))
1787                                 val = v_table[i].vm;
1788                         else
1789                                 val = v_table[i].vd;
1790                 }
1791         }
1792
1793         return val;
1794 }
1795
1796 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1797 {
1798         struct timespec now, diff1;
1799         u64 diff;
1800         unsigned long diffms;
1801         u32 count;
1802
1803         getrawmonotonic(&now);
1804         diff1 = timespec_sub(now, dev_priv->last_time2);
1805
1806         /* Don't divide by 0 */
1807         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1808         if (!diffms)
1809                 return;
1810
1811         count = I915_READ(GFXEC);
1812
1813         if (count < dev_priv->last_count2) {
1814                 diff = ~0UL - dev_priv->last_count2;
1815                 diff += count;
1816         } else {
1817                 diff = count - dev_priv->last_count2;
1818         }
1819
1820         dev_priv->last_count2 = count;
1821         dev_priv->last_time2 = now;
1822
1823         /* More magic constants... */
1824         diff = diff * 1181;
1825         div_u64(diff, diffms * 10);
1826         dev_priv->gfx_power = diff;
1827 }
1828
1829 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1830 {
1831         unsigned long t, corr, state1, corr2, state2;
1832         u32 pxvid, ext_v;
1833
1834         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1835         pxvid = (pxvid >> 24) & 0x7f;
1836         ext_v = pvid_to_extvid(dev_priv, pxvid);
1837
1838         state1 = ext_v;
1839
1840         t = i915_mch_val(dev_priv);
1841
1842         /* Revel in the empirically derived constants */
1843
1844         /* Correction factor in 1/100000 units */
1845         if (t > 80)
1846                 corr = ((t * 2349) + 135940);
1847         else if (t >= 50)
1848                 corr = ((t * 964) + 29317);
1849         else /* < 50 */
1850                 corr = ((t * 301) + 1004);
1851
1852         corr = corr * ((150142 * state1) / 10000 - 78642);
1853         corr /= 100000;
1854         corr2 = (corr * dev_priv->corr);
1855
1856         state2 = (corr2 * state1) / 10000;
1857         state2 /= 100; /* convert to mW */
1858
1859         i915_update_gfx_val(dev_priv);
1860
1861         return dev_priv->gfx_power + state2;
1862 }
1863
1864 /* Global for IPS driver to get at the current i915 device */
1865 static struct drm_i915_private *i915_mch_dev;
1866 /*
1867  * Lock protecting IPS related data structures
1868  *   - i915_mch_dev
1869  *   - dev_priv->max_delay
1870  *   - dev_priv->min_delay
1871  *   - dev_priv->fmax
1872  *   - dev_priv->gpu_busy
1873  */
1874 DEFINE_SPINLOCK(mchdev_lock);
1875
1876 /**
1877  * i915_read_mch_val - return value for IPS use
1878  *
1879  * Calculate and return a value for the IPS driver to use when deciding whether
1880  * we have thermal and power headroom to increase CPU or GPU power budget.
1881  */
1882 unsigned long i915_read_mch_val(void)
1883 {
1884         struct drm_i915_private *dev_priv;
1885         unsigned long chipset_val, graphics_val, ret = 0;
1886
1887         spin_lock(&mchdev_lock);
1888         if (!i915_mch_dev)
1889                 goto out_unlock;
1890         dev_priv = i915_mch_dev;
1891
1892         chipset_val = i915_chipset_val(dev_priv);
1893         graphics_val = i915_gfx_val(dev_priv);
1894
1895         ret = chipset_val + graphics_val;
1896
1897 out_unlock:
1898         spin_unlock(&mchdev_lock);
1899
1900         return ret;
1901 }
1902 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1903
1904 /**
1905  * i915_gpu_raise - raise GPU frequency limit
1906  *
1907  * Raise the limit; IPS indicates we have thermal headroom.
1908  */
1909 bool i915_gpu_raise(void)
1910 {
1911         struct drm_i915_private *dev_priv;
1912         bool ret = true;
1913
1914         spin_lock(&mchdev_lock);
1915         if (!i915_mch_dev) {
1916                 ret = false;
1917                 goto out_unlock;
1918         }
1919         dev_priv = i915_mch_dev;
1920
1921         if (dev_priv->max_delay > dev_priv->fmax)
1922                 dev_priv->max_delay--;
1923
1924 out_unlock:
1925         spin_unlock(&mchdev_lock);
1926
1927         return ret;
1928 }
1929 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1930
1931 /**
1932  * i915_gpu_lower - lower GPU frequency limit
1933  *
1934  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1935  * frequency maximum.
1936  */
1937 bool i915_gpu_lower(void)
1938 {
1939         struct drm_i915_private *dev_priv;
1940         bool ret = true;
1941
1942         spin_lock(&mchdev_lock);
1943         if (!i915_mch_dev) {
1944                 ret = false;
1945                 goto out_unlock;
1946         }
1947         dev_priv = i915_mch_dev;
1948
1949         if (dev_priv->max_delay < dev_priv->min_delay)
1950                 dev_priv->max_delay++;
1951
1952 out_unlock:
1953         spin_unlock(&mchdev_lock);
1954
1955         return ret;
1956 }
1957 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1958
1959 /**
1960  * i915_gpu_busy - indicate GPU business to IPS
1961  *
1962  * Tell the IPS driver whether or not the GPU is busy.
1963  */
1964 bool i915_gpu_busy(void)
1965 {
1966         struct drm_i915_private *dev_priv;
1967         bool ret = false;
1968
1969         spin_lock(&mchdev_lock);
1970         if (!i915_mch_dev)
1971                 goto out_unlock;
1972         dev_priv = i915_mch_dev;
1973
1974         ret = dev_priv->busy;
1975
1976 out_unlock:
1977         spin_unlock(&mchdev_lock);
1978
1979         return ret;
1980 }
1981 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1982
1983 /**
1984  * i915_gpu_turbo_disable - disable graphics turbo
1985  *
1986  * Disable graphics turbo by resetting the max frequency and setting the
1987  * current frequency to the default.
1988  */
1989 bool i915_gpu_turbo_disable(void)
1990 {
1991         struct drm_i915_private *dev_priv;
1992         bool ret = true;
1993
1994         spin_lock(&mchdev_lock);
1995         if (!i915_mch_dev) {
1996                 ret = false;
1997                 goto out_unlock;
1998         }
1999         dev_priv = i915_mch_dev;
2000
2001         dev_priv->max_delay = dev_priv->fstart;
2002
2003         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2004                 ret = false;
2005
2006 out_unlock:
2007         spin_unlock(&mchdev_lock);
2008
2009         return ret;
2010 }
2011 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2012
2013 /**
2014  * i915_driver_load - setup chip and create an initial config
2015  * @dev: DRM device
2016  * @flags: startup flags
2017  *
2018  * The driver load routine has to do several things:
2019  *   - drive output discovery via intel_modeset_init()
2020  *   - initialize the memory manager
2021  *   - allocate initial config memory
2022  *   - setup the DRM framebuffer with the allocated memory
2023  */
2024 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2025 {
2026         struct drm_i915_private *dev_priv;
2027         resource_size_t base, size;
2028         int ret = 0, mmio_bar;
2029         uint32_t agp_size, prealloc_size, prealloc_start;
2030         /* i915 has 4 more counters */
2031         dev->counters += 4;
2032         dev->types[6] = _DRM_STAT_IRQ;
2033         dev->types[7] = _DRM_STAT_PRIMARY;
2034         dev->types[8] = _DRM_STAT_SECONDARY;
2035         dev->types[9] = _DRM_STAT_DMA;
2036
2037         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2038         if (dev_priv == NULL)
2039                 return -ENOMEM;
2040
2041         dev->dev_private = (void *)dev_priv;
2042         dev_priv->dev = dev;
2043         dev_priv->info = (struct intel_device_info *) flags;
2044
2045         /* Add register map (needed for suspend/resume) */
2046         mmio_bar = IS_I9XX(dev) ? 0 : 1;
2047         base = drm_get_resource_start(dev, mmio_bar);
2048         size = drm_get_resource_len(dev, mmio_bar);
2049
2050         if (i915_get_bridge_dev(dev)) {
2051                 ret = -EIO;
2052                 goto free_priv;
2053         }
2054
2055         dev_priv->regs = ioremap(base, size);
2056         if (!dev_priv->regs) {
2057                 DRM_ERROR("failed to map registers\n");
2058                 ret = -EIO;
2059                 goto put_bridge;
2060         }
2061
2062         dev_priv->mm.gtt_mapping =
2063                 io_mapping_create_wc(dev->agp->base,
2064                                      dev->agp->agp_info.aper_size * 1024*1024);
2065         if (dev_priv->mm.gtt_mapping == NULL) {
2066                 ret = -EIO;
2067                 goto out_rmmap;
2068         }
2069
2070         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2071          * one would think, because the kernel disables PAT on first
2072          * generation Core chips because WC PAT gets overridden by a UC
2073          * MTRR if present.  Even if a UC MTRR isn't present.
2074          */
2075         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2076                                          dev->agp->agp_info.aper_size *
2077                                          1024 * 1024,
2078                                          MTRR_TYPE_WRCOMB, 1);
2079         if (dev_priv->mm.gtt_mtrr < 0) {
2080                 DRM_INFO("MTRR allocation failed.  Graphics "
2081                          "performance may suffer.\n");
2082         }
2083
2084         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2085         if (ret)
2086                 goto out_iomapfree;
2087
2088         dev_priv->wq = create_singlethread_workqueue("i915");
2089         if (dev_priv->wq == NULL) {
2090                 DRM_ERROR("Failed to create our workqueue.\n");
2091                 ret = -ENOMEM;
2092                 goto out_iomapfree;
2093         }
2094
2095         /* enable GEM by default */
2096         dev_priv->has_gem = 1;
2097
2098         if (prealloc_size > agp_size * 3 / 4) {
2099                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2100                           "memory stolen.\n",
2101                           prealloc_size / 1024, agp_size / 1024);
2102                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2103                           "updating the BIOS to fix).\n");
2104                 dev_priv->has_gem = 0;
2105         }
2106
2107         if (dev_priv->has_gem == 0 &&
2108             drm_core_check_feature(dev, DRIVER_MODESET)) {
2109                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2110                 ret = -ENODEV;
2111                 goto out_iomapfree;
2112         }
2113
2114         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2115         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2116         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2117                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2118                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2119         }
2120
2121         /* Try to make sure MCHBAR is enabled before poking at it */
2122         intel_setup_mchbar(dev);
2123
2124         i915_gem_load(dev);
2125
2126         /* Init HWS */
2127         if (!I915_NEED_GFX_HWS(dev)) {
2128                 ret = i915_init_phys_hws(dev);
2129                 if (ret != 0)
2130                         goto out_workqueue_free;
2131         }
2132
2133         if (IS_PINEVIEW(dev))
2134                 i915_pineview_get_mem_freq(dev);
2135         else if (IS_IRONLAKE(dev))
2136                 i915_ironlake_get_mem_freq(dev);
2137
2138         /* On the 945G/GM, the chipset reports the MSI capability on the
2139          * integrated graphics even though the support isn't actually there
2140          * according to the published specs.  It doesn't appear to function
2141          * correctly in testing on 945G.
2142          * This may be a side effect of MSI having been made available for PEG
2143          * and the registers being closely associated.
2144          *
2145          * According to chipset errata, on the 965GM, MSI interrupts may
2146          * be lost or delayed, but we use them anyways to avoid
2147          * stuck interrupts on some machines.
2148          */
2149         if (!IS_I945G(dev) && !IS_I945GM(dev))
2150                 pci_enable_msi(dev->pdev);
2151
2152         spin_lock_init(&dev_priv->user_irq_lock);
2153         spin_lock_init(&dev_priv->error_lock);
2154         dev_priv->trace_irq_seqno = 0;
2155
2156         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2157
2158         if (ret) {
2159                 (void) i915_driver_unload(dev);
2160                 return ret;
2161         }
2162
2163         /* Start out suspended */
2164         dev_priv->mm.suspended = 1;
2165
2166         intel_detect_pch(dev);
2167
2168         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2169                 ret = i915_load_modeset_init(dev, prealloc_start,
2170                                              prealloc_size, agp_size);
2171                 if (ret < 0) {
2172                         DRM_ERROR("failed to init modeset\n");
2173                         goto out_workqueue_free;
2174                 }
2175         }
2176
2177         /* Must be done after probing outputs */
2178         intel_opregion_init(dev, 0);
2179
2180         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2181                     (unsigned long) dev);
2182
2183         spin_lock(&mchdev_lock);
2184         i915_mch_dev = dev_priv;
2185         dev_priv->mchdev_lock = &mchdev_lock;
2186         spin_unlock(&mchdev_lock);
2187
2188         return 0;
2189
2190 out_workqueue_free:
2191         destroy_workqueue(dev_priv->wq);
2192 out_iomapfree:
2193         io_mapping_free(dev_priv->mm.gtt_mapping);
2194 out_rmmap:
2195         iounmap(dev_priv->regs);
2196 put_bridge:
2197         pci_dev_put(dev_priv->bridge_dev);
2198 free_priv:
2199         kfree(dev_priv);
2200         return ret;
2201 }
2202
2203 int i915_driver_unload(struct drm_device *dev)
2204 {
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206
2207         i915_destroy_error_state(dev);
2208
2209         spin_lock(&mchdev_lock);
2210         i915_mch_dev = NULL;
2211         spin_unlock(&mchdev_lock);
2212
2213         destroy_workqueue(dev_priv->wq);
2214         del_timer_sync(&dev_priv->hangcheck_timer);
2215
2216         io_mapping_free(dev_priv->mm.gtt_mapping);
2217         if (dev_priv->mm.gtt_mtrr >= 0) {
2218                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2219                          dev->agp->agp_info.aper_size * 1024 * 1024);
2220                 dev_priv->mm.gtt_mtrr = -1;
2221         }
2222
2223         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2224                 intel_modeset_cleanup(dev);
2225
2226                 /*
2227                  * free the memory space allocated for the child device
2228                  * config parsed from VBT
2229                  */
2230                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2231                         kfree(dev_priv->child_dev);
2232                         dev_priv->child_dev = NULL;
2233                         dev_priv->child_dev_num = 0;
2234                 }
2235                 drm_irq_uninstall(dev);
2236                 vga_switcheroo_unregister_client(dev->pdev);
2237                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2238         }
2239
2240         if (dev->pdev->msi_enabled)
2241                 pci_disable_msi(dev->pdev);
2242
2243         if (dev_priv->regs != NULL)
2244                 iounmap(dev_priv->regs);
2245
2246         intel_opregion_free(dev, 0);
2247
2248         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2249                 i915_gem_free_all_phys_object(dev);
2250
2251                 mutex_lock(&dev->struct_mutex);
2252                 i915_gem_cleanup_ringbuffer(dev);
2253                 mutex_unlock(&dev->struct_mutex);
2254                 if (I915_HAS_FBC(dev) && i915_powersave)
2255                         i915_cleanup_compression(dev);
2256                 drm_mm_takedown(&dev_priv->vram);
2257                 i915_gem_lastclose(dev);
2258
2259                 intel_cleanup_overlay(dev);
2260         }
2261
2262         intel_teardown_mchbar(dev);
2263
2264         pci_dev_put(dev_priv->bridge_dev);
2265         kfree(dev->dev_private);
2266
2267         return 0;
2268 }
2269
2270 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2271 {
2272         struct drm_i915_file_private *i915_file_priv;
2273
2274         DRM_DEBUG_DRIVER("\n");
2275         i915_file_priv = (struct drm_i915_file_private *)
2276             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2277
2278         if (!i915_file_priv)
2279                 return -ENOMEM;
2280
2281         file_priv->driver_priv = i915_file_priv;
2282
2283         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2284
2285         return 0;
2286 }
2287
2288 /**
2289  * i915_driver_lastclose - clean up after all DRM clients have exited
2290  * @dev: DRM device
2291  *
2292  * Take care of cleaning up after all DRM clients have exited.  In the
2293  * mode setting case, we want to restore the kernel's initial mode (just
2294  * in case the last client left us in a bad state).
2295  *
2296  * Additionally, in the non-mode setting case, we'll tear down the AGP
2297  * and DMA structures, since the kernel won't be using them, and clea
2298  * up any GEM state.
2299  */
2300 void i915_driver_lastclose(struct drm_device * dev)
2301 {
2302         drm_i915_private_t *dev_priv = dev->dev_private;
2303
2304         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2305                 drm_fb_helper_restore();
2306                 vga_switcheroo_process_delayed_switch();
2307                 return;
2308         }
2309
2310         i915_gem_lastclose(dev);
2311
2312         if (dev_priv->agp_heap)
2313                 i915_mem_takedown(&(dev_priv->agp_heap));
2314
2315         i915_dma_cleanup(dev);
2316 }
2317
2318 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2319 {
2320         drm_i915_private_t *dev_priv = dev->dev_private;
2321         i915_gem_release(dev, file_priv);
2322         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2323                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2324 }
2325
2326 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2327 {
2328         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2329
2330         kfree(i915_file_priv);
2331 }
2332
2333 struct drm_ioctl_desc i915_ioctls[] = {
2334         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2335         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2336         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
2337         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2338         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2339         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2340         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
2341         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2342         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2343         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
2344         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2345         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2346         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2347         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2348         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
2349         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2350         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2351         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2352         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2353         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2354         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2355         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2356         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2357         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2358         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2359         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2360         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2361         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2362         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2363         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2364         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2365         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2366         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2367         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2368         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2369         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2370         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2371         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2372         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2373         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2374 };
2375
2376 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2377
2378 /**
2379  * Determine if the device really is AGP or not.
2380  *
2381  * All Intel graphics chipsets are treated as AGP, even if they are really
2382  * PCI-e.
2383  *
2384  * \param dev   The device to be tested.
2385  *
2386  * \returns
2387  * A value of 1 is always retured to indictate every i9x5 is AGP.
2388  */
2389 int i915_driver_device_is_agp(struct drm_device * dev)
2390 {
2391         return 1;
2392 }