drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include <linux/sched/mm.h>
  32 #include "intel_drv.h"
  33 #include "intel_guc_submission.h"
  34
  35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  36 {
  37         return to_i915(node->minor->dev);
  38 }
  39
  40 static int i915_capabilities(struct seq_file *m, void *data)
  41 {
  42         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  43         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  44         struct drm_printer p = drm_seq_file_printer(m);
  45
  46         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  47         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  48         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  49
  50         intel_device_info_dump_flags(info, &p);
  51         intel_device_info_dump_runtime(info, &p);
  52         intel_driver_caps_print(&dev_priv->caps, &p);
  53
  54         kernel_param_lock(THIS_MODULE);
  55         i915_params_dump(&i915_modparams, &p);
  56         kernel_param_unlock(THIS_MODULE);
  57
  58         return 0;
  59 }
  60
  61 static char get_active_flag(struct drm_i915_gem_object *obj)
  62 {
  63         return i915_gem_object_is_active(obj) ? '*' : ' ';
  64 }
  65
  66 static char get_pin_flag(struct drm_i915_gem_object *obj)
  67 {
  68         return obj->pin_global ? 'p' : ' ';
  69 }
  70
  71 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  72 {
  73         switch (i915_gem_object_get_tiling(obj)) {
  74         default:
  75         case I915_TILING_NONE: return ' ';
  76         case I915_TILING_X: return 'X';
  77         case I915_TILING_Y: return 'Y';
  78         }
  79 }
  80
  81 static char get_global_flag(struct drm_i915_gem_object *obj)
  82 {
  83         return obj->userfault_count ? 'g' : ' ';
  84 }
  85
  86 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
  87 {
  88         return obj->mm.mapping ? 'M' : ' ';
  89 }
  90
  91 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
  92 {
  93         u64 size = 0;
  94         struct i915_vma *vma;
  95
  96         for_each_ggtt_vma(vma, obj) {
  97                 if (drm_mm_node_allocated(&vma->node))
  98                         size += vma->node.size;
  99         }
 100
 101         return size;
 102 }
 103
 104 static const char *
 105 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
 106 {
 107         size_t x = 0;
 108
 109         switch (page_sizes) {
 110         case 0:
 111                 return "";
 112         case I915_GTT_PAGE_SIZE_4K:
 113                 return "4K";
 114         case I915_GTT_PAGE_SIZE_64K:
 115                 return "64K";
 116         case I915_GTT_PAGE_SIZE_2M:
 117                 return "2M";
 118         default:
 119                 if (!buf)
 120                         return "M";
 121
 122                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 123                         x += snprintf(buf + x, len - x, "2M, ");
 124                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 125                         x += snprintf(buf + x, len - x, "64K, ");
 126                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 127                         x += snprintf(buf + x, len - x, "4K, ");
 128                 buf[x-2] = '\0';
 129
 130                 return buf;
 131         }
 132 }
 133
 134 static void
 135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 138         struct intel_engine_cs *engine;
 139         struct i915_vma *vma;
 140         unsigned int frontbuffer_bits;
 141         int pin_count = 0;
 142
 143         lockdep_assert_held(&obj->base.dev->struct_mutex);
 144
 145         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 146                    &obj->base,
 147                    get_active_flag(obj),
 148                    get_pin_flag(obj),
 149                    get_tiling_flag(obj),
 150                    get_global_flag(obj),
 151                    get_pin_mapped_flag(obj),
 152                    obj->base.size / 1024,
 153                    obj->read_domains,
 154                    obj->write_domain,
 155                    i915_cache_level_str(dev_priv, obj->cache_level),
 156                    obj->mm.dirty ? " dirty" : "",
 157                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 158         if (obj->base.name)
 159                 seq_printf(m, " (name: %d)", obj->base.name);
 160         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 161                 if (i915_vma_is_pinned(vma))
 162                         pin_count++;
 163         }
 164         seq_printf(m, " (pinned x %d)", pin_count);
 165         if (obj->pin_global)
 166                 seq_printf(m, " (global)");
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (!drm_mm_node_allocated(&vma->node))
 169                         continue;
 170
 171                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 172                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 173                            vma->node.start, vma->node.size,
 174                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 175                 if (i915_vma_is_ggtt(vma)) {
 176                         switch (vma->ggtt_view.type) {
 177                         case I915_GGTT_VIEW_NORMAL:
 178                                 seq_puts(m, ", normal");
 179                                 break;
 180
 181                         case I915_GGTT_VIEW_PARTIAL:
 182                                 seq_printf(m, ", partial [%08llx+%x]",
 183                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 184                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 185                                 break;
 186
 187                         case I915_GGTT_VIEW_ROTATED:
 188                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 189                                            vma->ggtt_view.rotated.plane[0].width,
 190                                            vma->ggtt_view.rotated.plane[0].height,
 191                                            vma->ggtt_view.rotated.plane[0].stride,
 192                                            vma->ggtt_view.rotated.plane[0].offset,
 193                                            vma->ggtt_view.rotated.plane[1].width,
 194                                            vma->ggtt_view.rotated.plane[1].height,
 195                                            vma->ggtt_view.rotated.plane[1].stride,
 196                                            vma->ggtt_view.rotated.plane[1].offset);
 197                                 break;
 198
 199                         default:
 200                                 MISSING_CASE(vma->ggtt_view.type);
 201                                 break;
 202                         }
 203                 }
 204                 if (vma->fence)
 205                         seq_printf(m, " , fence: %d%s",
 206                                    vma->fence->id,
 207                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 208                 seq_puts(m, ")");
 209         }
 210         if (obj->stolen)
 211                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 212
 213         engine = i915_gem_object_last_write_engine(obj);
 214         if (engine)
 215                 seq_printf(m, " (%s)", engine->name);
 216
 217         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 218         if (frontbuffer_bits)
 219                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 220 }
 221
 222 static int obj_rank_by_stolen(const void *A, const void *B)
 223 {
 224         const struct drm_i915_gem_object *a =
 225                 *(const struct drm_i915_gem_object **)A;
 226         const struct drm_i915_gem_object *b =
 227                 *(const struct drm_i915_gem_object **)B;
 228
 229         if (a->stolen->start < b->stolen->start)
 230                 return -1;
 231         if (a->stolen->start > b->stolen->start)
 232                 return 1;
 233         return 0;
 234 }
 235
 236 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 237 {
 238         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 239         struct drm_device *dev = &dev_priv->drm;
 240         struct drm_i915_gem_object **objects;
 241         struct drm_i915_gem_object *obj;
 242         u64 total_obj_size, total_gtt_size;
 243         unsigned long total, count, n;
 244         int ret;
 245
 246         total = READ_ONCE(dev_priv->mm.object_count);
 247         objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
 248         if (!objects)
 249                 return -ENOMEM;
 250
 251         ret = mutex_lock_interruptible(&dev->struct_mutex);
 252         if (ret)
 253                 goto out;
 254
 255         total_obj_size = total_gtt_size = count = 0;
 256
 257         spin_lock(&dev_priv->mm.obj_lock);
 258         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 259                 if (count == total)
 260                         break;
 261
 262                 if (obj->stolen == NULL)
 263                         continue;
 264
 265                 objects[count++] = obj;
 266                 total_obj_size += obj->base.size;
 267                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 268
 269         }
 270         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 271                 if (count == total)
 272                         break;
 273
 274                 if (obj->stolen == NULL)
 275                         continue;
 276
 277                 objects[count++] = obj;
 278                 total_obj_size += obj->base.size;
 279         }
 280         spin_unlock(&dev_priv->mm.obj_lock);
 281
 282         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 283
 284         seq_puts(m, "Stolen:\n");
 285         for (n = 0; n < count; n++) {
 286                 seq_puts(m, "   ");
 287                 describe_obj(m, objects[n]);
 288                 seq_putc(m, '\n');
 289         }
 290         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 291                    count, total_obj_size, total_gtt_size);
 292
 293         mutex_unlock(&dev->struct_mutex);
 294 out:
 295         kvfree(objects);
 296         return ret;
 297 }
 298
 299 struct file_stats {
 300         struct drm_i915_file_private *file_priv;
 301         unsigned long count;
 302         u64 total, unbound;
 303         u64 global, shared;
 304         u64 active, inactive;
 305 };
 306
 307 static int per_file_stats(int id, void *ptr, void *data)
 308 {
 309         struct drm_i915_gem_object *obj = ptr;
 310         struct file_stats *stats = data;
 311         struct i915_vma *vma;
 312
 313         lockdep_assert_held(&obj->base.dev->struct_mutex);
 314
 315         stats->count++;
 316         stats->total += obj->base.size;
 317         if (!obj->bind_count)
 318                 stats->unbound += obj->base.size;
 319         if (obj->base.name || obj->base.dma_buf)
 320                 stats->shared += obj->base.size;
 321
 322         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 323                 if (!drm_mm_node_allocated(&vma->node))
 324                         continue;
 325
 326                 if (i915_vma_is_ggtt(vma)) {
 327                         stats->global += vma->node.size;
 328                 } else {
 329                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 330
 331                         if (ppgtt->vm.file != stats->file_priv)
 332                                 continue;
 333                 }
 334
 335                 if (i915_vma_is_active(vma))
 336                         stats->active += vma->node.size;
 337                 else
 338                         stats->inactive += vma->node.size;
 339         }
 340
 341         return 0;
 342 }
 343
 344 #define print_file_stats(m, name, stats) do { \
 345         if (stats.count) \
 346                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 347                            name, \
 348                            stats.count, \
 349                            stats.total, \
 350                            stats.active, \
 351                            stats.inactive, \
 352                            stats.global, \
 353                            stats.shared, \
 354                            stats.unbound); \
 355 } while (0)
 356
 357 static void print_batch_pool_stats(struct seq_file *m,
 358                                    struct drm_i915_private *dev_priv)
 359 {
 360         struct drm_i915_gem_object *obj;
 361         struct file_stats stats;
 362         struct intel_engine_cs *engine;
 363         enum intel_engine_id id;
 364         int j;
 365
 366         memset(&stats, 0, sizeof(stats));
 367
 368         for_each_engine(engine, dev_priv, id) {
 369                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 370                         list_for_each_entry(obj,
 371                                             &engine->batch_pool.cache_list[j],
 372                                             batch_pool_link)
 373                                 per_file_stats(0, obj, &stats);
 374                 }
 375         }
 376
 377         print_file_stats(m, "[k]batch pool", stats);
 378 }
 379
 380 static int per_file_ctx_stats(int idx, void *ptr, void *data)
 381 {
 382         struct i915_gem_context *ctx = ptr;
 383         struct intel_engine_cs *engine;
 384         enum intel_engine_id id;
 385
 386         for_each_engine(engine, ctx->i915, id) {
 387                 struct intel_context *ce = to_intel_context(ctx, engine);
 388
 389                 if (ce->state)
 390                         per_file_stats(0, ce->state->obj, data);
 391                 if (ce->ring)
 392                         per_file_stats(0, ce->ring->vma->obj, data);
 393         }
 394
 395         return 0;
 396 }
 397
 398 static void print_context_stats(struct seq_file *m,
 399                                 struct drm_i915_private *dev_priv)
 400 {
 401         struct drm_device *dev = &dev_priv->drm;
 402         struct file_stats stats;
 403         struct drm_file *file;
 404
 405         memset(&stats, 0, sizeof(stats));
 406
 407         mutex_lock(&dev->struct_mutex);
 408         if (dev_priv->kernel_context)
 409                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 410
 411         list_for_each_entry(file, &dev->filelist, lhead) {
 412                 struct drm_i915_file_private *fpriv = file->driver_priv;
 413                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 414         }
 415         mutex_unlock(&dev->struct_mutex);
 416
 417         print_file_stats(m, "[k]contexts", stats);
 418 }
 419
 420 static int i915_gem_object_info(struct seq_file *m, void *data)
 421 {
 422         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 423         struct drm_device *dev = &dev_priv->drm;
 424         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 425         u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
 426         u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
 427         struct drm_i915_gem_object *obj;
 428         unsigned int page_sizes = 0;
 429         struct drm_file *file;
 430         char buf[80];
 431         int ret;
 432
 433         ret = mutex_lock_interruptible(&dev->struct_mutex);
 434         if (ret)
 435                 return ret;
 436
 437         seq_printf(m, "%u objects, %llu bytes\n",
 438                    dev_priv->mm.object_count,
 439                    dev_priv->mm.object_memory);
 440
 441         size = count = 0;
 442         mapped_size = mapped_count = 0;
 443         purgeable_size = purgeable_count = 0;
 444         huge_size = huge_count = 0;
 445
 446         spin_lock(&dev_priv->mm.obj_lock);
 447         list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
 448                 size += obj->base.size;
 449                 ++count;
 450
 451                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 452                         purgeable_size += obj->base.size;
 453                         ++purgeable_count;
 454                 }
 455
 456                 if (obj->mm.mapping) {
 457                         mapped_count++;
 458                         mapped_size += obj->base.size;
 459                 }
 460
 461                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 462                         huge_count++;
 463                         huge_size += obj->base.size;
 464                         page_sizes |= obj->mm.page_sizes.sg;
 465                 }
 466         }
 467         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 468
 469         size = count = dpy_size = dpy_count = 0;
 470         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 471                 size += obj->base.size;
 472                 ++count;
 473
 474                 if (obj->pin_global) {
 475                         dpy_size += obj->base.size;
 476                         ++dpy_count;
 477                 }
 478
 479                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 480                         purgeable_size += obj->base.size;
 481                         ++purgeable_count;
 482                 }
 483
 484                 if (obj->mm.mapping) {
 485                         mapped_count++;
 486                         mapped_size += obj->base.size;
 487                 }
 488
 489                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 490                         huge_count++;
 491                         huge_size += obj->base.size;
 492                         page_sizes |= obj->mm.page_sizes.sg;
 493                 }
 494         }
 495         spin_unlock(&dev_priv->mm.obj_lock);
 496
 497         seq_printf(m, "%u bound objects, %llu bytes\n",
 498                    count, size);
 499         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 500                    purgeable_count, purgeable_size);
 501         seq_printf(m, "%u mapped objects, %llu bytes\n",
 502                    mapped_count, mapped_size);
 503         seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
 504                    huge_count,
 505                    stringify_page_sizes(page_sizes, buf, sizeof(buf)),
 506                    huge_size);
 507         seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
 508                    dpy_count, dpy_size);
 509
 510         seq_printf(m, "%llu [%pa] gtt total\n",
 511                    ggtt->vm.total, &ggtt->mappable_end);
 512         seq_printf(m, "Supported page sizes: %s\n",
 513                    stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
 514                                         buf, sizeof(buf)));
 515
 516         seq_putc(m, '\n');
 517         print_batch_pool_stats(m, dev_priv);
 518         mutex_unlock(&dev->struct_mutex);
 519
 520         mutex_lock(&dev->filelist_mutex);
 521         print_context_stats(m, dev_priv);
 522         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 523                 struct file_stats stats;
 524                 struct drm_i915_file_private *file_priv = file->driver_priv;
 525                 struct i915_request *request;
 526                 struct task_struct *task;
 527
 528                 mutex_lock(&dev->struct_mutex);
 529
 530                 memset(&stats, 0, sizeof(stats));
 531                 stats.file_priv = file->driver_priv;
 532                 spin_lock(&file->table_lock);
 533                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 534                 spin_unlock(&file->table_lock);
 535                 /*
 536                  * Although we have a valid reference on file->pid, that does
 537                  * not guarantee that the task_struct who called get_pid() is
 538                  * still alive (e.g. get_pid(current) => fork() => exit()).
 539                  * Therefore, we need to protect this ->comm access using RCU.
 540                  */
 541                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 542                                                    struct i915_request,
 543                                                    client_link);
 544                 rcu_read_lock();
 545                 task = pid_task(request && request->gem_context->pid ?
 546                                 request->gem_context->pid : file->pid,
 547                                 PIDTYPE_PID);
 548                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 549                 rcu_read_unlock();
 550
 551                 mutex_unlock(&dev->struct_mutex);
 552         }
 553         mutex_unlock(&dev->filelist_mutex);
 554
 555         return 0;
 556 }
 557
 558 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 559 {
 560         struct drm_info_node *node = m->private;
 561         struct drm_i915_private *dev_priv = node_to_i915(node);
 562         struct drm_device *dev = &dev_priv->drm;
 563         struct drm_i915_gem_object **objects;
 564         struct drm_i915_gem_object *obj;
 565         u64 total_obj_size, total_gtt_size;
 566         unsigned long nobject, n;
 567         int count, ret;
 568
 569         nobject = READ_ONCE(dev_priv->mm.object_count);
 570         objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
 571         if (!objects)
 572                 return -ENOMEM;
 573
 574         ret = mutex_lock_interruptible(&dev->struct_mutex);
 575         if (ret)
 576                 return ret;
 577
 578         count = 0;
 579         spin_lock(&dev_priv->mm.obj_lock);
 580         list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
 581                 objects[count++] = obj;
 582                 if (count == nobject)
 583                         break;
 584         }
 585         spin_unlock(&dev_priv->mm.obj_lock);
 586
 587         total_obj_size = total_gtt_size = 0;
 588         for (n = 0;  n < count; n++) {
 589                 obj = objects[n];
 590
 591                 seq_puts(m, "   ");
 592                 describe_obj(m, obj);
 593                 seq_putc(m, '\n');
 594                 total_obj_size += obj->base.size;
 595                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 596         }
 597
 598         mutex_unlock(&dev->struct_mutex);
 599
 600         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 601                    count, total_obj_size, total_gtt_size);
 602         kvfree(objects);
 603
 604         return 0;
 605 }
 606
 607 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 608 {
 609         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 610         struct drm_device *dev = &dev_priv->drm;
 611         struct drm_i915_gem_object *obj;
 612         struct intel_engine_cs *engine;
 613         enum intel_engine_id id;
 614         int total = 0;
 615         int ret, j;
 616
 617         ret = mutex_lock_interruptible(&dev->struct_mutex);
 618         if (ret)
 619                 return ret;
 620
 621         for_each_engine(engine, dev_priv, id) {
 622                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 623                         int count;
 624
 625                         count = 0;
 626                         list_for_each_entry(obj,
 627                                             &engine->batch_pool.cache_list[j],
 628                                             batch_pool_link)
 629                                 count++;
 630                         seq_printf(m, "%s cache[%d]: %d objects\n",
 631                                    engine->name, j, count);
 632
 633                         list_for_each_entry(obj,
 634                                             &engine->batch_pool.cache_list[j],
 635                                             batch_pool_link) {
 636                                 seq_puts(m, "   ");
 637                                 describe_obj(m, obj);
 638                                 seq_putc(m, '\n');
 639                         }
 640
 641                         total += count;
 642                 }
 643         }
 644
 645         seq_printf(m, "total: %d\n", total);
 646
 647         mutex_unlock(&dev->struct_mutex);
 648
 649         return 0;
 650 }
 651
 652 static void gen8_display_interrupt_info(struct seq_file *m)
 653 {
 654         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 655         int pipe;
 656
 657         for_each_pipe(dev_priv, pipe) {
 658                 enum intel_display_power_domain power_domain;
 659
 660                 power_domain = POWER_DOMAIN_PIPE(pipe);
 661                 if (!intel_display_power_get_if_enabled(dev_priv,
 662                                                         power_domain)) {
 663                         seq_printf(m, "Pipe %c power disabled\n",
 664                                    pipe_name(pipe));
 665                         continue;
 666                 }
 667                 seq_printf(m, "Pipe %c IMR:\t%08x\n",
 668                            pipe_name(pipe),
 669                            I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 670                 seq_printf(m, "Pipe %c IIR:\t%08x\n",
 671                            pipe_name(pipe),
 672                            I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 673                 seq_printf(m, "Pipe %c IER:\t%08x\n",
 674                            pipe_name(pipe),
 675                            I915_READ(GEN8_DE_PIPE_IER(pipe)));
 676
 677                 intel_display_power_put(dev_priv, power_domain);
 678         }
 679
 680         seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 681                    I915_READ(GEN8_DE_PORT_IMR));
 682         seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 683                    I915_READ(GEN8_DE_PORT_IIR));
 684         seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 685                    I915_READ(GEN8_DE_PORT_IER));
 686
 687         seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 688                    I915_READ(GEN8_DE_MISC_IMR));
 689         seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 690                    I915_READ(GEN8_DE_MISC_IIR));
 691         seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 692                    I915_READ(GEN8_DE_MISC_IER));
 693
 694         seq_printf(m, "PCU interrupt mask:\t%08x\n",
 695                    I915_READ(GEN8_PCU_IMR));
 696         seq_printf(m, "PCU interrupt identity:\t%08x\n",
 697                    I915_READ(GEN8_PCU_IIR));
 698         seq_printf(m, "PCU interrupt enable:\t%08x\n",
 699                    I915_READ(GEN8_PCU_IER));
 700 }
 701
 702 static int i915_interrupt_info(struct seq_file *m, void *data)
 703 {
 704         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 705         struct intel_engine_cs *engine;
 706         enum intel_engine_id id;
 707         int i, pipe;
 708
 709         intel_runtime_pm_get(dev_priv);
 710
 711         if (IS_CHERRYVIEW(dev_priv)) {
 712                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 713                            I915_READ(GEN8_MASTER_IRQ));
 714
 715                 seq_printf(m, "Display IER:\t%08x\n",
 716                            I915_READ(VLV_IER));
 717                 seq_printf(m, "Display IIR:\t%08x\n",
 718                            I915_READ(VLV_IIR));
 719                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 720                            I915_READ(VLV_IIR_RW));
 721                 seq_printf(m, "Display IMR:\t%08x\n",
 722                            I915_READ(VLV_IMR));
 723                 for_each_pipe(dev_priv, pipe) {
 724                         enum intel_display_power_domain power_domain;
 725
 726                         power_domain = POWER_DOMAIN_PIPE(pipe);
 727                         if (!intel_display_power_get_if_enabled(dev_priv,
 728                                                                 power_domain)) {
 729                                 seq_printf(m, "Pipe %c power disabled\n",
 730                                            pipe_name(pipe));
 731                                 continue;
 732                         }
 733
 734                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 735                                    pipe_name(pipe),
 736                                    I915_READ(PIPESTAT(pipe)));
 737
 738                         intel_display_power_put(dev_priv, power_domain);
 739                 }
 740
 741                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 742                 seq_printf(m, "Port hotplug:\t%08x\n",
 743                            I915_READ(PORT_HOTPLUG_EN));
 744                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 745                            I915_READ(VLV_DPFLIPSTAT));
 746                 seq_printf(m, "DPINVGTT:\t%08x\n",
 747                            I915_READ(DPINVGTT));
 748                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 749
 750                 for (i = 0; i < 4; i++) {
 751                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 752                                    i, I915_READ(GEN8_GT_IMR(i)));
 753                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 754                                    i, I915_READ(GEN8_GT_IIR(i)));
 755                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 756                                    i, I915_READ(GEN8_GT_IER(i)));
 757                 }
 758
 759                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 760                            I915_READ(GEN8_PCU_IMR));
 761                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 762                            I915_READ(GEN8_PCU_IIR));
 763                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 764                            I915_READ(GEN8_PCU_IER));
 765         } else if (INTEL_GEN(dev_priv) >= 11) {
 766                 seq_printf(m, "Master Interrupt Control:  %08x\n",
 767                            I915_READ(GEN11_GFX_MSTR_IRQ));
 768
 769                 seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
 770                            I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
 771                 seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
 772                            I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
 773                 seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
 774                            I915_READ(GEN11_GUC_SG_INTR_ENABLE));
 775                 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
 776                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
 777                 seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
 778                            I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
 779                 seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
 780                            I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
 781
 782                 seq_printf(m, "Display Interrupt Control:\t%08x\n",
 783                            I915_READ(GEN11_DISPLAY_INT_CTL));
 784
 785                 gen8_display_interrupt_info(m);
 786         } else if (INTEL_GEN(dev_priv) >= 8) {
 787                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 788                            I915_READ(GEN8_MASTER_IRQ));
 789
 790                 for (i = 0; i < 4; i++) {
 791                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 792                                    i, I915_READ(GEN8_GT_IMR(i)));
 793                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 794                                    i, I915_READ(GEN8_GT_IIR(i)));
 795                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 796                                    i, I915_READ(GEN8_GT_IER(i)));
 797                 }
 798
 799                 gen8_display_interrupt_info(m);
 800         } else if (IS_VALLEYVIEW(dev_priv)) {
 801                 seq_printf(m, "Display IER:\t%08x\n",
 802                            I915_READ(VLV_IER));
 803                 seq_printf(m, "Display IIR:\t%08x\n",
 804                            I915_READ(VLV_IIR));
 805                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 806                            I915_READ(VLV_IIR_RW));
 807                 seq_printf(m, "Display IMR:\t%08x\n",
 808                            I915_READ(VLV_IMR));
 809                 for_each_pipe(dev_priv, pipe) {
 810                         enum intel_display_power_domain power_domain;
 811
 812                         power_domain = POWER_DOMAIN_PIPE(pipe);
 813                         if (!intel_display_power_get_if_enabled(dev_priv,
 814                                                                 power_domain)) {
 815                                 seq_printf(m, "Pipe %c power disabled\n",
 816                                            pipe_name(pipe));
 817                                 continue;
 818                         }
 819
 820                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(PIPESTAT(pipe)));
 823                         intel_display_power_put(dev_priv, power_domain);
 824                 }
 825
 826                 seq_printf(m, "Master IER:\t%08x\n",
 827                            I915_READ(VLV_MASTER_IER));
 828
 829                 seq_printf(m, "Render IER:\t%08x\n",
 830                            I915_READ(GTIER));
 831                 seq_printf(m, "Render IIR:\t%08x\n",
 832                            I915_READ(GTIIR));
 833                 seq_printf(m, "Render IMR:\t%08x\n",
 834                            I915_READ(GTIMR));
 835
 836                 seq_printf(m, "PM IER:\t\t%08x\n",
 837                            I915_READ(GEN6_PMIER));
 838                 seq_printf(m, "PM IIR:\t\t%08x\n",
 839                            I915_READ(GEN6_PMIIR));
 840                 seq_printf(m, "PM IMR:\t\t%08x\n",
 841                            I915_READ(GEN6_PMIMR));
 842
 843                 seq_printf(m, "Port hotplug:\t%08x\n",
 844                            I915_READ(PORT_HOTPLUG_EN));
 845                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 846                            I915_READ(VLV_DPFLIPSTAT));
 847                 seq_printf(m, "DPINVGTT:\t%08x\n",
 848                            I915_READ(DPINVGTT));
 849
 850         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 851                 seq_printf(m, "Interrupt enable:    %08x\n",
 852                            I915_READ(IER));
 853                 seq_printf(m, "Interrupt identity:  %08x\n",
 854                            I915_READ(IIR));
 855                 seq_printf(m, "Interrupt mask:      %08x\n",
 856                            I915_READ(IMR));
 857                 for_each_pipe(dev_priv, pipe)
 858                         seq_printf(m, "Pipe %c stat:         %08x\n",
 859                                    pipe_name(pipe),
 860                                    I915_READ(PIPESTAT(pipe)));
 861         } else {
 862                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 863                            I915_READ(DEIER));
 864                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 865                            I915_READ(DEIIR));
 866                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 867                            I915_READ(DEIMR));
 868                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 869                            I915_READ(SDEIER));
 870                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 871                            I915_READ(SDEIIR));
 872                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 873                            I915_READ(SDEIMR));
 874                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 875                            I915_READ(GTIER));
 876                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 877                            I915_READ(GTIIR));
 878                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 879                            I915_READ(GTIMR));
 880         }
 881
 882         if (INTEL_GEN(dev_priv) >= 11) {
 883                 seq_printf(m, "RCS Intr Mask:\t %08x\n",
 884                            I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
 885                 seq_printf(m, "BCS Intr Mask:\t %08x\n",
 886                            I915_READ(GEN11_BCS_RSVD_INTR_MASK));
 887                 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
 888                            I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
 889                 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
 890                            I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
 891                 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
 892                            I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
 893                 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
 894                            I915_READ(GEN11_GUC_SG_INTR_MASK));
 895                 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
 896                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
 897                 seq_printf(m, "Crypto Intr Mask:\t %08x\n",
 898                            I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
 899                 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
 900                            I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
 901
 902         } else if (INTEL_GEN(dev_priv) >= 6) {
 903                 for_each_engine(engine, dev_priv, id) {
 904                         seq_printf(m,
 905                                    "Graphics Interrupt mask (%s):       %08x\n",
 906                                    engine->name, I915_READ_IMR(engine));
 907                 }
 908         }
 909
 910         intel_runtime_pm_put(dev_priv);
 911
 912         return 0;
 913 }
 914
 915 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 916 {
 917         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 918         struct drm_device *dev = &dev_priv->drm;
 919         int i, ret;
 920
 921         ret = mutex_lock_interruptible(&dev->struct_mutex);
 922         if (ret)
 923                 return ret;
 924
 925         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 926         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 927                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 928
 929                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 930                            i, dev_priv->fence_regs[i].pin_count);
 931                 if (!vma)
 932                         seq_puts(m, "unused");
 933                 else
 934                         describe_obj(m, vma->obj);
 935                 seq_putc(m, '\n');
 936         }
 937
 938         mutex_unlock(&dev->struct_mutex);
 939         return 0;
 940 }
 941
 942 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 943 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 944                               size_t count, loff_t *pos)
 945 {
 946         struct i915_gpu_state *error = file->private_data;
 947         struct drm_i915_error_state_buf str;
 948         ssize_t ret;
 949         loff_t tmp;
 950
 951         if (!error)
 952                 return 0;
 953
 954         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 955         if (ret)
 956                 return ret;
 957
 958         ret = i915_error_state_to_str(&str, error);
 959         if (ret)
 960                 goto out;
 961
 962         tmp = 0;
 963         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 964         if (ret < 0)
 965                 goto out;
 966
 967         *pos = str.start + ret;
 968 out:
 969         i915_error_state_buf_release(&str);
 970         return ret;
 971 }
 972
 973 static int gpu_state_release(struct inode *inode, struct file *file)
 974 {
 975         i915_gpu_state_put(file->private_data);
 976         return 0;
 977 }
 978
 979 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 980 {
 981         struct drm_i915_private *i915 = inode->i_private;
 982         struct i915_gpu_state *gpu;
 983
 984         intel_runtime_pm_get(i915);
 985         gpu = i915_capture_gpu_state(i915);
 986         intel_runtime_pm_put(i915);
 987         if (!gpu)
 988                 return -ENOMEM;
 989
 990         file->private_data = gpu;
 991         return 0;
 992 }
 993
 994 static const struct file_operations i915_gpu_info_fops = {
 995         .owner = THIS_MODULE,
 996         .open = i915_gpu_info_open,
 997         .read = gpu_state_read,
 998         .llseek = default_llseek,
 999         .release = gpu_state_release,
1000 };
1001
1002 static ssize_t
1003 i915_error_state_write(struct file *filp,
1004                        const char __user *ubuf,
1005                        size_t cnt,
1006                        loff_t *ppos)
1007 {
1008         struct i915_gpu_state *error = filp->private_data;
1009
1010         if (!error)
1011                 return 0;
1012
1013         DRM_DEBUG_DRIVER("Resetting error state\n");
1014         i915_reset_error_state(error->i915);
1015
1016         return cnt;
1017 }
1018
1019 static int i915_error_state_open(struct inode *inode, struct file *file)
1020 {
1021         file->private_data = i915_first_error_state(inode->i_private);
1022         return 0;
1023 }
1024
1025 static const struct file_operations i915_error_state_fops = {
1026         .owner = THIS_MODULE,
1027         .open = i915_error_state_open,
1028         .read = gpu_state_read,
1029         .write = i915_error_state_write,
1030         .llseek = default_llseek,
1031         .release = gpu_state_release,
1032 };
1033 #endif
1034
1035 static int
1036 i915_next_seqno_set(void *data, u64 val)
1037 {
1038         struct drm_i915_private *dev_priv = data;
1039         struct drm_device *dev = &dev_priv->drm;
1040         int ret;
1041
1042         ret = mutex_lock_interruptible(&dev->struct_mutex);
1043         if (ret)
1044                 return ret;
1045
1046         intel_runtime_pm_get(dev_priv);
1047         ret = i915_gem_set_global_seqno(dev, val);
1048         intel_runtime_pm_put(dev_priv);
1049
1050         mutex_unlock(&dev->struct_mutex);
1051
1052         return ret;
1053 }
1054
1055 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1056                         NULL, i915_next_seqno_set,
1057                         "0x%llx\n");
1058
1059 static int i915_frequency_info(struct seq_file *m, void *unused)
1060 {
1061         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1062         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1063         int ret = 0;
1064
1065         intel_runtime_pm_get(dev_priv);
1066
1067         if (IS_GEN5(dev_priv)) {
1068                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1069                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1070
1071                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1072                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1073                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1074                            MEMSTAT_VID_SHIFT);
1075                 seq_printf(m, "Current P-state: %d\n",
1076                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1077         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1078                 u32 rpmodectl, freq_sts;
1079
1080                 mutex_lock(&dev_priv->pcu_lock);
1081
1082                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1083                 seq_printf(m, "Video Turbo Mode: %s\n",
1084                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1085                 seq_printf(m, "HW control enabled: %s\n",
1086                            yesno(rpmodectl & GEN6_RP_ENABLE));
1087                 seq_printf(m, "SW control enabled: %s\n",
1088                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1089                                   GEN6_RP_MEDIA_SW_MODE));
1090
1091                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1092                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1093                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1094
1095                 seq_printf(m, "actual GPU freq: %d MHz\n",
1096                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1097
1098                 seq_printf(m, "current GPU freq: %d MHz\n",
1099                            intel_gpu_freq(dev_priv, rps->cur_freq));
1100
1101                 seq_printf(m, "max GPU freq: %d MHz\n",
1102                            intel_gpu_freq(dev_priv, rps->max_freq));
1103
1104                 seq_printf(m, "min GPU freq: %d MHz\n",
1105                            intel_gpu_freq(dev_priv, rps->min_freq));
1106
1107                 seq_printf(m, "idle GPU freq: %d MHz\n",
1108                            intel_gpu_freq(dev_priv, rps->idle_freq));
1109
1110                 seq_printf(m,
1111                            "efficient (RPe) frequency: %d MHz\n",
1112                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1113                 mutex_unlock(&dev_priv->pcu_lock);
1114         } else if (INTEL_GEN(dev_priv) >= 6) {
1115                 u32 rp_state_limits;
1116                 u32 gt_perf_status;
1117                 u32 rp_state_cap;
1118                 u32 rpmodectl, rpinclimit, rpdeclimit;
1119                 u32 rpstat, cagf, reqf;
1120                 u32 rpupei, rpcurup, rpprevup;
1121                 u32 rpdownei, rpcurdown, rpprevdown;
1122                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1123                 int max_freq;
1124
1125                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1126                 if (IS_GEN9_LP(dev_priv)) {
1127                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1128                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1129                 } else {
1130                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1131                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1132                 }
1133
1134                 /* RPSTAT1 is in the GT power well */
1135                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1136
1137                 reqf = I915_READ(GEN6_RPNSWREQ);
1138                 if (INTEL_GEN(dev_priv) >= 9)
1139                         reqf >>= 23;
1140                 else {
1141                         reqf &= ~GEN6_TURBO_DISABLE;
1142                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1143                                 reqf >>= 24;
1144                         else
1145                                 reqf >>= 25;
1146                 }
1147                 reqf = intel_gpu_freq(dev_priv, reqf);
1148
1149                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1150                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1151                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1152
1153                 rpstat = I915_READ(GEN6_RPSTAT1);
1154                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1155                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1156                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1157                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1158                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1159                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1160                 cagf = intel_gpu_freq(dev_priv,
1161                                       intel_get_cagf(dev_priv, rpstat));
1162
1163                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1164
1165                 if (INTEL_GEN(dev_priv) >= 11) {
1166                         pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1167                         pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
1168                         /*
1169                          * The equivalent to the PM ISR & IIR cannot be read
1170                          * without affecting the current state of the system
1171                          */
1172                         pm_isr = 0;
1173                         pm_iir = 0;
1174                 } else if (INTEL_GEN(dev_priv) >= 8) {
1175                         pm_ier = I915_READ(GEN8_GT_IER(2));
1176                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1177                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1178                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1179                 } else {
1180                         pm_ier = I915_READ(GEN6_PMIER);
1181                         pm_imr = I915_READ(GEN6_PMIMR);
1182                         pm_isr = I915_READ(GEN6_PMISR);
1183                         pm_iir = I915_READ(GEN6_PMIIR);
1184                 }
1185                 pm_mask = I915_READ(GEN6_PMINTRMSK);
1186
1187                 seq_printf(m, "Video Turbo Mode: %s\n",
1188                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1189                 seq_printf(m, "HW control enabled: %s\n",
1190                            yesno(rpmodectl & GEN6_RP_ENABLE));
1191                 seq_printf(m, "SW control enabled: %s\n",
1192                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1193                                   GEN6_RP_MEDIA_SW_MODE));
1194
1195                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
1196                            pm_ier, pm_imr, pm_mask);
1197                 if (INTEL_GEN(dev_priv) <= 10)
1198                         seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
1199                                    pm_isr, pm_iir);
1200                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1201                            rps->pm_intrmsk_mbz);
1202                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1203                 seq_printf(m, "Render p-state ratio: %d\n",
1204                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1205                 seq_printf(m, "Render p-state VID: %d\n",
1206                            gt_perf_status & 0xff);
1207                 seq_printf(m, "Render p-state limit: %d\n",
1208                            rp_state_limits & 0xff);
1209                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1210                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1211                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1212                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1213                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1214                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1215                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1216                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1217                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1218                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1219                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1220                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1221                 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1222
1223                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1224                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1225                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1226                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1227                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1228                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1229                 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1230
1231                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1232                             rp_state_cap >> 16) & 0xff;
1233                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1234                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
1235                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1236                            intel_gpu_freq(dev_priv, max_freq));
1237
1238                 max_freq = (rp_state_cap & 0xff00) >> 8;
1239                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1240                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
1241                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1242                            intel_gpu_freq(dev_priv, max_freq));
1243
1244                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1245                             rp_state_cap >> 0) & 0xff;
1246                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1247                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
1248                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1249                            intel_gpu_freq(dev_priv, max_freq));
1250                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1251                            intel_gpu_freq(dev_priv, rps->max_freq));
1252
1253                 seq_printf(m, "Current freq: %d MHz\n",
1254                            intel_gpu_freq(dev_priv, rps->cur_freq));
1255                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1256                 seq_printf(m, "Idle freq: %d MHz\n",
1257                            intel_gpu_freq(dev_priv, rps->idle_freq));
1258                 seq_printf(m, "Min freq: %d MHz\n",
1259                            intel_gpu_freq(dev_priv, rps->min_freq));
1260                 seq_printf(m, "Boost freq: %d MHz\n",
1261                            intel_gpu_freq(dev_priv, rps->boost_freq));
1262                 seq_printf(m, "Max freq: %d MHz\n",
1263                            intel_gpu_freq(dev_priv, rps->max_freq));
1264                 seq_printf(m,
1265                            "efficient (RPe) frequency: %d MHz\n",
1266                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1267         } else {
1268                 seq_puts(m, "no P-state info available\n");
1269         }
1270
1271         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1272         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1273         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1274
1275         intel_runtime_pm_put(dev_priv);
1276         return ret;
1277 }
1278
1279 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1280                                struct seq_file *m,
1281                                struct intel_instdone *instdone)
1282 {
1283         int slice;
1284         int subslice;
1285
1286         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1287                    instdone->instdone);
1288
1289         if (INTEL_GEN(dev_priv) <= 3)
1290                 return;
1291
1292         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1293                    instdone->slice_common);
1294
1295         if (INTEL_GEN(dev_priv) <= 6)
1296                 return;
1297
1298         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1299                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1300                            slice, subslice, instdone->sampler[slice][subslice]);
1301
1302         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1303                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1304                            slice, subslice, instdone->row[slice][subslice]);
1305 }
1306
1307 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1308 {
1309         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1310         struct intel_engine_cs *engine;
1311         u64 acthd[I915_NUM_ENGINES];
1312         u32 seqno[I915_NUM_ENGINES];
1313         struct intel_instdone instdone;
1314         enum intel_engine_id id;
1315
1316         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1317                 seq_puts(m, "Wedged\n");
1318         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1319                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1320         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1321                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1322         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1323                 seq_puts(m, "Waiter holding struct mutex\n");
1324         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1325                 seq_puts(m, "struct_mutex blocked for reset\n");
1326
1327         if (!i915_modparams.enable_hangcheck) {
1328                 seq_puts(m, "Hangcheck disabled\n");
1329                 return 0;
1330         }
1331
1332         intel_runtime_pm_get(dev_priv);
1333
1334         for_each_engine(engine, dev_priv, id) {
1335                 acthd[id] = intel_engine_get_active_head(engine);
1336                 seqno[id] = intel_engine_get_seqno(engine);
1337         }
1338
1339         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1340
1341         intel_runtime_pm_put(dev_priv);
1342
1343         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1344                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1345                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1346                                             jiffies));
1347         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1348                 seq_puts(m, "Hangcheck active, work pending\n");
1349         else
1350                 seq_puts(m, "Hangcheck inactive\n");
1351
1352         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1353
1354         for_each_engine(engine, dev_priv, id) {
1355                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1356                 struct rb_node *rb;
1357
1358                 seq_printf(m, "%s:\n", engine->name);
1359                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1360                            engine->hangcheck.seqno, seqno[id],
1361                            intel_engine_last_submit(engine));
1362                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s, wedged? %s\n",
1363                            yesno(intel_engine_has_waiter(engine)),
1364                            yesno(test_bit(engine->id,
1365                                           &dev_priv->gpu_error.missed_irq_rings)),
1366                            yesno(engine->hangcheck.stalled),
1367                            yesno(engine->hangcheck.wedged));
1368
1369                 spin_lock_irq(&b->rb_lock);
1370                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1371                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1372
1373                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1374                                    w->tsk->comm, w->tsk->pid, w->seqno);
1375                 }
1376                 spin_unlock_irq(&b->rb_lock);
1377
1378                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1379                            (long long)engine->hangcheck.acthd,
1380                            (long long)acthd[id]);
1381                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1382                            hangcheck_action_to_str(engine->hangcheck.action),
1383                            engine->hangcheck.action,
1384                            jiffies_to_msecs(jiffies -
1385                                             engine->hangcheck.action_timestamp));
1386
1387                 if (engine->id == RCS) {
1388                         seq_puts(m, "\tinstdone read =\n");
1389
1390                         i915_instdone_info(dev_priv, m, &instdone);
1391
1392                         seq_puts(m, "\tinstdone accu =\n");
1393
1394                         i915_instdone_info(dev_priv, m,
1395                                            &engine->hangcheck.instdone);
1396                 }
1397         }
1398
1399         return 0;
1400 }
1401
1402 static int i915_reset_info(struct seq_file *m, void *unused)
1403 {
1404         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1405         struct i915_gpu_error *error = &dev_priv->gpu_error;
1406         struct intel_engine_cs *engine;
1407         enum intel_engine_id id;
1408
1409         seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1410
1411         for_each_engine(engine, dev_priv, id) {
1412                 seq_printf(m, "%s = %u\n", engine->name,
1413                            i915_reset_engine_count(error, engine));
1414         }
1415
1416         return 0;
1417 }
1418
1419 static int ironlake_drpc_info(struct seq_file *m)
1420 {
1421         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1422         u32 rgvmodectl, rstdbyctl;
1423         u16 crstandvid;
1424
1425         rgvmodectl = I915_READ(MEMMODECTL);
1426         rstdbyctl = I915_READ(RSTDBYCTL);
1427         crstandvid = I915_READ16(CRSTANDVID);
1428
1429         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1430         seq_printf(m, "Boost freq: %d\n",
1431                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1432                    MEMMODE_BOOST_FREQ_SHIFT);
1433         seq_printf(m, "HW control enabled: %s\n",
1434                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1435         seq_printf(m, "SW control enabled: %s\n",
1436                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1437         seq_printf(m, "Gated voltage change: %s\n",
1438                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1439         seq_printf(m, "Starting frequency: P%d\n",
1440                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1441         seq_printf(m, "Max P-state: P%d\n",
1442                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1443         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1444         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1445         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1446         seq_printf(m, "Render standby enabled: %s\n",
1447                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1448         seq_puts(m, "Current RS state: ");
1449         switch (rstdbyctl & RSX_STATUS_MASK) {
1450         case RSX_STATUS_ON:
1451                 seq_puts(m, "on\n");
1452                 break;
1453         case RSX_STATUS_RC1:
1454                 seq_puts(m, "RC1\n");
1455                 break;
1456         case RSX_STATUS_RC1E:
1457                 seq_puts(m, "RC1E\n");
1458                 break;
1459         case RSX_STATUS_RS1:
1460                 seq_puts(m, "RS1\n");
1461                 break;
1462         case RSX_STATUS_RS2:
1463                 seq_puts(m, "RS2 (RC6)\n");
1464                 break;
1465         case RSX_STATUS_RS3:
1466                 seq_puts(m, "RC3 (RC6+)\n");
1467                 break;
1468         default:
1469                 seq_puts(m, "unknown\n");
1470                 break;
1471         }
1472
1473         return 0;
1474 }
1475
1476 static int i915_forcewake_domains(struct seq_file *m, void *data)
1477 {
1478         struct drm_i915_private *i915 = node_to_i915(m->private);
1479         struct intel_uncore_forcewake_domain *fw_domain;
1480         unsigned int tmp;
1481
1482         seq_printf(m, "user.bypass_count = %u\n",
1483                    i915->uncore.user_forcewake.count);
1484
1485         for_each_fw_domain(fw_domain, i915, tmp)
1486                 seq_printf(m, "%s.wake_count = %u\n",
1487                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1488                            READ_ONCE(fw_domain->wake_count));
1489
1490         return 0;
1491 }
1492
1493 static void print_rc6_res(struct seq_file *m,
1494                           const char *title,
1495                           const i915_reg_t reg)
1496 {
1497         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1498
1499         seq_printf(m, "%s %u (%llu us)\n",
1500                    title, I915_READ(reg),
1501                    intel_rc6_residency_us(dev_priv, reg));
1502 }
1503
1504 static int vlv_drpc_info(struct seq_file *m)
1505 {
1506         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1507         u32 rcctl1, pw_status;
1508
1509         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1510         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1511
1512         seq_printf(m, "RC6 Enabled: %s\n",
1513                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1514                                         GEN6_RC_CTL_EI_MODE(1))));
1515         seq_printf(m, "Render Power Well: %s\n",
1516                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1517         seq_printf(m, "Media Power Well: %s\n",
1518                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1519
1520         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1521         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1522
1523         return i915_forcewake_domains(m, NULL);
1524 }
1525
1526 static int gen6_drpc_info(struct seq_file *m)
1527 {
1528         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1529         u32 gt_core_status, rcctl1, rc6vids = 0;
1530         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1531
1532         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1533         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1534
1535         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1536         if (INTEL_GEN(dev_priv) >= 9) {
1537                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1538                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1539         }
1540
1541         if (INTEL_GEN(dev_priv) <= 7) {
1542                 mutex_lock(&dev_priv->pcu_lock);
1543                 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
1544                                        &rc6vids);
1545                 mutex_unlock(&dev_priv->pcu_lock);
1546         }
1547
1548         seq_printf(m, "RC1e Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1550         seq_printf(m, "RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1552         if (INTEL_GEN(dev_priv) >= 9) {
1553                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1554                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1555                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1556                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1557         }
1558         seq_printf(m, "Deep RC6 Enabled: %s\n",
1559                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1560         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1561                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1562         seq_puts(m, "Current RC state: ");
1563         switch (gt_core_status & GEN6_RCn_MASK) {
1564         case GEN6_RC0:
1565                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1566                         seq_puts(m, "Core Power Down\n");
1567                 else
1568                         seq_puts(m, "on\n");
1569                 break;
1570         case GEN6_RC3:
1571                 seq_puts(m, "RC3\n");
1572                 break;
1573         case GEN6_RC6:
1574                 seq_puts(m, "RC6\n");
1575                 break;
1576         case GEN6_RC7:
1577                 seq_puts(m, "RC7\n");
1578                 break;
1579         default:
1580                 seq_puts(m, "Unknown\n");
1581                 break;
1582         }
1583
1584         seq_printf(m, "Core Power Down: %s\n",
1585                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1586         if (INTEL_GEN(dev_priv) >= 9) {
1587                 seq_printf(m, "Render Power Well: %s\n",
1588                         (gen9_powergate_status &
1589                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1590                 seq_printf(m, "Media Power Well: %s\n",
1591                         (gen9_powergate_status &
1592                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1593         }
1594
1595         /* Not exactly sure what this is */
1596         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1597                       GEN6_GT_GFX_RC6_LOCKED);
1598         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1599         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1600         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1601
1602         if (INTEL_GEN(dev_priv) <= 7) {
1603                 seq_printf(m, "RC6   voltage: %dmV\n",
1604                            GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1605                 seq_printf(m, "RC6+  voltage: %dmV\n",
1606                            GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1607                 seq_printf(m, "RC6++ voltage: %dmV\n",
1608                            GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1609         }
1610
1611         return i915_forcewake_domains(m, NULL);
1612 }
1613
1614 static int i915_drpc_info(struct seq_file *m, void *unused)
1615 {
1616         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1617         int err;
1618
1619         intel_runtime_pm_get(dev_priv);
1620
1621         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1622                 err = vlv_drpc_info(m);
1623         else if (INTEL_GEN(dev_priv) >= 6)
1624                 err = gen6_drpc_info(m);
1625         else
1626                 err = ironlake_drpc_info(m);
1627
1628         intel_runtime_pm_put(dev_priv);
1629
1630         return err;
1631 }
1632
1633 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1634 {
1635         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1636
1637         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1638                    dev_priv->fb_tracking.busy_bits);
1639
1640         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1641                    dev_priv->fb_tracking.flip_bits);
1642
1643         return 0;
1644 }
1645
1646 static int i915_fbc_status(struct seq_file *m, void *unused)
1647 {
1648         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1649         struct intel_fbc *fbc = &dev_priv->fbc;
1650
1651         if (!HAS_FBC(dev_priv))
1652                 return -ENODEV;
1653
1654         intel_runtime_pm_get(dev_priv);
1655         mutex_lock(&fbc->lock);
1656
1657         if (intel_fbc_is_active(dev_priv))
1658                 seq_puts(m, "FBC enabled\n");
1659         else
1660                 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1661
1662         if (intel_fbc_is_active(dev_priv)) {
1663                 u32 mask;
1664
1665                 if (INTEL_GEN(dev_priv) >= 8)
1666                         mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1667                 else if (INTEL_GEN(dev_priv) >= 7)
1668                         mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1669                 else if (INTEL_GEN(dev_priv) >= 5)
1670                         mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1671                 else if (IS_G4X(dev_priv))
1672                         mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1673                 else
1674                         mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1675                                                         FBC_STAT_COMPRESSED);
1676
1677                 seq_printf(m, "Compressing: %s\n", yesno(mask));
1678         }
1679
1680         mutex_unlock(&fbc->lock);
1681         intel_runtime_pm_put(dev_priv);
1682
1683         return 0;
1684 }
1685
1686 static int i915_fbc_false_color_get(void *data, u64 *val)
1687 {
1688         struct drm_i915_private *dev_priv = data;
1689
1690         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1691                 return -ENODEV;
1692
1693         *val = dev_priv->fbc.false_color;
1694
1695         return 0;
1696 }
1697
1698 static int i915_fbc_false_color_set(void *data, u64 val)
1699 {
1700         struct drm_i915_private *dev_priv = data;
1701         u32 reg;
1702
1703         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1704                 return -ENODEV;
1705
1706         mutex_lock(&dev_priv->fbc.lock);
1707
1708         reg = I915_READ(ILK_DPFC_CONTROL);
1709         dev_priv->fbc.false_color = val;
1710
1711         I915_WRITE(ILK_DPFC_CONTROL, val ?
1712                    (reg | FBC_CTL_FALSE_COLOR) :
1713                    (reg & ~FBC_CTL_FALSE_COLOR));
1714
1715         mutex_unlock(&dev_priv->fbc.lock);
1716         return 0;
1717 }
1718
1719 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1720                         i915_fbc_false_color_get, i915_fbc_false_color_set,
1721                         "%llu\n");
1722
1723 static int i915_ips_status(struct seq_file *m, void *unused)
1724 {
1725         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1726
1727         if (!HAS_IPS(dev_priv))
1728                 return -ENODEV;
1729
1730         intel_runtime_pm_get(dev_priv);
1731
1732         seq_printf(m, "Enabled by kernel parameter: %s\n",
1733                    yesno(i915_modparams.enable_ips));
1734
1735         if (INTEL_GEN(dev_priv) >= 8) {
1736                 seq_puts(m, "Currently: unknown\n");
1737         } else {
1738                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1739                         seq_puts(m, "Currently: enabled\n");
1740                 else
1741                         seq_puts(m, "Currently: disabled\n");
1742         }
1743
1744         intel_runtime_pm_put(dev_priv);
1745
1746         return 0;
1747 }
1748
1749 static int i915_sr_status(struct seq_file *m, void *unused)
1750 {
1751         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1752         bool sr_enabled = false;
1753
1754         intel_runtime_pm_get(dev_priv);
1755         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1756
1757         if (INTEL_GEN(dev_priv) >= 9)
1758                 /* no global SR status; inspect per-plane WM */;
1759         else if (HAS_PCH_SPLIT(dev_priv))
1760                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1761         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1762                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1763                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1764         else if (IS_I915GM(dev_priv))
1765                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1766         else if (IS_PINEVIEW(dev_priv))
1767                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1768         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1769                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1770
1771         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1772         intel_runtime_pm_put(dev_priv);
1773
1774         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1775
1776         return 0;
1777 }
1778
1779 static int i915_emon_status(struct seq_file *m, void *unused)
1780 {
1781         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1782         struct drm_device *dev = &dev_priv->drm;
1783         unsigned long temp, chipset, gfx;
1784         int ret;
1785
1786         if (!IS_GEN5(dev_priv))
1787                 return -ENODEV;
1788
1789         ret = mutex_lock_interruptible(&dev->struct_mutex);
1790         if (ret)
1791                 return ret;
1792
1793         temp = i915_mch_val(dev_priv);
1794         chipset = i915_chipset_val(dev_priv);
1795         gfx = i915_gfx_val(dev_priv);
1796         mutex_unlock(&dev->struct_mutex);
1797
1798         seq_printf(m, "GMCH temp: %ld\n", temp);
1799         seq_printf(m, "Chipset power: %ld\n", chipset);
1800         seq_printf(m, "GFX power: %ld\n", gfx);
1801         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1802
1803         return 0;
1804 }
1805
1806 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1807 {
1808         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1809         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1810         unsigned int max_gpu_freq, min_gpu_freq;
1811         int gpu_freq, ia_freq;
1812         int ret;
1813
1814         if (!HAS_LLC(dev_priv))
1815                 return -ENODEV;
1816
1817         intel_runtime_pm_get(dev_priv);
1818
1819         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1820         if (ret)
1821                 goto out;
1822
1823         min_gpu_freq = rps->min_freq;
1824         max_gpu_freq = rps->max_freq;
1825         if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
1826                 /* Convert GT frequency to 50 HZ units */
1827                 min_gpu_freq /= GEN9_FREQ_SCALER;
1828                 max_gpu_freq /= GEN9_FREQ_SCALER;
1829         }
1830
1831         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1832
1833         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1834                 ia_freq = gpu_freq;
1835                 sandybridge_pcode_read(dev_priv,
1836                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1837                                        &ia_freq);
1838                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1839                            intel_gpu_freq(dev_priv, (gpu_freq *
1840                                                      (IS_GEN9_BC(dev_priv) ||
1841                                                       INTEL_GEN(dev_priv) >= 10 ?
1842                                                       GEN9_FREQ_SCALER : 1))),
1843                            ((ia_freq >> 0) & 0xff) * 100,
1844                            ((ia_freq >> 8) & 0xff) * 100);
1845         }
1846
1847         mutex_unlock(&dev_priv->pcu_lock);
1848
1849 out:
1850         intel_runtime_pm_put(dev_priv);
1851         return ret;
1852 }
1853
1854 static int i915_opregion(struct seq_file *m, void *unused)
1855 {
1856         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1857         struct drm_device *dev = &dev_priv->drm;
1858         struct intel_opregion *opregion = &dev_priv->opregion;
1859         int ret;
1860
1861         ret = mutex_lock_interruptible(&dev->struct_mutex);
1862         if (ret)
1863                 goto out;
1864
1865         if (opregion->header)
1866                 seq_write(m, opregion->header, OPREGION_SIZE);
1867
1868         mutex_unlock(&dev->struct_mutex);
1869
1870 out:
1871         return 0;
1872 }
1873
1874 static int i915_vbt(struct seq_file *m, void *unused)
1875 {
1876         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1877
1878         if (opregion->vbt)
1879                 seq_write(m, opregion->vbt, opregion->vbt_size);
1880
1881         return 0;
1882 }
1883
1884 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1885 {
1886         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1887         struct drm_device *dev = &dev_priv->drm;
1888         struct intel_framebuffer *fbdev_fb = NULL;
1889         struct drm_framebuffer *drm_fb;
1890         int ret;
1891
1892         ret = mutex_lock_interruptible(&dev->struct_mutex);
1893         if (ret)
1894                 return ret;
1895
1896 #ifdef CONFIG_DRM_FBDEV_EMULATION
1897         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1898                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1899
1900                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901                            fbdev_fb->base.width,
1902                            fbdev_fb->base.height,
1903                            fbdev_fb->base.format->depth,
1904                            fbdev_fb->base.format->cpp[0] * 8,
1905                            fbdev_fb->base.modifier,
1906                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1907                 describe_obj(m, intel_fb_obj(&fbdev_fb->base));
1908                 seq_putc(m, '\n');
1909         }
1910 #endif
1911
1912         mutex_lock(&dev->mode_config.fb_lock);
1913         drm_for_each_fb(drm_fb, dev) {
1914                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1915                 if (fb == fbdev_fb)
1916                         continue;
1917
1918                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1919                            fb->base.width,
1920                            fb->base.height,
1921                            fb->base.format->depth,
1922                            fb->base.format->cpp[0] * 8,
1923                            fb->base.modifier,
1924                            drm_framebuffer_read_refcount(&fb->base));
1925                 describe_obj(m, intel_fb_obj(&fb->base));
1926                 seq_putc(m, '\n');
1927         }
1928         mutex_unlock(&dev->mode_config.fb_lock);
1929         mutex_unlock(&dev->struct_mutex);
1930
1931         return 0;
1932 }
1933
1934 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1935 {
1936         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
1937                    ring->space, ring->head, ring->tail, ring->emit);
1938 }
1939
1940 static int i915_context_status(struct seq_file *m, void *unused)
1941 {
1942         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1943         struct drm_device *dev = &dev_priv->drm;
1944         struct intel_engine_cs *engine;
1945         struct i915_gem_context *ctx;
1946         enum intel_engine_id id;
1947         int ret;
1948
1949         ret = mutex_lock_interruptible(&dev->struct_mutex);
1950         if (ret)
1951                 return ret;
1952
1953         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1954                 seq_printf(m, "HW context %u ", ctx->hw_id);
1955                 if (ctx->pid) {
1956                         struct task_struct *task;
1957
1958                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1959                         if (task) {
1960                                 seq_printf(m, "(%s [%d]) ",
1961                                            task->comm, task->pid);
1962                                 put_task_struct(task);
1963                         }
1964                 } else if (IS_ERR(ctx->file_priv)) {
1965                         seq_puts(m, "(deleted) ");
1966                 } else {
1967                         seq_puts(m, "(kernel) ");
1968                 }
1969
1970                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1971                 seq_putc(m, '\n');
1972
1973                 for_each_engine(engine, dev_priv, id) {
1974                         struct intel_context *ce =
1975                                 to_intel_context(ctx, engine);
1976
1977                         seq_printf(m, "%s: ", engine->name);
1978                         if (ce->state)
1979                                 describe_obj(m, ce->state->obj);
1980                         if (ce->ring)
1981                                 describe_ctx_ring(m, ce->ring);
1982                         seq_putc(m, '\n');
1983                 }
1984
1985                 seq_putc(m, '\n');
1986         }
1987
1988         mutex_unlock(&dev->struct_mutex);
1989
1990         return 0;
1991 }
1992
1993 static const char *swizzle_string(unsigned swizzle)
1994 {
1995         switch (swizzle) {
1996         case I915_BIT_6_SWIZZLE_NONE:
1997                 return "none";
1998         case I915_BIT_6_SWIZZLE_9:
1999                 return "bit9";
2000         case I915_BIT_6_SWIZZLE_9_10:
2001                 return "bit9/bit10";
2002         case I915_BIT_6_SWIZZLE_9_11:
2003                 return "bit9/bit11";
2004         case I915_BIT_6_SWIZZLE_9_10_11:
2005                 return "bit9/bit10/bit11";
2006         case I915_BIT_6_SWIZZLE_9_17:
2007                 return "bit9/bit17";
2008         case I915_BIT_6_SWIZZLE_9_10_17:
2009                 return "bit9/bit10/bit17";
2010         case I915_BIT_6_SWIZZLE_UNKNOWN:
2011                 return "unknown";
2012         }
2013
2014         return "bug";
2015 }
2016
2017 static int i915_swizzle_info(struct seq_file *m, void *data)
2018 {
2019         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2020
2021         intel_runtime_pm_get(dev_priv);
2022
2023         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2024                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2025         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2026                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2027
2028         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2029                 seq_printf(m, "DDC = 0x%08x\n",
2030                            I915_READ(DCC));
2031                 seq_printf(m, "DDC2 = 0x%08x\n",
2032                            I915_READ(DCC2));
2033                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2034                            I915_READ16(C0DRB3));
2035                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2036                            I915_READ16(C1DRB3));
2037         } else if (INTEL_GEN(dev_priv) >= 6) {
2038                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2039                            I915_READ(MAD_DIMM_C0));
2040                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2041                            I915_READ(MAD_DIMM_C1));
2042                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2043                            I915_READ(MAD_DIMM_C2));
2044                 seq_printf(m, "TILECTL = 0x%08x\n",
2045                            I915_READ(TILECTL));
2046                 if (INTEL_GEN(dev_priv) >= 8)
2047                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2048                                    I915_READ(GAMTARBMODE));
2049                 else
2050                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2051                                    I915_READ(ARB_MODE));
2052                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2053                            I915_READ(DISP_ARB_CTL));
2054         }
2055
2056         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2057                 seq_puts(m, "L-shaped memory detected\n");
2058
2059         intel_runtime_pm_put(dev_priv);
2060
2061         return 0;
2062 }
2063
2064 static int per_file_ctx(int id, void *ptr, void *data)
2065 {
2066         struct i915_gem_context *ctx = ptr;
2067         struct seq_file *m = data;
2068         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2069
2070         if (!ppgtt) {
2071                 seq_printf(m, "  no ppgtt for context %d\n",
2072                            ctx->user_handle);
2073                 return 0;
2074         }
2075
2076         if (i915_gem_context_is_default(ctx))
2077                 seq_puts(m, "  default context:\n");
2078         else
2079                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2080         ppgtt->debug_dump(ppgtt, m);
2081
2082         return 0;
2083 }
2084
2085 static void gen8_ppgtt_info(struct seq_file *m,
2086                             struct drm_i915_private *dev_priv)
2087 {
2088         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2089         struct intel_engine_cs *engine;
2090         enum intel_engine_id id;
2091         int i;
2092
2093         if (!ppgtt)
2094                 return;
2095
2096         for_each_engine(engine, dev_priv, id) {
2097                 seq_printf(m, "%s\n", engine->name);
2098                 for (i = 0; i < 4; i++) {
2099                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2100                         pdp <<= 32;
2101                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2102                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2103                 }
2104         }
2105 }
2106
2107 static void gen6_ppgtt_info(struct seq_file *m,
2108                             struct drm_i915_private *dev_priv)
2109 {
2110         struct intel_engine_cs *engine;
2111         enum intel_engine_id id;
2112
2113         if (IS_GEN6(dev_priv))
2114                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2115
2116         for_each_engine(engine, dev_priv, id) {
2117                 seq_printf(m, "%s\n", engine->name);
2118                 if (IS_GEN7(dev_priv))
2119                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2120                                    I915_READ(RING_MODE_GEN7(engine)));
2121                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2122                            I915_READ(RING_PP_DIR_BASE(engine)));
2123                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2124                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2125                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2126                            I915_READ(RING_PP_DIR_DCLV(engine)));
2127         }
2128         if (dev_priv->mm.aliasing_ppgtt) {
2129                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2130
2131                 seq_puts(m, "aliasing PPGTT:\n");
2132                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2133
2134                 ppgtt->debug_dump(ppgtt, m);
2135         }
2136
2137         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2138 }
2139
2140 static int i915_ppgtt_info(struct seq_file *m, void *data)
2141 {
2142         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2143         struct drm_device *dev = &dev_priv->drm;
2144         struct drm_file *file;
2145         int ret;
2146
2147         mutex_lock(&dev->filelist_mutex);
2148         ret = mutex_lock_interruptible(&dev->struct_mutex);
2149         if (ret)
2150                 goto out_unlock;
2151
2152         intel_runtime_pm_get(dev_priv);
2153
2154         if (INTEL_GEN(dev_priv) >= 8)
2155                 gen8_ppgtt_info(m, dev_priv);
2156         else if (INTEL_GEN(dev_priv) >= 6)
2157                 gen6_ppgtt_info(m, dev_priv);
2158
2159         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2160                 struct drm_i915_file_private *file_priv = file->driver_priv;
2161                 struct task_struct *task;
2162
2163                 task = get_pid_task(file->pid, PIDTYPE_PID);
2164                 if (!task) {
2165                         ret = -ESRCH;
2166                         goto out_rpm;
2167                 }
2168                 seq_printf(m, "\nproc: %s\n", task->comm);
2169                 put_task_struct(task);
2170                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2171                              (void *)(unsigned long)m);
2172         }
2173
2174 out_rpm:
2175         intel_runtime_pm_put(dev_priv);
2176         mutex_unlock(&dev->struct_mutex);
2177 out_unlock:
2178         mutex_unlock(&dev->filelist_mutex);
2179         return ret;
2180 }
2181
2182 static int count_irq_waiters(struct drm_i915_private *i915)
2183 {
2184         struct intel_engine_cs *engine;
2185         enum intel_engine_id id;
2186         int count = 0;
2187
2188         for_each_engine(engine, i915, id)
2189                 count += intel_engine_has_waiter(engine);
2190
2191         return count;
2192 }
2193
2194 static const char *rps_power_to_str(unsigned int power)
2195 {
2196         static const char * const strings[] = {
2197                 [LOW_POWER] = "low power",
2198                 [BETWEEN] = "mixed",
2199                 [HIGH_POWER] = "high power",
2200         };
2201
2202         if (power >= ARRAY_SIZE(strings) || !strings[power])
2203                 return "unknown";
2204
2205         return strings[power];
2206 }
2207
2208 static int i915_rps_boost_info(struct seq_file *m, void *data)
2209 {
2210         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2211         struct drm_device *dev = &dev_priv->drm;
2212         struct intel_rps *rps = &dev_priv->gt_pm.rps;
2213         struct drm_file *file;
2214
2215         seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2216         seq_printf(m, "GPU busy? %s [%d requests]\n",
2217                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2218         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2219         seq_printf(m, "Boosts outstanding? %d\n",
2220                    atomic_read(&rps->num_waiters));
2221         seq_printf(m, "Frequency requested %d\n",
2222                    intel_gpu_freq(dev_priv, rps->cur_freq));
2223         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2224                    intel_gpu_freq(dev_priv, rps->min_freq),
2225                    intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2226                    intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2227                    intel_gpu_freq(dev_priv, rps->max_freq));
2228         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2229                    intel_gpu_freq(dev_priv, rps->idle_freq),
2230                    intel_gpu_freq(dev_priv, rps->efficient_freq),
2231                    intel_gpu_freq(dev_priv, rps->boost_freq));
2232
2233         mutex_lock(&dev->filelist_mutex);
2234         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2235                 struct drm_i915_file_private *file_priv = file->driver_priv;
2236                 struct task_struct *task;
2237
2238                 rcu_read_lock();
2239                 task = pid_task(file->pid, PIDTYPE_PID);
2240                 seq_printf(m, "%s [%d]: %d boosts\n",
2241                            task ? task->comm : "<unknown>",
2242                            task ? task->pid : -1,
2243                            atomic_read(&file_priv->rps_client.boosts));
2244                 rcu_read_unlock();
2245         }
2246         seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2247                    atomic_read(&rps->boosts));
2248         mutex_unlock(&dev->filelist_mutex);
2249
2250         if (INTEL_GEN(dev_priv) >= 6 &&
2251             rps->enabled &&
2252             dev_priv->gt.active_requests) {
2253                 u32 rpup, rpupei;
2254                 u32 rpdown, rpdownei;
2255
2256                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2257                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2258                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2259                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2260                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2261                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2262
2263                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2264                            rps_power_to_str(rps->power));
2265                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2266                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2267                            rps->up_threshold);
2268                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2269                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2270                            rps->down_threshold);
2271         } else {
2272                 seq_puts(m, "\nRPS Autotuning inactive\n");
2273         }
2274
2275         return 0;
2276 }
2277
2278 static int i915_llc(struct seq_file *m, void *data)
2279 {
2280         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2281         const bool edram = INTEL_GEN(dev_priv) > 8;
2282
2283         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2284         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2285                    intel_uncore_edram_size(dev_priv)/1024/1024);
2286
2287         return 0;
2288 }
2289
2290 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2291 {
2292         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2293         struct drm_printer p;
2294
2295         if (!HAS_HUC(dev_priv))
2296                 return -ENODEV;
2297
2298         p = drm_seq_file_printer(m);
2299         intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2300
2301         intel_runtime_pm_get(dev_priv);
2302         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2303         intel_runtime_pm_put(dev_priv);
2304
2305         return 0;
2306 }
2307
2308 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2309 {
2310         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2311         struct drm_printer p;
2312         u32 tmp, i;
2313
2314         if (!HAS_GUC(dev_priv))
2315                 return -ENODEV;
2316
2317         p = drm_seq_file_printer(m);
2318         intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2319
2320         intel_runtime_pm_get(dev_priv);
2321
2322         tmp = I915_READ(GUC_STATUS);
2323
2324         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2325         seq_printf(m, "\tBootrom status = 0x%x\n",
2326                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2327         seq_printf(m, "\tuKernel status = 0x%x\n",
2328                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2329         seq_printf(m, "\tMIA Core status = 0x%x\n",
2330                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2331         seq_puts(m, "\nScratch registers:\n");
2332         for (i = 0; i < 16; i++)
2333                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2334
2335         intel_runtime_pm_put(dev_priv);
2336
2337         return 0;
2338 }
2339
2340 static const char *
2341 stringify_guc_log_type(enum guc_log_buffer_type type)
2342 {
2343         switch (type) {
2344         case GUC_ISR_LOG_BUFFER:
2345                 return "ISR";
2346         case GUC_DPC_LOG_BUFFER:
2347                 return "DPC";
2348         case GUC_CRASH_DUMP_LOG_BUFFER:
2349                 return "CRASH";
2350         default:
2351                 MISSING_CASE(type);
2352         }
2353
2354         return "";
2355 }
2356
2357 static void i915_guc_log_info(struct seq_file *m,
2358                               struct drm_i915_private *dev_priv)
2359 {
2360         struct intel_guc_log *log = &dev_priv->guc.log;
2361         enum guc_log_buffer_type type;
2362
2363         if (!intel_guc_log_relay_enabled(log)) {
2364                 seq_puts(m, "GuC log relay disabled\n");
2365                 return;
2366         }
2367
2368         seq_puts(m, "GuC logging stats:\n");
2369
2370         seq_printf(m, "\tRelay full count: %u\n",
2371                    log->relay.full_count);
2372
2373         for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
2374                 seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
2375                            stringify_guc_log_type(type),
2376                            log->stats[type].flush,
2377                            log->stats[type].sampled_overflow);
2378         }
2379 }
2380
2381 static void i915_guc_client_info(struct seq_file *m,
2382                                  struct drm_i915_private *dev_priv,
2383                                  struct intel_guc_client *client)
2384 {
2385         struct intel_engine_cs *engine;
2386         enum intel_engine_id id;
2387         uint64_t tot = 0;
2388
2389         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2390                 client->priority, client->stage_id, client->proc_desc_offset);
2391         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2392                 client->doorbell_id, client->doorbell_offset);
2393
2394         for_each_engine(engine, dev_priv, id) {
2395                 u64 submissions = client->submissions[id];
2396                 tot += submissions;
2397                 seq_printf(m, "\tSubmissions: %llu %s\n",
2398                                 submissions, engine->name);
2399         }
2400         seq_printf(m, "\tTotal: %llu\n", tot);
2401 }
2402
2403 static int i915_guc_info(struct seq_file *m, void *data)
2404 {
2405         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2406         const struct intel_guc *guc = &dev_priv->guc;
2407
2408         if (!USES_GUC(dev_priv))
2409                 return -ENODEV;
2410
2411         i915_guc_log_info(m, dev_priv);
2412
2413         if (!USES_GUC_SUBMISSION(dev_priv))
2414                 return 0;
2415
2416         GEM_BUG_ON(!guc->execbuf_client);
2417
2418         seq_printf(m, "\nDoorbell map:\n");
2419         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2420         seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline);
2421
2422         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2423         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2424         if (guc->preempt_client) {
2425                 seq_printf(m, "\nGuC preempt client @ %p:\n",
2426                            guc->preempt_client);
2427                 i915_guc_client_info(m, dev_priv, guc->preempt_client);
2428         }
2429
2430         /* Add more as required ... */
2431
2432         return 0;
2433 }
2434
2435 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2436 {
2437         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2438         const struct intel_guc *guc = &dev_priv->guc;
2439         struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2440         struct intel_guc_client *client = guc->execbuf_client;
2441         unsigned int tmp;
2442         int index;
2443
2444         if (!USES_GUC_SUBMISSION(dev_priv))
2445                 return -ENODEV;
2446
2447         for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2448                 struct intel_engine_cs *engine;
2449
2450                 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2451                         continue;
2452
2453                 seq_printf(m, "GuC stage descriptor %u:\n", index);
2454                 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2455                 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2456                 seq_printf(m, "\tPriority: %d\n", desc->priority);
2457                 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2458                 seq_printf(m, "\tEngines used: 0x%x\n",
2459                            desc->engines_used);
2460                 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2461                            desc->db_trigger_phy,
2462                            desc->db_trigger_cpu,
2463                            desc->db_trigger_uk);
2464                 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2465                            desc->process_desc);
2466                 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2467                            desc->wq_addr, desc->wq_size);
2468                 seq_putc(m, '\n');
2469
2470                 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2471                         u32 guc_engine_id = engine->guc_id;
2472                         struct guc_execlist_context *lrc =
2473                                                 &desc->lrc[guc_engine_id];
2474
2475                         seq_printf(m, "\t%s LRC:\n", engine->name);
2476                         seq_printf(m, "\t\tContext desc: 0x%x\n",
2477                                    lrc->context_desc);
2478                         seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2479                         seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2480                         seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2481                         seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2482                         seq_putc(m, '\n');
2483                 }
2484         }
2485
2486         return 0;
2487 }
2488
2489 static int i915_guc_log_dump(struct seq_file *m, void *data)
2490 {
2491         struct drm_info_node *node = m->private;
2492         struct drm_i915_private *dev_priv = node_to_i915(node);
2493         bool dump_load_err = !!node->info_ent->data;
2494         struct drm_i915_gem_object *obj = NULL;
2495         u32 *log;
2496         int i = 0;
2497
2498         if (!HAS_GUC(dev_priv))
2499                 return -ENODEV;
2500
2501         if (dump_load_err)
2502                 obj = dev_priv->guc.load_err_log;
2503         else if (dev_priv->guc.log.vma)
2504                 obj = dev_priv->guc.log.vma->obj;
2505
2506         if (!obj)
2507                 return 0;
2508
2509         log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2510         if (IS_ERR(log)) {
2511                 DRM_DEBUG("Failed to pin object\n");
2512                 seq_puts(m, "(log data unaccessible)\n");
2513                 return PTR_ERR(log);
2514         }
2515
2516         for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2517                 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2518                            *(log + i), *(log + i + 1),
2519                            *(log + i + 2), *(log + i + 3));
2520
2521         seq_putc(m, '\n');
2522
2523         i915_gem_object_unpin_map(obj);
2524
2525         return 0;
2526 }
2527
2528 static int i915_guc_log_level_get(void *data, u64 *val)
2529 {
2530         struct drm_i915_private *dev_priv = data;
2531
2532         if (!USES_GUC(dev_priv))
2533                 return -ENODEV;
2534
2535         *val = intel_guc_log_get_level(&dev_priv->guc.log);
2536
2537         return 0;
2538 }
2539
2540 static int i915_guc_log_level_set(void *data, u64 val)
2541 {
2542         struct drm_i915_private *dev_priv = data;
2543
2544         if (!USES_GUC(dev_priv))
2545                 return -ENODEV;
2546
2547         return intel_guc_log_set_level(&dev_priv->guc.log, val);
2548 }
2549
2550 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
2551                         i915_guc_log_level_get, i915_guc_log_level_set,
2552                         "%lld\n");
2553
2554 static int i915_guc_log_relay_open(struct inode *inode, struct file *file)
2555 {
2556         struct drm_i915_private *dev_priv = inode->i_private;
2557
2558         if (!USES_GUC(dev_priv))
2559                 return -ENODEV;
2560
2561         file->private_data = &dev_priv->guc.log;
2562
2563         return intel_guc_log_relay_open(&dev_priv->guc.log);
2564 }
2565
2566 static ssize_t
2567 i915_guc_log_relay_write(struct file *filp,
2568                          const char __user *ubuf,
2569                          size_t cnt,
2570                          loff_t *ppos)
2571 {
2572         struct intel_guc_log *log = filp->private_data;
2573
2574         intel_guc_log_relay_flush(log);
2575
2576         return cnt;
2577 }
2578
2579 static int i915_guc_log_relay_release(struct inode *inode, struct file *file)
2580 {
2581         struct drm_i915_private *dev_priv = inode->i_private;
2582
2583         intel_guc_log_relay_close(&dev_priv->guc.log);
2584
2585         return 0;
2586 }
2587
2588 static const struct file_operations i915_guc_log_relay_fops = {
2589         .owner = THIS_MODULE,
2590         .open = i915_guc_log_relay_open,
2591         .write = i915_guc_log_relay_write,
2592         .release = i915_guc_log_relay_release,
2593 };
2594
2595 static int i915_psr_sink_status_show(struct seq_file *m, void *data)
2596 {
2597         u8 val;
2598         static const char * const sink_status[] = {
2599                 "inactive",
2600                 "transition to active, capture and display",
2601                 "active, display from RFB",
2602                 "active, capture and display on sink device timings",
2603                 "transition to inactive, capture and display, timing re-sync",
2604                 "reserved",
2605                 "reserved",
2606                 "sink internal error",
2607         };
2608         struct drm_connector *connector = m->private;
2609         struct intel_dp *intel_dp =
2610                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
2611
2612         if (connector->status != connector_status_connected)
2613                 return -ENODEV;
2614
2615         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) == 1) {
2616                 const char *str = "unknown";
2617
2618                 val &= DP_PSR_SINK_STATE_MASK;
2619                 if (val < ARRAY_SIZE(sink_status))
2620                         str = sink_status[val];
2621                 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
2622         } else {
2623                 DRM_ERROR("dpcd read (at %u) failed\n", DP_PSR_STATUS);
2624         }
2625
2626         return 0;
2627 }
2628 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
2629
2630 static void
2631 psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
2632 {
2633         u32 val, psr_status;
2634
2635         if (dev_priv->psr.psr2_enabled) {
2636                 static const char * const live_status[] = {
2637                         "IDLE",
2638                         "CAPTURE",
2639                         "CAPTURE_FS",
2640                         "SLEEP",
2641                         "BUFON_FW",
2642                         "ML_UP",
2643                         "SU_STANDBY",
2644                         "FAST_SLEEP",
2645                         "DEEP_SLEEP",
2646                         "BUF_ON",
2647                         "TG_ON"
2648                 };
2649                 psr_status = I915_READ(EDP_PSR2_STATUS);
2650                 val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
2651                         EDP_PSR2_STATUS_STATE_SHIFT;
2652                 if (val < ARRAY_SIZE(live_status)) {
2653                         seq_printf(m, "Source PSR status: 0x%x [%s]\n",
2654                                    psr_status, live_status[val]);
2655                         return;
2656                 }
2657         } else {
2658                 static const char * const live_status[] = {
2659                         "IDLE",
2660                         "SRDONACK",
2661                         "SRDENT",
2662                         "BUFOFF",
2663                         "BUFON",
2664                         "AUXACK",
2665                         "SRDOFFACK",
2666                         "SRDENT_ON",
2667                 };
2668                 psr_status = I915_READ(EDP_PSR_STATUS);
2669                 val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
2670                         EDP_PSR_STATUS_STATE_SHIFT;
2671                 if (val < ARRAY_SIZE(live_status)) {
2672                         seq_printf(m, "Source PSR status: 0x%x [%s]\n",
2673                                    psr_status, live_status[val]);
2674                         return;
2675                 }
2676         }
2677
2678         seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown");
2679 }
2680
2681 static int i915_edp_psr_status(struct seq_file *m, void *data)
2682 {
2683         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2684         u32 psrperf = 0;
2685         bool enabled = false;
2686         bool sink_support;
2687
2688         if (!HAS_PSR(dev_priv))
2689                 return -ENODEV;
2690
2691         sink_support = dev_priv->psr.sink_support;
2692         seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
2693         if (!sink_support)
2694                 return 0;
2695
2696         intel_runtime_pm_get(dev_priv);
2697
2698         mutex_lock(&dev_priv->psr.lock);
2699         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2700         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2701                    dev_priv->psr.busy_frontbuffer_bits);
2702
2703         if (dev_priv->psr.psr2_enabled)
2704                 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2705         else
2706                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2707
2708         seq_printf(m, "Main link in standby mode: %s\n",
2709                    yesno(dev_priv->psr.link_standby));
2710
2711         seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
2712
2713         /*
2714          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2715          */
2716         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2717                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2718                         EDP_PSR_PERF_CNT_MASK;
2719
2720                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2721         }
2722
2723         psr_source_status(dev_priv, m);
2724         mutex_unlock(&dev_priv->psr.lock);
2725
2726         if (READ_ONCE(dev_priv->psr.debug)) {
2727                 seq_printf(m, "Last attempted entry at: %lld\n",
2728                            dev_priv->psr.last_entry_attempt);
2729                 seq_printf(m, "Last exit at: %lld\n",
2730                            dev_priv->psr.last_exit);
2731         }
2732
2733         intel_runtime_pm_put(dev_priv);
2734         return 0;
2735 }
2736
2737 static int
2738 i915_edp_psr_debug_set(void *data, u64 val)
2739 {
2740         struct drm_i915_private *dev_priv = data;
2741
2742         if (!CAN_PSR(dev_priv))
2743                 return -ENODEV;
2744
2745         DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
2746
2747         intel_runtime_pm_get(dev_priv);
2748         intel_psr_irq_control(dev_priv, !!val);
2749         intel_runtime_pm_put(dev_priv);
2750
2751         return 0;
2752 }
2753
2754 static int
2755 i915_edp_psr_debug_get(void *data, u64 *val)
2756 {
2757         struct drm_i915_private *dev_priv = data;
2758
2759         if (!CAN_PSR(dev_priv))
2760                 return -ENODEV;
2761
2762         *val = READ_ONCE(dev_priv->psr.debug);
2763         return 0;
2764 }
2765
2766 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
2767                         i915_edp_psr_debug_get, i915_edp_psr_debug_set,
2768                         "%llu\n");
2769
2770 static int i915_energy_uJ(struct seq_file *m, void *data)
2771 {
2772         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2773         unsigned long long power;
2774         u32 units;
2775
2776         if (INTEL_GEN(dev_priv) < 6)
2777                 return -ENODEV;
2778
2779         intel_runtime_pm_get(dev_priv);
2780
2781         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2782                 intel_runtime_pm_put(dev_priv);
2783                 return -ENODEV;
2784         }
2785
2786         units = (power & 0x1f00) >> 8;
2787         power = I915_READ(MCH_SECP_NRG_STTS);
2788         power = (1000000 * power) >> units; /* convert to uJ */
2789
2790         intel_runtime_pm_put(dev_priv);
2791
2792         seq_printf(m, "%llu", power);
2793
2794         return 0;
2795 }
2796
2797 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2798 {
2799         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2800         struct pci_dev *pdev = dev_priv->drm.pdev;
2801
2802         if (!HAS_RUNTIME_PM(dev_priv))
2803                 seq_puts(m, "Runtime power management not supported\n");
2804
2805         seq_printf(m, "GPU idle: %s (epoch %u)\n",
2806                    yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
2807         seq_printf(m, "IRQs disabled: %s\n",
2808                    yesno(!intel_irqs_enabled(dev_priv)));
2809 #ifdef CONFIG_PM
2810         seq_printf(m, "Usage count: %d\n",
2811                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2812 #else
2813         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2814 #endif
2815         seq_printf(m, "PCI device power state: %s [%d]\n",
2816                    pci_power_name(pdev->current_state),
2817                    pdev->current_state);
2818
2819         return 0;
2820 }
2821
2822 static int i915_power_domain_info(struct seq_file *m, void *unused)
2823 {
2824         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2825         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2826         int i;
2827
2828         mutex_lock(&power_domains->lock);
2829
2830         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2831         for (i = 0; i < power_domains->power_well_count; i++) {
2832                 struct i915_power_well *power_well;
2833                 enum intel_display_power_domain power_domain;
2834
2835                 power_well = &power_domains->power_wells[i];
2836                 seq_printf(m, "%-25s %d\n", power_well->name,
2837                            power_well->count);
2838
2839                 for_each_power_domain(power_domain, power_well->domains)
2840                         seq_printf(m, "  %-23s %d\n",
2841                                  intel_display_power_domain_str(power_domain),
2842                                  power_domains->domain_use_count[power_domain]);
2843         }
2844
2845         mutex_unlock(&power_domains->lock);
2846
2847         return 0;
2848 }
2849
2850 static int i915_dmc_info(struct seq_file *m, void *unused)
2851 {
2852         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2853         struct intel_csr *csr;
2854
2855         if (!HAS_CSR(dev_priv))
2856                 return -ENODEV;
2857
2858         csr = &dev_priv->csr;
2859
2860         intel_runtime_pm_get(dev_priv);
2861
2862         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2863         seq_printf(m, "path: %s\n", csr->fw_path);
2864
2865         if (!csr->dmc_payload)
2866                 goto out;
2867
2868         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2869                    CSR_VERSION_MINOR(csr->version));
2870
2871         if (IS_KABYLAKE(dev_priv) ||
2872             (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2873                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2874                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2875                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2876                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2877         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2878                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2879                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2880         }
2881
2882 out:
2883         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2884         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2885         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2886
2887         intel_runtime_pm_put(dev_priv);
2888
2889         return 0;
2890 }
2891
2892 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2893                                  struct drm_display_mode *mode)
2894 {
2895         int i;
2896
2897         for (i = 0; i < tabs; i++)
2898                 seq_putc(m, '\t');
2899
2900         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2901                    mode->base.id, mode->name,
2902                    mode->vrefresh, mode->clock,
2903                    mode->hdisplay, mode->hsync_start,
2904                    mode->hsync_end, mode->htotal,
2905                    mode->vdisplay, mode->vsync_start,
2906                    mode->vsync_end, mode->vtotal,
2907                    mode->type, mode->flags);
2908 }
2909
2910 static void intel_encoder_info(struct seq_file *m,
2911                                struct intel_crtc *intel_crtc,
2912                                struct intel_encoder *intel_encoder)
2913 {
2914         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2915         struct drm_device *dev = &dev_priv->drm;
2916         struct drm_crtc *crtc = &intel_crtc->base;
2917         struct intel_connector *intel_connector;
2918         struct drm_encoder *encoder;
2919
2920         encoder = &intel_encoder->base;
2921         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2922                    encoder->base.id, encoder->name);
2923         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2924                 struct drm_connector *connector = &intel_connector->base;
2925                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2926                            connector->base.id,
2927                            connector->name,
2928                            drm_get_connector_status_name(connector->status));
2929                 if (connector->status == connector_status_connected) {
2930                         struct drm_display_mode *mode = &crtc->mode;
2931                         seq_printf(m, ", mode:\n");
2932                         intel_seq_print_mode(m, 2, mode);
2933                 } else {
2934                         seq_putc(m, '\n');
2935                 }
2936         }
2937 }
2938
2939 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2940 {
2941         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2942         struct drm_device *dev = &dev_priv->drm;
2943         struct drm_crtc *crtc = &intel_crtc->base;
2944         struct intel_encoder *intel_encoder;
2945         struct drm_plane_state *plane_state = crtc->primary->state;
2946         struct drm_framebuffer *fb = plane_state->fb;
2947
2948         if (fb)
2949                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2950                            fb->base.id, plane_state->src_x >> 16,
2951                            plane_state->src_y >> 16, fb->width, fb->height);
2952         else
2953                 seq_puts(m, "\tprimary plane disabled\n");
2954         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2955                 intel_encoder_info(m, intel_crtc, intel_encoder);
2956 }
2957
2958 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2959 {
2960         struct drm_display_mode *mode = panel->fixed_mode;
2961
2962         seq_printf(m, "\tfixed mode:\n");
2963         intel_seq_print_mode(m, 2, mode);
2964 }
2965
2966 static void intel_dp_info(struct seq_file *m,
2967                           struct intel_connector *intel_connector)
2968 {
2969         struct intel_encoder *intel_encoder = intel_connector->encoder;
2970         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2971
2972         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2973         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2974         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2975                 intel_panel_info(m, &intel_connector->panel);
2976
2977         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2978                                 &intel_dp->aux);
2979 }
2980
2981 static void intel_dp_mst_info(struct seq_file *m,
2982                           struct intel_connector *intel_connector)
2983 {
2984         struct intel_encoder *intel_encoder = intel_connector->encoder;
2985         struct intel_dp_mst_encoder *intel_mst =
2986                 enc_to_mst(&intel_encoder->base);
2987         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2988         struct intel_dp *intel_dp = &intel_dig_port->dp;
2989         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2990                                         intel_connector->port);
2991
2992         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2993 }
2994
2995 static void intel_hdmi_info(struct seq_file *m,
2996                             struct intel_connector *intel_connector)
2997 {
2998         struct intel_encoder *intel_encoder = intel_connector->encoder;
2999         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3000
3001         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3002 }
3003
3004 static void intel_lvds_info(struct seq_file *m,
3005                             struct intel_connector *intel_connector)
3006 {
3007         intel_panel_info(m, &intel_connector->panel);
3008 }
3009
3010 static void intel_connector_info(struct seq_file *m,
3011                                  struct drm_connector *connector)
3012 {
3013         struct intel_connector *intel_connector = to_intel_connector(connector);
3014         struct intel_encoder *intel_encoder = intel_connector->encoder;
3015         struct drm_display_mode *mode;
3016
3017         seq_printf(m, "connector %d: type %s, status: %s\n",
3018                    connector->base.id, connector->name,
3019                    drm_get_connector_status_name(connector->status));
3020         if (connector->status == connector_status_connected) {
3021                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3022                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3023                            connector->display_info.width_mm,
3024                            connector->display_info.height_mm);
3025                 seq_printf(m, "\tsubpixel order: %s\n",
3026                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3027                 seq_printf(m, "\tCEA rev: %d\n",
3028                            connector->display_info.cea_rev);
3029         }
3030
3031         if (!intel_encoder)
3032                 return;
3033
3034         switch (connector->connector_type) {
3035         case DRM_MODE_CONNECTOR_DisplayPort:
3036         case DRM_MODE_CONNECTOR_eDP:
3037                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3038                         intel_dp_mst_info(m, intel_connector);
3039                 else
3040                         intel_dp_info(m, intel_connector);
3041                 break;
3042         case DRM_MODE_CONNECTOR_LVDS:
3043                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3044                         intel_lvds_info(m, intel_connector);
3045                 break;
3046         case DRM_MODE_CONNECTOR_HDMIA:
3047                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3048                     intel_encoder->type == INTEL_OUTPUT_DDI)
3049                         intel_hdmi_info(m, intel_connector);
3050                 break;
3051         default:
3052                 break;
3053         }
3054
3055         seq_printf(m, "\tmodes:\n");
3056         list_for_each_entry(mode, &connector->modes, head)
3057                 intel_seq_print_mode(m, 2, mode);
3058 }
3059
3060 static const char *plane_type(enum drm_plane_type type)
3061 {
3062         switch (type) {
3063         case DRM_PLANE_TYPE_OVERLAY:
3064                 return "OVL";
3065         case DRM_PLANE_TYPE_PRIMARY:
3066                 return "PRI";
3067         case DRM_PLANE_TYPE_CURSOR:
3068                 return "CUR";
3069         /*
3070          * Deliberately omitting default: to generate compiler warnings
3071          * when a new drm_plane_type gets added.
3072          */
3073         }
3074
3075         return "unknown";
3076 }
3077
3078 static const char *plane_rotation(unsigned int rotation)
3079 {
3080         static char buf[48];
3081         /*
3082          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3083          * will print them all to visualize if the values are misused
3084          */
3085         snprintf(buf, sizeof(buf),
3086                  "%s%s%s%s%s%s(0x%08x)",
3087                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3088                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3089                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3090                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3091                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3092                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3093                  rotation);
3094
3095         return buf;
3096 }
3097
3098 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3099 {
3100         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3101         struct drm_device *dev = &dev_priv->drm;
3102         struct intel_plane *intel_plane;
3103
3104         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3105                 struct drm_plane_state *state;
3106                 struct drm_plane *plane = &intel_plane->base;
3107                 struct drm_format_name_buf format_name;
3108
3109                 if (!plane->state) {
3110                         seq_puts(m, "plane->state is NULL!\n");
3111                         continue;
3112                 }
3113
3114                 state = plane->state;
3115
3116                 if (state->fb) {
3117                         drm_get_format_name(state->fb->format->format,
3118                                             &format_name);
3119                 } else {
3120                         sprintf(format_name.str, "N/A");
3121                 }
3122
3123                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3124                            plane->base.id,
3125                            plane_type(intel_plane->base.type),
3126                            state->crtc_x, state->crtc_y,
3127                            state->crtc_w, state->crtc_h,
3128                            (state->src_x >> 16),
3129                            ((state->src_x & 0xffff) * 15625) >> 10,
3130                            (state->src_y >> 16),
3131                            ((state->src_y & 0xffff) * 15625) >> 10,
3132                            (state->src_w >> 16),
3133                            ((state->src_w & 0xffff) * 15625) >> 10,
3134                            (state->src_h >> 16),
3135                            ((state->src_h & 0xffff) * 15625) >> 10,
3136                            format_name.str,
3137                            plane_rotation(state->rotation));
3138         }
3139 }
3140
3141 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3142 {
3143         struct intel_crtc_state *pipe_config;
3144         int num_scalers = intel_crtc->num_scalers;
3145         int i;
3146
3147         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3148
3149         /* Not all platformas have a scaler */
3150         if (num_scalers) {
3151                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3152                            num_scalers,
3153                            pipe_config->scaler_state.scaler_users,
3154                            pipe_config->scaler_state.scaler_id);
3155
3156                 for (i = 0; i < num_scalers; i++) {
3157                         struct intel_scaler *sc =
3158                                         &pipe_config->scaler_state.scalers[i];
3159
3160                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3161                                    i, yesno(sc->in_use), sc->mode);
3162                 }
3163                 seq_puts(m, "\n");
3164         } else {
3165                 seq_puts(m, "\tNo scalers available on this platform\n");
3166         }
3167 }
3168
3169 static int i915_display_info(struct seq_file *m, void *unused)
3170 {
3171         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3172         struct drm_device *dev = &dev_priv->drm;
3173         struct intel_crtc *crtc;
3174         struct drm_connector *connector;
3175         struct drm_connector_list_iter conn_iter;
3176
3177         intel_runtime_pm_get(dev_priv);
3178         seq_printf(m, "CRTC info\n");
3179         seq_printf(m, "---------\n");
3180         for_each_intel_crtc(dev, crtc) {
3181                 struct intel_crtc_state *pipe_config;
3182
3183                 drm_modeset_lock(&crtc->base.mutex, NULL);
3184                 pipe_config = to_intel_crtc_state(crtc->base.state);
3185
3186                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3187                            crtc->base.base.id, pipe_name(crtc->pipe),
3188                            yesno(pipe_config->base.active),
3189                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3190                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3191
3192                 if (pipe_config->base.active) {
3193                         struct intel_plane *cursor =
3194                                 to_intel_plane(crtc->base.cursor);
3195
3196                         intel_crtc_info(m, crtc);
3197
3198                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3199                                    yesno(cursor->base.state->visible),
3200                                    cursor->base.state->crtc_x,
3201                                    cursor->base.state->crtc_y,
3202                                    cursor->base.state->crtc_w,
3203                                    cursor->base.state->crtc_h,
3204                                    cursor->cursor.base);
3205                         intel_scaler_info(m, crtc);
3206                         intel_plane_info(m, crtc);
3207                 }
3208
3209                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3210                            yesno(!crtc->cpu_fifo_underrun_disabled),
3211                            yesno(!crtc->pch_fifo_underrun_disabled));
3212                 drm_modeset_unlock(&crtc->base.mutex);
3213         }
3214
3215         seq_printf(m, "\n");
3216         seq_printf(m, "Connector info\n");
3217         seq_printf(m, "--------------\n");
3218         mutex_lock(&dev->mode_config.mutex);
3219         drm_connector_list_iter_begin(dev, &conn_iter);
3220         drm_for_each_connector_iter(connector, &conn_iter)
3221                 intel_connector_info(m, connector);
3222         drm_connector_list_iter_end(&conn_iter);
3223         mutex_unlock(&dev->mode_config.mutex);
3224
3225         intel_runtime_pm_put(dev_priv);
3226
3227         return 0;
3228 }
3229
3230 static int i915_engine_info(struct seq_file *m, void *unused)
3231 {
3232         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3233         struct intel_engine_cs *engine;
3234         enum intel_engine_id id;
3235         struct drm_printer p;
3236
3237         intel_runtime_pm_get(dev_priv);
3238
3239         seq_printf(m, "GT awake? %s (epoch %u)\n",
3240                    yesno(dev_priv->gt.awake), dev_priv->gt.epoch);
3241         seq_printf(m, "Global active requests: %d\n",
3242                    dev_priv->gt.active_requests);
3243         seq_printf(m, "CS timestamp frequency: %u kHz\n",
3244                    dev_priv->info.cs_timestamp_frequency_khz);
3245
3246         p = drm_seq_file_printer(m);
3247         for_each_engine(engine, dev_priv, id)
3248                 intel_engine_dump(engine, &p, "%s\n", engine->name);
3249
3250         intel_runtime_pm_put(dev_priv);
3251
3252         return 0;
3253 }
3254
3255 static int i915_rcs_topology(struct seq_file *m, void *unused)
3256 {
3257         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3258         struct drm_printer p = drm_seq_file_printer(m);
3259
3260         intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
3261
3262         return 0;
3263 }
3264
3265 static int i915_shrinker_info(struct seq_file *m, void *unused)
3266 {
3267         struct drm_i915_private *i915 = node_to_i915(m->private);
3268
3269         seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3270         seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3271
3272         return 0;
3273 }
3274
3275 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3276 {
3277         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3278         struct drm_device *dev = &dev_priv->drm;
3279         int i;
3280
3281         drm_modeset_lock_all(dev);
3282         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3283                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3284
3285                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
3286                            pll->info->id);
3287                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3288                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3289                 seq_printf(m, " tracked hardware state:\n");
3290                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3291                 seq_printf(m, " dpll_md: 0x%08x\n",
3292                            pll->state.hw_state.dpll_md);
3293                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3294                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3295                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3296                 seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
3297                 seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
3298                 seq_printf(m, " mg_refclkin_ctl:        0x%08x\n",
3299                            pll->state.hw_state.mg_refclkin_ctl);
3300                 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
3301                            pll->state.hw_state.mg_clktop2_coreclkctl1);
3302                 seq_printf(m, " mg_clktop2_hsclkctl:    0x%08x\n",
3303                            pll->state.hw_state.mg_clktop2_hsclkctl);
3304                 seq_printf(m, " mg_pll_div0:  0x%08x\n",
3305                            pll->state.hw_state.mg_pll_div0);
3306                 seq_printf(m, " mg_pll_div1:  0x%08x\n",
3307                            pll->state.hw_state.mg_pll_div1);
3308                 seq_printf(m, " mg_pll_lf:    0x%08x\n",
3309                            pll->state.hw_state.mg_pll_lf);
3310                 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
3311                            pll->state.hw_state.mg_pll_frac_lock);
3312                 seq_printf(m, " mg_pll_ssc:   0x%08x\n",
3313                            pll->state.hw_state.mg_pll_ssc);
3314                 seq_printf(m, " mg_pll_bias:  0x%08x\n",
3315                            pll->state.hw_state.mg_pll_bias);
3316                 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
3317                            pll->state.hw_state.mg_pll_tdc_coldst_bias);
3318         }
3319         drm_modeset_unlock_all(dev);
3320
3321         return 0;
3322 }
3323
3324 static int i915_wa_registers(struct seq_file *m, void *unused)
3325 {
3326         struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
3327         int i;
3328
3329         seq_printf(m, "Workarounds applied: %d\n", wa->count);
3330         for (i = 0; i < wa->count; ++i)
3331                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
3332                            wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
3333
3334         return 0;
3335 }
3336
3337 static int i915_ipc_status_show(struct seq_file *m, void *data)
3338 {
3339         struct drm_i915_private *dev_priv = m->private;
3340
3341         seq_printf(m, "Isochronous Priority Control: %s\n",
3342                         yesno(dev_priv->ipc_enabled));
3343         return 0;
3344 }
3345
3346 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3347 {
3348         struct drm_i915_private *dev_priv = inode->i_private;
3349
3350         if (!HAS_IPC(dev_priv))
3351                 return -ENODEV;
3352
3353         return single_open(file, i915_ipc_status_show, dev_priv);
3354 }
3355
3356 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3357                                      size_t len, loff_t *offp)
3358 {
3359         struct seq_file *m = file->private_data;
3360         struct drm_i915_private *dev_priv = m->private;
3361         int ret;
3362         bool enable;
3363
3364         ret = kstrtobool_from_user(ubuf, len, &enable);
3365         if (ret < 0)
3366                 return ret;
3367
3368         intel_runtime_pm_get(dev_priv);
3369         if (!dev_priv->ipc_enabled && enable)
3370                 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3371         dev_priv->wm.distrust_bios_wm = true;
3372         dev_priv->ipc_enabled = enable;
3373         intel_enable_ipc(dev_priv);
3374         intel_runtime_pm_put(dev_priv);
3375
3376         return len;
3377 }
3378
3379 static const struct file_operations i915_ipc_status_fops = {
3380         .owner = THIS_MODULE,
3381         .open = i915_ipc_status_open,
3382         .read = seq_read,
3383         .llseek = seq_lseek,
3384         .release = single_release,
3385         .write = i915_ipc_status_write
3386 };
3387
3388 static int i915_ddb_info(struct seq_file *m, void *unused)
3389 {
3390         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3391         struct drm_device *dev = &dev_priv->drm;
3392         struct skl_ddb_allocation *ddb;
3393         struct skl_ddb_entry *entry;
3394         enum pipe pipe;
3395         int plane;
3396
3397         if (INTEL_GEN(dev_priv) < 9)
3398                 return -ENODEV;
3399
3400         drm_modeset_lock_all(dev);
3401
3402         ddb = &dev_priv->wm.skl_hw.ddb;
3403
3404         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3405
3406         for_each_pipe(dev_priv, pipe) {
3407                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3408
3409                 for_each_universal_plane(dev_priv, pipe, plane) {
3410                         entry = &ddb->plane[pipe][plane];
3411                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3412                                    entry->start, entry->end,
3413                                    skl_ddb_entry_size(entry));
3414                 }
3415
3416                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3417                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3418                            entry->end, skl_ddb_entry_size(entry));
3419         }
3420
3421         drm_modeset_unlock_all(dev);
3422
3423         return 0;
3424 }
3425
3426 static void drrs_status_per_crtc(struct seq_file *m,
3427                                  struct drm_device *dev,
3428                                  struct intel_crtc *intel_crtc)
3429 {
3430         struct drm_i915_private *dev_priv = to_i915(dev);
3431         struct i915_drrs *drrs = &dev_priv->drrs;
3432         int vrefresh = 0;
3433         struct drm_connector *connector;
3434         struct drm_connector_list_iter conn_iter;
3435
3436         drm_connector_list_iter_begin(dev, &conn_iter);
3437         drm_for_each_connector_iter(connector, &conn_iter) {
3438                 if (connector->state->crtc != &intel_crtc->base)
3439                         continue;
3440
3441                 seq_printf(m, "%s:\n", connector->name);
3442         }
3443         drm_connector_list_iter_end(&conn_iter);
3444
3445         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3446                 seq_puts(m, "\tVBT: DRRS_type: Static");
3447         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3448                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3449         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3450                 seq_puts(m, "\tVBT: DRRS_type: None");
3451         else
3452                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3453
3454         seq_puts(m, "\n\n");
3455
3456         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3457                 struct intel_panel *panel;
3458
3459                 mutex_lock(&drrs->mutex);
3460                 /* DRRS Supported */
3461                 seq_puts(m, "\tDRRS Supported: Yes\n");
3462
3463                 /* disable_drrs() will make drrs->dp NULL */
3464                 if (!drrs->dp) {
3465                         seq_puts(m, "Idleness DRRS: Disabled\n");
3466                         if (dev_priv->psr.enabled)
3467                                 seq_puts(m,
3468                                 "\tAs PSR is enabled, DRRS is not enabled\n");
3469                         mutex_unlock(&drrs->mutex);
3470                         return;
3471                 }
3472
3473                 panel = &drrs->dp->attached_connector->panel;
3474                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3475                                         drrs->busy_frontbuffer_bits);
3476
3477                 seq_puts(m, "\n\t\t");
3478                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3479                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3480                         vrefresh = panel->fixed_mode->vrefresh;
3481                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3482                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3483                         vrefresh = panel->downclock_mode->vrefresh;
3484                 } else {
3485                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3486                                                 drrs->refresh_rate_type);
3487                         mutex_unlock(&drrs->mutex);
3488                         return;
3489                 }
3490                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3491
3492                 seq_puts(m, "\n\t\t");
3493                 mutex_unlock(&drrs->mutex);
3494         } else {
3495                 /* DRRS not supported. Print the VBT parameter*/
3496                 seq_puts(m, "\tDRRS Supported : No");
3497         }
3498         seq_puts(m, "\n");
3499 }
3500
3501 static int i915_drrs_status(struct seq_file *m, void *unused)
3502 {
3503         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3504         struct drm_device *dev = &dev_priv->drm;
3505         struct intel_crtc *intel_crtc;
3506         int active_crtc_cnt = 0;
3507
3508         drm_modeset_lock_all(dev);
3509         for_each_intel_crtc(dev, intel_crtc) {
3510                 if (intel_crtc->base.state->active) {
3511                         active_crtc_cnt++;
3512                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3513
3514                         drrs_status_per_crtc(m, dev, intel_crtc);
3515                 }
3516         }
3517         drm_modeset_unlock_all(dev);
3518
3519         if (!active_crtc_cnt)
3520                 seq_puts(m, "No active crtc found\n");
3521
3522         return 0;
3523 }
3524
3525 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3526 {
3527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3528         struct drm_device *dev = &dev_priv->drm;
3529         struct intel_encoder *intel_encoder;
3530         struct intel_digital_port *intel_dig_port;
3531         struct drm_connector *connector;
3532         struct drm_connector_list_iter conn_iter;
3533
3534         drm_connector_list_iter_begin(dev, &conn_iter);
3535         drm_for_each_connector_iter(connector, &conn_iter) {
3536                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3537                         continue;
3538
3539                 intel_encoder = intel_attached_encoder(connector);
3540                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3541                         continue;
3542
3543                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3544                 if (!intel_dig_port->dp.can_mst)
3545                         continue;
3546
3547                 seq_printf(m, "MST Source Port %c\n",
3548                            port_name(intel_dig_port->base.port));
3549                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3550         }
3551         drm_connector_list_iter_end(&conn_iter);
3552
3553         return 0;
3554 }
3555
3556 static ssize_t i915_displayport_test_active_write(struct file *file,
3557                                                   const char __user *ubuf,
3558                                                   size_t len, loff_t *offp)
3559 {
3560         char *input_buffer;
3561         int status = 0;
3562         struct drm_device *dev;
3563         struct drm_connector *connector;
3564         struct drm_connector_list_iter conn_iter;
3565         struct intel_dp *intel_dp;
3566         int val = 0;
3567
3568         dev = ((struct seq_file *)file->private_data)->private;
3569
3570         if (len == 0)
3571                 return 0;
3572
3573         input_buffer = memdup_user_nul(ubuf, len);
3574         if (IS_ERR(input_buffer))
3575                 return PTR_ERR(input_buffer);
3576
3577         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3578
3579         drm_connector_list_iter_begin(dev, &conn_iter);
3580         drm_for_each_connector_iter(connector, &conn_iter) {
3581                 struct intel_encoder *encoder;
3582
3583                 if (connector->connector_type !=
3584                     DRM_MODE_CONNECTOR_DisplayPort)
3585                         continue;
3586
3587                 encoder = to_intel_encoder(connector->encoder);
3588                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3589                         continue;
3590
3591                 if (encoder && connector->status == connector_status_connected) {
3592                         intel_dp = enc_to_intel_dp(&encoder->base);
3593                         status = kstrtoint(input_buffer, 10, &val);
3594                         if (status < 0)
3595                                 break;
3596                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3597                         /* To prevent erroneous activation of the compliance
3598                          * testing code, only accept an actual value of 1 here
3599                          */
3600                         if (val == 1)
3601                                 intel_dp->compliance.test_active = 1;
3602                         else
3603                                 intel_dp->compliance.test_active = 0;
3604                 }
3605         }
3606         drm_connector_list_iter_end(&conn_iter);
3607         kfree(input_buffer);
3608         if (status < 0)
3609                 return status;
3610
3611         *offp += len;
3612         return len;
3613 }
3614
3615 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3616 {
3617         struct drm_i915_private *dev_priv = m->private;
3618         struct drm_device *dev = &dev_priv->drm;
3619         struct drm_connector *connector;
3620         struct drm_connector_list_iter conn_iter;
3621         struct intel_dp *intel_dp;
3622
3623         drm_connector_list_iter_begin(dev, &conn_iter);
3624         drm_for_each_connector_iter(connector, &conn_iter) {
3625                 struct intel_encoder *encoder;
3626
3627                 if (connector->connector_type !=
3628                     DRM_MODE_CONNECTOR_DisplayPort)
3629                         continue;
3630
3631                 encoder = to_intel_encoder(connector->encoder);
3632                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3633                         continue;
3634
3635                 if (encoder && connector->status == connector_status_connected) {
3636                         intel_dp = enc_to_intel_dp(&encoder->base);
3637                         if (intel_dp->compliance.test_active)
3638                                 seq_puts(m, "1");
3639                         else
3640                                 seq_puts(m, "0");
3641                 } else
3642                         seq_puts(m, "0");
3643         }
3644         drm_connector_list_iter_end(&conn_iter);
3645
3646         return 0;
3647 }
3648
3649 static int i915_displayport_test_active_open(struct inode *inode,
3650                                              struct file *file)
3651 {
3652         return single_open(file, i915_displayport_test_active_show,
3653                            inode->i_private);
3654 }
3655
3656 static const struct file_operations i915_displayport_test_active_fops = {
3657         .owner = THIS_MODULE,
3658         .open = i915_displayport_test_active_open,
3659         .read = seq_read,
3660         .llseek = seq_lseek,
3661         .release = single_release,
3662         .write = i915_displayport_test_active_write
3663 };
3664
3665 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3666 {
3667         struct drm_i915_private *dev_priv = m->private;
3668         struct drm_device *dev = &dev_priv->drm;
3669         struct drm_connector *connector;
3670         struct drm_connector_list_iter conn_iter;
3671         struct intel_dp *intel_dp;
3672
3673         drm_connector_list_iter_begin(dev, &conn_iter);
3674         drm_for_each_connector_iter(connector, &conn_iter) {
3675                 struct intel_encoder *encoder;
3676
3677                 if (connector->connector_type !=
3678                     DRM_MODE_CONNECTOR_DisplayPort)
3679                         continue;
3680
3681                 encoder = to_intel_encoder(connector->encoder);
3682                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3683                         continue;
3684
3685                 if (encoder && connector->status == connector_status_connected) {
3686                         intel_dp = enc_to_intel_dp(&encoder->base);
3687                         if (intel_dp->compliance.test_type ==
3688                             DP_TEST_LINK_EDID_READ)
3689                                 seq_printf(m, "%lx",
3690                                            intel_dp->compliance.test_data.edid);
3691                         else if (intel_dp->compliance.test_type ==
3692                                  DP_TEST_LINK_VIDEO_PATTERN) {
3693                                 seq_printf(m, "hdisplay: %d\n",
3694                                            intel_dp->compliance.test_data.hdisplay);
3695                                 seq_printf(m, "vdisplay: %d\n",
3696                                            intel_dp->compliance.test_data.vdisplay);
3697                                 seq_printf(m, "bpc: %u\n",
3698                                            intel_dp->compliance.test_data.bpc);
3699                         }
3700                 } else
3701                         seq_puts(m, "0");
3702         }
3703         drm_connector_list_iter_end(&conn_iter);
3704
3705         return 0;
3706 }
3707 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
3708
3709 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3710 {
3711         struct drm_i915_private *dev_priv = m->private;
3712         struct drm_device *dev = &dev_priv->drm;
3713         struct drm_connector *connector;
3714         struct drm_connector_list_iter conn_iter;
3715         struct intel_dp *intel_dp;
3716
3717         drm_connector_list_iter_begin(dev, &conn_iter);
3718         drm_for_each_connector_iter(connector, &conn_iter) {
3719                 struct intel_encoder *encoder;
3720
3721                 if (connector->connector_type !=
3722                     DRM_MODE_CONNECTOR_DisplayPort)
3723                         continue;
3724
3725                 encoder = to_intel_encoder(connector->encoder);
3726                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3727                         continue;
3728
3729                 if (encoder && connector->status == connector_status_connected) {
3730                         intel_dp = enc_to_intel_dp(&encoder->base);
3731                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3732                 } else
3733                         seq_puts(m, "0");
3734         }
3735         drm_connector_list_iter_end(&conn_iter);
3736
3737         return 0;
3738 }
3739 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
3740
3741 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3742 {
3743         struct drm_i915_private *dev_priv = m->private;
3744         struct drm_device *dev = &dev_priv->drm;
3745         int level;
3746         int num_levels;
3747
3748         if (IS_CHERRYVIEW(dev_priv))
3749                 num_levels = 3;
3750         else if (IS_VALLEYVIEW(dev_priv))
3751                 num_levels = 1;
3752         else if (IS_G4X(dev_priv))
3753                 num_levels = 3;
3754         else
3755                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3756
3757         drm_modeset_lock_all(dev);
3758
3759         for (level = 0; level < num_levels; level++) {
3760                 unsigned int latency = wm[level];
3761
3762                 /*
3763                  * - WM1+ latency values in 0.5us units
3764                  * - latencies are in us on gen9/vlv/chv
3765                  */
3766                 if (INTEL_GEN(dev_priv) >= 9 ||
3767                     IS_VALLEYVIEW(dev_priv) ||
3768                     IS_CHERRYVIEW(dev_priv) ||
3769                     IS_G4X(dev_priv))
3770                         latency *= 10;
3771                 else if (level > 0)
3772                         latency *= 5;
3773
3774                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3775                            level, wm[level], latency / 10, latency % 10);
3776         }
3777
3778         drm_modeset_unlock_all(dev);
3779 }
3780
3781 static int pri_wm_latency_show(struct seq_file *m, void *data)
3782 {
3783         struct drm_i915_private *dev_priv = m->private;
3784         const uint16_t *latencies;
3785
3786         if (INTEL_GEN(dev_priv) >= 9)
3787                 latencies = dev_priv->wm.skl_latency;
3788         else
3789                 latencies = dev_priv->wm.pri_latency;
3790
3791         wm_latency_show(m, latencies);
3792
3793         return 0;
3794 }
3795
3796 static int spr_wm_latency_show(struct seq_file *m, void *data)
3797 {
3798         struct drm_i915_private *dev_priv = m->private;
3799         const uint16_t *latencies;
3800
3801         if (INTEL_GEN(dev_priv) >= 9)
3802                 latencies = dev_priv->wm.skl_latency;
3803         else
3804                 latencies = dev_priv->wm.spr_latency;
3805
3806         wm_latency_show(m, latencies);
3807
3808         return 0;
3809 }
3810
3811 static int cur_wm_latency_show(struct seq_file *m, void *data)
3812 {
3813         struct drm_i915_private *dev_priv = m->private;
3814         const uint16_t *latencies;
3815
3816         if (INTEL_GEN(dev_priv) >= 9)
3817                 latencies = dev_priv->wm.skl_latency;
3818         else
3819                 latencies = dev_priv->wm.cur_latency;
3820
3821         wm_latency_show(m, latencies);
3822
3823         return 0;
3824 }
3825
3826 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3827 {
3828         struct drm_i915_private *dev_priv = inode->i_private;
3829
3830         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3831                 return -ENODEV;
3832
3833         return single_open(file, pri_wm_latency_show, dev_priv);
3834 }
3835
3836 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3837 {
3838         struct drm_i915_private *dev_priv = inode->i_private;
3839
3840         if (HAS_GMCH_DISPLAY(dev_priv))
3841                 return -ENODEV;
3842
3843         return single_open(file, spr_wm_latency_show, dev_priv);
3844 }
3845
3846 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3847 {
3848         struct drm_i915_private *dev_priv = inode->i_private;
3849
3850         if (HAS_GMCH_DISPLAY(dev_priv))
3851                 return -ENODEV;
3852
3853         return single_open(file, cur_wm_latency_show, dev_priv);
3854 }
3855
3856 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3857                                 size_t len, loff_t *offp, uint16_t wm[8])
3858 {
3859         struct seq_file *m = file->private_data;
3860         struct drm_i915_private *dev_priv = m->private;
3861         struct drm_device *dev = &dev_priv->drm;
3862         uint16_t new[8] = { 0 };
3863         int num_levels;
3864         int level;
3865         int ret;
3866         char tmp[32];
3867
3868         if (IS_CHERRYVIEW(dev_priv))
3869                 num_levels = 3;
3870         else if (IS_VALLEYVIEW(dev_priv))
3871                 num_levels = 1;
3872         else if (IS_G4X(dev_priv))
3873                 num_levels = 3;
3874         else
3875                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3876
3877         if (len >= sizeof(tmp))
3878                 return -EINVAL;
3879
3880         if (copy_from_user(tmp, ubuf, len))
3881                 return -EFAULT;
3882
3883         tmp[len] = '\0';
3884
3885         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3886                      &new[0], &new[1], &new[2], &new[3],
3887                      &new[4], &new[5], &new[6], &new[7]);
3888         if (ret != num_levels)
3889                 return -EINVAL;
3890
3891         drm_modeset_lock_all(dev);
3892
3893         for (level = 0; level < num_levels; level++)
3894                 wm[level] = new[level];
3895
3896         drm_modeset_unlock_all(dev);
3897
3898         return len;
3899 }
3900
3901
3902 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3903                                     size_t len, loff_t *offp)
3904 {
3905         struct seq_file *m = file->private_data;
3906         struct drm_i915_private *dev_priv = m->private;
3907         uint16_t *latencies;
3908
3909         if (INTEL_GEN(dev_priv) >= 9)
3910                 latencies = dev_priv->wm.skl_latency;
3911         else
3912                 latencies = dev_priv->wm.pri_latency;
3913
3914         return wm_latency_write(file, ubuf, len, offp, latencies);
3915 }
3916
3917 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3918                                     size_t len, loff_t *offp)
3919 {
3920         struct seq_file *m = file->private_data;
3921         struct drm_i915_private *dev_priv = m->private;
3922         uint16_t *latencies;
3923
3924         if (INTEL_GEN(dev_priv) >= 9)
3925                 latencies = dev_priv->wm.skl_latency;
3926         else
3927                 latencies = dev_priv->wm.spr_latency;
3928
3929         return wm_latency_write(file, ubuf, len, offp, latencies);
3930 }
3931
3932 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3933                                     size_t len, loff_t *offp)
3934 {
3935         struct seq_file *m = file->private_data;
3936         struct drm_i915_private *dev_priv = m->private;
3937         uint16_t *latencies;
3938
3939         if (INTEL_GEN(dev_priv) >= 9)
3940                 latencies = dev_priv->wm.skl_latency;
3941         else
3942                 latencies = dev_priv->wm.cur_latency;
3943
3944         return wm_latency_write(file, ubuf, len, offp, latencies);
3945 }
3946
3947 static const struct file_operations i915_pri_wm_latency_fops = {
3948         .owner = THIS_MODULE,
3949         .open = pri_wm_latency_open,
3950         .read = seq_read,
3951         .llseek = seq_lseek,
3952         .release = single_release,
3953         .write = pri_wm_latency_write
3954 };
3955
3956 static const struct file_operations i915_spr_wm_latency_fops = {
3957         .owner = THIS_MODULE,
3958         .open = spr_wm_latency_open,
3959         .read = seq_read,
3960         .llseek = seq_lseek,
3961         .release = single_release,
3962         .write = spr_wm_latency_write
3963 };
3964
3965 static const struct file_operations i915_cur_wm_latency_fops = {
3966         .owner = THIS_MODULE,
3967         .open = cur_wm_latency_open,
3968         .read = seq_read,
3969         .llseek = seq_lseek,
3970         .release = single_release,
3971         .write = cur_wm_latency_write
3972 };
3973
3974 static int
3975 i915_wedged_get(void *data, u64 *val)
3976 {
3977         struct drm_i915_private *dev_priv = data;
3978
3979         *val = i915_terminally_wedged(&dev_priv->gpu_error);
3980
3981         return 0;
3982 }
3983
3984 static int
3985 i915_wedged_set(void *data, u64 val)
3986 {
3987         struct drm_i915_private *i915 = data;
3988         struct intel_engine_cs *engine;
3989         unsigned int tmp;
3990
3991         /*
3992          * There is no safeguard against this debugfs entry colliding
3993          * with the hangcheck calling same i915_handle_error() in
3994          * parallel, causing an explosion. For now we assume that the
3995          * test harness is responsible enough not to inject gpu hangs
3996          * while it is writing to 'i915_wedged'
3997          */
3998
3999         if (i915_reset_backoff(&i915->gpu_error))
4000                 return -EAGAIN;
4001
4002         for_each_engine_masked(engine, i915, val, tmp) {
4003                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4004                 engine->hangcheck.stalled = true;
4005         }
4006
4007         i915_handle_error(i915, val, I915_ERROR_CAPTURE,
4008                           "Manually set wedged engine mask = %llx", val);
4009
4010         wait_on_bit(&i915->gpu_error.flags,
4011                     I915_RESET_HANDOFF,
4012                     TASK_UNINTERRUPTIBLE);
4013
4014         return 0;
4015 }
4016
4017 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4018                         i915_wedged_get, i915_wedged_set,
4019                         "%llu\n");
4020
4021 static int
4022 fault_irq_set(struct drm_i915_private *i915,
4023               unsigned long *irq,
4024               unsigned long val)
4025 {
4026         int err;
4027
4028         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4029         if (err)
4030                 return err;
4031
4032         err = i915_gem_wait_for_idle(i915,
4033                                      I915_WAIT_LOCKED |
4034                                      I915_WAIT_INTERRUPTIBLE,
4035                                      MAX_SCHEDULE_TIMEOUT);
4036         if (err)
4037                 goto err_unlock;
4038
4039         *irq = val;
4040         mutex_unlock(&i915->drm.struct_mutex);
4041
4042         /* Flush idle worker to disarm irq */
4043         drain_delayed_work(&i915->gt.idle_work);
4044
4045         return 0;
4046
4047 err_unlock:
4048         mutex_unlock(&i915->drm.struct_mutex);
4049         return err;
4050 }
4051
4052 static int
4053 i915_ring_missed_irq_get(void *data, u64 *val)
4054 {
4055         struct drm_i915_private *dev_priv = data;
4056
4057         *val = dev_priv->gpu_error.missed_irq_rings;
4058         return 0;
4059 }
4060
4061 static int
4062 i915_ring_missed_irq_set(void *data, u64 val)
4063 {
4064         struct drm_i915_private *i915 = data;
4065
4066         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4067 }
4068
4069 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4070                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4071                         "0x%08llx\n");
4072
4073 static int
4074 i915_ring_test_irq_get(void *data, u64 *val)
4075 {
4076         struct drm_i915_private *dev_priv = data;
4077
4078         *val = dev_priv->gpu_error.test_irq_rings;
4079
4080         return 0;
4081 }
4082
4083 static int
4084 i915_ring_test_irq_set(void *data, u64 val)
4085 {
4086         struct drm_i915_private *i915 = data;
4087
4088         val &= INTEL_INFO(i915)->ring_mask;
4089         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4090
4091         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4092 }
4093
4094 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4095                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4096                         "0x%08llx\n");
4097
4098 #define DROP_UNBOUND    BIT(0)
4099 #define DROP_BOUND      BIT(1)
4100 #define DROP_RETIRE     BIT(2)
4101 #define DROP_ACTIVE     BIT(3)
4102 #define DROP_FREED      BIT(4)
4103 #define DROP_SHRINK_ALL BIT(5)
4104 #define DROP_IDLE       BIT(6)
4105 #define DROP_ALL (DROP_UNBOUND  | \
4106                   DROP_BOUND    | \
4107                   DROP_RETIRE   | \
4108                   DROP_ACTIVE   | \
4109                   DROP_FREED    | \
4110                   DROP_SHRINK_ALL |\
4111                   DROP_IDLE)
4112 static int
4113 i915_drop_caches_get(void *data, u64 *val)
4114 {
4115         *val = DROP_ALL;
4116
4117         return 0;
4118 }
4119
4120 static int
4121 i915_drop_caches_set(void *data, u64 val)
4122 {
4123         struct drm_i915_private *dev_priv = data;
4124         struct drm_device *dev = &dev_priv->drm;
4125         int ret = 0;
4126
4127         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4128                   val, val & DROP_ALL);
4129
4130         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4131          * on ioctls on -EAGAIN. */
4132         if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4133                 ret = mutex_lock_interruptible(&dev->struct_mutex);
4134                 if (ret)
4135                         return ret;
4136
4137                 if (val & DROP_ACTIVE)
4138                         ret = i915_gem_wait_for_idle(dev_priv,
4139                                                      I915_WAIT_INTERRUPTIBLE |
4140                                                      I915_WAIT_LOCKED,
4141                                                      MAX_SCHEDULE_TIMEOUT);
4142
4143                 if (val & DROP_RETIRE)
4144                         i915_retire_requests(dev_priv);
4145
4146                 mutex_unlock(&dev->struct_mutex);
4147         }
4148
4149         fs_reclaim_acquire(GFP_KERNEL);
4150         if (val & DROP_BOUND)
4151                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4152
4153         if (val & DROP_UNBOUND)
4154                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4155
4156         if (val & DROP_SHRINK_ALL)
4157                 i915_gem_shrink_all(dev_priv);
4158         fs_reclaim_release(GFP_KERNEL);
4159
4160         if (val & DROP_IDLE) {
4161                 do {
4162                         if (READ_ONCE(dev_priv->gt.active_requests))
4163                                 flush_delayed_work(&dev_priv->gt.retire_work);
4164                         drain_delayed_work(&dev_priv->gt.idle_work);
4165                 } while (READ_ONCE(dev_priv->gt.awake));
4166         }
4167
4168         if (val & DROP_FREED)
4169                 i915_gem_drain_freed_objects(dev_priv);
4170
4171         return ret;
4172 }
4173
4174 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4175                         i915_drop_caches_get, i915_drop_caches_set,
4176                         "0x%08llx\n");
4177
4178 static int
4179 i915_cache_sharing_get(void *data, u64 *val)
4180 {
4181         struct drm_i915_private *dev_priv = data;
4182         u32 snpcr;
4183
4184         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4185                 return -ENODEV;
4186
4187         intel_runtime_pm_get(dev_priv);
4188
4189         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4190
4191         intel_runtime_pm_put(dev_priv);
4192
4193         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4194
4195         return 0;
4196 }
4197
4198 static int
4199 i915_cache_sharing_set(void *data, u64 val)
4200 {
4201         struct drm_i915_private *dev_priv = data;
4202         u32 snpcr;
4203
4204         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4205                 return -ENODEV;
4206
4207         if (val > 3)
4208                 return -EINVAL;
4209
4210         intel_runtime_pm_get(dev_priv);
4211         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4212
4213         /* Update the cache sharing policy here as well */
4214         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4215         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4216         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4217         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4218
4219         intel_runtime_pm_put(dev_priv);
4220         return 0;
4221 }
4222
4223 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4224                         i915_cache_sharing_get, i915_cache_sharing_set,
4225                         "%llu\n");
4226
4227 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4228                                           struct sseu_dev_info *sseu)
4229 {
4230 #define SS_MAX 2
4231         const int ss_max = SS_MAX;
4232         u32 sig1[SS_MAX], sig2[SS_MAX];
4233         int ss;
4234
4235         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4236         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4237         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4238         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4239
4240         for (ss = 0; ss < ss_max; ss++) {
4241                 unsigned int eu_cnt;
4242
4243                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4244                         /* skip disabled subslice */
4245                         continue;
4246
4247                 sseu->slice_mask = BIT(0);
4248                 sseu->subslice_mask[0] |= BIT(ss);
4249                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4250                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4251                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4252                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4253                 sseu->eu_total += eu_cnt;
4254                 sseu->eu_per_subslice = max_t(unsigned int,
4255                                               sseu->eu_per_subslice, eu_cnt);
4256         }
4257 #undef SS_MAX
4258 }
4259
4260 static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
4261                                      struct sseu_dev_info *sseu)
4262 {
4263 #define SS_MAX 6
4264         const struct intel_device_info *info = INTEL_INFO(dev_priv);
4265         u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
4266         int s, ss;
4267
4268         for (s = 0; s < info->sseu.max_slices; s++) {
4269                 /*
4270                  * FIXME: Valid SS Mask respects the spec and read
4271                  * only valid bits for those registers, excluding reserverd
4272                  * although this seems wrong because it would leave many
4273                  * subslices without ACK.
4274                  */
4275                 s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
4276                         GEN10_PGCTL_VALID_SS_MASK(s);
4277                 eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
4278                 eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
4279         }
4280
4281         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4282                      GEN9_PGCTL_SSA_EU19_ACK |
4283                      GEN9_PGCTL_SSA_EU210_ACK |
4284                      GEN9_PGCTL_SSA_EU311_ACK;
4285         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4286                      GEN9_PGCTL_SSB_EU19_ACK |
4287                      GEN9_PGCTL_SSB_EU210_ACK |
4288                      GEN9_PGCTL_SSB_EU311_ACK;
4289
4290         for (s = 0; s < info->sseu.max_slices; s++) {
4291                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4292                         /* skip disabled slice */
4293                         continue;
4294
4295                 sseu->slice_mask |= BIT(s);
4296                 sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
4297
4298                 for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4299                         unsigned int eu_cnt;
4300
4301                         if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4302                                 /* skip disabled subslice */
4303                                 continue;
4304
4305                         eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
4306                                                eu_mask[ss % 2]);
4307                         sseu->eu_total += eu_cnt;
4308                         sseu->eu_per_subslice = max_t(unsigned int,
4309                                                       sseu->eu_per_subslice,
4310                                                       eu_cnt);
4311                 }
4312         }
4313 #undef SS_MAX
4314 }
4315
4316 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4317                                     struct sseu_dev_info *sseu)
4318 {
4319 #define SS_MAX 3
4320         const struct intel_device_info *info = INTEL_INFO(dev_priv);
4321         u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
4322         int s, ss;
4323
4324         for (s = 0; s < info->sseu.max_slices; s++) {
4325                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4326                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4327                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4328         }
4329
4330         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4331                      GEN9_PGCTL_SSA_EU19_ACK |
4332                      GEN9_PGCTL_SSA_EU210_ACK |
4333                      GEN9_PGCTL_SSA_EU311_ACK;
4334         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4335                      GEN9_PGCTL_SSB_EU19_ACK |
4336                      GEN9_PGCTL_SSB_EU210_ACK |
4337                      GEN9_PGCTL_SSB_EU311_ACK;
4338
4339         for (s = 0; s < info->sseu.max_slices; s++) {
4340                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4341                         /* skip disabled slice */
4342                         continue;
4343
4344                 sseu->slice_mask |= BIT(s);
4345
4346                 if (IS_GEN9_BC(dev_priv))
4347                         sseu->subslice_mask[s] =
4348                                 INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4349
4350                 for (ss = 0; ss < info->sseu.max_subslices; ss++) {
4351                         unsigned int eu_cnt;
4352
4353                         if (IS_GEN9_LP(dev_priv)) {
4354                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4355                                         /* skip disabled subslice */
4356                                         continue;
4357
4358                                 sseu->subslice_mask[s] |= BIT(ss);
4359                         }
4360
4361                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4362                                                eu_mask[ss%2]);
4363                         sseu->eu_total += eu_cnt;
4364                         sseu->eu_per_subslice = max_t(unsigned int,
4365                                                       sseu->eu_per_subslice,
4366                                                       eu_cnt);
4367                 }
4368         }
4369 #undef SS_MAX
4370 }
4371
4372 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4373                                          struct sseu_dev_info *sseu)
4374 {
4375         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4376         int s;
4377
4378         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4379
4380         if (sseu->slice_mask) {
4381                 sseu->eu_per_subslice =
4382                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4383                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4384                         sseu->subslice_mask[s] =
4385                                 INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
4386                 }
4387                 sseu->eu_total = sseu->eu_per_subslice *
4388                                  sseu_subslice_total(sseu);
4389
4390                 /* subtract fused off EU(s) from enabled slice(s) */
4391                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4392                         u8 subslice_7eu =
4393                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4394
4395                         sseu->eu_total -= hweight8(subslice_7eu);
4396                 }
4397         }
4398 }
4399
4400 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4401                                  const struct sseu_dev_info *sseu)
4402 {
4403         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4404         const char *type = is_available_info ? "Available" : "Enabled";
4405         int s;
4406
4407         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4408                    sseu->slice_mask);
4409         seq_printf(m, "  %s Slice Total: %u\n", type,
4410                    hweight8(sseu->slice_mask));
4411         seq_printf(m, "  %s Subslice Total: %u\n", type,
4412                    sseu_subslice_total(sseu));
4413         for (s = 0; s < fls(sseu->slice_mask); s++) {
4414                 seq_printf(m, "  %s Slice%i subslices: %u\n", type,
4415                            s, hweight8(sseu->subslice_mask[s]));
4416         }
4417         seq_printf(m, "  %s EU Total: %u\n", type,
4418                    sseu->eu_total);
4419         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4420                    sseu->eu_per_subslice);
4421
4422         if (!is_available_info)
4423                 return;
4424
4425         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4426         if (HAS_POOLED_EU(dev_priv))
4427                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4428
4429         seq_printf(m, "  Has Slice Power Gating: %s\n",
4430                    yesno(sseu->has_slice_pg));
4431         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4432                    yesno(sseu->has_subslice_pg));
4433         seq_printf(m, "  Has EU Power Gating: %s\n",
4434                    yesno(sseu->has_eu_pg));
4435 }
4436
4437 static int i915_sseu_status(struct seq_file *m, void *unused)
4438 {
4439         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4440         struct sseu_dev_info sseu;
4441
4442         if (INTEL_GEN(dev_priv) < 8)
4443                 return -ENODEV;
4444
4445         seq_puts(m, "SSEU Device Info\n");
4446         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4447
4448         seq_puts(m, "SSEU Device Status\n");
4449         memset(&sseu, 0, sizeof(sseu));
4450         sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
4451         sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
4452         sseu.max_eus_per_subslice =
4453                 INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
4454
4455         intel_runtime_pm_get(dev_priv);
4456
4457         if (IS_CHERRYVIEW(dev_priv)) {
4458                 cherryview_sseu_device_status(dev_priv, &sseu);
4459         } else if (IS_BROADWELL(dev_priv)) {
4460                 broadwell_sseu_device_status(dev_priv, &sseu);
4461         } else if (IS_GEN9(dev_priv)) {
4462                 gen9_sseu_device_status(dev_priv, &sseu);
4463         } else if (INTEL_GEN(dev_priv) >= 10) {
4464                 gen10_sseu_device_status(dev_priv, &sseu);
4465         }
4466
4467         intel_runtime_pm_put(dev_priv);
4468
4469         i915_print_sseu_info(m, false, &sseu);
4470
4471         return 0;
4472 }
4473
4474 static int i915_forcewake_open(struct inode *inode, struct file *file)
4475 {
4476         struct drm_i915_private *i915 = inode->i_private;
4477
4478         if (INTEL_GEN(i915) < 6)
4479                 return 0;
4480
4481         intel_runtime_pm_get(i915);
4482         intel_uncore_forcewake_user_get(i915);
4483
4484         return 0;
4485 }
4486
4487 static int i915_forcewake_release(struct inode *inode, struct file *file)
4488 {
4489         struct drm_i915_private *i915 = inode->i_private;
4490
4491         if (INTEL_GEN(i915) < 6)
4492                 return 0;
4493
4494         intel_uncore_forcewake_user_put(i915);
4495         intel_runtime_pm_put(i915);
4496
4497         return 0;
4498 }
4499
4500 static const struct file_operations i915_forcewake_fops = {
4501         .owner = THIS_MODULE,
4502         .open = i915_forcewake_open,
4503         .release = i915_forcewake_release,
4504 };
4505
4506 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4507 {
4508         struct drm_i915_private *dev_priv = m->private;
4509         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4510
4511         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4512         seq_printf(m, "Detected: %s\n",
4513                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4514
4515         return 0;
4516 }
4517
4518 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4519                                         const char __user *ubuf, size_t len,
4520                                         loff_t *offp)
4521 {
4522         struct seq_file *m = file->private_data;
4523         struct drm_i915_private *dev_priv = m->private;
4524         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4525         unsigned int new_threshold;
4526         int i;
4527         char *newline;
4528         char tmp[16];
4529
4530         if (len >= sizeof(tmp))
4531                 return -EINVAL;
4532
4533         if (copy_from_user(tmp, ubuf, len))
4534                 return -EFAULT;
4535
4536         tmp[len] = '\0';
4537
4538         /* Strip newline, if any */
4539         newline = strchr(tmp, '\n');
4540         if (newline)
4541                 *newline = '\0';
4542
4543         if (strcmp(tmp, "reset") == 0)
4544                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4545         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4546                 return -EINVAL;
4547
4548         if (new_threshold > 0)
4549                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4550                               new_threshold);
4551         else
4552                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4553
4554         spin_lock_irq(&dev_priv->irq_lock);
4555         hotplug->hpd_storm_threshold = new_threshold;
4556         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4557         for_each_hpd_pin(i)
4558                 hotplug->stats[i].count = 0;
4559         spin_unlock_irq(&dev_priv->irq_lock);
4560
4561         /* Re-enable hpd immediately if we were in an irq storm */
4562         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4563
4564         return len;
4565 }
4566
4567 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4568 {
4569         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4570 }
4571
4572 static const struct file_operations i915_hpd_storm_ctl_fops = {
4573         .owner = THIS_MODULE,
4574         .open = i915_hpd_storm_ctl_open,
4575         .read = seq_read,
4576         .llseek = seq_lseek,
4577         .release = single_release,
4578         .write = i915_hpd_storm_ctl_write
4579 };
4580
4581 static int i915_drrs_ctl_set(void *data, u64 val)
4582 {
4583         struct drm_i915_private *dev_priv = data;
4584         struct drm_device *dev = &dev_priv->drm;
4585         struct intel_crtc *intel_crtc;
4586         struct intel_encoder *encoder;
4587         struct intel_dp *intel_dp;
4588
4589         if (INTEL_GEN(dev_priv) < 7)
4590                 return -ENODEV;
4591
4592         drm_modeset_lock_all(dev);
4593         for_each_intel_crtc(dev, intel_crtc) {
4594                 if (!intel_crtc->base.state->active ||
4595                                         !intel_crtc->config->has_drrs)
4596                         continue;
4597
4598                 for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
4599                         if (encoder->type != INTEL_OUTPUT_EDP)
4600                                 continue;
4601
4602                         DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
4603                                                 val ? "en" : "dis", val);
4604
4605                         intel_dp = enc_to_intel_dp(&encoder->base);
4606                         if (val)
4607                                 intel_edp_drrs_enable(intel_dp,
4608                                                         intel_crtc->config);
4609                         else
4610                                 intel_edp_drrs_disable(intel_dp,
4611                                                         intel_crtc->config);
4612                 }
4613         }
4614         drm_modeset_unlock_all(dev);
4615
4616         return 0;
4617 }
4618
4619 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
4620
4621 static ssize_t
4622 i915_fifo_underrun_reset_write(struct file *filp,
4623                                const char __user *ubuf,
4624                                size_t cnt, loff_t *ppos)
4625 {
4626         struct drm_i915_private *dev_priv = filp->private_data;
4627         struct intel_crtc *intel_crtc;
4628         struct drm_device *dev = &dev_priv->drm;
4629         int ret;
4630         bool reset;
4631
4632         ret = kstrtobool_from_user(ubuf, cnt, &reset);
4633         if (ret)
4634                 return ret;
4635
4636         if (!reset)
4637                 return cnt;
4638
4639         for_each_intel_crtc(dev, intel_crtc) {
4640                 struct drm_crtc_commit *commit;
4641                 struct intel_crtc_state *crtc_state;
4642
4643                 ret = drm_modeset_lock_single_interruptible(&intel_crtc->base.mutex);
4644                 if (ret)
4645                         return ret;
4646
4647                 crtc_state = to_intel_crtc_state(intel_crtc->base.state);
4648                 commit = crtc_state->base.commit;
4649                 if (commit) {
4650                         ret = wait_for_completion_interruptible(&commit->hw_done);
4651                         if (!ret)
4652                                 ret = wait_for_completion_interruptible(&commit->flip_done);
4653                 }
4654
4655                 if (!ret && crtc_state->base.active) {
4656                         DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
4657                                       pipe_name(intel_crtc->pipe));
4658
4659                         intel_crtc_arm_fifo_underrun(intel_crtc, crtc_state);
4660                 }
4661
4662                 drm_modeset_unlock(&intel_crtc->base.mutex);
4663
4664                 if (ret)
4665                         return ret;
4666         }
4667
4668         ret = intel_fbc_reset_underrun(dev_priv);
4669         if (ret)
4670                 return ret;
4671
4672         return cnt;
4673 }
4674
4675 static const struct file_operations i915_fifo_underrun_reset_ops = {
4676         .owner = THIS_MODULE,
4677         .open = simple_open,
4678         .write = i915_fifo_underrun_reset_write,
4679         .llseek = default_llseek,
4680 };
4681
4682 static const struct drm_info_list i915_debugfs_list[] = {
4683         {"i915_capabilities", i915_capabilities, 0},
4684         {"i915_gem_objects", i915_gem_object_info, 0},
4685         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4686         {"i915_gem_stolen", i915_gem_stolen_list_info },
4687         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4688         {"i915_gem_interrupt", i915_interrupt_info, 0},
4689         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4690         {"i915_guc_info", i915_guc_info, 0},
4691         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4692         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4693         {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4694         {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4695         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4696         {"i915_frequency_info", i915_frequency_info, 0},
4697         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4698         {"i915_reset_info", i915_reset_info, 0},
4699         {"i915_drpc_info", i915_drpc_info, 0},
4700         {"i915_emon_status", i915_emon_status, 0},
4701         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4702         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4703         {"i915_fbc_status", i915_fbc_status, 0},
4704         {"i915_ips_status", i915_ips_status, 0},
4705         {"i915_sr_status", i915_sr_status, 0},
4706         {"i915_opregion", i915_opregion, 0},
4707         {"i915_vbt", i915_vbt, 0},
4708         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4709         {"i915_context_status", i915_context_status, 0},
4710         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4711         {"i915_swizzle_info", i915_swizzle_info, 0},
4712         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4713         {"i915_llc", i915_llc, 0},
4714         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4715         {"i915_energy_uJ", i915_energy_uJ, 0},
4716         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4717         {"i915_power_domain_info", i915_power_domain_info, 0},
4718         {"i915_dmc_info", i915_dmc_info, 0},
4719         {"i915_display_info", i915_display_info, 0},
4720         {"i915_engine_info", i915_engine_info, 0},
4721         {"i915_rcs_topology", i915_rcs_topology, 0},
4722         {"i915_shrinker_info", i915_shrinker_info, 0},
4723         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4724         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4725         {"i915_wa_registers", i915_wa_registers, 0},
4726         {"i915_ddb_info", i915_ddb_info, 0},
4727         {"i915_sseu_status", i915_sseu_status, 0},
4728         {"i915_drrs_status", i915_drrs_status, 0},
4729         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4730 };
4731 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4732
4733 static const struct i915_debugfs_files {
4734         const char *name;
4735         const struct file_operations *fops;
4736 } i915_debugfs_files[] = {
4737         {"i915_wedged", &i915_wedged_fops},
4738         {"i915_cache_sharing", &i915_cache_sharing_fops},
4739         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4740         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4741         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4742 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4743         {"i915_error_state", &i915_error_state_fops},
4744         {"i915_gpu_info", &i915_gpu_info_fops},
4745 #endif
4746         {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
4747         {"i915_next_seqno", &i915_next_seqno_fops},
4748         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4749         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4750         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4751         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4752         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4753         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4754         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4755         {"i915_guc_log_level", &i915_guc_log_level_fops},
4756         {"i915_guc_log_relay", &i915_guc_log_relay_fops},
4757         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4758         {"i915_ipc_status", &i915_ipc_status_fops},
4759         {"i915_drrs_ctl", &i915_drrs_ctl_fops},
4760         {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}
4761 };
4762
4763 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4764 {
4765         struct drm_minor *minor = dev_priv->drm.primary;
4766         struct dentry *ent;
4767         int i;
4768
4769         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4770                                   minor->debugfs_root, to_i915(minor->dev),
4771                                   &i915_forcewake_fops);
4772         if (!ent)
4773                 return -ENOMEM;
4774
4775         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4776                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4777                                           S_IRUGO | S_IWUSR,
4778                                           minor->debugfs_root,
4779                                           to_i915(minor->dev),
4780                                           i915_debugfs_files[i].fops);
4781                 if (!ent)
4782                         return -ENOMEM;
4783         }
4784
4785         return drm_debugfs_create_files(i915_debugfs_list,
4786                                         I915_DEBUGFS_ENTRIES,
4787                                         minor->debugfs_root, minor);
4788 }
4789
4790 struct dpcd_block {
4791         /* DPCD dump start address. */
4792         unsigned int offset;
4793         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4794         unsigned int end;
4795         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4796         size_t size;
4797         /* Only valid for eDP. */
4798         bool edp;
4799 };
4800
4801 static const struct dpcd_block i915_dpcd_debug[] = {
4802         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4803         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4804         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4805         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4806         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4807         { .offset = DP_SET_POWER },
4808         { .offset = DP_EDP_DPCD_REV },
4809         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4810         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4811         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4812 };
4813
4814 static int i915_dpcd_show(struct seq_file *m, void *data)
4815 {
4816         struct drm_connector *connector = m->private;
4817         struct intel_dp *intel_dp =
4818                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4819         uint8_t buf[16];
4820         ssize_t err;
4821         int i;
4822
4823         if (connector->status != connector_status_connected)
4824                 return -ENODEV;
4825
4826         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4827                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4828                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4829
4830                 if (b->edp &&
4831                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4832                         continue;
4833
4834                 /* low tech for now */
4835                 if (WARN_ON(size > sizeof(buf)))
4836                         continue;
4837
4838                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4839                 if (err <= 0) {
4840                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4841                                   size, b->offset, err);
4842                         continue;
4843                 }
4844
4845                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4846         }
4847
4848         return 0;
4849 }
4850 DEFINE_SHOW_ATTRIBUTE(i915_dpcd);
4851
4852 static int i915_panel_show(struct seq_file *m, void *data)
4853 {
4854         struct drm_connector *connector = m->private;
4855         struct intel_dp *intel_dp =
4856                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4857
4858         if (connector->status != connector_status_connected)
4859                 return -ENODEV;
4860
4861         seq_printf(m, "Panel power up delay: %d\n",
4862                    intel_dp->panel_power_up_delay);
4863         seq_printf(m, "Panel power down delay: %d\n",
4864                    intel_dp->panel_power_down_delay);
4865         seq_printf(m, "Backlight on delay: %d\n",
4866                    intel_dp->backlight_on_delay);
4867         seq_printf(m, "Backlight off delay: %d\n",
4868                    intel_dp->backlight_off_delay);
4869
4870         return 0;
4871 }
4872 DEFINE_SHOW_ATTRIBUTE(i915_panel);
4873
4874 /**
4875  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4876  * @connector: pointer to a registered drm_connector
4877  *
4878  * Cleanup will be done by drm_connector_unregister() through a call to
4879  * drm_debugfs_connector_remove().
4880  *
4881  * Returns 0 on success, negative error codes on error.
4882  */
4883 int i915_debugfs_connector_add(struct drm_connector *connector)
4884 {
4885         struct dentry *root = connector->debugfs_entry;
4886
4887         /* The connector must have been registered beforehands. */
4888         if (!root)
4889                 return -ENODEV;
4890
4891         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4892             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4893                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4894                                     connector, &i915_dpcd_fops);
4895
4896         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
4897                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4898                                     connector, &i915_panel_fops);
4899                 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root,
4900                                     connector, &i915_psr_sink_status_fops);
4901         }
4902
4903         return 0;
4904 }