2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
38 #include <linux/kthread.h>
40 #define RING_CTX_OFF(x) \
41 offsetof(struct execlist_ring_context, x)
43 void set_context_pdp_root_pointer(struct execlist_ring_context *ring_context,
46 struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
49 for (i = 0; i < 8; i++)
50 pdp_pair[i].val = pdp[7 - i];
53 static int populate_shadow_context(struct intel_vgpu_workload *workload)
55 struct intel_vgpu *vgpu = workload->vgpu;
56 struct intel_gvt *gvt = vgpu->gvt;
57 int ring_id = workload->ring_id;
58 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
59 struct drm_i915_gem_object *ctx_obj =
60 shadow_ctx->engine[ring_id].state->obj;
61 struct execlist_ring_context *shadow_ring_context;
64 unsigned long context_gpa, context_page_num;
67 gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
68 workload->ctx_desc.lrca);
70 context_page_num = intel_lr_context_size(
71 &gvt->dev_priv->engine[ring_id]);
73 context_page_num = context_page_num >> PAGE_SHIFT;
75 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
76 context_page_num = 19;
80 while (i < context_page_num) {
81 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
82 (u32)((workload->ctx_desc.lrca + i) <<
84 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
85 gvt_err("Invalid guest context descriptor\n");
89 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
90 dst = kmap_atomic(page);
91 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
97 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
98 shadow_ring_context = kmap_atomic(page);
100 #define COPY_REG(name) \
101 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
102 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
105 COPY_REG(ctx_timestamp);
107 if (ring_id == RCS) {
108 COPY_REG(bb_per_ctx_ptr);
109 COPY_REG(rcs_indirect_ctx);
110 COPY_REG(rcs_indirect_ctx_offset);
114 set_context_pdp_root_pointer(shadow_ring_context,
115 workload->shadow_mm->shadow_page_table);
117 intel_gvt_hypervisor_read_gpa(vgpu,
118 workload->ring_context_gpa +
119 sizeof(*shadow_ring_context),
120 (void *)shadow_ring_context +
121 sizeof(*shadow_ring_context),
122 GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
124 kunmap_atomic(shadow_ring_context);
128 static int shadow_context_status_change(struct notifier_block *nb,
129 unsigned long action, void *data)
131 struct intel_vgpu *vgpu = container_of(nb,
132 struct intel_vgpu, shadow_ctx_notifier_block);
133 struct drm_i915_gem_request *req =
134 (struct drm_i915_gem_request *)data;
135 struct intel_gvt_workload_scheduler *scheduler =
136 &vgpu->gvt->scheduler;
137 struct intel_vgpu_workload *workload =
138 scheduler->current_workload[req->engine->id];
141 case INTEL_CONTEXT_SCHEDULE_IN:
142 intel_gvt_load_render_mmio(workload->vgpu,
144 atomic_set(&workload->shadow_ctx_active, 1);
146 case INTEL_CONTEXT_SCHEDULE_OUT:
147 intel_gvt_restore_render_mmio(workload->vgpu,
149 atomic_set(&workload->shadow_ctx_active, 0);
155 wake_up(&workload->shadow_ctx_status_wq);
159 static int dispatch_workload(struct intel_vgpu_workload *workload)
161 struct intel_vgpu *vgpu = workload->vgpu;
162 struct intel_gvt *gvt = vgpu->gvt;
163 int ring_id = workload->ring_id;
164 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
165 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
168 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
171 shadow_ctx->desc_template = workload->ctx_desc.addressing_mode <<
172 GEN8_CTX_ADDRESSING_MODE_SHIFT;
174 workload->req = i915_gem_request_alloc(&dev_priv->engine[ring_id],
176 if (IS_ERR_OR_NULL(workload->req)) {
177 gvt_err("fail to allocate gem request\n");
178 workload->status = PTR_ERR(workload->req);
179 workload->req = NULL;
180 return workload->status;
183 gvt_dbg_sched("ring id %d get i915 gem request %p\n",
184 ring_id, workload->req);
186 mutex_lock(&gvt->lock);
188 ret = intel_gvt_scan_and_shadow_workload(workload);
192 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
196 ret = populate_shadow_context(workload);
200 if (workload->prepare) {
201 ret = workload->prepare(workload);
206 mutex_unlock(&gvt->lock);
208 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
209 ring_id, workload->req);
211 i915_add_request_no_flush(workload->req);
213 workload->dispatched = true;
216 workload->status = ret;
218 workload->req = NULL;
220 mutex_unlock(&gvt->lock);
224 static struct intel_vgpu_workload *pick_next_workload(
225 struct intel_gvt *gvt, int ring_id)
227 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
228 struct intel_vgpu_workload *workload = NULL;
230 mutex_lock(&gvt->lock);
233 * no current vgpu / will be scheduled out / no workload
236 if (!scheduler->current_vgpu) {
237 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
241 if (scheduler->need_reschedule) {
242 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
246 if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) {
247 gvt_dbg_sched("ring id %d stop - no available workload\n",
253 * still have current workload, maybe the workload disptacher
254 * fail to submit it for some reason, resubmit it.
256 if (scheduler->current_workload[ring_id]) {
257 workload = scheduler->current_workload[ring_id];
258 gvt_dbg_sched("ring id %d still have current workload %p\n",
264 * pick a workload as current workload
265 * once current workload is set, schedule policy routines
266 * will wait the current workload is finished when trying to
267 * schedule out a vgpu.
269 scheduler->current_workload[ring_id] = container_of(
270 workload_q_head(scheduler->current_vgpu, ring_id)->next,
271 struct intel_vgpu_workload, list);
273 workload = scheduler->current_workload[ring_id];
275 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
277 atomic_inc(&workload->vgpu->running_workload_num);
279 mutex_unlock(&gvt->lock);
283 static void update_guest_context(struct intel_vgpu_workload *workload)
285 struct intel_vgpu *vgpu = workload->vgpu;
286 struct intel_gvt *gvt = vgpu->gvt;
287 int ring_id = workload->ring_id;
288 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
289 struct drm_i915_gem_object *ctx_obj =
290 shadow_ctx->engine[ring_id].state->obj;
291 struct execlist_ring_context *shadow_ring_context;
294 unsigned long context_gpa, context_page_num;
297 gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
298 workload->ctx_desc.lrca);
300 context_page_num = intel_lr_context_size(
301 &gvt->dev_priv->engine[ring_id]);
303 context_page_num = context_page_num >> PAGE_SHIFT;
305 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
306 context_page_num = 19;
310 while (i < context_page_num) {
311 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
312 (u32)((workload->ctx_desc.lrca + i) <<
314 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
315 gvt_err("invalid guest context descriptor\n");
319 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
320 src = kmap_atomic(page);
321 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
327 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
328 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
330 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
331 shadow_ring_context = kmap_atomic(page);
333 #define COPY_REG(name) \
334 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
335 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
338 COPY_REG(ctx_timestamp);
342 intel_gvt_hypervisor_write_gpa(vgpu,
343 workload->ring_context_gpa +
344 sizeof(*shadow_ring_context),
345 (void *)shadow_ring_context +
346 sizeof(*shadow_ring_context),
347 GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
349 kunmap_atomic(shadow_ring_context);
352 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
354 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
355 struct intel_vgpu_workload *workload;
358 mutex_lock(&gvt->lock);
360 workload = scheduler->current_workload[ring_id];
362 if (!workload->status && !workload->vgpu->resetting) {
363 wait_event(workload->shadow_ctx_status_wq,
364 !atomic_read(&workload->shadow_ctx_active));
366 update_guest_context(workload);
368 for_each_set_bit(event, workload->pending_events,
370 intel_vgpu_trigger_virtual_event(workload->vgpu,
374 gvt_dbg_sched("ring id %d complete workload %p status %d\n",
375 ring_id, workload, workload->status);
377 scheduler->current_workload[ring_id] = NULL;
379 atomic_dec(&workload->vgpu->running_workload_num);
381 list_del_init(&workload->list);
382 workload->complete(workload);
384 wake_up(&scheduler->workload_complete_wq);
385 mutex_unlock(&gvt->lock);
388 struct workload_thread_param {
389 struct intel_gvt *gvt;
393 static int workload_thread(void *priv)
395 struct workload_thread_param *p = (struct workload_thread_param *)priv;
396 struct intel_gvt *gvt = p->gvt;
397 int ring_id = p->ring_id;
398 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
399 struct intel_vgpu_workload *workload = NULL;
401 bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
405 gvt_dbg_core("workload thread for ring %d started\n", ring_id);
407 while (!kthread_should_stop()) {
408 ret = wait_event_interruptible(scheduler->waitq[ring_id],
409 kthread_should_stop() ||
410 (workload = pick_next_workload(gvt, ring_id)));
414 if (kthread_should_stop())
417 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
418 workload->ring_id, workload,
421 intel_runtime_pm_get(gvt->dev_priv);
424 * Always take i915 big lock first
426 ret = i915_mutex_lock_interruptible(&gvt->dev_priv->drm);
428 gvt_err("i915 submission is not available, retry\n");
433 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
434 workload->ring_id, workload);
437 intel_uncore_forcewake_get(gvt->dev_priv,
440 ret = dispatch_workload(workload);
442 gvt_err("fail to dispatch workload, skip\n");
446 gvt_dbg_sched("ring id %d wait workload %p\n",
447 workload->ring_id, workload);
449 workload->status = i915_wait_request(workload->req,
450 I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
452 if (workload->status != 0)
453 gvt_err("fail to wait workload, skip\n");
456 gvt_dbg_sched("will complete workload %p\n, status: %d\n",
457 workload, workload->status);
459 complete_current_workload(gvt, ring_id);
462 intel_uncore_forcewake_put(gvt->dev_priv,
465 mutex_unlock(&gvt->dev_priv->drm.struct_mutex);
467 intel_runtime_pm_put(gvt->dev_priv);
472 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
474 struct intel_gvt *gvt = vgpu->gvt;
475 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
477 if (atomic_read(&vgpu->running_workload_num)) {
478 gvt_dbg_sched("wait vgpu idle\n");
480 wait_event(scheduler->workload_complete_wq,
481 !atomic_read(&vgpu->running_workload_num));
485 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
487 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
490 gvt_dbg_core("clean workload scheduler\n");
492 for (i = 0; i < I915_NUM_ENGINES; i++) {
493 if (scheduler->thread[i]) {
494 kthread_stop(scheduler->thread[i]);
495 scheduler->thread[i] = NULL;
500 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
502 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
503 struct workload_thread_param *param = NULL;
507 gvt_dbg_core("init workload scheduler\n");
509 init_waitqueue_head(&scheduler->workload_complete_wq);
511 for (i = 0; i < I915_NUM_ENGINES; i++) {
512 init_waitqueue_head(&scheduler->waitq[i]);
514 param = kzalloc(sizeof(*param), GFP_KERNEL);
523 scheduler->thread[i] = kthread_run(workload_thread, param,
524 "gvt workload %d", i);
525 if (IS_ERR(scheduler->thread[i])) {
526 gvt_err("fail to create workload thread\n");
527 ret = PTR_ERR(scheduler->thread[i]);
533 intel_gvt_clean_workload_scheduler(gvt);
539 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
541 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
543 atomic_notifier_chain_unregister(&vgpu->shadow_ctx->status_notifier,
544 &vgpu->shadow_ctx_notifier_block);
546 mutex_lock(&dev_priv->drm.struct_mutex);
548 /* a little hacky to mark as ctx closed */
549 vgpu->shadow_ctx->closed = true;
550 i915_gem_context_put(vgpu->shadow_ctx);
552 mutex_unlock(&dev_priv->drm.struct_mutex);
555 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
557 atomic_set(&vgpu->running_workload_num, 0);
559 vgpu->shadow_ctx = i915_gem_context_create_gvt(
560 &vgpu->gvt->dev_priv->drm);
561 if (IS_ERR(vgpu->shadow_ctx))
562 return PTR_ERR(vgpu->shadow_ctx);
564 vgpu->shadow_ctx->engine[RCS].initialised = true;
566 vgpu->shadow_ctx_notifier_block.notifier_call =
567 shadow_context_status_change;
569 atomic_notifier_chain_register(&vgpu->shadow_ctx->status_notifier,
570 &vgpu->shadow_ctx_notifier_block);