drivers/gpu/drm/i915/gvt/display.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  26  *
  27  * Contributors:
  28  *    Terrence Xu <terrence.xu@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Bing Niu <bing.niu@intel.com>
  31  *    Zhi Wang <zhi.a.wang@intel.com>
  32  *
  33  */
  34
  35 #include "i915_drv.h"
  36 #include "gvt.h"
  37
  38 static int get_edp_pipe(struct intel_vgpu *vgpu)
  39 {
  40         u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
  41         int pipe = -1;
  42
  43         switch (data & TRANS_DDI_EDP_INPUT_MASK) {
  44         case TRANS_DDI_EDP_INPUT_A_ON:
  45         case TRANS_DDI_EDP_INPUT_A_ONOFF:
  46                 pipe = PIPE_A;
  47                 break;
  48         case TRANS_DDI_EDP_INPUT_B_ONOFF:
  49                 pipe = PIPE_B;
  50                 break;
  51         case TRANS_DDI_EDP_INPUT_C_ONOFF:
  52                 pipe = PIPE_C;
  53                 break;
  54         }
  55         return pipe;
  56 }
  57
  58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
  59 {
  60         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
  61
  62         if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
  63                 return 0;
  64
  65         if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
  66                 return 0;
  67         return 1;
  68 }
  69
  70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
  71 {
  72         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
  73
  74         if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
  75                 return -EINVAL;
  76
  77         if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
  78                 return 1;
  79
  80         if (edp_pipe_is_enabled(vgpu) &&
  81                         get_edp_pipe(vgpu) == pipe)
  82                 return 1;
  83         return 0;
  84 }
  85
  86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
  87         {
  88 /* EDID with 1024x768 as its resolution */
  89                 /*Header*/
  90                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
  91                 /* Vendor & Product Identification */
  92                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
  93                 /* Version & Revision */
  94                 0x01, 0x04,
  95                 /* Basic Display Parameters & Features */
  96                 0xa5, 0x34, 0x20, 0x78, 0x23,
  97                 /* Color Characteristics */
  98                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
  99                 /* Established Timings: maximum resolution is 1024x768 */
 100                 0x21, 0x08, 0x00,
 101                 /* Standard Timings. All invalid */
 102                 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
 103                 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
 104                 /* 18 Byte Data Blocks 1: invalid */
 105                 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
 106                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
 107                 /* 18 Byte Data Blocks 2: invalid */
 108                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
 109                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 110                 /* 18 Byte Data Blocks 3: invalid */
 111                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
 112                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
 113                 /* 18 Byte Data Blocks 4: invalid */
 114                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
 115                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
 116                 /* Extension Block Count */
 117                 0x00,
 118                 /* Checksum */
 119                 0xef,
 120         },
 121         {
 122 /* EDID with 1920x1200 as its resolution */
 123                 /*Header*/
 124                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
 125                 /* Vendor & Product Identification */
 126                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
 127                 /* Version & Revision */
 128                 0x01, 0x04,
 129                 /* Basic Display Parameters & Features */
 130                 0xa5, 0x34, 0x20, 0x78, 0x23,
 131                 /* Color Characteristics */
 132                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
 133                 /* Established Timings: maximum resolution is 1024x768 */
 134                 0x21, 0x08, 0x00,
 135                 /*
 136                  * Standard Timings.
 137                  * below new resolutions can be supported:
 138                  * 1920x1080, 1280x720, 1280x960, 1280x1024,
 139                  * 1440x900, 1600x1200, 1680x1050
 140                  */
 141                 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
 142                 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
 143                 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
 144                 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
 145                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
 146                 /* 18 Byte Data Blocks 2: invalid */
 147                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
 148                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 149                 /* 18 Byte Data Blocks 3: invalid */
 150                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
 151                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
 152                 /* 18 Byte Data Blocks 4: invalid */
 153                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
 154                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
 155                 /* Extension Block Count */
 156                 0x00,
 157                 /* Checksum */
 158                 0x45,
 159         },
 160 };
 161
 162 #define DPCD_HEADER_SIZE        0xb
 163
 164 /* let the virtual display supports DP1.2 */
 165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
 166         0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 167 };
 168
 169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 170 {
 171         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 172         int pipe;
 173
 174         vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
 175                         SDE_PORTC_HOTPLUG_CPT |
 176                         SDE_PORTD_HOTPLUG_CPT);
 177
 178         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 179                 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
 180                                 SDE_PORTE_HOTPLUG_SPT);
 181                 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
 182                                 SKL_FUSE_DOWNLOAD_STATUS |
 183                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
 184                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
 185                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
 186                 vgpu_vreg_t(vgpu, LCPLL1_CTL) |=
 187                                 LCPLL_PLL_ENABLE |
 188                                 LCPLL_PLL_LOCK;
 189                 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
 190
 191         }
 192
 193         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 194                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
 195                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 196                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 197                         TRANS_DDI_PORT_MASK);
 198                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 199                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
 200                         (PORT_B << TRANS_DDI_PORT_SHIFT) |
 201                         TRANS_DDI_FUNC_ENABLE);
 202                 if (IS_BROADWELL(dev_priv)) {
 203                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
 204                                 ~PORT_CLK_SEL_MASK;
 205                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
 206                                 PORT_CLK_SEL_LCPLL_810;
 207                 }
 208                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
 209                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
 210                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
 211         }
 212
 213         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 214                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
 215                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 216                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 217                         TRANS_DDI_PORT_MASK);
 218                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 219                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
 220                         (PORT_C << TRANS_DDI_PORT_SHIFT) |
 221                         TRANS_DDI_FUNC_ENABLE);
 222                 if (IS_BROADWELL(dev_priv)) {
 223                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
 224                                 ~PORT_CLK_SEL_MASK;
 225                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
 226                                 PORT_CLK_SEL_LCPLL_810;
 227                 }
 228                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
 229                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
 230                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
 231         }
 232
 233         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
 234                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
 235                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 236                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 237                         TRANS_DDI_PORT_MASK);
 238                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 239                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
 240                         (PORT_D << TRANS_DDI_PORT_SHIFT) |
 241                         TRANS_DDI_FUNC_ENABLE);
 242                 if (IS_BROADWELL(dev_priv)) {
 243                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
 244                                 ~PORT_CLK_SEL_MASK;
 245                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
 246                                 PORT_CLK_SEL_LCPLL_810;
 247                 }
 248                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
 249                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
 250                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
 251         }
 252
 253         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 254                         intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
 255                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
 256         }
 257
 258         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 259                 if (IS_BROADWELL(dev_priv))
 260                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 261                                 GEN8_PORT_DP_A_HOTPLUG;
 262                 else
 263                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 264
 265                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
 266         }
 267
 268         /* Clear host CRT status, so guest couldn't detect this host CRT. */
 269         if (IS_BROADWELL(dev_priv))
 270                 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
 271
 272         /* Disable Primary/Sprite/Cursor plane */
 273         for_each_pipe(dev_priv, pipe) {
 274                 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
 275                 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
 276                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~CURSOR_MODE;
 277                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= CURSOR_MODE_DISABLE;
 278         }
 279
 280         vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
 281 }
 282
 283 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
 284 {
 285         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 286
 287         kfree(port->edid);
 288         port->edid = NULL;
 289
 290         kfree(port->dpcd);
 291         port->dpcd = NULL;
 292 }
 293
 294 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
 295                                     int type, unsigned int resolution)
 296 {
 297         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 298
 299         if (WARN_ON(resolution >= GVT_EDID_NUM))
 300                 return -EINVAL;
 301
 302         port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
 303         if (!port->edid)
 304                 return -ENOMEM;
 305
 306         port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
 307         if (!port->dpcd) {
 308                 kfree(port->edid);
 309                 return -ENOMEM;
 310         }
 311
 312         memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
 313                         EDID_SIZE);
 314         port->edid->data_valid = true;
 315
 316         memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
 317         port->dpcd->data_valid = true;
 318         port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
 319         port->type = type;
 320
 321         emulate_monitor_status_change(vgpu);
 322
 323         return 0;
 324 }
 325
 326 /**
 327  * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
 328  * be turned on/off when a virtual pipe is enabled/disabled.
 329  * @gvt: a GVT device
 330  *
 331  * This function is used to turn on/off vblank timer according to currently
 332  * enabled/disabled virtual pipes.
 333  *
 334  */
 335 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
 336 {
 337         struct intel_gvt_irq *irq = &gvt->irq;
 338         struct intel_vgpu *vgpu;
 339         int pipe, id;
 340
 341         if (WARN_ON(!mutex_is_locked(&gvt->lock)))
 342                 return;
 343
 344         for_each_active_vgpu(gvt, vgpu, id) {
 345                 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
 346                         if (pipe_is_enabled(vgpu, pipe))
 347                                 goto out;
 348                 }
 349         }
 350
 351         /* all the pipes are disabled */
 352         hrtimer_cancel(&irq->vblank_timer.timer);
 353         return;
 354
 355 out:
 356         hrtimer_start(&irq->vblank_timer.timer,
 357                 ktime_add_ns(ktime_get(), irq->vblank_timer.period),
 358                 HRTIMER_MODE_ABS);
 359
 360 }
 361
 362 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
 363 {
 364         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 365         struct intel_vgpu_irq *irq = &vgpu->irq;
 366         int vblank_event[] = {
 367                 [PIPE_A] = PIPE_A_VBLANK,
 368                 [PIPE_B] = PIPE_B_VBLANK,
 369                 [PIPE_C] = PIPE_C_VBLANK,
 370         };
 371         int event;
 372
 373         if (pipe < PIPE_A || pipe > PIPE_C)
 374                 return;
 375
 376         for_each_set_bit(event, irq->flip_done_event[pipe],
 377                         INTEL_GVT_EVENT_MAX) {
 378                 clear_bit(event, irq->flip_done_event[pipe]);
 379                 if (!pipe_is_enabled(vgpu, pipe))
 380                         continue;
 381
 382                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
 383                 intel_vgpu_trigger_virtual_event(vgpu, event);
 384         }
 385
 386         if (pipe_is_enabled(vgpu, pipe)) {
 387                 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
 388                 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
 389         }
 390 }
 391
 392 static void emulate_vblank(struct intel_vgpu *vgpu)
 393 {
 394         int pipe;
 395
 396         for_each_pipe(vgpu->gvt->dev_priv, pipe)
 397                 emulate_vblank_on_pipe(vgpu, pipe);
 398 }
 399
 400 /**
 401  * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
 402  * @gvt: a GVT device
 403  *
 404  * This function is used to trigger vblank interrupts for vGPUs on GVT device
 405  *
 406  */
 407 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
 408 {
 409         struct intel_vgpu *vgpu;
 410         int id;
 411
 412         if (WARN_ON(!mutex_is_locked(&gvt->lock)))
 413                 return;
 414
 415         for_each_active_vgpu(gvt, vgpu, id)
 416                 emulate_vblank(vgpu);
 417 }
 418
 419 /**
 420  * intel_vgpu_clean_display - clean vGPU virtual display emulation
 421  * @vgpu: a vGPU
 422  *
 423  * This function is used to clean vGPU virtual display emulation stuffs
 424  *
 425  */
 426 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
 427 {
 428         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 429
 430         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 431                 clean_virtual_dp_monitor(vgpu, PORT_D);
 432         else
 433                 clean_virtual_dp_monitor(vgpu, PORT_B);
 434 }
 435
 436 /**
 437  * intel_vgpu_init_display- initialize vGPU virtual display emulation
 438  * @vgpu: a vGPU
 439  *
 440  * This function is used to initialize vGPU virtual display emulation stuffs
 441  *
 442  * Returns:
 443  * Zero on success, negative error code if failed.
 444  *
 445  */
 446 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
 447 {
 448         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 449
 450         intel_vgpu_init_i2c_edid(vgpu);
 451
 452         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 453                 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
 454                                                 resolution);
 455         else
 456                 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
 457                                                 resolution);
 458 }
 459
 460 /**
 461  * intel_vgpu_reset_display- reset vGPU virtual display emulation
 462  * @vgpu: a vGPU
 463  *
 464  * This function is used to reset vGPU virtual display emulation stuffs
 465  *
 466  */
 467 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
 468 {
 469         emulate_monitor_status_change(vgpu);
 470 }