drivers/gpu/drm/i915/display/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drm_atomic_helper.h>
  25
  26 #include "display/intel_dp.h"
  27
  28 #include "i915_drv.h"
  29 #include "intel_atomic.h"
  30 #include "intel_display_types.h"
  31 #include "intel_psr.h"
  32 #include "intel_sprite.h"
  33 #include "intel_hdmi.h"
  34
  35 /**
  36  * DOC: Panel Self Refresh (PSR/SRD)
  37  *
  38  * Since Haswell Display controller supports Panel Self-Refresh on display
  39  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  40  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  41  * when system is idle but display is on as it eliminates display refresh
  42  * request to DDR memory completely as long as the frame buffer for that
  43  * display is unchanged.
  44  *
  45  * Panel Self Refresh must be supported by both Hardware (source) and
  46  * Panel (sink).
  47  *
  48  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  49  * to power down the link and memory controller. For DSI panels the same idea
  50  * is called "manual mode".
  51  *
  52  * The implementation uses the hardware-based PSR support which automatically
  53  * enters/exits self-refresh mode. The hardware takes care of sending the
  54  * required DP aux message and could even retrain the link (that part isn't
  55  * enabled yet though). The hardware also keeps track of any frontbuffer
  56  * changes to know when to exit self-refresh mode again. Unfortunately that
  57  * part doesn't work too well, hence why the i915 PSR support uses the
  58  * software frontbuffer tracking to make sure it doesn't miss a screen
  59  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  60  * get called by the frontbuffer tracking code. Note that because of locking
  61  * issues the self-refresh re-enable code is done from a work queue, which
  62  * must be correctly synchronized/cancelled when shutting down the pipe."
  63  *
  64  * DC3CO (DC3 clock off)
  65  *
  66  * On top of PSR2, GEN12 adds a intermediate power savings state that turns
  67  * clock off automatically during PSR2 idle state.
  68  * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
  69  * entry/exit allows the HW to enter a low-power state even when page flipping
  70  * periodically (for instance a 30fps video playback scenario).
  71  *
  72  * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
  73  * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
  74  * frames, if no other flip occurs and the function above is executed, DC3CO is
  75  * disabled and PSR2 is configured to enter deep sleep, resetting again in case
  76  * of another flip.
  77  * Front buffer modifications do not trigger DC3CO activation on purpose as it
  78  * would bring a lot of complexity and most of the moderns systems will only
  79  * use page flips.
  80  */
  81
  82 static bool psr_global_enabled(struct drm_i915_private *i915)
  83 {
  84         switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  85         case I915_PSR_DEBUG_DEFAULT:
  86                 return i915->params.enable_psr;
  87         case I915_PSR_DEBUG_DISABLE:
  88                 return false;
  89         default:
  90                 return true;
  91         }
  92 }
  93
  94 static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
  95 {
  96         switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  97         case I915_PSR_DEBUG_DISABLE:
  98         case I915_PSR_DEBUG_FORCE_PSR1:
  99                 return false;
 100         default:
 101                 return true;
 102         }
 103 }
 104
 105 static void psr_irq_control(struct drm_i915_private *dev_priv)
 106 {
 107         enum transcoder trans_shift;
 108         u32 mask, val;
 109         i915_reg_t imr_reg;
 110
 111         /*
 112          * gen12+ has registers relative to transcoder and one per transcoder
 113          * using the same bit definition: handle it as TRANSCODER_EDP to force
 114          * 0 shift in bit definition
 115          */
 116         if (INTEL_GEN(dev_priv) >= 12) {
 117                 trans_shift = 0;
 118                 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
 119         } else {
 120                 trans_shift = dev_priv->psr.transcoder;
 121                 imr_reg = EDP_PSR_IMR;
 122         }
 123
 124         mask = EDP_PSR_ERROR(trans_shift);
 125         if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
 126                 mask |= EDP_PSR_POST_EXIT(trans_shift) |
 127                         EDP_PSR_PRE_ENTRY(trans_shift);
 128
 129         /* Warning: it is masking/setting reserved bits too */
 130         val = intel_de_read(dev_priv, imr_reg);
 131         val &= ~EDP_PSR_TRANS_MASK(trans_shift);
 132         val |= ~mask;
 133         intel_de_write(dev_priv, imr_reg, val);
 134 }
 135
 136 static void psr_event_print(struct drm_i915_private *i915,
 137                             u32 val, bool psr2_enabled)
 138 {
 139         drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
 140         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 141                 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
 142         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 143                 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
 144         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 145                 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
 146         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 147                 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
 148         if (val & PSR_EVENT_GRAPHICS_RESET)
 149                 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
 150         if (val & PSR_EVENT_PCH_INTERRUPT)
 151                 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
 152         if (val & PSR_EVENT_MEMORY_UP)
 153                 drm_dbg_kms(&i915->drm, "\tMemory up\n");
 154         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 155                 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
 156         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 157                 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
 158         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 159                 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
 160         if (val & PSR_EVENT_REGISTER_UPDATE)
 161                 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
 162         if (val & PSR_EVENT_HDCP_ENABLE)
 163                 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
 164         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 165                 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
 166         if (val & PSR_EVENT_VBI_ENABLE)
 167                 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
 168         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 169                 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
 170         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 171                 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
 172 }
 173
 174 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 175 {
 176         enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
 177         enum transcoder trans_shift;
 178         i915_reg_t imr_reg;
 179         ktime_t time_ns =  ktime_get();
 180
 181         if (INTEL_GEN(dev_priv) >= 12) {
 182                 trans_shift = 0;
 183                 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
 184         } else {
 185                 trans_shift = dev_priv->psr.transcoder;
 186                 imr_reg = EDP_PSR_IMR;
 187         }
 188
 189         if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
 190                 dev_priv->psr.last_entry_attempt = time_ns;
 191                 drm_dbg_kms(&dev_priv->drm,
 192                             "[transcoder %s] PSR entry attempt in 2 vblanks\n",
 193                             transcoder_name(cpu_transcoder));
 194         }
 195
 196         if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
 197                 dev_priv->psr.last_exit = time_ns;
 198                 drm_dbg_kms(&dev_priv->drm,
 199                             "[transcoder %s] PSR exit completed\n",
 200                             transcoder_name(cpu_transcoder));
 201
 202                 if (INTEL_GEN(dev_priv) >= 9) {
 203                         u32 val = intel_de_read(dev_priv,
 204                                                 PSR_EVENT(cpu_transcoder));
 205                         bool psr2_enabled = dev_priv->psr.psr2_enabled;
 206
 207                         intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
 208                                        val);
 209                         psr_event_print(dev_priv, val, psr2_enabled);
 210                 }
 211         }
 212
 213         if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
 214                 u32 val;
 215
 216                 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
 217                          transcoder_name(cpu_transcoder));
 218
 219                 dev_priv->psr.irq_aux_error = true;
 220
 221                 /*
 222                  * If this interruption is not masked it will keep
 223                  * interrupting so fast that it prevents the scheduled
 224                  * work to run.
 225                  * Also after a PSR error, we don't want to arm PSR
 226                  * again so we don't care about unmask the interruption
 227                  * or unset irq_aux_error.
 228                  */
 229                 val = intel_de_read(dev_priv, imr_reg);
 230                 val |= EDP_PSR_ERROR(trans_shift);
 231                 intel_de_write(dev_priv, imr_reg, val);
 232
 233                 schedule_work(&dev_priv->psr.work);
 234         }
 235 }
 236
 237 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 238 {
 239         u8 alpm_caps = 0;
 240
 241         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 242                               &alpm_caps) != 1)
 243                 return false;
 244         return alpm_caps & DP_ALPM_CAP;
 245 }
 246
 247 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 248 {
 249         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 250         u8 val = 8; /* assume the worst if we can't read the value */
 251
 252         if (drm_dp_dpcd_readb(&intel_dp->aux,
 253                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 254                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 255         else
 256                 drm_dbg_kms(&i915->drm,
 257                             "Unable to get sink synchronization latency, assuming 8 frames\n");
 258         return val;
 259 }
 260
 261 static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
 262 {
 263         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 264         u16 val;
 265         ssize_t r;
 266
 267         /*
 268          * Returning the default X granularity if granularity not required or
 269          * if DPCD read fails
 270          */
 271         if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
 272                 return 4;
 273
 274         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
 275         if (r != 2)
 276                 drm_dbg_kms(&i915->drm,
 277                             "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
 278
 279         /*
 280          * Spec says that if the value read is 0 the default granularity should
 281          * be used instead.
 282          */
 283         if (r != 2 || val == 0)
 284                 val = 4;
 285
 286         return val;
 287 }
 288
 289 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 290 {
 291         struct drm_i915_private *dev_priv =
 292                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 293
 294         if (dev_priv->psr.dp) {
 295                 drm_warn(&dev_priv->drm,
 296                          "More than one eDP panel found, PSR support should be extended\n");
 297                 return;
 298         }
 299
 300         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 301                          sizeof(intel_dp->psr_dpcd));
 302
 303         if (!intel_dp->psr_dpcd[0])
 304                 return;
 305         drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
 306                     intel_dp->psr_dpcd[0]);
 307
 308         if (drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_NO_PSR)) {
 309                 drm_dbg_kms(&dev_priv->drm,
 310                             "PSR support not currently available for this panel\n");
 311                 return;
 312         }
 313
 314         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 315                 drm_dbg_kms(&dev_priv->drm,
 316                             "Panel lacks power state control, PSR cannot be enabled\n");
 317                 return;
 318         }
 319
 320         dev_priv->psr.sink_support = true;
 321         dev_priv->psr.sink_sync_latency =
 322                 intel_dp_get_sink_sync_latency(intel_dp);
 323
 324         dev_priv->psr.dp = intel_dp;
 325
 326         if (INTEL_GEN(dev_priv) >= 9 &&
 327             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 328                 bool y_req = intel_dp->psr_dpcd[1] &
 329                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 330                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 331
 332                 /*
 333                  * All panels that supports PSR version 03h (PSR2 +
 334                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 335                  * only sure that it is going to be used when required by the
 336                  * panel. This way panel is capable to do selective update
 337                  * without a aux frame sync.
 338                  *
 339                  * To support PSR version 02h and PSR version 03h without
 340                  * Y-coordinate requirement panels we would need to enable
 341                  * GTC first.
 342                  */
 343                 dev_priv->psr.sink_psr2_support = y_req && alpm;
 344                 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
 345                             dev_priv->psr.sink_psr2_support ? "" : "not ");
 346
 347                 if (dev_priv->psr.sink_psr2_support) {
 348                         dev_priv->psr.colorimetry_support =
 349                                 intel_dp_get_colorimetry_status(intel_dp);
 350                         dev_priv->psr.su_x_granularity =
 351                                 intel_dp_get_su_x_granulartiy(intel_dp);
 352                 }
 353         }
 354 }
 355
 356 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 357 {
 358         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 359         u32 aux_clock_divider, aux_ctl;
 360         int i;
 361         static const u8 aux_msg[] = {
 362                 [0] = DP_AUX_NATIVE_WRITE << 4,
 363                 [1] = DP_SET_POWER >> 8,
 364                 [2] = DP_SET_POWER & 0xff,
 365                 [3] = 1 - 1,
 366                 [4] = DP_SET_POWER_D0,
 367         };
 368         u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
 369                            EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
 370                            EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
 371                            EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 372
 373         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 374         for (i = 0; i < sizeof(aux_msg); i += 4)
 375                 intel_de_write(dev_priv,
 376                                EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2),
 377                                intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 378
 379         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 380
 381         /* Start with bits set for DDI_AUX_CTL register */
 382         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
 383                                              aux_clock_divider);
 384
 385         /* Select only valid bits for SRD_AUX_CTL */
 386         aux_ctl &= psr_aux_mask;
 387         intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder),
 388                        aux_ctl);
 389 }
 390
 391 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 392 {
 393         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 394         u8 dpcd_val = DP_PSR_ENABLE;
 395
 396         /* Enable ALPM at sink for psr2 */
 397         if (dev_priv->psr.psr2_enabled) {
 398                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 399                                    DP_ALPM_ENABLE |
 400                                    DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 401
 402                 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 403         } else {
 404                 if (dev_priv->psr.link_standby)
 405                         dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 406
 407                 if (INTEL_GEN(dev_priv) >= 8)
 408                         dpcd_val |= DP_PSR_CRC_VERIFICATION;
 409         }
 410
 411         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 412
 413         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 414 }
 415
 416 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 417 {
 418         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 419         u32 val = 0;
 420
 421         if (INTEL_GEN(dev_priv) >= 11)
 422                 val |= EDP_PSR_TP4_TIME_0US;
 423
 424         if (dev_priv->params.psr_safest_params) {
 425                 val |= EDP_PSR_TP1_TIME_2500us;
 426                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 427                 goto check_tp3_sel;
 428         }
 429
 430         if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
 431                 val |= EDP_PSR_TP1_TIME_0us;
 432         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 433                 val |= EDP_PSR_TP1_TIME_100us;
 434         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
 435                 val |= EDP_PSR_TP1_TIME_500us;
 436         else
 437                 val |= EDP_PSR_TP1_TIME_2500us;
 438
 439         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
 440                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 441         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 442                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 443         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 444                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 445         else
 446                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 447
 448 check_tp3_sel:
 449         if (intel_dp_source_supports_hbr2(intel_dp) &&
 450             drm_dp_tps3_supported(intel_dp->dpcd))
 451                 val |= EDP_PSR_TP1_TP3_SEL;
 452         else
 453                 val |= EDP_PSR_TP1_TP2_SEL;
 454
 455         return val;
 456 }
 457
 458 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 459 {
 460         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 461         int idle_frames;
 462
 463         /* Let's use 6 as the minimum to cover all known cases including the
 464          * off-by-one issue that HW has in some cases.
 465          */
 466         idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 467         idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 468
 469         if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
 470                 idle_frames = 0xf;
 471
 472         return idle_frames;
 473 }
 474
 475 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 476 {
 477         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 478         u32 max_sleep_time = 0x1f;
 479         u32 val = EDP_PSR_ENABLE;
 480
 481         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
 482
 483         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 484         if (IS_HASWELL(dev_priv))
 485                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 486
 487         if (dev_priv->psr.link_standby)
 488                 val |= EDP_PSR_LINK_STANDBY;
 489
 490         val |= intel_psr1_get_tp_time(intel_dp);
 491
 492         if (INTEL_GEN(dev_priv) >= 8)
 493                 val |= EDP_PSR_CRC_ENABLE;
 494
 495         val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) &
 496                 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
 497         intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val);
 498 }
 499
 500 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 501 {
 502         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 503         u32 val = 0;
 504
 505         if (dev_priv->params.psr_safest_params)
 506                 return EDP_PSR2_TP2_TIME_2500us;
 507
 508         if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
 509             dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 510                 val |= EDP_PSR2_TP2_TIME_50us;
 511         else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 512                 val |= EDP_PSR2_TP2_TIME_100us;
 513         else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 514                 val |= EDP_PSR2_TP2_TIME_500us;
 515         else
 516                 val |= EDP_PSR2_TP2_TIME_2500us;
 517
 518         return val;
 519 }
 520
 521 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 522 {
 523         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 524         u32 val;
 525
 526         val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 527
 528         val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 529         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 530                 val |= EDP_Y_COORDINATE_ENABLE;
 531
 532         val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 533         val |= intel_psr2_get_tp_time(intel_dp);
 534
 535         if (INTEL_GEN(dev_priv) >= 12) {
 536                 /*
 537                  * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 538                  * values from BSpec. In order to setting an optimal power
 539                  * consumption, lower than 4k resoluition mode needs to decrese
 540                  * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
 541                  * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
 542                  */
 543                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 544                 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
 545                 val |= TGL_EDP_PSR2_FAST_WAKE(7);
 546         } else if (INTEL_GEN(dev_priv) >= 9) {
 547                 val |= EDP_PSR2_IO_BUFFER_WAKE(7);
 548                 val |= EDP_PSR2_FAST_WAKE(7);
 549         }
 550
 551         if (dev_priv->psr.psr2_sel_fetch_enabled) {
 552                 /* WA 1408330847 */
 553                 if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
 554                     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
 555                         intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 556                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 557                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK);
 558
 559                 intel_de_write(dev_priv,
 560                                PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder),
 561                                PSR2_MAN_TRK_CTL_ENABLE);
 562         } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 563                 intel_de_write(dev_priv,
 564                                PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0);
 565         }
 566
 567         /*
 568          * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
 569          * recommending keep this bit unset while PSR2 is enabled.
 570          */
 571         intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0);
 572
 573         intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
 574 }
 575
 576 static bool
 577 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 578 {
 579         if (INTEL_GEN(dev_priv) < 9)
 580                 return false;
 581         else if (INTEL_GEN(dev_priv) >= 12)
 582                 return trans == TRANSCODER_A;
 583         else
 584                 return trans == TRANSCODER_EDP;
 585 }
 586
 587 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
 588 {
 589         if (!cstate || !cstate->hw.active)
 590                 return 0;
 591
 592         return DIV_ROUND_UP(1000 * 1000,
 593                             drm_mode_vrefresh(&cstate->hw.adjusted_mode));
 594 }
 595
 596 static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
 597                                      u32 idle_frames)
 598 {
 599         u32 val;
 600
 601         idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
 602         val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder));
 603         val &= ~EDP_PSR2_IDLE_FRAME_MASK;
 604         val |= idle_frames;
 605         intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
 606 }
 607
 608 static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv)
 609 {
 610         psr2_program_idle_frames(dev_priv, 0);
 611         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
 612 }
 613
 614 static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv)
 615 {
 616         struct intel_dp *intel_dp = dev_priv->psr.dp;
 617
 618         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 619         psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
 620 }
 621
 622 static void tgl_dc3co_disable_work(struct work_struct *work)
 623 {
 624         struct drm_i915_private *dev_priv =
 625                 container_of(work, typeof(*dev_priv), psr.dc3co_work.work);
 626
 627         mutex_lock(&dev_priv->psr.lock);
 628         /* If delayed work is pending, it is not idle */
 629         if (delayed_work_pending(&dev_priv->psr.dc3co_work))
 630                 goto unlock;
 631
 632         tgl_psr2_disable_dc3co(dev_priv);
 633 unlock:
 634         mutex_unlock(&dev_priv->psr.lock);
 635 }
 636
 637 static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
 638 {
 639         if (!dev_priv->psr.dc3co_enabled)
 640                 return;
 641
 642         cancel_delayed_work(&dev_priv->psr.dc3co_work);
 643         /* Before PSR2 exit disallow dc3co*/
 644         tgl_psr2_disable_dc3co(dev_priv);
 645 }
 646
 647 static void
 648 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 649                                   struct intel_crtc_state *crtc_state)
 650 {
 651         const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
 652         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 653         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 654         u32 exit_scanlines;
 655
 656         if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
 657                 return;
 658
 659         /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
 660         if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A ||
 661             dig_port->base.port != PORT_A)
 662                 return;
 663
 664         /*
 665          * DC3CO Exit time 200us B.Spec 49196
 666          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
 667          */
 668         exit_scanlines =
 669                 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
 670
 671         if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
 672                 return;
 673
 674         crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
 675 }
 676
 677 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 678                                               struct intel_crtc_state *crtc_state)
 679 {
 680         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
 681         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 682         struct intel_plane_state *plane_state;
 683         struct intel_plane *plane;
 684         int i;
 685
 686         if (!dev_priv->params.enable_psr2_sel_fetch) {
 687                 drm_dbg_kms(&dev_priv->drm,
 688                             "PSR2 sel fetch not enabled, disabled by parameter\n");
 689                 return false;
 690         }
 691
 692         if (crtc_state->uapi.async_flip) {
 693                 drm_dbg_kms(&dev_priv->drm,
 694                             "PSR2 sel fetch not enabled, async flip enabled\n");
 695                 return false;
 696         }
 697
 698         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 699                 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) {
 700                         drm_dbg_kms(&dev_priv->drm,
 701                                     "PSR2 sel fetch not enabled, plane rotated\n");
 702                         return false;
 703                 }
 704         }
 705
 706         return crtc_state->enable_psr2_sel_fetch = true;
 707 }
 708
 709 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 710                                     struct intel_crtc_state *crtc_state)
 711 {
 712         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 713         int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 714         int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 715         int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 716
 717         if (!dev_priv->psr.sink_psr2_support)
 718                 return false;
 719
 720         if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
 721                 drm_dbg_kms(&dev_priv->drm,
 722                             "PSR2 not supported in transcoder %s\n",
 723                             transcoder_name(crtc_state->cpu_transcoder));
 724                 return false;
 725         }
 726
 727         if (!psr2_global_enabled(dev_priv)) {
 728                 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
 729                 return false;
 730         }
 731
 732         /*
 733          * DSC and PSR2 cannot be enabled simultaneously. If a requested
 734          * resolution requires DSC to be enabled, priority is given to DSC
 735          * over PSR2.
 736          */
 737         if (crtc_state->dsc.compression_enable) {
 738                 drm_dbg_kms(&dev_priv->drm,
 739                             "PSR2 cannot be enabled since DSC is enabled\n");
 740                 return false;
 741         }
 742
 743         if (crtc_state->crc_enabled) {
 744                 drm_dbg_kms(&dev_priv->drm,
 745                             "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
 746                 return false;
 747         }
 748
 749         if (INTEL_GEN(dev_priv) >= 12) {
 750                 psr_max_h = 5120;
 751                 psr_max_v = 3200;
 752                 max_bpp = 30;
 753         } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 754                 psr_max_h = 4096;
 755                 psr_max_v = 2304;
 756                 max_bpp = 24;
 757         } else if (IS_GEN(dev_priv, 9)) {
 758                 psr_max_h = 3640;
 759                 psr_max_v = 2304;
 760                 max_bpp = 24;
 761         }
 762
 763         if (crtc_state->pipe_bpp > max_bpp) {
 764                 drm_dbg_kms(&dev_priv->drm,
 765                             "PSR2 not enabled, pipe bpp %d > max supported %d\n",
 766                             crtc_state->pipe_bpp, max_bpp);
 767                 return false;
 768         }
 769
 770         /*
 771          * HW sends SU blocks of size four scan lines, which means the starting
 772          * X coordinate and Y granularity requirements will always be met. We
 773          * only need to validate the SU block width is a multiple of
 774          * x granularity.
 775          */
 776         if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
 777                 drm_dbg_kms(&dev_priv->drm,
 778                             "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
 779                             crtc_hdisplay, dev_priv->psr.su_x_granularity);
 780                 return false;
 781         }
 782
 783         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 784                 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 785                     !HAS_PSR_HW_TRACKING(dev_priv)) {
 786                         drm_dbg_kms(&dev_priv->drm,
 787                                     "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
 788                         return false;
 789                 }
 790         }
 791
 792         if (!crtc_state->enable_psr2_sel_fetch &&
 793             (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
 794                 drm_dbg_kms(&dev_priv->drm,
 795                             "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 796                             crtc_hdisplay, crtc_vdisplay,
 797                             psr_max_h, psr_max_v);
 798                 return false;
 799         }
 800
 801         tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 802         return true;
 803 }
 804
 805 void intel_psr_compute_config(struct intel_dp *intel_dp,
 806                               struct intel_crtc_state *crtc_state)
 807 {
 808         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 809         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 810         const struct drm_display_mode *adjusted_mode =
 811                 &crtc_state->hw.adjusted_mode;
 812         int psr_setup_time;
 813
 814         if (!CAN_PSR(dev_priv))
 815                 return;
 816
 817         if (intel_dp != dev_priv->psr.dp)
 818                 return;
 819
 820         if (!psr_global_enabled(dev_priv)) {
 821                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
 822                 return;
 823         }
 824
 825         /*
 826          * HSW spec explicitly says PSR is tied to port A.
 827          * BDW+ platforms have a instance of PSR registers per transcoder but
 828          * for now it only supports one instance of PSR, so lets keep it
 829          * hardcoded to PORT_A
 830          */
 831         if (dig_port->base.port != PORT_A) {
 832                 drm_dbg_kms(&dev_priv->drm,
 833                             "PSR condition failed: Port not supported\n");
 834                 return;
 835         }
 836
 837         if (dev_priv->psr.sink_not_reliable) {
 838                 drm_dbg_kms(&dev_priv->drm,
 839                             "PSR sink implementation is not reliable\n");
 840                 return;
 841         }
 842
 843         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 844                 drm_dbg_kms(&dev_priv->drm,
 845                             "PSR condition failed: Interlaced mode enabled\n");
 846                 return;
 847         }
 848
 849         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 850         if (psr_setup_time < 0) {
 851                 drm_dbg_kms(&dev_priv->drm,
 852                             "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 853                             intel_dp->psr_dpcd[1]);
 854                 return;
 855         }
 856
 857         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 858             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 859                 drm_dbg_kms(&dev_priv->drm,
 860                             "PSR condition failed: PSR setup time (%d us) too long\n",
 861                             psr_setup_time);
 862                 return;
 863         }
 864
 865         crtc_state->has_psr = true;
 866         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 867         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 868 }
 869
 870 static void intel_psr_activate(struct intel_dp *intel_dp)
 871 {
 872         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 873
 874         if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
 875                 drm_WARN_ON(&dev_priv->drm,
 876                             intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
 877
 878         drm_WARN_ON(&dev_priv->drm,
 879                     intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
 880         drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active);
 881         lockdep_assert_held(&dev_priv->psr.lock);
 882
 883         /* psr1 and psr2 are mutually exclusive.*/
 884         if (dev_priv->psr.psr2_enabled)
 885                 hsw_activate_psr2(intel_dp);
 886         else
 887                 hsw_activate_psr1(intel_dp);
 888
 889         dev_priv->psr.active = true;
 890 }
 891
 892 static void intel_psr_enable_source(struct intel_dp *intel_dp,
 893                                     const struct intel_crtc_state *crtc_state)
 894 {
 895         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 896         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 897         u32 mask;
 898
 899         /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 900          * use hardcoded values PSR AUX transactions
 901          */
 902         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 903                 hsw_psr_setup_aux(intel_dp);
 904
 905         if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
 906                                            !IS_GEMINILAKE(dev_priv))) {
 907                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
 908                 u32 chicken = intel_de_read(dev_priv, reg);
 909
 910                 chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
 911                            PSR2_ADD_VERTICAL_LINE_COUNT;
 912                 intel_de_write(dev_priv, reg, chicken);
 913         }
 914
 915         /*
 916          * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
 917          * mask LPSP to avoid dependency on other drivers that might block
 918          * runtime_pm besides preventing  other hw tracking issues now we
 919          * can rely on frontbuffer tracking.
 920          */
 921         mask = EDP_PSR_DEBUG_MASK_MEMUP |
 922                EDP_PSR_DEBUG_MASK_HPD |
 923                EDP_PSR_DEBUG_MASK_LPSP |
 924                EDP_PSR_DEBUG_MASK_MAX_SLEEP;
 925
 926         if (INTEL_GEN(dev_priv) < 11)
 927                 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
 928
 929         intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder),
 930                        mask);
 931
 932         psr_irq_control(dev_priv);
 933
 934         if (crtc_state->dc3co_exitline) {
 935                 u32 val;
 936
 937                 /*
 938                  * TODO: if future platforms supports DC3CO in more than one
 939                  * transcoder, EXITLINE will need to be unset when disabling PSR
 940                  */
 941                 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
 942                 val &= ~EXITLINE_MASK;
 943                 val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
 944                 val |= EXITLINE_ENABLE;
 945                 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
 946         }
 947
 948         if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
 949                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
 950                              dev_priv->psr.psr2_sel_fetch_enabled ?
 951                              IGNORE_PSR2_HW_TRACKING : 0);
 952 }
 953
 954 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 955                                     const struct intel_crtc_state *crtc_state,
 956                                     const struct drm_connector_state *conn_state)
 957 {
 958         struct intel_dp *intel_dp = dev_priv->psr.dp;
 959         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 960         struct intel_encoder *encoder = &dig_port->base;
 961         u32 val;
 962
 963         drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
 964
 965         dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
 966         dev_priv->psr.busy_frontbuffer_bits = 0;
 967         dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 968         dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
 969         dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
 970         /* DC5/DC6 requires at least 6 idle frames */
 971         val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
 972         dev_priv->psr.dc3co_exit_delay = val;
 973         dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
 974
 975         /*
 976          * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
 977          * will still keep the error set even after the reset done in the
 978          * irq_preinstall and irq_uninstall hooks.
 979          * And enabling in this situation cause the screen to freeze in the
 980          * first time that PSR HW tries to activate so lets keep PSR disabled
 981          * to avoid any rendering problems.
 982          */
 983         if (INTEL_GEN(dev_priv) >= 12) {
 984                 val = intel_de_read(dev_priv,
 985                                     TRANS_PSR_IIR(dev_priv->psr.transcoder));
 986                 val &= EDP_PSR_ERROR(0);
 987         } else {
 988                 val = intel_de_read(dev_priv, EDP_PSR_IIR);
 989                 val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
 990         }
 991         if (val) {
 992                 dev_priv->psr.sink_not_reliable = true;
 993                 drm_dbg_kms(&dev_priv->drm,
 994                             "PSR interruption error set, not enabling PSR\n");
 995                 return;
 996         }
 997
 998         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 999                     dev_priv->psr.psr2_enabled ? "2" : "1");
1000         intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1001                                      &dev_priv->psr.vsc);
1002         intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
1003         intel_psr_enable_sink(intel_dp);
1004         intel_psr_enable_source(intel_dp, crtc_state);
1005         dev_priv->psr.enabled = true;
1006
1007         intel_psr_activate(intel_dp);
1008 }
1009
1010 /**
1011  * intel_psr_enable - Enable PSR
1012  * @intel_dp: Intel DP
1013  * @crtc_state: new CRTC state
1014  * @conn_state: new CONNECTOR state
1015  *
1016  * This function can only be called after the pipe is fully trained and enabled.
1017  */
1018 void intel_psr_enable(struct intel_dp *intel_dp,
1019                       const struct intel_crtc_state *crtc_state,
1020                       const struct drm_connector_state *conn_state)
1021 {
1022         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1023
1024         if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
1025                 return;
1026
1027         if (!crtc_state->has_psr)
1028                 return;
1029
1030         drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
1031
1032         mutex_lock(&dev_priv->psr.lock);
1033         intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
1034         mutex_unlock(&dev_priv->psr.lock);
1035 }
1036
1037 static void intel_psr_exit(struct drm_i915_private *dev_priv)
1038 {
1039         u32 val;
1040
1041         if (!dev_priv->psr.active) {
1042                 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
1043                         val = intel_de_read(dev_priv,
1044                                             EDP_PSR2_CTL(dev_priv->psr.transcoder));
1045                         drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1046                 }
1047
1048                 val = intel_de_read(dev_priv,
1049                                     EDP_PSR_CTL(dev_priv->psr.transcoder));
1050                 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1051
1052                 return;
1053         }
1054
1055         if (dev_priv->psr.psr2_enabled) {
1056                 tgl_disallow_dc3co_on_psr2_exit(dev_priv);
1057                 val = intel_de_read(dev_priv,
1058                                     EDP_PSR2_CTL(dev_priv->psr.transcoder));
1059                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1060                 val &= ~EDP_PSR2_ENABLE;
1061                 intel_de_write(dev_priv,
1062                                EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
1063         } else {
1064                 val = intel_de_read(dev_priv,
1065                                     EDP_PSR_CTL(dev_priv->psr.transcoder));
1066                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1067                 val &= ~EDP_PSR_ENABLE;
1068                 intel_de_write(dev_priv,
1069                                EDP_PSR_CTL(dev_priv->psr.transcoder), val);
1070         }
1071         dev_priv->psr.active = false;
1072 }
1073
1074 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1075 {
1076         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1077         i915_reg_t psr_status;
1078         u32 psr_status_mask;
1079
1080         lockdep_assert_held(&dev_priv->psr.lock);
1081
1082         if (!dev_priv->psr.enabled)
1083                 return;
1084
1085         drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1086                     dev_priv->psr.psr2_enabled ? "2" : "1");
1087
1088         intel_psr_exit(dev_priv);
1089
1090         if (dev_priv->psr.psr2_enabled) {
1091                 psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
1092                 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1093         } else {
1094                 psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
1095                 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1096         }
1097
1098         /* Wait till PSR is idle */
1099         if (intel_de_wait_for_clear(dev_priv, psr_status,
1100                                     psr_status_mask, 2000))
1101                 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1102
1103         /* WA 1408330847 */
1104         if (dev_priv->psr.psr2_sel_fetch_enabled &&
1105             (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
1106              IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
1107                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1108                              DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1109
1110         /* Disable PSR on Sink */
1111         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1112
1113         if (dev_priv->psr.psr2_enabled)
1114                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1115
1116         dev_priv->psr.enabled = false;
1117 }
1118
1119 /**
1120  * intel_psr_disable - Disable PSR
1121  * @intel_dp: Intel DP
1122  * @old_crtc_state: old CRTC state
1123  *
1124  * This function needs to be called before disabling pipe.
1125  */
1126 void intel_psr_disable(struct intel_dp *intel_dp,
1127                        const struct intel_crtc_state *old_crtc_state)
1128 {
1129         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1130
1131         if (!old_crtc_state->has_psr)
1132                 return;
1133
1134         if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
1135                 return;
1136
1137         mutex_lock(&dev_priv->psr.lock);
1138
1139         intel_psr_disable_locked(intel_dp);
1140
1141         mutex_unlock(&dev_priv->psr.lock);
1142         cancel_work_sync(&dev_priv->psr.work);
1143         cancel_delayed_work_sync(&dev_priv->psr.dc3co_work);
1144 }
1145
1146 static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
1147 {
1148         if (IS_TIGERLAKE(dev_priv))
1149                 /*
1150                  * Writes to CURSURFLIVE in TGL are causing IOMMU errors and
1151                  * visual glitches that are often reproduced when executing
1152                  * CPU intensive workloads while a eDP 4K panel is attached.
1153                  *
1154                  * Manually exiting PSR causes the frontbuffer to be updated
1155                  * without glitches and the IOMMU errors are also gone but
1156                  * this comes at the cost of less time with PSR active.
1157                  *
1158                  * So using this workaround until this issue is root caused
1159                  * and a better fix is found.
1160                  */
1161                 intel_psr_exit(dev_priv);
1162         else if (INTEL_GEN(dev_priv) >= 9)
1163                 /*
1164                  * Display WA #0884: skl+
1165                  * This documented WA for bxt can be safely applied
1166                  * broadly so we can force HW tracking to exit PSR
1167                  * instead of disabling and re-enabling.
1168                  * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1169                  * but it makes more sense write to the current active
1170                  * pipe.
1171                  */
1172                 intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0);
1173         else
1174                 /*
1175                  * A write to CURSURFLIVE do not cause HW tracking to exit PSR
1176                  * on older gens so doing the manual exit instead.
1177                  */
1178                 intel_psr_exit(dev_priv);
1179 }
1180
1181 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1182                                         const struct intel_crtc_state *crtc_state,
1183                                         const struct intel_plane_state *plane_state,
1184                                         int color_plane)
1185 {
1186         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1187         enum pipe pipe = plane->pipe;
1188         u32 val;
1189
1190         if (!crtc_state->enable_psr2_sel_fetch)
1191                 return;
1192
1193         val = plane_state ? plane_state->ctl : 0;
1194         val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
1195         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
1196         if (!val || plane->id == PLANE_CURSOR)
1197                 return;
1198
1199         val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1;
1200         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1201
1202         val = plane_state->color_plane[color_plane].y << 16;
1203         val |= plane_state->color_plane[color_plane].x;
1204         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1205                           val);
1206
1207         /* Sizes are 0 based */
1208         val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16;
1209         val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1210         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1211 }
1212
1213 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1214 {
1215         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1217         struct i915_psr *psr = &dev_priv->psr;
1218
1219         if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
1220             !crtc_state->enable_psr2_sel_fetch)
1221                 return;
1222
1223         intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder),
1224                        crtc_state->psr2_man_track_ctl);
1225 }
1226
1227 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1228                                   struct drm_rect *clip, bool full_update)
1229 {
1230         u32 val = PSR2_MAN_TRK_CTL_ENABLE;
1231
1232         if (full_update) {
1233                 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1234                 goto exit;
1235         }
1236
1237         if (clip->y1 == -1)
1238                 goto exit;
1239
1240         val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1241         val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1242         val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1);
1243 exit:
1244         crtc_state->psr2_man_track_ctl = val;
1245 }
1246
1247 static void clip_area_update(struct drm_rect *overlap_damage_area,
1248                              struct drm_rect *damage_area)
1249 {
1250         if (overlap_damage_area->y1 == -1) {
1251                 overlap_damage_area->y1 = damage_area->y1;
1252                 overlap_damage_area->y2 = damage_area->y2;
1253                 return;
1254         }
1255
1256         if (damage_area->y1 < overlap_damage_area->y1)
1257                 overlap_damage_area->y1 = damage_area->y1;
1258
1259         if (damage_area->y2 > overlap_damage_area->y2)
1260                 overlap_damage_area->y2 = damage_area->y2;
1261 }
1262
1263 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1264                                 struct intel_crtc *crtc)
1265 {
1266         struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1267         struct intel_plane_state *new_plane_state, *old_plane_state;
1268         struct drm_rect pipe_clip = { .y1 = -1 };
1269         struct intel_plane *plane;
1270         bool full_update = false;
1271         int i, ret;
1272
1273         if (!crtc_state->enable_psr2_sel_fetch)
1274                 return 0;
1275
1276         ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1277         if (ret)
1278                 return ret;
1279
1280         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1281                                              new_plane_state, i) {
1282                 struct drm_rect temp;
1283
1284                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1285                         continue;
1286
1287                 /*
1288                  * TODO: Not clear how to handle planes with negative position,
1289                  * also planes are not updated if they have a negative X
1290                  * position so for now doing a full update in this cases
1291                  */
1292                 if (new_plane_state->uapi.dst.y1 < 0 ||
1293                     new_plane_state->uapi.dst.x1 < 0) {
1294                         full_update = true;
1295                         break;
1296                 }
1297
1298                 if (!new_plane_state->uapi.visible)
1299                         continue;
1300
1301                 /*
1302                  * For now doing a selective fetch in the whole plane area,
1303                  * optimizations will come in the future.
1304                  */
1305                 temp.y1 = new_plane_state->uapi.dst.y1;
1306                 temp.y2 = new_plane_state->uapi.dst.y2;
1307                 clip_area_update(&pipe_clip, &temp);
1308         }
1309
1310         psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1311         return 0;
1312 }
1313
1314 /**
1315  * intel_psr_update - Update PSR state
1316  * @intel_dp: Intel DP
1317  * @crtc_state: new CRTC state
1318  * @conn_state: new CONNECTOR state
1319  *
1320  * This functions will update PSR states, disabling, enabling or switching PSR
1321  * version when executing fastsets. For full modeset, intel_psr_disable() and
1322  * intel_psr_enable() should be called instead.
1323  */
1324 void intel_psr_update(struct intel_dp *intel_dp,
1325                       const struct intel_crtc_state *crtc_state,
1326                       const struct drm_connector_state *conn_state)
1327 {
1328         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1329         struct i915_psr *psr = &dev_priv->psr;
1330         bool enable, psr2_enable;
1331
1332         if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
1333                 return;
1334
1335         mutex_lock(&dev_priv->psr.lock);
1336
1337         enable = crtc_state->has_psr;
1338         psr2_enable = crtc_state->has_psr2;
1339
1340         if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
1341                 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1342                 if (crtc_state->crc_enabled && psr->enabled)
1343                         psr_force_hw_tracking_exit(dev_priv);
1344                 else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
1345                         /*
1346                          * Activate PSR again after a force exit when enabling
1347                          * CRC in older gens
1348                          */
1349                         if (!dev_priv->psr.active &&
1350                             !dev_priv->psr.busy_frontbuffer_bits)
1351                                 schedule_work(&dev_priv->psr.work);
1352                 }
1353
1354                 goto unlock;
1355         }
1356
1357         if (psr->enabled)
1358                 intel_psr_disable_locked(intel_dp);
1359
1360         if (enable)
1361                 intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
1362
1363 unlock:
1364         mutex_unlock(&dev_priv->psr.lock);
1365 }
1366
1367 /**
1368  * intel_psr_wait_for_idle - wait for PSR1 to idle
1369  * @new_crtc_state: new CRTC state
1370  * @out_value: PSR status in case of failure
1371  *
1372  * This function is expected to be called from pipe_update_start() where it is
1373  * not expected to race with PSR enable or disable.
1374  *
1375  * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
1376  */
1377 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
1378                             u32 *out_value)
1379 {
1380         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1381         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1382
1383         if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
1384                 return 0;
1385
1386         /* FIXME: Update this for PSR2 if we need to wait for idle */
1387         if (READ_ONCE(dev_priv->psr.psr2_enabled))
1388                 return 0;
1389
1390         /*
1391          * From bspec: Panel Self Refresh (BDW+)
1392          * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1393          * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1394          * defensive enough to cover everything.
1395          */
1396
1397         return __intel_wait_for_register(&dev_priv->uncore,
1398                                          EDP_PSR_STATUS(dev_priv->psr.transcoder),
1399                                          EDP_PSR_STATUS_STATE_MASK,
1400                                          EDP_PSR_STATUS_STATE_IDLE, 2, 50,
1401                                          out_value);
1402 }
1403
1404 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
1405 {
1406         i915_reg_t reg;
1407         u32 mask;
1408         int err;
1409
1410         if (!dev_priv->psr.enabled)
1411                 return false;
1412
1413         if (dev_priv->psr.psr2_enabled) {
1414                 reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
1415                 mask = EDP_PSR2_STATUS_STATE_MASK;
1416         } else {
1417                 reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
1418                 mask = EDP_PSR_STATUS_STATE_MASK;
1419         }
1420
1421         mutex_unlock(&dev_priv->psr.lock);
1422
1423         err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
1424         if (err)
1425                 drm_err(&dev_priv->drm,
1426                         "Timed out waiting for PSR Idle for re-enable\n");
1427
1428         /* After the unlocked wait, verify that PSR is still wanted! */
1429         mutex_lock(&dev_priv->psr.lock);
1430         return err == 0 && dev_priv->psr.enabled;
1431 }
1432
1433 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
1434 {
1435         struct drm_connector_list_iter conn_iter;
1436         struct drm_device *dev = &dev_priv->drm;
1437         struct drm_modeset_acquire_ctx ctx;
1438         struct drm_atomic_state *state;
1439         struct drm_connector *conn;
1440         int err = 0;
1441
1442         state = drm_atomic_state_alloc(dev);
1443         if (!state)
1444                 return -ENOMEM;
1445
1446         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1447         state->acquire_ctx = &ctx;
1448
1449 retry:
1450
1451         drm_connector_list_iter_begin(dev, &conn_iter);
1452         drm_for_each_connector_iter(conn, &conn_iter) {
1453                 struct drm_connector_state *conn_state;
1454                 struct drm_crtc_state *crtc_state;
1455
1456                 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
1457                         continue;
1458
1459                 conn_state = drm_atomic_get_connector_state(state, conn);
1460                 if (IS_ERR(conn_state)) {
1461                         err = PTR_ERR(conn_state);
1462                         break;
1463                 }
1464
1465                 if (!conn_state->crtc)
1466                         continue;
1467
1468                 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
1469                 if (IS_ERR(crtc_state)) {
1470                         err = PTR_ERR(crtc_state);
1471                         break;
1472                 }
1473
1474                 /* Mark mode as changed to trigger a pipe->update() */
1475                 crtc_state->mode_changed = true;
1476         }
1477         drm_connector_list_iter_end(&conn_iter);
1478
1479         if (err == 0)
1480                 err = drm_atomic_commit(state);
1481
1482         if (err == -EDEADLK) {
1483                 drm_atomic_state_clear(state);
1484                 err = drm_modeset_backoff(&ctx);
1485                 if (!err)
1486                         goto retry;
1487         }
1488
1489         drm_modeset_drop_locks(&ctx);
1490         drm_modeset_acquire_fini(&ctx);
1491         drm_atomic_state_put(state);
1492
1493         return err;
1494 }
1495
1496 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
1497 {
1498         const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
1499         u32 old_mode;
1500         int ret;
1501
1502         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
1503             mode > I915_PSR_DEBUG_FORCE_PSR1) {
1504                 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
1505                 return -EINVAL;
1506         }
1507
1508         ret = mutex_lock_interruptible(&dev_priv->psr.lock);
1509         if (ret)
1510                 return ret;
1511
1512         old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
1513         dev_priv->psr.debug = val;
1514
1515         /*
1516          * Do it right away if it's already enabled, otherwise it will be done
1517          * when enabling the source.
1518          */
1519         if (dev_priv->psr.enabled)
1520                 psr_irq_control(dev_priv);
1521
1522         mutex_unlock(&dev_priv->psr.lock);
1523
1524         if (old_mode != mode)
1525                 ret = intel_psr_fastset_force(dev_priv);
1526
1527         return ret;
1528 }
1529
1530 static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
1531 {
1532         struct i915_psr *psr = &dev_priv->psr;
1533
1534         intel_psr_disable_locked(psr->dp);
1535         psr->sink_not_reliable = true;
1536         /* let's make sure that sink is awaken */
1537         drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1538 }
1539
1540 static void intel_psr_work(struct work_struct *work)
1541 {
1542         struct drm_i915_private *dev_priv =
1543                 container_of(work, typeof(*dev_priv), psr.work);
1544
1545         mutex_lock(&dev_priv->psr.lock);
1546
1547         if (!dev_priv->psr.enabled)
1548                 goto unlock;
1549
1550         if (READ_ONCE(dev_priv->psr.irq_aux_error))
1551                 intel_psr_handle_irq(dev_priv);
1552
1553         /*
1554          * We have to make sure PSR is ready for re-enable
1555          * otherwise it keeps disabled until next full enable/disable cycle.
1556          * PSR might take some time to get fully disabled
1557          * and be ready for re-enable.
1558          */
1559         if (!__psr_wait_for_idle_locked(dev_priv))
1560                 goto unlock;
1561
1562         /*
1563          * The delayed work can race with an invalidate hence we need to
1564          * recheck. Since psr_flush first clears this and then reschedules we
1565          * won't ever miss a flush when bailing out here.
1566          */
1567         if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
1568                 goto unlock;
1569
1570         intel_psr_activate(dev_priv->psr.dp);
1571 unlock:
1572         mutex_unlock(&dev_priv->psr.lock);
1573 }
1574
1575 /**
1576  * intel_psr_invalidate - Invalidade PSR
1577  * @dev_priv: i915 device
1578  * @frontbuffer_bits: frontbuffer plane tracking bits
1579  * @origin: which operation caused the invalidate
1580  *
1581  * Since the hardware frontbuffer tracking has gaps we need to integrate
1582  * with the software frontbuffer tracking. This function gets called every
1583  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
1584  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
1585  *
1586  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
1587  */
1588 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1589                           unsigned frontbuffer_bits, enum fb_op_origin origin)
1590 {
1591         if (!CAN_PSR(dev_priv))
1592                 return;
1593
1594         if (origin == ORIGIN_FLIP)
1595                 return;
1596
1597         mutex_lock(&dev_priv->psr.lock);
1598         if (!dev_priv->psr.enabled) {
1599                 mutex_unlock(&dev_priv->psr.lock);
1600                 return;
1601         }
1602
1603         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
1604         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1605
1606         if (frontbuffer_bits)
1607                 intel_psr_exit(dev_priv);
1608
1609         mutex_unlock(&dev_priv->psr.lock);
1610 }
1611
1612 /*
1613  * When we will be completely rely on PSR2 S/W tracking in future,
1614  * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
1615  * event also therefore tgl_dc3co_flush() require to be changed
1616  * accordingly in future.
1617  */
1618 static void
1619 tgl_dc3co_flush(struct drm_i915_private *dev_priv,
1620                 unsigned int frontbuffer_bits, enum fb_op_origin origin)
1621 {
1622         mutex_lock(&dev_priv->psr.lock);
1623
1624         if (!dev_priv->psr.dc3co_enabled)
1625                 goto unlock;
1626
1627         if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
1628                 goto unlock;
1629
1630         /*
1631          * At every frontbuffer flush flip event modified delay of delayed work,
1632          * when delayed work schedules that means display has been idle.
1633          */
1634         if (!(frontbuffer_bits &
1635             INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)))
1636                 goto unlock;
1637
1638         tgl_psr2_enable_dc3co(dev_priv);
1639         mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work,
1640                          dev_priv->psr.dc3co_exit_delay);
1641
1642 unlock:
1643         mutex_unlock(&dev_priv->psr.lock);
1644 }
1645
1646 /**
1647  * intel_psr_flush - Flush PSR
1648  * @dev_priv: i915 device
1649  * @frontbuffer_bits: frontbuffer plane tracking bits
1650  * @origin: which operation caused the flush
1651  *
1652  * Since the hardware frontbuffer tracking has gaps we need to integrate
1653  * with the software frontbuffer tracking. This function gets called every
1654  * time frontbuffer rendering has completed and flushed out to memory. PSR
1655  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
1656  *
1657  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
1658  */
1659 void intel_psr_flush(struct drm_i915_private *dev_priv,
1660                      unsigned frontbuffer_bits, enum fb_op_origin origin)
1661 {
1662         if (!CAN_PSR(dev_priv))
1663                 return;
1664
1665         if (origin == ORIGIN_FLIP) {
1666                 tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
1667                 return;
1668         }
1669
1670         mutex_lock(&dev_priv->psr.lock);
1671         if (!dev_priv->psr.enabled) {
1672                 mutex_unlock(&dev_priv->psr.lock);
1673                 return;
1674         }
1675
1676         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
1677         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1678
1679         /* By definition flush = invalidate + flush */
1680         if (frontbuffer_bits)
1681                 psr_force_hw_tracking_exit(dev_priv);
1682
1683         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
1684                 schedule_work(&dev_priv->psr.work);
1685         mutex_unlock(&dev_priv->psr.lock);
1686 }
1687
1688 /**
1689  * intel_psr_init - Init basic PSR work and mutex.
1690  * @dev_priv: i915 device private
1691  *
1692  * This function is  called only once at driver load to initialize basic
1693  * PSR stuff.
1694  */
1695 void intel_psr_init(struct drm_i915_private *dev_priv)
1696 {
1697         if (!HAS_PSR(dev_priv))
1698                 return;
1699
1700         if (!dev_priv->psr.sink_support)
1701                 return;
1702
1703         if (IS_HASWELL(dev_priv))
1704                 /*
1705                  * HSW don't have PSR registers on the same space as transcoder
1706                  * so set this to a value that when subtract to the register
1707                  * in transcoder space results in the right offset for HSW
1708                  */
1709                 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
1710
1711         if (dev_priv->params.enable_psr == -1)
1712                 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
1713                         dev_priv->params.enable_psr = 0;
1714
1715         /* Set link_standby x link_off defaults */
1716         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1717                 /* HSW and BDW require workarounds that we don't implement. */
1718                 dev_priv->psr.link_standby = false;
1719         else if (INTEL_GEN(dev_priv) < 12)
1720                 /* For new platforms up to TGL let's respect VBT back again */
1721                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
1722
1723         INIT_WORK(&dev_priv->psr.work, intel_psr_work);
1724         INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work);
1725         mutex_init(&dev_priv->psr.lock);
1726 }
1727
1728 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
1729                                            u8 *status, u8 *error_status)
1730 {
1731         struct drm_dp_aux *aux = &intel_dp->aux;
1732         int ret;
1733
1734         ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
1735         if (ret != 1)
1736                 return ret;
1737
1738         ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
1739         if (ret != 1)
1740                 return ret;
1741
1742         *status = *status & DP_PSR_SINK_STATE_MASK;
1743
1744         return 0;
1745 }
1746
1747 static void psr_alpm_check(struct intel_dp *intel_dp)
1748 {
1749         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1750         struct drm_dp_aux *aux = &intel_dp->aux;
1751         struct i915_psr *psr = &dev_priv->psr;
1752         u8 val;
1753         int r;
1754
1755         if (!psr->psr2_enabled)
1756                 return;
1757
1758         r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
1759         if (r != 1) {
1760                 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
1761                 return;
1762         }
1763
1764         if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
1765                 intel_psr_disable_locked(intel_dp);
1766                 psr->sink_not_reliable = true;
1767                 drm_dbg_kms(&dev_priv->drm,
1768                             "ALPM lock timeout error, disabling PSR\n");
1769
1770                 /* Clearing error */
1771                 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
1772         }
1773 }
1774
1775 static void psr_capability_changed_check(struct intel_dp *intel_dp)
1776 {
1777         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1778         struct i915_psr *psr = &dev_priv->psr;
1779         u8 val;
1780         int r;
1781
1782         r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
1783         if (r != 1) {
1784                 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
1785                 return;
1786         }
1787
1788         if (val & DP_PSR_CAPS_CHANGE) {
1789                 intel_psr_disable_locked(intel_dp);
1790                 psr->sink_not_reliable = true;
1791                 drm_dbg_kms(&dev_priv->drm,
1792                             "Sink PSR capability changed, disabling PSR\n");
1793
1794                 /* Clearing it */
1795                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
1796         }
1797 }
1798
1799 void intel_psr_short_pulse(struct intel_dp *intel_dp)
1800 {
1801         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1802         struct i915_psr *psr = &dev_priv->psr;
1803         u8 status, error_status;
1804         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
1805                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
1806                           DP_PSR_LINK_CRC_ERROR;
1807
1808         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
1809                 return;
1810
1811         mutex_lock(&psr->lock);
1812
1813         if (!psr->enabled || psr->dp != intel_dp)
1814                 goto exit;
1815
1816         if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
1817                 drm_err(&dev_priv->drm,
1818                         "Error reading PSR status or error status\n");
1819                 goto exit;
1820         }
1821
1822         if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
1823                 intel_psr_disable_locked(intel_dp);
1824                 psr->sink_not_reliable = true;
1825         }
1826
1827         if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
1828                 drm_dbg_kms(&dev_priv->drm,
1829                             "PSR sink internal error, disabling PSR\n");
1830         if (error_status & DP_PSR_RFB_STORAGE_ERROR)
1831                 drm_dbg_kms(&dev_priv->drm,
1832                             "PSR RFB storage error, disabling PSR\n");
1833         if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
1834                 drm_dbg_kms(&dev_priv->drm,
1835                             "PSR VSC SDP uncorrectable error, disabling PSR\n");
1836         if (error_status & DP_PSR_LINK_CRC_ERROR)
1837                 drm_dbg_kms(&dev_priv->drm,
1838                             "PSR Link CRC error, disabling PSR\n");
1839
1840         if (error_status & ~errors)
1841                 drm_err(&dev_priv->drm,
1842                         "PSR_ERROR_STATUS unhandled errors %x\n",
1843                         error_status & ~errors);
1844         /* clear status register */
1845         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
1846
1847         psr_alpm_check(intel_dp);
1848         psr_capability_changed_check(intel_dp);
1849
1850 exit:
1851         mutex_unlock(&psr->lock);
1852 }
1853
1854 bool intel_psr_enabled(struct intel_dp *intel_dp)
1855 {
1856         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1857         bool ret;
1858
1859         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
1860                 return false;
1861
1862         mutex_lock(&dev_priv->psr.lock);
1863         ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
1864         mutex_unlock(&dev_priv->psr.lock);
1865
1866         return ret;
1867 }