drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "i915_trace.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_connector.h"
  51 #include "intel_ddi.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_fifo_underrun.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_lspcon.h"
  62 #include "intel_lvds.h"
  63 #include "intel_panel.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC throughput values used for slice count calculations KPixels/s */
  72 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  73 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  74 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  75
  76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  77 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  78
  79 /* Compliance test status bits  */
  80 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  81 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  82 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  84
  85 struct dp_link_dpll {
  86         int clock;
  87         struct dpll dpll;
  88 };
  89
  90 static const struct dp_link_dpll g4x_dpll[] = {
  91         { 162000,
  92                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  93         { 270000,
  94                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  95 };
  96
  97 static const struct dp_link_dpll pch_dpll[] = {
  98         { 162000,
  99                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 100         { 270000,
 101                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 102 };
 103
 104 static const struct dp_link_dpll vlv_dpll[] = {
 105         { 162000,
 106                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 107         { 270000,
 108                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 109 };
 110
 111 /*
 112  * CHV supports eDP 1.4 that have  more link rates.
 113  * Below only provides the fixed rate but exclude variable rate.
 114  */
 115 static const struct dp_link_dpll chv_dpll[] = {
 116         /*
 117          * CHV requires to program fractional division for m2.
 118          * m2 is stored in fixed point format using formula below
 119          * (m2_int << 22) | m2_fraction
 120          */
 121         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 122                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 123         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 124                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 125 };
 126
 127 /* Constants for DP DSC configurations */
 128 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 129
 130 /* With Single pipe configuration, HW is capable of supporting maximum
 131  * of 4 slices per line.
 132  */
 133 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 134
 135 /**
 136  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 137  * @intel_dp: DP struct
 138  *
 139  * If a CPU or PCH DP output is attached to an eDP panel, this function
 140  * will return true, and false otherwise.
 141  */
 142 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 143 {
 144         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 145
 146         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 147 }
 148
 149 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 150 {
 151         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 152 }
 153
 154 static void intel_dp_link_down(struct intel_encoder *encoder,
 155                                const struct intel_crtc_state *old_crtc_state);
 156 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 157 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 158 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 159                                            const struct intel_crtc_state *crtc_state);
 160 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 161                                       enum pipe pipe);
 162 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 163
 164 /* update sink rates from dpcd */
 165 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 166 {
 167         static const int dp_rates[] = {
 168                 162000, 270000, 540000, 810000
 169         };
 170         int i, max_rate;
 171
 172         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 173
 174         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 175                 if (dp_rates[i] > max_rate)
 176                         break;
 177                 intel_dp->sink_rates[i] = dp_rates[i];
 178         }
 179
 180         intel_dp->num_sink_rates = i;
 181 }
 182
 183 /* Get length of rates array potentially limited by max_rate. */
 184 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 185 {
 186         int i;
 187
 188         /* Limit results by potentially reduced max rate */
 189         for (i = 0; i < len; i++) {
 190                 if (rates[len - i - 1] <= max_rate)
 191                         return len - i;
 192         }
 193
 194         return 0;
 195 }
 196
 197 /* Get length of common rates array potentially limited by max_rate. */
 198 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 199                                           int max_rate)
 200 {
 201         return intel_dp_rate_limit_len(intel_dp->common_rates,
 202                                        intel_dp->num_common_rates, max_rate);
 203 }
 204
 205 /* Theoretical max between source and sink */
 206 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 207 {
 208         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 209 }
 210
 211 /* Theoretical max between source and sink */
 212 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 213 {
 214         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 215         int source_max = intel_dig_port->max_lanes;
 216         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 217         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 218
 219         return min3(source_max, sink_max, fia_max);
 220 }
 221
 222 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 223 {
 224         return intel_dp->max_link_lane_count;
 225 }
 226
 227 int
 228 intel_dp_link_required(int pixel_clock, int bpp)
 229 {
 230         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 231         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 232 }
 233
 234 int
 235 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 236 {
 237         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 238          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 239          * is transmitted every LS_Clk per lane, there is no need to account for
 240          * the channel encoding that is done in the PHY layer here.
 241          */
 242
 243         return max_link_clock * max_lanes;
 244 }
 245
 246 static int
 247 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 248 {
 249         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 250         struct intel_encoder *encoder = &intel_dig_port->base;
 251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 252         int max_dotclk = dev_priv->max_dotclk_freq;
 253         int ds_max_dotclk;
 254
 255         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 256
 257         if (type != DP_DS_PORT_TYPE_VGA)
 258                 return max_dotclk;
 259
 260         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 261                                                     intel_dp->downstream_ports);
 262
 263         if (ds_max_dotclk != 0)
 264                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 265
 266         return max_dotclk;
 267 }
 268
 269 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 270 {
 271         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 272         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 273         enum port port = dig_port->base.port;
 274
 275         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 276
 277         /* Low voltage SKUs are limited to max of 5.4G */
 278         if (voltage == VOLTAGE_INFO_0_85V)
 279                 return 540000;
 280
 281         /* For this SKU 8.1G is supported in all ports */
 282         if (IS_CNL_WITH_PORT_F(dev_priv))
 283                 return 810000;
 284
 285         /* For other SKUs, max rate on ports A and D is 5.4G */
 286         if (port == PORT_A || port == PORT_D)
 287                 return 540000;
 288
 289         return 810000;
 290 }
 291
 292 static int icl_max_source_rate(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 295         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 296         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 297
 298         if (intel_phy_is_combo(dev_priv, phy) &&
 299             !IS_ELKHARTLAKE(dev_priv) &&
 300             !intel_dp_is_edp(intel_dp))
 301                 return 540000;
 302
 303         return 810000;
 304 }
 305
 306 static void
 307 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 308 {
 309         /* The values must be in increasing order */
 310         static const int cnl_rates[] = {
 311                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 312         };
 313         static const int bxt_rates[] = {
 314                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 315         };
 316         static const int skl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000
 318         };
 319         static const int hsw_rates[] = {
 320                 162000, 270000, 540000
 321         };
 322         static const int g4x_rates[] = {
 323                 162000, 270000
 324         };
 325         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 326         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 327         const struct ddi_vbt_port_info *info =
 328                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 329         const int *source_rates;
 330         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 331
 332         /* This should only be done once */
 333         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 334
 335         if (INTEL_GEN(dev_priv) >= 10) {
 336                 source_rates = cnl_rates;
 337                 size = ARRAY_SIZE(cnl_rates);
 338                 if (IS_GEN(dev_priv, 10))
 339                         max_rate = cnl_max_source_rate(intel_dp);
 340                 else
 341                         max_rate = icl_max_source_rate(intel_dp);
 342         } else if (IS_GEN9_LP(dev_priv)) {
 343                 source_rates = bxt_rates;
 344                 size = ARRAY_SIZE(bxt_rates);
 345         } else if (IS_GEN9_BC(dev_priv)) {
 346                 source_rates = skl_rates;
 347                 size = ARRAY_SIZE(skl_rates);
 348         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 349                    IS_BROADWELL(dev_priv)) {
 350                 source_rates = hsw_rates;
 351                 size = ARRAY_SIZE(hsw_rates);
 352         } else {
 353                 source_rates = g4x_rates;
 354                 size = ARRAY_SIZE(g4x_rates);
 355         }
 356
 357         if (max_rate && vbt_max_rate)
 358                 max_rate = min(max_rate, vbt_max_rate);
 359         else if (vbt_max_rate)
 360                 max_rate = vbt_max_rate;
 361
 362         if (max_rate)
 363                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 364
 365         intel_dp->source_rates = source_rates;
 366         intel_dp->num_source_rates = size;
 367 }
 368
 369 static int intersect_rates(const int *source_rates, int source_len,
 370                            const int *sink_rates, int sink_len,
 371                            int *common_rates)
 372 {
 373         int i = 0, j = 0, k = 0;
 374
 375         while (i < source_len && j < sink_len) {
 376                 if (source_rates[i] == sink_rates[j]) {
 377                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 378                                 return k;
 379                         common_rates[k] = source_rates[i];
 380                         ++k;
 381                         ++i;
 382                         ++j;
 383                 } else if (source_rates[i] < sink_rates[j]) {
 384                         ++i;
 385                 } else {
 386                         ++j;
 387                 }
 388         }
 389         return k;
 390 }
 391
 392 /* return index of rate in rates array, or -1 if not found */
 393 static int intel_dp_rate_index(const int *rates, int len, int rate)
 394 {
 395         int i;
 396
 397         for (i = 0; i < len; i++)
 398                 if (rate == rates[i])
 399                         return i;
 400
 401         return -1;
 402 }
 403
 404 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 405 {
 406         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 407
 408         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 409                                                      intel_dp->num_source_rates,
 410                                                      intel_dp->sink_rates,
 411                                                      intel_dp->num_sink_rates,
 412                                                      intel_dp->common_rates);
 413
 414         /* Paranoia, there should always be something in common. */
 415         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 416                 intel_dp->common_rates[0] = 162000;
 417                 intel_dp->num_common_rates = 1;
 418         }
 419 }
 420
 421 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 422                                        u8 lane_count)
 423 {
 424         /*
 425          * FIXME: we need to synchronize the current link parameters with
 426          * hardware readout. Currently fast link training doesn't work on
 427          * boot-up.
 428          */
 429         if (link_rate == 0 ||
 430             link_rate > intel_dp->max_link_rate)
 431                 return false;
 432
 433         if (lane_count == 0 ||
 434             lane_count > intel_dp_max_lane_count(intel_dp))
 435                 return false;
 436
 437         return true;
 438 }
 439
 440 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 441                                                      int link_rate,
 442                                                      u8 lane_count)
 443 {
 444         const struct drm_display_mode *fixed_mode =
 445                 intel_dp->attached_connector->panel.fixed_mode;
 446         int mode_rate, max_rate;
 447
 448         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 449         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 450         if (mode_rate > max_rate)
 451                 return false;
 452
 453         return true;
 454 }
 455
 456 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 457                                             int link_rate, u8 lane_count)
 458 {
 459         int index;
 460
 461         index = intel_dp_rate_index(intel_dp->common_rates,
 462                                     intel_dp->num_common_rates,
 463                                     link_rate);
 464         if (index > 0) {
 465                 if (intel_dp_is_edp(intel_dp) &&
 466                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 467                                                               intel_dp->common_rates[index - 1],
 468                                                               lane_count)) {
 469                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 470                         return 0;
 471                 }
 472                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 473                 intel_dp->max_link_lane_count = lane_count;
 474         } else if (lane_count > 1) {
 475                 if (intel_dp_is_edp(intel_dp) &&
 476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 477                                                               intel_dp_max_common_rate(intel_dp),
 478                                                               lane_count >> 1)) {
 479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 480                         return 0;
 481                 }
 482                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 483                 intel_dp->max_link_lane_count = lane_count >> 1;
 484         } else {
 485                 DRM_ERROR("Link Training Unsuccessful\n");
 486                 return -1;
 487         }
 488
 489         return 0;
 490 }
 491
 492 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 493 {
 494         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 495                        DP_DSC_FEC_OVERHEAD_FACTOR);
 496 }
 497
 498 static int
 499 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 500 {
 501         if (INTEL_GEN(i915) >= 11)
 502                 return 7680 * 8;
 503         else
 504                 return 6144 * 8;
 505 }
 506
 507 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 508                                        u32 link_clock, u32 lane_count,
 509                                        u32 mode_clock, u32 mode_hdisplay)
 510 {
 511         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 512         int i;
 513
 514         /*
 515          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 516          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 517          * for SST -> TimeSlotsPerMTP is 1,
 518          * for MST -> TimeSlotsPerMTP has to be calculated
 519          */
 520         bits_per_pixel = (link_clock * lane_count * 8) /
 521                          intel_dp_mode_to_fec_clock(mode_clock);
 522         DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
 523
 524         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 525         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 526                 mode_hdisplay;
 527         DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
 528
 529         /*
 530          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 531          * check, output bpp from small joiner RAM check)
 532          */
 533         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 534
 535         /* Error out if the max bpp is less than smallest allowed valid bpp */
 536         if (bits_per_pixel < valid_dsc_bpp[0]) {
 537                 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
 538                               bits_per_pixel, valid_dsc_bpp[0]);
 539                 return 0;
 540         }
 541
 542         /* Find the nearest match in the array of known BPPs from VESA */
 543         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 544                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 545                         break;
 546         }
 547         bits_per_pixel = valid_dsc_bpp[i];
 548
 549         /*
 550          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 551          * fractional part is 0
 552          */
 553         return bits_per_pixel << 4;
 554 }
 555
 556 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 557                                        int mode_clock, int mode_hdisplay)
 558 {
 559         u8 min_slice_count, i;
 560         int max_slice_width;
 561
 562         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 563                 min_slice_count = DIV_ROUND_UP(mode_clock,
 564                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 565         else
 566                 min_slice_count = DIV_ROUND_UP(mode_clock,
 567                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 568
 569         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 570         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 571                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
 572                               max_slice_width);
 573                 return 0;
 574         }
 575         /* Also take into account max slice width */
 576         min_slice_count = min_t(u8, min_slice_count,
 577                                 DIV_ROUND_UP(mode_hdisplay,
 578                                              max_slice_width));
 579
 580         /* Find the closest match to the valid slice count values */
 581         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 582                 if (valid_dsc_slicecount[i] >
 583                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 584                                                     false))
 585                         break;
 586                 if (min_slice_count  <= valid_dsc_slicecount[i])
 587                         return valid_dsc_slicecount[i];
 588         }
 589
 590         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
 591         return 0;
 592 }
 593
 594 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 595                                   int hdisplay)
 596 {
 597         /*
 598          * Older platforms don't like hdisplay==4096 with DP.
 599          *
 600          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 601          * and frame counter increment), but we don't get vblank interrupts,
 602          * and the pipe underruns immediately. The link also doesn't seem
 603          * to get trained properly.
 604          *
 605          * On CHV the vblank interrupts don't seem to disappear but
 606          * otherwise the symptoms are similar.
 607          *
 608          * TODO: confirm the behaviour on HSW+
 609          */
 610         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 611 }
 612
 613 static enum drm_mode_status
 614 intel_dp_mode_valid(struct drm_connector *connector,
 615                     struct drm_display_mode *mode)
 616 {
 617         struct intel_dp *intel_dp = intel_attached_dp(connector);
 618         struct intel_connector *intel_connector = to_intel_connector(connector);
 619         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 620         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 621         int target_clock = mode->clock;
 622         int max_rate, mode_rate, max_lanes, max_link_clock;
 623         int max_dotclk;
 624         u16 dsc_max_output_bpp = 0;
 625         u8 dsc_slice_count = 0;
 626
 627         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 628                 return MODE_NO_DBLESCAN;
 629
 630         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 631
 632         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 633                 if (mode->hdisplay > fixed_mode->hdisplay)
 634                         return MODE_PANEL;
 635
 636                 if (mode->vdisplay > fixed_mode->vdisplay)
 637                         return MODE_PANEL;
 638
 639                 target_clock = fixed_mode->clock;
 640         }
 641
 642         max_link_clock = intel_dp_max_link_rate(intel_dp);
 643         max_lanes = intel_dp_max_lane_count(intel_dp);
 644
 645         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 646         mode_rate = intel_dp_link_required(target_clock, 18);
 647
 648         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 649                 return MODE_H_ILLEGAL;
 650
 651         /*
 652          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 653          * integer value since we support only integer values of bpp.
 654          */
 655         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 656             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 657                 if (intel_dp_is_edp(intel_dp)) {
 658                         dsc_max_output_bpp =
 659                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 660                         dsc_slice_count =
 661                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 662                                                                 true);
 663                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 664                         dsc_max_output_bpp =
 665                                 intel_dp_dsc_get_output_bpp(dev_priv,
 666                                                             max_link_clock,
 667                                                             max_lanes,
 668                                                             target_clock,
 669                                                             mode->hdisplay) >> 4;
 670                         dsc_slice_count =
 671                                 intel_dp_dsc_get_slice_count(intel_dp,
 672                                                              target_clock,
 673                                                              mode->hdisplay);
 674                 }
 675         }
 676
 677         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 678             target_clock > max_dotclk)
 679                 return MODE_CLOCK_HIGH;
 680
 681         if (mode->clock < 10000)
 682                 return MODE_CLOCK_LOW;
 683
 684         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 685                 return MODE_H_ILLEGAL;
 686
 687         return intel_mode_valid_max_plane_size(dev_priv, mode);
 688 }
 689
 690 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 691 {
 692         int i;
 693         u32 v = 0;
 694
 695         if (src_bytes > 4)
 696                 src_bytes = 4;
 697         for (i = 0; i < src_bytes; i++)
 698                 v |= ((u32)src[i]) << ((3 - i) * 8);
 699         return v;
 700 }
 701
 702 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 703 {
 704         int i;
 705         if (dst_bytes > 4)
 706                 dst_bytes = 4;
 707         for (i = 0; i < dst_bytes; i++)
 708                 dst[i] = src >> ((3-i) * 8);
 709 }
 710
 711 static void
 712 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 713 static void
 714 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 715                                               bool force_disable_vdd);
 716 static void
 717 intel_dp_pps_init(struct intel_dp *intel_dp);
 718
 719 static intel_wakeref_t
 720 pps_lock(struct intel_dp *intel_dp)
 721 {
 722         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 723         intel_wakeref_t wakeref;
 724
 725         /*
 726          * See intel_power_sequencer_reset() why we need
 727          * a power domain reference here.
 728          */
 729         wakeref = intel_display_power_get(dev_priv,
 730                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 731
 732         mutex_lock(&dev_priv->pps_mutex);
 733
 734         return wakeref;
 735 }
 736
 737 static intel_wakeref_t
 738 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 739 {
 740         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 741
 742         mutex_unlock(&dev_priv->pps_mutex);
 743         intel_display_power_put(dev_priv,
 744                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 745                                 wakeref);
 746         return 0;
 747 }
 748
 749 #define with_pps_lock(dp, wf) \
 750         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 751
 752 static void
 753 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 754 {
 755         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 756         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 757         enum pipe pipe = intel_dp->pps_pipe;
 758         bool pll_enabled, release_cl_override = false;
 759         enum dpio_phy phy = DPIO_PHY(pipe);
 760         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 761         u32 DP;
 762
 763         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 764                  "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 765                  pipe_name(pipe), intel_dig_port->base.base.base.id,
 766                  intel_dig_port->base.base.name))
 767                 return;
 768
 769         DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 770                       pipe_name(pipe), intel_dig_port->base.base.base.id,
 771                       intel_dig_port->base.base.name);
 772
 773         /* Preserve the BIOS-computed detected bit. This is
 774          * supposed to be read-only.
 775          */
 776         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 777         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 778         DP |= DP_PORT_WIDTH(1);
 779         DP |= DP_LINK_TRAIN_PAT_1;
 780
 781         if (IS_CHERRYVIEW(dev_priv))
 782                 DP |= DP_PIPE_SEL_CHV(pipe);
 783         else
 784                 DP |= DP_PIPE_SEL(pipe);
 785
 786         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 787
 788         /*
 789          * The DPLL for the pipe must be enabled for this to work.
 790          * So enable temporarily it if it's not already enabled.
 791          */
 792         if (!pll_enabled) {
 793                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 794                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 795
 796                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 797                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 798                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 799                                   pipe_name(pipe));
 800                         return;
 801                 }
 802         }
 803
 804         /*
 805          * Similar magic as in intel_dp_enable_port().
 806          * We _must_ do this port enable + disable trick
 807          * to make this power sequencer lock onto the port.
 808          * Otherwise even VDD force bit won't work.
 809          */
 810         I915_WRITE(intel_dp->output_reg, DP);
 811         POSTING_READ(intel_dp->output_reg);
 812
 813         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 814         POSTING_READ(intel_dp->output_reg);
 815
 816         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 817         POSTING_READ(intel_dp->output_reg);
 818
 819         if (!pll_enabled) {
 820                 vlv_force_pll_off(dev_priv, pipe);
 821
 822                 if (release_cl_override)
 823                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 824         }
 825 }
 826
 827 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 828 {
 829         struct intel_encoder *encoder;
 830         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 831
 832         /*
 833          * We don't have power sequencer currently.
 834          * Pick one that's not used by other ports.
 835          */
 836         for_each_intel_dp(&dev_priv->drm, encoder) {
 837                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 838
 839                 if (encoder->type == INTEL_OUTPUT_EDP) {
 840                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 841                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 842
 843                         if (intel_dp->pps_pipe != INVALID_PIPE)
 844                                 pipes &= ~(1 << intel_dp->pps_pipe);
 845                 } else {
 846                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 847
 848                         if (intel_dp->active_pipe != INVALID_PIPE)
 849                                 pipes &= ~(1 << intel_dp->active_pipe);
 850                 }
 851         }
 852
 853         if (pipes == 0)
 854                 return INVALID_PIPE;
 855
 856         return ffs(pipes) - 1;
 857 }
 858
 859 static enum pipe
 860 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 861 {
 862         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 863         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 864         enum pipe pipe;
 865
 866         lockdep_assert_held(&dev_priv->pps_mutex);
 867
 868         /* We should never land here with regular DP ports */
 869         WARN_ON(!intel_dp_is_edp(intel_dp));
 870
 871         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 872                 intel_dp->active_pipe != intel_dp->pps_pipe);
 873
 874         if (intel_dp->pps_pipe != INVALID_PIPE)
 875                 return intel_dp->pps_pipe;
 876
 877         pipe = vlv_find_free_pps(dev_priv);
 878
 879         /*
 880          * Didn't find one. This should not happen since there
 881          * are two power sequencers and up to two eDP ports.
 882          */
 883         if (WARN_ON(pipe == INVALID_PIPE))
 884                 pipe = PIPE_A;
 885
 886         vlv_steal_power_sequencer(dev_priv, pipe);
 887         intel_dp->pps_pipe = pipe;
 888
 889         DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 890                       pipe_name(intel_dp->pps_pipe),
 891                       intel_dig_port->base.base.base.id,
 892                       intel_dig_port->base.base.name);
 893
 894         /* init power sequencer on this pipe and port */
 895         intel_dp_init_panel_power_sequencer(intel_dp);
 896         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 897
 898         /*
 899          * Even vdd force doesn't work until we've made
 900          * the power sequencer lock in on the port.
 901          */
 902         vlv_power_sequencer_kick(intel_dp);
 903
 904         return intel_dp->pps_pipe;
 905 }
 906
 907 static int
 908 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 909 {
 910         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 911         int backlight_controller = dev_priv->vbt.backlight.controller;
 912
 913         lockdep_assert_held(&dev_priv->pps_mutex);
 914
 915         /* We should never land here with regular DP ports */
 916         WARN_ON(!intel_dp_is_edp(intel_dp));
 917
 918         if (!intel_dp->pps_reset)
 919                 return backlight_controller;
 920
 921         intel_dp->pps_reset = false;
 922
 923         /*
 924          * Only the HW needs to be reprogrammed, the SW state is fixed and
 925          * has been setup during connector init.
 926          */
 927         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 928
 929         return backlight_controller;
 930 }
 931
 932 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 933                                enum pipe pipe);
 934
 935 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 936                                enum pipe pipe)
 937 {
 938         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 939 }
 940
 941 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 942                                 enum pipe pipe)
 943 {
 944         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 945 }
 946
 947 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 948                          enum pipe pipe)
 949 {
 950         return true;
 951 }
 952
 953 static enum pipe
 954 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 955                      enum port port,
 956                      vlv_pipe_check pipe_check)
 957 {
 958         enum pipe pipe;
 959
 960         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 961                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 962                         PANEL_PORT_SELECT_MASK;
 963
 964                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 965                         continue;
 966
 967                 if (!pipe_check(dev_priv, pipe))
 968                         continue;
 969
 970                 return pipe;
 971         }
 972
 973         return INVALID_PIPE;
 974 }
 975
 976 static void
 977 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 978 {
 979         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 980         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 981         enum port port = intel_dig_port->base.port;
 982
 983         lockdep_assert_held(&dev_priv->pps_mutex);
 984
 985         /* try to find a pipe with this port selected */
 986         /* first pick one where the panel is on */
 987         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 988                                                   vlv_pipe_has_pp_on);
 989         /* didn't find one? pick one where vdd is on */
 990         if (intel_dp->pps_pipe == INVALID_PIPE)
 991                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 992                                                           vlv_pipe_has_vdd_on);
 993         /* didn't find one? pick one with just the correct port */
 994         if (intel_dp->pps_pipe == INVALID_PIPE)
 995                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 996                                                           vlv_pipe_any);
 997
 998         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 999         if (intel_dp->pps_pipe == INVALID_PIPE) {
1000                 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
1001                               intel_dig_port->base.base.base.id,
1002                               intel_dig_port->base.base.name);
1003                 return;
1004         }
1005
1006         DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1007                       intel_dig_port->base.base.base.id,
1008                       intel_dig_port->base.base.name,
1009                       pipe_name(intel_dp->pps_pipe));
1010
1011         intel_dp_init_panel_power_sequencer(intel_dp);
1012         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1013 }
1014
1015 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1016 {
1017         struct intel_encoder *encoder;
1018
1019         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
1020                     !IS_GEN9_LP(dev_priv)))
1021                 return;
1022
1023         /*
1024          * We can't grab pps_mutex here due to deadlock with power_domain
1025          * mutex when power_domain functions are called while holding pps_mutex.
1026          * That also means that in order to use pps_pipe the code needs to
1027          * hold both a power domain reference and pps_mutex, and the power domain
1028          * reference get/put must be done while _not_ holding pps_mutex.
1029          * pps_{lock,unlock}() do these steps in the correct order, so one
1030          * should use them always.
1031          */
1032
1033         for_each_intel_dp(&dev_priv->drm, encoder) {
1034                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1035
1036                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1037
1038                 if (encoder->type != INTEL_OUTPUT_EDP)
1039                         continue;
1040
1041                 if (IS_GEN9_LP(dev_priv))
1042                         intel_dp->pps_reset = true;
1043                 else
1044                         intel_dp->pps_pipe = INVALID_PIPE;
1045         }
1046 }
1047
1048 struct pps_registers {
1049         i915_reg_t pp_ctrl;
1050         i915_reg_t pp_stat;
1051         i915_reg_t pp_on;
1052         i915_reg_t pp_off;
1053         i915_reg_t pp_div;
1054 };
1055
1056 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1057                                     struct pps_registers *regs)
1058 {
1059         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1060         int pps_idx = 0;
1061
1062         memset(regs, 0, sizeof(*regs));
1063
1064         if (IS_GEN9_LP(dev_priv))
1065                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1066         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1067                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1068
1069         regs->pp_ctrl = PP_CONTROL(pps_idx);
1070         regs->pp_stat = PP_STATUS(pps_idx);
1071         regs->pp_on = PP_ON_DELAYS(pps_idx);
1072         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1073
1074         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1075         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1076                 regs->pp_div = INVALID_MMIO_REG;
1077         else
1078                 regs->pp_div = PP_DIVISOR(pps_idx);
1079 }
1080
1081 static i915_reg_t
1082 _pp_ctrl_reg(struct intel_dp *intel_dp)
1083 {
1084         struct pps_registers regs;
1085
1086         intel_pps_get_registers(intel_dp, &regs);
1087
1088         return regs.pp_ctrl;
1089 }
1090
1091 static i915_reg_t
1092 _pp_stat_reg(struct intel_dp *intel_dp)
1093 {
1094         struct pps_registers regs;
1095
1096         intel_pps_get_registers(intel_dp, &regs);
1097
1098         return regs.pp_stat;
1099 }
1100
1101 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1102    This function only applicable when panel PM state is not to be tracked */
1103 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1104                               void *unused)
1105 {
1106         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1107                                                  edp_notifier);
1108         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1109         intel_wakeref_t wakeref;
1110
1111         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1112                 return 0;
1113
1114         with_pps_lock(intel_dp, wakeref) {
1115                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1116                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1117                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1118                         u32 pp_div;
1119
1120                         pp_ctrl_reg = PP_CONTROL(pipe);
1121                         pp_div_reg  = PP_DIVISOR(pipe);
1122                         pp_div = I915_READ(pp_div_reg);
1123                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1124
1125                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1126                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1127                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1128                         msleep(intel_dp->panel_power_cycle_delay);
1129                 }
1130         }
1131
1132         return 0;
1133 }
1134
1135 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1136 {
1137         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1138
1139         lockdep_assert_held(&dev_priv->pps_mutex);
1140
1141         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1142             intel_dp->pps_pipe == INVALID_PIPE)
1143                 return false;
1144
1145         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1146 }
1147
1148 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1149 {
1150         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1151
1152         lockdep_assert_held(&dev_priv->pps_mutex);
1153
1154         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1155             intel_dp->pps_pipe == INVALID_PIPE)
1156                 return false;
1157
1158         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1159 }
1160
1161 static void
1162 intel_dp_check_edp(struct intel_dp *intel_dp)
1163 {
1164         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1165
1166         if (!intel_dp_is_edp(intel_dp))
1167                 return;
1168
1169         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1170                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1171                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1172                               I915_READ(_pp_stat_reg(intel_dp)),
1173                               I915_READ(_pp_ctrl_reg(intel_dp)));
1174         }
1175 }
1176
1177 static u32
1178 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1179 {
1180         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1181         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1182         const unsigned int timeout_ms = 10;
1183         u32 status;
1184         bool done;
1185
1186 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1187         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1188                                   msecs_to_jiffies_timeout(timeout_ms));
1189
1190         /* just trace the final value */
1191         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1192
1193         if (!done)
1194                 DRM_ERROR("%s did not complete or timeout within %ums (status 0x%08x)\n",
1195                           intel_dp->aux.name, timeout_ms, status);
1196 #undef C
1197
1198         return status;
1199 }
1200
1201 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1202 {
1203         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1204
1205         if (index)
1206                 return 0;
1207
1208         /*
1209          * The clock divider is based off the hrawclk, and would like to run at
1210          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1211          */
1212         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1213 }
1214
1215 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1216 {
1217         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1218         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1219
1220         if (index)
1221                 return 0;
1222
1223         /*
1224          * The clock divider is based off the cdclk or PCH rawclk, and would
1225          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1226          * divide by 2000 and use that
1227          */
1228         if (dig_port->aux_ch == AUX_CH_A)
1229                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1230         else
1231                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1232 }
1233
1234 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1235 {
1236         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1237         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1238
1239         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1240                 /* Workaround for non-ULT HSW */
1241                 switch (index) {
1242                 case 0: return 63;
1243                 case 1: return 72;
1244                 default: return 0;
1245                 }
1246         }
1247
1248         return ilk_get_aux_clock_divider(intel_dp, index);
1249 }
1250
1251 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1252 {
1253         /*
1254          * SKL doesn't need us to program the AUX clock divider (Hardware will
1255          * derive the clock from CDCLK automatically). We still implement the
1256          * get_aux_clock_divider vfunc to plug-in into the existing code.
1257          */
1258         return index ? 0 : 1;
1259 }
1260
1261 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1262                                 int send_bytes,
1263                                 u32 aux_clock_divider)
1264 {
1265         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1266         struct drm_i915_private *dev_priv =
1267                         to_i915(intel_dig_port->base.base.dev);
1268         u32 precharge, timeout;
1269
1270         if (IS_GEN(dev_priv, 6))
1271                 precharge = 3;
1272         else
1273                 precharge = 5;
1274
1275         if (IS_BROADWELL(dev_priv))
1276                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1277         else
1278                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1279
1280         return DP_AUX_CH_CTL_SEND_BUSY |
1281                DP_AUX_CH_CTL_DONE |
1282                DP_AUX_CH_CTL_INTERRUPT |
1283                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1284                timeout |
1285                DP_AUX_CH_CTL_RECEIVE_ERROR |
1286                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1287                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1288                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1289 }
1290
1291 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1292                                 int send_bytes,
1293                                 u32 unused)
1294 {
1295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296         struct drm_i915_private *i915 =
1297                         to_i915(intel_dig_port->base.base.dev);
1298         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1299         u32 ret;
1300
1301         ret = DP_AUX_CH_CTL_SEND_BUSY |
1302               DP_AUX_CH_CTL_DONE |
1303               DP_AUX_CH_CTL_INTERRUPT |
1304               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1305               DP_AUX_CH_CTL_TIME_OUT_MAX |
1306               DP_AUX_CH_CTL_RECEIVE_ERROR |
1307               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1308               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1309               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1310
1311         if (intel_phy_is_tc(i915, phy) &&
1312             intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1313                 ret |= DP_AUX_CH_CTL_TBT_IO;
1314
1315         return ret;
1316 }
1317
1318 static int
1319 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1320                   const u8 *send, int send_bytes,
1321                   u8 *recv, int recv_size,
1322                   u32 aux_send_ctl_flags)
1323 {
1324         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1325         struct drm_i915_private *i915 =
1326                         to_i915(intel_dig_port->base.base.dev);
1327         struct intel_uncore *uncore = &i915->uncore;
1328         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1329         bool is_tc_port = intel_phy_is_tc(i915, phy);
1330         i915_reg_t ch_ctl, ch_data[5];
1331         u32 aux_clock_divider;
1332         enum intel_display_power_domain aux_domain =
1333                 intel_aux_power_domain(intel_dig_port);
1334         intel_wakeref_t aux_wakeref;
1335         intel_wakeref_t pps_wakeref;
1336         int i, ret, recv_bytes;
1337         int try, clock = 0;
1338         u32 status;
1339         bool vdd;
1340
1341         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1342         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1343                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1344
1345         if (is_tc_port)
1346                 intel_tc_port_lock(intel_dig_port);
1347
1348         aux_wakeref = intel_display_power_get(i915, aux_domain);
1349         pps_wakeref = pps_lock(intel_dp);
1350
1351         /*
1352          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1353          * In such cases we want to leave VDD enabled and it's up to upper layers
1354          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1355          * ourselves.
1356          */
1357         vdd = edp_panel_vdd_on(intel_dp);
1358
1359         /* dp aux is extremely sensitive to irq latency, hence request the
1360          * lowest possible wakeup latency and so prevent the cpu from going into
1361          * deep sleep states.
1362          */
1363         pm_qos_update_request(&i915->pm_qos, 0);
1364
1365         intel_dp_check_edp(intel_dp);
1366
1367         /* Try to wait for any previous AUX channel activity */
1368         for (try = 0; try < 3; try++) {
1369                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1370                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1371                         break;
1372                 msleep(1);
1373         }
1374         /* just trace the final value */
1375         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1376
1377         if (try == 3) {
1378                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1379
1380                 if (status != intel_dp->aux_busy_last_status) {
1381                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1382                              status);
1383                         intel_dp->aux_busy_last_status = status;
1384                 }
1385
1386                 ret = -EBUSY;
1387                 goto out;
1388         }
1389
1390         /* Only 5 data registers! */
1391         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1392                 ret = -E2BIG;
1393                 goto out;
1394         }
1395
1396         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1397                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1398                                                           send_bytes,
1399                                                           aux_clock_divider);
1400
1401                 send_ctl |= aux_send_ctl_flags;
1402
1403                 /* Must try at least 3 times according to DP spec */
1404                 for (try = 0; try < 5; try++) {
1405                         /* Load the send data into the aux channel data registers */
1406                         for (i = 0; i < send_bytes; i += 4)
1407                                 intel_uncore_write(uncore,
1408                                                    ch_data[i >> 2],
1409                                                    intel_dp_pack_aux(send + i,
1410                                                                      send_bytes - i));
1411
1412                         /* Send the command and wait for it to complete */
1413                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1414
1415                         status = intel_dp_aux_wait_done(intel_dp);
1416
1417                         /* Clear done status and any errors */
1418                         intel_uncore_write(uncore,
1419                                            ch_ctl,
1420                                            status |
1421                                            DP_AUX_CH_CTL_DONE |
1422                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1423                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1424
1425                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1426                          *   400us delay required for errors and timeouts
1427                          *   Timeout errors from the HW already meet this
1428                          *   requirement so skip to next iteration
1429                          */
1430                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1431                                 continue;
1432
1433                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1434                                 usleep_range(400, 500);
1435                                 continue;
1436                         }
1437                         if (status & DP_AUX_CH_CTL_DONE)
1438                                 goto done;
1439                 }
1440         }
1441
1442         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1443                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1444                 ret = -EBUSY;
1445                 goto out;
1446         }
1447
1448 done:
1449         /* Check for timeout or receive error.
1450          * Timeouts occur when the sink is not connected
1451          */
1452         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1453                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1454                 ret = -EIO;
1455                 goto out;
1456         }
1457
1458         /* Timeouts occur when the device isn't connected, so they're
1459          * "normal" -- don't fill the kernel log with these */
1460         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1461                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1462                 ret = -ETIMEDOUT;
1463                 goto out;
1464         }
1465
1466         /* Unload any bytes sent back from the other side */
1467         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1468                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1469
1470         /*
1471          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1472          * We have no idea of what happened so we return -EBUSY so
1473          * drm layer takes care for the necessary retries.
1474          */
1475         if (recv_bytes == 0 || recv_bytes > 20) {
1476                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1477                               recv_bytes);
1478                 ret = -EBUSY;
1479                 goto out;
1480         }
1481
1482         if (recv_bytes > recv_size)
1483                 recv_bytes = recv_size;
1484
1485         for (i = 0; i < recv_bytes; i += 4)
1486                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1487                                     recv + i, recv_bytes - i);
1488
1489         ret = recv_bytes;
1490 out:
1491         pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1492
1493         if (vdd)
1494                 edp_panel_vdd_off(intel_dp, false);
1495
1496         pps_unlock(intel_dp, pps_wakeref);
1497         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1498
1499         if (is_tc_port)
1500                 intel_tc_port_unlock(intel_dig_port);
1501
1502         return ret;
1503 }
1504
1505 #define BARE_ADDRESS_SIZE       3
1506 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1507
1508 static void
1509 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1510                     const struct drm_dp_aux_msg *msg)
1511 {
1512         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1513         txbuf[1] = (msg->address >> 8) & 0xff;
1514         txbuf[2] = msg->address & 0xff;
1515         txbuf[3] = msg->size - 1;
1516 }
1517
1518 static ssize_t
1519 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1520 {
1521         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1522         u8 txbuf[20], rxbuf[20];
1523         size_t txsize, rxsize;
1524         int ret;
1525
1526         intel_dp_aux_header(txbuf, msg);
1527
1528         switch (msg->request & ~DP_AUX_I2C_MOT) {
1529         case DP_AUX_NATIVE_WRITE:
1530         case DP_AUX_I2C_WRITE:
1531         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1532                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1533                 rxsize = 2; /* 0 or 1 data bytes */
1534
1535                 if (WARN_ON(txsize > 20))
1536                         return -E2BIG;
1537
1538                 WARN_ON(!msg->buffer != !msg->size);
1539
1540                 if (msg->buffer)
1541                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1542
1543                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1544                                         rxbuf, rxsize, 0);
1545                 if (ret > 0) {
1546                         msg->reply = rxbuf[0] >> 4;
1547
1548                         if (ret > 1) {
1549                                 /* Number of bytes written in a short write. */
1550                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1551                         } else {
1552                                 /* Return payload size. */
1553                                 ret = msg->size;
1554                         }
1555                 }
1556                 break;
1557
1558         case DP_AUX_NATIVE_READ:
1559         case DP_AUX_I2C_READ:
1560                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1561                 rxsize = msg->size + 1;
1562
1563                 if (WARN_ON(rxsize > 20))
1564                         return -E2BIG;
1565
1566                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1567                                         rxbuf, rxsize, 0);
1568                 if (ret > 0) {
1569                         msg->reply = rxbuf[0] >> 4;
1570                         /*
1571                          * Assume happy day, and copy the data. The caller is
1572                          * expected to check msg->reply before touching it.
1573                          *
1574                          * Return payload size.
1575                          */
1576                         ret--;
1577                         memcpy(msg->buffer, rxbuf + 1, ret);
1578                 }
1579                 break;
1580
1581         default:
1582                 ret = -EINVAL;
1583                 break;
1584         }
1585
1586         return ret;
1587 }
1588
1589
1590 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1591 {
1592         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1593         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1594         enum aux_ch aux_ch = dig_port->aux_ch;
1595
1596         switch (aux_ch) {
1597         case AUX_CH_B:
1598         case AUX_CH_C:
1599         case AUX_CH_D:
1600                 return DP_AUX_CH_CTL(aux_ch);
1601         default:
1602                 MISSING_CASE(aux_ch);
1603                 return DP_AUX_CH_CTL(AUX_CH_B);
1604         }
1605 }
1606
1607 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1608 {
1609         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1610         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1611         enum aux_ch aux_ch = dig_port->aux_ch;
1612
1613         switch (aux_ch) {
1614         case AUX_CH_B:
1615         case AUX_CH_C:
1616         case AUX_CH_D:
1617                 return DP_AUX_CH_DATA(aux_ch, index);
1618         default:
1619                 MISSING_CASE(aux_ch);
1620                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1621         }
1622 }
1623
1624 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1625 {
1626         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1627         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1628         enum aux_ch aux_ch = dig_port->aux_ch;
1629
1630         switch (aux_ch) {
1631         case AUX_CH_A:
1632                 return DP_AUX_CH_CTL(aux_ch);
1633         case AUX_CH_B:
1634         case AUX_CH_C:
1635         case AUX_CH_D:
1636                 return PCH_DP_AUX_CH_CTL(aux_ch);
1637         default:
1638                 MISSING_CASE(aux_ch);
1639                 return DP_AUX_CH_CTL(AUX_CH_A);
1640         }
1641 }
1642
1643 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1644 {
1645         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1646         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1647         enum aux_ch aux_ch = dig_port->aux_ch;
1648
1649         switch (aux_ch) {
1650         case AUX_CH_A:
1651                 return DP_AUX_CH_DATA(aux_ch, index);
1652         case AUX_CH_B:
1653         case AUX_CH_C:
1654         case AUX_CH_D:
1655                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1656         default:
1657                 MISSING_CASE(aux_ch);
1658                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1659         }
1660 }
1661
1662 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1663 {
1664         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1665         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1666         enum aux_ch aux_ch = dig_port->aux_ch;
1667
1668         switch (aux_ch) {
1669         case AUX_CH_A:
1670         case AUX_CH_B:
1671         case AUX_CH_C:
1672         case AUX_CH_D:
1673         case AUX_CH_E:
1674         case AUX_CH_F:
1675         case AUX_CH_G:
1676                 return DP_AUX_CH_CTL(aux_ch);
1677         default:
1678                 MISSING_CASE(aux_ch);
1679                 return DP_AUX_CH_CTL(AUX_CH_A);
1680         }
1681 }
1682
1683 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1684 {
1685         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1686         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1687         enum aux_ch aux_ch = dig_port->aux_ch;
1688
1689         switch (aux_ch) {
1690         case AUX_CH_A:
1691         case AUX_CH_B:
1692         case AUX_CH_C:
1693         case AUX_CH_D:
1694         case AUX_CH_E:
1695         case AUX_CH_F:
1696         case AUX_CH_G:
1697                 return DP_AUX_CH_DATA(aux_ch, index);
1698         default:
1699                 MISSING_CASE(aux_ch);
1700                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1701         }
1702 }
1703
1704 static void
1705 intel_dp_aux_fini(struct intel_dp *intel_dp)
1706 {
1707         kfree(intel_dp->aux.name);
1708 }
1709
1710 static void
1711 intel_dp_aux_init(struct intel_dp *intel_dp)
1712 {
1713         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1714         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1715         struct intel_encoder *encoder = &dig_port->base;
1716
1717         if (INTEL_GEN(dev_priv) >= 9) {
1718                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1719                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1720         } else if (HAS_PCH_SPLIT(dev_priv)) {
1721                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1722                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1723         } else {
1724                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1725                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1726         }
1727
1728         if (INTEL_GEN(dev_priv) >= 9)
1729                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1730         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1731                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1732         else if (HAS_PCH_SPLIT(dev_priv))
1733                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1734         else
1735                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1736
1737         if (INTEL_GEN(dev_priv) >= 9)
1738                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1739         else
1740                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1741
1742         drm_dp_aux_init(&intel_dp->aux);
1743
1744         /* Failure to allocate our preferred name is not critical */
1745         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1746                                        port_name(encoder->port));
1747         intel_dp->aux.transfer = intel_dp_aux_transfer;
1748 }
1749
1750 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1751 {
1752         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1753
1754         return max_rate >= 540000;
1755 }
1756
1757 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1758 {
1759         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1760
1761         return max_rate >= 810000;
1762 }
1763
1764 static void
1765 intel_dp_set_clock(struct intel_encoder *encoder,
1766                    struct intel_crtc_state *pipe_config)
1767 {
1768         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1769         const struct dp_link_dpll *divisor = NULL;
1770         int i, count = 0;
1771
1772         if (IS_G4X(dev_priv)) {
1773                 divisor = g4x_dpll;
1774                 count = ARRAY_SIZE(g4x_dpll);
1775         } else if (HAS_PCH_SPLIT(dev_priv)) {
1776                 divisor = pch_dpll;
1777                 count = ARRAY_SIZE(pch_dpll);
1778         } else if (IS_CHERRYVIEW(dev_priv)) {
1779                 divisor = chv_dpll;
1780                 count = ARRAY_SIZE(chv_dpll);
1781         } else if (IS_VALLEYVIEW(dev_priv)) {
1782                 divisor = vlv_dpll;
1783                 count = ARRAY_SIZE(vlv_dpll);
1784         }
1785
1786         if (divisor && count) {
1787                 for (i = 0; i < count; i++) {
1788                         if (pipe_config->port_clock == divisor[i].clock) {
1789                                 pipe_config->dpll = divisor[i].dpll;
1790                                 pipe_config->clock_set = true;
1791                                 break;
1792                         }
1793                 }
1794         }
1795 }
1796
1797 static void snprintf_int_array(char *str, size_t len,
1798                                const int *array, int nelem)
1799 {
1800         int i;
1801
1802         str[0] = '\0';
1803
1804         for (i = 0; i < nelem; i++) {
1805                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1806                 if (r >= len)
1807                         return;
1808                 str += r;
1809                 len -= r;
1810         }
1811 }
1812
1813 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1814 {
1815         char str[128]; /* FIXME: too big for stack? */
1816
1817         if ((drm_debug & DRM_UT_KMS) == 0)
1818                 return;
1819
1820         snprintf_int_array(str, sizeof(str),
1821                            intel_dp->source_rates, intel_dp->num_source_rates);
1822         DRM_DEBUG_KMS("source rates: %s\n", str);
1823
1824         snprintf_int_array(str, sizeof(str),
1825                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1826         DRM_DEBUG_KMS("sink rates: %s\n", str);
1827
1828         snprintf_int_array(str, sizeof(str),
1829                            intel_dp->common_rates, intel_dp->num_common_rates);
1830         DRM_DEBUG_KMS("common rates: %s\n", str);
1831 }
1832
1833 int
1834 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1835 {
1836         int len;
1837
1838         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1839         if (WARN_ON(len <= 0))
1840                 return 162000;
1841
1842         return intel_dp->common_rates[len - 1];
1843 }
1844
1845 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1846 {
1847         int i = intel_dp_rate_index(intel_dp->sink_rates,
1848                                     intel_dp->num_sink_rates, rate);
1849
1850         if (WARN_ON(i < 0))
1851                 i = 0;
1852
1853         return i;
1854 }
1855
1856 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1857                            u8 *link_bw, u8 *rate_select)
1858 {
1859         /* eDP 1.4 rate select method. */
1860         if (intel_dp->use_rate_select) {
1861                 *link_bw = 0;
1862                 *rate_select =
1863                         intel_dp_rate_select(intel_dp, port_clock);
1864         } else {
1865                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1866                 *rate_select = 0;
1867         }
1868 }
1869
1870 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1871                                          const struct intel_crtc_state *pipe_config)
1872 {
1873         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1874
1875         /* On TGL, FEC is supported on all Pipes */
1876         if (INTEL_GEN(dev_priv) >= 12)
1877                 return true;
1878
1879         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1880                 return true;
1881
1882         return false;
1883 }
1884
1885 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1886                                   const struct intel_crtc_state *pipe_config)
1887 {
1888         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1889                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1890 }
1891
1892 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1893                                          const struct intel_crtc_state *pipe_config)
1894 {
1895         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1896
1897         if (!INTEL_INFO(dev_priv)->display.has_dsc)
1898                 return false;
1899
1900         /* On TGL, DSC is supported on all Pipes */
1901         if (INTEL_GEN(dev_priv) >= 12)
1902                 return true;
1903
1904         if (INTEL_GEN(dev_priv) >= 10 &&
1905             pipe_config->cpu_transcoder != TRANSCODER_A)
1906                 return true;
1907
1908         return false;
1909 }
1910
1911 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1912                                   const struct intel_crtc_state *pipe_config)
1913 {
1914         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1915                 return false;
1916
1917         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1918                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1919 }
1920
1921 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1922                                 struct intel_crtc_state *pipe_config)
1923 {
1924         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1925         struct intel_connector *intel_connector = intel_dp->attached_connector;
1926         int bpp, bpc;
1927
1928         bpp = pipe_config->pipe_bpp;
1929         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1930
1931         if (bpc > 0)
1932                 bpp = min(bpp, 3*bpc);
1933
1934         if (intel_dp_is_edp(intel_dp)) {
1935                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1936                 if (intel_connector->base.display_info.bpc == 0 &&
1937                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1938                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1939                                       dev_priv->vbt.edp.bpp);
1940                         bpp = dev_priv->vbt.edp.bpp;
1941                 }
1942         }
1943
1944         return bpp;
1945 }
1946
1947 /* Adjust link config limits based on compliance test requests. */
1948 void
1949 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1950                                   struct intel_crtc_state *pipe_config,
1951                                   struct link_config_limits *limits)
1952 {
1953         /* For DP Compliance we override the computed bpp for the pipe */
1954         if (intel_dp->compliance.test_data.bpc != 0) {
1955                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1956
1957                 limits->min_bpp = limits->max_bpp = bpp;
1958                 pipe_config->dither_force_disable = bpp == 6 * 3;
1959
1960                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1961         }
1962
1963         /* Use values requested by Compliance Test Request */
1964         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1965                 int index;
1966
1967                 /* Validate the compliance test data since max values
1968                  * might have changed due to link train fallback.
1969                  */
1970                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1971                                                intel_dp->compliance.test_lane_count)) {
1972                         index = intel_dp_rate_index(intel_dp->common_rates,
1973                                                     intel_dp->num_common_rates,
1974                                                     intel_dp->compliance.test_link_rate);
1975                         if (index >= 0)
1976                                 limits->min_clock = limits->max_clock = index;
1977                         limits->min_lane_count = limits->max_lane_count =
1978                                 intel_dp->compliance.test_lane_count;
1979                 }
1980         }
1981 }
1982
1983 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1984 {
1985         /*
1986          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1987          * format of the number of bytes per pixel will be half the number
1988          * of bytes of RGB pixel.
1989          */
1990         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1991                 bpp /= 2;
1992
1993         return bpp;
1994 }
1995
1996 /* Optimize link config in order: max bpp, min clock, min lanes */
1997 static int
1998 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1999                                   struct intel_crtc_state *pipe_config,
2000                                   const struct link_config_limits *limits)
2001 {
2002         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2003         int bpp, clock, lane_count;
2004         int mode_rate, link_clock, link_avail;
2005
2006         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2007                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2008
2009                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2010                                                    output_bpp);
2011
2012                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2013                         for (lane_count = limits->min_lane_count;
2014                              lane_count <= limits->max_lane_count;
2015                              lane_count <<= 1) {
2016                                 link_clock = intel_dp->common_rates[clock];
2017                                 link_avail = intel_dp_max_data_rate(link_clock,
2018                                                                     lane_count);
2019
2020                                 if (mode_rate <= link_avail) {
2021                                         pipe_config->lane_count = lane_count;
2022                                         pipe_config->pipe_bpp = bpp;
2023                                         pipe_config->port_clock = link_clock;
2024
2025                                         return 0;
2026                                 }
2027                         }
2028                 }
2029         }
2030
2031         return -EINVAL;
2032 }
2033
2034 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2035 {
2036         int i, num_bpc;
2037         u8 dsc_bpc[3] = {0};
2038
2039         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2040                                                        dsc_bpc);
2041         for (i = 0; i < num_bpc; i++) {
2042                 if (dsc_max_bpc >= dsc_bpc[i])
2043                         return dsc_bpc[i] * 3;
2044         }
2045
2046         return 0;
2047 }
2048
2049 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2050                                        struct intel_crtc_state *pipe_config,
2051                                        struct drm_connector_state *conn_state,
2052                                        struct link_config_limits *limits)
2053 {
2054         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2055         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2056         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2057         u8 dsc_max_bpc;
2058         int pipe_bpp;
2059         int ret;
2060
2061         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2062                 intel_dp_supports_fec(intel_dp, pipe_config);
2063
2064         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2065                 return -EINVAL;
2066
2067         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2068         if (INTEL_GEN(dev_priv) >= 12)
2069                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2070         else
2071                 dsc_max_bpc = min_t(u8, 10,
2072                                     conn_state->max_requested_bpc);
2073
2074         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2075
2076         /* Min Input BPC for ICL+ is 8 */
2077         if (pipe_bpp < 8 * 3) {
2078                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
2079                 return -EINVAL;
2080         }
2081
2082         /*
2083          * For now enable DSC for max bpp, max link rate, max lane count.
2084          * Optimize this later for the minimum possible link rate/lane count
2085          * with DSC enabled for the requested mode.
2086          */
2087         pipe_config->pipe_bpp = pipe_bpp;
2088         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2089         pipe_config->lane_count = limits->max_lane_count;
2090
2091         if (intel_dp_is_edp(intel_dp)) {
2092                 pipe_config->dsc.compressed_bpp =
2093                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2094                               pipe_config->pipe_bpp);
2095                 pipe_config->dsc.slice_count =
2096                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2097                                                         true);
2098         } else {
2099                 u16 dsc_max_output_bpp;
2100                 u8 dsc_dp_slice_count;
2101
2102                 dsc_max_output_bpp =
2103                         intel_dp_dsc_get_output_bpp(dev_priv,
2104                                                     pipe_config->port_clock,
2105                                                     pipe_config->lane_count,
2106                                                     adjusted_mode->crtc_clock,
2107                                                     adjusted_mode->crtc_hdisplay);
2108                 dsc_dp_slice_count =
2109                         intel_dp_dsc_get_slice_count(intel_dp,
2110                                                      adjusted_mode->crtc_clock,
2111                                                      adjusted_mode->crtc_hdisplay);
2112                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2113                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
2114                         return -EINVAL;
2115                 }
2116                 pipe_config->dsc.compressed_bpp = min_t(u16,
2117                                                                dsc_max_output_bpp >> 4,
2118                                                                pipe_config->pipe_bpp);
2119                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2120         }
2121         /*
2122          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2123          * is greater than the maximum Cdclock and if slice count is even
2124          * then we need to use 2 VDSC instances.
2125          */
2126         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2127                 if (pipe_config->dsc.slice_count > 1) {
2128                         pipe_config->dsc.dsc_split = true;
2129                 } else {
2130                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
2131                         return -EINVAL;
2132                 }
2133         }
2134
2135         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
2136         if (ret < 0) {
2137                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2138                               "Compressed BPP = %d\n",
2139                               pipe_config->pipe_bpp,
2140                               pipe_config->dsc.compressed_bpp);
2141                 return ret;
2142         }
2143
2144         pipe_config->dsc.compression_enable = true;
2145         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2146                       "Compressed Bpp = %d Slice Count = %d\n",
2147                       pipe_config->pipe_bpp,
2148                       pipe_config->dsc.compressed_bpp,
2149                       pipe_config->dsc.slice_count);
2150
2151         return 0;
2152 }
2153
2154 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2155 {
2156         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2157                 return 6 * 3;
2158         else
2159                 return 8 * 3;
2160 }
2161
2162 static int
2163 intel_dp_compute_link_config(struct intel_encoder *encoder,
2164                              struct intel_crtc_state *pipe_config,
2165                              struct drm_connector_state *conn_state)
2166 {
2167         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2168         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2169         struct link_config_limits limits;
2170         int common_len;
2171         int ret;
2172
2173         common_len = intel_dp_common_len_rate_limit(intel_dp,
2174                                                     intel_dp->max_link_rate);
2175
2176         /* No common link rates between source and sink */
2177         WARN_ON(common_len <= 0);
2178
2179         limits.min_clock = 0;
2180         limits.max_clock = common_len - 1;
2181
2182         limits.min_lane_count = 1;
2183         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2184
2185         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2186         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2187
2188         if (intel_dp_is_edp(intel_dp)) {
2189                 /*
2190                  * Use the maximum clock and number of lanes the eDP panel
2191                  * advertizes being capable of. The panels are generally
2192                  * designed to support only a single clock and lane
2193                  * configuration, and typically these values correspond to the
2194                  * native resolution of the panel.
2195                  */
2196                 limits.min_lane_count = limits.max_lane_count;
2197                 limits.min_clock = limits.max_clock;
2198         }
2199
2200         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2201
2202         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2203                       "max rate %d max bpp %d pixel clock %iKHz\n",
2204                       limits.max_lane_count,
2205                       intel_dp->common_rates[limits.max_clock],
2206                       limits.max_bpp, adjusted_mode->crtc_clock);
2207
2208         /*
2209          * Optimize for slow and wide. This is the place to add alternative
2210          * optimization policy.
2211          */
2212         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2213
2214         /* enable compression if the mode doesn't fit available BW */
2215         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2216         if (ret || intel_dp->force_dsc_en) {
2217                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2218                                                   conn_state, &limits);
2219                 if (ret < 0)
2220                         return ret;
2221         }
2222
2223         if (pipe_config->dsc.compression_enable) {
2224                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2225                               pipe_config->lane_count, pipe_config->port_clock,
2226                               pipe_config->pipe_bpp,
2227                               pipe_config->dsc.compressed_bpp);
2228
2229                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2230                               intel_dp_link_required(adjusted_mode->crtc_clock,
2231                                                      pipe_config->dsc.compressed_bpp),
2232                               intel_dp_max_data_rate(pipe_config->port_clock,
2233                                                      pipe_config->lane_count));
2234         } else {
2235                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2236                               pipe_config->lane_count, pipe_config->port_clock,
2237                               pipe_config->pipe_bpp);
2238
2239                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2240                               intel_dp_link_required(adjusted_mode->crtc_clock,
2241                                                      pipe_config->pipe_bpp),
2242                               intel_dp_max_data_rate(pipe_config->port_clock,
2243                                                      pipe_config->lane_count));
2244         }
2245         return 0;
2246 }
2247
2248 static int
2249 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2250                          struct drm_connector *connector,
2251                          struct intel_crtc_state *crtc_state)
2252 {
2253         const struct drm_display_info *info = &connector->display_info;
2254         const struct drm_display_mode *adjusted_mode =
2255                 &crtc_state->base.adjusted_mode;
2256         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2257         int ret;
2258
2259         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2260             !intel_dp_get_colorimetry_status(intel_dp) ||
2261             !connector->ycbcr_420_allowed)
2262                 return 0;
2263
2264         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2265
2266         /* YCBCR 420 output conversion needs a scaler */
2267         ret = skl_update_scaler_crtc(crtc_state);
2268         if (ret) {
2269                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2270                 return ret;
2271         }
2272
2273         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2274
2275         return 0;
2276 }
2277
2278 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2279                                   const struct drm_connector_state *conn_state)
2280 {
2281         const struct intel_digital_connector_state *intel_conn_state =
2282                 to_intel_digital_connector_state(conn_state);
2283         const struct drm_display_mode *adjusted_mode =
2284                 &crtc_state->base.adjusted_mode;
2285
2286         /*
2287          * Our YCbCr output is always limited range.
2288          * crtc_state->limited_color_range only applies to RGB,
2289          * and it must never be set for YCbCr or we risk setting
2290          * some conflicting bits in PIPECONF which will mess up
2291          * the colors on the monitor.
2292          */
2293         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2294                 return false;
2295
2296         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2297                 /*
2298                  * See:
2299                  * CEA-861-E - 5.1 Default Encoding Parameters
2300                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2301                  */
2302                 return crtc_state->pipe_bpp != 18 &&
2303                         drm_default_rgb_quant_range(adjusted_mode) ==
2304                         HDMI_QUANTIZATION_RANGE_LIMITED;
2305         } else {
2306                 return intel_conn_state->broadcast_rgb ==
2307                         INTEL_BROADCAST_RGB_LIMITED;
2308         }
2309 }
2310
2311 int
2312 intel_dp_compute_config(struct intel_encoder *encoder,
2313                         struct intel_crtc_state *pipe_config,
2314                         struct drm_connector_state *conn_state)
2315 {
2316         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2317         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2318         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2319         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2320         enum port port = encoder->port;
2321         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2322         struct intel_connector *intel_connector = intel_dp->attached_connector;
2323         struct intel_digital_connector_state *intel_conn_state =
2324                 to_intel_digital_connector_state(conn_state);
2325         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2326                                            DP_DPCD_QUIRK_CONSTANT_N);
2327         int ret = 0, output_bpp;
2328
2329         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2330                 pipe_config->has_pch_encoder = true;
2331
2332         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2333
2334         if (lspcon->active)
2335                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2336         else
2337                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2338                                                pipe_config);
2339
2340         if (ret)
2341                 return ret;
2342
2343         pipe_config->has_drrs = false;
2344         if (IS_G4X(dev_priv) || port == PORT_A)
2345                 pipe_config->has_audio = false;
2346         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2347                 pipe_config->has_audio = intel_dp->has_audio;
2348         else
2349                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2350
2351         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2352                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2353                                        adjusted_mode);
2354
2355                 if (INTEL_GEN(dev_priv) >= 9) {
2356                         ret = skl_update_scaler_crtc(pipe_config);
2357                         if (ret)
2358                                 return ret;
2359                 }
2360
2361                 if (HAS_GMCH(dev_priv))
2362                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2363                                                  conn_state->scaling_mode);
2364                 else
2365                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2366                                                 conn_state->scaling_mode);
2367         }
2368
2369         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2370                 return -EINVAL;
2371
2372         if (HAS_GMCH(dev_priv) &&
2373             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2374                 return -EINVAL;
2375
2376         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2377                 return -EINVAL;
2378
2379         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2380                 return -EINVAL;
2381
2382         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2383         if (ret < 0)
2384                 return ret;
2385
2386         pipe_config->limited_color_range =
2387                 intel_dp_limited_color_range(pipe_config, conn_state);
2388
2389         if (pipe_config->dsc.compression_enable)
2390                 output_bpp = pipe_config->dsc.compressed_bpp;
2391         else
2392                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2393
2394         intel_link_compute_m_n(output_bpp,
2395                                pipe_config->lane_count,
2396                                adjusted_mode->crtc_clock,
2397                                pipe_config->port_clock,
2398                                &pipe_config->dp_m_n,
2399                                constant_n, pipe_config->fec_enable);
2400
2401         if (intel_connector->panel.downclock_mode != NULL &&
2402                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2403                         pipe_config->has_drrs = true;
2404                         intel_link_compute_m_n(output_bpp,
2405                                                pipe_config->lane_count,
2406                                                intel_connector->panel.downclock_mode->clock,
2407                                                pipe_config->port_clock,
2408                                                &pipe_config->dp_m2_n2,
2409                                                constant_n, pipe_config->fec_enable);
2410         }
2411
2412         if (!HAS_DDI(dev_priv))
2413                 intel_dp_set_clock(encoder, pipe_config);
2414
2415         intel_psr_compute_config(intel_dp, pipe_config);
2416
2417         intel_hdcp_transcoder_config(intel_connector,
2418                                      pipe_config->cpu_transcoder);
2419
2420         return 0;
2421 }
2422
2423 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2424                               int link_rate, u8 lane_count,
2425                               bool link_mst)
2426 {
2427         intel_dp->link_trained = false;
2428         intel_dp->link_rate = link_rate;
2429         intel_dp->lane_count = lane_count;
2430         intel_dp->link_mst = link_mst;
2431 }
2432
2433 static void intel_dp_prepare(struct intel_encoder *encoder,
2434                              const struct intel_crtc_state *pipe_config)
2435 {
2436         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2437         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2438         enum port port = encoder->port;
2439         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2440         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2441
2442         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2443                                  pipe_config->lane_count,
2444                                  intel_crtc_has_type(pipe_config,
2445                                                      INTEL_OUTPUT_DP_MST));
2446
2447         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2448         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2449
2450         /*
2451          * There are four kinds of DP registers:
2452          *
2453          *      IBX PCH
2454          *      SNB CPU
2455          *      IVB CPU
2456          *      CPT PCH
2457          *
2458          * IBX PCH and CPU are the same for almost everything,
2459          * except that the CPU DP PLL is configured in this
2460          * register
2461          *
2462          * CPT PCH is quite different, having many bits moved
2463          * to the TRANS_DP_CTL register instead. That
2464          * configuration happens (oddly) in ironlake_pch_enable
2465          */
2466
2467         /* Preserve the BIOS-computed detected bit. This is
2468          * supposed to be read-only.
2469          */
2470         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2471
2472         /* Handle DP bits in common between all three register formats */
2473         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2474         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2475
2476         /* Split out the IBX/CPU vs CPT settings */
2477
2478         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2479                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2480                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2481                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2482                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2483                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2484
2485                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2486                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2487
2488                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2489         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2490                 u32 trans_dp;
2491
2492                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2493
2494                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2495                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2496                         trans_dp |= TRANS_DP_ENH_FRAMING;
2497                 else
2498                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2499                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2500         } else {
2501                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2502                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2503
2504                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2505                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2506                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2507                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2508                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2509
2510                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2511                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2512
2513                 if (IS_CHERRYVIEW(dev_priv))
2514                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2515                 else
2516                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2517         }
2518 }
2519
2520 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2521 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2522
2523 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2524 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2525
2526 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2527 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2528
2529 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2530
2531 static void wait_panel_status(struct intel_dp *intel_dp,
2532                                        u32 mask,
2533                                        u32 value)
2534 {
2535         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2536         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2537
2538         lockdep_assert_held(&dev_priv->pps_mutex);
2539
2540         intel_pps_verify_state(intel_dp);
2541
2542         pp_stat_reg = _pp_stat_reg(intel_dp);
2543         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2544
2545         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2546                         mask, value,
2547                         I915_READ(pp_stat_reg),
2548                         I915_READ(pp_ctrl_reg));
2549
2550         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2551                                        mask, value, 5000))
2552                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2553                                 I915_READ(pp_stat_reg),
2554                                 I915_READ(pp_ctrl_reg));
2555
2556         DRM_DEBUG_KMS("Wait complete\n");
2557 }
2558
2559 static void wait_panel_on(struct intel_dp *intel_dp)
2560 {
2561         DRM_DEBUG_KMS("Wait for panel power on\n");
2562         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2563 }
2564
2565 static void wait_panel_off(struct intel_dp *intel_dp)
2566 {
2567         DRM_DEBUG_KMS("Wait for panel power off time\n");
2568         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2569 }
2570
2571 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2572 {
2573         ktime_t panel_power_on_time;
2574         s64 panel_power_off_duration;
2575
2576         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2577
2578         /* take the difference of currrent time and panel power off time
2579          * and then make panel wait for t11_t12 if needed. */
2580         panel_power_on_time = ktime_get_boottime();
2581         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2582
2583         /* When we disable the VDD override bit last we have to do the manual
2584          * wait. */
2585         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2586                 wait_remaining_ms_from_jiffies(jiffies,
2587                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2588
2589         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2590 }
2591
2592 static void wait_backlight_on(struct intel_dp *intel_dp)
2593 {
2594         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2595                                        intel_dp->backlight_on_delay);
2596 }
2597
2598 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2599 {
2600         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2601                                        intel_dp->backlight_off_delay);
2602 }
2603
2604 /* Read the current pp_control value, unlocking the register if it
2605  * is locked
2606  */
2607
2608 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2609 {
2610         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2611         u32 control;
2612
2613         lockdep_assert_held(&dev_priv->pps_mutex);
2614
2615         control = I915_READ(_pp_ctrl_reg(intel_dp));
2616         if (WARN_ON(!HAS_DDI(dev_priv) &&
2617                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2618                 control &= ~PANEL_UNLOCK_MASK;
2619                 control |= PANEL_UNLOCK_REGS;
2620         }
2621         return control;
2622 }
2623
2624 /*
2625  * Must be paired with edp_panel_vdd_off().
2626  * Must hold pps_mutex around the whole on/off sequence.
2627  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2628  */
2629 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2630 {
2631         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2632         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2633         u32 pp;
2634         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2635         bool need_to_disable = !intel_dp->want_panel_vdd;
2636
2637         lockdep_assert_held(&dev_priv->pps_mutex);
2638
2639         if (!intel_dp_is_edp(intel_dp))
2640                 return false;
2641
2642         cancel_delayed_work(&intel_dp->panel_vdd_work);
2643         intel_dp->want_panel_vdd = true;
2644
2645         if (edp_have_panel_vdd(intel_dp))
2646                 return need_to_disable;
2647
2648         intel_display_power_get(dev_priv,
2649                                 intel_aux_power_domain(intel_dig_port));
2650
2651         DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n",
2652                       intel_dig_port->base.base.base.id,
2653                       intel_dig_port->base.base.name);
2654
2655         if (!edp_have_panel_power(intel_dp))
2656                 wait_panel_power_cycle(intel_dp);
2657
2658         pp = ironlake_get_pp_control(intel_dp);
2659         pp |= EDP_FORCE_VDD;
2660
2661         pp_stat_reg = _pp_stat_reg(intel_dp);
2662         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2663
2664         I915_WRITE(pp_ctrl_reg, pp);
2665         POSTING_READ(pp_ctrl_reg);
2666         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2667                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2668         /*
2669          * If the panel wasn't on, delay before accessing aux channel
2670          */
2671         if (!edp_have_panel_power(intel_dp)) {
2672                 DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n",
2673                               intel_dig_port->base.base.base.id,
2674                               intel_dig_port->base.base.name);
2675                 msleep(intel_dp->panel_power_up_delay);
2676         }
2677
2678         return need_to_disable;
2679 }
2680
2681 /*
2682  * Must be paired with intel_edp_panel_vdd_off() or
2683  * intel_edp_panel_off().
2684  * Nested calls to these functions are not allowed since
2685  * we drop the lock. Caller must use some higher level
2686  * locking to prevent nested calls from other threads.
2687  */
2688 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2689 {
2690         intel_wakeref_t wakeref;
2691         bool vdd;
2692
2693         if (!intel_dp_is_edp(intel_dp))
2694                 return;
2695
2696         vdd = false;
2697         with_pps_lock(intel_dp, wakeref)
2698                 vdd = edp_panel_vdd_on(intel_dp);
2699         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2700                         dp_to_dig_port(intel_dp)->base.base.base.id,
2701                         dp_to_dig_port(intel_dp)->base.base.name);
2702 }
2703
2704 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2705 {
2706         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2707         struct intel_digital_port *intel_dig_port =
2708                 dp_to_dig_port(intel_dp);
2709         u32 pp;
2710         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2711
2712         lockdep_assert_held(&dev_priv->pps_mutex);
2713
2714         WARN_ON(intel_dp->want_panel_vdd);
2715
2716         if (!edp_have_panel_vdd(intel_dp))
2717                 return;
2718
2719         DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n",
2720                       intel_dig_port->base.base.base.id,
2721                       intel_dig_port->base.base.name);
2722
2723         pp = ironlake_get_pp_control(intel_dp);
2724         pp &= ~EDP_FORCE_VDD;
2725
2726         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2727         pp_stat_reg = _pp_stat_reg(intel_dp);
2728
2729         I915_WRITE(pp_ctrl_reg, pp);
2730         POSTING_READ(pp_ctrl_reg);
2731
2732         /* Make sure sequencer is idle before allowing subsequent activity */
2733         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2734         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2735
2736         if ((pp & PANEL_POWER_ON) == 0)
2737                 intel_dp->panel_power_off_time = ktime_get_boottime();
2738
2739         intel_display_power_put_unchecked(dev_priv,
2740                                           intel_aux_power_domain(intel_dig_port));
2741 }
2742
2743 static void edp_panel_vdd_work(struct work_struct *__work)
2744 {
2745         struct intel_dp *intel_dp =
2746                 container_of(to_delayed_work(__work),
2747                              struct intel_dp, panel_vdd_work);
2748         intel_wakeref_t wakeref;
2749
2750         with_pps_lock(intel_dp, wakeref) {
2751                 if (!intel_dp->want_panel_vdd)
2752                         edp_panel_vdd_off_sync(intel_dp);
2753         }
2754 }
2755
2756 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2757 {
2758         unsigned long delay;
2759
2760         /*
2761          * Queue the timer to fire a long time from now (relative to the power
2762          * down delay) to keep the panel power up across a sequence of
2763          * operations.
2764          */
2765         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2766         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2767 }
2768
2769 /*
2770  * Must be paired with edp_panel_vdd_on().
2771  * Must hold pps_mutex around the whole on/off sequence.
2772  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2773  */
2774 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2775 {
2776         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2777
2778         lockdep_assert_held(&dev_priv->pps_mutex);
2779
2780         if (!intel_dp_is_edp(intel_dp))
2781                 return;
2782
2783         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2784                         dp_to_dig_port(intel_dp)->base.base.base.id,
2785                         dp_to_dig_port(intel_dp)->base.base.name);
2786
2787         intel_dp->want_panel_vdd = false;
2788
2789         if (sync)
2790                 edp_panel_vdd_off_sync(intel_dp);
2791         else
2792                 edp_panel_vdd_schedule_off(intel_dp);
2793 }
2794
2795 static void edp_panel_on(struct intel_dp *intel_dp)
2796 {
2797         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2798         u32 pp;
2799         i915_reg_t pp_ctrl_reg;
2800
2801         lockdep_assert_held(&dev_priv->pps_mutex);
2802
2803         if (!intel_dp_is_edp(intel_dp))
2804                 return;
2805
2806         DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n",
2807                       dp_to_dig_port(intel_dp)->base.base.base.id,
2808                       dp_to_dig_port(intel_dp)->base.base.name);
2809
2810         if (WARN(edp_have_panel_power(intel_dp),
2811                  "[ENCODER:%d:%s] panel power already on\n",
2812                  dp_to_dig_port(intel_dp)->base.base.base.id,
2813                  dp_to_dig_port(intel_dp)->base.base.name))
2814                 return;
2815
2816         wait_panel_power_cycle(intel_dp);
2817
2818         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2819         pp = ironlake_get_pp_control(intel_dp);
2820         if (IS_GEN(dev_priv, 5)) {
2821                 /* ILK workaround: disable reset around power sequence */
2822                 pp &= ~PANEL_POWER_RESET;
2823                 I915_WRITE(pp_ctrl_reg, pp);
2824                 POSTING_READ(pp_ctrl_reg);
2825         }
2826
2827         pp |= PANEL_POWER_ON;
2828         if (!IS_GEN(dev_priv, 5))
2829                 pp |= PANEL_POWER_RESET;
2830
2831         I915_WRITE(pp_ctrl_reg, pp);
2832         POSTING_READ(pp_ctrl_reg);
2833
2834         wait_panel_on(intel_dp);
2835         intel_dp->last_power_on = jiffies;
2836
2837         if (IS_GEN(dev_priv, 5)) {
2838                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2839                 I915_WRITE(pp_ctrl_reg, pp);
2840                 POSTING_READ(pp_ctrl_reg);
2841         }
2842 }
2843
2844 void intel_edp_panel_on(struct intel_dp *intel_dp)
2845 {
2846         intel_wakeref_t wakeref;
2847
2848         if (!intel_dp_is_edp(intel_dp))
2849                 return;
2850
2851         with_pps_lock(intel_dp, wakeref)
2852                 edp_panel_on(intel_dp);
2853 }
2854
2855
2856 static void edp_panel_off(struct intel_dp *intel_dp)
2857 {
2858         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2859         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2860         u32 pp;
2861         i915_reg_t pp_ctrl_reg;
2862
2863         lockdep_assert_held(&dev_priv->pps_mutex);
2864
2865         if (!intel_dp_is_edp(intel_dp))
2866                 return;
2867
2868         DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n",
2869                       dig_port->base.base.base.id, dig_port->base.base.name);
2870
2871         WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2872              dig_port->base.base.base.id, dig_port->base.base.name);
2873
2874         pp = ironlake_get_pp_control(intel_dp);
2875         /* We need to switch off panel power _and_ force vdd, for otherwise some
2876          * panels get very unhappy and cease to work. */
2877         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2878                 EDP_BLC_ENABLE);
2879
2880         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2881
2882         intel_dp->want_panel_vdd = false;
2883
2884         I915_WRITE(pp_ctrl_reg, pp);
2885         POSTING_READ(pp_ctrl_reg);
2886
2887         wait_panel_off(intel_dp);
2888         intel_dp->panel_power_off_time = ktime_get_boottime();
2889
2890         /* We got a reference when we enabled the VDD. */
2891         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2892 }
2893
2894 void intel_edp_panel_off(struct intel_dp *intel_dp)
2895 {
2896         intel_wakeref_t wakeref;
2897
2898         if (!intel_dp_is_edp(intel_dp))
2899                 return;
2900
2901         with_pps_lock(intel_dp, wakeref)
2902                 edp_panel_off(intel_dp);
2903 }
2904
2905 /* Enable backlight in the panel power control. */
2906 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2907 {
2908         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2909         intel_wakeref_t wakeref;
2910
2911         /*
2912          * If we enable the backlight right away following a panel power
2913          * on, we may see slight flicker as the panel syncs with the eDP
2914          * link.  So delay a bit to make sure the image is solid before
2915          * allowing it to appear.
2916          */
2917         wait_backlight_on(intel_dp);
2918
2919         with_pps_lock(intel_dp, wakeref) {
2920                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2921                 u32 pp;
2922
2923                 pp = ironlake_get_pp_control(intel_dp);
2924                 pp |= EDP_BLC_ENABLE;
2925
2926                 I915_WRITE(pp_ctrl_reg, pp);
2927                 POSTING_READ(pp_ctrl_reg);
2928         }
2929 }
2930
2931 /* Enable backlight PWM and backlight PP control. */
2932 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2933                             const struct drm_connector_state *conn_state)
2934 {
2935         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2936
2937         if (!intel_dp_is_edp(intel_dp))
2938                 return;
2939
2940         DRM_DEBUG_KMS("\n");
2941
2942         intel_panel_enable_backlight(crtc_state, conn_state);
2943         _intel_edp_backlight_on(intel_dp);
2944 }
2945
2946 /* Disable backlight in the panel power control. */
2947 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2948 {
2949         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2950         intel_wakeref_t wakeref;
2951
2952         if (!intel_dp_is_edp(intel_dp))
2953                 return;
2954
2955         with_pps_lock(intel_dp, wakeref) {
2956                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2957                 u32 pp;
2958
2959                 pp = ironlake_get_pp_control(intel_dp);
2960                 pp &= ~EDP_BLC_ENABLE;
2961
2962                 I915_WRITE(pp_ctrl_reg, pp);
2963                 POSTING_READ(pp_ctrl_reg);
2964         }
2965
2966         intel_dp->last_backlight_off = jiffies;
2967         edp_wait_backlight_off(intel_dp);
2968 }
2969
2970 /* Disable backlight PP control and backlight PWM. */
2971 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2972 {
2973         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2974
2975         if (!intel_dp_is_edp(intel_dp))
2976                 return;
2977
2978         DRM_DEBUG_KMS("\n");
2979
2980         _intel_edp_backlight_off(intel_dp);
2981         intel_panel_disable_backlight(old_conn_state);
2982 }
2983
2984 /*
2985  * Hook for controlling the panel power control backlight through the bl_power
2986  * sysfs attribute. Take care to handle multiple calls.
2987  */
2988 static void intel_edp_backlight_power(struct intel_connector *connector,
2989                                       bool enable)
2990 {
2991         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2992         intel_wakeref_t wakeref;
2993         bool is_enabled;
2994
2995         is_enabled = false;
2996         with_pps_lock(intel_dp, wakeref)
2997                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2998         if (is_enabled == enable)
2999                 return;
3000
3001         DRM_DEBUG_KMS("panel power control backlight %s\n",
3002                       enable ? "enable" : "disable");
3003
3004         if (enable)
3005                 _intel_edp_backlight_on(intel_dp);
3006         else
3007                 _intel_edp_backlight_off(intel_dp);
3008 }
3009
3010 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3011 {
3012         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3013         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3014         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
3015
3016         I915_STATE_WARN(cur_state != state,
3017                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3018                         dig_port->base.base.base.id, dig_port->base.base.name,
3019                         onoff(state), onoff(cur_state));
3020 }
3021 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3022
3023 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3024 {
3025         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
3026
3027         I915_STATE_WARN(cur_state != state,
3028                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3029                         onoff(state), onoff(cur_state));
3030 }
3031 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3032 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3033
3034 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
3035                                 const struct intel_crtc_state *pipe_config)
3036 {
3037         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3038         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3039
3040         assert_pipe_disabled(dev_priv, crtc->pipe);
3041         assert_dp_port_disabled(intel_dp);
3042         assert_edp_pll_disabled(dev_priv);
3043
3044         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
3045                       pipe_config->port_clock);
3046
3047         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3048
3049         if (pipe_config->port_clock == 162000)
3050                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3051         else
3052                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3053
3054         I915_WRITE(DP_A, intel_dp->DP);
3055         POSTING_READ(DP_A);
3056         udelay(500);
3057
3058         /*
3059          * [DevILK] Work around required when enabling DP PLL
3060          * while a pipe is enabled going to FDI:
3061          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3062          * 2. Program DP PLL enable
3063          */
3064         if (IS_GEN(dev_priv, 5))
3065                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3066
3067         intel_dp->DP |= DP_PLL_ENABLE;
3068
3069         I915_WRITE(DP_A, intel_dp->DP);
3070         POSTING_READ(DP_A);
3071         udelay(200);
3072 }
3073
3074 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
3075                                  const struct intel_crtc_state *old_crtc_state)
3076 {
3077         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3078         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3079
3080         assert_pipe_disabled(dev_priv, crtc->pipe);
3081         assert_dp_port_disabled(intel_dp);
3082         assert_edp_pll_enabled(dev_priv);
3083
3084         DRM_DEBUG_KMS("disabling eDP PLL\n");
3085
3086         intel_dp->DP &= ~DP_PLL_ENABLE;
3087
3088         I915_WRITE(DP_A, intel_dp->DP);
3089         POSTING_READ(DP_A);
3090         udelay(200);
3091 }
3092
3093 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3094 {
3095         /*
3096          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3097          * be capable of signalling downstream hpd with a long pulse.
3098          * Whether or not that means D3 is safe to use is not clear,
3099          * but let's assume so until proven otherwise.
3100          *
3101          * FIXME should really check all downstream ports...
3102          */
3103         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3104                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3105                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3106 }
3107
3108 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3109                                            const struct intel_crtc_state *crtc_state,
3110                                            bool enable)
3111 {
3112         int ret;
3113
3114         if (!crtc_state->dsc.compression_enable)
3115                 return;
3116
3117         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3118                                  enable ? DP_DECOMPRESSION_EN : 0);
3119         if (ret < 0)
3120                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3121                               enable ? "enable" : "disable");
3122 }
3123
3124 /* If the sink supports it, try to set the power state appropriately */
3125 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3126 {
3127         int ret, i;
3128
3129         /* Should have a valid DPCD by this point */
3130         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3131                 return;
3132
3133         if (mode != DRM_MODE_DPMS_ON) {
3134                 if (downstream_hpd_needs_d0(intel_dp))
3135                         return;
3136
3137                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3138                                          DP_SET_POWER_D3);
3139         } else {
3140                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3141
3142                 /*
3143                  * When turning on, we need to retry for 1ms to give the sink
3144                  * time to wake up.
3145                  */
3146                 for (i = 0; i < 3; i++) {
3147                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3148                                                  DP_SET_POWER_D0);
3149                         if (ret == 1)
3150                                 break;
3151                         msleep(1);
3152                 }
3153
3154                 if (ret == 1 && lspcon->active)
3155                         lspcon_wait_pcon_mode(lspcon);
3156         }
3157
3158         if (ret != 1)
3159                 DRM_DEBUG_KMS("failed to %s sink power state\n",
3160                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3161 }
3162
3163 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3164                                  enum port port, enum pipe *pipe)
3165 {
3166         enum pipe p;
3167
3168         for_each_pipe(dev_priv, p) {
3169                 u32 val = I915_READ(TRANS_DP_CTL(p));
3170
3171                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3172                         *pipe = p;
3173                         return true;
3174                 }
3175         }
3176
3177         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3178
3179         /* must initialize pipe to something for the asserts */
3180         *pipe = PIPE_A;
3181
3182         return false;
3183 }
3184
3185 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3186                            i915_reg_t dp_reg, enum port port,
3187                            enum pipe *pipe)
3188 {
3189         bool ret;
3190         u32 val;
3191
3192         val = I915_READ(dp_reg);
3193
3194         ret = val & DP_PORT_EN;
3195
3196         /* asserts want to know the pipe even if the port is disabled */
3197         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3198                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3199         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3200                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3201         else if (IS_CHERRYVIEW(dev_priv))
3202                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3203         else
3204                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3205
3206         return ret;
3207 }
3208
3209 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3210                                   enum pipe *pipe)
3211 {
3212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3213         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3214         intel_wakeref_t wakeref;
3215         bool ret;
3216
3217         wakeref = intel_display_power_get_if_enabled(dev_priv,
3218                                                      encoder->power_domain);
3219         if (!wakeref)
3220                 return false;
3221
3222         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3223                                     encoder->port, pipe);
3224
3225         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3226
3227         return ret;
3228 }
3229
3230 static void intel_dp_get_config(struct intel_encoder *encoder,
3231                                 struct intel_crtc_state *pipe_config)
3232 {
3233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3234         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3235         u32 tmp, flags = 0;
3236         enum port port = encoder->port;
3237         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3238
3239         if (encoder->type == INTEL_OUTPUT_EDP)
3240                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3241         else
3242                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3243
3244         tmp = I915_READ(intel_dp->output_reg);
3245
3246         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3247
3248         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3249                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3250
3251                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3252                         flags |= DRM_MODE_FLAG_PHSYNC;
3253                 else
3254                         flags |= DRM_MODE_FLAG_NHSYNC;
3255
3256                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3257                         flags |= DRM_MODE_FLAG_PVSYNC;
3258                 else
3259                         flags |= DRM_MODE_FLAG_NVSYNC;
3260         } else {
3261                 if (tmp & DP_SYNC_HS_HIGH)
3262                         flags |= DRM_MODE_FLAG_PHSYNC;
3263                 else
3264                         flags |= DRM_MODE_FLAG_NHSYNC;
3265
3266                 if (tmp & DP_SYNC_VS_HIGH)
3267                         flags |= DRM_MODE_FLAG_PVSYNC;
3268                 else
3269                         flags |= DRM_MODE_FLAG_NVSYNC;
3270         }
3271
3272         pipe_config->base.adjusted_mode.flags |= flags;
3273
3274         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3275                 pipe_config->limited_color_range = true;
3276
3277         pipe_config->lane_count =
3278                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3279
3280         intel_dp_get_m_n(crtc, pipe_config);
3281
3282         if (port == PORT_A) {
3283                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3284                         pipe_config->port_clock = 162000;
3285                 else
3286                         pipe_config->port_clock = 270000;
3287         }
3288
3289         pipe_config->base.adjusted_mode.crtc_clock =
3290                 intel_dotclock_calculate(pipe_config->port_clock,
3291                                          &pipe_config->dp_m_n);
3292
3293         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3294             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3295                 /*
3296                  * This is a big fat ugly hack.
3297                  *
3298                  * Some machines in UEFI boot mode provide us a VBT that has 18
3299                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3300                  * unknown we fail to light up. Yet the same BIOS boots up with
3301                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3302                  * max, not what it tells us to use.
3303                  *
3304                  * Note: This will still be broken if the eDP panel is not lit
3305                  * up by the BIOS, and thus we can't get the mode at module
3306                  * load.
3307                  */
3308                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3309                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3310                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3311         }
3312 }
3313
3314 static void intel_disable_dp(struct intel_encoder *encoder,
3315                              const struct intel_crtc_state *old_crtc_state,
3316                              const struct drm_connector_state *old_conn_state)
3317 {
3318         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3319
3320         intel_dp->link_trained = false;
3321
3322         if (old_crtc_state->has_audio)
3323                 intel_audio_codec_disable(encoder,
3324                                           old_crtc_state, old_conn_state);
3325
3326         /* Make sure the panel is off before trying to change the mode. But also
3327          * ensure that we have vdd while we switch off the panel. */
3328         intel_edp_panel_vdd_on(intel_dp);
3329         intel_edp_backlight_off(old_conn_state);
3330         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3331         intel_edp_panel_off(intel_dp);
3332 }
3333
3334 static void g4x_disable_dp(struct intel_encoder *encoder,
3335                            const struct intel_crtc_state *old_crtc_state,
3336                            const struct drm_connector_state *old_conn_state)
3337 {
3338         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3339 }
3340
3341 static void vlv_disable_dp(struct intel_encoder *encoder,
3342                            const struct intel_crtc_state *old_crtc_state,
3343                            const struct drm_connector_state *old_conn_state)
3344 {
3345         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3346 }
3347
3348 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3349                                 const struct intel_crtc_state *old_crtc_state,
3350                                 const struct drm_connector_state *old_conn_state)
3351 {
3352         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3353         enum port port = encoder->port;
3354
3355         /*
3356          * Bspec does not list a specific disable sequence for g4x DP.
3357          * Follow the ilk+ sequence (disable pipe before the port) for
3358          * g4x DP as it does not suffer from underruns like the normal
3359          * g4x modeset sequence (disable pipe after the port).
3360          */
3361         intel_dp_link_down(encoder, old_crtc_state);
3362
3363         /* Only ilk+ has port A */
3364         if (port == PORT_A)
3365                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3366 }
3367
3368 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3369                                 const struct intel_crtc_state *old_crtc_state,
3370                                 const struct drm_connector_state *old_conn_state)
3371 {
3372         intel_dp_link_down(encoder, old_crtc_state);
3373 }
3374
3375 static void chv_post_disable_dp(struct intel_encoder *encoder,
3376                                 const struct intel_crtc_state *old_crtc_state,
3377                                 const struct drm_connector_state *old_conn_state)
3378 {
3379         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3380
3381         intel_dp_link_down(encoder, old_crtc_state);
3382
3383         vlv_dpio_get(dev_priv);
3384
3385         /* Assert data lane reset */
3386         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3387
3388         vlv_dpio_put(dev_priv);
3389 }
3390
3391 static void
3392 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3393                          u32 *DP,
3394                          u8 dp_train_pat)
3395 {
3396         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3397         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3398         enum port port = intel_dig_port->base.port;
3399         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3400
3401         if (dp_train_pat & train_pat_mask)
3402                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3403                               dp_train_pat & train_pat_mask);
3404
3405         if (HAS_DDI(dev_priv)) {
3406                 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3407
3408                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3409                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3410                 else
3411                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3412
3413                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3414                 switch (dp_train_pat & train_pat_mask) {
3415                 case DP_TRAINING_PATTERN_DISABLE:
3416                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3417
3418                         break;
3419                 case DP_TRAINING_PATTERN_1:
3420                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3421                         break;
3422                 case DP_TRAINING_PATTERN_2:
3423                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3424                         break;
3425                 case DP_TRAINING_PATTERN_3:
3426                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3427                         break;
3428                 case DP_TRAINING_PATTERN_4:
3429                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3430                         break;
3431                 }
3432                 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
3433
3434         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3435                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3436                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3437
3438                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3439                 case DP_TRAINING_PATTERN_DISABLE:
3440                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3441                         break;
3442                 case DP_TRAINING_PATTERN_1:
3443                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3444                         break;
3445                 case DP_TRAINING_PATTERN_2:
3446                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3447                         break;
3448                 case DP_TRAINING_PATTERN_3:
3449                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3450                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3451                         break;
3452                 }
3453
3454         } else {
3455                 *DP &= ~DP_LINK_TRAIN_MASK;
3456
3457                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3458                 case DP_TRAINING_PATTERN_DISABLE:
3459                         *DP |= DP_LINK_TRAIN_OFF;
3460                         break;
3461                 case DP_TRAINING_PATTERN_1:
3462                         *DP |= DP_LINK_TRAIN_PAT_1;
3463                         break;
3464                 case DP_TRAINING_PATTERN_2:
3465                         *DP |= DP_LINK_TRAIN_PAT_2;
3466                         break;
3467                 case DP_TRAINING_PATTERN_3:
3468                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3469                         *DP |= DP_LINK_TRAIN_PAT_2;
3470                         break;
3471                 }
3472         }
3473 }
3474
3475 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3476                                  const struct intel_crtc_state *old_crtc_state)
3477 {
3478         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3479
3480         /* enable with pattern 1 (as per spec) */
3481
3482         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3483
3484         /*
3485          * Magic for VLV/CHV. We _must_ first set up the register
3486          * without actually enabling the port, and then do another
3487          * write to enable the port. Otherwise link training will
3488          * fail when the power sequencer is freshly used for this port.
3489          */
3490         intel_dp->DP |= DP_PORT_EN;
3491         if (old_crtc_state->has_audio)
3492                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3493
3494         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3495         POSTING_READ(intel_dp->output_reg);
3496 }
3497
3498 static void intel_enable_dp(struct intel_encoder *encoder,
3499                             const struct intel_crtc_state *pipe_config,
3500                             const struct drm_connector_state *conn_state)
3501 {
3502         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3503         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3504         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3505         u32 dp_reg = I915_READ(intel_dp->output_reg);
3506         enum pipe pipe = crtc->pipe;
3507         intel_wakeref_t wakeref;
3508
3509         if (WARN_ON(dp_reg & DP_PORT_EN))
3510                 return;
3511
3512         with_pps_lock(intel_dp, wakeref) {
3513                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3514                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3515
3516                 intel_dp_enable_port(intel_dp, pipe_config);
3517
3518                 edp_panel_vdd_on(intel_dp);
3519                 edp_panel_on(intel_dp);
3520                 edp_panel_vdd_off(intel_dp, true);
3521         }
3522
3523         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3524                 unsigned int lane_mask = 0x0;
3525
3526                 if (IS_CHERRYVIEW(dev_priv))
3527                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3528
3529                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3530                                     lane_mask);
3531         }
3532
3533         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3534         intel_dp_start_link_train(intel_dp);
3535         intel_dp_stop_link_train(intel_dp);
3536
3537         if (pipe_config->has_audio) {
3538                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3539                                  pipe_name(pipe));
3540                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3541         }
3542 }
3543
3544 static void g4x_enable_dp(struct intel_encoder *encoder,
3545                           const struct intel_crtc_state *pipe_config,
3546                           const struct drm_connector_state *conn_state)
3547 {
3548         intel_enable_dp(encoder, pipe_config, conn_state);
3549         intel_edp_backlight_on(pipe_config, conn_state);
3550 }
3551
3552 static void vlv_enable_dp(struct intel_encoder *encoder,
3553                           const struct intel_crtc_state *pipe_config,
3554                           const struct drm_connector_state *conn_state)
3555 {
3556         intel_edp_backlight_on(pipe_config, conn_state);
3557 }
3558
3559 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3560                               const struct intel_crtc_state *pipe_config,
3561                               const struct drm_connector_state *conn_state)
3562 {
3563         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3564         enum port port = encoder->port;
3565
3566         intel_dp_prepare(encoder, pipe_config);
3567
3568         /* Only ilk+ has port A */
3569         if (port == PORT_A)
3570                 ironlake_edp_pll_on(intel_dp, pipe_config);
3571 }
3572
3573 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3574 {
3575         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3576         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3577         enum pipe pipe = intel_dp->pps_pipe;
3578         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3579
3580         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3581
3582         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3583                 return;
3584
3585         edp_panel_vdd_off_sync(intel_dp);
3586
3587         /*
3588          * VLV seems to get confused when multiple power sequencers
3589          * have the same port selected (even if only one has power/vdd
3590          * enabled). The failure manifests as vlv_wait_port_ready() failing
3591          * CHV on the other hand doesn't seem to mind having the same port
3592          * selected in multiple power sequencers, but let's clear the
3593          * port select always when logically disconnecting a power sequencer
3594          * from a port.
3595          */
3596         DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3597                       pipe_name(pipe), intel_dig_port->base.base.base.id,
3598                       intel_dig_port->base.base.name);
3599         I915_WRITE(pp_on_reg, 0);
3600         POSTING_READ(pp_on_reg);
3601
3602         intel_dp->pps_pipe = INVALID_PIPE;
3603 }
3604
3605 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3606                                       enum pipe pipe)
3607 {
3608         struct intel_encoder *encoder;
3609
3610         lockdep_assert_held(&dev_priv->pps_mutex);
3611
3612         for_each_intel_dp(&dev_priv->drm, encoder) {
3613                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3614
3615                 WARN(intel_dp->active_pipe == pipe,
3616                      "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3617                      pipe_name(pipe), encoder->base.base.id,
3618                      encoder->base.name);
3619
3620                 if (intel_dp->pps_pipe != pipe)
3621                         continue;
3622
3623                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3624                               pipe_name(pipe), encoder->base.base.id,
3625                               encoder->base.name);
3626
3627                 /* make sure vdd is off before we steal it */
3628                 vlv_detach_power_sequencer(intel_dp);
3629         }
3630 }
3631
3632 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3633                                            const struct intel_crtc_state *crtc_state)
3634 {
3635         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3636         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3637         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3638
3639         lockdep_assert_held(&dev_priv->pps_mutex);
3640
3641         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3642
3643         if (intel_dp->pps_pipe != INVALID_PIPE &&
3644             intel_dp->pps_pipe != crtc->pipe) {
3645                 /*
3646                  * If another power sequencer was being used on this
3647                  * port previously make sure to turn off vdd there while
3648                  * we still have control of it.
3649                  */
3650                 vlv_detach_power_sequencer(intel_dp);
3651         }
3652
3653         /*
3654          * We may be stealing the power
3655          * sequencer from another port.
3656          */
3657         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3658
3659         intel_dp->active_pipe = crtc->pipe;
3660
3661         if (!intel_dp_is_edp(intel_dp))
3662                 return;
3663
3664         /* now it's all ours */
3665         intel_dp->pps_pipe = crtc->pipe;
3666
3667         DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3668                       pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3669                       encoder->base.name);
3670
3671         /* init power sequencer on this pipe and port */
3672         intel_dp_init_panel_power_sequencer(intel_dp);
3673         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3674 }
3675
3676 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3677                               const struct intel_crtc_state *pipe_config,
3678                               const struct drm_connector_state *conn_state)
3679 {
3680         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3681
3682         intel_enable_dp(encoder, pipe_config, conn_state);
3683 }
3684
3685 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3686                                   const struct intel_crtc_state *pipe_config,
3687                                   const struct drm_connector_state *conn_state)
3688 {
3689         intel_dp_prepare(encoder, pipe_config);
3690
3691         vlv_phy_pre_pll_enable(encoder, pipe_config);
3692 }
3693
3694 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3695                               const struct intel_crtc_state *pipe_config,
3696                               const struct drm_connector_state *conn_state)
3697 {
3698         chv_phy_pre_encoder_enable(encoder, pipe_config);
3699
3700         intel_enable_dp(encoder, pipe_config, conn_state);
3701
3702         /* Second common lane will stay alive on its own now */
3703         chv_phy_release_cl2_override(encoder);
3704 }
3705
3706 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3707                                   const struct intel_crtc_state *pipe_config,
3708                                   const struct drm_connector_state *conn_state)
3709 {
3710         intel_dp_prepare(encoder, pipe_config);
3711
3712         chv_phy_pre_pll_enable(encoder, pipe_config);
3713 }
3714
3715 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3716                                     const struct intel_crtc_state *old_crtc_state,
3717                                     const struct drm_connector_state *old_conn_state)
3718 {
3719         chv_phy_post_pll_disable(encoder, old_crtc_state);
3720 }
3721
3722 /*
3723  * Fetch AUX CH registers 0x202 - 0x207 which contain
3724  * link status information
3725  */
3726 bool
3727 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3728 {
3729         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3730                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3731 }
3732
3733 /* These are source-specific values. */
3734 u8
3735 intel_dp_voltage_max(struct intel_dp *intel_dp)
3736 {
3737         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3738         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3739         enum port port = encoder->port;
3740
3741         if (HAS_DDI(dev_priv))
3742                 return intel_ddi_dp_voltage_max(encoder);
3743         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3744                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3745         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3746                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3747         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3748                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3749         else
3750                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3751 }
3752
3753 u8
3754 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3755 {
3756         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3757         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3758         enum port port = encoder->port;
3759
3760         if (HAS_DDI(dev_priv)) {
3761                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3762         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3763                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3764                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3765                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3766                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3767                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3768                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3769                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3770                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3771                 default:
3772                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3773                 }
3774         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3775                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3776                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3777                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3778                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3779                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3780                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3781                 default:
3782                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3783                 }
3784         } else {
3785                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3786                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3787                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3788                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3789                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3790                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3791                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3792                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3793                 default:
3794                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3795                 }
3796         }
3797 }
3798
3799 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3800 {
3801         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3802         unsigned long demph_reg_value, preemph_reg_value,
3803                 uniqtranscale_reg_value;
3804         u8 train_set = intel_dp->train_set[0];
3805
3806         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3807         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3808                 preemph_reg_value = 0x0004000;
3809                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3810                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3811                         demph_reg_value = 0x2B405555;
3812                         uniqtranscale_reg_value = 0x552AB83A;
3813                         break;
3814                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3815                         demph_reg_value = 0x2B404040;
3816                         uniqtranscale_reg_value = 0x5548B83A;
3817                         break;
3818                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3819                         demph_reg_value = 0x2B245555;
3820                         uniqtranscale_reg_value = 0x5560B83A;
3821                         break;
3822                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3823                         demph_reg_value = 0x2B405555;
3824                         uniqtranscale_reg_value = 0x5598DA3A;
3825                         break;
3826                 default:
3827                         return 0;
3828                 }
3829                 break;
3830         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3831                 preemph_reg_value = 0x0002000;
3832                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3833                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3834                         demph_reg_value = 0x2B404040;
3835                         uniqtranscale_reg_value = 0x5552B83A;
3836                         break;
3837                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3838                         demph_reg_value = 0x2B404848;
3839                         uniqtranscale_reg_value = 0x5580B83A;
3840                         break;
3841                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3842                         demph_reg_value = 0x2B404040;
3843                         uniqtranscale_reg_value = 0x55ADDA3A;
3844                         break;
3845                 default:
3846                         return 0;
3847                 }
3848                 break;
3849         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3850                 preemph_reg_value = 0x0000000;
3851                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3852                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3853                         demph_reg_value = 0x2B305555;
3854                         uniqtranscale_reg_value = 0x5570B83A;
3855                         break;
3856                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3857                         demph_reg_value = 0x2B2B4040;
3858                         uniqtranscale_reg_value = 0x55ADDA3A;
3859                         break;
3860                 default:
3861                         return 0;
3862                 }
3863                 break;
3864         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3865                 preemph_reg_value = 0x0006000;
3866                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3867                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3868                         demph_reg_value = 0x1B405555;
3869                         uniqtranscale_reg_value = 0x55ADDA3A;
3870                         break;
3871                 default:
3872                         return 0;
3873                 }
3874                 break;
3875         default:
3876                 return 0;
3877         }
3878
3879         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3880                                  uniqtranscale_reg_value, 0);
3881
3882         return 0;
3883 }
3884
3885 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3886 {
3887         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3888         u32 deemph_reg_value, margin_reg_value;
3889         bool uniq_trans_scale = false;
3890         u8 train_set = intel_dp->train_set[0];
3891
3892         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3893         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3894                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3895                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3896                         deemph_reg_value = 128;
3897                         margin_reg_value = 52;
3898                         break;
3899                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3900                         deemph_reg_value = 128;
3901                         margin_reg_value = 77;
3902                         break;
3903                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3904                         deemph_reg_value = 128;
3905                         margin_reg_value = 102;
3906                         break;
3907                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3908                         deemph_reg_value = 128;
3909                         margin_reg_value = 154;
3910                         uniq_trans_scale = true;
3911                         break;
3912                 default:
3913                         return 0;
3914                 }
3915                 break;
3916         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3917                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3918                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3919                         deemph_reg_value = 85;
3920                         margin_reg_value = 78;
3921                         break;
3922                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3923                         deemph_reg_value = 85;
3924                         margin_reg_value = 116;
3925                         break;
3926                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3927                         deemph_reg_value = 85;
3928                         margin_reg_value = 154;
3929                         break;
3930                 default:
3931                         return 0;
3932                 }
3933                 break;
3934         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3935                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3936                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3937                         deemph_reg_value = 64;
3938                         margin_reg_value = 104;
3939                         break;
3940                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3941                         deemph_reg_value = 64;
3942                         margin_reg_value = 154;
3943                         break;
3944                 default:
3945                         return 0;
3946                 }
3947                 break;
3948         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3949                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3950                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3951                         deemph_reg_value = 43;
3952                         margin_reg_value = 154;
3953                         break;
3954                 default:
3955                         return 0;
3956                 }
3957                 break;
3958         default:
3959                 return 0;
3960         }
3961
3962         chv_set_phy_signal_level(encoder, deemph_reg_value,
3963                                  margin_reg_value, uniq_trans_scale);
3964
3965         return 0;
3966 }
3967
3968 static u32
3969 g4x_signal_levels(u8 train_set)
3970 {
3971         u32 signal_levels = 0;
3972
3973         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3974         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3975         default:
3976                 signal_levels |= DP_VOLTAGE_0_4;
3977                 break;
3978         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3979                 signal_levels |= DP_VOLTAGE_0_6;
3980                 break;
3981         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3982                 signal_levels |= DP_VOLTAGE_0_8;
3983                 break;
3984         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3985                 signal_levels |= DP_VOLTAGE_1_2;
3986                 break;
3987         }
3988         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3989         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3990         default:
3991                 signal_levels |= DP_PRE_EMPHASIS_0;
3992                 break;
3993         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3994                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3995                 break;
3996         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3997                 signal_levels |= DP_PRE_EMPHASIS_6;
3998                 break;
3999         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4000                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4001                 break;
4002         }
4003         return signal_levels;
4004 }
4005
4006 /* SNB CPU eDP voltage swing and pre-emphasis control */
4007 static u32
4008 snb_cpu_edp_signal_levels(u8 train_set)
4009 {
4010         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4011                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4012         switch (signal_levels) {
4013         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4014         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4015                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4016         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4017                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4018         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4019         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4020                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4021         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4022         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4023                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4024         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4025         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4026                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4027         default:
4028                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4029                               "0x%x\n", signal_levels);
4030                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4031         }
4032 }
4033
4034 /* IVB CPU eDP voltage swing and pre-emphasis control */
4035 static u32
4036 ivb_cpu_edp_signal_levels(u8 train_set)
4037 {
4038         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4039                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4040         switch (signal_levels) {
4041         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4042                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4043         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4044                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4045         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4046                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4047
4048         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4049                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4050         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4051                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4052
4053         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4054                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4055         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4056                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4057
4058         default:
4059                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4060                               "0x%x\n", signal_levels);
4061                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4062         }
4063 }
4064
4065 void
4066 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4067 {
4068         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4069         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4070         enum port port = intel_dig_port->base.port;
4071         u32 signal_levels, mask = 0;
4072         u8 train_set = intel_dp->train_set[0];
4073
4074         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4075                 signal_levels = bxt_signal_levels(intel_dp);
4076         } else if (HAS_DDI(dev_priv)) {
4077                 signal_levels = ddi_signal_levels(intel_dp);
4078                 mask = DDI_BUF_EMP_MASK;
4079         } else if (IS_CHERRYVIEW(dev_priv)) {
4080                 signal_levels = chv_signal_levels(intel_dp);
4081         } else if (IS_VALLEYVIEW(dev_priv)) {
4082                 signal_levels = vlv_signal_levels(intel_dp);
4083         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4084                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4085                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4086         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4087                 signal_levels = snb_cpu_edp_signal_levels(train_set);
4088                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4089         } else {
4090                 signal_levels = g4x_signal_levels(train_set);
4091                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4092         }
4093
4094         if (mask)
4095                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
4096
4097         DRM_DEBUG_KMS("Using vswing level %d\n",
4098                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
4099         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
4100                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4101                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
4102
4103         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4104
4105         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4106         POSTING_READ(intel_dp->output_reg);
4107 }
4108
4109 void
4110 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4111                                        u8 dp_train_pat)
4112 {
4113         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4114         struct drm_i915_private *dev_priv =
4115                 to_i915(intel_dig_port->base.base.dev);
4116
4117         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4118
4119         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4120         POSTING_READ(intel_dp->output_reg);
4121 }
4122
4123 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4124 {
4125         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4126         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4127         enum port port = intel_dig_port->base.port;
4128         u32 val;
4129
4130         if (!HAS_DDI(dev_priv))
4131                 return;
4132
4133         val = I915_READ(intel_dp->regs.dp_tp_ctl);
4134         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4135         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4136         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4137
4138         /*
4139          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4140          * reason we need to set idle transmission mode is to work around a HW
4141          * issue where we enable the pipe while not in idle link-training mode.
4142          * In this case there is requirement to wait for a minimum number of
4143          * idle patterns to be sent.
4144          */
4145         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4146                 return;
4147
4148         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4149                                   DP_TP_STATUS_IDLE_DONE, 1))
4150                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4151 }
4152
4153 static void
4154 intel_dp_link_down(struct intel_encoder *encoder,
4155                    const struct intel_crtc_state *old_crtc_state)
4156 {
4157         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4158         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4159         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4160         enum port port = encoder->port;
4161         u32 DP = intel_dp->DP;
4162
4163         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4164                 return;
4165
4166         DRM_DEBUG_KMS("\n");
4167
4168         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4169             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4170                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4171                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4172         } else {
4173                 DP &= ~DP_LINK_TRAIN_MASK;
4174                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4175         }
4176         I915_WRITE(intel_dp->output_reg, DP);
4177         POSTING_READ(intel_dp->output_reg);
4178
4179         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4180         I915_WRITE(intel_dp->output_reg, DP);
4181         POSTING_READ(intel_dp->output_reg);
4182
4183         /*
4184          * HW workaround for IBX, we need to move the port
4185          * to transcoder A after disabling it to allow the
4186          * matching HDMI port to be enabled on transcoder A.
4187          */
4188         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4189                 /*
4190                  * We get CPU/PCH FIFO underruns on the other pipe when
4191                  * doing the workaround. Sweep them under the rug.
4192                  */
4193                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4194                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4195
4196                 /* always enable with pattern 1 (as per spec) */
4197                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4198                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4199                         DP_LINK_TRAIN_PAT_1;
4200                 I915_WRITE(intel_dp->output_reg, DP);
4201                 POSTING_READ(intel_dp->output_reg);
4202
4203                 DP &= ~DP_PORT_EN;
4204                 I915_WRITE(intel_dp->output_reg, DP);
4205                 POSTING_READ(intel_dp->output_reg);
4206
4207                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4208                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4209                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4210         }
4211
4212         msleep(intel_dp->panel_power_down_delay);
4213
4214         intel_dp->DP = DP;
4215
4216         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4217                 intel_wakeref_t wakeref;
4218
4219                 with_pps_lock(intel_dp, wakeref)
4220                         intel_dp->active_pipe = INVALID_PIPE;
4221         }
4222 }
4223
4224 static void
4225 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4226 {
4227         u8 dpcd_ext[6];
4228
4229         /*
4230          * Prior to DP1.3 the bit represented by
4231          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4232          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4233          * the true capability of the panel. The only way to check is to
4234          * then compare 0000h and 2200h.
4235          */
4236         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4237               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4238                 return;
4239
4240         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4241                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4242                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4243                 return;
4244         }
4245
4246         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4247                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4248                 return;
4249         }
4250
4251         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4252                 return;
4253
4254         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4255                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4256
4257         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4258 }
4259
4260 bool
4261 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4262 {
4263         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4264                              sizeof(intel_dp->dpcd)) < 0)
4265                 return false; /* aux transfer failed */
4266
4267         intel_dp_extended_receiver_capabilities(intel_dp);
4268
4269         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4270
4271         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4272 }
4273
4274 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4275 {
4276         u8 dprx = 0;
4277
4278         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4279                               &dprx) != 1)
4280                 return false;
4281         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4282 }
4283
4284 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4285 {
4286         /*
4287          * Clear the cached register set to avoid using stale values
4288          * for the sinks that do not support DSC.
4289          */
4290         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4291
4292         /* Clear fec_capable to avoid using stale values */
4293         intel_dp->fec_capable = 0;
4294
4295         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4296         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4297             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4298                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4299                                      intel_dp->dsc_dpcd,
4300                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4301                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4302                                   DP_DSC_SUPPORT);
4303
4304                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4305                               (int)sizeof(intel_dp->dsc_dpcd),
4306                               intel_dp->dsc_dpcd);
4307
4308                 /* FEC is supported only on DP 1.4 */
4309                 if (!intel_dp_is_edp(intel_dp) &&
4310                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4311                                       &intel_dp->fec_capable) < 0)
4312                         DRM_ERROR("Failed to read FEC DPCD register\n");
4313
4314                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4315         }
4316 }
4317
4318 static bool
4319 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4320 {
4321         struct drm_i915_private *dev_priv =
4322                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4323
4324         /* this function is meant to be called only once */
4325         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4326
4327         if (!intel_dp_read_dpcd(intel_dp))
4328                 return false;
4329
4330         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4331                          drm_dp_is_branch(intel_dp->dpcd));
4332
4333         /*
4334          * Read the eDP display control registers.
4335          *
4336          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4337          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4338          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4339          * method). The display control registers should read zero if they're
4340          * not supported anyway.
4341          */
4342         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4343                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4344                              sizeof(intel_dp->edp_dpcd))
4345                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4346                               intel_dp->edp_dpcd);
4347
4348         /*
4349          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4350          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4351          */
4352         intel_psr_init_dpcd(intel_dp);
4353
4354         /* Read the eDP 1.4+ supported link rates. */
4355         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4356                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4357                 int i;
4358
4359                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4360                                 sink_rates, sizeof(sink_rates));
4361
4362                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4363                         int val = le16_to_cpu(sink_rates[i]);
4364
4365                         if (val == 0)
4366                                 break;
4367
4368                         /* Value read multiplied by 200kHz gives the per-lane
4369                          * link rate in kHz. The source rates are, however,
4370                          * stored in terms of LS_Clk kHz. The full conversion
4371                          * back to symbols is
4372                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4373                          */
4374                         intel_dp->sink_rates[i] = (val * 200) / 10;
4375                 }
4376                 intel_dp->num_sink_rates = i;
4377         }
4378
4379         /*
4380          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4381          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4382          */
4383         if (intel_dp->num_sink_rates)
4384                 intel_dp->use_rate_select = true;
4385         else
4386                 intel_dp_set_sink_rates(intel_dp);
4387
4388         intel_dp_set_common_rates(intel_dp);
4389
4390         /* Read the eDP DSC DPCD registers */
4391         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4392                 intel_dp_get_dsc_sink_cap(intel_dp);
4393
4394         return true;
4395 }
4396
4397
4398 static bool
4399 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4400 {
4401         if (!intel_dp_read_dpcd(intel_dp))
4402                 return false;
4403
4404         /*
4405          * Don't clobber cached eDP rates. Also skip re-reading
4406          * the OUI/ID since we know it won't change.
4407          */
4408         if (!intel_dp_is_edp(intel_dp)) {
4409                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4410                                  drm_dp_is_branch(intel_dp->dpcd));
4411
4412                 intel_dp_set_sink_rates(intel_dp);
4413                 intel_dp_set_common_rates(intel_dp);
4414         }
4415
4416         /*
4417          * Some eDP panels do not set a valid value for sink count, that is why
4418          * it don't care about read it here and in intel_edp_init_dpcd().
4419          */
4420         if (!intel_dp_is_edp(intel_dp) &&
4421             !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4422                 u8 count;
4423                 ssize_t r;
4424
4425                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4426                 if (r < 1)
4427                         return false;
4428
4429                 /*
4430                  * Sink count can change between short pulse hpd hence
4431                  * a member variable in intel_dp will track any changes
4432                  * between short pulse interrupts.
4433                  */
4434                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4435
4436                 /*
4437                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4438                  * a dongle is present but no display. Unless we require to know
4439                  * if a dongle is present or not, we don't need to update
4440                  * downstream port information. So, an early return here saves
4441                  * time from performing other operations which are not required.
4442                  */
4443                 if (!intel_dp->sink_count)
4444                         return false;
4445         }
4446
4447         if (!drm_dp_is_branch(intel_dp->dpcd))
4448                 return true; /* native DP sink */
4449
4450         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4451                 return true; /* no per-port downstream info */
4452
4453         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4454                              intel_dp->downstream_ports,
4455                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4456                 return false; /* downstream port status fetch failed */
4457
4458         return true;
4459 }
4460
4461 static bool
4462 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4463 {
4464         u8 mstm_cap;
4465
4466         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4467                 return false;
4468
4469         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4470                 return false;
4471
4472         return mstm_cap & DP_MST_CAP;
4473 }
4474
4475 static bool
4476 intel_dp_can_mst(struct intel_dp *intel_dp)
4477 {
4478         return i915_modparams.enable_dp_mst &&
4479                 intel_dp->can_mst &&
4480                 intel_dp_sink_can_mst(intel_dp);
4481 }
4482
4483 static void
4484 intel_dp_configure_mst(struct intel_dp *intel_dp)
4485 {
4486         struct intel_encoder *encoder =
4487                 &dp_to_dig_port(intel_dp)->base;
4488         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4489
4490         DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4491                       encoder->base.base.id, encoder->base.name,
4492                       yesno(intel_dp->can_mst), yesno(sink_can_mst),
4493                       yesno(i915_modparams.enable_dp_mst));
4494
4495         if (!intel_dp->can_mst)
4496                 return;
4497
4498         intel_dp->is_mst = sink_can_mst &&
4499                 i915_modparams.enable_dp_mst;
4500
4501         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4502                                         intel_dp->is_mst);
4503 }
4504
4505 static bool
4506 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4507 {
4508         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4509                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4510                 DP_DPRX_ESI_LEN;
4511 }
4512
4513 bool
4514 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4515                        const struct drm_connector_state *conn_state)
4516 {
4517         /*
4518          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4519          * of Color Encoding Format and Content Color Gamut], in order to
4520          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4521          */
4522         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4523                 return true;
4524
4525         switch (conn_state->colorspace) {
4526         case DRM_MODE_COLORIMETRY_SYCC_601:
4527         case DRM_MODE_COLORIMETRY_OPYCC_601:
4528         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4529         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4530         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4531                 return true;
4532         default:
4533                 break;
4534         }
4535
4536         return false;
4537 }
4538
4539 static void
4540 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
4541                        const struct intel_crtc_state *crtc_state,
4542                        const struct drm_connector_state *conn_state)
4543 {
4544         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4545         struct dp_sdp vsc_sdp = {};
4546
4547         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4548         vsc_sdp.sdp_header.HB0 = 0;
4549         vsc_sdp.sdp_header.HB1 = 0x7;
4550
4551         /*
4552          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4553          * Colorimetry Format indication.
4554          */
4555         vsc_sdp.sdp_header.HB2 = 0x5;
4556
4557         /*
4558          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4559          * Colorimetry Format indication (HB2 = 05h).
4560          */
4561         vsc_sdp.sdp_header.HB3 = 0x13;
4562
4563         /* DP 1.4a spec, Table 2-120 */
4564         switch (crtc_state->output_format) {
4565         case INTEL_OUTPUT_FORMAT_YCBCR444:
4566                 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
4567                 break;
4568         case INTEL_OUTPUT_FORMAT_YCBCR420:
4569                 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
4570                 break;
4571         case INTEL_OUTPUT_FORMAT_RGB:
4572         default:
4573                 /* RGB: DB16[7:4] = 0h */
4574                 break;
4575         }
4576
4577         switch (conn_state->colorspace) {
4578         case DRM_MODE_COLORIMETRY_BT709_YCC:
4579                 vsc_sdp.db[16] |= 0x1;
4580                 break;
4581         case DRM_MODE_COLORIMETRY_XVYCC_601:
4582                 vsc_sdp.db[16] |= 0x2;
4583                 break;
4584         case DRM_MODE_COLORIMETRY_XVYCC_709:
4585                 vsc_sdp.db[16] |= 0x3;
4586                 break;
4587         case DRM_MODE_COLORIMETRY_SYCC_601:
4588                 vsc_sdp.db[16] |= 0x4;
4589                 break;
4590         case DRM_MODE_COLORIMETRY_OPYCC_601:
4591                 vsc_sdp.db[16] |= 0x5;
4592                 break;
4593         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4594         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4595                 vsc_sdp.db[16] |= 0x6;
4596                 break;
4597         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4598                 vsc_sdp.db[16] |= 0x7;
4599                 break;
4600         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
4601         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
4602                 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
4603                 break;
4604         default:
4605                 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
4606
4607                 /* RGB->YCBCR color conversion uses the BT.709 color space. */
4608                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4609                         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4610                 break;
4611         }
4612
4613         /*
4614          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4615          * the following Component Bit Depth values are defined:
4616          * 001b = 8bpc.
4617          * 010b = 10bpc.
4618          * 011b = 12bpc.
4619          * 100b = 16bpc.
4620          */
4621         switch (crtc_state->pipe_bpp) {
4622         case 24: /* 8bpc */
4623                 vsc_sdp.db[17] = 0x1;
4624                 break;
4625         case 30: /* 10bpc */
4626                 vsc_sdp.db[17] = 0x2;
4627                 break;
4628         case 36: /* 12bpc */
4629                 vsc_sdp.db[17] = 0x3;
4630                 break;
4631         case 48: /* 16bpc */
4632                 vsc_sdp.db[17] = 0x4;
4633                 break;
4634         default:
4635                 MISSING_CASE(crtc_state->pipe_bpp);
4636                 break;
4637         }
4638
4639         /*
4640          * Dynamic Range (Bit 7)
4641          * 0 = VESA range, 1 = CTA range.
4642          * all YCbCr are always limited range
4643          */
4644         vsc_sdp.db[17] |= 0x80;
4645
4646         /*
4647          * Content Type (Bits 2:0)
4648          * 000b = Not defined.
4649          * 001b = Graphics.
4650          * 010b = Photo.
4651          * 011b = Video.
4652          * 100b = Game
4653          * All other values are RESERVED.
4654          * Note: See CTA-861-G for the definition and expected
4655          * processing by a stream sink for the above contect types.
4656          */
4657         vsc_sdp.db[18] = 0;
4658
4659         intel_dig_port->write_infoframe(&intel_dig_port->base,
4660                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4661 }
4662
4663 static void
4664 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
4665                                           const struct intel_crtc_state *crtc_state,
4666                                           const struct drm_connector_state *conn_state)
4667 {
4668         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4669         struct dp_sdp infoframe_sdp = {};
4670         struct hdmi_drm_infoframe drm_infoframe = {};
4671         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4672         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4673         ssize_t len;
4674         int ret;
4675
4676         ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
4677         if (ret) {
4678                 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
4679                 return;
4680         }
4681
4682         len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
4683         if (len < 0) {
4684                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4685                 return;
4686         }
4687
4688         if (len != infoframe_size) {
4689                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4690                 return;
4691         }
4692
4693         /*
4694          * Set up the infoframe sdp packet for HDR static metadata.
4695          * Prepare VSC Header for SU as per DP 1.4a spec,
4696          * Table 2-100 and Table 2-101
4697          */
4698
4699         /* Packet ID, 00h for non-Audio INFOFRAME */
4700         infoframe_sdp.sdp_header.HB0 = 0;
4701         /*
4702          * Packet Type 80h + Non-audio INFOFRAME Type value
4703          * HDMI_INFOFRAME_TYPE_DRM: 0x87,
4704          */
4705         infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
4706         /*
4707          * Least Significant Eight Bits of (Data Byte Count – 1)
4708          * infoframe_size - 1,
4709          */
4710         infoframe_sdp.sdp_header.HB2 = 0x1D;
4711         /* INFOFRAME SDP Version Number */
4712         infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
4713         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4714         infoframe_sdp.db[0] = drm_infoframe.version;
4715         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4716         infoframe_sdp.db[1] = drm_infoframe.length;
4717         /*
4718          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4719          * HDMI_INFOFRAME_HEADER_SIZE
4720          */
4721         BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4722         memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4723                HDMI_DRM_INFOFRAME_SIZE);
4724
4725         /*
4726          * Size of DP infoframe sdp packet for HDR static metadata is consist of
4727          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4728          * - Two Data Blocks: 2 bytes
4729          *    CTA Header Byte2 (INFOFRAME Version Number)
4730          *    CTA Header Byte3 (Length of INFOFRAME)
4731          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4732          *
4733          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4734          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4735          * will pad rest of the size.
4736          */
4737         intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
4738                                         HDMI_PACKET_TYPE_GAMUT_METADATA,
4739                                         &infoframe_sdp,
4740                                         sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
4741 }
4742
4743 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
4744                          const struct intel_crtc_state *crtc_state,
4745                          const struct drm_connector_state *conn_state)
4746 {
4747         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
4748                 return;
4749
4750         intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
4751 }
4752
4753 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
4754                                   const struct intel_crtc_state *crtc_state,
4755                                   const struct drm_connector_state *conn_state)
4756 {
4757         if (!conn_state->hdr_output_metadata)
4758                 return;
4759
4760         intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
4761                                                   crtc_state,
4762                                                   conn_state);
4763 }
4764
4765 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4766 {
4767         int status = 0;
4768         int test_link_rate;
4769         u8 test_lane_count, test_link_bw;
4770         /* (DP CTS 1.2)
4771          * 4.3.1.11
4772          */
4773         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4774         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4775                                    &test_lane_count);
4776
4777         if (status <= 0) {
4778                 DRM_DEBUG_KMS("Lane count read failed\n");
4779                 return DP_TEST_NAK;
4780         }
4781         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4782
4783         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4784                                    &test_link_bw);
4785         if (status <= 0) {
4786                 DRM_DEBUG_KMS("Link Rate read failed\n");
4787                 return DP_TEST_NAK;
4788         }
4789         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4790
4791         /* Validate the requested link rate and lane count */
4792         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4793                                         test_lane_count))
4794                 return DP_TEST_NAK;
4795
4796         intel_dp->compliance.test_lane_count = test_lane_count;
4797         intel_dp->compliance.test_link_rate = test_link_rate;
4798
4799         return DP_TEST_ACK;
4800 }
4801
4802 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4803 {
4804         u8 test_pattern;
4805         u8 test_misc;
4806         __be16 h_width, v_height;
4807         int status = 0;
4808
4809         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4810         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4811                                    &test_pattern);
4812         if (status <= 0) {
4813                 DRM_DEBUG_KMS("Test pattern read failed\n");
4814                 return DP_TEST_NAK;
4815         }
4816         if (test_pattern != DP_COLOR_RAMP)
4817                 return DP_TEST_NAK;
4818
4819         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4820                                   &h_width, 2);
4821         if (status <= 0) {
4822                 DRM_DEBUG_KMS("H Width read failed\n");
4823                 return DP_TEST_NAK;
4824         }
4825
4826         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4827                                   &v_height, 2);
4828         if (status <= 0) {
4829                 DRM_DEBUG_KMS("V Height read failed\n");
4830                 return DP_TEST_NAK;
4831         }
4832
4833         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4834                                    &test_misc);
4835         if (status <= 0) {
4836                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4837                 return DP_TEST_NAK;
4838         }
4839         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4840                 return DP_TEST_NAK;
4841         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4842                 return DP_TEST_NAK;
4843         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4844         case DP_TEST_BIT_DEPTH_6:
4845                 intel_dp->compliance.test_data.bpc = 6;
4846                 break;
4847         case DP_TEST_BIT_DEPTH_8:
4848                 intel_dp->compliance.test_data.bpc = 8;
4849                 break;
4850         default:
4851                 return DP_TEST_NAK;
4852         }
4853
4854         intel_dp->compliance.test_data.video_pattern = test_pattern;
4855         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4856         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4857         /* Set test active flag here so userspace doesn't interrupt things */
4858         intel_dp->compliance.test_active = 1;
4859
4860         return DP_TEST_ACK;
4861 }
4862
4863 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4864 {
4865         u8 test_result = DP_TEST_ACK;
4866         struct intel_connector *intel_connector = intel_dp->attached_connector;
4867         struct drm_connector *connector = &intel_connector->base;
4868
4869         if (intel_connector->detect_edid == NULL ||
4870             connector->edid_corrupt ||
4871             intel_dp->aux.i2c_defer_count > 6) {
4872                 /* Check EDID read for NACKs, DEFERs and corruption
4873                  * (DP CTS 1.2 Core r1.1)
4874                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4875                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4876                  *    4.2.2.6 : EDID corruption detected
4877                  * Use failsafe mode for all cases
4878                  */
4879                 if (intel_dp->aux.i2c_nack_count > 0 ||
4880                         intel_dp->aux.i2c_defer_count > 0)
4881                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4882                                       intel_dp->aux.i2c_nack_count,
4883                                       intel_dp->aux.i2c_defer_count);
4884                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4885         } else {
4886                 struct edid *block = intel_connector->detect_edid;
4887
4888                 /* We have to write the checksum
4889                  * of the last block read
4890                  */
4891                 block += intel_connector->detect_edid->extensions;
4892
4893                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4894                                        block->checksum) <= 0)
4895                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4896
4897                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4898                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4899         }
4900
4901         /* Set test active flag here so userspace doesn't interrupt things */
4902         intel_dp->compliance.test_active = 1;
4903
4904         return test_result;
4905 }
4906
4907 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4908 {
4909         u8 test_result = DP_TEST_NAK;
4910         return test_result;
4911 }
4912
4913 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4914 {
4915         u8 response = DP_TEST_NAK;
4916         u8 request = 0;
4917         int status;
4918
4919         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4920         if (status <= 0) {
4921                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4922                 goto update_status;
4923         }
4924
4925         switch (request) {
4926         case DP_TEST_LINK_TRAINING:
4927                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4928                 response = intel_dp_autotest_link_training(intel_dp);
4929                 break;
4930         case DP_TEST_LINK_VIDEO_PATTERN:
4931                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4932                 response = intel_dp_autotest_video_pattern(intel_dp);
4933                 break;
4934         case DP_TEST_LINK_EDID_READ:
4935                 DRM_DEBUG_KMS("EDID test requested\n");
4936                 response = intel_dp_autotest_edid(intel_dp);
4937                 break;
4938         case DP_TEST_LINK_PHY_TEST_PATTERN:
4939                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4940                 response = intel_dp_autotest_phy_pattern(intel_dp);
4941                 break;
4942         default:
4943                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4944                 break;
4945         }
4946
4947         if (response & DP_TEST_ACK)
4948                 intel_dp->compliance.test_type = request;
4949
4950 update_status:
4951         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4952         if (status <= 0)
4953                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4954 }
4955
4956 static int
4957 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4958 {
4959         bool bret;
4960
4961         if (intel_dp->is_mst) {
4962                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4963                 int ret = 0;
4964                 int retry;
4965                 bool handled;
4966
4967                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4968                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4969 go_again:
4970                 if (bret == true) {
4971
4972                         /* check link status - esi[10] = 0x200c */
4973                         if (intel_dp->active_mst_links > 0 &&
4974                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4975                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4976                                 intel_dp_start_link_train(intel_dp);
4977                                 intel_dp_stop_link_train(intel_dp);
4978                         }
4979
4980                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4981                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4982
4983                         if (handled) {
4984                                 for (retry = 0; retry < 3; retry++) {
4985                                         int wret;
4986                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4987                                                                  DP_SINK_COUNT_ESI+1,
4988                                                                  &esi[1], 3);
4989                                         if (wret == 3) {
4990                                                 break;
4991                                         }
4992                                 }
4993
4994                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4995                                 if (bret == true) {
4996                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4997                                         goto go_again;
4998                                 }
4999                         } else
5000                                 ret = 0;
5001
5002                         return ret;
5003                 } else {
5004                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
5005                         intel_dp->is_mst = false;
5006                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5007                                                         intel_dp->is_mst);
5008                 }
5009         }
5010         return -EINVAL;
5011 }
5012
5013 static bool
5014 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5015 {
5016         u8 link_status[DP_LINK_STATUS_SIZE];
5017
5018         if (!intel_dp->link_trained)
5019                 return false;
5020
5021         /*
5022          * While PSR source HW is enabled, it will control main-link sending
5023          * frames, enabling and disabling it so trying to do a retrain will fail
5024          * as the link would or not be on or it could mix training patterns
5025          * and frame data at the same time causing retrain to fail.
5026          * Also when exiting PSR, HW will retrain the link anyways fixing
5027          * any link status error.
5028          */
5029         if (intel_psr_enabled(intel_dp))
5030                 return false;
5031
5032         if (!intel_dp_get_link_status(intel_dp, link_status))
5033                 return false;
5034
5035         /*
5036          * Validate the cached values of intel_dp->link_rate and
5037          * intel_dp->lane_count before attempting to retrain.
5038          */
5039         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5040                                         intel_dp->lane_count))
5041                 return false;
5042
5043         /* Retrain if Channel EQ or CR not ok */
5044         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5045 }
5046
5047 int intel_dp_retrain_link(struct intel_encoder *encoder,
5048                           struct drm_modeset_acquire_ctx *ctx)
5049 {
5050         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5051         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
5052         struct intel_connector *connector = intel_dp->attached_connector;
5053         struct drm_connector_state *conn_state;
5054         struct intel_crtc_state *crtc_state;
5055         struct intel_crtc *crtc;
5056         int ret;
5057
5058         /* FIXME handle the MST connectors as well */
5059
5060         if (!connector || connector->base.status != connector_status_connected)
5061                 return 0;
5062
5063         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5064                                ctx);
5065         if (ret)
5066                 return ret;
5067
5068         conn_state = connector->base.state;
5069
5070         crtc = to_intel_crtc(conn_state->crtc);
5071         if (!crtc)
5072                 return 0;
5073
5074         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5075         if (ret)
5076                 return ret;
5077
5078         crtc_state = to_intel_crtc_state(crtc->base.state);
5079
5080         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
5081
5082         if (!crtc_state->base.active)
5083                 return 0;
5084
5085         if (conn_state->commit &&
5086             !try_wait_for_completion(&conn_state->commit->hw_done))
5087                 return 0;
5088
5089         if (!intel_dp_needs_link_retrain(intel_dp))
5090                 return 0;
5091
5092         /* Suppress underruns caused by re-training */
5093         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5094         if (crtc_state->has_pch_encoder)
5095                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5096                                                       intel_crtc_pch_transcoder(crtc), false);
5097
5098         intel_dp_start_link_train(intel_dp);
5099         intel_dp_stop_link_train(intel_dp);
5100
5101         /* Keep underrun reporting disabled until things are stable */
5102         intel_wait_for_vblank(dev_priv, crtc->pipe);
5103
5104         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5105         if (crtc_state->has_pch_encoder)
5106                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5107                                                       intel_crtc_pch_transcoder(crtc), true);
5108
5109         return 0;
5110 }
5111
5112 /*
5113  * If display is now connected check links status,
5114  * there has been known issues of link loss triggering
5115  * long pulse.
5116  *
5117  * Some sinks (eg. ASUS PB287Q) seem to perform some
5118  * weird HPD ping pong during modesets. So we can apparently
5119  * end up with HPD going low during a modeset, and then
5120  * going back up soon after. And once that happens we must
5121  * retrain the link to get a picture. That's in case no
5122  * userspace component reacted to intermittent HPD dip.
5123  */
5124 static enum intel_hotplug_state
5125 intel_dp_hotplug(struct intel_encoder *encoder,
5126                  struct intel_connector *connector,
5127                  bool irq_received)
5128 {
5129         struct drm_modeset_acquire_ctx ctx;
5130         enum intel_hotplug_state state;
5131         int ret;
5132
5133         state = intel_encoder_hotplug(encoder, connector, irq_received);
5134
5135         drm_modeset_acquire_init(&ctx, 0);
5136
5137         for (;;) {
5138                 ret = intel_dp_retrain_link(encoder, &ctx);
5139
5140                 if (ret == -EDEADLK) {
5141                         drm_modeset_backoff(&ctx);
5142                         continue;
5143                 }
5144
5145                 break;
5146         }
5147
5148         drm_modeset_drop_locks(&ctx);
5149         drm_modeset_acquire_fini(&ctx);
5150         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
5151
5152         /*
5153          * Keeping it consistent with intel_ddi_hotplug() and
5154          * intel_hdmi_hotplug().
5155          */
5156         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
5157                 state = INTEL_HOTPLUG_RETRY;
5158
5159         return state;
5160 }
5161
5162 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5163 {
5164         u8 val;
5165
5166         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5167                 return;
5168
5169         if (drm_dp_dpcd_readb(&intel_dp->aux,
5170                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5171                 return;
5172
5173         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5174
5175         if (val & DP_AUTOMATED_TEST_REQUEST)
5176                 intel_dp_handle_test_request(intel_dp);
5177
5178         if (val & DP_CP_IRQ)
5179                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5180
5181         if (val & DP_SINK_SPECIFIC_IRQ)
5182                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
5183 }
5184
5185 /*
5186  * According to DP spec
5187  * 5.1.2:
5188  *  1. Read DPCD
5189  *  2. Configure link according to Receiver Capabilities
5190  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5191  *  4. Check link status on receipt of hot-plug interrupt
5192  *
5193  * intel_dp_short_pulse -  handles short pulse interrupts
5194  * when full detection is not required.
5195  * Returns %true if short pulse is handled and full detection
5196  * is NOT required and %false otherwise.
5197  */
5198 static bool
5199 intel_dp_short_pulse(struct intel_dp *intel_dp)
5200 {
5201         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5202         u8 old_sink_count = intel_dp->sink_count;
5203         bool ret;
5204
5205         /*
5206          * Clearing compliance test variables to allow capturing
5207          * of values for next automated test request.
5208          */
5209         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5210
5211         /*
5212          * Now read the DPCD to see if it's actually running
5213          * If the current value of sink count doesn't match with
5214          * the value that was stored earlier or dpcd read failed
5215          * we need to do full detection
5216          */
5217         ret = intel_dp_get_dpcd(intel_dp);
5218
5219         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5220                 /* No need to proceed if we are going to do full detect */
5221                 return false;
5222         }
5223
5224         intel_dp_check_service_irq(intel_dp);
5225
5226         /* Handle CEC interrupts, if any */
5227         drm_dp_cec_irq(&intel_dp->aux);
5228
5229         /* defer to the hotplug work for link retraining if needed */
5230         if (intel_dp_needs_link_retrain(intel_dp))
5231                 return false;
5232
5233         intel_psr_short_pulse(intel_dp);
5234
5235         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5236                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
5237                 /* Send a Hotplug Uevent to userspace to start modeset */
5238                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5239         }
5240
5241         return true;
5242 }
5243
5244 /* XXX this is probably wrong for multiple downstream ports */
5245 static enum drm_connector_status
5246 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5247 {
5248         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5249         u8 *dpcd = intel_dp->dpcd;
5250         u8 type;
5251
5252         if (WARN_ON(intel_dp_is_edp(intel_dp)))
5253                 return connector_status_connected;
5254
5255         if (lspcon->active)
5256                 lspcon_resume(lspcon);
5257
5258         if (!intel_dp_get_dpcd(intel_dp))
5259                 return connector_status_disconnected;
5260
5261         /* if there's no downstream port, we're done */
5262         if (!drm_dp_is_branch(dpcd))
5263                 return connector_status_connected;
5264
5265         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5266         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5267             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5268
5269                 return intel_dp->sink_count ?
5270                 connector_status_connected : connector_status_disconnected;
5271         }
5272
5273         if (intel_dp_can_mst(intel_dp))
5274                 return connector_status_connected;
5275
5276         /* If no HPD, poke DDC gently */
5277         if (drm_probe_ddc(&intel_dp->aux.ddc))
5278                 return connector_status_connected;
5279
5280         /* Well we tried, say unknown for unreliable port types */
5281         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5282                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5283                 if (type == DP_DS_PORT_TYPE_VGA ||
5284                     type == DP_DS_PORT_TYPE_NON_EDID)
5285                         return connector_status_unknown;
5286         } else {
5287                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5288                         DP_DWN_STRM_PORT_TYPE_MASK;
5289                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5290                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5291                         return connector_status_unknown;
5292         }
5293
5294         /* Anything else is out of spec, warn and ignore */
5295         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5296         return connector_status_disconnected;
5297 }
5298
5299 static enum drm_connector_status
5300 edp_detect(struct intel_dp *intel_dp)
5301 {
5302         return connector_status_connected;
5303 }
5304
5305 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5306 {
5307         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5308         u32 bit;
5309
5310         switch (encoder->hpd_pin) {
5311         case HPD_PORT_B:
5312                 bit = SDE_PORTB_HOTPLUG;
5313                 break;
5314         case HPD_PORT_C:
5315                 bit = SDE_PORTC_HOTPLUG;
5316                 break;
5317         case HPD_PORT_D:
5318                 bit = SDE_PORTD_HOTPLUG;
5319                 break;
5320         default:
5321                 MISSING_CASE(encoder->hpd_pin);
5322                 return false;
5323         }
5324
5325         return I915_READ(SDEISR) & bit;
5326 }
5327
5328 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5329 {
5330         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5331         u32 bit;
5332
5333         switch (encoder->hpd_pin) {
5334         case HPD_PORT_B:
5335                 bit = SDE_PORTB_HOTPLUG_CPT;
5336                 break;
5337         case HPD_PORT_C:
5338                 bit = SDE_PORTC_HOTPLUG_CPT;
5339                 break;
5340         case HPD_PORT_D:
5341                 bit = SDE_PORTD_HOTPLUG_CPT;
5342                 break;
5343         default:
5344                 MISSING_CASE(encoder->hpd_pin);
5345                 return false;
5346         }
5347
5348         return I915_READ(SDEISR) & bit;
5349 }
5350
5351 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5352 {
5353         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5354         u32 bit;
5355
5356         switch (encoder->hpd_pin) {
5357         case HPD_PORT_A:
5358                 bit = SDE_PORTA_HOTPLUG_SPT;
5359                 break;
5360         case HPD_PORT_E:
5361                 bit = SDE_PORTE_HOTPLUG_SPT;
5362                 break;
5363         default:
5364                 return cpt_digital_port_connected(encoder);
5365         }
5366
5367         return I915_READ(SDEISR) & bit;
5368 }
5369
5370 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5371 {
5372         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5373         u32 bit;
5374
5375         switch (encoder->hpd_pin) {
5376         case HPD_PORT_B:
5377                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5378                 break;
5379         case HPD_PORT_C:
5380                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5381                 break;
5382         case HPD_PORT_D:
5383                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5384                 break;
5385         default:
5386                 MISSING_CASE(encoder->hpd_pin);
5387                 return false;
5388         }
5389
5390         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5391 }
5392
5393 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5394 {
5395         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5396         u32 bit;
5397
5398         switch (encoder->hpd_pin) {
5399         case HPD_PORT_B:
5400                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5401                 break;
5402         case HPD_PORT_C:
5403                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5404                 break;
5405         case HPD_PORT_D:
5406                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5407                 break;
5408         default:
5409                 MISSING_CASE(encoder->hpd_pin);
5410                 return false;
5411         }
5412
5413         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5414 }
5415
5416 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5417 {
5418         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5419
5420         if (encoder->hpd_pin == HPD_PORT_A)
5421                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5422         else
5423                 return ibx_digital_port_connected(encoder);
5424 }
5425
5426 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5427 {
5428         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5429
5430         if (encoder->hpd_pin == HPD_PORT_A)
5431                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5432         else
5433                 return cpt_digital_port_connected(encoder);
5434 }
5435
5436 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5437 {
5438         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5439
5440         if (encoder->hpd_pin == HPD_PORT_A)
5441                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5442         else
5443                 return cpt_digital_port_connected(encoder);
5444 }
5445
5446 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5447 {
5448         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5449
5450         if (encoder->hpd_pin == HPD_PORT_A)
5451                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5452         else
5453                 return cpt_digital_port_connected(encoder);
5454 }
5455
5456 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5457 {
5458         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5459         u32 bit;
5460
5461         switch (encoder->hpd_pin) {
5462         case HPD_PORT_A:
5463                 bit = BXT_DE_PORT_HP_DDIA;
5464                 break;
5465         case HPD_PORT_B:
5466                 bit = BXT_DE_PORT_HP_DDIB;
5467                 break;
5468         case HPD_PORT_C:
5469                 bit = BXT_DE_PORT_HP_DDIC;
5470                 break;
5471         default:
5472                 MISSING_CASE(encoder->hpd_pin);
5473                 return false;
5474         }
5475
5476         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5477 }
5478
5479 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5480                                      struct intel_digital_port *intel_dig_port)
5481 {
5482         enum port port = intel_dig_port->base.port;
5483
5484         if (HAS_PCH_MCC(dev_priv) && port == PORT_C)
5485                 return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
5486
5487         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5488 }
5489
5490 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5491 {
5492         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5493         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5494         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5495
5496         if (intel_phy_is_combo(dev_priv, phy))
5497                 return icl_combo_port_connected(dev_priv, dig_port);
5498         else if (intel_phy_is_tc(dev_priv, phy))
5499                 return intel_tc_port_connected(dig_port);
5500         else
5501                 MISSING_CASE(encoder->hpd_pin);
5502
5503         return false;
5504 }
5505
5506 /*
5507  * intel_digital_port_connected - is the specified port connected?
5508  * @encoder: intel_encoder
5509  *
5510  * In cases where there's a connector physically connected but it can't be used
5511  * by our hardware we also return false, since the rest of the driver should
5512  * pretty much treat the port as disconnected. This is relevant for type-C
5513  * (starting on ICL) where there's ownership involved.
5514  *
5515  * Return %true if port is connected, %false otherwise.
5516  */
5517 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5518 {
5519         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5520
5521         if (HAS_GMCH(dev_priv)) {
5522                 if (IS_GM45(dev_priv))
5523                         return gm45_digital_port_connected(encoder);
5524                 else
5525                         return g4x_digital_port_connected(encoder);
5526         }
5527
5528         if (INTEL_GEN(dev_priv) >= 11)
5529                 return icl_digital_port_connected(encoder);
5530         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5531                 return spt_digital_port_connected(encoder);
5532         else if (IS_GEN9_LP(dev_priv))
5533                 return bxt_digital_port_connected(encoder);
5534         else if (IS_GEN(dev_priv, 8))
5535                 return bdw_digital_port_connected(encoder);
5536         else if (IS_GEN(dev_priv, 7))
5537                 return ivb_digital_port_connected(encoder);
5538         else if (IS_GEN(dev_priv, 6))
5539                 return snb_digital_port_connected(encoder);
5540         else if (IS_GEN(dev_priv, 5))
5541                 return ilk_digital_port_connected(encoder);
5542
5543         MISSING_CASE(INTEL_GEN(dev_priv));
5544         return false;
5545 }
5546
5547 bool intel_digital_port_connected(struct intel_encoder *encoder)
5548 {
5549         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5550         bool is_connected = false;
5551         intel_wakeref_t wakeref;
5552
5553         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5554                 is_connected = __intel_digital_port_connected(encoder);
5555
5556         return is_connected;
5557 }
5558
5559 static struct edid *
5560 intel_dp_get_edid(struct intel_dp *intel_dp)
5561 {
5562         struct intel_connector *intel_connector = intel_dp->attached_connector;
5563
5564         /* use cached edid if we have one */
5565         if (intel_connector->edid) {
5566                 /* invalid edid */
5567                 if (IS_ERR(intel_connector->edid))
5568                         return NULL;
5569
5570                 return drm_edid_duplicate(intel_connector->edid);
5571         } else
5572                 return drm_get_edid(&intel_connector->base,
5573                                     &intel_dp->aux.ddc);
5574 }
5575
5576 static void
5577 intel_dp_set_edid(struct intel_dp *intel_dp)
5578 {
5579         struct intel_connector *intel_connector = intel_dp->attached_connector;
5580         struct edid *edid;
5581
5582         intel_dp_unset_edid(intel_dp);
5583         edid = intel_dp_get_edid(intel_dp);
5584         intel_connector->detect_edid = edid;
5585
5586         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5587         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5588 }
5589
5590 static void
5591 intel_dp_unset_edid(struct intel_dp *intel_dp)
5592 {
5593         struct intel_connector *intel_connector = intel_dp->attached_connector;
5594
5595         drm_dp_cec_unset_edid(&intel_dp->aux);
5596         kfree(intel_connector->detect_edid);
5597         intel_connector->detect_edid = NULL;
5598
5599         intel_dp->has_audio = false;
5600 }
5601
5602 static int
5603 intel_dp_detect(struct drm_connector *connector,
5604                 struct drm_modeset_acquire_ctx *ctx,
5605                 bool force)
5606 {
5607         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5608         struct intel_dp *intel_dp = intel_attached_dp(connector);
5609         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5610         struct intel_encoder *encoder = &dig_port->base;
5611         enum drm_connector_status status;
5612
5613         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5614                       connector->base.id, connector->name);
5615         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5616
5617         /* Can't disconnect eDP */
5618         if (intel_dp_is_edp(intel_dp))
5619                 status = edp_detect(intel_dp);
5620         else if (intel_digital_port_connected(encoder))
5621                 status = intel_dp_detect_dpcd(intel_dp);
5622         else
5623                 status = connector_status_disconnected;
5624
5625         if (status == connector_status_disconnected) {
5626                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5627                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5628
5629                 if (intel_dp->is_mst) {
5630                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5631                                       intel_dp->is_mst,
5632                                       intel_dp->mst_mgr.mst_state);
5633                         intel_dp->is_mst = false;
5634                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5635                                                         intel_dp->is_mst);
5636                 }
5637
5638                 goto out;
5639         }
5640
5641         if (intel_dp->reset_link_params) {
5642                 /* Initial max link lane count */
5643                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5644
5645                 /* Initial max link rate */
5646                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5647
5648                 intel_dp->reset_link_params = false;
5649         }
5650
5651         intel_dp_print_rates(intel_dp);
5652
5653         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5654         if (INTEL_GEN(dev_priv) >= 11)
5655                 intel_dp_get_dsc_sink_cap(intel_dp);
5656
5657         intel_dp_configure_mst(intel_dp);
5658
5659         if (intel_dp->is_mst) {
5660                 /*
5661                  * If we are in MST mode then this connector
5662                  * won't appear connected or have anything
5663                  * with EDID on it
5664                  */
5665                 status = connector_status_disconnected;
5666                 goto out;
5667         }
5668
5669         /*
5670          * Some external monitors do not signal loss of link synchronization
5671          * with an IRQ_HPD, so force a link status check.
5672          */
5673         if (!intel_dp_is_edp(intel_dp)) {
5674                 int ret;
5675
5676                 ret = intel_dp_retrain_link(encoder, ctx);
5677                 if (ret)
5678                         return ret;
5679         }
5680
5681         /*
5682          * Clearing NACK and defer counts to get their exact values
5683          * while reading EDID which are required by Compliance tests
5684          * 4.2.2.4 and 4.2.2.5
5685          */
5686         intel_dp->aux.i2c_nack_count = 0;
5687         intel_dp->aux.i2c_defer_count = 0;
5688
5689         intel_dp_set_edid(intel_dp);
5690         if (intel_dp_is_edp(intel_dp) ||
5691             to_intel_connector(connector)->detect_edid)
5692                 status = connector_status_connected;
5693
5694         intel_dp_check_service_irq(intel_dp);
5695
5696 out:
5697         if (status != connector_status_connected && !intel_dp->is_mst)
5698                 intel_dp_unset_edid(intel_dp);
5699
5700         /*
5701          * Make sure the refs for power wells enabled during detect are
5702          * dropped to avoid a new detect cycle triggered by HPD polling.
5703          */
5704         intel_display_power_flush_work(dev_priv);
5705
5706         return status;
5707 }
5708
5709 static void
5710 intel_dp_force(struct drm_connector *connector)
5711 {
5712         struct intel_dp *intel_dp = intel_attached_dp(connector);
5713         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5714         struct intel_encoder *intel_encoder = &dig_port->base;
5715         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5716         enum intel_display_power_domain aux_domain =
5717                 intel_aux_power_domain(dig_port);
5718         intel_wakeref_t wakeref;
5719
5720         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5721                       connector->base.id, connector->name);
5722         intel_dp_unset_edid(intel_dp);
5723
5724         if (connector->status != connector_status_connected)
5725                 return;
5726
5727         wakeref = intel_display_power_get(dev_priv, aux_domain);
5728
5729         intel_dp_set_edid(intel_dp);
5730
5731         intel_display_power_put(dev_priv, aux_domain, wakeref);
5732 }
5733
5734 static int intel_dp_get_modes(struct drm_connector *connector)
5735 {
5736         struct intel_connector *intel_connector = to_intel_connector(connector);
5737         struct edid *edid;
5738
5739         edid = intel_connector->detect_edid;
5740         if (edid) {
5741                 int ret = intel_connector_update_modes(connector, edid);
5742                 if (ret)
5743                         return ret;
5744         }
5745
5746         /* if eDP has no EDID, fall back to fixed mode */
5747         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5748             intel_connector->panel.fixed_mode) {
5749                 struct drm_display_mode *mode;
5750
5751                 mode = drm_mode_duplicate(connector->dev,
5752                                           intel_connector->panel.fixed_mode);
5753                 if (mode) {
5754                         drm_mode_probed_add(connector, mode);
5755                         return 1;
5756                 }
5757         }
5758
5759         return 0;
5760 }
5761
5762 static int
5763 intel_dp_connector_register(struct drm_connector *connector)
5764 {
5765         struct intel_dp *intel_dp = intel_attached_dp(connector);
5766         int ret;
5767
5768         ret = intel_connector_register(connector);
5769         if (ret)
5770                 return ret;
5771
5772         i915_debugfs_connector_add(connector);
5773
5774         DRM_DEBUG_KMS("registering %s bus for %s\n",
5775                       intel_dp->aux.name, connector->kdev->kobj.name);
5776
5777         intel_dp->aux.dev = connector->kdev;
5778         ret = drm_dp_aux_register(&intel_dp->aux);
5779         if (!ret)
5780                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5781         return ret;
5782 }
5783
5784 static void
5785 intel_dp_connector_unregister(struct drm_connector *connector)
5786 {
5787         struct intel_dp *intel_dp = intel_attached_dp(connector);
5788
5789         drm_dp_cec_unregister_connector(&intel_dp->aux);
5790         drm_dp_aux_unregister(&intel_dp->aux);
5791         intel_connector_unregister(connector);
5792 }
5793
5794 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5795 {
5796         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5797         struct intel_dp *intel_dp = &intel_dig_port->dp;
5798
5799         intel_dp_mst_encoder_cleanup(intel_dig_port);
5800         if (intel_dp_is_edp(intel_dp)) {
5801                 intel_wakeref_t wakeref;
5802
5803                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5804                 /*
5805                  * vdd might still be enabled do to the delayed vdd off.
5806                  * Make sure vdd is actually turned off here.
5807                  */
5808                 with_pps_lock(intel_dp, wakeref)
5809                         edp_panel_vdd_off_sync(intel_dp);
5810
5811                 if (intel_dp->edp_notifier.notifier_call) {
5812                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5813                         intel_dp->edp_notifier.notifier_call = NULL;
5814                 }
5815         }
5816
5817         intel_dp_aux_fini(intel_dp);
5818 }
5819
5820 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5821 {
5822         intel_dp_encoder_flush_work(encoder);
5823
5824         drm_encoder_cleanup(encoder);
5825         kfree(enc_to_dig_port(encoder));
5826 }
5827
5828 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5829 {
5830         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5831         intel_wakeref_t wakeref;
5832
5833         if (!intel_dp_is_edp(intel_dp))
5834                 return;
5835
5836         /*
5837          * vdd might still be enabled do to the delayed vdd off.
5838          * Make sure vdd is actually turned off here.
5839          */
5840         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5841         with_pps_lock(intel_dp, wakeref)
5842                 edp_panel_vdd_off_sync(intel_dp);
5843 }
5844
5845 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5846 {
5847         long ret;
5848
5849 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5850         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5851                                                msecs_to_jiffies(timeout));
5852
5853         if (!ret)
5854                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5855 }
5856
5857 static
5858 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5859                                 u8 *an)
5860 {
5861         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5862         static const struct drm_dp_aux_msg msg = {
5863                 .request = DP_AUX_NATIVE_WRITE,
5864                 .address = DP_AUX_HDCP_AKSV,
5865                 .size = DRM_HDCP_KSV_LEN,
5866         };
5867         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5868         ssize_t dpcd_ret;
5869         int ret;
5870
5871         /* Output An first, that's easy */
5872         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5873                                      an, DRM_HDCP_AN_LEN);
5874         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5875                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5876                               dpcd_ret);
5877                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5878         }
5879
5880         /*
5881          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5882          * order to get it on the wire, we need to create the AUX header as if
5883          * we were writing the data, and then tickle the hardware to output the
5884          * data once the header is sent out.
5885          */
5886         intel_dp_aux_header(txbuf, &msg);
5887
5888         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5889                                 rxbuf, sizeof(rxbuf),
5890                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5891         if (ret < 0) {
5892                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5893                 return ret;
5894         } else if (ret == 0) {
5895                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5896                 return -EIO;
5897         }
5898
5899         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5900         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5901                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5902                               reply);
5903                 return -EIO;
5904         }
5905         return 0;
5906 }
5907
5908 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5909                                    u8 *bksv)
5910 {
5911         ssize_t ret;
5912         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5913                                DRM_HDCP_KSV_LEN);
5914         if (ret != DRM_HDCP_KSV_LEN) {
5915                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5916                 return ret >= 0 ? -EIO : ret;
5917         }
5918         return 0;
5919 }
5920
5921 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5922                                       u8 *bstatus)
5923 {
5924         ssize_t ret;
5925         /*
5926          * For some reason the HDMI and DP HDCP specs call this register
5927          * definition by different names. In the HDMI spec, it's called BSTATUS,
5928          * but in DP it's called BINFO.
5929          */
5930         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5931                                bstatus, DRM_HDCP_BSTATUS_LEN);
5932         if (ret != DRM_HDCP_BSTATUS_LEN) {
5933                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5934                 return ret >= 0 ? -EIO : ret;
5935         }
5936         return 0;
5937 }
5938
5939 static
5940 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5941                              u8 *bcaps)
5942 {
5943         ssize_t ret;
5944
5945         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5946                                bcaps, 1);
5947         if (ret != 1) {
5948                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5949                 return ret >= 0 ? -EIO : ret;
5950         }
5951
5952         return 0;
5953 }
5954
5955 static
5956 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5957                                    bool *repeater_present)
5958 {
5959         ssize_t ret;
5960         u8 bcaps;
5961
5962         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5963         if (ret)
5964                 return ret;
5965
5966         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5967         return 0;
5968 }
5969
5970 static
5971 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5972                                 u8 *ri_prime)
5973 {
5974         ssize_t ret;
5975         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5976                                ri_prime, DRM_HDCP_RI_LEN);
5977         if (ret != DRM_HDCP_RI_LEN) {
5978                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5979                 return ret >= 0 ? -EIO : ret;
5980         }
5981         return 0;
5982 }
5983
5984 static
5985 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5986                                  bool *ksv_ready)
5987 {
5988         ssize_t ret;
5989         u8 bstatus;
5990         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5991                                &bstatus, 1);
5992         if (ret != 1) {
5993                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5994                 return ret >= 0 ? -EIO : ret;
5995         }
5996         *ksv_ready = bstatus & DP_BSTATUS_READY;
5997         return 0;
5998 }
5999
6000 static
6001 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6002                                 int num_downstream, u8 *ksv_fifo)
6003 {
6004         ssize_t ret;
6005         int i;
6006
6007         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6008         for (i = 0; i < num_downstream; i += 3) {
6009                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6010                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6011                                        DP_AUX_HDCP_KSV_FIFO,
6012                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
6013                                        len);
6014                 if (ret != len) {
6015                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
6016                                       i, ret);
6017                         return ret >= 0 ? -EIO : ret;
6018                 }
6019         }
6020         return 0;
6021 }
6022
6023 static
6024 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6025                                     int i, u32 *part)
6026 {
6027         ssize_t ret;
6028
6029         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6030                 return -EINVAL;
6031
6032         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6033                                DP_AUX_HDCP_V_PRIME(i), part,
6034                                DRM_HDCP_V_PRIME_PART_LEN);
6035         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6036                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6037                 return ret >= 0 ? -EIO : ret;
6038         }
6039         return 0;
6040 }
6041
6042 static
6043 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6044                                     bool enable)
6045 {
6046         /* Not used for single stream DisplayPort setups */
6047         return 0;
6048 }
6049
6050 static
6051 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6052 {
6053         ssize_t ret;
6054         u8 bstatus;
6055
6056         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6057                                &bstatus, 1);
6058         if (ret != 1) {
6059                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6060                 return false;
6061         }
6062
6063         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6064 }
6065
6066 static
6067 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6068                           bool *hdcp_capable)
6069 {
6070         ssize_t ret;
6071         u8 bcaps;
6072
6073         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6074         if (ret)
6075                 return ret;
6076
6077         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6078         return 0;
6079 }
6080
6081 struct hdcp2_dp_errata_stream_type {
6082         u8      msg_id;
6083         u8      stream_type;
6084 } __packed;
6085
6086 struct hdcp2_dp_msg_data {
6087         u8 msg_id;
6088         u32 offset;
6089         bool msg_detectable;
6090         u32 timeout;
6091         u32 timeout2; /* Added for non_paired situation */
6092 };
6093
6094 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6095         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6096         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6097           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6098         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6099           false, 0, 0 },
6100         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6101           false, 0, 0 },
6102         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6103           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6104           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6105         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6106           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6107           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6108         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6109         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6110           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6111         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6112           0, 0 },
6113         { HDCP_2_2_REP_SEND_RECVID_LIST,
6114           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6115           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6116         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6117           0, 0 },
6118         { HDCP_2_2_REP_STREAM_MANAGE,
6119           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6120           0, 0 },
6121         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6122           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6123 /* local define to shovel this through the write_2_2 interface */
6124 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
6125         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6126           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6127           0, 0 },
6128 };
6129
6130 static inline
6131 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6132                                   u8 *rx_status)
6133 {
6134         ssize_t ret;
6135
6136         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6137                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6138                                HDCP_2_2_DP_RXSTATUS_LEN);
6139         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6140                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6141                 return ret >= 0 ? -EIO : ret;
6142         }
6143
6144         return 0;
6145 }
6146
6147 static
6148 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6149                                   u8 msg_id, bool *msg_ready)
6150 {
6151         u8 rx_status;
6152         int ret;
6153
6154         *msg_ready = false;
6155         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6156         if (ret < 0)
6157                 return ret;
6158
6159         switch (msg_id) {
6160         case HDCP_2_2_AKE_SEND_HPRIME:
6161                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6162                         *msg_ready = true;
6163                 break;
6164         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6165                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6166                         *msg_ready = true;
6167                 break;
6168         case HDCP_2_2_REP_SEND_RECVID_LIST:
6169                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6170                         *msg_ready = true;
6171                 break;
6172         default:
6173                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6174                 return -EINVAL;
6175         }
6176
6177         return 0;
6178 }
6179
6180 static ssize_t
6181 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6182                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6183 {
6184         struct intel_dp *dp = &intel_dig_port->dp;
6185         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6186         u8 msg_id = hdcp2_msg_data->msg_id;
6187         int ret, timeout;
6188         bool msg_ready = false;
6189
6190         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6191                 timeout = hdcp2_msg_data->timeout2;
6192         else
6193                 timeout = hdcp2_msg_data->timeout;
6194
6195         /*
6196          * There is no way to detect the CERT, LPRIME and STREAM_READY
6197          * availability. So Wait for timeout and read the msg.
6198          */
6199         if (!hdcp2_msg_data->msg_detectable) {
6200                 mdelay(timeout);
6201                 ret = 0;
6202         } else {
6203                 /*
6204                  * As we want to check the msg availability at timeout, Ignoring
6205                  * the timeout at wait for CP_IRQ.
6206                  */
6207                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6208                 ret = hdcp2_detect_msg_availability(intel_dig_port,
6209                                                     msg_id, &msg_ready);
6210                 if (!msg_ready)
6211                         ret = -ETIMEDOUT;
6212         }
6213
6214         if (ret)
6215                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6216                               hdcp2_msg_data->msg_id, ret, timeout);
6217
6218         return ret;
6219 }
6220
6221 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6222 {
6223         int i;
6224
6225         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6226                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6227                         return &hdcp2_dp_msg_data[i];
6228
6229         return NULL;
6230 }
6231
6232 static
6233 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6234                              void *buf, size_t size)
6235 {
6236         struct intel_dp *dp = &intel_dig_port->dp;
6237         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6238         unsigned int offset;
6239         u8 *byte = buf;
6240         ssize_t ret, bytes_to_write, len;
6241         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6242
6243         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6244         if (!hdcp2_msg_data)
6245                 return -EINVAL;
6246
6247         offset = hdcp2_msg_data->offset;
6248
6249         /* No msg_id in DP HDCP2.2 msgs */
6250         bytes_to_write = size - 1;
6251         byte++;
6252
6253         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6254
6255         while (bytes_to_write) {
6256                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6257                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6258
6259                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6260                                         offset, (void *)byte, len);
6261                 if (ret < 0)
6262                         return ret;
6263
6264                 bytes_to_write -= ret;
6265                 byte += ret;
6266                 offset += ret;
6267         }
6268
6269         return size;
6270 }
6271
6272 static
6273 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6274 {
6275         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6276         u32 dev_cnt;
6277         ssize_t ret;
6278
6279         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6280                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6281                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6282         if (ret != HDCP_2_2_RXINFO_LEN)
6283                 return ret >= 0 ? -EIO : ret;
6284
6285         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6286                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6287
6288         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6289                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6290
6291         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6292                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6293                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6294
6295         return ret;
6296 }
6297
6298 static
6299 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6300                             u8 msg_id, void *buf, size_t size)
6301 {
6302         unsigned int offset;
6303         u8 *byte = buf;
6304         ssize_t ret, bytes_to_recv, len;
6305         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6306
6307         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6308         if (!hdcp2_msg_data)
6309                 return -EINVAL;
6310         offset = hdcp2_msg_data->offset;
6311
6312         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6313         if (ret < 0)
6314                 return ret;
6315
6316         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6317                 ret = get_receiver_id_list_size(intel_dig_port);
6318                 if (ret < 0)
6319                         return ret;
6320
6321                 size = ret;
6322         }
6323         bytes_to_recv = size - 1;
6324
6325         /* DP adaptation msgs has no msg_id */
6326         byte++;
6327
6328         while (bytes_to_recv) {
6329                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6330                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6331
6332                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6333                                        (void *)byte, len);
6334                 if (ret < 0) {
6335                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6336                         return ret;
6337                 }
6338
6339                 bytes_to_recv -= ret;
6340                 byte += ret;
6341                 offset += ret;
6342         }
6343         byte = buf;
6344         *byte = msg_id;
6345
6346         return size;
6347 }
6348
6349 static
6350 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6351                                       bool is_repeater, u8 content_type)
6352 {
6353         struct hdcp2_dp_errata_stream_type stream_type_msg;
6354
6355         if (is_repeater)
6356                 return 0;
6357
6358         /*
6359          * Errata for DP: As Stream type is used for encryption, Receiver
6360          * should be communicated with stream type for the decryption of the
6361          * content.
6362          * Repeater will be communicated with stream type as a part of it's
6363          * auth later in time.
6364          */
6365         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6366         stream_type_msg.stream_type = content_type;
6367
6368         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6369                                         sizeof(stream_type_msg));
6370 }
6371
6372 static
6373 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6374 {
6375         u8 rx_status;
6376         int ret;
6377
6378         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6379         if (ret)
6380                 return ret;
6381
6382         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6383                 ret = HDCP_REAUTH_REQUEST;
6384         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6385                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6386         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6387                 ret = HDCP_TOPOLOGY_CHANGE;
6388
6389         return ret;
6390 }
6391
6392 static
6393 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6394                            bool *capable)
6395 {
6396         u8 rx_caps[3];
6397         int ret;
6398
6399         *capable = false;
6400         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6401                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6402                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6403         if (ret != HDCP_2_2_RXCAPS_LEN)
6404                 return ret >= 0 ? -EIO : ret;
6405
6406         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6407             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6408                 *capable = true;
6409
6410         return 0;
6411 }
6412
6413 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6414         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6415         .read_bksv = intel_dp_hdcp_read_bksv,
6416         .read_bstatus = intel_dp_hdcp_read_bstatus,
6417         .repeater_present = intel_dp_hdcp_repeater_present,
6418         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6419         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6420         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6421         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6422         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6423         .check_link = intel_dp_hdcp_check_link,
6424         .hdcp_capable = intel_dp_hdcp_capable,
6425         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6426         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6427         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6428         .check_2_2_link = intel_dp_hdcp2_check_link,
6429         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6430         .protocol = HDCP_PROTOCOL_DP,
6431 };
6432
6433 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6434 {
6435         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6436         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6437
6438         lockdep_assert_held(&dev_priv->pps_mutex);
6439
6440         if (!edp_have_panel_vdd(intel_dp))
6441                 return;
6442
6443         /*
6444          * The VDD bit needs a power domain reference, so if the bit is
6445          * already enabled when we boot or resume, grab this reference and
6446          * schedule a vdd off, so we don't hold on to the reference
6447          * indefinitely.
6448          */
6449         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6450         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6451
6452         edp_panel_vdd_schedule_off(intel_dp);
6453 }
6454
6455 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6456 {
6457         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6458         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6459         enum pipe pipe;
6460
6461         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6462                                   encoder->port, &pipe))
6463                 return pipe;
6464
6465         return INVALID_PIPE;
6466 }
6467
6468 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6469 {
6470         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6471         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6472         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6473         intel_wakeref_t wakeref;
6474
6475         if (!HAS_DDI(dev_priv))
6476                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6477
6478         if (lspcon->active)
6479                 lspcon_resume(lspcon);
6480
6481         intel_dp->reset_link_params = true;
6482
6483         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6484             !intel_dp_is_edp(intel_dp))
6485                 return;
6486
6487         with_pps_lock(intel_dp, wakeref) {
6488                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6489                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6490
6491                 if (intel_dp_is_edp(intel_dp)) {
6492                         /*
6493                          * Reinit the power sequencer, in case BIOS did
6494                          * something nasty with it.
6495                          */
6496                         intel_dp_pps_init(intel_dp);
6497                         intel_edp_panel_vdd_sanitize(intel_dp);
6498                 }
6499         }
6500 }
6501
6502 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6503         .force = intel_dp_force,
6504         .fill_modes = drm_helper_probe_single_connector_modes,
6505         .atomic_get_property = intel_digital_connector_atomic_get_property,
6506         .atomic_set_property = intel_digital_connector_atomic_set_property,
6507         .late_register = intel_dp_connector_register,
6508         .early_unregister = intel_dp_connector_unregister,
6509         .destroy = intel_connector_destroy,
6510         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6511         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6512 };
6513
6514 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6515         .detect_ctx = intel_dp_detect,
6516         .get_modes = intel_dp_get_modes,
6517         .mode_valid = intel_dp_mode_valid,
6518         .atomic_check = intel_digital_connector_atomic_check,
6519 };
6520
6521 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6522         .reset = intel_dp_encoder_reset,
6523         .destroy = intel_dp_encoder_destroy,
6524 };
6525
6526 enum irqreturn
6527 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6528 {
6529         struct intel_dp *intel_dp = &intel_dig_port->dp;
6530
6531         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6532                 /*
6533                  * vdd off can generate a long pulse on eDP which
6534                  * would require vdd on to handle it, and thus we
6535                  * would end up in an endless cycle of
6536                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6537                  */
6538                 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6539                               intel_dig_port->base.base.base.id,
6540                               intel_dig_port->base.base.name);
6541                 return IRQ_HANDLED;
6542         }
6543
6544         DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6545                       intel_dig_port->base.base.base.id,
6546                       intel_dig_port->base.base.name,
6547                       long_hpd ? "long" : "short");
6548
6549         if (long_hpd) {
6550                 intel_dp->reset_link_params = true;
6551                 return IRQ_NONE;
6552         }
6553
6554         if (intel_dp->is_mst) {
6555                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6556                         /*
6557                          * If we were in MST mode, and device is not
6558                          * there, get out of MST mode
6559                          */
6560                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6561                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6562                         intel_dp->is_mst = false;
6563                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6564                                                         intel_dp->is_mst);
6565
6566                         return IRQ_NONE;
6567                 }
6568         }
6569
6570         if (!intel_dp->is_mst) {
6571                 bool handled;
6572
6573                 handled = intel_dp_short_pulse(intel_dp);
6574
6575                 if (!handled)
6576                         return IRQ_NONE;
6577         }
6578
6579         return IRQ_HANDLED;
6580 }
6581
6582 /* check the VBT to see whether the eDP is on another port */
6583 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6584 {
6585         /*
6586          * eDP not supported on g4x. so bail out early just
6587          * for a bit extra safety in case the VBT is bonkers.
6588          */
6589         if (INTEL_GEN(dev_priv) < 5)
6590                 return false;
6591
6592         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6593                 return true;
6594
6595         return intel_bios_is_port_edp(dev_priv, port);
6596 }
6597
6598 static void
6599 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6600 {
6601         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6602         enum port port = dp_to_dig_port(intel_dp)->base.port;
6603
6604         if (!IS_G4X(dev_priv) && port != PORT_A)
6605                 intel_attach_force_audio_property(connector);
6606
6607         intel_attach_broadcast_rgb_property(connector);
6608         if (HAS_GMCH(dev_priv))
6609                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6610         else if (INTEL_GEN(dev_priv) >= 5)
6611                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6612
6613         intel_attach_colorspace_property(connector);
6614
6615         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
6616                 drm_object_attach_property(&connector->base,
6617                                            connector->dev->mode_config.hdr_output_metadata_property,
6618                                            0);
6619
6620         if (intel_dp_is_edp(intel_dp)) {
6621                 u32 allowed_scalers;
6622
6623                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6624                 if (!HAS_GMCH(dev_priv))
6625                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6626
6627                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6628
6629                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6630
6631         }
6632 }
6633
6634 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6635 {
6636         intel_dp->panel_power_off_time = ktime_get_boottime();
6637         intel_dp->last_power_on = jiffies;
6638         intel_dp->last_backlight_off = jiffies;
6639 }
6640
6641 static void
6642 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6643 {
6644         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6645         u32 pp_on, pp_off, pp_ctl;
6646         struct pps_registers regs;
6647
6648         intel_pps_get_registers(intel_dp, &regs);
6649
6650         pp_ctl = ironlake_get_pp_control(intel_dp);
6651
6652         /* Ensure PPS is unlocked */
6653         if (!HAS_DDI(dev_priv))
6654                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6655
6656         pp_on = I915_READ(regs.pp_on);
6657         pp_off = I915_READ(regs.pp_off);
6658
6659         /* Pull timing values out of registers */
6660         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6661         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6662         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6663         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6664
6665         if (i915_mmio_reg_valid(regs.pp_div)) {
6666                 u32 pp_div;
6667
6668                 pp_div = I915_READ(regs.pp_div);
6669
6670                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6671         } else {
6672                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6673         }
6674 }
6675
6676 static void
6677 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6678 {
6679         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6680                       state_name,
6681                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6682 }
6683
6684 static void
6685 intel_pps_verify_state(struct intel_dp *intel_dp)
6686 {
6687         struct edp_power_seq hw;
6688         struct edp_power_seq *sw = &intel_dp->pps_delays;
6689
6690         intel_pps_readout_hw_state(intel_dp, &hw);
6691
6692         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6693             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6694                 DRM_ERROR("PPS state mismatch\n");
6695                 intel_pps_dump_state("sw", sw);
6696                 intel_pps_dump_state("hw", &hw);
6697         }
6698 }
6699
6700 static void
6701 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6702 {
6703         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6704         struct edp_power_seq cur, vbt, spec,
6705                 *final = &intel_dp->pps_delays;
6706
6707         lockdep_assert_held(&dev_priv->pps_mutex);
6708
6709         /* already initialized? */
6710         if (final->t11_t12 != 0)
6711                 return;
6712
6713         intel_pps_readout_hw_state(intel_dp, &cur);
6714
6715         intel_pps_dump_state("cur", &cur);
6716
6717         vbt = dev_priv->vbt.edp.pps;
6718         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6719          * of 500ms appears to be too short. Ocassionally the panel
6720          * just fails to power back on. Increasing the delay to 800ms
6721          * seems sufficient to avoid this problem.
6722          */
6723         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6724                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6725                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6726                               vbt.t11_t12);
6727         }
6728         /* T11_T12 delay is special and actually in units of 100ms, but zero
6729          * based in the hw (so we need to add 100 ms). But the sw vbt
6730          * table multiplies it with 1000 to make it in units of 100usec,
6731          * too. */
6732         vbt.t11_t12 += 100 * 10;
6733
6734         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6735          * our hw here, which are all in 100usec. */
6736         spec.t1_t3 = 210 * 10;
6737         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6738         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6739         spec.t10 = 500 * 10;
6740         /* This one is special and actually in units of 100ms, but zero
6741          * based in the hw (so we need to add 100 ms). But the sw vbt
6742          * table multiplies it with 1000 to make it in units of 100usec,
6743          * too. */
6744         spec.t11_t12 = (510 + 100) * 10;
6745
6746         intel_pps_dump_state("vbt", &vbt);
6747
6748         /* Use the max of the register settings and vbt. If both are
6749          * unset, fall back to the spec limits. */
6750 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6751                                        spec.field : \
6752                                        max(cur.field, vbt.field))
6753         assign_final(t1_t3);
6754         assign_final(t8);
6755         assign_final(t9);
6756         assign_final(t10);
6757         assign_final(t11_t12);
6758 #undef assign_final
6759
6760 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6761         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6762         intel_dp->backlight_on_delay = get_delay(t8);
6763         intel_dp->backlight_off_delay = get_delay(t9);
6764         intel_dp->panel_power_down_delay = get_delay(t10);
6765         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6766 #undef get_delay
6767
6768         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6769                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6770                       intel_dp->panel_power_cycle_delay);
6771
6772         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6773                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6774
6775         /*
6776          * We override the HW backlight delays to 1 because we do manual waits
6777          * on them. For T8, even BSpec recommends doing it. For T9, if we
6778          * don't do this, we'll end up waiting for the backlight off delay
6779          * twice: once when we do the manual sleep, and once when we disable
6780          * the panel and wait for the PP_STATUS bit to become zero.
6781          */
6782         final->t8 = 1;
6783         final->t9 = 1;
6784
6785         /*
6786          * HW has only a 100msec granularity for t11_t12 so round it up
6787          * accordingly.
6788          */
6789         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6790 }
6791
6792 static void
6793 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6794                                               bool force_disable_vdd)
6795 {
6796         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6797         u32 pp_on, pp_off, port_sel = 0;
6798         int div = dev_priv->rawclk_freq / 1000;
6799         struct pps_registers regs;
6800         enum port port = dp_to_dig_port(intel_dp)->base.port;
6801         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6802
6803         lockdep_assert_held(&dev_priv->pps_mutex);
6804
6805         intel_pps_get_registers(intel_dp, &regs);
6806
6807         /*
6808          * On some VLV machines the BIOS can leave the VDD
6809          * enabled even on power sequencers which aren't
6810          * hooked up to any port. This would mess up the
6811          * power domain tracking the first time we pick
6812          * one of these power sequencers for use since
6813          * edp_panel_vdd_on() would notice that the VDD was
6814          * already on and therefore wouldn't grab the power
6815          * domain reference. Disable VDD first to avoid this.
6816          * This also avoids spuriously turning the VDD on as
6817          * soon as the new power sequencer gets initialized.
6818          */
6819         if (force_disable_vdd) {
6820                 u32 pp = ironlake_get_pp_control(intel_dp);
6821
6822                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6823
6824                 if (pp & EDP_FORCE_VDD)
6825                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6826
6827                 pp &= ~EDP_FORCE_VDD;
6828
6829                 I915_WRITE(regs.pp_ctrl, pp);
6830         }
6831
6832         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6833                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6834         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6835                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6836
6837         /* Haswell doesn't have any port selection bits for the panel
6838          * power sequencer any more. */
6839         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6840                 port_sel = PANEL_PORT_SELECT_VLV(port);
6841         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6842                 switch (port) {
6843                 case PORT_A:
6844                         port_sel = PANEL_PORT_SELECT_DPA;
6845                         break;
6846                 case PORT_C:
6847                         port_sel = PANEL_PORT_SELECT_DPC;
6848                         break;
6849                 case PORT_D:
6850                         port_sel = PANEL_PORT_SELECT_DPD;
6851                         break;
6852                 default:
6853                         MISSING_CASE(port);
6854                         break;
6855                 }
6856         }
6857
6858         pp_on |= port_sel;
6859
6860         I915_WRITE(regs.pp_on, pp_on);
6861         I915_WRITE(regs.pp_off, pp_off);
6862
6863         /*
6864          * Compute the divisor for the pp clock, simply match the Bspec formula.
6865          */
6866         if (i915_mmio_reg_valid(regs.pp_div)) {
6867                 I915_WRITE(regs.pp_div,
6868                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6869                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6870         } else {
6871                 u32 pp_ctl;
6872
6873                 pp_ctl = I915_READ(regs.pp_ctrl);
6874                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6875                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6876                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6877         }
6878
6879         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6880                       I915_READ(regs.pp_on),
6881                       I915_READ(regs.pp_off),
6882                       i915_mmio_reg_valid(regs.pp_div) ?
6883                       I915_READ(regs.pp_div) :
6884                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6885 }
6886
6887 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6888 {
6889         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6890
6891         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6892                 vlv_initial_power_sequencer_setup(intel_dp);
6893         } else {
6894                 intel_dp_init_panel_power_sequencer(intel_dp);
6895                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6896         }
6897 }
6898
6899 /**
6900  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6901  * @dev_priv: i915 device
6902  * @crtc_state: a pointer to the active intel_crtc_state
6903  * @refresh_rate: RR to be programmed
6904  *
6905  * This function gets called when refresh rate (RR) has to be changed from
6906  * one frequency to another. Switches can be between high and low RR
6907  * supported by the panel or to any other RR based on media playback (in
6908  * this case, RR value needs to be passed from user space).
6909  *
6910  * The caller of this function needs to take a lock on dev_priv->drrs.
6911  */
6912 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6913                                     const struct intel_crtc_state *crtc_state,
6914                                     int refresh_rate)
6915 {
6916         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6918         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6919
6920         if (refresh_rate <= 0) {
6921                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6922                 return;
6923         }
6924
6925         if (intel_dp == NULL) {
6926                 DRM_DEBUG_KMS("DRRS not supported.\n");
6927                 return;
6928         }
6929
6930         if (!intel_crtc) {
6931                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6932                 return;
6933         }
6934
6935         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6936                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6937                 return;
6938         }
6939
6940         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6941                         refresh_rate)
6942                 index = DRRS_LOW_RR;
6943
6944         if (index == dev_priv->drrs.refresh_rate_type) {
6945                 DRM_DEBUG_KMS(
6946                         "DRRS requested for previously set RR...ignoring\n");
6947                 return;
6948         }
6949
6950         if (!crtc_state->base.active) {
6951                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6952                 return;
6953         }
6954
6955         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6956                 switch (index) {
6957                 case DRRS_HIGH_RR:
6958                         intel_dp_set_m_n(crtc_state, M1_N1);
6959                         break;
6960                 case DRRS_LOW_RR:
6961                         intel_dp_set_m_n(crtc_state, M2_N2);
6962                         break;
6963                 case DRRS_MAX_RR:
6964                 default:
6965                         DRM_ERROR("Unsupported refreshrate type\n");
6966                 }
6967         } else if (INTEL_GEN(dev_priv) > 6) {
6968                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6969                 u32 val;
6970
6971                 val = I915_READ(reg);
6972                 if (index > DRRS_HIGH_RR) {
6973                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6974                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6975                         else
6976                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6977                 } else {
6978                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6979                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6980                         else
6981                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6982                 }
6983                 I915_WRITE(reg, val);
6984         }
6985
6986         dev_priv->drrs.refresh_rate_type = index;
6987
6988         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6989 }
6990
6991 /**
6992  * intel_edp_drrs_enable - init drrs struct if supported
6993  * @intel_dp: DP struct
6994  * @crtc_state: A pointer to the active crtc state.
6995  *
6996  * Initializes frontbuffer_bits and drrs.dp
6997  */
6998 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6999                            const struct intel_crtc_state *crtc_state)
7000 {
7001         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7002
7003         if (!crtc_state->has_drrs) {
7004                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
7005                 return;
7006         }
7007
7008         if (dev_priv->psr.enabled) {
7009                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
7010                 return;
7011         }
7012
7013         mutex_lock(&dev_priv->drrs.mutex);
7014         if (dev_priv->drrs.dp) {
7015                 DRM_DEBUG_KMS("DRRS already enabled\n");
7016                 goto unlock;
7017         }
7018
7019         dev_priv->drrs.busy_frontbuffer_bits = 0;
7020
7021         dev_priv->drrs.dp = intel_dp;
7022
7023 unlock:
7024         mutex_unlock(&dev_priv->drrs.mutex);
7025 }
7026
7027 /**
7028  * intel_edp_drrs_disable - Disable DRRS
7029  * @intel_dp: DP struct
7030  * @old_crtc_state: Pointer to old crtc_state.
7031  *
7032  */
7033 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7034                             const struct intel_crtc_state *old_crtc_state)
7035 {
7036         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7037
7038         if (!old_crtc_state->has_drrs)
7039                 return;
7040
7041         mutex_lock(&dev_priv->drrs.mutex);
7042         if (!dev_priv->drrs.dp) {
7043                 mutex_unlock(&dev_priv->drrs.mutex);
7044                 return;
7045         }
7046
7047         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7048                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7049                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7050
7051         dev_priv->drrs.dp = NULL;
7052         mutex_unlock(&dev_priv->drrs.mutex);
7053
7054         cancel_delayed_work_sync(&dev_priv->drrs.work);
7055 }
7056
7057 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7058 {
7059         struct drm_i915_private *dev_priv =
7060                 container_of(work, typeof(*dev_priv), drrs.work.work);
7061         struct intel_dp *intel_dp;
7062
7063         mutex_lock(&dev_priv->drrs.mutex);
7064
7065         intel_dp = dev_priv->drrs.dp;
7066
7067         if (!intel_dp)
7068                 goto unlock;
7069
7070         /*
7071          * The delayed work can race with an invalidate hence we need to
7072          * recheck.
7073          */
7074
7075         if (dev_priv->drrs.busy_frontbuffer_bits)
7076                 goto unlock;
7077
7078         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7079                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7080
7081                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7082                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7083         }
7084
7085 unlock:
7086         mutex_unlock(&dev_priv->drrs.mutex);
7087 }
7088
7089 /**
7090  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7091  * @dev_priv: i915 device
7092  * @frontbuffer_bits: frontbuffer plane tracking bits
7093  *
7094  * This function gets called everytime rendering on the given planes start.
7095  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7096  *
7097  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7098  */
7099 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7100                                unsigned int frontbuffer_bits)
7101 {
7102         struct drm_crtc *crtc;
7103         enum pipe pipe;
7104
7105         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7106                 return;
7107
7108         cancel_delayed_work(&dev_priv->drrs.work);
7109
7110         mutex_lock(&dev_priv->drrs.mutex);
7111         if (!dev_priv->drrs.dp) {
7112                 mutex_unlock(&dev_priv->drrs.mutex);
7113                 return;
7114         }
7115
7116         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7117         pipe = to_intel_crtc(crtc)->pipe;
7118
7119         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7120         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7121
7122         /* invalidate means busy screen hence upclock */
7123         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7124                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7125                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7126
7127         mutex_unlock(&dev_priv->drrs.mutex);
7128 }
7129
7130 /**
7131  * intel_edp_drrs_flush - Restart Idleness DRRS
7132  * @dev_priv: i915 device
7133  * @frontbuffer_bits: frontbuffer plane tracking bits
7134  *
7135  * This function gets called every time rendering on the given planes has
7136  * completed or flip on a crtc is completed. So DRRS should be upclocked
7137  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7138  * if no other planes are dirty.
7139  *
7140  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7141  */
7142 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7143                           unsigned int frontbuffer_bits)
7144 {
7145         struct drm_crtc *crtc;
7146         enum pipe pipe;
7147
7148         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7149                 return;
7150
7151         cancel_delayed_work(&dev_priv->drrs.work);
7152
7153         mutex_lock(&dev_priv->drrs.mutex);
7154         if (!dev_priv->drrs.dp) {
7155                 mutex_unlock(&dev_priv->drrs.mutex);
7156                 return;
7157         }
7158
7159         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7160         pipe = to_intel_crtc(crtc)->pipe;
7161
7162         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7163         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7164
7165         /* flush means busy screen hence upclock */
7166         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7167                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7168                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7169
7170         /*
7171          * flush also means no more activity hence schedule downclock, if all
7172          * other fbs are quiescent too
7173          */
7174         if (!dev_priv->drrs.busy_frontbuffer_bits)
7175                 schedule_delayed_work(&dev_priv->drrs.work,
7176                                 msecs_to_jiffies(1000));
7177         mutex_unlock(&dev_priv->drrs.mutex);
7178 }
7179
7180 /**
7181  * DOC: Display Refresh Rate Switching (DRRS)
7182  *
7183  * Display Refresh Rate Switching (DRRS) is a power conservation feature
7184  * which enables swtching between low and high refresh rates,
7185  * dynamically, based on the usage scenario. This feature is applicable
7186  * for internal panels.
7187  *
7188  * Indication that the panel supports DRRS is given by the panel EDID, which
7189  * would list multiple refresh rates for one resolution.
7190  *
7191  * DRRS is of 2 types - static and seamless.
7192  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7193  * (may appear as a blink on screen) and is used in dock-undock scenario.
7194  * Seamless DRRS involves changing RR without any visual effect to the user
7195  * and can be used during normal system usage. This is done by programming
7196  * certain registers.
7197  *
7198  * Support for static/seamless DRRS may be indicated in the VBT based on
7199  * inputs from the panel spec.
7200  *
7201  * DRRS saves power by switching to low RR based on usage scenarios.
7202  *
7203  * The implementation is based on frontbuffer tracking implementation.  When
7204  * there is a disturbance on the screen triggered by user activity or a periodic
7205  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
7206  * no movement on screen, after a timeout of 1 second, a switch to low RR is
7207  * made.
7208  *
7209  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7210  * and intel_edp_drrs_flush() are called.
7211  *
7212  * DRRS can be further extended to support other internal panels and also
7213  * the scenario of video playback wherein RR is set based on the rate
7214  * requested by userspace.
7215  */
7216
7217 /**
7218  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7219  * @connector: eDP connector
7220  * @fixed_mode: preferred mode of panel
7221  *
7222  * This function is  called only once at driver load to initialize basic
7223  * DRRS stuff.
7224  *
7225  * Returns:
7226  * Downclock mode if panel supports it, else return NULL.
7227  * DRRS support is determined by the presence of downclock mode (apart
7228  * from VBT setting).
7229  */
7230 static struct drm_display_mode *
7231 intel_dp_drrs_init(struct intel_connector *connector,
7232                    struct drm_display_mode *fixed_mode)
7233 {
7234         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7235         struct drm_display_mode *downclock_mode = NULL;
7236
7237         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7238         mutex_init(&dev_priv->drrs.mutex);
7239
7240         if (INTEL_GEN(dev_priv) <= 6) {
7241                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7242                 return NULL;
7243         }
7244
7245         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7246                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7247                 return NULL;
7248         }
7249
7250         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7251         if (!downclock_mode) {
7252                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7253                 return NULL;
7254         }
7255
7256         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7257
7258         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7259         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7260         return downclock_mode;
7261 }
7262
7263 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7264                                      struct intel_connector *intel_connector)
7265 {
7266         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7267         struct drm_device *dev = &dev_priv->drm;
7268         struct drm_connector *connector = &intel_connector->base;
7269         struct drm_display_mode *fixed_mode = NULL;
7270         struct drm_display_mode *downclock_mode = NULL;
7271         bool has_dpcd;
7272         enum pipe pipe = INVALID_PIPE;
7273         intel_wakeref_t wakeref;
7274         struct edid *edid;
7275
7276         if (!intel_dp_is_edp(intel_dp))
7277                 return true;
7278
7279         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7280
7281         /*
7282          * On IBX/CPT we may get here with LVDS already registered. Since the
7283          * driver uses the only internal power sequencer available for both
7284          * eDP and LVDS bail out early in this case to prevent interfering
7285          * with an already powered-on LVDS power sequencer.
7286          */
7287         if (intel_get_lvds_encoder(dev_priv)) {
7288                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7289                 DRM_INFO("LVDS was detected, not registering eDP\n");
7290
7291                 return false;
7292         }
7293
7294         with_pps_lock(intel_dp, wakeref) {
7295                 intel_dp_init_panel_power_timestamps(intel_dp);
7296                 intel_dp_pps_init(intel_dp);
7297                 intel_edp_panel_vdd_sanitize(intel_dp);
7298         }
7299
7300         /* Cache DPCD and EDID for edp. */
7301         has_dpcd = intel_edp_init_dpcd(intel_dp);
7302
7303         if (!has_dpcd) {
7304                 /* if this fails, presume the device is a ghost */
7305                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7306                 goto out_vdd_off;
7307         }
7308
7309         mutex_lock(&dev->mode_config.mutex);
7310         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7311         if (edid) {
7312                 if (drm_add_edid_modes(connector, edid)) {
7313                         drm_connector_update_edid_property(connector,
7314                                                                 edid);
7315                 } else {
7316                         kfree(edid);
7317                         edid = ERR_PTR(-EINVAL);
7318                 }
7319         } else {
7320                 edid = ERR_PTR(-ENOENT);
7321         }
7322         intel_connector->edid = edid;
7323
7324         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7325         if (fixed_mode)
7326                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7327
7328         /* fallback to VBT if available for eDP */
7329         if (!fixed_mode)
7330                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7331         mutex_unlock(&dev->mode_config.mutex);
7332
7333         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7334                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7335                 register_reboot_notifier(&intel_dp->edp_notifier);
7336
7337                 /*
7338                  * Figure out the current pipe for the initial backlight setup.
7339                  * If the current pipe isn't valid, try the PPS pipe, and if that
7340                  * fails just assume pipe A.
7341                  */
7342                 pipe = vlv_active_pipe(intel_dp);
7343
7344                 if (pipe != PIPE_A && pipe != PIPE_B)
7345                         pipe = intel_dp->pps_pipe;
7346
7347                 if (pipe != PIPE_A && pipe != PIPE_B)
7348                         pipe = PIPE_A;
7349
7350                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7351                               pipe_name(pipe));
7352         }
7353
7354         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7355         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7356         intel_panel_setup_backlight(connector, pipe);
7357
7358         if (fixed_mode)
7359                 drm_connector_init_panel_orientation_property(
7360                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7361
7362         return true;
7363
7364 out_vdd_off:
7365         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7366         /*
7367          * vdd might still be enabled do to the delayed vdd off.
7368          * Make sure vdd is actually turned off here.
7369          */
7370         with_pps_lock(intel_dp, wakeref)
7371                 edp_panel_vdd_off_sync(intel_dp);
7372
7373         return false;
7374 }
7375
7376 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7377 {
7378         struct intel_connector *intel_connector;
7379         struct drm_connector *connector;
7380
7381         intel_connector = container_of(work, typeof(*intel_connector),
7382                                        modeset_retry_work);
7383         connector = &intel_connector->base;
7384         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7385                       connector->name);
7386
7387         /* Grab the locks before changing connector property*/
7388         mutex_lock(&connector->dev->mode_config.mutex);
7389         /* Set connector link status to BAD and send a Uevent to notify
7390          * userspace to do a modeset.
7391          */
7392         drm_connector_set_link_status_property(connector,
7393                                                DRM_MODE_LINK_STATUS_BAD);
7394         mutex_unlock(&connector->dev->mode_config.mutex);
7395         /* Send Hotplug uevent so userspace can reprobe */
7396         drm_kms_helper_hotplug_event(connector->dev);
7397 }
7398
7399 bool
7400 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7401                         struct intel_connector *intel_connector)
7402 {
7403         struct drm_connector *connector = &intel_connector->base;
7404         struct intel_dp *intel_dp = &intel_dig_port->dp;
7405         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7406         struct drm_device *dev = intel_encoder->base.dev;
7407         struct drm_i915_private *dev_priv = to_i915(dev);
7408         enum port port = intel_encoder->port;
7409         enum phy phy = intel_port_to_phy(dev_priv, port);
7410         int type;
7411
7412         /* Initialize the work for modeset in case of link train failure */
7413         INIT_WORK(&intel_connector->modeset_retry_work,
7414                   intel_dp_modeset_retry_work_fn);
7415
7416         if (WARN(intel_dig_port->max_lanes < 1,
7417                  "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7418                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
7419                  intel_encoder->base.name))
7420                 return false;
7421
7422         intel_dp_set_source_rates(intel_dp);
7423
7424         intel_dp->reset_link_params = true;
7425         intel_dp->pps_pipe = INVALID_PIPE;
7426         intel_dp->active_pipe = INVALID_PIPE;
7427
7428         /* Preserve the current hw state. */
7429         intel_dp->DP = I915_READ(intel_dp->output_reg);
7430         intel_dp->attached_connector = intel_connector;
7431
7432         if (intel_dp_is_port_edp(dev_priv, port)) {
7433                 /*
7434                  * Currently we don't support eDP on TypeC ports, although in
7435                  * theory it could work on TypeC legacy ports.
7436                  */
7437                 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7438                 type = DRM_MODE_CONNECTOR_eDP;
7439         } else {
7440                 type = DRM_MODE_CONNECTOR_DisplayPort;
7441         }
7442
7443         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7444                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7445
7446         /*
7447          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7448          * for DP the encoder type can be set by the caller to
7449          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7450          */
7451         if (type == DRM_MODE_CONNECTOR_eDP)
7452                 intel_encoder->type = INTEL_OUTPUT_EDP;
7453
7454         /* eDP only on port B and/or C on vlv/chv */
7455         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7456                     intel_dp_is_edp(intel_dp) &&
7457                     port != PORT_B && port != PORT_C))
7458                 return false;
7459
7460         DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n",
7461                       type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7462                       intel_encoder->base.base.id, intel_encoder->base.name);
7463
7464         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7465         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7466
7467         if (!HAS_GMCH(dev_priv))
7468                 connector->interlace_allowed = true;
7469         connector->doublescan_allowed = 0;
7470
7471         if (INTEL_GEN(dev_priv) >= 11)
7472                 connector->ycbcr_420_allowed = true;
7473
7474         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7475
7476         intel_dp_aux_init(intel_dp);
7477
7478         intel_connector_attach_encoder(intel_connector, intel_encoder);
7479
7480         if (HAS_DDI(dev_priv))
7481                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7482         else
7483                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7484
7485         /* init MST on ports that can support it */
7486         intel_dp_mst_encoder_init(intel_dig_port,
7487                                   intel_connector->base.base.id);
7488
7489         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7490                 intel_dp_aux_fini(intel_dp);
7491                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7492                 goto fail;
7493         }
7494
7495         intel_dp_add_properties(intel_dp, connector);
7496
7497         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7498                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7499                 if (ret)
7500                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7501         }
7502
7503         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7504          * 0xd.  Failure to do so will result in spurious interrupts being
7505          * generated on the port when a cable is not attached.
7506          */
7507         if (IS_G45(dev_priv)) {
7508                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7509                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7510         }
7511
7512         return true;
7513
7514 fail:
7515         drm_connector_cleanup(connector);
7516
7517         return false;
7518 }
7519
7520 bool intel_dp_init(struct drm_i915_private *dev_priv,
7521                    i915_reg_t output_reg,
7522                    enum port port)
7523 {
7524         struct intel_digital_port *intel_dig_port;
7525         struct intel_encoder *intel_encoder;
7526         struct drm_encoder *encoder;
7527         struct intel_connector *intel_connector;
7528
7529         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7530         if (!intel_dig_port)
7531                 return false;
7532
7533         intel_connector = intel_connector_alloc();
7534         if (!intel_connector)
7535                 goto err_connector_alloc;
7536
7537         intel_encoder = &intel_dig_port->base;
7538         encoder = &intel_encoder->base;
7539
7540         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7541                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7542                              "DP %c", port_name(port)))
7543                 goto err_encoder_init;
7544
7545         intel_encoder->hotplug = intel_dp_hotplug;
7546         intel_encoder->compute_config = intel_dp_compute_config;
7547         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7548         intel_encoder->get_config = intel_dp_get_config;
7549         intel_encoder->update_pipe = intel_panel_update_backlight;
7550         intel_encoder->suspend = intel_dp_encoder_suspend;
7551         if (IS_CHERRYVIEW(dev_priv)) {
7552                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7553                 intel_encoder->pre_enable = chv_pre_enable_dp;
7554                 intel_encoder->enable = vlv_enable_dp;
7555                 intel_encoder->disable = vlv_disable_dp;
7556                 intel_encoder->post_disable = chv_post_disable_dp;
7557                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7558         } else if (IS_VALLEYVIEW(dev_priv)) {
7559                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7560                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7561                 intel_encoder->enable = vlv_enable_dp;
7562                 intel_encoder->disable = vlv_disable_dp;
7563                 intel_encoder->post_disable = vlv_post_disable_dp;
7564         } else {
7565                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7566                 intel_encoder->enable = g4x_enable_dp;
7567                 intel_encoder->disable = g4x_disable_dp;
7568                 intel_encoder->post_disable = g4x_post_disable_dp;
7569         }
7570
7571         intel_dig_port->dp.output_reg = output_reg;
7572         intel_dig_port->max_lanes = 4;
7573
7574         intel_encoder->type = INTEL_OUTPUT_DP;
7575         intel_encoder->power_domain = intel_port_to_power_domain(port);
7576         if (IS_CHERRYVIEW(dev_priv)) {
7577                 if (port == PORT_D)
7578                         intel_encoder->pipe_mask = BIT(PIPE_C);
7579                 else
7580                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
7581         } else {
7582                 intel_encoder->pipe_mask = ~0;
7583         }
7584         intel_encoder->cloneable = 0;
7585         intel_encoder->port = port;
7586
7587         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7588
7589         if (port != PORT_A)
7590                 intel_infoframe_init(intel_dig_port);
7591
7592         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7593         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7594                 goto err_init_connector;
7595
7596         return true;
7597
7598 err_init_connector:
7599         drm_encoder_cleanup(encoder);
7600 err_encoder_init:
7601         kfree(intel_connector);
7602 err_connector_alloc:
7603         kfree(intel_dig_port);
7604         return false;
7605 }
7606
7607 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7608 {
7609         struct intel_encoder *encoder;
7610
7611         for_each_intel_encoder(&dev_priv->drm, encoder) {
7612                 struct intel_dp *intel_dp;
7613
7614                 if (encoder->type != INTEL_OUTPUT_DDI)
7615                         continue;
7616
7617                 intel_dp = enc_to_intel_dp(&encoder->base);
7618
7619                 if (!intel_dp->can_mst)
7620                         continue;
7621
7622                 if (intel_dp->is_mst)
7623                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7624         }
7625 }
7626
7627 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7628 {
7629         struct intel_encoder *encoder;
7630
7631         for_each_intel_encoder(&dev_priv->drm, encoder) {
7632                 struct intel_dp *intel_dp;
7633                 int ret;
7634
7635                 if (encoder->type != INTEL_OUTPUT_DDI)
7636                         continue;
7637
7638                 intel_dp = enc_to_intel_dp(&encoder->base);
7639
7640                 if (!intel_dp->can_mst)
7641                         continue;
7642
7643                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
7644                                                      true);
7645                 if (ret) {
7646                         intel_dp->is_mst = false;
7647                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7648                                                         false);
7649                 }
7650         }
7651 }