drivers/gpu/drm/i915/display/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <madhav.chauhan@intel.com>
  25  *   Jani Nikula <jani.nikula@intel.com>
  26  */
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_mipi_dsi.h>
  30
  31 #include "intel_atomic.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_dsi.h"
  36 #include "intel_panel.h"
  37 #include "intel_vdsc.h"
  38
  39 static int header_credits_available(struct drm_i915_private *dev_priv,
  40                                     enum transcoder dsi_trans)
  41 {
  42         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  43                 >> FREE_HEADER_CREDIT_SHIFT;
  44 }
  45
  46 static int payload_credits_available(struct drm_i915_private *dev_priv,
  47                                      enum transcoder dsi_trans)
  48 {
  49         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  50                 >> FREE_PLOAD_CREDIT_SHIFT;
  51 }
  52
  53 static void wait_for_header_credits(struct drm_i915_private *dev_priv,
  54                                     enum transcoder dsi_trans)
  55 {
  56         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  57                         MAX_HEADER_CREDIT, 100))
  58                 drm_err(&dev_priv->drm, "DSI header credits not released\n");
  59 }
  60
  61 static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
  62                                      enum transcoder dsi_trans)
  63 {
  64         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  65                         MAX_PLOAD_CREDIT, 100))
  66                 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
  67 }
  68
  69 static enum transcoder dsi_port_to_transcoder(enum port port)
  70 {
  71         if (port == PORT_A)
  72                 return TRANSCODER_DSI_0;
  73         else
  74                 return TRANSCODER_DSI_1;
  75 }
  76
  77 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
  78 {
  79         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  80         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
  81         struct mipi_dsi_device *dsi;
  82         enum port port;
  83         enum transcoder dsi_trans;
  84         int ret;
  85
  86         /* wait for header/payload credits to be released */
  87         for_each_dsi_port(port, intel_dsi->ports) {
  88                 dsi_trans = dsi_port_to_transcoder(port);
  89                 wait_for_header_credits(dev_priv, dsi_trans);
  90                 wait_for_payload_credits(dev_priv, dsi_trans);
  91         }
  92
  93         /* send nop DCS command */
  94         for_each_dsi_port(port, intel_dsi->ports) {
  95                 dsi = intel_dsi->dsi_hosts[port]->device;
  96                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
  97                 dsi->channel = 0;
  98                 ret = mipi_dsi_dcs_nop(dsi);
  99                 if (ret < 0)
 100                         drm_err(&dev_priv->drm,
 101                                 "error sending DCS NOP command\n");
 102         }
 103
 104         /* wait for header credits to be released */
 105         for_each_dsi_port(port, intel_dsi->ports) {
 106                 dsi_trans = dsi_port_to_transcoder(port);
 107                 wait_for_header_credits(dev_priv, dsi_trans);
 108         }
 109
 110         /* wait for LP TX in progress bit to be cleared */
 111         for_each_dsi_port(port, intel_dsi->ports) {
 112                 dsi_trans = dsi_port_to_transcoder(port);
 113                 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
 114                                   LPTX_IN_PROGRESS), 20))
 115                         drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
 116         }
 117 }
 118
 119 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
 120                                u32 len)
 121 {
 122         struct intel_dsi *intel_dsi = host->intel_dsi;
 123         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 124         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 125         int free_credits;
 126         int i, j;
 127
 128         for (i = 0; i < len; i += 4) {
 129                 u32 tmp = 0;
 130
 131                 free_credits = payload_credits_available(dev_priv, dsi_trans);
 132                 if (free_credits < 1) {
 133                         drm_err(&dev_priv->drm,
 134                                 "Payload credit not available\n");
 135                         return false;
 136                 }
 137
 138                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 139                         tmp |= *data++ << 8 * j;
 140
 141                 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp);
 142         }
 143
 144         return true;
 145 }
 146
 147 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 148                             struct mipi_dsi_packet pkt, bool enable_lpdt)
 149 {
 150         struct intel_dsi *intel_dsi = host->intel_dsi;
 151         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 152         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 153         u32 tmp;
 154         int free_credits;
 155
 156         /* check if header credit available */
 157         free_credits = header_credits_available(dev_priv, dsi_trans);
 158         if (free_credits < 1) {
 159                 drm_err(&dev_priv->drm,
 160                         "send pkt header failed, not enough hdr credits\n");
 161                 return -1;
 162         }
 163
 164         tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
 165
 166         if (pkt.payload)
 167                 tmp |= PAYLOAD_PRESENT;
 168         else
 169                 tmp &= ~PAYLOAD_PRESENT;
 170
 171         tmp &= ~VBLANK_FENCE;
 172
 173         if (enable_lpdt)
 174                 tmp |= LP_DATA_TRANSFER;
 175
 176         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 177         tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
 178         tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
 179         tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
 180         tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
 181         intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
 182
 183         return 0;
 184 }
 185
 186 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 187                               struct mipi_dsi_packet pkt)
 188 {
 189         struct intel_dsi *intel_dsi = host->intel_dsi;
 190         struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 191
 192         /* payload queue can accept *256 bytes*, check limit */
 193         if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
 194                 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
 195                 return -1;
 196         }
 197
 198         /* load data into command payload queue */
 199         if (!add_payld_to_queue(host, pkt.payload,
 200                                 pkt.payload_length)) {
 201                 drm_err(&i915->drm, "adding payload to queue failed\n");
 202                 return -1;
 203         }
 204
 205         return 0;
 206 }
 207
 208 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
 209 {
 210         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 211         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 212         u32 tmp, mode_flags;
 213         enum port port;
 214
 215         mode_flags = crtc_state->mode_flags;
 216
 217         /*
 218          * case 1 also covers dual link
 219          * In case of dual link, frame update should be set on
 220          * DSI_0
 221          */
 222         if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
 223                 port = PORT_A;
 224         else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
 225                 port = PORT_B;
 226         else
 227                 return;
 228
 229         tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
 230         tmp |= DSI_FRAME_UPDATE_REQUEST;
 231         intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
 232 }
 233
 234 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 235 {
 236         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 237         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 238         enum phy phy;
 239         u32 tmp;
 240         int lane;
 241
 242         for_each_dsi_phy(phy, intel_dsi->phys) {
 243                 /*
 244                  * Program voltage swing and pre-emphasis level values as per
 245                  * table in BSPEC under DDI buffer programing
 246                  */
 247                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
 248                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 249                 tmp |= SCALING_MODE_SEL(0x2);
 250                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 251                 tmp |= RTERM_SELECT(0x6);
 252                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 253
 254                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
 255                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 256                 tmp |= SCALING_MODE_SEL(0x2);
 257                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 258                 tmp |= RTERM_SELECT(0x6);
 259                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 260
 261                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
 262                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 263                          RCOMP_SCALAR_MASK);
 264                 tmp |= SWING_SEL_UPPER(0x2);
 265                 tmp |= SWING_SEL_LOWER(0x2);
 266                 tmp |= RCOMP_SCALAR(0x98);
 267                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 268
 269                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
 270                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 271                          RCOMP_SCALAR_MASK);
 272                 tmp |= SWING_SEL_UPPER(0x2);
 273                 tmp |= SWING_SEL_LOWER(0x2);
 274                 tmp |= RCOMP_SCALAR(0x98);
 275                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
 276
 277                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
 278                 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 279                          CURSOR_COEFF_MASK);
 280                 tmp |= POST_CURSOR_1(0x0);
 281                 tmp |= POST_CURSOR_2(0x0);
 282                 tmp |= CURSOR_COEFF(0x3f);
 283                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
 284
 285                 for (lane = 0; lane <= 3; lane++) {
 286                         /* Bspec: must not use GRP register for write */
 287                         tmp = intel_de_read(dev_priv,
 288                                             ICL_PORT_TX_DW4_LN(lane, phy));
 289                         tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 290                                  CURSOR_COEFF_MASK);
 291                         tmp |= POST_CURSOR_1(0x0);
 292                         tmp |= POST_CURSOR_2(0x0);
 293                         tmp |= CURSOR_COEFF(0x3f);
 294                         intel_de_write(dev_priv,
 295                                        ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 296                 }
 297         }
 298 }
 299
 300 static void configure_dual_link_mode(struct intel_encoder *encoder,
 301                                      const struct intel_crtc_state *pipe_config)
 302 {
 303         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 304         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 305         u32 dss_ctl1;
 306
 307         dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
 308         dss_ctl1 |= SPLITTER_ENABLE;
 309         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 310         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 311
 312         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 313                 const struct drm_display_mode *adjusted_mode =
 314                                         &pipe_config->hw.adjusted_mode;
 315                 u32 dss_ctl2;
 316                 u16 hactive = adjusted_mode->crtc_hdisplay;
 317                 u16 dl_buffer_depth;
 318
 319                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 320                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 321
 322                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 323                         drm_err(&dev_priv->drm,
 324                                 "DL buffer depth exceed max value\n");
 325
 326                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 327                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 328                 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
 329                 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
 330                 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 331                 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2);
 332         } else {
 333                 /* Interleave */
 334                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 335         }
 336
 337         intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
 338 }
 339
 340 /* aka DSI 8X clock */
 341 static int afe_clk(struct intel_encoder *encoder,
 342                    const struct intel_crtc_state *crtc_state)
 343 {
 344         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 345         int bpp;
 346
 347         if (crtc_state->dsc.compression_enable)
 348                 bpp = crtc_state->dsc.compressed_bpp;
 349         else
 350                 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 351
 352         return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 353 }
 354
 355 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 356                                           const struct intel_crtc_state *crtc_state)
 357 {
 358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 359         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 360         enum port port;
 361         int afe_clk_khz;
 362         u32 esc_clk_div_m;
 363
 364         afe_clk_khz = afe_clk(encoder, crtc_state);
 365         esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 366
 367         for_each_dsi_port(port, intel_dsi->ports) {
 368                 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
 369                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 370                 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
 371         }
 372
 373         for_each_dsi_port(port, intel_dsi->ports) {
 374                 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
 375                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 376                 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
 377         }
 378 }
 379
 380 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
 381                                      struct intel_dsi *intel_dsi)
 382 {
 383         enum port port;
 384
 385         for_each_dsi_port(port, intel_dsi->ports) {
 386                 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
 387                 intel_dsi->io_wakeref[port] =
 388                         intel_display_power_get(dev_priv,
 389                                                 port == PORT_A ?
 390                                                 POWER_DOMAIN_PORT_DDI_A_IO :
 391                                                 POWER_DOMAIN_PORT_DDI_B_IO);
 392         }
 393 }
 394
 395 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 396 {
 397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 398         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 399         enum port port;
 400         u32 tmp;
 401
 402         for_each_dsi_port(port, intel_dsi->ports) {
 403                 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
 404                 tmp |= COMBO_PHY_MODE_DSI;
 405                 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
 406         }
 407
 408         get_dsi_io_power_domains(dev_priv, intel_dsi);
 409 }
 410
 411 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 412 {
 413         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 414         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 415         enum phy phy;
 416
 417         for_each_dsi_phy(phy, intel_dsi->phys)
 418                 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 419                                                intel_dsi->lane_count, false);
 420 }
 421
 422 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 423 {
 424         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 425         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 426         enum phy phy;
 427         u32 tmp;
 428         int lane;
 429
 430         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 431         for_each_dsi_phy(phy, intel_dsi->phys) {
 432                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
 433                 tmp &= ~LOADGEN_SELECT;
 434                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
 435                 for (lane = 0; lane <= 3; lane++) {
 436                         tmp = intel_de_read(dev_priv,
 437                                             ICL_PORT_TX_DW4_LN(lane, phy));
 438                         tmp &= ~LOADGEN_SELECT;
 439                         if (lane != 2)
 440                                 tmp |= LOADGEN_SELECT;
 441                         intel_de_write(dev_priv,
 442                                        ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 443                 }
 444         }
 445
 446         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 447         for_each_dsi_phy(phy, intel_dsi->phys) {
 448                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
 449                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 450                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 451                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
 452                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
 453                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 454                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 455                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 456
 457                 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
 458                 if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
 459                         tmp = intel_de_read(dev_priv,
 460                                             ICL_PORT_PCS_DW1_AUX(phy));
 461                         tmp &= ~LATENCY_OPTIM_MASK;
 462                         tmp |= LATENCY_OPTIM_VAL(0);
 463                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 464                                        tmp);
 465
 466                         tmp = intel_de_read(dev_priv,
 467                                             ICL_PORT_PCS_DW1_LN0(phy));
 468                         tmp &= ~LATENCY_OPTIM_MASK;
 469                         tmp |= LATENCY_OPTIM_VAL(0x1);
 470                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
 471                                        tmp);
 472                 }
 473         }
 474
 475 }
 476
 477 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 478 {
 479         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 480         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 481         u32 tmp;
 482         enum phy phy;
 483
 484         /* clear common keeper enable bit */
 485         for_each_dsi_phy(phy, intel_dsi->phys) {
 486                 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
 487                 tmp &= ~COMMON_KEEPER_EN;
 488                 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
 489                 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
 490                 tmp &= ~COMMON_KEEPER_EN;
 491                 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp);
 492         }
 493
 494         /*
 495          * Set SUS Clock Config bitfield to 11b
 496          * Note: loadgen select program is done
 497          * as part of lane phy sequence configuration
 498          */
 499         for_each_dsi_phy(phy, intel_dsi->phys) {
 500                 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
 501                 tmp |= SUS_CLOCK_CONFIG;
 502                 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp);
 503         }
 504
 505         /* Clear training enable to change swing values */
 506         for_each_dsi_phy(phy, intel_dsi->phys) {
 507                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
 508                 tmp &= ~TX_TRAINING_EN;
 509                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 510                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
 511                 tmp &= ~TX_TRAINING_EN;
 512                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 513         }
 514
 515         /* Program swing and de-emphasis */
 516         dsi_program_swing_and_deemphasis(encoder);
 517
 518         /* Set training enable to trigger update */
 519         for_each_dsi_phy(phy, intel_dsi->phys) {
 520                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
 521                 tmp |= TX_TRAINING_EN;
 522                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 523                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
 524                 tmp |= TX_TRAINING_EN;
 525                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 526         }
 527 }
 528
 529 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 530 {
 531         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 532         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 533         u32 tmp;
 534         enum port port;
 535
 536         for_each_dsi_port(port, intel_dsi->ports) {
 537                 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 538                 tmp |= DDI_BUF_CTL_ENABLE;
 539                 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
 540
 541                 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 542                                   DDI_BUF_IS_IDLE),
 543                                   500))
 544                         drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
 545                                 port_name(port));
 546         }
 547 }
 548
 549 static void
 550 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 551                              const struct intel_crtc_state *crtc_state)
 552 {
 553         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 554         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 555         u32 tmp;
 556         enum port port;
 557         enum phy phy;
 558
 559         /* Program T-INIT master registers */
 560         for_each_dsi_port(port, intel_dsi->ports) {
 561                 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port));
 562                 tmp &= ~MASTER_INIT_TIMER_MASK;
 563                 tmp |= intel_dsi->init_count;
 564                 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp);
 565         }
 566
 567         /* Program DPHY clock lanes timings */
 568         for_each_dsi_port(port, intel_dsi->ports) {
 569                 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
 570                                intel_dsi->dphy_reg);
 571
 572                 /* shadow register inside display core */
 573                 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
 574                                intel_dsi->dphy_reg);
 575         }
 576
 577         /* Program DPHY data lanes timings */
 578         for_each_dsi_port(port, intel_dsi->ports) {
 579                 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
 580                                intel_dsi->dphy_data_lane_reg);
 581
 582                 /* shadow register inside display core */
 583                 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
 584                                intel_dsi->dphy_data_lane_reg);
 585         }
 586
 587         /*
 588          * If DSI link operating at or below an 800 MHz,
 589          * TA_SURE should be override and programmed to
 590          * a value '0' inside TA_PARAM_REGISTERS otherwise
 591          * leave all fields at HW default values.
 592          */
 593         if (IS_GEN(dev_priv, 11)) {
 594                 if (afe_clk(encoder, crtc_state) <= 800000) {
 595                         for_each_dsi_port(port, intel_dsi->ports) {
 596                                 tmp = intel_de_read(dev_priv,
 597                                                     DPHY_TA_TIMING_PARAM(port));
 598                                 tmp &= ~TA_SURE_MASK;
 599                                 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 600                                 intel_de_write(dev_priv,
 601                                                DPHY_TA_TIMING_PARAM(port),
 602                                                tmp);
 603
 604                                 /* shadow register inside display core */
 605                                 tmp = intel_de_read(dev_priv,
 606                                                     DSI_TA_TIMING_PARAM(port));
 607                                 tmp &= ~TA_SURE_MASK;
 608                                 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 609                                 intel_de_write(dev_priv,
 610                                                DSI_TA_TIMING_PARAM(port), tmp);
 611                         }
 612                 }
 613         }
 614
 615         if (IS_JSL_EHL(dev_priv)) {
 616                 for_each_dsi_phy(phy, intel_dsi->phys) {
 617                         tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
 618                         tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
 619                         intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp);
 620                 }
 621         }
 622 }
 623
 624 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 625 {
 626         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 627         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 628         u32 tmp;
 629         enum phy phy;
 630
 631         mutex_lock(&dev_priv->dpll.lock);
 632         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 633         for_each_dsi_phy(phy, intel_dsi->phys)
 634                 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 635
 636         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 637         mutex_unlock(&dev_priv->dpll.lock);
 638 }
 639
 640 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 641 {
 642         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 643         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 644         u32 tmp;
 645         enum phy phy;
 646
 647         mutex_lock(&dev_priv->dpll.lock);
 648         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 649         for_each_dsi_phy(phy, intel_dsi->phys)
 650                 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 651
 652         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 653         mutex_unlock(&dev_priv->dpll.lock);
 654 }
 655
 656 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 657                               const struct intel_crtc_state *crtc_state)
 658 {
 659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 660         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 661         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 662         enum phy phy;
 663         u32 val;
 664
 665         mutex_lock(&dev_priv->dpll.lock);
 666
 667         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 668         for_each_dsi_phy(phy, intel_dsi->phys) {
 669                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 670                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 671         }
 672         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 673
 674         for_each_dsi_phy(phy, intel_dsi->phys) {
 675                 if (INTEL_GEN(dev_priv) >= 12)
 676                         val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 677                 else
 678                         val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 679         }
 680         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 681
 682         intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
 683
 684         mutex_unlock(&dev_priv->dpll.lock);
 685 }
 686
 687 static void
 688 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 689                                const struct intel_crtc_state *pipe_config)
 690 {
 691         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 692         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 693         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 694         enum pipe pipe = intel_crtc->pipe;
 695         u32 tmp;
 696         enum port port;
 697         enum transcoder dsi_trans;
 698
 699         for_each_dsi_port(port, intel_dsi->ports) {
 700                 dsi_trans = dsi_port_to_transcoder(port);
 701                 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
 702
 703                 if (intel_dsi->eotp_pkt)
 704                         tmp &= ~EOTP_DISABLED;
 705                 else
 706                         tmp |= EOTP_DISABLED;
 707
 708                 /* enable link calibration if freq > 1.5Gbps */
 709                 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 710                         tmp &= ~LINK_CALIBRATION_MASK;
 711                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 712                 }
 713
 714                 /* configure continuous clock */
 715                 tmp &= ~CONTINUOUS_CLK_MASK;
 716                 if (intel_dsi->clock_stop)
 717                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 718                 else
 719                         tmp |= CLK_HS_CONTINUOUS;
 720
 721                 /* configure buffer threshold limit to minimum */
 722                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 723                 tmp |= PIX_BUF_THRESHOLD_1_4;
 724
 725                 /* set virtual channel to '0' */
 726                 tmp &= ~PIX_VIRT_CHAN_MASK;
 727                 tmp |= PIX_VIRT_CHAN(0);
 728
 729                 /* program BGR transmission */
 730                 if (intel_dsi->bgr_enabled)
 731                         tmp |= BGR_TRANSMISSION;
 732
 733                 /* select pixel format */
 734                 tmp &= ~PIX_FMT_MASK;
 735                 if (pipe_config->dsc.compression_enable) {
 736                         tmp |= PIX_FMT_COMPRESSED;
 737                 } else {
 738                         switch (intel_dsi->pixel_format) {
 739                         default:
 740                                 MISSING_CASE(intel_dsi->pixel_format);
 741                                 fallthrough;
 742                         case MIPI_DSI_FMT_RGB565:
 743                                 tmp |= PIX_FMT_RGB565;
 744                                 break;
 745                         case MIPI_DSI_FMT_RGB666_PACKED:
 746                                 tmp |= PIX_FMT_RGB666_PACKED;
 747                                 break;
 748                         case MIPI_DSI_FMT_RGB666:
 749                                 tmp |= PIX_FMT_RGB666_LOOSE;
 750                                 break;
 751                         case MIPI_DSI_FMT_RGB888:
 752                                 tmp |= PIX_FMT_RGB888;
 753                                 break;
 754                         }
 755                 }
 756
 757                 if (INTEL_GEN(dev_priv) >= 12) {
 758                         if (is_vid_mode(intel_dsi))
 759                                 tmp |= BLANKING_PACKET_ENABLE;
 760                 }
 761
 762                 /* program DSI operation mode */
 763                 if (is_vid_mode(intel_dsi)) {
 764                         tmp &= ~OP_MODE_MASK;
 765                         switch (intel_dsi->video_mode_format) {
 766                         default:
 767                                 MISSING_CASE(intel_dsi->video_mode_format);
 768                                 fallthrough;
 769                         case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
 770                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 771                                 break;
 772                         case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
 773                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 774                                 break;
 775                         }
 776                 } else {
 777                         /*
 778                          * FIXME: Retrieve this info from VBT.
 779                          * As per the spec when dsi transcoder is operating
 780                          * in TE GATE mode, TE comes from GPIO
 781                          * which is UTIL PIN for DSI 0.
 782                          * Also this GPIO would not be used for other
 783                          * purposes is an assumption.
 784                          */
 785                         tmp &= ~OP_MODE_MASK;
 786                         tmp |= CMD_MODE_TE_GATE;
 787                         tmp |= TE_SOURCE_GPIO;
 788                 }
 789
 790                 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 791         }
 792
 793         /* enable port sync mode if dual link */
 794         if (intel_dsi->dual_link) {
 795                 for_each_dsi_port(port, intel_dsi->ports) {
 796                         dsi_trans = dsi_port_to_transcoder(port);
 797                         tmp = intel_de_read(dev_priv,
 798                                             TRANS_DDI_FUNC_CTL2(dsi_trans));
 799                         tmp |= PORT_SYNC_MODE_ENABLE;
 800                         intel_de_write(dev_priv,
 801                                        TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 802                 }
 803
 804                 /* configure stream splitting */
 805                 configure_dual_link_mode(encoder, pipe_config);
 806         }
 807
 808         for_each_dsi_port(port, intel_dsi->ports) {
 809                 dsi_trans = dsi_port_to_transcoder(port);
 810
 811                 /* select data lane width */
 812                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
 813                 tmp &= ~DDI_PORT_WIDTH_MASK;
 814                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 815
 816                 /* select input pipe */
 817                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 818                 switch (pipe) {
 819                 default:
 820                         MISSING_CASE(pipe);
 821                         fallthrough;
 822                 case PIPE_A:
 823                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 824                         break;
 825                 case PIPE_B:
 826                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 827                         break;
 828                 case PIPE_C:
 829                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 830                         break;
 831                 case PIPE_D:
 832                         tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
 833                         break;
 834                 }
 835
 836                 /* enable DDI buffer */
 837                 tmp |= TRANS_DDI_FUNC_ENABLE;
 838                 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
 839         }
 840
 841         /* wait for link ready */
 842         for_each_dsi_port(port, intel_dsi->ports) {
 843                 dsi_trans = dsi_port_to_transcoder(port);
 844                 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
 845                                  LINK_READY), 2500))
 846                         drm_err(&dev_priv->drm, "DSI link not ready\n");
 847         }
 848 }
 849
 850 static void
 851 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 852                                  const struct intel_crtc_state *crtc_state)
 853 {
 854         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 855         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 856         const struct drm_display_mode *adjusted_mode =
 857                 &crtc_state->hw.adjusted_mode;
 858         enum port port;
 859         enum transcoder dsi_trans;
 860         /* horizontal timings */
 861         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 862         u16 hback_porch;
 863         /* vertical timings */
 864         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 865         int mul = 1, div = 1;
 866
 867         /*
 868          * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
 869          * for slower link speed if DSC is enabled.
 870          *
 871          * The compression frequency ratio is the ratio between compressed and
 872          * non-compressed link speeds, and simplifies down to the ratio between
 873          * compressed and non-compressed bpp.
 874          */
 875         if (crtc_state->dsc.compression_enable) {
 876                 mul = crtc_state->dsc.compressed_bpp;
 877                 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 878         }
 879
 880         hactive = adjusted_mode->crtc_hdisplay;
 881
 882         if (is_vid_mode(intel_dsi))
 883                 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
 884         else
 885                 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
 886
 887         hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
 888         hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
 889         hsync_size  = hsync_end - hsync_start;
 890         hback_porch = (adjusted_mode->crtc_htotal -
 891                        adjusted_mode->crtc_hsync_end);
 892         vactive = adjusted_mode->crtc_vdisplay;
 893
 894         if (is_vid_mode(intel_dsi)) {
 895                 vtotal = adjusted_mode->crtc_vtotal;
 896         } else {
 897                 int bpp, line_time_us, byte_clk_period_ns;
 898
 899                 if (crtc_state->dsc.compression_enable)
 900                         bpp = crtc_state->dsc.compressed_bpp;
 901                 else
 902                         bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 903
 904                 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
 905                 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
 906                 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
 907         }
 908         vsync_start = adjusted_mode->crtc_vsync_start;
 909         vsync_end = adjusted_mode->crtc_vsync_end;
 910         vsync_shift = hsync_start - htotal / 2;
 911
 912         if (intel_dsi->dual_link) {
 913                 hactive /= 2;
 914                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 915                         hactive += intel_dsi->pixel_overlap;
 916                 htotal /= 2;
 917         }
 918
 919         /* minimum hactive as per bspec: 256 pixels */
 920         if (adjusted_mode->crtc_hdisplay < 256)
 921                 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
 922
 923         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 924         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 925                 drm_err(&dev_priv->drm,
 926                         "hactive pixels are not multiple of 4\n");
 927
 928         /* program TRANS_HTOTAL register */
 929         for_each_dsi_port(port, intel_dsi->ports) {
 930                 dsi_trans = dsi_port_to_transcoder(port);
 931                 intel_de_write(dev_priv, HTOTAL(dsi_trans),
 932                                (hactive - 1) | ((htotal - 1) << 16));
 933         }
 934
 935         /* TRANS_HSYNC register to be programmed only for video mode */
 936         if (is_vid_mode(intel_dsi)) {
 937                 if (intel_dsi->video_mode_format ==
 938                     VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 939                         /* BSPEC: hsync size should be atleast 16 pixels */
 940                         if (hsync_size < 16)
 941                                 drm_err(&dev_priv->drm,
 942                                         "hsync size < 16 pixels\n");
 943                 }
 944
 945                 if (hback_porch < 16)
 946                         drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
 947
 948                 if (intel_dsi->dual_link) {
 949                         hsync_start /= 2;
 950                         hsync_end /= 2;
 951                 }
 952
 953                 for_each_dsi_port(port, intel_dsi->ports) {
 954                         dsi_trans = dsi_port_to_transcoder(port);
 955                         intel_de_write(dev_priv, HSYNC(dsi_trans),
 956                                        (hsync_start - 1) | ((hsync_end - 1) << 16));
 957                 }
 958         }
 959
 960         /* program TRANS_VTOTAL register */
 961         for_each_dsi_port(port, intel_dsi->ports) {
 962                 dsi_trans = dsi_port_to_transcoder(port);
 963                 /*
 964                  * FIXME: Programing this by assuming progressive mode, since
 965                  * non-interlaced info from VBT is not saved inside
 966                  * struct drm_display_mode.
 967                  * For interlace mode: program required pixel minus 2
 968                  */
 969                 intel_de_write(dev_priv, VTOTAL(dsi_trans),
 970                                (vactive - 1) | ((vtotal - 1) << 16));
 971         }
 972
 973         if (vsync_end < vsync_start || vsync_end > vtotal)
 974                 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
 975
 976         if (vsync_start < vactive)
 977                 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
 978
 979         /* program TRANS_VSYNC register for video mode only */
 980         if (is_vid_mode(intel_dsi)) {
 981                 for_each_dsi_port(port, intel_dsi->ports) {
 982                         dsi_trans = dsi_port_to_transcoder(port);
 983                         intel_de_write(dev_priv, VSYNC(dsi_trans),
 984                                        (vsync_start - 1) | ((vsync_end - 1) << 16));
 985                 }
 986         }
 987
 988         /*
 989          * FIXME: It has to be programmed only for video modes and interlaced
 990          * modes. Put the check condition here once interlaced
 991          * info available as described above.
 992          * program TRANS_VSYNCSHIFT register
 993          */
 994         if (is_vid_mode(intel_dsi)) {
 995                 for_each_dsi_port(port, intel_dsi->ports) {
 996                         dsi_trans = dsi_port_to_transcoder(port);
 997                         intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),
 998                                        vsync_shift);
 999                 }
1000         }
1001
1002         /* program TRANS_VBLANK register, should be same as vtotal programmed */
1003         if (INTEL_GEN(dev_priv) >= 12) {
1004                 for_each_dsi_port(port, intel_dsi->ports) {
1005                         dsi_trans = dsi_port_to_transcoder(port);
1006                         intel_de_write(dev_priv, VBLANK(dsi_trans),
1007                                        (vactive - 1) | ((vtotal - 1) << 16));
1008                 }
1009         }
1010 }
1011
1012 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1015         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1016         enum port port;
1017         enum transcoder dsi_trans;
1018         u32 tmp;
1019
1020         for_each_dsi_port(port, intel_dsi->ports) {
1021                 dsi_trans = dsi_port_to_transcoder(port);
1022                 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1023                 tmp |= PIPECONF_ENABLE;
1024                 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1025
1026                 /* wait for transcoder to be enabled */
1027                 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1028                                           I965_PIPECONF_ACTIVE, 10))
1029                         drm_err(&dev_priv->drm,
1030                                 "DSI transcoder not enabled\n");
1031         }
1032 }
1033
1034 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1035                                      const struct intel_crtc_state *crtc_state)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1038         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1039         enum port port;
1040         enum transcoder dsi_trans;
1041         u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1042
1043         /*
1044          * escape clock count calculation:
1045          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1046          * UI (nsec) = (10^6)/Bitrate
1047          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1048          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
1049          */
1050         divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1051         mul = 8 * 1000000;
1052         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1053                                      divisor);
1054         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1055         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1056
1057         for_each_dsi_port(port, intel_dsi->ports) {
1058                 dsi_trans = dsi_port_to_transcoder(port);
1059
1060                 /* program hst_tx_timeout */
1061                 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans));
1062                 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
1063                 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
1064                 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp);
1065
1066                 /* FIXME: DSI_CALIB_TO */
1067
1068                 /* program lp_rx_host timeout */
1069                 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans));
1070                 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
1071                 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
1072                 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp);
1073
1074                 /* FIXME: DSI_PWAIT_TO */
1075
1076                 /* program turn around timeout */
1077                 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans));
1078                 tmp &= ~TA_TIMEOUT_VALUE_MASK;
1079                 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
1080                 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp);
1081         }
1082 }
1083
1084 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1085                                       bool enable)
1086 {
1087         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1088         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1089         u32 tmp;
1090
1091         /*
1092          * used as TE i/p for DSI0,
1093          * for dual link/DSI1 TE is from slave DSI1
1094          * through GPIO.
1095          */
1096         if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1097                 return;
1098
1099         tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1100
1101         if (enable) {
1102                 tmp |= UTIL_PIN_DIRECTION_INPUT;
1103                 tmp |= UTIL_PIN_ENABLE;
1104         } else {
1105                 tmp &= ~UTIL_PIN_ENABLE;
1106         }
1107         intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1108 }
1109
1110 static void
1111 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1112                               const struct intel_crtc_state *crtc_state)
1113 {
1114         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1115
1116         /* step 4a: power up all lanes of the DDI used by DSI */
1117         gen11_dsi_power_up_lanes(encoder);
1118
1119         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1120         gen11_dsi_config_phy_lanes_sequence(encoder);
1121
1122         /* step 4c: configure voltage swing and skew */
1123         gen11_dsi_voltage_swing_program_seq(encoder);
1124
1125         /* enable DDI buffer */
1126         gen11_dsi_enable_ddi_buffer(encoder);
1127
1128         /* setup D-PHY timings */
1129         gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1130
1131         /* Since transcoder is configured to take events from GPIO */
1132         gen11_dsi_config_util_pin(encoder, true);
1133
1134         /* step 4h: setup DSI protocol timeouts */
1135         gen11_dsi_setup_timeouts(encoder, crtc_state);
1136
1137         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1138         gen11_dsi_configure_transcoder(encoder, crtc_state);
1139
1140         /* Step 4l: Gate DDI clocks */
1141         if (IS_GEN(dev_priv, 11))
1142                 gen11_dsi_gate_clocks(encoder);
1143 }
1144
1145 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1146 {
1147         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1148         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1149         struct mipi_dsi_device *dsi;
1150         enum port port;
1151         enum transcoder dsi_trans;
1152         u32 tmp;
1153         int ret;
1154
1155         /* set maximum return packet size */
1156         for_each_dsi_port(port, intel_dsi->ports) {
1157                 dsi_trans = dsi_port_to_transcoder(port);
1158
1159                 /*
1160                  * FIXME: This uses the number of DW's currently in the payload
1161                  * receive queue. This is probably not what we want here.
1162                  */
1163                 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1164                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1165                 /* multiply "Number Rx Payload DW" by 4 to get max value */
1166                 tmp = tmp * 4;
1167                 dsi = intel_dsi->dsi_hosts[port]->device;
1168                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1169                 if (ret < 0)
1170                         drm_err(&dev_priv->drm,
1171                                 "error setting max return pkt size%d\n", tmp);
1172         }
1173
1174         /* panel power on related mipi dsi vbt sequences */
1175         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1176         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1177         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1178         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1179         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1180
1181         /* ensure all panel commands dispatched before enabling transcoder */
1182         wait_for_cmds_dispatched_to_panel(encoder);
1183 }
1184
1185 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1186                                      struct intel_encoder *encoder,
1187                                      const struct intel_crtc_state *crtc_state,
1188                                      const struct drm_connector_state *conn_state)
1189 {
1190         /* step2: enable IO power */
1191         gen11_dsi_enable_io_power(encoder);
1192
1193         /* step3: enable DSI PLL */
1194         gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1195 }
1196
1197 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1198                                  struct intel_encoder *encoder,
1199                                  const struct intel_crtc_state *pipe_config,
1200                                  const struct drm_connector_state *conn_state)
1201 {
1202         /* step3b */
1203         gen11_dsi_map_pll(encoder, pipe_config);
1204
1205         /* step4: enable DSI port and DPHY */
1206         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1207
1208         /* step5: program and powerup panel */
1209         gen11_dsi_powerup_panel(encoder);
1210
1211         intel_dsc_enable(encoder, pipe_config);
1212
1213         /* step6c: configure transcoder timings */
1214         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1215 }
1216
1217 static void gen11_dsi_enable(struct intel_atomic_state *state,
1218                              struct intel_encoder *encoder,
1219                              const struct intel_crtc_state *crtc_state,
1220                              const struct drm_connector_state *conn_state)
1221 {
1222         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1223
1224         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
1225
1226         /* step6d: enable dsi transcoder */
1227         gen11_dsi_enable_transcoder(encoder);
1228
1229         /* step7: enable backlight */
1230         intel_panel_enable_backlight(crtc_state, conn_state);
1231         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1232
1233         intel_crtc_vblank_on(crtc_state);
1234 }
1235
1236 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1237 {
1238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1239         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1240         enum port port;
1241         enum transcoder dsi_trans;
1242         u32 tmp;
1243
1244         for_each_dsi_port(port, intel_dsi->ports) {
1245                 dsi_trans = dsi_port_to_transcoder(port);
1246
1247                 /* disable transcoder */
1248                 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1249                 tmp &= ~PIPECONF_ENABLE;
1250                 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1251
1252                 /* wait for transcoder to be disabled */
1253                 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1254                                             I965_PIPECONF_ACTIVE, 50))
1255                         drm_err(&dev_priv->drm,
1256                                 "DSI trancoder not disabled\n");
1257         }
1258 }
1259
1260 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1261 {
1262         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1263
1264         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1265         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1266         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1267
1268         /* ensure cmds dispatched to panel */
1269         wait_for_cmds_dispatched_to_panel(encoder);
1270 }
1271
1272 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1273 {
1274         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1275         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1276         enum port port;
1277         enum transcoder dsi_trans;
1278         u32 tmp;
1279
1280         /* disable periodic update mode */
1281         if (is_cmd_mode(intel_dsi)) {
1282                 for_each_dsi_port(port, intel_dsi->ports) {
1283                         tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
1284                         tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
1285                         intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
1286                 }
1287         }
1288
1289         /* put dsi link in ULPS */
1290         for_each_dsi_port(port, intel_dsi->ports) {
1291                 dsi_trans = dsi_port_to_transcoder(port);
1292                 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1293                 tmp |= LINK_ENTER_ULPS;
1294                 tmp &= ~LINK_ULPS_TYPE_LP11;
1295                 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1296
1297                 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1298                                  LINK_IN_ULPS),
1299                                 10))
1300                         drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1301         }
1302
1303         /* disable ddi function */
1304         for_each_dsi_port(port, intel_dsi->ports) {
1305                 dsi_trans = dsi_port_to_transcoder(port);
1306                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1307                 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1308                 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1309         }
1310
1311         /* disable port sync mode if dual link */
1312         if (intel_dsi->dual_link) {
1313                 for_each_dsi_port(port, intel_dsi->ports) {
1314                         dsi_trans = dsi_port_to_transcoder(port);
1315                         tmp = intel_de_read(dev_priv,
1316                                             TRANS_DDI_FUNC_CTL2(dsi_trans));
1317                         tmp &= ~PORT_SYNC_MODE_ENABLE;
1318                         intel_de_write(dev_priv,
1319                                        TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1320                 }
1321         }
1322 }
1323
1324 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1325 {
1326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1327         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1328         u32 tmp;
1329         enum port port;
1330
1331         gen11_dsi_ungate_clocks(encoder);
1332         for_each_dsi_port(port, intel_dsi->ports) {
1333                 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1334                 tmp &= ~DDI_BUF_CTL_ENABLE;
1335                 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
1336
1337                 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1338                                  DDI_BUF_IS_IDLE),
1339                                  8))
1340                         drm_err(&dev_priv->drm,
1341                                 "DDI port:%c buffer not idle\n",
1342                                 port_name(port));
1343         }
1344         gen11_dsi_gate_clocks(encoder);
1345 }
1346
1347 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1348 {
1349         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1350         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1351         enum port port;
1352         u32 tmp;
1353
1354         for_each_dsi_port(port, intel_dsi->ports) {
1355                 intel_wakeref_t wakeref;
1356
1357                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1358                 intel_display_power_put(dev_priv,
1359                                         port == PORT_A ?
1360                                         POWER_DOMAIN_PORT_DDI_A_IO :
1361                                         POWER_DOMAIN_PORT_DDI_B_IO,
1362                                         wakeref);
1363         }
1364
1365         /* set mode to DDI */
1366         for_each_dsi_port(port, intel_dsi->ports) {
1367                 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
1368                 tmp &= ~COMBO_PHY_MODE_DSI;
1369                 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
1370         }
1371 }
1372
1373 static void gen11_dsi_disable(struct intel_atomic_state *state,
1374                               struct intel_encoder *encoder,
1375                               const struct intel_crtc_state *old_crtc_state,
1376                               const struct drm_connector_state *old_conn_state)
1377 {
1378         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1379
1380         /* step1: turn off backlight */
1381         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1382         intel_panel_disable_backlight(old_conn_state);
1383
1384         /* step2d,e: disable transcoder and wait */
1385         gen11_dsi_disable_transcoder(encoder);
1386
1387         /* step2f,g: powerdown panel */
1388         gen11_dsi_powerdown_panel(encoder);
1389
1390         /* step2h,i,j: deconfig trancoder */
1391         gen11_dsi_deconfigure_trancoder(encoder);
1392
1393         /* step3: disable port */
1394         gen11_dsi_disable_port(encoder);
1395
1396         gen11_dsi_config_util_pin(encoder, false);
1397
1398         /* step4: disable IO power */
1399         gen11_dsi_disable_io_power(encoder);
1400 }
1401
1402 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1403                                    struct intel_encoder *encoder,
1404                                    const struct intel_crtc_state *old_crtc_state,
1405                                    const struct drm_connector_state *old_conn_state)
1406 {
1407         intel_crtc_vblank_off(old_crtc_state);
1408
1409         intel_dsc_disable(old_crtc_state);
1410
1411         skl_scaler_disable(old_crtc_state);
1412 }
1413
1414 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1415                                                  struct drm_display_mode *mode)
1416 {
1417         /* FIXME: DSC? */
1418         return intel_dsi_mode_valid(connector, mode);
1419 }
1420
1421 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1422                                   struct intel_crtc_state *pipe_config)
1423 {
1424         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1425         struct drm_display_mode *adjusted_mode =
1426                                         &pipe_config->hw.adjusted_mode;
1427
1428         if (pipe_config->dsc.compressed_bpp) {
1429                 int div = pipe_config->dsc.compressed_bpp;
1430                 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1431
1432                 adjusted_mode->crtc_htotal =
1433                         DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1434                 adjusted_mode->crtc_hsync_start =
1435                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1436                 adjusted_mode->crtc_hsync_end =
1437                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1438         }
1439
1440         if (intel_dsi->dual_link) {
1441                 adjusted_mode->crtc_hdisplay *= 2;
1442                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1443                         adjusted_mode->crtc_hdisplay -=
1444                                                 intel_dsi->pixel_overlap;
1445                 adjusted_mode->crtc_htotal *= 2;
1446         }
1447         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1448         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1449
1450         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1451                 if (intel_dsi->dual_link) {
1452                         adjusted_mode->crtc_hsync_start *= 2;
1453                         adjusted_mode->crtc_hsync_end *= 2;
1454                 }
1455         }
1456         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1457         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1458 }
1459
1460 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1461 {
1462         struct drm_device *dev = intel_dsi->base.base.dev;
1463         struct drm_i915_private *dev_priv = to_i915(dev);
1464         enum transcoder dsi_trans;
1465         u32 val;
1466
1467         if (intel_dsi->ports == BIT(PORT_B))
1468                 dsi_trans = TRANSCODER_DSI_1;
1469         else
1470                 dsi_trans = TRANSCODER_DSI_0;
1471
1472         val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1473         return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1474 }
1475
1476 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1477                                           struct intel_crtc_state *pipe_config)
1478 {
1479         if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1480                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1481                                             I915_MODE_FLAG_DSI_USE_TE0;
1482         else if (intel_dsi->ports == BIT(PORT_B))
1483                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1484         else
1485                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1486 }
1487
1488 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1489                                  struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1492         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1493         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1494
1495         /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1496         pipe_config->port_clock = intel_dpll_get_freq(i915,
1497                                                       pipe_config->shared_dpll,
1498                                                       &pipe_config->dpll_hw_state);
1499
1500         pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1501         if (intel_dsi->dual_link)
1502                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1503
1504         gen11_dsi_get_timings(encoder, pipe_config);
1505         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1506         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1507
1508         /* Get the details on which TE should be enabled */
1509         if (is_cmd_mode(intel_dsi))
1510                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1511
1512         if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1513                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1514 }
1515
1516 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1517                                         struct intel_crtc_state *crtc_state)
1518 {
1519         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1520         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1521         int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
1522         bool use_dsc;
1523         int ret;
1524
1525         use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1526         if (!use_dsc)
1527                 return 0;
1528
1529         if (crtc_state->pipe_bpp < 8 * 3)
1530                 return -EINVAL;
1531
1532         /* FIXME: split only when necessary */
1533         if (crtc_state->dsc.slice_count > 1)
1534                 crtc_state->dsc.dsc_split = true;
1535
1536         vdsc_cfg->convert_rgb = true;
1537
1538         /* FIXME: initialize from VBT */
1539         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1540
1541         ret = intel_dsc_compute_params(encoder, crtc_state);
1542         if (ret)
1543                 return ret;
1544
1545         /* DSI specific sanity checks on the common code */
1546         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1547         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1548         drm_WARN_ON(&dev_priv->drm,
1549                     vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1550         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1551         drm_WARN_ON(&dev_priv->drm,
1552                     vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1553
1554         ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1555         if (ret)
1556                 return ret;
1557
1558         crtc_state->dsc.compression_enable = true;
1559
1560         return 0;
1561 }
1562
1563 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1564                                     struct intel_crtc_state *pipe_config,
1565                                     struct drm_connector_state *conn_state)
1566 {
1567         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1568         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1569                                                    base);
1570         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1571         const struct drm_display_mode *fixed_mode =
1572                 intel_connector->panel.fixed_mode;
1573         struct drm_display_mode *adjusted_mode =
1574                 &pipe_config->hw.adjusted_mode;
1575         int ret;
1576
1577         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1578         intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1579
1580         ret = intel_pch_panel_fitting(pipe_config, conn_state);
1581         if (ret)
1582                 return ret;
1583
1584         adjusted_mode->flags = 0;
1585
1586         /* Dual link goes to trancoder DSI'0' */
1587         if (intel_dsi->ports == BIT(PORT_B))
1588                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1589         else
1590                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1591
1592         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1593                 pipe_config->pipe_bpp = 24;
1594         else
1595                 pipe_config->pipe_bpp = 18;
1596
1597         pipe_config->clock_set = true;
1598
1599         if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1600                 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1601
1602         pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1603
1604         /*
1605          * In case of TE GATE cmd mode, we
1606          * receive TE from the slave if
1607          * dual link is enabled
1608          */
1609         if (is_cmd_mode(intel_dsi))
1610                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1611
1612         return 0;
1613 }
1614
1615 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1616                                         struct intel_crtc_state *crtc_state)
1617 {
1618         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1619
1620         get_dsi_io_power_domains(i915,
1621                                  enc_to_intel_dsi(encoder));
1622 }
1623
1624 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1625                                    enum pipe *pipe)
1626 {
1627         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1628         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1629         enum transcoder dsi_trans;
1630         intel_wakeref_t wakeref;
1631         enum port port;
1632         bool ret = false;
1633         u32 tmp;
1634
1635         wakeref = intel_display_power_get_if_enabled(dev_priv,
1636                                                      encoder->power_domain);
1637         if (!wakeref)
1638                 return false;
1639
1640         for_each_dsi_port(port, intel_dsi->ports) {
1641                 dsi_trans = dsi_port_to_transcoder(port);
1642                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1643                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1644                 case TRANS_DDI_EDP_INPUT_A_ON:
1645                         *pipe = PIPE_A;
1646                         break;
1647                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1648                         *pipe = PIPE_B;
1649                         break;
1650                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1651                         *pipe = PIPE_C;
1652                         break;
1653                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1654                         *pipe = PIPE_D;
1655                         break;
1656                 default:
1657                         drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1658                         goto out;
1659                 }
1660
1661                 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1662                 ret = tmp & PIPECONF_ENABLE;
1663         }
1664 out:
1665         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1666         return ret;
1667 }
1668
1669 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1670                                             struct intel_crtc_state *crtc_state)
1671 {
1672         if (crtc_state->dsc.compression_enable) {
1673                 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1674                 crtc_state->uapi.mode_changed = true;
1675
1676                 return false;
1677         }
1678
1679         return true;
1680 }
1681
1682 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1683 {
1684         intel_encoder_destroy(encoder);
1685 }
1686
1687 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1688         .destroy = gen11_dsi_encoder_destroy,
1689 };
1690
1691 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1692         .detect = intel_panel_detect,
1693         .late_register = intel_connector_register,
1694         .early_unregister = intel_connector_unregister,
1695         .destroy = intel_connector_destroy,
1696         .fill_modes = drm_helper_probe_single_connector_modes,
1697         .atomic_get_property = intel_digital_connector_atomic_get_property,
1698         .atomic_set_property = intel_digital_connector_atomic_set_property,
1699         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1700         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1701 };
1702
1703 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1704         .get_modes = intel_dsi_get_modes,
1705         .mode_valid = gen11_dsi_mode_valid,
1706         .atomic_check = intel_digital_connector_atomic_check,
1707 };
1708
1709 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1710                                  struct mipi_dsi_device *dsi)
1711 {
1712         return 0;
1713 }
1714
1715 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1716                                  struct mipi_dsi_device *dsi)
1717 {
1718         return 0;
1719 }
1720
1721 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1722                                        const struct mipi_dsi_msg *msg)
1723 {
1724         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1725         struct mipi_dsi_packet dsi_pkt;
1726         ssize_t ret;
1727         bool enable_lpdt = false;
1728
1729         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1730         if (ret < 0)
1731                 return ret;
1732
1733         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1734                 enable_lpdt = true;
1735
1736         /* send packet header */
1737         ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1738         if (ret < 0)
1739                 return ret;
1740
1741         /* only long packet contains payload */
1742         if (mipi_dsi_packet_format_is_long(msg->type)) {
1743                 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1744                 if (ret < 0)
1745                         return ret;
1746         }
1747
1748         //TODO: add payload receive code if needed
1749
1750         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1751
1752         return ret;
1753 }
1754
1755 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1756         .attach = gen11_dsi_host_attach,
1757         .detach = gen11_dsi_host_detach,
1758         .transfer = gen11_dsi_host_transfer,
1759 };
1760
1761 #define ICL_PREPARE_CNT_MAX     0x7
1762 #define ICL_CLK_ZERO_CNT_MAX    0xf
1763 #define ICL_TRAIL_CNT_MAX       0x7
1764 #define ICL_TCLK_PRE_CNT_MAX    0x3
1765 #define ICL_TCLK_POST_CNT_MAX   0x7
1766 #define ICL_HS_ZERO_CNT_MAX     0xf
1767 #define ICL_EXIT_ZERO_CNT_MAX   0x7
1768
1769 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1770 {
1771         struct drm_device *dev = intel_dsi->base.base.dev;
1772         struct drm_i915_private *dev_priv = to_i915(dev);
1773         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1774         u32 tlpx_ns;
1775         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1776         u32 ths_prepare_ns, tclk_trail_ns;
1777         u32 hs_zero_cnt;
1778         u32 tclk_pre_cnt, tclk_post_cnt;
1779
1780         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1781
1782         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1783         ths_prepare_ns = max(mipi_config->ths_prepare,
1784                              mipi_config->tclk_prepare);
1785
1786         /*
1787          * prepare cnt in escape clocks
1788          * this field represents a hexadecimal value with a precision
1789          * of 1.2 – i.e. the most significant bit is the integer
1790          * and the least significant 2 bits are fraction bits.
1791          * so, the field can represent a range of 0.25 to 1.75
1792          */
1793         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1794         if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1795                 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1796                             prepare_cnt);
1797                 prepare_cnt = ICL_PREPARE_CNT_MAX;
1798         }
1799
1800         /* clk zero count in escape clocks */
1801         clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1802                                     ths_prepare_ns, tlpx_ns);
1803         if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1804                 drm_dbg_kms(&dev_priv->drm,
1805                             "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1806                 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1807         }
1808
1809         /* trail cnt in escape clocks*/
1810         trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1811         if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1812                 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1813                             trail_cnt);
1814                 trail_cnt = ICL_TRAIL_CNT_MAX;
1815         }
1816
1817         /* tclk pre count in escape clocks */
1818         tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1819         if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1820                 drm_dbg_kms(&dev_priv->drm,
1821                             "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1822                 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1823         }
1824
1825         /* tclk post count in escape clocks */
1826         tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1827         if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1828                 drm_dbg_kms(&dev_priv->drm,
1829                             "tclk_post_cnt out of range (%d)\n",
1830                             tclk_post_cnt);
1831                 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1832         }
1833
1834         /* hs zero cnt in escape clocks */
1835         hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1836                                    ths_prepare_ns, tlpx_ns);
1837         if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1838                 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1839                             hs_zero_cnt);
1840                 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1841         }
1842
1843         /* hs exit zero cnt in escape clocks */
1844         exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1845         if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1846                 drm_dbg_kms(&dev_priv->drm,
1847                             "exit_zero_cnt out of range (%d)\n",
1848                             exit_zero_cnt);
1849                 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1850         }
1851
1852         /* clock lane dphy timings */
1853         intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1854                                CLK_PREPARE(prepare_cnt) |
1855                                CLK_ZERO_OVERRIDE |
1856                                CLK_ZERO(clk_zero_cnt) |
1857                                CLK_PRE_OVERRIDE |
1858                                CLK_PRE(tclk_pre_cnt) |
1859                                CLK_POST_OVERRIDE |
1860                                CLK_POST(tclk_post_cnt) |
1861                                CLK_TRAIL_OVERRIDE |
1862                                CLK_TRAIL(trail_cnt));
1863
1864         /* data lanes dphy timings */
1865         intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1866                                          HS_PREPARE(prepare_cnt) |
1867                                          HS_ZERO_OVERRIDE |
1868                                          HS_ZERO(hs_zero_cnt) |
1869                                          HS_TRAIL_OVERRIDE |
1870                                          HS_TRAIL(trail_cnt) |
1871                                          HS_EXIT_OVERRIDE |
1872                                          HS_EXIT(exit_zero_cnt));
1873
1874         intel_dsi_log_params(intel_dsi);
1875 }
1876
1877 static void icl_dsi_add_properties(struct intel_connector *connector)
1878 {
1879         u32 allowed_scalers;
1880
1881         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1882                            BIT(DRM_MODE_SCALE_FULLSCREEN) |
1883                            BIT(DRM_MODE_SCALE_CENTER);
1884
1885         drm_connector_attach_scaling_mode_property(&connector->base,
1886                                                    allowed_scalers);
1887
1888         connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1889
1890         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1891                                 intel_dsi_get_panel_orientation(connector),
1892                                 connector->panel.fixed_mode->hdisplay,
1893                                 connector->panel.fixed_mode->vdisplay);
1894 }
1895
1896 void icl_dsi_init(struct drm_i915_private *dev_priv)
1897 {
1898         struct drm_device *dev = &dev_priv->drm;
1899         struct intel_dsi *intel_dsi;
1900         struct intel_encoder *encoder;
1901         struct intel_connector *intel_connector;
1902         struct drm_connector *connector;
1903         struct drm_display_mode *fixed_mode;
1904         enum port port;
1905
1906         if (!intel_bios_is_dsi_present(dev_priv, &port))
1907                 return;
1908
1909         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1910         if (!intel_dsi)
1911                 return;
1912
1913         intel_connector = intel_connector_alloc();
1914         if (!intel_connector) {
1915                 kfree(intel_dsi);
1916                 return;
1917         }
1918
1919         encoder = &intel_dsi->base;
1920         intel_dsi->attached_connector = intel_connector;
1921         connector = &intel_connector->base;
1922
1923         /* register DSI encoder with DRM subsystem */
1924         drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1925                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1926
1927         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1928         encoder->pre_enable = gen11_dsi_pre_enable;
1929         encoder->enable = gen11_dsi_enable;
1930         encoder->disable = gen11_dsi_disable;
1931         encoder->post_disable = gen11_dsi_post_disable;
1932         encoder->port = port;
1933         encoder->get_config = gen11_dsi_get_config;
1934         encoder->update_pipe = intel_panel_update_backlight;
1935         encoder->compute_config = gen11_dsi_compute_config;
1936         encoder->get_hw_state = gen11_dsi_get_hw_state;
1937         encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1938         encoder->type = INTEL_OUTPUT_DSI;
1939         encoder->cloneable = 0;
1940         encoder->pipe_mask = ~0;
1941         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1942         encoder->get_power_domains = gen11_dsi_get_power_domains;
1943
1944         /* register DSI connector with DRM subsystem */
1945         drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1946                            DRM_MODE_CONNECTOR_DSI);
1947         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1948         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1949         connector->interlace_allowed = false;
1950         connector->doublescan_allowed = false;
1951         intel_connector->get_hw_state = intel_connector_get_hw_state;
1952
1953         /* attach connector to encoder */
1954         intel_connector_attach_encoder(intel_connector, encoder);
1955
1956         mutex_lock(&dev->mode_config.mutex);
1957         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1958         mutex_unlock(&dev->mode_config.mutex);
1959
1960         if (!fixed_mode) {
1961                 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
1962                 goto err;
1963         }
1964
1965         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1966         intel_panel_setup_backlight(connector, INVALID_PIPE);
1967
1968         if (dev_priv->vbt.dsi.config->dual_link)
1969                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1970         else
1971                 intel_dsi->ports = BIT(port);
1972
1973         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1974         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1975
1976         for_each_dsi_port(port, intel_dsi->ports) {
1977                 struct intel_dsi_host *host;
1978
1979                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1980                 if (!host)
1981                         goto err;
1982
1983                 intel_dsi->dsi_hosts[port] = host;
1984         }
1985
1986         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1987                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1988                 goto err;
1989         }
1990
1991         icl_dphy_param_init(intel_dsi);
1992
1993         icl_dsi_add_properties(intel_connector);
1994         return;
1995
1996 err:
1997         drm_connector_cleanup(connector);
1998         drm_encoder_cleanup(&encoder->base);
1999         kfree(intel_dsi);
2000         kfree(intel_connector);
2001 }