drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

   1 /* Hisilicon Hibmc SoC drm driver
   2  *
   3  * Based on the bochs drm driver.
   4  *
   5  * Copyright (c) 2016 Huawei Limited.
   6  *
   7  * Author:
   8  *      Rongrong Zou <zourongrong@huawei.com>
   9  *      Rongrong Zou <zourongrong@gmail.com>
  10  *      Jianhua Li <lijianhua@huawei.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  */
  18
  19 #include <drm/drm_atomic.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23
  24 #include "hibmc_drm_drv.h"
  25 #include "hibmc_drm_regs.h"
  26
  27 struct hibmc_display_panel_pll {
  28         unsigned long M;
  29         unsigned long N;
  30         unsigned long OD;
  31         unsigned long POD;
  32 };
  33
  34 struct hibmc_dislay_pll_config {
  35         unsigned long hdisplay;
  36         unsigned long vdisplay;
  37         u32 pll1_config_value;
  38         u32 pll2_config_value;
  39 };
  40
  41 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
  42         {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
  43         {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
  44         {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
  45         {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ},
  46         {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
  47         {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
  48         {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
  49         {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
  50         {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
  51         {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
  52 };
  53
  54 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1)))
  55
  56 static int hibmc_plane_atomic_check(struct drm_plane *plane,
  57                                     struct drm_plane_state *state)
  58 {
  59         struct drm_framebuffer *fb = state->fb;
  60         struct drm_crtc *crtc = state->crtc;
  61         struct drm_crtc_state *crtc_state;
  62         u32 src_w = state->src_w >> 16;
  63         u32 src_h = state->src_h >> 16;
  64
  65         if (!crtc || !fb)
  66                 return 0;
  67
  68         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
  69         if (IS_ERR(crtc_state))
  70                 return PTR_ERR(crtc_state);
  71
  72         if (src_w != state->crtc_w || src_h != state->crtc_h) {
  73                 DRM_DEBUG_ATOMIC("scale not support\n");
  74                 return -EINVAL;
  75         }
  76
  77         if (state->crtc_x < 0 || state->crtc_y < 0) {
  78                 DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n");
  79                 return -EINVAL;
  80         }
  81
  82         if (state->crtc_x + state->crtc_w >
  83             crtc_state->adjusted_mode.hdisplay ||
  84             state->crtc_y + state->crtc_h >
  85             crtc_state->adjusted_mode.vdisplay) {
  86                 DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n");
  87                 return -EINVAL;
  88         }
  89
  90         return 0;
  91 }
  92
  93 static void hibmc_plane_atomic_update(struct drm_plane *plane,
  94                                       struct drm_plane_state *old_state)
  95 {
  96         struct drm_plane_state  *state  = plane->state;
  97         u32 reg;
  98         int ret;
  99         u64 gpu_addr = 0;
 100         unsigned int line_l;
 101         struct hibmc_drm_private *priv = plane->dev->dev_private;
 102         struct hibmc_framebuffer *hibmc_fb;
 103         struct hibmc_bo *bo;
 104
 105         if (!state->fb)
 106                 return;
 107
 108         hibmc_fb = to_hibmc_framebuffer(state->fb);
 109         bo = gem_to_hibmc_bo(hibmc_fb->obj);
 110         ret = ttm_bo_reserve(&bo->bo, true, false, NULL);
 111         if (ret) {
 112                 DRM_ERROR("failed to reserve ttm_bo: %d", ret);
 113                 return;
 114         }
 115
 116         ret = hibmc_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
 117         ttm_bo_unreserve(&bo->bo);
 118         if (ret) {
 119                 DRM_ERROR("failed to pin hibmc_bo: %d", ret);
 120                 return;
 121         }
 122
 123         writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
 124
 125         reg = state->fb->width * (state->fb->format->cpp[0]);
 126         /* now line_pad is 16 */
 127         reg = PADDING(16, reg);
 128
 129         line_l = state->fb->width * state->fb->format->cpp[0];
 130         line_l = PADDING(16, line_l);
 131         writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
 132                HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
 133                priv->mmio + HIBMC_CRT_FB_WIDTH);
 134
 135         /* SET PIXEL FORMAT */
 136         reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
 137         reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK;
 138         reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
 139                            state->fb->format->cpp[0] * 8 / 16);
 140         writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
 141 }
 142
 143 static const u32 channel_formats1[] = {
 144         DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
 145         DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
 146         DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
 147         DRM_FORMAT_ABGR8888
 148 };
 149
 150 static struct drm_plane_funcs hibmc_plane_funcs = {
 151         .update_plane   = drm_atomic_helper_update_plane,
 152         .disable_plane  = drm_atomic_helper_disable_plane,
 153         .set_property = drm_atomic_helper_plane_set_property,
 154         .destroy = drm_plane_cleanup,
 155         .reset = drm_atomic_helper_plane_reset,
 156         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 157         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 158 };
 159
 160 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
 161         .atomic_check = hibmc_plane_atomic_check,
 162         .atomic_update = hibmc_plane_atomic_update,
 163 };
 164
 165 static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv)
 166 {
 167         struct drm_device *dev = priv->dev;
 168         struct drm_plane *plane;
 169         int ret = 0;
 170
 171         plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
 172         if (!plane) {
 173                 DRM_ERROR("failed to alloc memory when init plane\n");
 174                 return ERR_PTR(-ENOMEM);
 175         }
 176         /*
 177          * plane init
 178          * TODO: Now only support primary plane, overlay planes
 179          * need to do.
 180          */
 181         ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs,
 182                                        channel_formats1,
 183                                        ARRAY_SIZE(channel_formats1),
 184                                        DRM_PLANE_TYPE_PRIMARY,
 185                                        NULL);
 186         if (ret) {
 187                 DRM_ERROR("failed to init plane: %d\n", ret);
 188                 return ERR_PTR(ret);
 189         }
 190
 191         drm_plane_helper_add(plane, &hibmc_plane_helper_funcs);
 192         return plane;
 193 }
 194
 195 static void hibmc_crtc_enable(struct drm_crtc *crtc)
 196 {
 197         unsigned int reg;
 198         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 199
 200         hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
 201
 202         /* Enable display power gate & LOCALMEM power gate*/
 203         reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
 204         reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
 205         reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
 206         reg |= HIBMC_CURR_GATE_LOCALMEM(1);
 207         reg |= HIBMC_CURR_GATE_DISPLAY(1);
 208         hibmc_set_current_gate(priv, reg);
 209         drm_crtc_vblank_on(crtc);
 210 }
 211
 212 static void hibmc_crtc_disable(struct drm_crtc *crtc)
 213 {
 214         unsigned int reg;
 215         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 216
 217         drm_crtc_vblank_off(crtc);
 218
 219         hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP);
 220
 221         /* Enable display power gate & LOCALMEM power gate*/
 222         reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
 223         reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
 224         reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
 225         reg |= HIBMC_CURR_GATE_LOCALMEM(0);
 226         reg |= HIBMC_CURR_GATE_DISPLAY(0);
 227         hibmc_set_current_gate(priv, reg);
 228 }
 229
 230 static unsigned int format_pll_reg(void)
 231 {
 232         unsigned int pllreg = 0;
 233         struct hibmc_display_panel_pll pll = {0};
 234
 235         /*
 236          * Note that all PLL's have the same format. Here,
 237          * we just use Panel PLL parameter to work out the bit
 238          * fields in the register.On returning a 32 bit number, the value can
 239          * be applied to any PLL in the calling function.
 240          */
 241         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);
 242         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);
 243         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);
 244         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
 245         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
 246         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
 247         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
 248
 249         return pllreg;
 250 }
 251
 252 static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll)
 253 {
 254         u32 val;
 255         struct hibmc_drm_private *priv = dev->dev_private;
 256
 257         val = readl(priv->mmio + CRT_PLL1_HS);
 258         val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1));
 259         writel(val, priv->mmio + CRT_PLL1_HS);
 260
 261         val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1);
 262         writel(val, priv->mmio + CRT_PLL1_HS);
 263
 264         writel(pll, priv->mmio + CRT_PLL1_HS);
 265
 266         usleep_range(1000, 2000);
 267
 268         val = pll & ~(CRT_PLL1_HS_POWERON(1));
 269         writel(val, priv->mmio + CRT_PLL1_HS);
 270
 271         usleep_range(1000, 2000);
 272
 273         val &= ~(CRT_PLL1_HS_INTER_BYPASS(1));
 274         writel(val, priv->mmio + CRT_PLL1_HS);
 275
 276         usleep_range(1000, 2000);
 277
 278         val |= CRT_PLL1_HS_OUTER_BYPASS(1);
 279         writel(val, priv->mmio + CRT_PLL1_HS);
 280 }
 281
 282 static void get_pll_config(unsigned long x, unsigned long y,
 283                            u32 *pll1, u32 *pll2)
 284 {
 285         int i;
 286         int count = ARRAY_SIZE(hibmc_pll_table);
 287
 288         for (i = 0; i < count; i++) {
 289                 if (hibmc_pll_table[i].hdisplay == x &&
 290                     hibmc_pll_table[i].vdisplay == y) {
 291                         *pll1 = hibmc_pll_table[i].pll1_config_value;
 292                         *pll2 = hibmc_pll_table[i].pll2_config_value;
 293                         return;
 294                 }
 295         }
 296
 297         /* if found none, we use default value */
 298         *pll1 = CRT_PLL1_HS_25MHZ;
 299         *pll2 = CRT_PLL2_HS_25MHZ;
 300 }
 301
 302 /*
 303  * This function takes care the extra registers and bit fields required to
 304  * setup a mode in board.
 305  * Explanation about Display Control register:
 306  * FPGA only supports 7 predefined pixel clocks, and clock select is
 307  * in bit 4:0 of new register 0x802a8.
 308  */
 309 static unsigned int display_ctrl_adjust(struct drm_device *dev,
 310                                         struct drm_display_mode *mode,
 311                                         unsigned int ctrl)
 312 {
 313         unsigned long x, y;
 314         u32 pll1; /* bit[31:0] of PLL */
 315         u32 pll2; /* bit[63:32] of PLL */
 316         struct hibmc_drm_private *priv = dev->dev_private;
 317
 318         x = mode->hdisplay;
 319         y = mode->vdisplay;
 320
 321         get_pll_config(x, y, &pll1, &pll2);
 322         writel(pll2, priv->mmio + CRT_PLL2_HS);
 323         set_vclock_hisilicon(dev, pll1);
 324
 325         /*
 326          * Hisilicon has to set up the top-left and bottom-right
 327          * registers as well.
 328          * Note that normal chip only use those two register for
 329          * auto-centering mode.
 330          */
 331         writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
 332                HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),
 333                priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);
 334
 335         writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
 336                HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),
 337                priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);
 338
 339         /*
 340          * Assume common fields in ctrl have been properly set before
 341          * calling this function.
 342          * This function only sets the extra fields in ctrl.
 343          */
 344
 345         /* Set bit 25 of display controller: Select CRT or VGA clock */
 346         ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK;
 347         ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK;
 348
 349         ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT);
 350
 351         /* clock_phase_polarity is 0 */
 352         ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0);
 353
 354         writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);
 355
 356         return ctrl;
 357 }
 358
 359 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 360 {
 361         unsigned int val;
 362         struct drm_display_mode *mode = &crtc->state->mode;
 363         struct drm_device *dev = crtc->dev;
 364         struct hibmc_drm_private *priv = dev->dev_private;
 365         int width = mode->hsync_end - mode->hsync_start;
 366         int height = mode->vsync_end - mode->vsync_start;
 367
 368         writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);
 369         writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
 370                HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),
 371                priv->mmio + HIBMC_CRT_HORZ_TOTAL);
 372
 373         writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
 374                HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),
 375                priv->mmio + HIBMC_CRT_HORZ_SYNC);
 376
 377         writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
 378                HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),
 379                priv->mmio + HIBMC_CRT_VERT_TOTAL);
 380
 381         writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
 382                HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),
 383                priv->mmio + HIBMC_CRT_VERT_SYNC);
 384
 385         val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);
 386         val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);
 387         val |= HIBMC_CRT_DISP_CTL_TIMING(1);
 388         val |= HIBMC_CRT_DISP_CTL_PLANE(1);
 389
 390         display_ctrl_adjust(dev, mode, val);
 391 }
 392
 393 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc,
 394                                     struct drm_crtc_state *old_state)
 395 {
 396         unsigned int reg;
 397         struct drm_device *dev = crtc->dev;
 398         struct hibmc_drm_private *priv = dev->dev_private;
 399
 400         hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
 401
 402         /* Enable display power gate & LOCALMEM power gate*/
 403         reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
 404         reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
 405         reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
 406         reg |= HIBMC_CURR_GATE_DISPLAY(1);
 407         reg |= HIBMC_CURR_GATE_LOCALMEM(1);
 408         hibmc_set_current_gate(priv, reg);
 409
 410         /* We can add more initialization as needed. */
 411 }
 412
 413 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc,
 414                                     struct drm_crtc_state *old_state)
 415
 416 {
 417         unsigned long flags;
 418
 419         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 420         if (crtc->state->event)
 421                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 422         crtc->state->event = NULL;
 423         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 424 }
 425
 426 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc)
 427 {
 428         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 429
 430         writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1),
 431                priv->mmio + HIBMC_RAW_INTERRUPT_EN);
 432
 433         return 0;
 434 }
 435
 436 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc)
 437 {
 438         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 439
 440         writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0),
 441                priv->mmio + HIBMC_RAW_INTERRUPT_EN);
 442 }
 443
 444 static const struct drm_crtc_funcs hibmc_crtc_funcs = {
 445         .page_flip = drm_atomic_helper_page_flip,
 446         .set_config = drm_atomic_helper_set_config,
 447         .destroy = drm_crtc_cleanup,
 448         .reset = drm_atomic_helper_crtc_reset,
 449         .atomic_duplicate_state =  drm_atomic_helper_crtc_duplicate_state,
 450         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 451         .enable_vblank = hibmc_crtc_enable_vblank,
 452         .disable_vblank = hibmc_crtc_disable_vblank,
 453 };
 454
 455 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = {
 456         .enable         = hibmc_crtc_enable,
 457         .disable        = hibmc_crtc_disable,
 458         .mode_set_nofb  = hibmc_crtc_mode_set_nofb,
 459         .atomic_begin   = hibmc_crtc_atomic_begin,
 460         .atomic_flush   = hibmc_crtc_atomic_flush,
 461 };
 462
 463 int hibmc_de_init(struct hibmc_drm_private *priv)
 464 {
 465         struct drm_device *dev = priv->dev;
 466         struct drm_crtc *crtc;
 467         struct drm_plane *plane;
 468         int ret;
 469
 470         plane = hibmc_plane_init(priv);
 471         if (IS_ERR(plane)) {
 472                 DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane));
 473                 return PTR_ERR(plane);
 474         }
 475
 476         crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL);
 477         if (!crtc) {
 478                 DRM_ERROR("failed to alloc memory when init crtc\n");
 479                 return -ENOMEM;
 480         }
 481
 482         ret = drm_crtc_init_with_planes(dev, crtc, plane,
 483                                         NULL, &hibmc_crtc_funcs, NULL);
 484         if (ret) {
 485                 DRM_ERROR("failed to init crtc: %d\n", ret);
 486                 return ret;
 487         }
 488
 489         ret = drm_mode_crtc_set_gamma_size(crtc, 256);
 490         if (ret) {
 491                 DRM_ERROR("failed to set gamma size: %d\n", ret);
 492                 return ret;
 493         }
 494         drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs);
 495
 496         return 0;
 497 }