drivers/gpu/drm/etnaviv/etnaviv_iommu.c

   1 /*
   2  * Copyright (C) 2014 Christian Gmeiner <christian.gmeiner@gmail.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/sizes.h>
  19 #include <linux/slab.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/bitops.h>
  22
  23 #include "etnaviv_gpu.h"
  24 #include "etnaviv_mmu.h"
  25 #include "etnaviv_iommu.h"
  26 #include "state_hi.xml.h"
  27
  28 #define PT_SIZE         SZ_2M
  29 #define PT_ENTRIES      (PT_SIZE / sizeof(u32))
  30
  31 #define GPU_MEM_START   0x80000000
  32
  33 struct etnaviv_iommuv1_domain {
  34         struct etnaviv_iommu_domain base;
  35         u32 *pgtable_cpu;
  36         dma_addr_t pgtable_dma;
  37 };
  38
  39 static struct etnaviv_iommuv1_domain *
  40 to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
  41 {
  42         return container_of(domain, struct etnaviv_iommuv1_domain, base);
  43 }
  44
  45 static int __etnaviv_iommu_init(struct etnaviv_iommuv1_domain *etnaviv_domain)
  46 {
  47         u32 *p;
  48         int i;
  49
  50         etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
  51                                                 etnaviv_domain->base.dev,
  52                                                 SZ_4K,
  53                                                 &etnaviv_domain->base.bad_page_dma,
  54                                                 GFP_KERNEL);
  55         if (!etnaviv_domain->base.bad_page_cpu)
  56                 return -ENOMEM;
  57
  58         p = etnaviv_domain->base.bad_page_cpu;
  59         for (i = 0; i < SZ_4K / 4; i++)
  60                 *p++ = 0xdead55aa;
  61
  62         etnaviv_domain->pgtable_cpu =
  63                         dma_alloc_coherent(etnaviv_domain->base.dev, PT_SIZE,
  64                                            &etnaviv_domain->pgtable_dma,
  65                                            GFP_KERNEL);
  66         if (!etnaviv_domain->pgtable_cpu) {
  67                 dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
  68                                   etnaviv_domain->base.bad_page_cpu,
  69                                   etnaviv_domain->base.bad_page_dma);
  70                 return -ENOMEM;
  71         }
  72
  73         for (i = 0; i < PT_ENTRIES; i++)
  74                 etnaviv_domain->pgtable_cpu[i] =
  75                                 etnaviv_domain->base.bad_page_dma;
  76
  77         return 0;
  78 }
  79
  80 static void etnaviv_iommuv1_domain_free(struct etnaviv_iommu_domain *domain)
  81 {
  82         struct etnaviv_iommuv1_domain *etnaviv_domain =
  83                         to_etnaviv_domain(domain);
  84
  85         dma_free_coherent(etnaviv_domain->base.dev, PT_SIZE,
  86                           etnaviv_domain->pgtable_cpu,
  87                           etnaviv_domain->pgtable_dma);
  88
  89         dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
  90                           etnaviv_domain->base.bad_page_cpu,
  91                           etnaviv_domain->base.bad_page_dma);
  92
  93         kfree(etnaviv_domain);
  94 }
  95
  96 static int etnaviv_iommuv1_map(struct etnaviv_iommu_domain *domain,
  97                                unsigned long iova, phys_addr_t paddr,
  98                                size_t size, int prot)
  99 {
 100         struct etnaviv_iommuv1_domain *etnaviv_domain = to_etnaviv_domain(domain);
 101         unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
 102
 103         if (size != SZ_4K)
 104                 return -EINVAL;
 105
 106         etnaviv_domain->pgtable_cpu[index] = paddr;
 107
 108         return 0;
 109 }
 110
 111 static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_domain *domain,
 112         unsigned long iova, size_t size)
 113 {
 114         struct etnaviv_iommuv1_domain *etnaviv_domain =
 115                         to_etnaviv_domain(domain);
 116         unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
 117
 118         if (size != SZ_4K)
 119                 return -EINVAL;
 120
 121         etnaviv_domain->pgtable_cpu[index] = etnaviv_domain->base.bad_page_dma;
 122
 123         return SZ_4K;
 124 }
 125
 126 static size_t etnaviv_iommuv1_dump_size(struct etnaviv_iommu_domain *domain)
 127 {
 128         return PT_SIZE;
 129 }
 130
 131 static void etnaviv_iommuv1_dump(struct etnaviv_iommu_domain *domain, void *buf)
 132 {
 133         struct etnaviv_iommuv1_domain *etnaviv_domain =
 134                         to_etnaviv_domain(domain);
 135
 136         memcpy(buf, etnaviv_domain->pgtable_cpu, PT_SIZE);
 137 }
 138
 139 void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
 140 {
 141         struct etnaviv_iommuv1_domain *etnaviv_domain =
 142                         to_etnaviv_domain(gpu->mmu->domain);
 143         u32 pgtable;
 144
 145         /* set base addresses */
 146         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
 147         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
 148         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
 149         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
 150         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
 151
 152         /* set page table address in MC */
 153         pgtable = (u32)etnaviv_domain->pgtable_dma;
 154
 155         gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable);
 156         gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable);
 157         gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable);
 158         gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable);
 159         gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
 160 }
 161
 162 const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
 163         .free = etnaviv_iommuv1_domain_free,
 164         .map = etnaviv_iommuv1_map,
 165         .unmap = etnaviv_iommuv1_unmap,
 166         .dump_size = etnaviv_iommuv1_dump_size,
 167         .dump = etnaviv_iommuv1_dump,
 168 };
 169
 170 struct etnaviv_iommu_domain *
 171 etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
 172 {
 173         struct etnaviv_iommuv1_domain *etnaviv_domain;
 174         struct etnaviv_iommu_domain *domain;
 175         int ret;
 176
 177         etnaviv_domain = kzalloc(sizeof(*etnaviv_domain), GFP_KERNEL);
 178         if (!etnaviv_domain)
 179                 return NULL;
 180
 181         domain = &etnaviv_domain->base;
 182
 183         domain->dev = gpu->dev;
 184         domain->base = GPU_MEM_START;
 185         domain->size = PT_ENTRIES * SZ_4K;
 186         domain->ops = &etnaviv_iommuv1_ops;
 187
 188         ret = __etnaviv_iommu_init(etnaviv_domain);
 189         if (ret)
 190                 goto out_free;
 191
 192         return &etnaviv_domain->base;
 193
 194 out_free:
 195         kfree(etnaviv_domain);
 196         return NULL;
 197 }