drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/irq.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <drm/drm_of.h>
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_encoder_slave.h>
  31 #include <drm/bridge/dw_hdmi.h>
  32
  33 #include <uapi/linux/media-bus-format.h>
  34 #include <uapi/linux/videodev2.h>
  35
  36 #include "dw-hdmi.h"
  37 #include "dw-hdmi-audio.h"
  38 #include "dw-hdmi-cec.h"
  39
  40 #include <media/cec-notifier.h>
  41
  42 #define DDC_SEGMENT_ADDR        0x30
  43
  44 #define HDMI_EDID_LEN           512
  45
  46 enum hdmi_datamap {
  47         RGB444_8B = 0x01,
  48         RGB444_10B = 0x03,
  49         RGB444_12B = 0x05,
  50         RGB444_16B = 0x07,
  51         YCbCr444_8B = 0x09,
  52         YCbCr444_10B = 0x0B,
  53         YCbCr444_12B = 0x0D,
  54         YCbCr444_16B = 0x0F,
  55         YCbCr422_8B = 0x16,
  56         YCbCr422_10B = 0x14,
  57         YCbCr422_12B = 0x12,
  58 };
  59
  60 static const u16 csc_coeff_default[3][4] = {
  61         { 0x2000, 0x0000, 0x0000, 0x0000 },
  62         { 0x0000, 0x2000, 0x0000, 0x0000 },
  63         { 0x0000, 0x0000, 0x2000, 0x0000 }
  64 };
  65
  66 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  67         { 0x2000, 0x6926, 0x74fd, 0x010e },
  68         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  69         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  70 };
  71
  72 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  73         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  74         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  75         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  76 };
  77
  78 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  79         { 0x2591, 0x1322, 0x074b, 0x0000 },
  80         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  81         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  82 };
  83
  84 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  85         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  86         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  87         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  88 };
  89
  90 struct hdmi_vmode {
  91         bool mdataenablepolarity;
  92
  93         unsigned int mpixelclock;
  94         unsigned int mpixelrepetitioninput;
  95         unsigned int mpixelrepetitionoutput;
  96 };
  97
  98 struct hdmi_data_info {
  99         unsigned int enc_in_bus_format;
 100         unsigned int enc_out_bus_format;
 101         unsigned int enc_in_encoding;
 102         unsigned int enc_out_encoding;
 103         unsigned int pix_repet_factor;
 104         unsigned int hdcp_enable;
 105         struct hdmi_vmode video_mode;
 106 };
 107
 108 struct dw_hdmi_i2c {
 109         struct i2c_adapter      adap;
 110
 111         struct mutex            lock;   /* used to serialize data transfers */
 112         struct completion       cmp;
 113         u8                      stat;
 114
 115         u8                      slave_reg;
 116         bool                    is_regaddr;
 117         bool                    is_segment;
 118 };
 119
 120 struct dw_hdmi_phy_data {
 121         enum dw_hdmi_phy_type type;
 122         const char *name;
 123         unsigned int gen;
 124         bool has_svsret;
 125         int (*configure)(struct dw_hdmi *hdmi,
 126                          const struct dw_hdmi_plat_data *pdata,
 127                          unsigned long mpixelclock);
 128 };
 129
 130 struct dw_hdmi {
 131         struct drm_connector connector;
 132         struct drm_bridge bridge;
 133
 134         unsigned int version;
 135
 136         struct platform_device *audio;
 137         struct platform_device *cec;
 138         struct device *dev;
 139         struct clk *isfr_clk;
 140         struct clk *iahb_clk;
 141         struct clk *cec_clk;
 142         struct dw_hdmi_i2c *i2c;
 143
 144         struct hdmi_data_info hdmi_data;
 145         const struct dw_hdmi_plat_data *plat_data;
 146
 147         int vic;
 148
 149         u8 edid[HDMI_EDID_LEN];
 150         bool cable_plugin;
 151
 152         struct {
 153                 const struct dw_hdmi_phy_ops *ops;
 154                 const char *name;
 155                 void *data;
 156                 bool enabled;
 157         } phy;
 158
 159         struct drm_display_mode previous_mode;
 160
 161         struct i2c_adapter *ddc;
 162         void __iomem *regs;
 163         bool sink_is_hdmi;
 164         bool sink_has_audio;
 165
 166         struct mutex mutex;             /* for state below and previous_mode */
 167         enum drm_connector_force force; /* mutex-protected force state */
 168         bool disabled;                  /* DRM has disabled our bridge */
 169         bool bridge_is_on;              /* indicates the bridge is on */
 170         bool rxsense;                   /* rxsense state */
 171         u8 phy_mask;                    /* desired phy int mask settings */
 172         u8 mc_clkdis;                   /* clock disable register */
 173
 174         spinlock_t audio_lock;
 175         struct mutex audio_mutex;
 176         unsigned int sample_rate;
 177         unsigned int audio_cts;
 178         unsigned int audio_n;
 179         bool audio_enable;
 180
 181         unsigned int reg_shift;
 182         struct regmap *regm;
 183         void (*enable_audio)(struct dw_hdmi *hdmi);
 184         void (*disable_audio)(struct dw_hdmi *hdmi);
 185
 186         struct cec_notifier *cec_notifier;
 187 };
 188
 189 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 190         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 191          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 192
 193 #define HDMI_PHY_RX_SENSE \
 194         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 195          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 196
 197 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 198 {
 199         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
 200 }
 201
 202 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 203 {
 204         unsigned int val = 0;
 205
 206         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
 207
 208         return val;
 209 }
 210
 211 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 212 {
 213         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
 214 }
 215
 216 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 217                              u8 shift, u8 mask)
 218 {
 219         hdmi_modb(hdmi, data << shift, mask, reg);
 220 }
 221
 222 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 223 {
 224         /* Software reset */
 225         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 226
 227         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 228         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 229
 230         /* Set done, not acknowledged and arbitration interrupt polarities */
 231         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 232         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 233                     HDMI_I2CM_CTLINT);
 234
 235         /* Clear DONE and ERROR interrupts */
 236         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 237                     HDMI_IH_I2CM_STAT0);
 238
 239         /* Mute DONE and ERROR interrupts */
 240         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 241                     HDMI_IH_MUTE_I2CM_STAT0);
 242 }
 243
 244 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 245                             unsigned char *buf, unsigned int length)
 246 {
 247         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 248         int stat;
 249
 250         if (!i2c->is_regaddr) {
 251                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 252                 i2c->slave_reg = 0x00;
 253                 i2c->is_regaddr = true;
 254         }
 255
 256         while (length--) {
 257                 reinit_completion(&i2c->cmp);
 258
 259                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 260                 if (i2c->is_segment)
 261                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 262                                     HDMI_I2CM_OPERATION);
 263                 else
 264                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 265                                     HDMI_I2CM_OPERATION);
 266
 267                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 268                 if (!stat)
 269                         return -EAGAIN;
 270
 271                 /* Check for error condition on the bus */
 272                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 273                         return -EIO;
 274
 275                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 276         }
 277         i2c->is_segment = false;
 278
 279         return 0;
 280 }
 281
 282 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 283                              unsigned char *buf, unsigned int length)
 284 {
 285         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 286         int stat;
 287
 288         if (!i2c->is_regaddr) {
 289                 /* Use the first write byte as register address */
 290                 i2c->slave_reg = buf[0];
 291                 length--;
 292                 buf++;
 293                 i2c->is_regaddr = true;
 294         }
 295
 296         while (length--) {
 297                 reinit_completion(&i2c->cmp);
 298
 299                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 300                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 301                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 302                             HDMI_I2CM_OPERATION);
 303
 304                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 305                 if (!stat)
 306                         return -EAGAIN;
 307
 308                 /* Check for error condition on the bus */
 309                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 310                         return -EIO;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 317                             struct i2c_msg *msgs, int num)
 318 {
 319         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 320         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 321         u8 addr = msgs[0].addr;
 322         int i, ret = 0;
 323
 324         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 325
 326         for (i = 0; i < num; i++) {
 327                 if (msgs[i].len == 0) {
 328                         dev_dbg(hdmi->dev,
 329                                 "unsupported transfer %d/%d, no data\n",
 330                                 i + 1, num);
 331                         return -EOPNOTSUPP;
 332                 }
 333         }
 334
 335         mutex_lock(&i2c->lock);
 336
 337         /* Unmute DONE and ERROR interrupts */
 338         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 339
 340         /* Set slave device address taken from the first I2C message */
 341         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 342
 343         /* Set slave device register address on transfer */
 344         i2c->is_regaddr = false;
 345
 346         /* Set segment pointer for I2C extended read mode operation */
 347         i2c->is_segment = false;
 348
 349         for (i = 0; i < num; i++) {
 350                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 351                         i + 1, num, msgs[i].len, msgs[i].flags);
 352                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 353                         i2c->is_segment = true;
 354                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 355                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 356                 } else {
 357                         if (msgs[i].flags & I2C_M_RD)
 358                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 359                                                        msgs[i].len);
 360                         else
 361                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 362                                                         msgs[i].len);
 363                 }
 364                 if (ret < 0)
 365                         break;
 366         }
 367
 368         if (!ret)
 369                 ret = num;
 370
 371         /* Mute DONE and ERROR interrupts */
 372         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 373                     HDMI_IH_MUTE_I2CM_STAT0);
 374
 375         mutex_unlock(&i2c->lock);
 376
 377         return ret;
 378 }
 379
 380 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 381 {
 382         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 383 }
 384
 385 static const struct i2c_algorithm dw_hdmi_algorithm = {
 386         .master_xfer    = dw_hdmi_i2c_xfer,
 387         .functionality  = dw_hdmi_i2c_func,
 388 };
 389
 390 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 391 {
 392         struct i2c_adapter *adap;
 393         struct dw_hdmi_i2c *i2c;
 394         int ret;
 395
 396         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 397         if (!i2c)
 398                 return ERR_PTR(-ENOMEM);
 399
 400         mutex_init(&i2c->lock);
 401         init_completion(&i2c->cmp);
 402
 403         adap = &i2c->adap;
 404         adap->class = I2C_CLASS_DDC;
 405         adap->owner = THIS_MODULE;
 406         adap->dev.parent = hdmi->dev;
 407         adap->algo = &dw_hdmi_algorithm;
 408         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 409         i2c_set_adapdata(adap, hdmi);
 410
 411         ret = i2c_add_adapter(adap);
 412         if (ret) {
 413                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 414                 devm_kfree(hdmi->dev, i2c);
 415                 return ERR_PTR(ret);
 416         }
 417
 418         hdmi->i2c = i2c;
 419
 420         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 421
 422         return adap;
 423 }
 424
 425 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 426                            unsigned int n)
 427 {
 428         /* Must be set/cleared first */
 429         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 430
 431         /* nshift factor = 0 */
 432         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 433
 434         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 435                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 436         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 437         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 438
 439         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 440         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 441         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 442 }
 443
 444 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 445 {
 446         unsigned int n = (128 * freq) / 1000;
 447         unsigned int mult = 1;
 448
 449         while (freq > 48000) {
 450                 mult *= 2;
 451                 freq /= 2;
 452         }
 453
 454         switch (freq) {
 455         case 32000:
 456                 if (pixel_clk == 25175000)
 457                         n = 4576;
 458                 else if (pixel_clk == 27027000)
 459                         n = 4096;
 460                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 461                         n = 11648;
 462                 else
 463                         n = 4096;
 464                 n *= mult;
 465                 break;
 466
 467         case 44100:
 468                 if (pixel_clk == 25175000)
 469                         n = 7007;
 470                 else if (pixel_clk == 74176000)
 471                         n = 17836;
 472                 else if (pixel_clk == 148352000)
 473                         n = 8918;
 474                 else
 475                         n = 6272;
 476                 n *= mult;
 477                 break;
 478
 479         case 48000:
 480                 if (pixel_clk == 25175000)
 481                         n = 6864;
 482                 else if (pixel_clk == 27027000)
 483                         n = 6144;
 484                 else if (pixel_clk == 74176000)
 485                         n = 11648;
 486                 else if (pixel_clk == 148352000)
 487                         n = 5824;
 488                 else
 489                         n = 6144;
 490                 n *= mult;
 491                 break;
 492
 493         default:
 494                 break;
 495         }
 496
 497         return n;
 498 }
 499
 500 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 501         unsigned long pixel_clk, unsigned int sample_rate)
 502 {
 503         unsigned long ftdms = pixel_clk;
 504         unsigned int n, cts;
 505         u64 tmp;
 506
 507         n = hdmi_compute_n(sample_rate, pixel_clk);
 508
 509         /*
 510          * Compute the CTS value from the N value.  Note that CTS and N
 511          * can be up to 20 bits in total, so we need 64-bit math.  Also
 512          * note that our TDMS clock is not fully accurate; it is accurate
 513          * to kHz.  This can introduce an unnecessary remainder in the
 514          * calculation below, so we don't try to warn about that.
 515          */
 516         tmp = (u64)ftdms * n;
 517         do_div(tmp, 128 * sample_rate);
 518         cts = tmp;
 519
 520         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 521                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 522                 n, cts);
 523
 524         spin_lock_irq(&hdmi->audio_lock);
 525         hdmi->audio_n = n;
 526         hdmi->audio_cts = cts;
 527         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 528         spin_unlock_irq(&hdmi->audio_lock);
 529 }
 530
 531 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 532 {
 533         mutex_lock(&hdmi->audio_mutex);
 534         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 535         mutex_unlock(&hdmi->audio_mutex);
 536 }
 537
 538 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 539 {
 540         mutex_lock(&hdmi->audio_mutex);
 541         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 542                                  hdmi->sample_rate);
 543         mutex_unlock(&hdmi->audio_mutex);
 544 }
 545
 546 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 547 {
 548         mutex_lock(&hdmi->audio_mutex);
 549         hdmi->sample_rate = rate;
 550         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 551                                  hdmi->sample_rate);
 552         mutex_unlock(&hdmi->audio_mutex);
 553 }
 554 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 555
 556 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
 557 {
 558         if (enable)
 559                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 560         else
 561                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 562         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
 563 }
 564
 565 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 566 {
 567         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 568 }
 569
 570 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
 571 {
 572         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 573 }
 574
 575 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
 576 {
 577         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 578         hdmi_enable_audio_clk(hdmi, true);
 579 }
 580
 581 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
 582 {
 583         hdmi_enable_audio_clk(hdmi, false);
 584 }
 585
 586 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 587 {
 588         unsigned long flags;
 589
 590         spin_lock_irqsave(&hdmi->audio_lock, flags);
 591         hdmi->audio_enable = true;
 592         if (hdmi->enable_audio)
 593                 hdmi->enable_audio(hdmi);
 594         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 595 }
 596 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 597
 598 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 599 {
 600         unsigned long flags;
 601
 602         spin_lock_irqsave(&hdmi->audio_lock, flags);
 603         hdmi->audio_enable = false;
 604         if (hdmi->disable_audio)
 605                 hdmi->disable_audio(hdmi);
 606         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 607 }
 608 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 609
 610 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 611 {
 612         switch (bus_format) {
 613         case MEDIA_BUS_FMT_RGB888_1X24:
 614         case MEDIA_BUS_FMT_RGB101010_1X30:
 615         case MEDIA_BUS_FMT_RGB121212_1X36:
 616         case MEDIA_BUS_FMT_RGB161616_1X48:
 617                 return true;
 618
 619         default:
 620                 return false;
 621         }
 622 }
 623
 624 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 625 {
 626         switch (bus_format) {
 627         case MEDIA_BUS_FMT_YUV8_1X24:
 628         case MEDIA_BUS_FMT_YUV10_1X30:
 629         case MEDIA_BUS_FMT_YUV12_1X36:
 630         case MEDIA_BUS_FMT_YUV16_1X48:
 631                 return true;
 632
 633         default:
 634                 return false;
 635         }
 636 }
 637
 638 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 639 {
 640         switch (bus_format) {
 641         case MEDIA_BUS_FMT_UYVY8_1X16:
 642         case MEDIA_BUS_FMT_UYVY10_1X20:
 643         case MEDIA_BUS_FMT_UYVY12_1X24:
 644                 return true;
 645
 646         default:
 647                 return false;
 648         }
 649 }
 650
 651 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 652 {
 653         switch (bus_format) {
 654         case MEDIA_BUS_FMT_RGB888_1X24:
 655         case MEDIA_BUS_FMT_YUV8_1X24:
 656         case MEDIA_BUS_FMT_UYVY8_1X16:
 657         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 658                 return 8;
 659
 660         case MEDIA_BUS_FMT_RGB101010_1X30:
 661         case MEDIA_BUS_FMT_YUV10_1X30:
 662         case MEDIA_BUS_FMT_UYVY10_1X20:
 663         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 664                 return 10;
 665
 666         case MEDIA_BUS_FMT_RGB121212_1X36:
 667         case MEDIA_BUS_FMT_YUV12_1X36:
 668         case MEDIA_BUS_FMT_UYVY12_1X24:
 669         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 670                 return 12;
 671
 672         case MEDIA_BUS_FMT_RGB161616_1X48:
 673         case MEDIA_BUS_FMT_YUV16_1X48:
 674         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 675                 return 16;
 676
 677         default:
 678                 return 0;
 679         }
 680 }
 681
 682 /*
 683  * this submodule is responsible for the video data synchronization.
 684  * for example, for RGB 4:4:4 input, the data map is defined as
 685  *                      pin{47~40} <==> R[7:0]
 686  *                      pin{31~24} <==> G[7:0]
 687  *                      pin{15~8}  <==> B[7:0]
 688  */
 689 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 690 {
 691         int color_format = 0;
 692         u8 val;
 693
 694         switch (hdmi->hdmi_data.enc_in_bus_format) {
 695         case MEDIA_BUS_FMT_RGB888_1X24:
 696                 color_format = 0x01;
 697                 break;
 698         case MEDIA_BUS_FMT_RGB101010_1X30:
 699                 color_format = 0x03;
 700                 break;
 701         case MEDIA_BUS_FMT_RGB121212_1X36:
 702                 color_format = 0x05;
 703                 break;
 704         case MEDIA_BUS_FMT_RGB161616_1X48:
 705                 color_format = 0x07;
 706                 break;
 707
 708         case MEDIA_BUS_FMT_YUV8_1X24:
 709         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 710                 color_format = 0x09;
 711                 break;
 712         case MEDIA_BUS_FMT_YUV10_1X30:
 713         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 714                 color_format = 0x0B;
 715                 break;
 716         case MEDIA_BUS_FMT_YUV12_1X36:
 717         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 718                 color_format = 0x0D;
 719                 break;
 720         case MEDIA_BUS_FMT_YUV16_1X48:
 721         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 722                 color_format = 0x0F;
 723                 break;
 724
 725         case MEDIA_BUS_FMT_UYVY8_1X16:
 726                 color_format = 0x16;
 727                 break;
 728         case MEDIA_BUS_FMT_UYVY10_1X20:
 729                 color_format = 0x14;
 730                 break;
 731         case MEDIA_BUS_FMT_UYVY12_1X24:
 732                 color_format = 0x12;
 733                 break;
 734
 735         default:
 736                 return;
 737         }
 738
 739         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 740                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 741                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 742         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 743
 744         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 745         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 746                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 747                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 748         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 749         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 750         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 751         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 752         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 753         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 754         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 755 }
 756
 757 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 758 {
 759         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 760 }
 761
 762 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 763 {
 764         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 765                 return 0;
 766
 767         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 768             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 769                 return 1;
 770
 771         return 0;
 772 }
 773
 774 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 775 {
 776         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 777                 return 0;
 778
 779         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 780             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 781                 return 1;
 782
 783         return 0;
 784 }
 785
 786 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 787 {
 788         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 789         unsigned i;
 790         u32 csc_scale = 1;
 791
 792         if (is_color_space_conversion(hdmi)) {
 793                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
 794                         if (hdmi->hdmi_data.enc_out_encoding ==
 795                                                 V4L2_YCBCR_ENC_601)
 796                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 797                         else
 798                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 799                 } else if (hdmi_bus_fmt_is_rgb(
 800                                         hdmi->hdmi_data.enc_in_bus_format)) {
 801                         if (hdmi->hdmi_data.enc_out_encoding ==
 802                                                 V4L2_YCBCR_ENC_601)
 803                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 804                         else
 805                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 806                         csc_scale = 0;
 807                 }
 808         }
 809
 810         /* The CSC registers are sequential, alternating MSB then LSB */
 811         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 812                 u16 coeff_a = (*csc_coeff)[0][i];
 813                 u16 coeff_b = (*csc_coeff)[1][i];
 814                 u16 coeff_c = (*csc_coeff)[2][i];
 815
 816                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 817                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 818                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 819                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 820                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 821                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 822         }
 823
 824         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 825                   HDMI_CSC_SCALE);
 826 }
 827
 828 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 829 {
 830         int color_depth = 0;
 831         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 832         int decimation = 0;
 833
 834         /* YCC422 interpolation to 444 mode */
 835         if (is_color_space_interpolation(hdmi))
 836                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 837         else if (is_color_space_decimation(hdmi))
 838                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 839
 840         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
 841         case 8:
 842                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 843                 break;
 844         case 10:
 845                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 846                 break;
 847         case 12:
 848                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 849                 break;
 850         case 16:
 851                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 852                 break;
 853
 854         default:
 855                 return;
 856         }
 857
 858         /* Configure the CSC registers */
 859         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 860         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 861                   HDMI_CSC_SCALE);
 862
 863         dw_hdmi_update_csc_coeffs(hdmi);
 864 }
 865
 866 /*
 867  * HDMI video packetizer is used to packetize the data.
 868  * for example, if input is YCC422 mode or repeater is used,
 869  * data should be repacked this module can be bypassed.
 870  */
 871 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 872 {
 873         unsigned int color_depth = 0;
 874         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 875         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 876         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 877         u8 val, vp_conf;
 878
 879         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 880             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
 881                 switch (hdmi_bus_fmt_color_depth(
 882                                         hdmi->hdmi_data.enc_out_bus_format)) {
 883                 case 8:
 884                         color_depth = 4;
 885                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 886                         break;
 887                 case 10:
 888                         color_depth = 5;
 889                         break;
 890                 case 12:
 891                         color_depth = 6;
 892                         break;
 893                 case 16:
 894                         color_depth = 7;
 895                         break;
 896                 default:
 897                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 898                 }
 899         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
 900                 switch (hdmi_bus_fmt_color_depth(
 901                                         hdmi->hdmi_data.enc_out_bus_format)) {
 902                 case 0:
 903                 case 8:
 904                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 905                         break;
 906                 case 10:
 907                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 908                         break;
 909                 case 12:
 910                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 911                         break;
 912
 913                 default:
 914                         return;
 915                 }
 916                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 917         } else {
 918                 return;
 919         }
 920
 921         /* set the packetizer registers */
 922         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 923                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 924                 ((hdmi_data->pix_repet_factor <<
 925                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 926                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 927         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 928
 929         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 930                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 931
 932         /* Data from pixel repeater block */
 933         if (hdmi_data->pix_repet_factor > 1) {
 934                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 935                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 936         } else { /* data from packetizer block */
 937                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 938                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 939         }
 940
 941         hdmi_modb(hdmi, vp_conf,
 942                   HDMI_VP_CONF_PR_EN_MASK |
 943                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 944
 945         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 946                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 947
 948         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 949
 950         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 951                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 952                           HDMI_VP_CONF_PP_EN_ENABLE |
 953                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 954         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 955                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 956                           HDMI_VP_CONF_PP_EN_DISABLE |
 957                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 958         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 959                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 960                           HDMI_VP_CONF_PP_EN_DISABLE |
 961                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 962         } else {
 963                 return;
 964         }
 965
 966         hdmi_modb(hdmi, vp_conf,
 967                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 968                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 969
 970         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 971                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 972                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 973                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 974
 975         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 976                   HDMI_VP_CONF);
 977 }
 978
 979 /* -----------------------------------------------------------------------------
 980  * Synopsys PHY Handling
 981  */
 982
 983 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 984                                        unsigned char bit)
 985 {
 986         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 987                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 988 }
 989
 990 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 991 {
 992         u32 val;
 993
 994         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 995                 if (msec-- == 0)
 996                         return false;
 997                 udelay(1000);
 998         }
 999         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1000
1001         return true;
1002 }
1003
1004 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1005                            unsigned char addr)
1006 {
1007         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1008         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1009         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1010                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1011         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1012                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1013         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1014                     HDMI_PHY_I2CM_OPERATION_ADDR);
1015         hdmi_phy_wait_i2c_done(hdmi, 1000);
1016 }
1017 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1018
1019 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1020 {
1021         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1022                          HDMI_PHY_CONF0_PDZ_OFFSET,
1023                          HDMI_PHY_CONF0_PDZ_MASK);
1024 }
1025
1026 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1027 {
1028         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1029                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1030                          HDMI_PHY_CONF0_ENTMDS_MASK);
1031 }
1032
1033 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1034 {
1035         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1036                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1037                          HDMI_PHY_CONF0_SVSRET_MASK);
1038 }
1039
1040 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1041 {
1042         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1043                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1044                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1045 }
1046
1047 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1048 {
1049         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1050                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1051                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1052 }
1053
1054 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1055 {
1056         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1057                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1058                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1059 }
1060
1061 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1062 {
1063         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1064                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1065                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1066 }
1067
1068 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1069 {
1070         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1071         unsigned int i;
1072         u16 val;
1073
1074         if (phy->gen == 1) {
1075                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1076                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1077                 return;
1078         }
1079
1080         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1081
1082         /*
1083          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1084          * to low power mode.
1085          */
1086         for (i = 0; i < 5; ++i) {
1087                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1088                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1089                         break;
1090
1091                 usleep_range(1000, 2000);
1092         }
1093
1094         if (val & HDMI_PHY_TX_PHY_LOCK)
1095                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1096         else
1097                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1098
1099         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1100 }
1101
1102 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1103 {
1104         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1105         unsigned int i;
1106         u8 val;
1107
1108         if (phy->gen == 1) {
1109                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1110
1111                 /* Toggle TMDS enable. */
1112                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1113                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1114                 return 0;
1115         }
1116
1117         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1118         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1119
1120         /* Wait for PHY PLL lock */
1121         for (i = 0; i < 5; ++i) {
1122                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1123                 if (val)
1124                         break;
1125
1126                 usleep_range(1000, 2000);
1127         }
1128
1129         if (!val) {
1130                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1131                 return -ETIMEDOUT;
1132         }
1133
1134         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1135         return 0;
1136 }
1137
1138 /*
1139  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1140  * information the DWC MHL PHY has the same register layout and is thus also
1141  * supported by this function.
1142  */
1143 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1144                 const struct dw_hdmi_plat_data *pdata,
1145                 unsigned long mpixelclock)
1146 {
1147         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1148         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1149         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1150
1151         /* PLL/MPLL Cfg - always match on final entry */
1152         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1153                 if (mpixelclock <= mpll_config->mpixelclock)
1154                         break;
1155
1156         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1157                 if (mpixelclock <= curr_ctrl->mpixelclock)
1158                         break;
1159
1160         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1161                 if (mpixelclock <= phy_config->mpixelclock)
1162                         break;
1163
1164         if (mpll_config->mpixelclock == ~0UL ||
1165             curr_ctrl->mpixelclock == ~0UL ||
1166             phy_config->mpixelclock == ~0UL)
1167                 return -EINVAL;
1168
1169         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1170                               HDMI_3D_TX_PHY_CPCE_CTRL);
1171         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1172                               HDMI_3D_TX_PHY_GMPCTRL);
1173         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1174                               HDMI_3D_TX_PHY_CURRCTRL);
1175
1176         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1177         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1178                               HDMI_3D_TX_PHY_MSM_CTRL);
1179
1180         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1181         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1182                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1183         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1184                               HDMI_3D_TX_PHY_VLEVCTRL);
1185
1186         /* Override and disable clock termination. */
1187         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1188                               HDMI_3D_TX_PHY_CKCALCTRL);
1189
1190         return 0;
1191 }
1192
1193 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1194 {
1195         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1196         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1197         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1198         int ret;
1199
1200         dw_hdmi_phy_power_off(hdmi);
1201
1202         /* Leave low power consumption mode by asserting SVSRET. */
1203         if (phy->has_svsret)
1204                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1205
1206         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1207         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1208         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1209
1210         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1211
1212         hdmi_phy_test_clear(hdmi, 1);
1213         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1214                     HDMI_PHY_I2CM_SLAVE_ADDR);
1215         hdmi_phy_test_clear(hdmi, 0);
1216
1217         /* Write to the PHY as configured by the platform */
1218         if (pdata->configure_phy)
1219                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1220         else
1221                 ret = phy->configure(hdmi, pdata, mpixelclock);
1222         if (ret) {
1223                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1224                         mpixelclock);
1225                 return ret;
1226         }
1227
1228         return dw_hdmi_phy_power_on(hdmi);
1229 }
1230
1231 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1232                             struct drm_display_mode *mode)
1233 {
1234         int i, ret;
1235
1236         /* HDMI Phy spec says to do the phy initialization sequence twice */
1237         for (i = 0; i < 2; i++) {
1238                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1239                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1240
1241                 ret = hdmi_phy_configure(hdmi);
1242                 if (ret)
1243                         return ret;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1250 {
1251         dw_hdmi_phy_power_off(hdmi);
1252 }
1253
1254 static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1255                                                       void *data)
1256 {
1257         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1258                 connector_status_connected : connector_status_disconnected;
1259 }
1260
1261 static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1262                                    bool force, bool disabled, bool rxsense)
1263 {
1264         u8 old_mask = hdmi->phy_mask;
1265
1266         if (force || disabled || !rxsense)
1267                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1268         else
1269                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1270
1271         if (old_mask != hdmi->phy_mask)
1272                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1273 }
1274
1275 static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1276 {
1277         /*
1278          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1279          * any pending interrupt.
1280          */
1281         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1282         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1283                     HDMI_IH_PHY_STAT0);
1284
1285         /* Enable cable hot plug irq. */
1286         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1287
1288         /* Clear and unmute interrupts. */
1289         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1290                     HDMI_IH_PHY_STAT0);
1291         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1292                     HDMI_IH_MUTE_PHY_STAT0);
1293 }
1294
1295 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1296         .init = dw_hdmi_phy_init,
1297         .disable = dw_hdmi_phy_disable,
1298         .read_hpd = dw_hdmi_phy_read_hpd,
1299         .update_hpd = dw_hdmi_phy_update_hpd,
1300         .setup_hpd = dw_hdmi_phy_setup_hpd,
1301 };
1302
1303 /* -----------------------------------------------------------------------------
1304  * HDMI TX Setup
1305  */
1306
1307 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1308 {
1309         u8 de;
1310
1311         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1312                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1313         else
1314                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1315
1316         /* disable rx detect */
1317         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1318                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1319
1320         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1321
1322         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1323                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1324 }
1325
1326 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1327 {
1328         struct hdmi_avi_infoframe frame;
1329         u8 val;
1330
1331         /* Initialise info frame from DRM mode */
1332         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1333
1334         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1335                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1336         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1337                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1338         else
1339                 frame.colorspace = HDMI_COLORSPACE_RGB;
1340
1341         /* Set up colorimetry */
1342         switch (hdmi->hdmi_data.enc_out_encoding) {
1343         case V4L2_YCBCR_ENC_601:
1344                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1345                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1346                 else
1347                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1348                 frame.extended_colorimetry =
1349                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1350                 break;
1351         case V4L2_YCBCR_ENC_709:
1352                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1353                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1354                 else
1355                         frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1356                 frame.extended_colorimetry =
1357                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1358                 break;
1359         default: /* Carries no data */
1360                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1361                 frame.extended_colorimetry =
1362                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1363                 break;
1364         }
1365
1366         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1367
1368         /*
1369          * The Designware IP uses a different byte format from standard
1370          * AVI info frames, though generally the bits are in the correct
1371          * bytes.
1372          */
1373
1374         /*
1375          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1376          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1377          * bit 6 rather than 4.
1378          */
1379         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1380         if (frame.active_aspect & 15)
1381                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1382         if (frame.top_bar || frame.bottom_bar)
1383                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1384         if (frame.left_bar || frame.right_bar)
1385                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1386         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1387
1388         /* AVI data byte 2 differences: none */
1389         val = ((frame.colorimetry & 0x3) << 6) |
1390               ((frame.picture_aspect & 0x3) << 4) |
1391               (frame.active_aspect & 0xf);
1392         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1393
1394         /* AVI data byte 3 differences: none */
1395         val = ((frame.extended_colorimetry & 0x7) << 4) |
1396               ((frame.quantization_range & 0x3) << 2) |
1397               (frame.nups & 0x3);
1398         if (frame.itc)
1399                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1400         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1401
1402         /* AVI data byte 4 differences: none */
1403         val = frame.video_code & 0x7f;
1404         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1405
1406         /* AVI Data Byte 5- set up input and output pixel repetition */
1407         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1408                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1409                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1410                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1411                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1412                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1413         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1414
1415         /*
1416          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1417          * ycc range in bits 2,3 rather than 6,7
1418          */
1419         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1420               (frame.content_type & 0x3);
1421         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1422
1423         /* AVI Data Bytes 6-13 */
1424         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1425         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1426         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1427         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1428         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1429         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1430         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1431         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1432 }
1433
1434 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1435                                                  struct drm_display_mode *mode)
1436 {
1437         struct hdmi_vendor_infoframe frame;
1438         u8 buffer[10];
1439         ssize_t err;
1440
1441         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1442         if (err < 0)
1443                 /*
1444                  * Going into that statement does not means vendor infoframe
1445                  * fails. It just informed us that vendor infoframe is not
1446                  * needed for the selected mode. Only 4k or stereoscopic 3D
1447                  * mode requires vendor infoframe. So just simply return.
1448                  */
1449                 return;
1450
1451         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1452         if (err < 0) {
1453                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1454                         err);
1455                 return;
1456         }
1457         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1458                         HDMI_FC_DATAUTO0_VSD_MASK);
1459
1460         /* Set the length of HDMI vendor specific InfoFrame payload */
1461         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1462
1463         /* Set 24bit IEEE Registration Identifier */
1464         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1465         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1466         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1467
1468         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1469         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1470         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1471
1472         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1473                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1474
1475         /* Packet frame interpolation */
1476         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1477
1478         /* Auto packets per frame and line spacing */
1479         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1480
1481         /* Configures the Frame Composer On RDRB mode */
1482         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1483                         HDMI_FC_DATAUTO0_VSD_MASK);
1484 }
1485
1486 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1487                              const struct drm_display_mode *mode)
1488 {
1489         u8 inv_val;
1490         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1491         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1492         unsigned int vdisplay;
1493
1494         vmode->mpixelclock = mode->clock * 1000;
1495
1496         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1497
1498         /* Set up HDMI_FC_INVIDCONF */
1499         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1500                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1501                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1502
1503         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1504                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1505                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1506
1507         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1508                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1509                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1510
1511         inv_val |= (vmode->mdataenablepolarity ?
1512                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1513                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1514
1515         if (hdmi->vic == 39)
1516                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1517         else
1518                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1519                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1520                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1521
1522         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1523                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1524                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1525
1526         inv_val |= hdmi->sink_is_hdmi ?
1527                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1528                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1529
1530         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1531
1532         vdisplay = mode->vdisplay;
1533         vblank = mode->vtotal - mode->vdisplay;
1534         v_de_vs = mode->vsync_start - mode->vdisplay;
1535         vsync_len = mode->vsync_end - mode->vsync_start;
1536
1537         /*
1538          * When we're setting an interlaced mode, we need
1539          * to adjust the vertical timing to suit.
1540          */
1541         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1542                 vdisplay /= 2;
1543                 vblank /= 2;
1544                 v_de_vs /= 2;
1545                 vsync_len /= 2;
1546         }
1547
1548         /* Set up horizontal active pixel width */
1549         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1550         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1551
1552         /* Set up vertical active lines */
1553         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1554         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1555
1556         /* Set up horizontal blanking pixel region width */
1557         hblank = mode->htotal - mode->hdisplay;
1558         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1559         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1560
1561         /* Set up vertical blanking pixel region width */
1562         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1563
1564         /* Set up HSYNC active edge delay width (in pixel clks) */
1565         h_de_hs = mode->hsync_start - mode->hdisplay;
1566         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1567         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1568
1569         /* Set up VSYNC active edge delay (in lines) */
1570         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1571
1572         /* Set up HSYNC active pulse width (in pixel clks) */
1573         hsync_len = mode->hsync_end - mode->hsync_start;
1574         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1575         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1576
1577         /* Set up VSYNC active edge delay (in lines) */
1578         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1579 }
1580
1581 /* HDMI Initialization Step B.4 */
1582 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1583 {
1584         /* control period minimum duration */
1585         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1586         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1587         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1588
1589         /* Set to fill TMDS data channels */
1590         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1591         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1592         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1593
1594         /* Enable pixel clock and tmds data path */
1595         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1596                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1597                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1598                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1599                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1600         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1601         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1602
1603         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1604         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1605
1606         /* Enable csc path */
1607         if (is_color_space_conversion(hdmi)) {
1608                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1609                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1610         }
1611
1612         /* Enable color space conversion if needed */
1613         if (is_color_space_conversion(hdmi))
1614                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1615                             HDMI_MC_FLOWCTRL);
1616         else
1617                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1618                             HDMI_MC_FLOWCTRL);
1619 }
1620
1621 /* Workaround to clear the overflow condition */
1622 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1623 {
1624         unsigned int count;
1625         unsigned int i;
1626         u8 val;
1627
1628         /*
1629          * Under some circumstances the Frame Composer arithmetic unit can miss
1630          * an FC register write due to being busy processing the previous one.
1631          * The issue can be worked around by issuing a TMDS software reset and
1632          * then write one of the FC registers several times.
1633          *
1634          * The number of iterations matters and depends on the HDMI TX revision
1635          * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1636          * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1637          * 4 and 1 iterations respectively.
1638          */
1639
1640         switch (hdmi->version) {
1641         case 0x130a:
1642                 count = 4;
1643                 break;
1644         case 0x131a:
1645                 count = 1;
1646                 break;
1647         default:
1648                 return;
1649         }
1650
1651         /* TMDS software reset */
1652         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1653
1654         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1655         for (i = 0; i < count; i++)
1656                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1657 }
1658
1659 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1660 {
1661         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1662         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1663 }
1664
1665 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1666 {
1667         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1668                     HDMI_IH_MUTE_FC_STAT2);
1669 }
1670
1671 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1672 {
1673         int ret;
1674
1675         hdmi_disable_overflow_interrupts(hdmi);
1676
1677         hdmi->vic = drm_match_cea_mode(mode);
1678
1679         if (!hdmi->vic) {
1680                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1681         } else {
1682                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1683         }
1684
1685         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1686             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1687             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1688             (hdmi->vic == 17) || (hdmi->vic == 18))
1689                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1690         else
1691                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1692
1693         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1694         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1695
1696         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1697         if (hdmi->plat_data->input_bus_format)
1698                 hdmi->hdmi_data.enc_in_bus_format =
1699                         hdmi->plat_data->input_bus_format;
1700         else
1701                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1702
1703         /* TOFIX: Get input encoding from plat data or fallback to none */
1704         if (hdmi->plat_data->input_bus_encoding)
1705                 hdmi->hdmi_data.enc_in_encoding =
1706                         hdmi->plat_data->input_bus_encoding;
1707         else
1708                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1709
1710         /* TOFIX: Default to RGB888 output format */
1711         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1712
1713         hdmi->hdmi_data.pix_repet_factor = 0;
1714         hdmi->hdmi_data.hdcp_enable = 0;
1715         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1716
1717         /* HDMI Initialization Step B.1 */
1718         hdmi_av_composer(hdmi, mode);
1719
1720         /* HDMI Initializateion Step B.2 */
1721         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1722         if (ret)
1723                 return ret;
1724         hdmi->phy.enabled = true;
1725
1726         /* HDMI Initialization Step B.3 */
1727         dw_hdmi_enable_video_path(hdmi);
1728
1729         if (hdmi->sink_has_audio) {
1730                 dev_dbg(hdmi->dev, "sink has audio support\n");
1731
1732                 /* HDMI Initialization Step E - Configure audio */
1733                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1734                 hdmi_enable_audio_clk(hdmi, true);
1735         }
1736
1737         /* not for DVI mode */
1738         if (hdmi->sink_is_hdmi) {
1739                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1740
1741                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1742                 hdmi_config_AVI(hdmi, mode);
1743                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1744         } else {
1745                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1746         }
1747
1748         hdmi_video_packetize(hdmi);
1749         hdmi_video_csc(hdmi);
1750         hdmi_video_sample(hdmi);
1751         hdmi_tx_hdcp_config(hdmi);
1752
1753         dw_hdmi_clear_overflow(hdmi);
1754         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1755                 hdmi_enable_overflow_interrupts(hdmi);
1756
1757         return 0;
1758 }
1759
1760 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1761 {
1762         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1763                     HDMI_PHY_I2CM_INT_ADDR);
1764
1765         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1766                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1767                     HDMI_PHY_I2CM_CTLINT_ADDR);
1768 }
1769
1770 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1771 {
1772         u8 ih_mute;
1773
1774         /*
1775          * Boot up defaults are:
1776          * HDMI_IH_MUTE   = 0x03 (disabled)
1777          * HDMI_IH_MUTE_* = 0x00 (enabled)
1778          *
1779          * Disable top level interrupt bits in HDMI block
1780          */
1781         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1782                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1783                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1784
1785         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1786
1787         /* by default mask all interrupts */
1788         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1789         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1790         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1791         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1792         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1793         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1794         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1795         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1796         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1797         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1798         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1799         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1800         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1801         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1802
1803         /* Disable interrupts in the IH_MUTE_* registers */
1804         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1805         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1806         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1807         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1808         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1809         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1810         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1811         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1812         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1813         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1814
1815         /* Enable top level interrupt bits in HDMI block */
1816         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1817                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1818         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1819 }
1820
1821 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1822 {
1823         hdmi->bridge_is_on = true;
1824         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1825 }
1826
1827 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1828 {
1829         if (hdmi->phy.enabled) {
1830                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1831                 hdmi->phy.enabled = false;
1832         }
1833
1834         hdmi->bridge_is_on = false;
1835 }
1836
1837 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1838 {
1839         int force = hdmi->force;
1840
1841         if (hdmi->disabled) {
1842                 force = DRM_FORCE_OFF;
1843         } else if (force == DRM_FORCE_UNSPECIFIED) {
1844                 if (hdmi->rxsense)
1845                         force = DRM_FORCE_ON;
1846                 else
1847                         force = DRM_FORCE_OFF;
1848         }
1849
1850         if (force == DRM_FORCE_OFF) {
1851                 if (hdmi->bridge_is_on)
1852                         dw_hdmi_poweroff(hdmi);
1853         } else {
1854                 if (!hdmi->bridge_is_on)
1855                         dw_hdmi_poweron(hdmi);
1856         }
1857 }
1858
1859 /*
1860  * Adjust the detection of RXSENSE according to whether we have a forced
1861  * connection mode enabled, or whether we have been disabled.  There is
1862  * no point processing RXSENSE interrupts if we have a forced connection
1863  * state, or DRM has us disabled.
1864  *
1865  * We also disable rxsense interrupts when we think we're disconnected
1866  * to avoid floating TDMS signals giving false rxsense interrupts.
1867  *
1868  * Note: we still need to listen for HPD interrupts even when DRM has us
1869  * disabled so that we can detect a connect event.
1870  */
1871 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1872 {
1873         if (hdmi->phy.ops->update_hpd)
1874                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
1875                                           hdmi->force, hdmi->disabled,
1876                                           hdmi->rxsense);
1877 }
1878
1879 static enum drm_connector_status
1880 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1881 {
1882         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1883                                              connector);
1884
1885         mutex_lock(&hdmi->mutex);
1886         hdmi->force = DRM_FORCE_UNSPECIFIED;
1887         dw_hdmi_update_power(hdmi);
1888         dw_hdmi_update_phy_mask(hdmi);
1889         mutex_unlock(&hdmi->mutex);
1890
1891         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1892 }
1893
1894 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1895 {
1896         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1897                                              connector);
1898         struct edid *edid;
1899         int ret = 0;
1900
1901         if (!hdmi->ddc)
1902                 return 0;
1903
1904         edid = drm_get_edid(connector, hdmi->ddc);
1905         if (edid) {
1906                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1907                         edid->width_cm, edid->height_cm);
1908
1909                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1910                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1911                 drm_mode_connector_update_edid_property(connector, edid);
1912                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1913                 ret = drm_add_edid_modes(connector, edid);
1914                 /* Store the ELD */
1915                 drm_edid_to_eld(connector, edid);
1916                 kfree(edid);
1917         } else {
1918                 dev_dbg(hdmi->dev, "failed to get edid\n");
1919         }
1920
1921         return ret;
1922 }
1923
1924 static void dw_hdmi_connector_force(struct drm_connector *connector)
1925 {
1926         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1927                                              connector);
1928
1929         mutex_lock(&hdmi->mutex);
1930         hdmi->force = connector->force;
1931         dw_hdmi_update_power(hdmi);
1932         dw_hdmi_update_phy_mask(hdmi);
1933         mutex_unlock(&hdmi->mutex);
1934 }
1935
1936 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1937         .fill_modes = drm_helper_probe_single_connector_modes,
1938         .detect = dw_hdmi_connector_detect,
1939         .destroy = drm_connector_cleanup,
1940         .force = dw_hdmi_connector_force,
1941         .reset = drm_atomic_helper_connector_reset,
1942         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1943         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1944 };
1945
1946 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1947         .get_modes = dw_hdmi_connector_get_modes,
1948         .best_encoder = drm_atomic_helper_best_encoder,
1949 };
1950
1951 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1952 {
1953         struct dw_hdmi *hdmi = bridge->driver_private;
1954         struct drm_encoder *encoder = bridge->encoder;
1955         struct drm_connector *connector = &hdmi->connector;
1956
1957         connector->interlace_allowed = 1;
1958         connector->polled = DRM_CONNECTOR_POLL_HPD;
1959
1960         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1961
1962         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1963                            DRM_MODE_CONNECTOR_HDMIA);
1964
1965         drm_mode_connector_attach_encoder(connector, encoder);
1966
1967         return 0;
1968 }
1969
1970 static enum drm_mode_status
1971 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1972                           const struct drm_display_mode *mode)
1973 {
1974         struct dw_hdmi *hdmi = bridge->driver_private;
1975         struct drm_connector *connector = &hdmi->connector;
1976         enum drm_mode_status mode_status = MODE_OK;
1977
1978         /* We don't support double-clocked modes */
1979         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1980                 return MODE_BAD;
1981
1982         if (hdmi->plat_data->mode_valid)
1983                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1984
1985         return mode_status;
1986 }
1987
1988 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1989                                     struct drm_display_mode *orig_mode,
1990                                     struct drm_display_mode *mode)
1991 {
1992         struct dw_hdmi *hdmi = bridge->driver_private;
1993
1994         mutex_lock(&hdmi->mutex);
1995
1996         /* Store the display mode for plugin/DKMS poweron events */
1997         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1998
1999         mutex_unlock(&hdmi->mutex);
2000 }
2001
2002 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2003 {
2004         struct dw_hdmi *hdmi = bridge->driver_private;
2005
2006         mutex_lock(&hdmi->mutex);
2007         hdmi->disabled = true;
2008         dw_hdmi_update_power(hdmi);
2009         dw_hdmi_update_phy_mask(hdmi);
2010         mutex_unlock(&hdmi->mutex);
2011 }
2012
2013 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2014 {
2015         struct dw_hdmi *hdmi = bridge->driver_private;
2016
2017         mutex_lock(&hdmi->mutex);
2018         hdmi->disabled = false;
2019         dw_hdmi_update_power(hdmi);
2020         dw_hdmi_update_phy_mask(hdmi);
2021         mutex_unlock(&hdmi->mutex);
2022 }
2023
2024 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2025         .attach = dw_hdmi_bridge_attach,
2026         .enable = dw_hdmi_bridge_enable,
2027         .disable = dw_hdmi_bridge_disable,
2028         .mode_set = dw_hdmi_bridge_mode_set,
2029         .mode_valid = dw_hdmi_bridge_mode_valid,
2030 };
2031
2032 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2033 {
2034         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2035         unsigned int stat;
2036
2037         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2038         if (!stat)
2039                 return IRQ_NONE;
2040
2041         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2042
2043         i2c->stat = stat;
2044
2045         complete(&i2c->cmp);
2046
2047         return IRQ_HANDLED;
2048 }
2049
2050 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2051 {
2052         struct dw_hdmi *hdmi = dev_id;
2053         u8 intr_stat;
2054         irqreturn_t ret = IRQ_NONE;
2055
2056         if (hdmi->i2c)
2057                 ret = dw_hdmi_i2c_irq(hdmi);
2058
2059         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2060         if (intr_stat) {
2061                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2062                 return IRQ_WAKE_THREAD;
2063         }
2064
2065         return ret;
2066 }
2067
2068 void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2069 {
2070         mutex_lock(&hdmi->mutex);
2071
2072         if (!hdmi->force) {
2073                 /*
2074                  * If the RX sense status indicates we're disconnected,
2075                  * clear the software rxsense status.
2076                  */
2077                 if (!rx_sense)
2078                         hdmi->rxsense = false;
2079
2080                 /*
2081                  * Only set the software rxsense status when both
2082                  * rxsense and hpd indicates we're connected.
2083                  * This avoids what seems to be bad behaviour in
2084                  * at least iMX6S versions of the phy.
2085                  */
2086                 if (hpd)
2087                         hdmi->rxsense = true;
2088
2089                 dw_hdmi_update_power(hdmi);
2090                 dw_hdmi_update_phy_mask(hdmi);
2091         }
2092         mutex_unlock(&hdmi->mutex);
2093 }
2094
2095 void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense)
2096 {
2097         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2098
2099         __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense);
2100 }
2101 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2102
2103 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2104 {
2105         struct dw_hdmi *hdmi = dev_id;
2106         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2107
2108         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2109         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2110         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2111
2112         phy_pol_mask = 0;
2113         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2114                 phy_pol_mask |= HDMI_PHY_HPD;
2115         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2116                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2117         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2118                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2119         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2120                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2121         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2122                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2123
2124         if (phy_pol_mask)
2125                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2126
2127         /*
2128          * RX sense tells us whether the TDMS transmitters are detecting
2129          * load - in other words, there's something listening on the
2130          * other end of the link.  Use this to decide whether we should
2131          * power on the phy as HPD may be toggled by the sink to merely
2132          * ask the source to re-read the EDID.
2133          */
2134         if (intr_stat &
2135             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2136                 __dw_hdmi_setup_rx_sense(hdmi,
2137                                          phy_stat & HDMI_PHY_HPD,
2138                                          phy_stat & HDMI_PHY_RX_SENSE);
2139
2140                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2141                         cec_notifier_set_phys_addr(hdmi->cec_notifier,
2142                                                    CEC_PHYS_ADDR_INVALID);
2143         }
2144
2145         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2146                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2147                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2148                 if (hdmi->bridge.dev)
2149                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2150         }
2151
2152         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2153         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2154                     HDMI_IH_MUTE_PHY_STAT0);
2155
2156         return IRQ_HANDLED;
2157 }
2158
2159 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2160         {
2161                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2162                 .name = "DWC HDMI TX PHY",
2163                 .gen = 1,
2164         }, {
2165                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2166                 .name = "DWC MHL PHY + HEAC PHY",
2167                 .gen = 2,
2168                 .has_svsret = true,
2169                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2170         }, {
2171                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2172                 .name = "DWC MHL PHY",
2173                 .gen = 2,
2174                 .has_svsret = true,
2175                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2176         }, {
2177                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2178                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2179                 .gen = 2,
2180                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2181         }, {
2182                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2183                 .name = "DWC HDMI 3D TX PHY",
2184                 .gen = 2,
2185                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2186         }, {
2187                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2188                 .name = "DWC HDMI 2.0 TX PHY",
2189                 .gen = 2,
2190                 .has_svsret = true,
2191                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2192         }, {
2193                 .type = DW_HDMI_PHY_VENDOR_PHY,
2194                 .name = "Vendor PHY",
2195         }
2196 };
2197
2198 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2199 {
2200         unsigned int i;
2201         u8 phy_type;
2202
2203         phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2204
2205         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2206                 /* Vendor PHYs require support from the glue layer. */
2207                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2208                         dev_err(hdmi->dev,
2209                                 "Vendor HDMI PHY not supported by glue layer\n");
2210                         return -ENODEV;
2211                 }
2212
2213                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2214                 hdmi->phy.data = hdmi->plat_data->phy_data;
2215                 hdmi->phy.name = hdmi->plat_data->phy_name;
2216                 return 0;
2217         }
2218
2219         /* Synopsys PHYs are handled internally. */
2220         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2221                 if (dw_hdmi_phys[i].type == phy_type) {
2222                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2223                         hdmi->phy.name = dw_hdmi_phys[i].name;
2224                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2225
2226                         if (!dw_hdmi_phys[i].configure &&
2227                             !hdmi->plat_data->configure_phy) {
2228                                 dev_err(hdmi->dev, "%s requires platform support\n",
2229                                         hdmi->phy.name);
2230                                 return -ENODEV;
2231                         }
2232
2233                         return 0;
2234                 }
2235         }
2236
2237         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2238         return -ENODEV;
2239 }
2240
2241 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2242 {
2243         mutex_lock(&hdmi->mutex);
2244         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2245         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2246         mutex_unlock(&hdmi->mutex);
2247 }
2248
2249 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2250 {
2251         mutex_lock(&hdmi->mutex);
2252         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2253         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2254         mutex_unlock(&hdmi->mutex);
2255 }
2256
2257 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2258         .write = hdmi_writeb,
2259         .read = hdmi_readb,
2260         .enable = dw_hdmi_cec_enable,
2261         .disable = dw_hdmi_cec_disable,
2262 };
2263
2264 static const struct regmap_config hdmi_regmap_8bit_config = {
2265         .reg_bits       = 32,
2266         .val_bits       = 8,
2267         .reg_stride     = 1,
2268         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2269 };
2270
2271 static const struct regmap_config hdmi_regmap_32bit_config = {
2272         .reg_bits       = 32,
2273         .val_bits       = 32,
2274         .reg_stride     = 4,
2275         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2276 };
2277
2278 static struct dw_hdmi *
2279 __dw_hdmi_probe(struct platform_device *pdev,
2280                 const struct dw_hdmi_plat_data *plat_data)
2281 {
2282         struct device *dev = &pdev->dev;
2283         struct device_node *np = dev->of_node;
2284         struct platform_device_info pdevinfo;
2285         struct device_node *ddc_node;
2286         struct dw_hdmi_cec_data cec;
2287         struct dw_hdmi *hdmi;
2288         struct resource *iores = NULL;
2289         int irq;
2290         int ret;
2291         u32 val = 1;
2292         u8 prod_id0;
2293         u8 prod_id1;
2294         u8 config0;
2295         u8 config3;
2296
2297         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2298         if (!hdmi)
2299                 return ERR_PTR(-ENOMEM);
2300
2301         hdmi->plat_data = plat_data;
2302         hdmi->dev = dev;
2303         hdmi->sample_rate = 48000;
2304         hdmi->disabled = true;
2305         hdmi->rxsense = true;
2306         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2307         hdmi->mc_clkdis = 0x7f;
2308
2309         mutex_init(&hdmi->mutex);
2310         mutex_init(&hdmi->audio_mutex);
2311         spin_lock_init(&hdmi->audio_lock);
2312
2313         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2314         if (ddc_node) {
2315                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2316                 of_node_put(ddc_node);
2317                 if (!hdmi->ddc) {
2318                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2319                         return ERR_PTR(-EPROBE_DEFER);
2320                 }
2321
2322         } else {
2323                 dev_dbg(hdmi->dev, "no ddc property found\n");
2324         }
2325
2326         if (!plat_data->regm) {
2327                 const struct regmap_config *reg_config;
2328
2329                 of_property_read_u32(np, "reg-io-width", &val);
2330                 switch (val) {
2331                 case 4:
2332                         reg_config = &hdmi_regmap_32bit_config;
2333                         hdmi->reg_shift = 2;
2334                         break;
2335                 case 1:
2336                         reg_config = &hdmi_regmap_8bit_config;
2337                         break;
2338                 default:
2339                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2340                         return ERR_PTR(-EINVAL);
2341                 }
2342
2343                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2344                 hdmi->regs = devm_ioremap_resource(dev, iores);
2345                 if (IS_ERR(hdmi->regs)) {
2346                         ret = PTR_ERR(hdmi->regs);
2347                         goto err_res;
2348                 }
2349
2350                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2351                 if (IS_ERR(hdmi->regm)) {
2352                         dev_err(dev, "Failed to configure regmap\n");
2353                         ret = PTR_ERR(hdmi->regm);
2354                         goto err_res;
2355                 }
2356         } else {
2357                 hdmi->regm = plat_data->regm;
2358         }
2359
2360         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2361         if (IS_ERR(hdmi->isfr_clk)) {
2362                 ret = PTR_ERR(hdmi->isfr_clk);
2363                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2364                 goto err_res;
2365         }
2366
2367         ret = clk_prepare_enable(hdmi->isfr_clk);
2368         if (ret) {
2369                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2370                 goto err_res;
2371         }
2372
2373         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2374         if (IS_ERR(hdmi->iahb_clk)) {
2375                 ret = PTR_ERR(hdmi->iahb_clk);
2376                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2377                 goto err_isfr;
2378         }
2379
2380         ret = clk_prepare_enable(hdmi->iahb_clk);
2381         if (ret) {
2382                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2383                 goto err_isfr;
2384         }
2385
2386         hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2387         if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2388                 hdmi->cec_clk = NULL;
2389         } else if (IS_ERR(hdmi->cec_clk)) {
2390                 ret = PTR_ERR(hdmi->cec_clk);
2391                 if (ret != -EPROBE_DEFER)
2392                         dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2393                                 ret);
2394
2395                 hdmi->cec_clk = NULL;
2396                 goto err_iahb;
2397         } else {
2398                 ret = clk_prepare_enable(hdmi->cec_clk);
2399                 if (ret) {
2400                         dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2401                                 ret);
2402                         goto err_iahb;
2403                 }
2404         }
2405
2406         /* Product and revision IDs */
2407         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2408                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2409         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2410         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2411
2412         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2413             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2414                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2415                         hdmi->version, prod_id0, prod_id1);
2416                 ret = -ENODEV;
2417                 goto err_iahb;
2418         }
2419
2420         ret = dw_hdmi_detect_phy(hdmi);
2421         if (ret < 0)
2422                 goto err_iahb;
2423
2424         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2425                  hdmi->version >> 12, hdmi->version & 0xfff,
2426                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2427                  hdmi->phy.name);
2428
2429         initialize_hdmi_ih_mutes(hdmi);
2430
2431         irq = platform_get_irq(pdev, 0);
2432         if (irq < 0) {
2433                 ret = irq;
2434                 goto err_iahb;
2435         }
2436
2437         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2438                                         dw_hdmi_irq, IRQF_SHARED,
2439                                         dev_name(dev), hdmi);
2440         if (ret)
2441                 goto err_iahb;
2442
2443         hdmi->cec_notifier = cec_notifier_get(dev);
2444         if (!hdmi->cec_notifier) {
2445                 ret = -ENOMEM;
2446                 goto err_iahb;
2447         }
2448
2449         /*
2450          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2451          * N and cts values before enabling phy
2452          */
2453         hdmi_init_clk_regenerator(hdmi);
2454
2455         /* If DDC bus is not specified, try to register HDMI I2C bus */
2456         if (!hdmi->ddc) {
2457                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2458                 if (IS_ERR(hdmi->ddc))
2459                         hdmi->ddc = NULL;
2460         }
2461
2462         hdmi->bridge.driver_private = hdmi;
2463         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2464 #ifdef CONFIG_OF
2465         hdmi->bridge.of_node = pdev->dev.of_node;
2466 #endif
2467
2468         dw_hdmi_setup_i2c(hdmi);
2469         if (hdmi->phy.ops->setup_hpd)
2470                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2471
2472         memset(&pdevinfo, 0, sizeof(pdevinfo));
2473         pdevinfo.parent = dev;
2474         pdevinfo.id = PLATFORM_DEVID_AUTO;
2475
2476         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2477         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2478
2479         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2480                 struct dw_hdmi_audio_data audio;
2481
2482                 audio.phys = iores->start;
2483                 audio.base = hdmi->regs;
2484                 audio.irq = irq;
2485                 audio.hdmi = hdmi;
2486                 audio.eld = hdmi->connector.eld;
2487                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2488                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2489
2490                 pdevinfo.name = "dw-hdmi-ahb-audio";
2491                 pdevinfo.data = &audio;
2492                 pdevinfo.size_data = sizeof(audio);
2493                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2494                 hdmi->audio = platform_device_register_full(&pdevinfo);
2495         } else if (config0 & HDMI_CONFIG0_I2S) {
2496                 struct dw_hdmi_i2s_audio_data audio;
2497
2498                 audio.hdmi      = hdmi;
2499                 audio.write     = hdmi_writeb;
2500                 audio.read      = hdmi_readb;
2501                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2502                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2503
2504                 pdevinfo.name = "dw-hdmi-i2s-audio";
2505                 pdevinfo.data = &audio;
2506                 pdevinfo.size_data = sizeof(audio);
2507                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2508                 hdmi->audio = platform_device_register_full(&pdevinfo);
2509         }
2510
2511         if (config0 & HDMI_CONFIG0_CEC) {
2512                 cec.hdmi = hdmi;
2513                 cec.ops = &dw_hdmi_cec_ops;
2514                 cec.irq = irq;
2515
2516                 pdevinfo.name = "dw-hdmi-cec";
2517                 pdevinfo.data = &cec;
2518                 pdevinfo.size_data = sizeof(cec);
2519                 pdevinfo.dma_mask = 0;
2520
2521                 hdmi->cec = platform_device_register_full(&pdevinfo);
2522         }
2523
2524         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2525         if (hdmi->i2c)
2526                 dw_hdmi_i2c_init(hdmi);
2527
2528         platform_set_drvdata(pdev, hdmi);
2529
2530         return hdmi;
2531
2532 err_iahb:
2533         if (hdmi->i2c) {
2534                 i2c_del_adapter(&hdmi->i2c->adap);
2535                 hdmi->ddc = NULL;
2536         }
2537
2538         if (hdmi->cec_notifier)
2539                 cec_notifier_put(hdmi->cec_notifier);
2540
2541         clk_disable_unprepare(hdmi->iahb_clk);
2542         if (hdmi->cec_clk)
2543                 clk_disable_unprepare(hdmi->cec_clk);
2544 err_isfr:
2545         clk_disable_unprepare(hdmi->isfr_clk);
2546 err_res:
2547         i2c_put_adapter(hdmi->ddc);
2548
2549         return ERR_PTR(ret);
2550 }
2551
2552 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2553 {
2554         if (hdmi->audio && !IS_ERR(hdmi->audio))
2555                 platform_device_unregister(hdmi->audio);
2556         if (!IS_ERR(hdmi->cec))
2557                 platform_device_unregister(hdmi->cec);
2558
2559         /* Disable all interrupts */
2560         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2561
2562         if (hdmi->cec_notifier)
2563                 cec_notifier_put(hdmi->cec_notifier);
2564
2565         clk_disable_unprepare(hdmi->iahb_clk);
2566         clk_disable_unprepare(hdmi->isfr_clk);
2567         if (hdmi->cec_clk)
2568                 clk_disable_unprepare(hdmi->cec_clk);
2569
2570         if (hdmi->i2c)
2571                 i2c_del_adapter(&hdmi->i2c->adap);
2572         else
2573                 i2c_put_adapter(hdmi->ddc);
2574 }
2575
2576 /* -----------------------------------------------------------------------------
2577  * Probe/remove API, used from platforms based on the DRM bridge API.
2578  */
2579 int dw_hdmi_probe(struct platform_device *pdev,
2580                   const struct dw_hdmi_plat_data *plat_data)
2581 {
2582         struct dw_hdmi *hdmi;
2583
2584         hdmi = __dw_hdmi_probe(pdev, plat_data);
2585         if (IS_ERR(hdmi))
2586                 return PTR_ERR(hdmi);
2587
2588         drm_bridge_add(&hdmi->bridge);
2589
2590         return 0;
2591 }
2592 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2593
2594 void dw_hdmi_remove(struct platform_device *pdev)
2595 {
2596         struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2597
2598         drm_bridge_remove(&hdmi->bridge);
2599
2600         __dw_hdmi_remove(hdmi);
2601 }
2602 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2603
2604 /* -----------------------------------------------------------------------------
2605  * Bind/unbind API, used from platforms based on the component framework.
2606  */
2607 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2608                  const struct dw_hdmi_plat_data *plat_data)
2609 {
2610         struct dw_hdmi *hdmi;
2611         int ret;
2612
2613         hdmi = __dw_hdmi_probe(pdev, plat_data);
2614         if (IS_ERR(hdmi))
2615                 return PTR_ERR(hdmi);
2616
2617         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2618         if (ret) {
2619                 dw_hdmi_remove(pdev);
2620                 DRM_ERROR("Failed to initialize bridge with drm\n");
2621                 return ret;
2622         }
2623
2624         return 0;
2625 }
2626 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2627
2628 void dw_hdmi_unbind(struct device *dev)
2629 {
2630         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2631
2632         __dw_hdmi_remove(hdmi);
2633 }
2634 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2635
2636 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2637 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2638 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2639 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2640 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2641 MODULE_LICENSE("GPL");
2642 MODULE_ALIAS("platform:dw-hdmi");