drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/of_device.h>
  20
  21 #include <drm/drm_of.h>
  22 #include <drm/drmP.h>
  23 #include <drm/drm_crtc_helper.h>
  24 #include <drm/drm_edid.h>
  25 #include <drm/drm_encoder_slave.h>
  26 #include <drm/bridge/dw_hdmi.h>
  27
  28 #include "dw_hdmi.h"
  29
  30 #define HDMI_EDID_LEN           512
  31
  32 #define RGB                     0
  33 #define YCBCR444                1
  34 #define YCBCR422_16BITS         2
  35 #define YCBCR422_8BITS          3
  36 #define XVYCC444                4
  37
  38 enum hdmi_datamap {
  39         RGB444_8B = 0x01,
  40         RGB444_10B = 0x03,
  41         RGB444_12B = 0x05,
  42         RGB444_16B = 0x07,
  43         YCbCr444_8B = 0x09,
  44         YCbCr444_10B = 0x0B,
  45         YCbCr444_12B = 0x0D,
  46         YCbCr444_16B = 0x0F,
  47         YCbCr422_8B = 0x16,
  48         YCbCr422_10B = 0x14,
  49         YCbCr422_12B = 0x12,
  50 };
  51
  52 static const u16 csc_coeff_default[3][4] = {
  53         { 0x2000, 0x0000, 0x0000, 0x0000 },
  54         { 0x0000, 0x2000, 0x0000, 0x0000 },
  55         { 0x0000, 0x0000, 0x2000, 0x0000 }
  56 };
  57
  58 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  59         { 0x2000, 0x6926, 0x74fd, 0x010e },
  60         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  61         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  62 };
  63
  64 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  65         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  66         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  67         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  68 };
  69
  70 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  71         { 0x2591, 0x1322, 0x074b, 0x0000 },
  72         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  73         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  74 };
  75
  76 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  77         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  78         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  79         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  80 };
  81
  82 struct hdmi_vmode {
  83         bool mdvi;
  84         bool mhsyncpolarity;
  85         bool mvsyncpolarity;
  86         bool minterlaced;
  87         bool mdataenablepolarity;
  88
  89         unsigned int mpixelclock;
  90         unsigned int mpixelrepetitioninput;
  91         unsigned int mpixelrepetitionoutput;
  92 };
  93
  94 struct hdmi_data_info {
  95         unsigned int enc_in_format;
  96         unsigned int enc_out_format;
  97         unsigned int enc_color_depth;
  98         unsigned int colorimetry;
  99         unsigned int pix_repet_factor;
 100         unsigned int hdcp_enable;
 101         struct hdmi_vmode video_mode;
 102 };
 103
 104 struct dw_hdmi {
 105         struct drm_connector connector;
 106         struct drm_encoder *encoder;
 107         struct drm_bridge *bridge;
 108
 109         enum dw_hdmi_devtype dev_type;
 110         struct device *dev;
 111         struct clk *isfr_clk;
 112         struct clk *iahb_clk;
 113
 114         struct hdmi_data_info hdmi_data;
 115         const struct dw_hdmi_plat_data *plat_data;
 116
 117         int vic;
 118
 119         u8 edid[HDMI_EDID_LEN];
 120         bool cable_plugin;
 121
 122         bool phy_enabled;
 123         struct drm_display_mode previous_mode;
 124
 125         struct regmap *regmap;
 126         struct i2c_adapter *ddc;
 127         void __iomem *regs;
 128
 129         unsigned int sample_rate;
 130         int ratio;
 131
 132         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 133         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 134 };
 135
 136 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 137 {
 138         writel(val, hdmi->regs + (offset << 2));
 139 }
 140
 141 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 142 {
 143         return readl(hdmi->regs + (offset << 2));
 144 }
 145
 146 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 147 {
 148         writeb(val, hdmi->regs + offset);
 149 }
 150
 151 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 152 {
 153         return readb(hdmi->regs + offset);
 154 }
 155
 156 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 157 {
 158         hdmi->write(hdmi, val, offset);
 159 }
 160
 161 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 162 {
 163         return hdmi->read(hdmi, offset);
 164 }
 165
 166 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 167 {
 168         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 169
 170         val |= data & mask;
 171         hdmi_writeb(hdmi, val, reg);
 172 }
 173
 174 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 175                              u8 shift, u8 mask)
 176 {
 177         hdmi_modb(hdmi, data << shift, mask, reg);
 178 }
 179
 180 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 181                            unsigned int n)
 182 {
 183         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 184         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 185         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 186
 187         /* nshift factor = 0 */
 188         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 189
 190         /* Must be set/cleared first */
 191         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 192
 193         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 194         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 195         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 196                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 197 }
 198
 199 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 200                                    unsigned int ratio)
 201 {
 202         unsigned int n = (128 * freq) / 1000;
 203
 204         switch (freq) {
 205         case 32000:
 206                 if (pixel_clk == 25170000)
 207                         n = (ratio == 150) ? 9152 : 4576;
 208                 else if (pixel_clk == 27020000)
 209                         n = (ratio == 150) ? 8192 : 4096;
 210                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 211                         n = 11648;
 212                 else
 213                         n = 4096;
 214                 break;
 215
 216         case 44100:
 217                 if (pixel_clk == 25170000)
 218                         n = 7007;
 219                 else if (pixel_clk == 74170000)
 220                         n = 17836;
 221                 else if (pixel_clk == 148350000)
 222                         n = (ratio == 150) ? 17836 : 8918;
 223                 else
 224                         n = 6272;
 225                 break;
 226
 227         case 48000:
 228                 if (pixel_clk == 25170000)
 229                         n = (ratio == 150) ? 9152 : 6864;
 230                 else if (pixel_clk == 27020000)
 231                         n = (ratio == 150) ? 8192 : 6144;
 232                 else if (pixel_clk == 74170000)
 233                         n = 11648;
 234                 else if (pixel_clk == 148350000)
 235                         n = (ratio == 150) ? 11648 : 5824;
 236                 else
 237                         n = 6144;
 238                 break;
 239
 240         case 88200:
 241                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 242                 break;
 243
 244         case 96000:
 245                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 246                 break;
 247
 248         case 176400:
 249                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 250                 break;
 251
 252         case 192000:
 253                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 254                 break;
 255
 256         default:
 257                 break;
 258         }
 259
 260         return n;
 261 }
 262
 263 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 264                                      unsigned int ratio)
 265 {
 266         unsigned int cts = 0;
 267
 268         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 269                  pixel_clk, ratio);
 270
 271         switch (freq) {
 272         case 32000:
 273                 if (pixel_clk == 297000000) {
 274                         cts = 222750;
 275                         break;
 276                 }
 277         case 48000:
 278         case 96000:
 279         case 192000:
 280                 switch (pixel_clk) {
 281                 case 25200000:
 282                 case 27000000:
 283                 case 54000000:
 284                 case 74250000:
 285                 case 148500000:
 286                         cts = pixel_clk / 1000;
 287                         break;
 288                 case 297000000:
 289                         cts = 247500;
 290                         break;
 291                 /*
 292                  * All other TMDS clocks are not supported by
 293                  * DWC_hdmi_tx. The TMDS clocks divided or
 294                  * multiplied by 1,001 coefficients are not
 295                  * supported.
 296                  */
 297                 default:
 298                         break;
 299                 }
 300                 break;
 301         case 44100:
 302         case 88200:
 303         case 176400:
 304                 switch (pixel_clk) {
 305                 case 25200000:
 306                         cts = 28000;
 307                         break;
 308                 case 27000000:
 309                         cts = 30000;
 310                         break;
 311                 case 54000000:
 312                         cts = 60000;
 313                         break;
 314                 case 74250000:
 315                         cts = 82500;
 316                         break;
 317                 case 148500000:
 318                         cts = 165000;
 319                         break;
 320                 case 297000000:
 321                         cts = 247500;
 322                         break;
 323                 default:
 324                         break;
 325                 }
 326                 break;
 327         default:
 328                 break;
 329         }
 330         if (ratio == 100)
 331                 return cts;
 332         return (cts * ratio) / 100;
 333 }
 334
 335 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 336                                      unsigned long pixel_clk)
 337 {
 338         unsigned int clk_n, clk_cts;
 339
 340         clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
 341                                hdmi->ratio);
 342         clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
 343                                    hdmi->ratio);
 344
 345         if (!clk_cts) {
 346                 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
 347                         __func__, pixel_clk);
 348                 return;
 349         }
 350
 351         dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
 352                 __func__, hdmi->sample_rate, hdmi->ratio,
 353                 pixel_clk, clk_n, clk_cts);
 354
 355         hdmi_set_cts_n(hdmi, clk_cts, clk_n);
 356 }
 357
 358 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 359 {
 360         hdmi_set_clk_regenerator(hdmi, 74250000);
 361 }
 362
 363 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 364 {
 365         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
 366 }
 367
 368 /*
 369  * this submodule is responsible for the video data synchronization.
 370  * for example, for RGB 4:4:4 input, the data map is defined as
 371  *                      pin{47~40} <==> R[7:0]
 372  *                      pin{31~24} <==> G[7:0]
 373  *                      pin{15~8}  <==> B[7:0]
 374  */
 375 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 376 {
 377         int color_format = 0;
 378         u8 val;
 379
 380         if (hdmi->hdmi_data.enc_in_format == RGB) {
 381                 if (hdmi->hdmi_data.enc_color_depth == 8)
 382                         color_format = 0x01;
 383                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 384                         color_format = 0x03;
 385                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 386                         color_format = 0x05;
 387                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 388                         color_format = 0x07;
 389                 else
 390                         return;
 391         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 392                 if (hdmi->hdmi_data.enc_color_depth == 8)
 393                         color_format = 0x09;
 394                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 395                         color_format = 0x0B;
 396                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 397                         color_format = 0x0D;
 398                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 399                         color_format = 0x0F;
 400                 else
 401                         return;
 402         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 403                 if (hdmi->hdmi_data.enc_color_depth == 8)
 404                         color_format = 0x16;
 405                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 406                         color_format = 0x14;
 407                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 408                         color_format = 0x12;
 409                 else
 410                         return;
 411         }
 412
 413         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 414                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 415                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 416         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 417
 418         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 419         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 420                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 421                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 422         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 423         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 424         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 425         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 426         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 427         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 428         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 429 }
 430
 431 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 432 {
 433         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 434 }
 435
 436 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 437 {
 438         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 439                 return 0;
 440         if (hdmi->hdmi_data.enc_in_format == RGB ||
 441             hdmi->hdmi_data.enc_in_format == YCBCR444)
 442                 return 1;
 443         return 0;
 444 }
 445
 446 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 447 {
 448         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 449                 return 0;
 450         if (hdmi->hdmi_data.enc_out_format == RGB ||
 451             hdmi->hdmi_data.enc_out_format == YCBCR444)
 452                 return 1;
 453         return 0;
 454 }
 455
 456 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 457 {
 458         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 459         unsigned i;
 460         u32 csc_scale = 1;
 461
 462         if (is_color_space_conversion(hdmi)) {
 463                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 464                         if (hdmi->hdmi_data.colorimetry ==
 465                                         HDMI_COLORIMETRY_ITU_601)
 466                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 467                         else
 468                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 469                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 470                         if (hdmi->hdmi_data.colorimetry ==
 471                                         HDMI_COLORIMETRY_ITU_601)
 472                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 473                         else
 474                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 475                         csc_scale = 0;
 476                 }
 477         }
 478
 479         /* The CSC registers are sequential, alternating MSB then LSB */
 480         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 481                 u16 coeff_a = (*csc_coeff)[0][i];
 482                 u16 coeff_b = (*csc_coeff)[1][i];
 483                 u16 coeff_c = (*csc_coeff)[2][i];
 484
 485                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 486                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 487                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 488                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 489                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 490                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 491         }
 492
 493         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 494                   HDMI_CSC_SCALE);
 495 }
 496
 497 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 498 {
 499         int color_depth = 0;
 500         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 501         int decimation = 0;
 502
 503         /* YCC422 interpolation to 444 mode */
 504         if (is_color_space_interpolation(hdmi))
 505                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 506         else if (is_color_space_decimation(hdmi))
 507                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 508
 509         if (hdmi->hdmi_data.enc_color_depth == 8)
 510                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 511         else if (hdmi->hdmi_data.enc_color_depth == 10)
 512                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 513         else if (hdmi->hdmi_data.enc_color_depth == 12)
 514                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 515         else if (hdmi->hdmi_data.enc_color_depth == 16)
 516                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 517         else
 518                 return;
 519
 520         /* Configure the CSC registers */
 521         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 522         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 523                   HDMI_CSC_SCALE);
 524
 525         dw_hdmi_update_csc_coeffs(hdmi);
 526 }
 527
 528 /*
 529  * HDMI video packetizer is used to packetize the data.
 530  * for example, if input is YCC422 mode or repeater is used,
 531  * data should be repacked this module can be bypassed.
 532  */
 533 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 534 {
 535         unsigned int color_depth = 0;
 536         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 537         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 538         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 539         u8 val, vp_conf;
 540
 541         if (hdmi_data->enc_out_format == RGB ||
 542             hdmi_data->enc_out_format == YCBCR444) {
 543                 if (!hdmi_data->enc_color_depth) {
 544                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 545                 } else if (hdmi_data->enc_color_depth == 8) {
 546                         color_depth = 4;
 547                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 548                 } else if (hdmi_data->enc_color_depth == 10) {
 549                         color_depth = 5;
 550                 } else if (hdmi_data->enc_color_depth == 12) {
 551                         color_depth = 6;
 552                 } else if (hdmi_data->enc_color_depth == 16) {
 553                         color_depth = 7;
 554                 } else {
 555                         return;
 556                 }
 557         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 558                 if (!hdmi_data->enc_color_depth ||
 559                     hdmi_data->enc_color_depth == 8)
 560                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 561                 else if (hdmi_data->enc_color_depth == 10)
 562                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 563                 else if (hdmi_data->enc_color_depth == 12)
 564                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 565                 else
 566                         return;
 567                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 568         } else {
 569                 return;
 570         }
 571
 572         /* set the packetizer registers */
 573         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 574                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 575                 ((hdmi_data->pix_repet_factor <<
 576                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 577                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 578         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 579
 580         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 581                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 582
 583         /* Data from pixel repeater block */
 584         if (hdmi_data->pix_repet_factor > 1) {
 585                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 586                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 587         } else { /* data from packetizer block */
 588                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 589                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 590         }
 591
 592         hdmi_modb(hdmi, vp_conf,
 593                   HDMI_VP_CONF_PR_EN_MASK |
 594                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 595
 596         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 597                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 598
 599         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 600
 601         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 602                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 603                           HDMI_VP_CONF_PP_EN_ENABLE |
 604                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 605         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 606                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 607                           HDMI_VP_CONF_PP_EN_DISABLE |
 608                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 609         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 610                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 611                           HDMI_VP_CONF_PP_EN_DISABLE |
 612                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 613         } else {
 614                 return;
 615         }
 616
 617         hdmi_modb(hdmi, vp_conf,
 618                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 619                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 620
 621         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 622                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 623                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 624                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 625
 626         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 627                   HDMI_VP_CONF);
 628 }
 629
 630 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 631                                        unsigned char bit)
 632 {
 633         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 634                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 635 }
 636
 637 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 638                                         unsigned char bit)
 639 {
 640         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 641                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 642 }
 643
 644 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 645                                        unsigned char bit)
 646 {
 647         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 648                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 649 }
 650
 651 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 652                                      unsigned char bit)
 653 {
 654         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 655 }
 656
 657 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 658                                       unsigned char bit)
 659 {
 660         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 661 }
 662
 663 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 664 {
 665         u32 val;
 666
 667         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 668                 if (msec-- == 0)
 669                         return false;
 670                 udelay(1000);
 671         }
 672         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 673
 674         return true;
 675 }
 676
 677 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 678                                  unsigned char addr)
 679 {
 680         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 681         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 682         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 683                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 684         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 685                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 686         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 687                     HDMI_PHY_I2CM_OPERATION_ADDR);
 688         hdmi_phy_wait_i2c_done(hdmi, 1000);
 689 }
 690
 691 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 692                               unsigned char addr)
 693 {
 694         __hdmi_phy_i2c_write(hdmi, data, addr);
 695         return 0;
 696 }
 697
 698 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
 699 {
 700         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 701                          HDMI_PHY_CONF0_PDZ_OFFSET,
 702                          HDMI_PHY_CONF0_PDZ_MASK);
 703 }
 704
 705 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 706 {
 707         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 708                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 709                          HDMI_PHY_CONF0_ENTMDS_MASK);
 710 }
 711
 712 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 713 {
 714         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 715                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 716                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 717 }
 718
 719 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 720 {
 721         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 722                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 723                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 724 }
 725
 726 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 727 {
 728         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 729                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 730                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 731 }
 732
 733 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 734 {
 735         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 736                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 737                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 738 }
 739
 740 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 741 {
 742         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 743                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 744                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 745 }
 746
 747 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 748                               unsigned char res, int cscon)
 749 {
 750         unsigned res_idx, i;
 751         u8 val, msec;
 752         const struct dw_hdmi_mpll_config *mpll_config =
 753                                                 hdmi->plat_data->mpll_cfg;
 754         const struct dw_hdmi_curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
 755         const struct dw_hdmi_sym_term *sym_term =  hdmi->plat_data->sym_term;
 756
 757         if (prep)
 758                 return -EINVAL;
 759
 760         switch (res) {
 761         case 0: /* color resolution 0 is 8 bit colour depth */
 762         case 8:
 763                 res_idx = DW_HDMI_RES_8;
 764                 break;
 765         case 10:
 766                 res_idx = DW_HDMI_RES_10;
 767                 break;
 768         case 12:
 769                 res_idx = DW_HDMI_RES_12;
 770                 break;
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         /* Enable csc path */
 776         if (cscon)
 777                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 778         else
 779                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 780
 781         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 782
 783         /* gen2 tx power off */
 784         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 785
 786         /* gen2 pddq */
 787         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 788
 789         /* PHY reset */
 790         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 791         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 792
 793         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 794
 795         hdmi_phy_test_clear(hdmi, 1);
 796         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 797                     HDMI_PHY_I2CM_SLAVE_ADDR);
 798         hdmi_phy_test_clear(hdmi, 0);
 799
 800         /* PLL/MPLL Cfg - always match on final entry */
 801         for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
 802                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 803                     mpll_config[i].mpixelclock)
 804                         break;
 805
 806         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
 807         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
 808
 809         for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
 810                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 811                     curr_ctrl[i].mpixelclock)
 812                         break;
 813
 814         if (curr_ctrl[i].mpixelclock == (~0UL)) {
 815                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 816                         hdmi->hdmi_data.video_mode.mpixelclock);
 817                 return -EINVAL;
 818         }
 819
 820         /* CURRCTRL */
 821         hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
 822
 823         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 824         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 825
 826         for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
 827                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 828                     sym_term[i].mpixelclock)
 829                         break;
 830
 831         /* RESISTANCE TERM 133Ohm Cfg */
 832         hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19);  /* TXTERM */
 833         /* PREEMP Cgf 0.00 */
 834         hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09);  /* CKSYMTXCTRL */
 835
 836         /* TX/CK LVL 10 */
 837         hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
 838         /* REMOVE CLK TERM */
 839         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 840
 841         dw_hdmi_phy_enable_power(hdmi, 1);
 842
 843         /* toggle TMDS enable */
 844         dw_hdmi_phy_enable_tmds(hdmi, 0);
 845         dw_hdmi_phy_enable_tmds(hdmi, 1);
 846
 847         /* gen2 tx power on */
 848         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 849         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 850
 851         if (hdmi->dev_type == RK3288_HDMI)
 852                 dw_hdmi_phy_enable_spare(hdmi, 1);
 853
 854         /*Wait for PHY PLL lock */
 855         msec = 5;
 856         do {
 857                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 858                 if (!val)
 859                         break;
 860
 861                 if (msec == 0) {
 862                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 863                         return -ETIMEDOUT;
 864                 }
 865
 866                 udelay(1000);
 867                 msec--;
 868         } while (1);
 869
 870         return 0;
 871 }
 872
 873 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 874 {
 875         int i, ret;
 876         bool cscon = false;
 877
 878         /*check csc whether needed activated in HDMI mode */
 879         cscon = (is_color_space_conversion(hdmi) &&
 880                         !hdmi->hdmi_data.video_mode.mdvi);
 881
 882         /* HDMI Phy spec says to do the phy initialization sequence twice */
 883         for (i = 0; i < 2; i++) {
 884                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 885                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 886                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 887                 dw_hdmi_phy_enable_power(hdmi, 0);
 888
 889                 /* Enable CSC */
 890                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 891                 if (ret)
 892                         return ret;
 893         }
 894
 895         hdmi->phy_enabled = true;
 896         return 0;
 897 }
 898
 899 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 900 {
 901         u8 de;
 902
 903         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 904                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 905         else
 906                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 907
 908         /* disable rx detect */
 909         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 910                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 911
 912         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 913
 914         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 915                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 916 }
 917
 918 static void hdmi_config_AVI(struct dw_hdmi *hdmi)
 919 {
 920         u8 val, pix_fmt, under_scan;
 921         u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
 922         bool aspect_16_9;
 923
 924         aspect_16_9 = false; /* FIXME */
 925
 926         /* AVI Data Byte 1 */
 927         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 928                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
 929         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 930                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
 931         else
 932                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
 933
 934                 under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
 935
 936         /*
 937          * Active format identification data is present in the AVI InfoFrame.
 938          * Under scan info, no bar data
 939          */
 940         val = pix_fmt | under_scan |
 941                 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
 942                 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
 943
 944         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 945
 946         /* AVI Data Byte 2 -Set the Aspect Ratio */
 947         if (aspect_16_9) {
 948                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
 949                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
 950         } else {
 951                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
 952                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
 953         }
 954
 955         /* Set up colorimetry */
 956         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 957                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
 958                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 959                         ext_colorimetry =
 960                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 961                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 962                         ext_colorimetry =
 963                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
 964         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 965                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 966                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
 967                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 968                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
 969                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 970         } else { /* Carries no data */
 971                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
 972                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 973         }
 974
 975         val = colorimetry | coded_ratio | act_ratio;
 976         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
 977
 978         /* AVI Data Byte 3 */
 979         val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
 980                 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
 981                 HDMI_FC_AVICONF2_SCALING_NONE;
 982         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
 983
 984         /* AVI Data Byte 4 */
 985         hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
 986
 987         /* AVI Data Byte 5- set up input and output pixel repetition */
 988         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
 989                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
 990                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
 991                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
 992                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
 993                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
 994         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
 995
 996         /* IT Content and quantization range = don't care */
 997         val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
 998                 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
 999         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1000
1001         /* AVI Data Bytes 6-13 */
1002         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1003         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1004         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1005         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1006         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1007         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1008         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1009         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1010 }
1011
1012 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1013                              const struct drm_display_mode *mode)
1014 {
1015         u8 inv_val;
1016         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1017         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1018
1019         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1020         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1021         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1022         vmode->mpixelclock = mode->clock * 1000;
1023
1024         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1025
1026         /* Set up HDMI_FC_INVIDCONF */
1027         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1028                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1029                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1030
1031         inv_val |= (vmode->mvsyncpolarity ?
1032                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1033                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1034
1035         inv_val |= (vmode->mhsyncpolarity ?
1036                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1037                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1038
1039         inv_val |= (vmode->mdataenablepolarity ?
1040                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1041                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1042
1043         if (hdmi->vic == 39)
1044                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1045         else
1046                 inv_val |= (vmode->minterlaced ?
1047                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1048                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1049
1050         inv_val |= (vmode->minterlaced ?
1051                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1052                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1053
1054         inv_val |= (vmode->mdvi ?
1055                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1056                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1057
1058         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1059
1060         /* Set up horizontal active pixel width */
1061         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1062         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1063
1064         /* Set up vertical active lines */
1065         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1066         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1067
1068         /* Set up horizontal blanking pixel region width */
1069         hblank = mode->htotal - mode->hdisplay;
1070         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1071         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1072
1073         /* Set up vertical blanking pixel region width */
1074         vblank = mode->vtotal - mode->vdisplay;
1075         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1076
1077         /* Set up HSYNC active edge delay width (in pixel clks) */
1078         h_de_hs = mode->hsync_start - mode->hdisplay;
1079         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1080         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1081
1082         /* Set up VSYNC active edge delay (in lines) */
1083         v_de_vs = mode->vsync_start - mode->vdisplay;
1084         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1085
1086         /* Set up HSYNC active pulse width (in pixel clks) */
1087         hsync_len = mode->hsync_end - mode->hsync_start;
1088         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1089         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1090
1091         /* Set up VSYNC active edge delay (in lines) */
1092         vsync_len = mode->vsync_end - mode->vsync_start;
1093         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1094 }
1095
1096 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1097 {
1098         if (!hdmi->phy_enabled)
1099                 return;
1100
1101         dw_hdmi_phy_enable_tmds(hdmi, 0);
1102         dw_hdmi_phy_enable_power(hdmi, 0);
1103
1104         hdmi->phy_enabled = false;
1105 }
1106
1107 /* HDMI Initialization Step B.4 */
1108 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1109 {
1110         u8 clkdis;
1111
1112         /* control period minimum duration */
1113         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1114         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1115         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1116
1117         /* Set to fill TMDS data channels */
1118         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1119         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1120         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1121
1122         /* Enable pixel clock and tmds data path */
1123         clkdis = 0x7F;
1124         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1125         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1126
1127         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1128         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1129
1130         /* Enable csc path */
1131         if (is_color_space_conversion(hdmi)) {
1132                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1133                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1134         }
1135 }
1136
1137 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1138 {
1139         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1140 }
1141
1142 /* Workaround to clear the overflow condition */
1143 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1144 {
1145         int count;
1146         u8 val;
1147
1148         /* TMDS software reset */
1149         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1150
1151         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1152         if (hdmi->dev_type == IMX6DL_HDMI) {
1153                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1154                 return;
1155         }
1156
1157         for (count = 0; count < 4; count++)
1158                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1159 }
1160
1161 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1162 {
1163         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1164         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1165 }
1166
1167 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1168 {
1169         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1170                     HDMI_IH_MUTE_FC_STAT2);
1171 }
1172
1173 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1174 {
1175         int ret;
1176
1177         hdmi_disable_overflow_interrupts(hdmi);
1178
1179         hdmi->vic = drm_match_cea_mode(mode);
1180
1181         if (!hdmi->vic) {
1182                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1183                 hdmi->hdmi_data.video_mode.mdvi = true;
1184         } else {
1185                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1186                 hdmi->hdmi_data.video_mode.mdvi = false;
1187         }
1188
1189         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1190             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1191             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1192             (hdmi->vic == 17) || (hdmi->vic == 18))
1193                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1194         else
1195                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1196
1197         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1198             (hdmi->vic == 12) || (hdmi->vic == 13) ||
1199             (hdmi->vic == 14) || (hdmi->vic == 15) ||
1200             (hdmi->vic == 25) || (hdmi->vic == 26) ||
1201             (hdmi->vic == 27) || (hdmi->vic == 28) ||
1202             (hdmi->vic == 29) || (hdmi->vic == 30) ||
1203             (hdmi->vic == 35) || (hdmi->vic == 36) ||
1204             (hdmi->vic == 37) || (hdmi->vic == 38))
1205                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1206         else
1207                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1208
1209         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1210
1211         /* TODO: Get input format from IPU (via FB driver interface) */
1212         hdmi->hdmi_data.enc_in_format = RGB;
1213
1214         hdmi->hdmi_data.enc_out_format = RGB;
1215
1216         hdmi->hdmi_data.enc_color_depth = 8;
1217         hdmi->hdmi_data.pix_repet_factor = 0;
1218         hdmi->hdmi_data.hdcp_enable = 0;
1219         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1220
1221         /* HDMI Initialization Step B.1 */
1222         hdmi_av_composer(hdmi, mode);
1223
1224         /* HDMI Initializateion Step B.2 */
1225         ret = dw_hdmi_phy_init(hdmi);
1226         if (ret)
1227                 return ret;
1228
1229         /* HDMI Initialization Step B.3 */
1230         dw_hdmi_enable_video_path(hdmi);
1231
1232         /* not for DVI mode */
1233         if (hdmi->hdmi_data.video_mode.mdvi) {
1234                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1235         } else {
1236                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1237
1238                 /* HDMI Initialization Step E - Configure audio */
1239                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1240                 hdmi_enable_audio_clk(hdmi);
1241
1242                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1243                 hdmi_config_AVI(hdmi);
1244         }
1245
1246         hdmi_video_packetize(hdmi);
1247         hdmi_video_csc(hdmi);
1248         hdmi_video_sample(hdmi);
1249         hdmi_tx_hdcp_config(hdmi);
1250
1251         dw_hdmi_clear_overflow(hdmi);
1252         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1253                 hdmi_enable_overflow_interrupts(hdmi);
1254
1255         return 0;
1256 }
1257
1258 /* Wait until we are registered to enable interrupts */
1259 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1260 {
1261         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1262                     HDMI_PHY_I2CM_INT_ADDR);
1263
1264         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1265                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1266                     HDMI_PHY_I2CM_CTLINT_ADDR);
1267
1268         /* enable cable hot plug irq */
1269         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1270
1271         /* Clear Hotplug interrupts */
1272         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1273
1274         return 0;
1275 }
1276
1277 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1278 {
1279         u8 ih_mute;
1280
1281         /*
1282          * Boot up defaults are:
1283          * HDMI_IH_MUTE   = 0x03 (disabled)
1284          * HDMI_IH_MUTE_* = 0x00 (enabled)
1285          *
1286          * Disable top level interrupt bits in HDMI block
1287          */
1288         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1289                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1290                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1291
1292         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1293
1294         /* by default mask all interrupts */
1295         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1296         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1297         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1298         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1299         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1300         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1301         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1302         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1303         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1304         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1305         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1306         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1307         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1308         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1309         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1310
1311         /* Disable interrupts in the IH_MUTE_* registers */
1312         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1313         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1314         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1315         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1316         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1317         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1318         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1319         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1320         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1321         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1322
1323         /* Enable top level interrupt bits in HDMI block */
1324         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1325                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1326         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1327 }
1328
1329 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1330 {
1331         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1332 }
1333
1334 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1335 {
1336         dw_hdmi_phy_disable(hdmi);
1337 }
1338
1339 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1340                                     struct drm_display_mode *orig_mode,
1341                                     struct drm_display_mode *mode)
1342 {
1343         struct dw_hdmi *hdmi = bridge->driver_private;
1344
1345         dw_hdmi_setup(hdmi, mode);
1346
1347         /* Store the display mode for plugin/DKMS poweron events */
1348         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1349 }
1350
1351 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1352                                       const struct drm_display_mode *mode,
1353                                       struct drm_display_mode *adjusted_mode)
1354 {
1355         return true;
1356 }
1357
1358 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1359 {
1360         struct dw_hdmi *hdmi = bridge->driver_private;
1361
1362         dw_hdmi_poweroff(hdmi);
1363 }
1364
1365 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1366 {
1367         struct dw_hdmi *hdmi = bridge->driver_private;
1368
1369         dw_hdmi_poweron(hdmi);
1370 }
1371
1372 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1373 {
1374         /* do nothing */
1375 }
1376
1377 static enum drm_connector_status
1378 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1379 {
1380         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1381                                              connector);
1382
1383         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1384                 connector_status_connected : connector_status_disconnected;
1385 }
1386
1387 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1388 {
1389         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1390                                              connector);
1391         struct edid *edid;
1392         int ret;
1393
1394         if (!hdmi->ddc)
1395                 return 0;
1396
1397         edid = drm_get_edid(connector, hdmi->ddc);
1398         if (edid) {
1399                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1400                         edid->width_cm, edid->height_cm);
1401
1402                 drm_mode_connector_update_edid_property(connector, edid);
1403                 ret = drm_add_edid_modes(connector, edid);
1404                 kfree(edid);
1405         } else {
1406                 dev_dbg(hdmi->dev, "failed to get edid\n");
1407         }
1408
1409         return 0;
1410 }
1411
1412 static enum drm_mode_status
1413 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1414                              struct drm_display_mode *mode)
1415 {
1416         struct dw_hdmi *hdmi = container_of(connector,
1417                                            struct dw_hdmi, connector);
1418         enum drm_mode_status mode_status = MODE_OK;
1419
1420         if (hdmi->plat_data->mode_valid)
1421                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1422
1423         return mode_status;
1424 }
1425
1426 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1427                                                            *connector)
1428 {
1429         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1430                                              connector);
1431
1432         return hdmi->encoder;
1433 }
1434
1435 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1436 {
1437         drm_connector_unregister(connector);
1438         drm_connector_cleanup(connector);
1439 }
1440
1441 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1442         .dpms = drm_helper_connector_dpms,
1443         .fill_modes = drm_helper_probe_single_connector_modes,
1444         .detect = dw_hdmi_connector_detect,
1445         .destroy = dw_hdmi_connector_destroy,
1446 };
1447
1448 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1449         .get_modes = dw_hdmi_connector_get_modes,
1450         .mode_valid = dw_hdmi_connector_mode_valid,
1451         .best_encoder = dw_hdmi_connector_best_encoder,
1452 };
1453
1454 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1455         .enable = dw_hdmi_bridge_enable,
1456         .disable = dw_hdmi_bridge_disable,
1457         .pre_enable = dw_hdmi_bridge_nop,
1458         .post_disable = dw_hdmi_bridge_nop,
1459         .mode_set = dw_hdmi_bridge_mode_set,
1460         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1461 };
1462
1463 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1464 {
1465         struct dw_hdmi *hdmi = dev_id;
1466         u8 intr_stat;
1467
1468         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1469         if (intr_stat)
1470                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1471
1472         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1473 }
1474
1475 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1476 {
1477         struct dw_hdmi *hdmi = dev_id;
1478         u8 intr_stat;
1479         u8 phy_int_pol;
1480
1481         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1482
1483         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1484
1485         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1486                 if (phy_int_pol & HDMI_PHY_HPD) {
1487                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1488
1489                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1490
1491                         dw_hdmi_poweron(hdmi);
1492                 } else {
1493                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1494
1495                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1496                                   HDMI_PHY_POL0);
1497
1498                         dw_hdmi_poweroff(hdmi);
1499                 }
1500                 drm_helper_hpd_irq_event(hdmi->connector.dev);
1501         }
1502
1503         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1504         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1505
1506         return IRQ_HANDLED;
1507 }
1508
1509 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1510 {
1511         struct drm_encoder *encoder = hdmi->encoder;
1512         struct drm_bridge *bridge;
1513         int ret;
1514
1515         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1516         if (!bridge) {
1517                 DRM_ERROR("Failed to allocate drm bridge\n");
1518                 return -ENOMEM;
1519         }
1520
1521         hdmi->bridge = bridge;
1522         bridge->driver_private = hdmi;
1523         bridge->funcs = &dw_hdmi_bridge_funcs;
1524         ret = drm_bridge_attach(drm, bridge);
1525         if (ret) {
1526                 DRM_ERROR("Failed to initialize bridge with drm\n");
1527                 return -EINVAL;
1528         }
1529
1530         encoder->bridge = bridge;
1531         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1532
1533         drm_connector_helper_add(&hdmi->connector,
1534                                  &dw_hdmi_connector_helper_funcs);
1535         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1536                            DRM_MODE_CONNECTOR_HDMIA);
1537
1538         hdmi->connector.encoder = encoder;
1539
1540         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1541
1542         return 0;
1543 }
1544
1545 int dw_hdmi_bind(struct device *dev, struct device *master,
1546                  void *data, struct drm_encoder *encoder,
1547                  struct resource *iores, int irq,
1548                  const struct dw_hdmi_plat_data *plat_data)
1549 {
1550         struct drm_device *drm = data;
1551         struct device_node *np = dev->of_node;
1552         struct device_node *ddc_node;
1553         struct dw_hdmi *hdmi;
1554         int ret;
1555         u32 val = 1;
1556
1557         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1558         if (!hdmi)
1559                 return -ENOMEM;
1560
1561         hdmi->plat_data = plat_data;
1562         hdmi->dev = dev;
1563         hdmi->dev_type = plat_data->dev_type;
1564         hdmi->sample_rate = 48000;
1565         hdmi->ratio = 100;
1566         hdmi->encoder = encoder;
1567
1568         of_property_read_u32(np, "reg-io-width", &val);
1569
1570         switch (val) {
1571         case 4:
1572                 hdmi->write = dw_hdmi_writel;
1573                 hdmi->read = dw_hdmi_readl;
1574                 break;
1575         case 1:
1576                 hdmi->write = dw_hdmi_writeb;
1577                 hdmi->read = dw_hdmi_readb;
1578                 break;
1579         default:
1580                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1581                 return -EINVAL;
1582         }
1583
1584         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1585         if (ddc_node) {
1586                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1587                 of_node_put(ddc_node);
1588                 if (!hdmi->ddc) {
1589                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1590                         return -EPROBE_DEFER;
1591                 }
1592
1593         } else {
1594                 dev_dbg(hdmi->dev, "no ddc property found\n");
1595         }
1596
1597         hdmi->regs = devm_ioremap_resource(dev, iores);
1598         if (IS_ERR(hdmi->regs))
1599                 return PTR_ERR(hdmi->regs);
1600
1601         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1602         if (IS_ERR(hdmi->isfr_clk)) {
1603                 ret = PTR_ERR(hdmi->isfr_clk);
1604                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1605                 return ret;
1606         }
1607
1608         ret = clk_prepare_enable(hdmi->isfr_clk);
1609         if (ret) {
1610                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1611                 return ret;
1612         }
1613
1614         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1615         if (IS_ERR(hdmi->iahb_clk)) {
1616                 ret = PTR_ERR(hdmi->iahb_clk);
1617                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1618                 goto err_isfr;
1619         }
1620
1621         ret = clk_prepare_enable(hdmi->iahb_clk);
1622         if (ret) {
1623                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1624                 goto err_isfr;
1625         }
1626
1627         /* Product and revision IDs */
1628         dev_info(dev,
1629                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1630                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1631                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1632                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1633                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1634
1635         initialize_hdmi_ih_mutes(hdmi);
1636
1637         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1638                                         dw_hdmi_irq, IRQF_SHARED,
1639                                         dev_name(dev), hdmi);
1640         if (ret)
1641                 goto err_iahb;
1642
1643         /*
1644          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1645          * N and cts values before enabling phy
1646          */
1647         hdmi_init_clk_regenerator(hdmi);
1648
1649         /*
1650          * Configure registers related to HDMI interrupt
1651          * generation before registering IRQ.
1652          */
1653         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1654
1655         /* Clear Hotplug interrupts */
1656         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1657
1658         ret = dw_hdmi_fb_registered(hdmi);
1659         if (ret)
1660                 goto err_iahb;
1661
1662         ret = dw_hdmi_register(drm, hdmi);
1663         if (ret)
1664                 goto err_iahb;
1665
1666         /* Unmute interrupts */
1667         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1668
1669         dev_set_drvdata(dev, hdmi);
1670
1671         return 0;
1672
1673 err_iahb:
1674         clk_disable_unprepare(hdmi->iahb_clk);
1675 err_isfr:
1676         clk_disable_unprepare(hdmi->isfr_clk);
1677
1678         return ret;
1679 }
1680 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1681
1682 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1683 {
1684         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1685
1686         /* Disable all interrupts */
1687         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1688
1689         hdmi->connector.funcs->destroy(&hdmi->connector);
1690         hdmi->encoder->funcs->destroy(hdmi->encoder);
1691
1692         clk_disable_unprepare(hdmi->iahb_clk);
1693         clk_disable_unprepare(hdmi->isfr_clk);
1694         i2c_put_adapter(hdmi->ddc);
1695 }
1696 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1697
1698 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1699 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1700 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1701 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1702 MODULE_LICENSE("GPL");
1703 MODULE_ALIAS("platform:dw-hdmi");