drivers/gpu/drm/arm/hdlcd_drv.c

   1 /*
   2  * Copyright (C) 2013-2015 ARM Limited
   3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive
   7  * for more details.
   8  *
   9  *  ARM HDLCD Driver
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/list.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/of_reserved_mem.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #include <drm/drmP.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_crtc.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27 #include <drm/drm_gem_cma_helper.h>
  28 #include <drm/drm_gem_framebuffer_helper.h>
  29 #include <drm/drm_of.h>
  30
  31 #include "hdlcd_drv.h"
  32 #include "hdlcd_regs.h"
  33
  34 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
  35 {
  36         struct hdlcd_drm_private *hdlcd = drm->dev_private;
  37         struct platform_device *pdev = to_platform_device(drm->dev);
  38         struct resource *res;
  39         u32 version;
  40         int ret;
  41
  42         hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
  43         if (IS_ERR(hdlcd->clk))
  44                 return PTR_ERR(hdlcd->clk);
  45
  46 #ifdef CONFIG_DEBUG_FS
  47         atomic_set(&hdlcd->buffer_underrun_count, 0);
  48         atomic_set(&hdlcd->bus_error_count, 0);
  49         atomic_set(&hdlcd->vsync_count, 0);
  50         atomic_set(&hdlcd->dma_end_count, 0);
  51 #endif
  52
  53         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  54         hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
  55         if (IS_ERR(hdlcd->mmio)) {
  56                 DRM_ERROR("failed to map control registers area\n");
  57                 ret = PTR_ERR(hdlcd->mmio);
  58                 hdlcd->mmio = NULL;
  59                 return ret;
  60         }
  61
  62         version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
  63         if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
  64                 DRM_ERROR("unknown product id: 0x%x\n", version);
  65                 return -EINVAL;
  66         }
  67         DRM_INFO("found ARM HDLCD version r%dp%d\n",
  68                 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
  69                 version & HDLCD_VERSION_MINOR_MASK);
  70
  71         /* Get the optional framebuffer memory resource */
  72         ret = of_reserved_mem_device_init(drm->dev);
  73         if (ret && ret != -ENODEV)
  74                 return ret;
  75
  76         ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
  77         if (ret)
  78                 goto setup_fail;
  79
  80         ret = hdlcd_setup_crtc(drm);
  81         if (ret < 0) {
  82                 DRM_ERROR("failed to create crtc\n");
  83                 goto setup_fail;
  84         }
  85
  86         ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
  87         if (ret < 0) {
  88                 DRM_ERROR("failed to install IRQ handler\n");
  89                 goto irq_fail;
  90         }
  91
  92         return 0;
  93
  94 irq_fail:
  95         drm_crtc_cleanup(&hdlcd->crtc);
  96 setup_fail:
  97         of_reserved_mem_device_release(drm->dev);
  98
  99         return ret;
 100 }
 101
 102 static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
 103 {
 104         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 105
 106         drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
 107 }
 108
 109 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
 110         .fb_create = drm_gem_fb_create,
 111         .output_poll_changed = hdlcd_fb_output_poll_changed,
 112         .atomic_check = drm_atomic_helper_check,
 113         .atomic_commit = drm_atomic_helper_commit,
 114 };
 115
 116 static void hdlcd_setup_mode_config(struct drm_device *drm)
 117 {
 118         drm_mode_config_init(drm);
 119         drm->mode_config.min_width = 0;
 120         drm->mode_config.min_height = 0;
 121         drm->mode_config.max_width = HDLCD_MAX_XRES;
 122         drm->mode_config.max_height = HDLCD_MAX_YRES;
 123         drm->mode_config.funcs = &hdlcd_mode_config_funcs;
 124 }
 125
 126 static void hdlcd_lastclose(struct drm_device *drm)
 127 {
 128         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 129
 130         drm_fbdev_cma_restore_mode(hdlcd->fbdev);
 131 }
 132
 133 static irqreturn_t hdlcd_irq(int irq, void *arg)
 134 {
 135         struct drm_device *drm = arg;
 136         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 137         unsigned long irq_status;
 138
 139         irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
 140
 141 #ifdef CONFIG_DEBUG_FS
 142         if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
 143                 atomic_inc(&hdlcd->buffer_underrun_count);
 144
 145         if (irq_status & HDLCD_INTERRUPT_DMA_END)
 146                 atomic_inc(&hdlcd->dma_end_count);
 147
 148         if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
 149                 atomic_inc(&hdlcd->bus_error_count);
 150
 151         if (irq_status & HDLCD_INTERRUPT_VSYNC)
 152                 atomic_inc(&hdlcd->vsync_count);
 153
 154 #endif
 155         if (irq_status & HDLCD_INTERRUPT_VSYNC)
 156                 drm_crtc_handle_vblank(&hdlcd->crtc);
 157
 158         /* acknowledge interrupt(s) */
 159         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 static void hdlcd_irq_preinstall(struct drm_device *drm)
 165 {
 166         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 167         /* Ensure interrupts are disabled */
 168         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
 169         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
 170 }
 171
 172 static int hdlcd_irq_postinstall(struct drm_device *drm)
 173 {
 174 #ifdef CONFIG_DEBUG_FS
 175         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 176         unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
 177
 178         /* enable debug interrupts */
 179         irq_mask |= HDLCD_DEBUG_INT_MASK;
 180
 181         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
 182 #endif
 183         return 0;
 184 }
 185
 186 static void hdlcd_irq_uninstall(struct drm_device *drm)
 187 {
 188         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 189         /* disable all the interrupts that we might have enabled */
 190         unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
 191
 192 #ifdef CONFIG_DEBUG_FS
 193         /* disable debug interrupts */
 194         irq_mask &= ~HDLCD_DEBUG_INT_MASK;
 195 #endif
 196
 197         /* disable vsync interrupts */
 198         irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
 199
 200         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
 201 }
 202
 203 #ifdef CONFIG_DEBUG_FS
 204 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
 205 {
 206         struct drm_info_node *node = (struct drm_info_node *)m->private;
 207         struct drm_device *drm = node->minor->dev;
 208         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 209
 210         seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
 211         seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
 212         seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
 213         seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
 214         return 0;
 215 }
 216
 217 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
 218 {
 219         struct drm_info_node *node = (struct drm_info_node *)m->private;
 220         struct drm_device *drm = node->minor->dev;
 221         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 222         unsigned long clkrate = clk_get_rate(hdlcd->clk);
 223         unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
 224
 225         seq_printf(m, "hw  : %lu\n", clkrate);
 226         seq_printf(m, "mode: %lu\n", mode_clock);
 227         return 0;
 228 }
 229
 230 static struct drm_info_list hdlcd_debugfs_list[] = {
 231         { "interrupt_count", hdlcd_show_underrun_count, 0 },
 232         { "clocks", hdlcd_show_pxlclock, 0 },
 233         { "fb", drm_fb_cma_debugfs_show, 0 },
 234 };
 235
 236 static int hdlcd_debugfs_init(struct drm_minor *minor)
 237 {
 238         return drm_debugfs_create_files(hdlcd_debugfs_list,
 239                 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
 240 }
 241 #endif
 242
 243 DEFINE_DRM_GEM_CMA_FOPS(fops);
 244
 245 static struct drm_driver hdlcd_driver = {
 246         .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
 247                            DRIVER_MODESET | DRIVER_PRIME |
 248                            DRIVER_ATOMIC,
 249         .lastclose = hdlcd_lastclose,
 250         .irq_handler = hdlcd_irq,
 251         .irq_preinstall = hdlcd_irq_preinstall,
 252         .irq_postinstall = hdlcd_irq_postinstall,
 253         .irq_uninstall = hdlcd_irq_uninstall,
 254         .gem_free_object_unlocked = drm_gem_cma_free_object,
 255         .gem_vm_ops = &drm_gem_cma_vm_ops,
 256         .dumb_create = drm_gem_cma_dumb_create,
 257         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 258         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 259         .gem_prime_export = drm_gem_prime_export,
 260         .gem_prime_import = drm_gem_prime_import,
 261         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 262         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 263         .gem_prime_vmap = drm_gem_cma_prime_vmap,
 264         .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
 265         .gem_prime_mmap = drm_gem_cma_prime_mmap,
 266 #ifdef CONFIG_DEBUG_FS
 267         .debugfs_init = hdlcd_debugfs_init,
 268 #endif
 269         .fops = &fops,
 270         .name = "hdlcd",
 271         .desc = "ARM HDLCD Controller DRM",
 272         .date = "20151021",
 273         .major = 1,
 274         .minor = 0,
 275 };
 276
 277 static int hdlcd_drm_bind(struct device *dev)
 278 {
 279         struct drm_device *drm;
 280         struct hdlcd_drm_private *hdlcd;
 281         int ret;
 282
 283         hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
 284         if (!hdlcd)
 285                 return -ENOMEM;
 286
 287         drm = drm_dev_alloc(&hdlcd_driver, dev);
 288         if (IS_ERR(drm))
 289                 return PTR_ERR(drm);
 290
 291         drm->dev_private = hdlcd;
 292         dev_set_drvdata(dev, drm);
 293
 294         hdlcd_setup_mode_config(drm);
 295         ret = hdlcd_load(drm, 0);
 296         if (ret)
 297                 goto err_free;
 298
 299         /* Set the CRTC's port so that the encoder component can find it */
 300         hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 301
 302         ret = component_bind_all(dev, drm);
 303         if (ret) {
 304                 DRM_ERROR("Failed to bind all components\n");
 305                 goto err_unload;
 306         }
 307
 308         ret = pm_runtime_set_active(dev);
 309         if (ret)
 310                 goto err_pm_active;
 311
 312         pm_runtime_enable(dev);
 313
 314         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 315         if (ret < 0) {
 316                 DRM_ERROR("failed to initialise vblank\n");
 317                 goto err_vblank;
 318         }
 319
 320         drm_mode_config_reset(drm);
 321         drm_kms_helper_poll_init(drm);
 322
 323         hdlcd->fbdev = drm_fbdev_cma_init(drm, 32,
 324                                           drm->mode_config.num_connector);
 325
 326         if (IS_ERR(hdlcd->fbdev)) {
 327                 ret = PTR_ERR(hdlcd->fbdev);
 328                 hdlcd->fbdev = NULL;
 329                 goto err_fbdev;
 330         }
 331
 332         ret = drm_dev_register(drm, 0);
 333         if (ret)
 334                 goto err_register;
 335
 336         return 0;
 337
 338 err_register:
 339         if (hdlcd->fbdev) {
 340                 drm_fbdev_cma_fini(hdlcd->fbdev);
 341                 hdlcd->fbdev = NULL;
 342         }
 343 err_fbdev:
 344         drm_kms_helper_poll_fini(drm);
 345 err_vblank:
 346         pm_runtime_disable(drm->dev);
 347 err_pm_active:
 348         component_unbind_all(dev, drm);
 349 err_unload:
 350         of_node_put(hdlcd->crtc.port);
 351         hdlcd->crtc.port = NULL;
 352         drm_irq_uninstall(drm);
 353         of_reserved_mem_device_release(drm->dev);
 354 err_free:
 355         drm_mode_config_cleanup(drm);
 356         dev_set_drvdata(dev, NULL);
 357         drm_dev_unref(drm);
 358
 359         return ret;
 360 }
 361
 362 static void hdlcd_drm_unbind(struct device *dev)
 363 {
 364         struct drm_device *drm = dev_get_drvdata(dev);
 365         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 366
 367         drm_dev_unregister(drm);
 368         if (hdlcd->fbdev) {
 369                 drm_fbdev_cma_fini(hdlcd->fbdev);
 370                 hdlcd->fbdev = NULL;
 371         }
 372         drm_kms_helper_poll_fini(drm);
 373         component_unbind_all(dev, drm);
 374         of_node_put(hdlcd->crtc.port);
 375         hdlcd->crtc.port = NULL;
 376         pm_runtime_get_sync(drm->dev);
 377         drm_irq_uninstall(drm);
 378         pm_runtime_put_sync(drm->dev);
 379         pm_runtime_disable(drm->dev);
 380         of_reserved_mem_device_release(drm->dev);
 381         drm_mode_config_cleanup(drm);
 382         drm_dev_unref(drm);
 383         drm->dev_private = NULL;
 384         dev_set_drvdata(dev, NULL);
 385 }
 386
 387 static const struct component_master_ops hdlcd_master_ops = {
 388         .bind           = hdlcd_drm_bind,
 389         .unbind         = hdlcd_drm_unbind,
 390 };
 391
 392 static int compare_dev(struct device *dev, void *data)
 393 {
 394         return dev->of_node == data;
 395 }
 396
 397 static int hdlcd_probe(struct platform_device *pdev)
 398 {
 399         struct device_node *port;
 400         struct component_match *match = NULL;
 401
 402         /* there is only one output port inside each device, find it */
 403         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 404         if (!port)
 405                 return -ENODEV;
 406
 407         drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
 408         of_node_put(port);
 409
 410         return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
 411                                                match);
 412 }
 413
 414 static int hdlcd_remove(struct platform_device *pdev)
 415 {
 416         component_master_del(&pdev->dev, &hdlcd_master_ops);
 417         return 0;
 418 }
 419
 420 static const struct of_device_id  hdlcd_of_match[] = {
 421         { .compatible   = "arm,hdlcd" },
 422         {},
 423 };
 424 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
 425
 426 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
 427 {
 428         struct drm_device *drm = dev_get_drvdata(dev);
 429         struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
 430
 431         if (!hdlcd)
 432                 return 0;
 433
 434         drm_kms_helper_poll_disable(drm);
 435
 436         hdlcd->state = drm_atomic_helper_suspend(drm);
 437         if (IS_ERR(hdlcd->state)) {
 438                 drm_kms_helper_poll_enable(drm);
 439                 return PTR_ERR(hdlcd->state);
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
 446 {
 447         struct drm_device *drm = dev_get_drvdata(dev);
 448         struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
 449
 450         if (!hdlcd)
 451                 return 0;
 452
 453         drm_atomic_helper_resume(drm, hdlcd->state);
 454         drm_kms_helper_poll_enable(drm);
 455         pm_runtime_set_active(dev);
 456
 457         return 0;
 458 }
 459
 460 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
 461
 462 static struct platform_driver hdlcd_platform_driver = {
 463         .probe          = hdlcd_probe,
 464         .remove         = hdlcd_remove,
 465         .driver = {
 466                 .name = "hdlcd",
 467                 .pm = &hdlcd_pm_ops,
 468                 .of_match_table = hdlcd_of_match,
 469         },
 470 };
 471
 472 module_platform_driver(hdlcd_platform_driver);
 473
 474 MODULE_AUTHOR("Liviu Dudau");
 475 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
 476 MODULE_LICENSE("GPL v2");