drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/delay.h>
  26 #include <linux/kernel.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29 #include <linux/pci.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "power_state.h"
  32 #include "hwmgr.h"
  33 #include "ppsmc.h"
  34 #include "amd_acpi.h"
  35 #include "pp_psm.h"
  36
  37 extern const struct pp_smumgr_func ci_smu_funcs;
  38 extern const struct pp_smumgr_func smu8_smu_funcs;
  39 extern const struct pp_smumgr_func iceland_smu_funcs;
  40 extern const struct pp_smumgr_func tonga_smu_funcs;
  41 extern const struct pp_smumgr_func fiji_smu_funcs;
  42 extern const struct pp_smumgr_func polaris10_smu_funcs;
  43 extern const struct pp_smumgr_func vega10_smu_funcs;
  44 extern const struct pp_smumgr_func vega12_smu_funcs;
  45 extern const struct pp_smumgr_func smu10_smu_funcs;
  46
  47 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
  48 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
  49 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
  50 extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
  51 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
  52
  53 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  54 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
  55 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
  56 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  57 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  58 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  59 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  60
  61 static int phm_thermal_l2h_irq(void *private_data,
  62                  unsigned src_id, const uint32_t *iv_entry)
  63 {
  64         struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
  65         struct amdgpu_device *adev = hwmgr->adev;
  66
  67         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
  68                         PCI_BUS_NUM(adev->pdev->devfn),
  69                         PCI_SLOT(adev->pdev->devfn),
  70                         PCI_FUNC(adev->pdev->devfn));
  71         return 0;
  72 }
  73
  74 static int phm_thermal_h2l_irq(void *private_data,
  75                  unsigned src_id, const uint32_t *iv_entry)
  76 {
  77         struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
  78         struct amdgpu_device *adev = hwmgr->adev;
  79
  80         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
  81                         PCI_BUS_NUM(adev->pdev->devfn),
  82                         PCI_SLOT(adev->pdev->devfn),
  83                         PCI_FUNC(adev->pdev->devfn));
  84         return 0;
  85 }
  86
  87 static int phm_ctf_irq(void *private_data,
  88                  unsigned src_id, const uint32_t *iv_entry)
  89 {
  90         struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
  91         struct amdgpu_device *adev = hwmgr->adev;
  92
  93         pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
  94                         PCI_BUS_NUM(adev->pdev->devfn),
  95                         PCI_SLOT(adev->pdev->devfn),
  96                         PCI_FUNC(adev->pdev->devfn));
  97         return 0;
  98 }
  99
 100 static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
 101         { .handler = phm_thermal_l2h_irq },
 102         { .handler = phm_thermal_h2l_irq },
 103         { .handler = phm_ctf_irq }
 104 };
 105
 106 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
 107 {
 108         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
 109         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
 110         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
 111         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
 112         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
 113
 114         hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
 115         hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
 116         hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 117         hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
 118         hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
 119 }
 120
 121 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 122 {
 123         if (hwmgr == NULL)
 124                 return -EINVAL;
 125
 126         hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
 127         hwmgr->power_source = PP_PowerSource_AC;
 128         hwmgr->pp_table_version = PP_TABLE_V1;
 129         hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 130         hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 131         hwmgr_init_default_caps(hwmgr);
 132         hwmgr_set_user_specify_caps(hwmgr);
 133         hwmgr->fan_ctrl_is_in_default_mode = true;
 134         hwmgr->reload_fw = 1;
 135         hwmgr_init_workload_prority(hwmgr);
 136
 137         switch (hwmgr->chip_family) {
 138         case AMDGPU_FAMILY_CI:
 139                 hwmgr->smumgr_funcs = &ci_smu_funcs;
 140                 ci_set_asic_special_caps(hwmgr);
 141                 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
 142                                         PP_ENABLE_GFX_CG_THRU_SMU);
 143                 hwmgr->pp_table_version = PP_TABLE_V0;
 144                 hwmgr->od_enabled = false;
 145                 smu7_init_function_pointers(hwmgr);
 146                 break;
 147         case AMDGPU_FAMILY_CZ:
 148                 hwmgr->od_enabled = false;
 149                 hwmgr->smumgr_funcs = &smu8_smu_funcs;
 150                 smu8_init_function_pointers(hwmgr);
 151                 break;
 152         case AMDGPU_FAMILY_VI:
 153                 switch (hwmgr->chip_id) {
 154                 case CHIP_TOPAZ:
 155                         hwmgr->smumgr_funcs = &iceland_smu_funcs;
 156                         topaz_set_asic_special_caps(hwmgr);
 157                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 158                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 159                         hwmgr->pp_table_version = PP_TABLE_V0;
 160                         hwmgr->od_enabled = false;
 161                         break;
 162                 case CHIP_TONGA:
 163                         hwmgr->smumgr_funcs = &tonga_smu_funcs;
 164                         tonga_set_asic_special_caps(hwmgr);
 165                         hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
 166                         break;
 167                 case CHIP_FIJI:
 168                         hwmgr->smumgr_funcs = &fiji_smu_funcs;
 169                         fiji_set_asic_special_caps(hwmgr);
 170                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 171                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 172                         break;
 173                 case CHIP_POLARIS11:
 174                 case CHIP_POLARIS10:
 175                 case CHIP_POLARIS12:
 176                         hwmgr->smumgr_funcs = &polaris10_smu_funcs;
 177                         polaris_set_asic_special_caps(hwmgr);
 178                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 179                         break;
 180                 default:
 181                         return -EINVAL;
 182                 }
 183                 smu7_init_function_pointers(hwmgr);
 184                 break;
 185         case AMDGPU_FAMILY_AI:
 186                 switch (hwmgr->chip_id) {
 187                 case CHIP_VEGA10:
 188                         hwmgr->smumgr_funcs = &vega10_smu_funcs;
 189                         vega10_hwmgr_init(hwmgr);
 190                         break;
 191                 case CHIP_VEGA12:
 192                         hwmgr->smumgr_funcs = &vega12_smu_funcs;
 193                         vega12_hwmgr_init(hwmgr);
 194                         break;
 195                 default:
 196                         return -EINVAL;
 197                 }
 198                 break;
 199         case AMDGPU_FAMILY_RV:
 200                 switch (hwmgr->chip_id) {
 201                 case CHIP_RAVEN:
 202                         hwmgr->od_enabled = false;
 203                         hwmgr->smumgr_funcs = &smu10_smu_funcs;
 204                         smu10_init_function_pointers(hwmgr);
 205                         break;
 206                 default:
 207                         return -EINVAL;
 208                 }
 209                 break;
 210         default:
 211                 return -EINVAL;
 212         }
 213
 214         return 0;
 215 }
 216
 217 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
 218 {
 219         int ret = 0;
 220
 221         if (hwmgr == NULL)
 222                 return -EINVAL;
 223
 224         if (hwmgr->pptable_func == NULL ||
 225             hwmgr->pptable_func->pptable_init == NULL ||
 226             hwmgr->hwmgr_func->backend_init == NULL)
 227                 return -EINVAL;
 228
 229         ret = hwmgr->pptable_func->pptable_init(hwmgr);
 230         if (ret)
 231                 goto err;
 232
 233         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
 234         if (ret)
 235                 goto err1;
 236
 237         ret = psm_init_power_state_table(hwmgr);
 238         if (ret)
 239                 goto err2;
 240
 241         ret = phm_setup_asic(hwmgr);
 242         if (ret)
 243                 goto err2;
 244
 245         ret = phm_enable_dynamic_state_management(hwmgr);
 246         if (ret)
 247                 goto err2;
 248         ret = phm_start_thermal_controller(hwmgr);
 249         ret |= psm_set_performance_states(hwmgr);
 250         if (ret)
 251                 goto err2;
 252
 253         ret = phm_register_thermal_interrupt(hwmgr, &thermal_irq_src);
 254         if (ret)
 255                 goto err2;
 256
 257         return 0;
 258 err2:
 259         if (hwmgr->hwmgr_func->backend_fini)
 260                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 261 err1:
 262         if (hwmgr->pptable_func->pptable_fini)
 263                 hwmgr->pptable_func->pptable_fini(hwmgr);
 264 err:
 265         pr_err("amdgpu: powerplay initialization failed\n");
 266         return ret;
 267 }
 268
 269 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
 270 {
 271         if (hwmgr == NULL)
 272                 return -EINVAL;
 273
 274         phm_stop_thermal_controller(hwmgr);
 275         psm_set_boot_states(hwmgr);
 276         psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 277         phm_disable_dynamic_state_management(hwmgr);
 278         phm_disable_clock_power_gatings(hwmgr);
 279
 280         if (hwmgr->hwmgr_func->backend_fini)
 281                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 282         if (hwmgr->pptable_func->pptable_fini)
 283                 hwmgr->pptable_func->pptable_fini(hwmgr);
 284         return psm_fini_power_state_table(hwmgr);
 285 }
 286
 287 int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
 288 {
 289         int ret = 0;
 290
 291         if (hwmgr == NULL)
 292                 return -EINVAL;
 293
 294         phm_disable_smc_firmware_ctf(hwmgr);
 295         ret = psm_set_boot_states(hwmgr);
 296         if (ret)
 297                 return ret;
 298         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 299         if (ret)
 300                 return ret;
 301         ret = phm_power_down_asic(hwmgr);
 302
 303         return ret;
 304 }
 305
 306 int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
 307 {
 308         int ret = 0;
 309
 310         if (hwmgr == NULL)
 311                 return -EINVAL;
 312
 313         ret = phm_setup_asic(hwmgr);
 314         if (ret)
 315                 return ret;
 316
 317         ret = phm_enable_dynamic_state_management(hwmgr);
 318         if (ret)
 319                 return ret;
 320         ret = phm_start_thermal_controller(hwmgr);
 321         if (ret)
 322                 return ret;
 323
 324         ret |= psm_set_performance_states(hwmgr);
 325         if (ret)
 326                 return ret;
 327
 328         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 329
 330         return ret;
 331 }
 332
 333 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 334 {
 335         switch (state) {
 336         case POWER_STATE_TYPE_BATTERY:
 337                 return PP_StateUILabel_Battery;
 338         case POWER_STATE_TYPE_BALANCED:
 339                 return PP_StateUILabel_Balanced;
 340         case POWER_STATE_TYPE_PERFORMANCE:
 341                 return PP_StateUILabel_Performance;
 342         default:
 343                 return PP_StateUILabel_None;
 344         }
 345 }
 346
 347 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
 348                 enum amd_pm_state_type *user_state)
 349 {
 350         int ret = 0;
 351
 352         if (hwmgr == NULL)
 353                 return -EINVAL;
 354
 355         switch (task_id) {
 356         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
 357                 ret = phm_set_cpu_power_state(hwmgr);
 358                 if (ret)
 359                         return ret;
 360                 ret = psm_set_performance_states(hwmgr);
 361                 if (ret)
 362                         return ret;
 363                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 364                 break;
 365         case AMD_PP_TASK_ENABLE_USER_STATE:
 366         {
 367                 enum PP_StateUILabel requested_ui_label;
 368                 struct pp_power_state *requested_ps = NULL;
 369
 370                 if (user_state == NULL) {
 371                         ret = -EINVAL;
 372                         break;
 373                 }
 374
 375                 requested_ui_label = power_state_convert(*user_state);
 376                 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
 377                 if (ret)
 378                         return ret;
 379                 ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
 380                 break;
 381         }
 382         case AMD_PP_TASK_COMPLETE_INIT:
 383         case AMD_PP_TASK_READJUST_POWER_STATE:
 384                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 385                 break;
 386         default:
 387                 break;
 388         }
 389         return ret;
 390 }
 391
 392 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 393 {
 394         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 395
 396         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
 397         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
 398
 399 #if defined(CONFIG_ACPI)
 400         if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
 401                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 402 #endif
 403
 404         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 405                 PHM_PlatformCaps_DynamicPatchPowerState);
 406
 407         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 408                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 409
 410         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 411                         PHM_PlatformCaps_DynamicPowerManagement);
 412
 413         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 414                                         PHM_PlatformCaps_SMC);
 415
 416         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 417                                         PHM_PlatformCaps_DynamicUVDState);
 418
 419         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 420                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 421         return;
 422 }
 423
 424 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
 425 {
 426         if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
 427                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 428                         PHM_PlatformCaps_SclkDeepSleep);
 429         else
 430                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 431                         PHM_PlatformCaps_SclkDeepSleep);
 432
 433         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 434                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 435                             PHM_PlatformCaps_PowerContainment);
 436                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 437                         PHM_PlatformCaps_CAC);
 438         } else {
 439                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 440                             PHM_PlatformCaps_PowerContainment);
 441                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 442                         PHM_PlatformCaps_CAC);
 443         }
 444
 445         if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
 446                 hwmgr->od_enabled = true;
 447
 448         return 0;
 449 }
 450
 451 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 452 {
 453         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 454                                                 PHM_PlatformCaps_EVV);
 455         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 456                                                 PHM_PlatformCaps_SQRamping);
 457         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 458                                                 PHM_PlatformCaps_RegulatorHot);
 459
 460         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 461                                         PHM_PlatformCaps_AutomaticDCTransition);
 462
 463         if (hwmgr->chip_id != CHIP_POLARIS10)
 464                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 465                                         PHM_PlatformCaps_SPLLShutdownSupport);
 466
 467         if (hwmgr->chip_id != CHIP_POLARIS11) {
 468                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 469                                                         PHM_PlatformCaps_DBRamping);
 470                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 471                                                         PHM_PlatformCaps_TDRamping);
 472                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 473                                                         PHM_PlatformCaps_TCPRamping);
 474         }
 475         return 0;
 476 }
 477
 478 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 479 {
 480         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 481                                                 PHM_PlatformCaps_EVV);
 482         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 483                         PHM_PlatformCaps_SQRamping);
 484         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 485                         PHM_PlatformCaps_DBRamping);
 486         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 487                         PHM_PlatformCaps_TDRamping);
 488         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 489                         PHM_PlatformCaps_TCPRamping);
 490         return 0;
 491 }
 492
 493 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 494 {
 495         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 496                                                 PHM_PlatformCaps_EVV);
 497         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 498                         PHM_PlatformCaps_SQRamping);
 499         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 500                         PHM_PlatformCaps_DBRamping);
 501         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 502                         PHM_PlatformCaps_TDRamping);
 503         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 504                         PHM_PlatformCaps_TCPRamping);
 505
 506         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 507                       PHM_PlatformCaps_UVDPowerGating);
 508         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 509                       PHM_PlatformCaps_VCEPowerGating);
 510         return 0;
 511 }
 512
 513 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 514 {
 515         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 516                                                 PHM_PlatformCaps_EVV);
 517         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 518                         PHM_PlatformCaps_SQRamping);
 519         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 520                         PHM_PlatformCaps_DBRamping);
 521         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 522                         PHM_PlatformCaps_TDRamping);
 523         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 524                         PHM_PlatformCaps_TCPRamping);
 525         return 0;
 526 }
 527
 528 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 529 {
 530         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 531                         PHM_PlatformCaps_SQRamping);
 532         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 533                         PHM_PlatformCaps_DBRamping);
 534         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 535                         PHM_PlatformCaps_TDRamping);
 536         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 537                         PHM_PlatformCaps_TCPRamping);
 538         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 539                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
 540         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 541                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
 542         return 0;
 543 }