drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smu/smu_8_0_d.h"
  32 #include "smu8_fusion.h"
  33 #include "smu/smu_8_0_sh_mask.h"
  34 #include "smumgr.h"
  35 #include "hwmgr.h"
  36 #include "hardwaremanager.h"
  37 #include "cz_ppsmc.h"
  38 #include "cz_hwmgr.h"
  39 #include "power_state.h"
  40 #include "cz_clockpowergating.h"
  41
  42 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
  43 #define CURRENT_NB_VID_MASK 0xff000000
  44 #define CURRENT_NB_VID__SHIFT 24
  45 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
  46 #define CURRENT_GFX_VID_MASK 0xff000000
  47 #define CURRENT_GFX_VID__SHIFT 24
  48
  49 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
  50
  51 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
  52 {
  53         if (PhwCz_Magic != hw_ps->magic)
  54                 return NULL;
  55
  56         return (struct cz_power_state *)hw_ps;
  57 }
  58
  59 static const struct cz_power_state *cast_const_PhwCzPowerState(
  60                                 const struct pp_hw_power_state *hw_ps)
  61 {
  62         if (PhwCz_Magic != hw_ps->magic)
  63                 return NULL;
  64
  65         return (struct cz_power_state *)hw_ps;
  66 }
  67
  68 static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
  69                                         uint32_t clock, uint32_t msg)
  70 {
  71         int i = 0;
  72         struct phm_vce_clock_voltage_dependency_table *ptable =
  73                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
  74
  75         switch (msg) {
  76         case PPSMC_MSG_SetEclkSoftMin:
  77         case PPSMC_MSG_SetEclkHardMin:
  78                 for (i = 0; i < (int)ptable->count; i++) {
  79                         if (clock <= ptable->entries[i].ecclk)
  80                                 break;
  81                 }
  82                 break;
  83
  84         case PPSMC_MSG_SetEclkSoftMax:
  85         case PPSMC_MSG_SetEclkHardMax:
  86                 for (i = ptable->count - 1; i >= 0; i--) {
  87                         if (clock >= ptable->entries[i].ecclk)
  88                                 break;
  89                 }
  90                 break;
  91
  92         default:
  93                 break;
  94         }
  95
  96         return i;
  97 }
  98
  99 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
 100                                 uint32_t clock, uint32_t msg)
 101 {
 102         int i = 0;
 103         struct phm_clock_voltage_dependency_table *table =
 104                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 105
 106         switch (msg) {
 107         case PPSMC_MSG_SetSclkSoftMin:
 108         case PPSMC_MSG_SetSclkHardMin:
 109                 for (i = 0; i < (int)table->count; i++) {
 110                         if (clock <= table->entries[i].clk)
 111                                 break;
 112                 }
 113                 break;
 114
 115         case PPSMC_MSG_SetSclkSoftMax:
 116         case PPSMC_MSG_SetSclkHardMax:
 117                 for (i = table->count - 1; i >= 0; i--) {
 118                         if (clock >= table->entries[i].clk)
 119                                 break;
 120                 }
 121                 break;
 122
 123         default:
 124                 break;
 125         }
 126         return i;
 127 }
 128
 129 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
 130                                         uint32_t clock, uint32_t msg)
 131 {
 132         int i = 0;
 133         struct phm_uvd_clock_voltage_dependency_table *ptable =
 134                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 135
 136         switch (msg) {
 137         case PPSMC_MSG_SetUvdSoftMin:
 138         case PPSMC_MSG_SetUvdHardMin:
 139                 for (i = 0; i < (int)ptable->count; i++) {
 140                         if (clock <= ptable->entries[i].vclk)
 141                                 break;
 142                 }
 143                 break;
 144
 145         case PPSMC_MSG_SetUvdSoftMax:
 146         case PPSMC_MSG_SetUvdHardMax:
 147                 for (i = ptable->count - 1; i >= 0; i--) {
 148                         if (clock >= ptable->entries[i].vclk)
 149                                 break;
 150                 }
 151                 break;
 152
 153         default:
 154                 break;
 155         }
 156
 157         return i;
 158 }
 159
 160 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 161 {
 162         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 163
 164         if (cz_hwmgr->max_sclk_level == 0) {
 165                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
 166                 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
 167         }
 168
 169         return cz_hwmgr->max_sclk_level;
 170 }
 171
 172 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 173 {
 174         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 175         uint32_t i;
 176         struct cgs_system_info sys_info = {0};
 177         int result;
 178
 179         cz_hwmgr->gfx_ramp_step = 256*25/100;
 180         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 181
 182         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 183                 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
 184
 185         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
 186         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
 187         cz_hwmgr->clock_slow_down_freq = 25000;
 188         cz_hwmgr->skip_clock_slow_down = 1;
 189         cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
 190         cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
 191         cz_hwmgr->voting_rights_clients = 0x00C00033;
 192         cz_hwmgr->static_screen_threshold = 8;
 193         cz_hwmgr->ddi_power_gating_disabled = 0;
 194         cz_hwmgr->bapm_enabled = 1;
 195         cz_hwmgr->voltage_drop_threshold = 0;
 196         cz_hwmgr->gfx_power_gating_threshold = 500;
 197         cz_hwmgr->vce_slow_sclk_threshold = 20000;
 198         cz_hwmgr->dce_slow_sclk_threshold = 30000;
 199         cz_hwmgr->disable_driver_thermal_policy = 1;
 200         cz_hwmgr->disable_nb_ps3_in_battery = 0;
 201
 202         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 203                                                         PHM_PlatformCaps_ABM);
 204
 205         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 206                                     PHM_PlatformCaps_NonABMSupportInPPLib);
 207
 208         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 209                                         PHM_PlatformCaps_DynamicM3Arbiter);
 210
 211         cz_hwmgr->override_dynamic_mgpg = 1;
 212
 213         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 214                                   PHM_PlatformCaps_DynamicPatchPowerState);
 215
 216         cz_hwmgr->thermal_auto_throttling_treshold = 0;
 217         cz_hwmgr->tdr_clock = 0;
 218         cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
 219
 220         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 221                                         PHM_PlatformCaps_DynamicUVDState);
 222
 223         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 224                         PHM_PlatformCaps_UVDDPM);
 225         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_VCEDPM);
 227
 228         cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
 229         cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
 230         cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
 231         cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
 232
 233         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 234                                    PHM_PlatformCaps_DisableVoltageIsland);
 235
 236         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 237                       PHM_PlatformCaps_UVDPowerGating);
 238         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 239                       PHM_PlatformCaps_VCEPowerGating);
 240         sys_info.size = sizeof(struct cgs_system_info);
 241         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 242         result = cgs_query_system_info(hwmgr->device, &sys_info);
 243         if (!result) {
 244                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
 245                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 246                                       PHM_PlatformCaps_UVDPowerGating);
 247                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
 248                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 249                                       PHM_PlatformCaps_VCEPowerGating);
 250         }
 251
 252         return 0;
 253 }
 254
 255 static uint32_t cz_convert_8Bit_index_to_voltage(
 256                         struct pp_hwmgr *hwmgr, uint16_t voltage)
 257 {
 258         return 6200 - (voltage * 25);
 259 }
 260
 261 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 262                         struct phm_clock_and_voltage_limits *table)
 263 {
 264         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 265         struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
 266         struct phm_clock_voltage_dependency_table *dep_table =
 267                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 268
 269         if (dep_table->count > 0) {
 270                 table->sclk = dep_table->entries[dep_table->count-1].clk;
 271                 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
 272                    (uint16_t)dep_table->entries[dep_table->count-1].v);
 273         }
 274         table->mclk = sys_info->nbp_memory_clock[0];
 275         return 0;
 276 }
 277
 278 static int cz_init_dynamic_state_adjustment_rule_settings(
 279                         struct pp_hwmgr *hwmgr,
 280                         ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
 281 {
 282         uint32_t table_size =
 283                 sizeof(struct phm_clock_voltage_dependency_table) +
 284                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 285
 286         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 287                                         kzalloc(table_size, GFP_KERNEL);
 288
 289         if (NULL == table_clk_vlt) {
 290                 pr_err("Can not allocate memory!\n");
 291                 return -ENOMEM;
 292         }
 293
 294         table_clk_vlt->count = 8;
 295         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 296         table_clk_vlt->entries[0].v = 0;
 297         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 298         table_clk_vlt->entries[1].v = 1;
 299         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 300         table_clk_vlt->entries[2].v = 2;
 301         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 302         table_clk_vlt->entries[3].v = 3;
 303         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 304         table_clk_vlt->entries[4].v = 4;
 305         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 306         table_clk_vlt->entries[5].v = 5;
 307         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 308         table_clk_vlt->entries[6].v = 6;
 309         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 310         table_clk_vlt->entries[7].v = 7;
 311         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 312
 313         return 0;
 314 }
 315
 316 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
 317 {
 318         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 319         ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
 320         uint32_t i;
 321         int result = 0;
 322         uint8_t frev, crev;
 323         uint16_t size;
 324
 325         info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
 326                         hwmgr->device,
 327                         GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
 328                         &size, &frev, &crev);
 329
 330         if (crev != 9) {
 331                 pr_err("Unsupported IGP table: %d %d\n", frev, crev);
 332                 return -EINVAL;
 333         }
 334
 335         if (info == NULL) {
 336                 pr_err("Could not retrieve the Integrated System Info Table!\n");
 337                 return -EINVAL;
 338         }
 339
 340         cz_hwmgr->sys_info.bootup_uma_clock =
 341                                    le32_to_cpu(info->ulBootUpUMAClock);
 342
 343         cz_hwmgr->sys_info.bootup_engine_clock =
 344                                 le32_to_cpu(info->ulBootUpEngineClock);
 345
 346         cz_hwmgr->sys_info.dentist_vco_freq =
 347                                    le32_to_cpu(info->ulDentistVCOFreq);
 348
 349         cz_hwmgr->sys_info.system_config =
 350                                      le32_to_cpu(info->ulSystemConfig);
 351
 352         cz_hwmgr->sys_info.bootup_nb_voltage_index =
 353                                   le16_to_cpu(info->usBootUpNBVoltage);
 354
 355         cz_hwmgr->sys_info.htc_hyst_lmt =
 356                         (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
 357
 358         cz_hwmgr->sys_info.htc_tmp_lmt =
 359                         (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
 360
 361         if (cz_hwmgr->sys_info.htc_tmp_lmt <=
 362                         cz_hwmgr->sys_info.htc_hyst_lmt) {
 363                 pr_err("The htcTmpLmt should be larger than htcHystLmt.\n");
 364                 return -EINVAL;
 365         }
 366
 367         cz_hwmgr->sys_info.nb_dpm_enable =
 368                                 cz_hwmgr->enable_nb_ps_policy &&
 369                                 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
 370
 371         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 372                 if (i < CZ_NUM_NBPMEMORYCLOCK) {
 373                         cz_hwmgr->sys_info.nbp_memory_clock[i] =
 374                           le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
 375                 }
 376                 cz_hwmgr->sys_info.nbp_n_clock[i] =
 377                             le32_to_cpu(info->ulNbpStateNClkFreq[i]);
 378         }
 379
 380         for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
 381                 cz_hwmgr->sys_info.display_clock[i] =
 382                                         le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 383         }
 384
 385         /* Here use 4 levels, make sure not exceed */
 386         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 387                 cz_hwmgr->sys_info.nbp_voltage_index[i] =
 388                              le16_to_cpu(info->usNBPStateVoltage[i]);
 389         }
 390
 391         if (!cz_hwmgr->sys_info.nb_dpm_enable) {
 392                 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
 393                         if (i < CZ_NUM_NBPMEMORYCLOCK) {
 394                                 cz_hwmgr->sys_info.nbp_memory_clock[i] =
 395                                     cz_hwmgr->sys_info.nbp_memory_clock[0];
 396                         }
 397                         cz_hwmgr->sys_info.nbp_n_clock[i] =
 398                                     cz_hwmgr->sys_info.nbp_n_clock[0];
 399                         cz_hwmgr->sys_info.nbp_voltage_index[i] =
 400                                     cz_hwmgr->sys_info.nbp_voltage_index[0];
 401                 }
 402         }
 403
 404         if (le32_to_cpu(info->ulGPUCapInfo) &
 405                 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
 406                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 407                                     PHM_PlatformCaps_EnableDFSBypass);
 408         }
 409
 410         cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
 411
 412         cz_construct_max_power_limits_table (hwmgr,
 413                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 414
 415         cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
 416                                     &info->sDISPCLK_Voltage[0]);
 417
 418         return result;
 419 }
 420
 421 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 422 {
 423         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 424
 425         cz_hwmgr->boot_power_level.engineClock =
 426                                 cz_hwmgr->sys_info.bootup_engine_clock;
 427
 428         cz_hwmgr->boot_power_level.vddcIndex =
 429                         (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
 430
 431         cz_hwmgr->boot_power_level.dsDividerIndex = 0;
 432         cz_hwmgr->boot_power_level.ssDividerIndex = 0;
 433         cz_hwmgr->boot_power_level.allowGnbSlow = 1;
 434         cz_hwmgr->boot_power_level.forceNBPstate = 0;
 435         cz_hwmgr->boot_power_level.hysteresis_up = 0;
 436         cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
 437         cz_hwmgr->boot_power_level.display_wm = 0;
 438         cz_hwmgr->boot_power_level.vce_wm = 0;
 439
 440         return 0;
 441 }
 442
 443 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
 444                                         void *output, void *storage, int result)
 445 {
 446         return 0;
 447 }
 448
 449 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
 450                                        void *output, void *storage, int result)
 451 {
 452         struct SMU8_Fusion_ClkTable *clock_table;
 453         int ret;
 454         uint32_t i;
 455         void *table = NULL;
 456         pp_atomctrl_clock_dividers_kong dividers;
 457
 458         struct phm_clock_voltage_dependency_table *vddc_table =
 459                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 460         struct phm_clock_voltage_dependency_table *vdd_gfx_table =
 461                 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
 462         struct phm_acp_clock_voltage_dependency_table *acp_table =
 463                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 464         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
 465                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 466         struct phm_vce_clock_voltage_dependency_table *vce_table =
 467                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 468
 469         if (!hwmgr->need_pp_table_upload)
 470                 return 0;
 471
 472         ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
 473
 474         PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
 475                             "Fail to get clock table from SMU!", return -EINVAL;);
 476
 477         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 478
 479         /* patch clock table */
 480         PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 481                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 482         PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 483                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 484         PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 485                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 486         PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 487                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 488         PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 489                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 490
 491         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 492
 493                 /* vddc_sclk */
 494                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 495                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 496                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 497                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 498
 499                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 500                                                       clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 501                                                       &dividers);
 502
 503                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 504                         (uint8_t)dividers.pll_post_divider;
 505
 506                 /* vddgfx_sclk */
 507                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 508                         (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
 509
 510                 /* acp breakdown */
 511                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 512                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 513                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 514                         (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
 515
 516                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 517                                                       clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
 518                                                       &dividers);
 519
 520                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 521                         (uint8_t)dividers.pll_post_divider;
 522
 523
 524                 /* uvd breakdown */
 525                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 526                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 527                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 528                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 529
 530                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 531                                                       clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 532                                                       &dividers);
 533
 534                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 535                         (uint8_t)dividers.pll_post_divider;
 536
 537                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 538                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 539                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 540                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 541
 542                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 543                                                       clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 544                                                       &dividers);
 545
 546                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 547                         (uint8_t)dividers.pll_post_divider;
 548
 549                 /* vce breakdown */
 550                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 551                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 552                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 553                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 554
 555
 556                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 557                                                       clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 558                                                       &dividers);
 559
 560                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 561                         (uint8_t)dividers.pll_post_divider;
 562
 563         }
 564         ret = smum_upload_powerplay_table(hwmgr->smumgr);
 565
 566         return ret;
 567 }
 568
 569 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
 570                                  void *output, void *storage, int result)
 571 {
 572         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 573         struct phm_clock_voltage_dependency_table *table =
 574                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 575         unsigned long clock = 0, level;
 576
 577         if (NULL == table || table->count <= 0)
 578                 return -EINVAL;
 579
 580         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 581         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
 582
 583         level = cz_get_max_sclk_level(hwmgr) - 1;
 584
 585         if (level < table->count)
 586                 clock = table->entries[level].clk;
 587         else
 588                 clock = table->entries[table->count - 1].clk;
 589
 590         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 591         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
 592
 593         return 0;
 594 }
 595
 596 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
 597                                 void *output, void *storage, int result)
 598 {
 599         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 600         struct phm_uvd_clock_voltage_dependency_table *table =
 601                                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 602         unsigned long clock = 0, level;
 603
 604         if (NULL == table || table->count <= 0)
 605                 return -EINVAL;
 606
 607         cz_hwmgr->uvd_dpm.soft_min_clk = 0;
 608         cz_hwmgr->uvd_dpm.hard_min_clk = 0;
 609
 610         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
 611         level = smum_get_argument(hwmgr->smumgr);
 612
 613         if (level < table->count)
 614                 clock = table->entries[level].vclk;
 615         else
 616                 clock = table->entries[table->count - 1].vclk;
 617
 618         cz_hwmgr->uvd_dpm.soft_max_clk = clock;
 619         cz_hwmgr->uvd_dpm.hard_max_clk = clock;
 620
 621         return 0;
 622 }
 623
 624 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
 625                                 void *output, void *storage, int result)
 626 {
 627         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 628         struct phm_vce_clock_voltage_dependency_table *table =
 629                                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 630         unsigned long clock = 0, level;
 631
 632         if (NULL == table || table->count <= 0)
 633                 return -EINVAL;
 634
 635         cz_hwmgr->vce_dpm.soft_min_clk = 0;
 636         cz_hwmgr->vce_dpm.hard_min_clk = 0;
 637
 638         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
 639         level = smum_get_argument(hwmgr->smumgr);
 640
 641         if (level < table->count)
 642                 clock = table->entries[level].ecclk;
 643         else
 644                 clock = table->entries[table->count - 1].ecclk;
 645
 646         cz_hwmgr->vce_dpm.soft_max_clk = clock;
 647         cz_hwmgr->vce_dpm.hard_max_clk = clock;
 648
 649         return 0;
 650 }
 651
 652 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
 653                                 void *output, void *storage, int result)
 654 {
 655         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 656         struct phm_acp_clock_voltage_dependency_table *table =
 657                                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 658         unsigned long clock = 0, level;
 659
 660         if (NULL == table || table->count <= 0)
 661                 return -EINVAL;
 662
 663         cz_hwmgr->acp_dpm.soft_min_clk = 0;
 664         cz_hwmgr->acp_dpm.hard_min_clk = 0;
 665
 666         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
 667         level = smum_get_argument(hwmgr->smumgr);
 668
 669         if (level < table->count)
 670                 clock = table->entries[level].acpclk;
 671         else
 672                 clock = table->entries[table->count - 1].acpclk;
 673
 674         cz_hwmgr->acp_dpm.soft_max_clk = clock;
 675         cz_hwmgr->acp_dpm.hard_max_clk = clock;
 676         return 0;
 677 }
 678
 679 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 680                                 void *output, void *storage, int result)
 681 {
 682         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 683
 684         cz_hwmgr->uvd_power_gated = false;
 685         cz_hwmgr->vce_power_gated = false;
 686         cz_hwmgr->samu_power_gated = false;
 687         cz_hwmgr->acp_power_gated = false;
 688         cz_hwmgr->pgacpinit = true;
 689
 690         return 0;
 691 }
 692
 693 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
 694                                 void *output, void *storage, int result)
 695 {
 696         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 697
 698         cz_hwmgr->low_sclk_interrupt_threshold = 0;
 699
 700         return 0;
 701 }
 702 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
 703                                         void *input, void *output,
 704                                         void *storage, int result)
 705 {
 706         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 707         struct phm_clock_voltage_dependency_table *table =
 708                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 709
 710         unsigned long clock = 0;
 711         unsigned long level;
 712         unsigned long stable_pstate_sclk;
 713         unsigned long percentage;
 714
 715         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 716         level = cz_get_max_sclk_level(hwmgr) - 1;
 717
 718         if (level < table->count)
 719                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
 720         else
 721                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
 722
 723         clock = hwmgr->display_config.min_core_set_clock;
 724         if (clock == 0)
 725                 pr_info("min_core_set_clock not set\n");
 726
 727         if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
 728                 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
 729
 730                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 731                                                 PPSMC_MSG_SetSclkHardMin,
 732                                                  cz_get_sclk_level(hwmgr,
 733                                         cz_hwmgr->sclk_dpm.hard_min_clk,
 734                                              PPSMC_MSG_SetSclkHardMin));
 735         }
 736
 737         clock = cz_hwmgr->sclk_dpm.soft_min_clk;
 738
 739         /* update minimum clocks for Stable P-State feature */
 740         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 741                                      PHM_PlatformCaps_StablePState)) {
 742                 percentage = 75;
 743                 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
 744                 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
 745                                         percentage) / 100;
 746
 747                 if (clock < stable_pstate_sclk)
 748                         clock = stable_pstate_sclk;
 749         } else {
 750                 if (clock < hwmgr->gfx_arbiter.sclk)
 751                         clock = hwmgr->gfx_arbiter.sclk;
 752         }
 753
 754         if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
 755                 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
 756                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 757                                                 PPSMC_MSG_SetSclkSoftMin,
 758                                                 cz_get_sclk_level(hwmgr,
 759                                         cz_hwmgr->sclk_dpm.soft_min_clk,
 760                                              PPSMC_MSG_SetSclkSoftMin));
 761         }
 762
 763         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 764                                     PHM_PlatformCaps_StablePState) &&
 765                          cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
 766                 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 767                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 768                                                 PPSMC_MSG_SetSclkSoftMax,
 769                                                 cz_get_sclk_level(hwmgr,
 770                                         cz_hwmgr->sclk_dpm.soft_max_clk,
 771                                         PPSMC_MSG_SetSclkSoftMax));
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
 778                                         void *input, void *output,
 779                                         void *storage, int result)
 780 {
 781         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 782                                 PHM_PlatformCaps_SclkDeepSleep)) {
 783                 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
 784                 if (clks == 0)
 785                         clks = CZ_MIN_DEEP_SLEEP_SCLK;
 786
 787                 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
 788
 789                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 790                                 PPSMC_MSG_SetMinDeepSleepSclk,
 791                                 clks);
 792         }
 793
 794         return 0;
 795 }
 796
 797 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
 798                                         void *input, void *output,
 799                                         void *storage, int result)
 800 {
 801         struct cz_hwmgr *cz_hwmgr =
 802                                   (struct cz_hwmgr *)(hwmgr->backend);
 803
 804         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 805                                         PPSMC_MSG_SetWatermarkFrequency,
 806                                         cz_hwmgr->sclk_dpm.soft_max_clk);
 807
 808         return 0;
 809 }
 810
 811 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
 812                                         void *input, void *output,
 813                                         void *storage, int result)
 814 {
 815         return 0;
 816 }
 817
 818
 819 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
 820                                         void *input, void *output,
 821                                         void *storage, int result)
 822 {
 823         int ret = 0;
 824
 825         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 826         unsigned long dpm_features = 0;
 827
 828         if (!cz_hwmgr->is_nb_dpm_enabled) {
 829                 PP_DBG_LOG("enabling ALL SMU features.\n");
 830                 dpm_features |= NB_DPM_MASK;
 831                 ret = smum_send_msg_to_smc_with_parameter(
 832                                                           hwmgr->smumgr,
 833                                                           PPSMC_MSG_EnableAllSmuFeatures,
 834                                                           dpm_features);
 835                 if (ret == 0)
 836                         cz_hwmgr->is_nb_dpm_enabled = true;
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 843 {
 844         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 845
 846         if (hw_data->is_nb_dpm_enabled) {
 847                 if (enable) {
 848                         PP_DBG_LOG("enable Low Memory PState.\n");
 849
 850                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 851                                                 PPSMC_MSG_EnableLowMemoryPstate,
 852                                                 (lock ? 1 : 0));
 853                 } else {
 854                         PP_DBG_LOG("disable Low Memory PState.\n");
 855
 856                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 857                                                 PPSMC_MSG_DisableLowMemoryPstate,
 858                                                 (lock ? 1 : 0));
 859                 }
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
 866                                         void *input, void *output,
 867                                         void *storage, int result)
 868 {
 869         bool disable_switch;
 870         bool enable_low_mem_state;
 871         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 872         const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
 873         const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
 874
 875         if (hw_data->sys_info.nb_dpm_enable) {
 876                 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
 877                 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
 878
 879                 if (pnew_state->action == FORCE_HIGH)
 880                         cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
 881                 else if (pnew_state->action == CANCEL_FORCE_HIGH)
 882                         cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
 883                 else
 884                         cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
 885         }
 886         return 0;
 887 }
 888
 889 static const struct phm_master_table_item cz_set_power_state_list[] = {
 890         { .tableFunction = cz_tf_update_sclk_limit },
 891         { .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
 892         { .tableFunction = cz_tf_set_watermark_threshold },
 893         { .tableFunction = cz_tf_set_enabled_levels },
 894         { .tableFunction = cz_tf_enable_nb_dpm },
 895         { .tableFunction = cz_tf_update_low_mem_pstate },
 896         { }
 897 };
 898
 899 static const struct phm_master_table_header cz_set_power_state_master = {
 900         0,
 901         PHM_MasterTableFlag_None,
 902         cz_set_power_state_list
 903 };
 904
 905 static const struct phm_master_table_item cz_setup_asic_list[] = {
 906         { .tableFunction = cz_tf_reset_active_process_mask },
 907         { .tableFunction = cz_tf_upload_pptable_to_smu },
 908         { .tableFunction = cz_tf_init_sclk_limit },
 909         { .tableFunction = cz_tf_init_uvd_limit },
 910         { .tableFunction = cz_tf_init_vce_limit },
 911         { .tableFunction = cz_tf_init_acp_limit },
 912         { .tableFunction = cz_tf_init_power_gate_state },
 913         { .tableFunction = cz_tf_init_sclk_threshold },
 914         { }
 915 };
 916
 917 static const struct phm_master_table_header cz_setup_asic_master = {
 918         0,
 919         PHM_MasterTableFlag_None,
 920         cz_setup_asic_list
 921 };
 922
 923 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
 924                                         void *input, void *output,
 925                                         void *storage, int result)
 926 {
 927         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 928         hw_data->disp_clk_bypass_pending = false;
 929         hw_data->disp_clk_bypass = false;
 930
 931         return 0;
 932 }
 933
 934 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
 935                                         void *input, void *output,
 936                                         void *storage, int result)
 937 {
 938         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 939         hw_data->is_nb_dpm_enabled = false;
 940
 941         return 0;
 942 }
 943
 944 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 945                                         void *input, void *output,
 946                                         void *storage, int result)
 947 {
 948         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 949
 950         hw_data->cc6_settings.cc6_setting_changed = false;
 951         hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 952         hw_data->cc6_settings.cpu_cc6_disable = false;
 953         hw_data->cc6_settings.cpu_pstate_disable = false;
 954
 955         return 0;
 956 }
 957
 958 static const struct phm_master_table_item cz_power_down_asic_list[] = {
 959         { .tableFunction = cz_tf_power_up_display_clock_sys_pll },
 960         { .tableFunction = cz_tf_clear_nb_dpm_flag },
 961         { .tableFunction = cz_tf_reset_cc6_data },
 962         { }
 963 };
 964
 965 static const struct phm_master_table_header cz_power_down_asic_master = {
 966         0,
 967         PHM_MasterTableFlag_None,
 968         cz_power_down_asic_list
 969 };
 970
 971 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
 972                                 void *output, void *storage, int result)
 973 {
 974         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
 975                                 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
 976         return 0;
 977 }
 978
 979 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
 980                            void *storage, int result)
 981 {
 982         int res = 0xff;
 983         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 984         unsigned long dpm_features = 0;
 985
 986         cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
 987         dpm_features |= SCLK_DPM_MASK;
 988
 989         res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 990                                 PPSMC_MSG_EnableAllSmuFeatures,
 991                                 dpm_features);
 992
 993         return res;
 994 }
 995
 996 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
 997                                 void *output, void *storage, int result)
 998 {
 999         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1000
1001         cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1002         cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1003
1004         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1005                                 PPSMC_MSG_SetSclkSoftMin,
1006                                 cz_get_sclk_level(hwmgr,
1007                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1008                                 PPSMC_MSG_SetSclkSoftMin));
1009
1010         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1011                                 PPSMC_MSG_SetSclkSoftMax,
1012                                 cz_get_sclk_level(hwmgr,
1013                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1014                                 PPSMC_MSG_SetSclkSoftMax));
1015
1016         return 0;
1017 }
1018
1019 static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1020                                 void *output, void *storage, int result)
1021 {
1022         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1023
1024         cz_hwmgr->acp_boot_level = 0xff;
1025         return 0;
1026 }
1027
1028 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1029                                 unsigned long check_feature)
1030 {
1031         int result;
1032         unsigned long features;
1033
1034         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1035         if (result == 0) {
1036                 features = smum_get_argument(hwmgr->smumgr);
1037                 if (features & check_feature)
1038                         return true;
1039         }
1040
1041         return result;
1042 }
1043
1044 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1045                                 void *output, void *storage, int result)
1046 {
1047         if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1048                 return PP_Result_TableImmediateExit;
1049         return 0;
1050 }
1051
1052 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1053                                 void *output, void *storage, int result)
1054 {
1055         /* TO DO */
1056         return 0;
1057 }
1058
1059 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1060                                                 void *input, void *output,
1061                                                 void *storage, int result)
1062 {
1063         if (!cz_dpm_check_smu_features(hwmgr,
1064                              SMU_EnabledFeatureScoreboard_SclkDpmOn))
1065                 return PP_Result_TableImmediateExit;
1066         return 0;
1067 }
1068
1069 static const struct phm_master_table_item cz_disable_dpm_list[] = {
1070         { .tableFunction = cz_tf_check_for_dpm_enabled },
1071         { },
1072 };
1073
1074
1075 static const struct phm_master_table_header cz_disable_dpm_master = {
1076         0,
1077         PHM_MasterTableFlag_None,
1078         cz_disable_dpm_list
1079 };
1080
1081 static const struct phm_master_table_item cz_enable_dpm_list[] = {
1082         { .tableFunction = cz_tf_check_for_dpm_disabled },
1083         { .tableFunction = cz_tf_program_voting_clients },
1084         { .tableFunction = cz_tf_start_dpm },
1085         { .tableFunction = cz_tf_program_bootup_state },
1086         { .tableFunction = cz_tf_enable_didt },
1087         { .tableFunction = cz_tf_reset_acp_boot_level },
1088         { },
1089 };
1090
1091 static const struct phm_master_table_header cz_enable_dpm_master = {
1092         0,
1093         PHM_MasterTableFlag_None,
1094         cz_enable_dpm_list
1095 };
1096
1097 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1098                                 struct pp_power_state  *prequest_ps,
1099                         const struct pp_power_state *pcurrent_ps)
1100 {
1101         struct cz_power_state *cz_ps =
1102                                 cast_PhwCzPowerState(&prequest_ps->hardware);
1103
1104         const struct cz_power_state *cz_current_ps =
1105                                 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1106
1107         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1108         struct PP_Clocks clocks = {0, 0, 0, 0};
1109         bool force_high;
1110         uint32_t  num_of_active_displays = 0;
1111         struct cgs_display_info info = {0};
1112
1113         cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1114         cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1115
1116         cz_ps->need_dfs_bypass = true;
1117
1118         cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1119                                 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1120
1121         cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1122
1123         clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1124                                 hwmgr->display_config.min_mem_set_clock :
1125                                 cz_hwmgr->sys_info.nbp_memory_clock[1];
1126
1127         cgs_get_active_displays_info(hwmgr->device, &info);
1128         num_of_active_displays = info.display_count;
1129
1130         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1131                 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1132
1133         if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1134                 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1135
1136         force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1137                         || (num_of_active_displays >= 3);
1138
1139         cz_ps->action = cz_current_ps->action;
1140
1141         if (!force_high && (cz_ps->action == FORCE_HIGH))
1142                 cz_ps->action = CANCEL_FORCE_HIGH;
1143         else if (force_high && (cz_ps->action != FORCE_HIGH))
1144                 cz_ps->action = FORCE_HIGH;
1145         else
1146                 cz_ps->action = DO_NOTHING;
1147
1148         return 0;
1149 }
1150
1151 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1152 {
1153         int result = 0;
1154         struct cz_hwmgr *data;
1155
1156         data = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1157         if (data == NULL)
1158                 return -ENOMEM;
1159
1160         hwmgr->backend = data;
1161
1162         result = cz_initialize_dpm_defaults(hwmgr);
1163         if (result != 0) {
1164                 pr_err("cz_initialize_dpm_defaults failed\n");
1165                 return result;
1166         }
1167
1168         result = cz_get_system_info_data(hwmgr);
1169         if (result != 0) {
1170                 pr_err("cz_get_system_info_data failed\n");
1171                 return result;
1172         }
1173
1174         cz_construct_boot_state(hwmgr);
1175
1176         result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1177                                 &(hwmgr->setup_asic));
1178         if (result != 0) {
1179                 pr_err("Fail to construct setup ASIC\n");
1180                 return result;
1181         }
1182
1183         result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1184                                 &(hwmgr->power_down_asic));
1185         if (result != 0) {
1186                 pr_err("Fail to construct power down ASIC\n");
1187                 return result;
1188         }
1189
1190         result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1191                                 &(hwmgr->disable_dynamic_state_management));
1192         if (result != 0) {
1193                 pr_err("Fail to disable_dynamic_state\n");
1194                 return result;
1195         }
1196         result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1197                                 &(hwmgr->enable_dynamic_state_management));
1198         if (result != 0) {
1199                 pr_err("Fail to enable_dynamic_state\n");
1200                 return result;
1201         }
1202         result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1203                                 &(hwmgr->set_power_state));
1204         if (result != 0) {
1205                 pr_err("Fail to construct set_power_state\n");
1206                 return result;
1207         }
1208         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
1209
1210         result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1211         if (result != 0) {
1212                 pr_err("Fail to construct enable_clock_power_gatings\n");
1213                 return result;
1214         }
1215         return result;
1216 }
1217
1218 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1219 {
1220         if (hwmgr != NULL) {
1221                 phm_destroy_table(hwmgr, &(hwmgr->enable_clock_power_gatings));
1222                 phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
1223                 phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
1224                 phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
1225                 phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
1226                 phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
1227
1228                 if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
1229                         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
1230                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
1231                 }
1232
1233                 kfree(hwmgr->backend);
1234                 hwmgr->backend = NULL;
1235         }
1236         return 0;
1237 }
1238
1239 static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1240 {
1241         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1242
1243         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1244                                         PPSMC_MSG_SetSclkSoftMin,
1245                                         cz_get_sclk_level(hwmgr,
1246                                         cz_hwmgr->sclk_dpm.soft_max_clk,
1247                                         PPSMC_MSG_SetSclkSoftMin));
1248
1249         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1250                                 PPSMC_MSG_SetSclkSoftMax,
1251                                 cz_get_sclk_level(hwmgr,
1252                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1253                                 PPSMC_MSG_SetSclkSoftMax));
1254
1255         return 0;
1256 }
1257
1258 static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1259 {
1260         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1261         struct phm_clock_voltage_dependency_table *table =
1262                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1263         unsigned long clock = 0, level;
1264
1265         if (NULL == table || table->count <= 0)
1266                 return -EINVAL;
1267
1268         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1269         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1270
1271         level = cz_get_max_sclk_level(hwmgr) - 1;
1272
1273         if (level < table->count)
1274                 clock = table->entries[level].clk;
1275         else
1276                 clock = table->entries[table->count - 1].clk;
1277
1278         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1279         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1280
1281         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1282                                 PPSMC_MSG_SetSclkSoftMin,
1283                                 cz_get_sclk_level(hwmgr,
1284                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1285                                 PPSMC_MSG_SetSclkSoftMin));
1286
1287         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1288                                 PPSMC_MSG_SetSclkSoftMax,
1289                                 cz_get_sclk_level(hwmgr,
1290                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1291                                 PPSMC_MSG_SetSclkSoftMax));
1292
1293         return 0;
1294 }
1295
1296 static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1297 {
1298         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1299
1300         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1301                         PPSMC_MSG_SetSclkSoftMax,
1302                         cz_get_sclk_level(hwmgr,
1303                         cz_hwmgr->sclk_dpm.soft_min_clk,
1304                         PPSMC_MSG_SetSclkSoftMax));
1305
1306         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1307                                 PPSMC_MSG_SetSclkSoftMin,
1308                                 cz_get_sclk_level(hwmgr,
1309                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1310                                 PPSMC_MSG_SetSclkSoftMin));
1311
1312         return 0;
1313 }
1314
1315 static int cz_phm_force_dpm_sclk(struct pp_hwmgr *hwmgr, uint32_t sclk)
1316 {
1317         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1318                                 PPSMC_MSG_SetSclkSoftMin,
1319                                 cz_get_sclk_level(hwmgr,
1320                                 sclk,
1321                                 PPSMC_MSG_SetSclkSoftMin));
1322
1323         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1324                                 PPSMC_MSG_SetSclkSoftMax,
1325                                 cz_get_sclk_level(hwmgr,
1326                                 sclk,
1327                                 PPSMC_MSG_SetSclkSoftMax));
1328         return 0;
1329 }
1330
1331 static int cz_get_profiling_clk(struct pp_hwmgr *hwmgr, uint32_t *sclk)
1332 {
1333         struct phm_clock_voltage_dependency_table *table =
1334                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1335         int32_t tmp_sclk;
1336         int32_t count;
1337
1338         tmp_sclk = table->entries[table->count-1].clk * 70 / 100;
1339
1340         for (count = table->count-1; count >= 0; count--) {
1341                 if (tmp_sclk >= table->entries[count].clk) {
1342                         tmp_sclk = table->entries[count].clk;
1343                         *sclk = tmp_sclk;
1344                         break;
1345                 }
1346         }
1347         if (count < 0)
1348                 *sclk = table->entries[0].clk;
1349
1350         return 0;
1351 }
1352
1353 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1354                                 enum amd_dpm_forced_level level)
1355 {
1356         uint32_t sclk = 0;
1357         int ret = 0;
1358         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1359                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1360                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1361
1362         if (level == hwmgr->dpm_level)
1363                 return ret;
1364
1365         if (!(hwmgr->dpm_level & profile_mode_mask)) {
1366                 /* enter profile mode, save current level, disable gfx cg*/
1367                 if (level & profile_mode_mask) {
1368                         hwmgr->saved_dpm_level = hwmgr->dpm_level;
1369                         cgs_set_clockgating_state(hwmgr->device,
1370                                                 AMD_IP_BLOCK_TYPE_GFX,
1371                                                 AMD_CG_STATE_UNGATE);
1372                 }
1373         } else {
1374                 /* exit profile mode, restore level, enable gfx cg*/
1375                 if (!(level & profile_mode_mask)) {
1376                         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1377                                 level = hwmgr->saved_dpm_level;
1378                         cgs_set_clockgating_state(hwmgr->device,
1379                                         AMD_IP_BLOCK_TYPE_GFX,
1380                                         AMD_CG_STATE_GATE);
1381                 }
1382         }
1383
1384         switch (level) {
1385         case AMD_DPM_FORCED_LEVEL_HIGH:
1386         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1387                 ret = cz_phm_force_dpm_highest(hwmgr);
1388                 if (ret)
1389                         return ret;
1390                 hwmgr->dpm_level = level;
1391                 break;
1392         case AMD_DPM_FORCED_LEVEL_LOW:
1393         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1394                 ret = cz_phm_force_dpm_lowest(hwmgr);
1395                 if (ret)
1396                         return ret;
1397                 hwmgr->dpm_level = level;
1398                 break;
1399         case AMD_DPM_FORCED_LEVEL_AUTO:
1400                 ret = cz_phm_unforce_dpm_levels(hwmgr);
1401                 if (ret)
1402                         return ret;
1403                 hwmgr->dpm_level = level;
1404                 break;
1405         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1406                 ret = cz_get_profiling_clk(hwmgr, &sclk);
1407                 if (ret)
1408                         return ret;
1409                 hwmgr->dpm_level = level;
1410                 cz_phm_force_dpm_sclk(hwmgr, sclk);
1411                 break;
1412         case AMD_DPM_FORCED_LEVEL_MANUAL:
1413                 hwmgr->dpm_level = level;
1414                 break;
1415         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1416         default:
1417                 break;
1418         }
1419
1420         return ret;
1421 }
1422
1423 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1424 {
1425         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1426                                          PHM_PlatformCaps_UVDPowerGating))
1427                 return smum_send_msg_to_smc(hwmgr->smumgr,
1428                                                      PPSMC_MSG_UVDPowerOFF);
1429         return 0;
1430 }
1431
1432 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1433 {
1434         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1435                                          PHM_PlatformCaps_UVDPowerGating)) {
1436                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1437                                   PHM_PlatformCaps_UVDDynamicPowerGating)) {
1438                         return smum_send_msg_to_smc_with_parameter(
1439                                                                 hwmgr->smumgr,
1440                                                    PPSMC_MSG_UVDPowerON, 1);
1441                 } else {
1442                         return smum_send_msg_to_smc_with_parameter(
1443                                                                 hwmgr->smumgr,
1444                                                    PPSMC_MSG_UVDPowerON, 0);
1445                 }
1446         }
1447
1448         return 0;
1449 }
1450
1451 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1452 {
1453         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1454         struct phm_uvd_clock_voltage_dependency_table *ptable =
1455                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1456
1457         if (!bgate) {
1458                 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1459                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1460                                          PHM_PlatformCaps_StablePState)) {
1461                         cz_hwmgr->uvd_dpm.hard_min_clk =
1462                                    ptable->entries[ptable->count - 1].vclk;
1463
1464                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1465                                                      PPSMC_MSG_SetUvdHardMin,
1466                                                       cz_get_uvd_level(hwmgr,
1467                                              cz_hwmgr->uvd_dpm.hard_min_clk,
1468                                                    PPSMC_MSG_SetUvdHardMin));
1469
1470                         cz_enable_disable_uvd_dpm(hwmgr, true);
1471                 } else {
1472                         cz_enable_disable_uvd_dpm(hwmgr, true);
1473                 }
1474         } else {
1475                 cz_enable_disable_uvd_dpm(hwmgr, false);
1476         }
1477
1478         return 0;
1479 }
1480
1481 int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1482 {
1483         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1484         struct phm_vce_clock_voltage_dependency_table *ptable =
1485                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1486
1487         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1488         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1489                                          PHM_PlatformCaps_StablePState)) {
1490                 cz_hwmgr->vce_dpm.hard_min_clk =
1491                                   ptable->entries[ptable->count - 1].ecclk;
1492
1493                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1494                                         PPSMC_MSG_SetEclkHardMin,
1495                                         cz_get_eclk_level(hwmgr,
1496                                              cz_hwmgr->vce_dpm.hard_min_clk,
1497                                                 PPSMC_MSG_SetEclkHardMin));
1498         } else {
1499                 /*Program HardMin based on the vce_arbiter.ecclk */
1500                 if (hwmgr->vce_arbiter.ecclk == 0) {
1501                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1502                                             PPSMC_MSG_SetEclkHardMin, 0);
1503                 /* disable ECLK DPM 0. Otherwise VCE could hang if
1504                  * switching SCLK from DPM 0 to 6/7 */
1505                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1506                                         PPSMC_MSG_SetEclkSoftMin, 1);
1507                 } else {
1508                         cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1509                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1510                                                 PPSMC_MSG_SetEclkHardMin,
1511                                                 cz_get_eclk_level(hwmgr,
1512                                                 cz_hwmgr->vce_dpm.hard_min_clk,
1513                                                 PPSMC_MSG_SetEclkHardMin));
1514                 }
1515         }
1516         return 0;
1517 }
1518
1519 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1520 {
1521         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1522                                          PHM_PlatformCaps_VCEPowerGating))
1523                 return smum_send_msg_to_smc(hwmgr->smumgr,
1524                                                      PPSMC_MSG_VCEPowerOFF);
1525         return 0;
1526 }
1527
1528 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1529 {
1530         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1531                                          PHM_PlatformCaps_VCEPowerGating))
1532                 return smum_send_msg_to_smc(hwmgr->smumgr,
1533                                                      PPSMC_MSG_VCEPowerON);
1534         return 0;
1535 }
1536
1537 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1538 {
1539         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1540
1541         return cz_hwmgr->sys_info.bootup_uma_clock;
1542 }
1543
1544 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1545 {
1546         struct pp_power_state  *ps;
1547         struct cz_power_state  *cz_ps;
1548
1549         if (hwmgr == NULL)
1550                 return -EINVAL;
1551
1552         ps = hwmgr->request_ps;
1553
1554         if (ps == NULL)
1555                 return -EINVAL;
1556
1557         cz_ps = cast_PhwCzPowerState(&ps->hardware);
1558
1559         if (low)
1560                 return cz_ps->levels[0].engineClock;
1561         else
1562                 return cz_ps->levels[cz_ps->level-1].engineClock;
1563 }
1564
1565 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1566                                         struct pp_hw_power_state *hw_ps)
1567 {
1568         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1569         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1570
1571         cz_ps->level = 1;
1572         cz_ps->nbps_flags = 0;
1573         cz_ps->bapm_flags = 0;
1574         cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1575
1576         return 0;
1577 }
1578
1579 static int cz_dpm_get_pp_table_entry_callback(
1580                                                      struct pp_hwmgr *hwmgr,
1581                                            struct pp_hw_power_state *hw_ps,
1582                                                           unsigned int index,
1583                                                      const void *clock_info)
1584 {
1585         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1586
1587         const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1588
1589         struct phm_clock_voltage_dependency_table *table =
1590                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
1591         uint8_t clock_info_index = cz_clock_info->index;
1592
1593         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1594                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1595
1596         cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1597         cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1598
1599         cz_ps->level = index + 1;
1600
1601         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1602                 cz_ps->levels[index].dsDividerIndex = 5;
1603                 cz_ps->levels[index].ssDividerIndex = 5;
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1610 {
1611         int result;
1612         unsigned long ret = 0;
1613
1614         result = pp_tables_get_num_of_entries(hwmgr, &ret);
1615
1616         return result ? 0 : ret;
1617 }
1618
1619 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1620                     unsigned long entry, struct pp_power_state *ps)
1621 {
1622         int result;
1623         struct cz_power_state *cz_ps;
1624
1625         ps->hardware.magic = PhwCz_Magic;
1626
1627         cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1628
1629         result = pp_tables_get_entry(hwmgr, entry, ps,
1630                         cz_dpm_get_pp_table_entry_callback);
1631
1632         cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1633         cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1634
1635         return result;
1636 }
1637
1638 static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1639 {
1640         return sizeof(struct cz_power_state);
1641 }
1642
1643 static void cz_hw_print_display_cfg(
1644         const struct cc6_settings *cc6_settings)
1645 {
1646         PP_DBG_LOG("New Display Configuration:\n");
1647
1648         PP_DBG_LOG("   cpu_cc6_disable: %d\n",
1649                         cc6_settings->cpu_cc6_disable);
1650         PP_DBG_LOG("   cpu_pstate_disable: %d\n",
1651                         cc6_settings->cpu_pstate_disable);
1652         PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
1653                         cc6_settings->nb_pstate_switch_disable);
1654         PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
1655                         cc6_settings->cpu_pstate_separation_time);
1656 }
1657
1658  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1659 {
1660         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1661         uint32_t data = 0;
1662
1663         if (hw_data->cc6_settings.cc6_setting_changed) {
1664
1665                 hw_data->cc6_settings.cc6_setting_changed = false;
1666
1667                 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1668
1669                 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1670                         & PWRMGT_SEPARATION_TIME_MASK)
1671                         << PWRMGT_SEPARATION_TIME_SHIFT;
1672
1673                 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1674                         << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1675
1676                 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1677                         << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1678
1679                 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1680                         data);
1681
1682                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1683                                                 PPSMC_MSG_SetDisplaySizePowerParams,
1684                                                 data);
1685         }
1686
1687         return 0;
1688 }
1689
1690
1691 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1692                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1693 {
1694         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1695
1696         if (separation_time !=
1697             hw_data->cc6_settings.cpu_pstate_separation_time ||
1698             cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||
1699             pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||
1700             pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {
1701
1702                 hw_data->cc6_settings.cc6_setting_changed = true;
1703
1704                 hw_data->cc6_settings.cpu_pstate_separation_time =
1705                         separation_time;
1706                 hw_data->cc6_settings.cpu_cc6_disable =
1707                         cc6_disable;
1708                 hw_data->cc6_settings.cpu_pstate_disable =
1709                         pstate_disable;
1710                 hw_data->cc6_settings.nb_pstate_switch_disable =
1711                         pstate_switch_disable;
1712
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1719                 struct amd_pp_simple_clock_info *info)
1720 {
1721         uint32_t i;
1722         const struct phm_clock_voltage_dependency_table *table =
1723                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1724         const struct phm_clock_and_voltage_limits *limits =
1725                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1726
1727         info->engine_max_clock = limits->sclk;
1728         info->memory_max_clock = limits->mclk;
1729
1730         for (i = table->count - 1; i > 0; i--) {
1731                 if (limits->vddc >= table->entries[i].v) {
1732                         info->level = table->entries[i].clk;
1733                         return 0;
1734                 }
1735         }
1736         return -EINVAL;
1737 }
1738
1739 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1740                 enum pp_clock_type type, uint32_t mask)
1741 {
1742         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1743                 return -EINVAL;
1744
1745         switch (type) {
1746         case PP_SCLK:
1747                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1748                                 PPSMC_MSG_SetSclkSoftMin,
1749                                 mask);
1750                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1751                                 PPSMC_MSG_SetSclkSoftMax,
1752                                 mask);
1753                 break;
1754         default:
1755                 break;
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1762                 enum pp_clock_type type, char *buf)
1763 {
1764         struct phm_clock_voltage_dependency_table *sclk_table =
1765                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1766         int i, now, size = 0;
1767
1768         switch (type) {
1769         case PP_SCLK:
1770                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1771                                 CGS_IND_REG__SMC,
1772                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1773                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1774                                 CURR_SCLK_INDEX);
1775
1776                 for (i = 0; i < sclk_table->count; i++)
1777                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1778                                         i, sclk_table->entries[i].clk / 100,
1779                                         (i == now) ? "*" : "");
1780                 break;
1781         default:
1782                 break;
1783         }
1784         return size;
1785 }
1786
1787 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1788                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1789                                 PHM_PerformanceLevel *level)
1790 {
1791         const struct cz_power_state *ps;
1792         struct cz_hwmgr *data;
1793         uint32_t level_index;
1794         uint32_t i;
1795
1796         if (level == NULL || hwmgr == NULL || state == NULL)
1797                 return -EINVAL;
1798
1799         data = (struct cz_hwmgr *)(hwmgr->backend);
1800         ps = cast_const_PhwCzPowerState(state);
1801
1802         level_index = index > ps->level - 1 ? ps->level - 1 : index;
1803         level->coreClock = ps->levels[level_index].engineClock;
1804
1805         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1806                 for (i = 1; i < ps->level; i++) {
1807                         if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1808                                 level->coreClock = ps->levels[i].engineClock;
1809                                 break;
1810                         }
1811                 }
1812         }
1813
1814         if (level_index == 0)
1815                 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1816         else
1817                 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1818
1819         level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1820         level->nonLocalMemoryFreq = 0;
1821         level->nonLocalMemoryWidth = 0;
1822
1823         return 0;
1824 }
1825
1826 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1827         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1828 {
1829         const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1830
1831         clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1832         clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1833
1834         return 0;
1835 }
1836
1837 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1838                                                 struct amd_pp_clocks *clocks)
1839 {
1840         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1841         int i;
1842         struct phm_clock_voltage_dependency_table *table;
1843
1844         clocks->count = cz_get_max_sclk_level(hwmgr);
1845         switch (type) {
1846         case amd_pp_disp_clock:
1847                 for (i = 0; i < clocks->count; i++)
1848                         clocks->clock[i] = data->sys_info.display_clock[i];
1849                 break;
1850         case amd_pp_sys_clock:
1851                 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1852                 for (i = 0; i < clocks->count; i++)
1853                         clocks->clock[i] = table->entries[i].clk;
1854                 break;
1855         case amd_pp_mem_clock:
1856                 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1857                 for (i = 0; i < clocks->count; i++)
1858                         clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1859                 break;
1860         default:
1861                 return -1;
1862         }
1863
1864         return 0;
1865 }
1866
1867 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1868 {
1869         struct phm_clock_voltage_dependency_table *table =
1870                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1871         unsigned long level;
1872         const struct phm_clock_and_voltage_limits *limits =
1873                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1874
1875         if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1876                 return -EINVAL;
1877
1878         level = cz_get_max_sclk_level(hwmgr) - 1;
1879
1880         if (level < table->count)
1881                 clocks->engine_max_clock = table->entries[level].clk;
1882         else
1883                 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1884
1885         clocks->memory_max_clock = limits->mclk;
1886
1887         return 0;
1888 }
1889
1890 static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1891 {
1892         int actual_temp = 0;
1893         uint32_t val = cgs_read_ind_register(hwmgr->device,
1894                                              CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP);
1895         uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1896
1897         if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1898                 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1899         else
1900                 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1901
1902         return actual_temp;
1903 }
1904
1905 static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1906                           void *value, int *size)
1907 {
1908         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1909
1910         struct phm_clock_voltage_dependency_table *table =
1911                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1912
1913         struct phm_vce_clock_voltage_dependency_table *vce_table =
1914                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1915
1916         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1917                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1918
1919         uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1920                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1921         uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1922                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1923         uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1924                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1925
1926         uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1927         uint16_t vddnb, vddgfx;
1928         int result;
1929
1930         /* size must be at least 4 bytes for all sensors */
1931         if (*size < 4)
1932                 return -EINVAL;
1933         *size = 4;
1934
1935         switch (idx) {
1936         case AMDGPU_PP_SENSOR_GFX_SCLK:
1937                 if (sclk_index < NUM_SCLK_LEVELS) {
1938                         sclk = table->entries[sclk_index].clk;
1939                         *((uint32_t *)value) = sclk;
1940                         return 0;
1941                 }
1942                 return -EINVAL;
1943         case AMDGPU_PP_SENSOR_VDDNB:
1944                 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1945                         CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1946                 vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1947                 *((uint32_t *)value) = vddnb;
1948                 return 0;
1949         case AMDGPU_PP_SENSOR_VDDGFX:
1950                 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1951                         CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1952                 vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1953                 *((uint32_t *)value) = vddgfx;
1954                 return 0;
1955         case AMDGPU_PP_SENSOR_UVD_VCLK:
1956                 if (!cz_hwmgr->uvd_power_gated) {
1957                         if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1958                                 return -EINVAL;
1959                         } else {
1960                                 vclk = uvd_table->entries[uvd_index].vclk;
1961                                 *((uint32_t *)value) = vclk;
1962                                 return 0;
1963                         }
1964                 }
1965                 *((uint32_t *)value) = 0;
1966                 return 0;
1967         case AMDGPU_PP_SENSOR_UVD_DCLK:
1968                 if (!cz_hwmgr->uvd_power_gated) {
1969                         if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1970                                 return -EINVAL;
1971                         } else {
1972                                 dclk = uvd_table->entries[uvd_index].dclk;
1973                                 *((uint32_t *)value) = dclk;
1974                                 return 0;
1975                         }
1976                 }
1977                 *((uint32_t *)value) = 0;
1978                 return 0;
1979         case AMDGPU_PP_SENSOR_VCE_ECCLK:
1980                 if (!cz_hwmgr->vce_power_gated) {
1981                         if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1982                                 return -EINVAL;
1983                         } else {
1984                                 ecclk = vce_table->entries[vce_index].ecclk;
1985                                 *((uint32_t *)value) = ecclk;
1986                                 return 0;
1987                         }
1988                 }
1989                 *((uint32_t *)value) = 0;
1990                 return 0;
1991         case AMDGPU_PP_SENSOR_GPU_LOAD:
1992                 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1993                 if (0 == result) {
1994                         activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1995                         activity_percent = activity_percent > 100 ? 100 : activity_percent;
1996                 } else {
1997                         activity_percent = 50;
1998                 }
1999                 *((uint32_t *)value) = activity_percent;
2000                 return 0;
2001         case AMDGPU_PP_SENSOR_UVD_POWER:
2002                 *((uint32_t *)value) = cz_hwmgr->uvd_power_gated ? 0 : 1;
2003                 return 0;
2004         case AMDGPU_PP_SENSOR_VCE_POWER:
2005                 *((uint32_t *)value) = cz_hwmgr->vce_power_gated ? 0 : 1;
2006                 return 0;
2007         case AMDGPU_PP_SENSOR_GPU_TEMP:
2008                 *((uint32_t *)value) = cz_thermal_get_temperature(hwmgr);
2009                 return 0;
2010         default:
2011                 return -EINVAL;
2012         }
2013 }
2014
2015 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
2016         .backend_init = cz_hwmgr_backend_init,
2017         .backend_fini = cz_hwmgr_backend_fini,
2018         .asic_setup = NULL,
2019         .apply_state_adjust_rules = cz_apply_state_adjust_rules,
2020         .force_dpm_level = cz_dpm_force_dpm_level,
2021         .get_power_state_size = cz_get_power_state_size,
2022         .powerdown_uvd = cz_dpm_powerdown_uvd,
2023         .powergate_uvd = cz_dpm_powergate_uvd,
2024         .powergate_vce = cz_dpm_powergate_vce,
2025         .get_mclk = cz_dpm_get_mclk,
2026         .get_sclk = cz_dpm_get_sclk,
2027         .patch_boot_state = cz_dpm_patch_boot_state,
2028         .get_pp_table_entry = cz_dpm_get_pp_table_entry,
2029         .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
2030         .set_cpu_power_state = cz_set_cpu_power_state,
2031         .store_cc6_data = cz_store_cc6_data,
2032         .force_clock_level = cz_force_clock_level,
2033         .print_clock_levels = cz_print_clock_levels,
2034         .get_dal_power_level = cz_get_dal_power_level,
2035         .get_performance_level = cz_get_performance_level,
2036         .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
2037         .get_clock_by_type = cz_get_clock_by_type,
2038         .get_max_high_clocks = cz_get_max_high_clocks,
2039         .read_sensor = cz_read_sensor,
2040 };
2041
2042 int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
2043 {
2044         hwmgr->hwmgr_func = &cz_hwmgr_funcs;
2045         hwmgr->pptable_func = &pptable_funcs;
2046         return 0;
2047 }