drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corp
   4  *
   5  * Author:
   6  * Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 /* DC versions of linux includes */
  10 #include <include/drm_dsc_dc.h>
  11
  12 #define EXPORT_SYMBOL(symbol)   /* nothing */
  13 #define BUILD_BUG_ON(cond)      /* nothing */
  14 #define DIV_ROUND_UP(a, b)      (((b) + (a) - 1) / (b))
  15 #define ERANGE                  -1
  16 #define DRM_DEBUG_KMS(msg)      /* nothing */
  17 #define cpu_to_be16(__x) little_to_big(__x)
  18
  19 static unsigned short little_to_big(int data)
  20 {
  21         /* Swap lower and upper byte. DMCU uses big endian format. */
  22         return (0xff & (data >> 8)) + ((data & 0xff) << 8);
  23 }
  24
  25 /*
  26  * Everything below this comment was copied directly from drm_dsc.c.
  27  * Only the functions needed in DC are included.
  28  * Please keep this file synced with upstream.
  29  */
  30
  31 /**
  32  * DOC: dsc helpers
  33  *
  34  * These functions contain some common logic and helpers to deal with VESA
  35  * Display Stream Compression standard required for DSC on Display Port/eDP or
  36  * MIPI display interfaces.
  37  */
  38
  39 /**
  40  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
  41  *
  42  * @pps_payload:
  43  * Bitwise struct for DSC Picture Parameter Set. This is defined
  44  * by &struct drm_dsc_picture_parameter_set
  45  * @dsc_cfg:
  46  * DSC Configuration data filled by driver as defined by
  47  * &struct drm_dsc_config
  48  *
  49  * DSC source device sends a picture parameter set (PPS) containing the
  50  * information required by the sink to decode the compressed frame. Driver
  51  * populates the DSC PPS struct using the DSC configuration parameters in
  52  * the order expected by the DSC Display Sink device. For the DSC, the sink
  53  * device expects the PPS payload in big endian format for fields
  54  * that span more than 1 byte.
  55  */
  56 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
  57                                 const struct drm_dsc_config *dsc_cfg)
  58 {
  59         int i;
  60
  61         /* Protect against someone accidently changing struct size */
  62         BUILD_BUG_ON(sizeof(*pps_payload) !=
  63                      DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
  64
  65         memset(pps_payload, 0, sizeof(*pps_payload));
  66
  67         /* PPS 0 */
  68         pps_payload->dsc_version =
  69                 dsc_cfg->dsc_version_minor |
  70                 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
  71
  72         /* PPS 1, 2 is 0 */
  73
  74         /* PPS 3 */
  75         pps_payload->pps_3 =
  76                 dsc_cfg->line_buf_depth |
  77                 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
  78
  79         /* PPS 4 */
  80         pps_payload->pps_4 =
  81                 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
  82                  DSC_PPS_MSB_SHIFT) |
  83                 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
  84                 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
  85                 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
  86                 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
  87
  88         /* PPS 5 */
  89         pps_payload->bits_per_pixel_low =
  90                 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
  91
  92         /*
  93          * The DSC panel expects the PPS packet to have big endian format
  94          * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
  95          * to big endian format. If format is little endian, it will swap
  96          * bytes to convert to Big endian else keep it unchanged.
  97          */
  98
  99         /* PPS 6, 7 */
 100         pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
 101
 102         /* PPS 8, 9 */
 103         pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
 104
 105         /* PPS 10, 11 */
 106         pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
 107
 108         /* PPS 12, 13 */
 109         pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
 110
 111         /* PPS 14, 15 */
 112         pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
 113
 114         /* PPS 16 */
 115         pps_payload->initial_xmit_delay_high =
 116                 ((dsc_cfg->initial_xmit_delay &
 117                   DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
 118                  DSC_PPS_MSB_SHIFT);
 119
 120         /* PPS 17 */
 121         pps_payload->initial_xmit_delay_low =
 122                 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
 123
 124         /* PPS 18, 19 */
 125         pps_payload->initial_dec_delay =
 126                 cpu_to_be16(dsc_cfg->initial_dec_delay);
 127
 128         /* PPS 20 is 0 */
 129
 130         /* PPS 21 */
 131         pps_payload->initial_scale_value =
 132                 dsc_cfg->initial_scale_value;
 133
 134         /* PPS 22, 23 */
 135         pps_payload->scale_increment_interval =
 136                 cpu_to_be16(dsc_cfg->scale_increment_interval);
 137
 138         /* PPS 24 */
 139         pps_payload->scale_decrement_interval_high =
 140                 ((dsc_cfg->scale_decrement_interval &
 141                   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
 142                  DSC_PPS_MSB_SHIFT);
 143
 144         /* PPS 25 */
 145         pps_payload->scale_decrement_interval_low =
 146                 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
 147
 148         /* PPS 26[7:0], PPS 27[7:5] RESERVED */
 149
 150         /* PPS 27 */
 151         pps_payload->first_line_bpg_offset =
 152                 dsc_cfg->first_line_bpg_offset;
 153
 154         /* PPS 28, 29 */
 155         pps_payload->nfl_bpg_offset =
 156                 cpu_to_be16(dsc_cfg->nfl_bpg_offset);
 157
 158         /* PPS 30, 31 */
 159         pps_payload->slice_bpg_offset =
 160                 cpu_to_be16(dsc_cfg->slice_bpg_offset);
 161
 162         /* PPS 32, 33 */
 163         pps_payload->initial_offset =
 164                 cpu_to_be16(dsc_cfg->initial_offset);
 165
 166         /* PPS 34, 35 */
 167         pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
 168
 169         /* PPS 36 */
 170         pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
 171
 172         /* PPS 37 */
 173         pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
 174
 175         /* PPS 38, 39 */
 176         pps_payload->rc_model_size =
 177                 cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
 178
 179         /* PPS 40 */
 180         pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
 181
 182         /* PPS 41 */
 183         pps_payload->rc_quant_incr_limit0 =
 184                 dsc_cfg->rc_quant_incr_limit0;
 185
 186         /* PPS 42 */
 187         pps_payload->rc_quant_incr_limit1 =
 188                 dsc_cfg->rc_quant_incr_limit1;
 189
 190         /* PPS 43 */
 191         pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
 192                 DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
 193
 194         /* PPS 44 - 57 */
 195         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
 196                 pps_payload->rc_buf_thresh[i] =
 197                         dsc_cfg->rc_buf_thresh[i];
 198
 199         /* PPS 58 - 87 */
 200         /*
 201          * For DSC sink programming the RC Range parameter fields
 202          * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
 203          */
 204         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 205                 pps_payload->rc_range_parameters[i] =
 206                         ((dsc_cfg->rc_range_params[i].range_min_qp <<
 207                           DSC_PPS_RC_RANGE_MINQP_SHIFT) |
 208                          (dsc_cfg->rc_range_params[i].range_max_qp <<
 209                           DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
 210                          (dsc_cfg->rc_range_params[i].range_bpg_offset));
 211                 pps_payload->rc_range_parameters[i] =
 212                         cpu_to_be16(pps_payload->rc_range_parameters[i]);
 213         }
 214
 215         /* PPS 88 */
 216         pps_payload->native_422_420 = dsc_cfg->native_422 |
 217                 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
 218
 219         /* PPS 89 */
 220         pps_payload->second_line_bpg_offset =
 221                 dsc_cfg->second_line_bpg_offset;
 222
 223         /* PPS 90, 91 */
 224         pps_payload->nsl_bpg_offset =
 225                 cpu_to_be16(dsc_cfg->nsl_bpg_offset);
 226
 227         /* PPS 92, 93 */
 228         pps_payload->second_line_offset_adj =
 229                 cpu_to_be16(dsc_cfg->second_line_offset_adj);
 230
 231         /* PPS 94 - 127 are O */
 232 }
 233 EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
 234
 235 /**
 236  * drm_dsc_compute_rc_parameters() - Write rate control
 237  * parameters to the dsc configuration defined in
 238  * &struct drm_dsc_config in accordance with the DSC 1.2
 239  * specification. Some configuration fields must be present
 240  * beforehand.
 241  *
 242  * @vdsc_cfg:
 243  * DSC Configuration data partially filled by driver
 244  */
 245 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
 246 {
 247         unsigned long groups_per_line = 0;
 248         unsigned long groups_total = 0;
 249         unsigned long num_extra_mux_bits = 0;
 250         unsigned long slice_bits = 0;
 251         unsigned long hrd_delay = 0;
 252         unsigned long final_scale = 0;
 253         unsigned long rbs_min = 0;
 254
 255         if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
 256                 /* Number of groups used to code each line of a slice */
 257                 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
 258                                                DSC_RC_PIXELS_PER_GROUP);
 259
 260                 /* chunksize in Bytes */
 261                 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
 262                                                           vdsc_cfg->bits_per_pixel,
 263                                                           (8 * 16));
 264         } else {
 265                 /* Number of groups used to code each line of a slice */
 266                 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
 267                                                DSC_RC_PIXELS_PER_GROUP);
 268
 269                 /* chunksize in Bytes */
 270                 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
 271                                                           vdsc_cfg->bits_per_pixel,
 272                                                           (8 * 16));
 273         }
 274
 275         if (vdsc_cfg->convert_rgb)
 276                 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
 277                                           (4 * vdsc_cfg->bits_per_component + 4)
 278                                           - 2);
 279         else if (vdsc_cfg->native_422)
 280                 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
 281                         (4 * vdsc_cfg->bits_per_component + 4) +
 282                         3 * (4 * vdsc_cfg->bits_per_component) - 2;
 283         else
 284                 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
 285                         (4 * vdsc_cfg->bits_per_component + 4) +
 286                         2 * (4 * vdsc_cfg->bits_per_component) - 2;
 287         /* Number of bits in one Slice */
 288         slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
 289
 290         while ((num_extra_mux_bits > 0) &&
 291                ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
 292                 num_extra_mux_bits--;
 293
 294         if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
 295                 vdsc_cfg->initial_scale_value = groups_per_line + 8;
 296
 297         /* scale_decrement_interval calculation according to DSC spec 1.11 */
 298         if (vdsc_cfg->initial_scale_value > 8)
 299                 vdsc_cfg->scale_decrement_interval = groups_per_line /
 300                         (vdsc_cfg->initial_scale_value - 8);
 301         else
 302                 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
 303
 304         vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
 305                 (vdsc_cfg->initial_xmit_delay *
 306                  vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
 307
 308         if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
 309                 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
 310                 return -ERANGE;
 311         }
 312
 313         final_scale = (vdsc_cfg->rc_model_size * 8) /
 314                 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
 315         if (vdsc_cfg->slice_height > 1)
 316                 /*
 317                  * NflBpgOffset is 16 bit value with 11 fractional bits
 318                  * hence we multiply by 2^11 for preserving the
 319                  * fractional part
 320                  */
 321                 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
 322                                                         (vdsc_cfg->slice_height - 1));
 323         else
 324                 vdsc_cfg->nfl_bpg_offset = 0;
 325
 326         /* 2^16 - 1 */
 327         if (vdsc_cfg->nfl_bpg_offset > 65535) {
 328                 DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
 329                 return -ERANGE;
 330         }
 331
 332         /* Number of groups used to code the entire slice */
 333         groups_total = groups_per_line * vdsc_cfg->slice_height;
 334
 335         /* slice_bpg_offset is 16 bit value with 11 fractional bits */
 336         vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
 337                                                     vdsc_cfg->initial_offset +
 338                                                     num_extra_mux_bits) << 11),
 339                                                   groups_total);
 340
 341         if (final_scale > 9) {
 342                 /*
 343                  * ScaleIncrementInterval =
 344                  * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
 345                  * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
 346                  * we need divide by 2^11 from pstDscCfg values
 347                  */
 348                 vdsc_cfg->scale_increment_interval =
 349                                 (vdsc_cfg->final_offset * (1 << 11)) /
 350                                 ((vdsc_cfg->nfl_bpg_offset +
 351                                 vdsc_cfg->slice_bpg_offset) *
 352                                 (final_scale - 9));
 353         } else {
 354                 /*
 355                  * If finalScaleValue is less than or equal to 9, a value of 0 should
 356                  * be used to disable the scale increment at the end of the slice
 357                  */
 358                 vdsc_cfg->scale_increment_interval = 0;
 359         }
 360
 361         if (vdsc_cfg->scale_increment_interval > 65535) {
 362                 DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
 363                 return -ERANGE;
 364         }
 365
 366         /*
 367          * DSC spec mentions that bits_per_pixel specifies the target
 368          * bits/pixel (bpp) rate that is used by the encoder,
 369          * in steps of 1/16 of a bit per pixel
 370          */
 371         rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
 372                 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
 373                              vdsc_cfg->bits_per_pixel, 16) +
 374                 groups_per_line * vdsc_cfg->first_line_bpg_offset;
 375
 376         hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
 377         vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
 378         vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
 379
 380         /* As per DSC spec v1.2a recommendation: */
 381         if (vdsc_cfg->native_420)
 382                 vdsc_cfg->second_line_offset_adj = 512;
 383         else
 384                 vdsc_cfg->second_line_offset_adj = 0;
 385
 386         return 0;
 387 }
 388 EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);