drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dc_bios_types.h"
  28 #include "dcn10_stream_encoder.h"
  29 #include "reg_helper.h"
  30 #include "hw_shared.h"
  31
  32 #define DC_LOGGER \
  33                 enc1->base.ctx->logger
  34
  35
  36 #define REG(reg)\
  37         (enc1->regs->reg)
  38
  39 #undef FN
  40 #define FN(reg_name, field_name) \
  41         enc1->se_shift->field_name, enc1->se_mask->field_name
  42
  43 #define VBI_LINE_0 0
  44 #define DP_BLANK_MAX_RETRY 20
  45 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  46
  47
  48 enum {
  49         DP_MST_UPDATE_MAX_RETRY = 50
  50 };
  51
  52 #define CTX \
  53         enc1->base.ctx
  54
  55 void enc1_update_generic_info_packet(
  56         struct dcn10_stream_encoder *enc1,
  57         uint32_t packet_index,
  58         const struct dc_info_packet *info_packet)
  59 {
  60         uint32_t regval;
  61         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  62          * use 50 for now.
  63          */
  64         uint32_t max_retries = 50;
  65
  66         /*we need turn on clock before programming AFMT block*/
  67         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  68
  69         if (packet_index >= 8)
  70                 ASSERT(0);
  71
  72         /* poll dig_update_lock is not locked -> asic internal signal
  73          * assume otg master lock will unlock it
  74          */
  75 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  76                         0, 10, max_retries);*/
  77
  78         /* check if HW reading GSP memory */
  79         REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  80                         0, 10, max_retries);
  81
  82         /* HW does is not reading GSP memory not reading too long ->
  83          * something wrong. clear GPS memory access and notify?
  84          * hw SW is writing to GSP memory
  85          */
  86         REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  87
  88         /* choose which generic packet to use */
  89         regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
  90         REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
  91                         AFMT_GENERIC_INDEX, packet_index);
  92
  93         /* write generic packet header
  94          * (4th byte is for GENERIC0 only)
  95          */
  96         REG_SET_4(AFMT_GENERIC_HDR, 0,
  97                         AFMT_GENERIC_HB0, info_packet->hb0,
  98                         AFMT_GENERIC_HB1, info_packet->hb1,
  99                         AFMT_GENERIC_HB2, info_packet->hb2,
 100                         AFMT_GENERIC_HB3, info_packet->hb3);
 101
 102         /* write generic packet contents
 103          * (we never use last 4 bytes)
 104          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
 105          */
 106         {
 107                 const uint32_t *content =
 108                         (const uint32_t *) &info_packet->sb[0];
 109
 110                 REG_WRITE(AFMT_GENERIC_0, *content++);
 111                 REG_WRITE(AFMT_GENERIC_1, *content++);
 112                 REG_WRITE(AFMT_GENERIC_2, *content++);
 113                 REG_WRITE(AFMT_GENERIC_3, *content++);
 114                 REG_WRITE(AFMT_GENERIC_4, *content++);
 115                 REG_WRITE(AFMT_GENERIC_5, *content++);
 116                 REG_WRITE(AFMT_GENERIC_6, *content++);
 117                 REG_WRITE(AFMT_GENERIC_7, *content);
 118         }
 119
 120         switch (packet_index) {
 121         case 0:
 122                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 123                                 AFMT_GENERIC0_FRAME_UPDATE, 1);
 124                 break;
 125         case 1:
 126                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 127                                 AFMT_GENERIC1_FRAME_UPDATE, 1);
 128                 break;
 129         case 2:
 130                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 131                                 AFMT_GENERIC2_FRAME_UPDATE, 1);
 132                 break;
 133         case 3:
 134                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 135                                 AFMT_GENERIC3_FRAME_UPDATE, 1);
 136                 break;
 137         case 4:
 138                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 139                                 AFMT_GENERIC4_FRAME_UPDATE, 1);
 140                 break;
 141         case 5:
 142                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 143                                 AFMT_GENERIC5_FRAME_UPDATE, 1);
 144                 break;
 145         case 6:
 146                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 147                                 AFMT_GENERIC6_FRAME_UPDATE, 1);
 148                 break;
 149         case 7:
 150                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 151                                 AFMT_GENERIC7_FRAME_UPDATE, 1);
 152                 break;
 153         default:
 154                 break;
 155         }
 156 }
 157
 158 static void enc1_update_hdmi_info_packet(
 159         struct dcn10_stream_encoder *enc1,
 160         uint32_t packet_index,
 161         const struct dc_info_packet *info_packet)
 162 {
 163         uint32_t cont, send, line;
 164
 165         if (info_packet->valid) {
 166                 enc1_update_generic_info_packet(
 167                         enc1,
 168                         packet_index,
 169                         info_packet);
 170
 171                 /* enable transmission of packet(s) -
 172                  * packet transmission begins on the next frame
 173                  */
 174                 cont = 1;
 175                 /* send packet(s) every frame */
 176                 send = 1;
 177                 /* select line number to send packets on */
 178                 line = 2;
 179         } else {
 180                 cont = 0;
 181                 send = 0;
 182                 line = 0;
 183         }
 184
 185         /* choose which generic packet control to use */
 186         switch (packet_index) {
 187         case 0:
 188                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 189                                 HDMI_GENERIC0_CONT, cont,
 190                                 HDMI_GENERIC0_SEND, send,
 191                                 HDMI_GENERIC0_LINE, line);
 192                 break;
 193         case 1:
 194                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 195                                 HDMI_GENERIC1_CONT, cont,
 196                                 HDMI_GENERIC1_SEND, send,
 197                                 HDMI_GENERIC1_LINE, line);
 198                 break;
 199         case 2:
 200                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 201                                 HDMI_GENERIC0_CONT, cont,
 202                                 HDMI_GENERIC0_SEND, send,
 203                                 HDMI_GENERIC0_LINE, line);
 204                 break;
 205         case 3:
 206                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 207                                 HDMI_GENERIC1_CONT, cont,
 208                                 HDMI_GENERIC1_SEND, send,
 209                                 HDMI_GENERIC1_LINE, line);
 210                 break;
 211         case 4:
 212                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 213                                 HDMI_GENERIC0_CONT, cont,
 214                                 HDMI_GENERIC0_SEND, send,
 215                                 HDMI_GENERIC0_LINE, line);
 216                 break;
 217         case 5:
 218                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 219                                 HDMI_GENERIC1_CONT, cont,
 220                                 HDMI_GENERIC1_SEND, send,
 221                                 HDMI_GENERIC1_LINE, line);
 222                 break;
 223         case 6:
 224                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 225                                 HDMI_GENERIC0_CONT, cont,
 226                                 HDMI_GENERIC0_SEND, send,
 227                                 HDMI_GENERIC0_LINE, line);
 228                 break;
 229         case 7:
 230                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 231                                 HDMI_GENERIC1_CONT, cont,
 232                                 HDMI_GENERIC1_SEND, send,
 233                                 HDMI_GENERIC1_LINE, line);
 234                 break;
 235         default:
 236                 /* invalid HW packet index */
 237                 DC_LOG_WARNING(
 238                         "Invalid HW packet index: %s()\n",
 239                         __func__);
 240                 return;
 241         }
 242 }
 243
 244 /* setup stream encoder in dp mode */
 245 void enc1_stream_encoder_dp_set_stream_attribute(
 246         struct stream_encoder *enc,
 247         struct dc_crtc_timing *crtc_timing,
 248         enum dc_color_space output_color_space)
 249 {
 250         uint32_t h_active_start;
 251         uint32_t v_active_start;
 252         uint32_t misc0 = 0;
 253         uint32_t misc1 = 0;
 254         uint32_t h_blank;
 255         uint32_t h_back_porch;
 256         uint8_t synchronous_clock = 0; /* asynchronous mode */
 257         uint8_t colorimetry_bpc;
 258         uint8_t dynamic_range_rgb = 0; /*full range*/
 259         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 260
 261         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 262
 263         REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
 264
 265         /* set pixel encoding */
 266         switch (crtc_timing->pixel_encoding) {
 267         case PIXEL_ENCODING_YCBCR422:
 268                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 269                                 DP_PIXEL_ENCODING_TYPE_YCBCR422);
 270                 break;
 271         case PIXEL_ENCODING_YCBCR444:
 272                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 273                                 DP_PIXEL_ENCODING_TYPE_YCBCR444);
 274
 275                 if (crtc_timing->flags.Y_ONLY)
 276                         if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
 277                                 /* HW testing only, no use case yet.
 278                                  * Color depth of Y-only could be
 279                                  * 8, 10, 12, 16 bits
 280                                  */
 281                                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 282                                                 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
 283                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 284                  * of Y-only mode.
 285                  * This bit is set in HW if register
 286                  * DP_PIXEL_ENCODING is programmed to 0x4
 287                  */
 288                 break;
 289         case PIXEL_ENCODING_YCBCR420:
 290                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 291                                 DP_PIXEL_ENCODING_TYPE_YCBCR420);
 292                 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 293                 break;
 294         default:
 295                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 296                                 DP_PIXEL_ENCODING_TYPE_RGB444);
 297                 break;
 298         }
 299
 300         misc1 = REG_READ(DP_MSA_MISC);
 301
 302         /* set color depth */
 303
 304         switch (crtc_timing->display_color_depth) {
 305         case COLOR_DEPTH_666:
 306                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 307                                 0);
 308                 break;
 309         case COLOR_DEPTH_888:
 310                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 311                                 DP_COMPONENT_PIXEL_DEPTH_8BPC);
 312                 break;
 313         case COLOR_DEPTH_101010:
 314                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 315                                 DP_COMPONENT_PIXEL_DEPTH_10BPC);
 316
 317                 break;
 318         case COLOR_DEPTH_121212:
 319                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 320                                 DP_COMPONENT_PIXEL_DEPTH_12BPC);
 321                 break;
 322         default:
 323                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 324                                 DP_COMPONENT_PIXEL_DEPTH_6BPC);
 325                 break;
 326         }
 327
 328         /* set dynamic range and YCbCr range */
 329
 330         switch (crtc_timing->display_color_depth) {
 331         case COLOR_DEPTH_666:
 332                 colorimetry_bpc = 0;
 333                 break;
 334         case COLOR_DEPTH_888:
 335                 colorimetry_bpc = 1;
 336                 break;
 337         case COLOR_DEPTH_101010:
 338                 colorimetry_bpc = 2;
 339                 break;
 340         case COLOR_DEPTH_121212:
 341                 colorimetry_bpc = 3;
 342                 break;
 343         default:
 344                 colorimetry_bpc = 0;
 345                 break;
 346         }
 347
 348         misc0 = misc0 | synchronous_clock;
 349         misc0 = colorimetry_bpc << 5;
 350
 351         switch (output_color_space) {
 352         case COLOR_SPACE_SRGB:
 353                 misc0 = misc0 | 0x0;
 354                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 355                 dynamic_range_rgb = 0; /*full range*/
 356                 break;
 357         case COLOR_SPACE_SRGB_LIMITED:
 358                 misc0 = misc0 | 0x8; /* bit3=1 */
 359                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 360                 dynamic_range_rgb = 1; /*limited range*/
 361                 break;
 362         case COLOR_SPACE_YCBCR601:
 363         case COLOR_SPACE_YCBCR601_LIMITED:
 364                 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 365                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 366                 dynamic_range_ycbcr = 0; /*bt601*/
 367                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 368                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 369                 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
 370                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 371                 break;
 372         case COLOR_SPACE_YCBCR709:
 373         case COLOR_SPACE_YCBCR709_LIMITED:
 374                 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 375                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 376                 dynamic_range_ycbcr = 1; /*bt709*/
 377                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 378                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 379                 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
 380                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 381                 break;
 382         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 383                 dynamic_range_rgb = 1; /*limited range*/
 384                 break;
 385         case COLOR_SPACE_2020_RGB_FULLRANGE:
 386         case COLOR_SPACE_2020_YCBCR:
 387         case COLOR_SPACE_XR_RGB:
 388         case COLOR_SPACE_MSREF_SCRGB:
 389         case COLOR_SPACE_ADOBERGB:
 390         case COLOR_SPACE_DCIP3:
 391         case COLOR_SPACE_XV_YCC_709:
 392         case COLOR_SPACE_XV_YCC_601:
 393         case COLOR_SPACE_DISPLAYNATIVE:
 394         case COLOR_SPACE_DOLBYVISION:
 395         case COLOR_SPACE_APPCTRL:
 396         case COLOR_SPACE_CUSTOMPOINTS:
 397         case COLOR_SPACE_UNKNOWN:
 398                 /* do nothing */
 399                 break;
 400         }
 401
 402         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 403         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 404
 405         /* dcn new register
 406          * dc_crtc_timing is vesa dmt struct. data from edid
 407          */
 408         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 409                         DP_MSA_HTOTAL, crtc_timing->h_total,
 410                         DP_MSA_VTOTAL, crtc_timing->v_total);
 411
 412         /* calculate from vesa timing parameters
 413          * h_active_start related to leading edge of sync
 414          */
 415
 416         h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
 417                         crtc_timing->h_addressable - crtc_timing->h_border_right;
 418
 419         h_back_porch = h_blank - crtc_timing->h_front_porch -
 420                         crtc_timing->h_sync_width;
 421
 422         /* start at beginning of left border */
 423         h_active_start = crtc_timing->h_sync_width + h_back_porch;
 424
 425
 426         v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
 427                         crtc_timing->v_addressable - crtc_timing->v_border_bottom -
 428                         crtc_timing->v_front_porch;
 429
 430
 431         /* start at beginning of left border */
 432         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 433                 DP_MSA_HSTART, h_active_start,
 434                 DP_MSA_VSTART, v_active_start);
 435
 436         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 437                         DP_MSA_HSYNCWIDTH,
 438                         crtc_timing->h_sync_width,
 439                         DP_MSA_HSYNCPOLARITY,
 440                         !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
 441                         DP_MSA_VSYNCWIDTH,
 442                         crtc_timing->v_sync_width,
 443                         DP_MSA_VSYNCPOLARITY,
 444                         !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
 445
 446         /* HWDITH include border or overscan */
 447         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 448                 DP_MSA_HWIDTH, crtc_timing->h_border_left +
 449                 crtc_timing->h_addressable + crtc_timing->h_border_right,
 450                 DP_MSA_VHEIGHT, crtc_timing->v_border_top +
 451                 crtc_timing->v_addressable + crtc_timing->v_border_bottom);
 452 }
 453
 454 static void enc1_stream_encoder_set_stream_attribute_helper(
 455                 struct dcn10_stream_encoder *enc1,
 456                 struct dc_crtc_timing *crtc_timing)
 457 {
 458         switch (crtc_timing->pixel_encoding) {
 459         case PIXEL_ENCODING_YCBCR422:
 460                 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 461                 break;
 462         default:
 463                 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 464                 break;
 465         }
 466         REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 467 }
 468
 469 /* setup stream encoder in hdmi mode */
 470 void enc1_stream_encoder_hdmi_set_stream_attribute(
 471         struct stream_encoder *enc,
 472         struct dc_crtc_timing *crtc_timing,
 473         int actual_pix_clk_khz,
 474         bool enable_audio)
 475 {
 476         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 477         struct bp_encoder_control cntl = {0};
 478
 479         cntl.action = ENCODER_CONTROL_SETUP;
 480         cntl.engine_id = enc1->base.id;
 481         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 482         cntl.enable_dp_audio = enable_audio;
 483         cntl.pixel_clock = actual_pix_clk_khz;
 484         cntl.lanes_number = LANE_COUNT_FOUR;
 485
 486         if (enc1->base.bp->funcs->encoder_control(
 487                         enc1->base.bp, &cntl) != BP_RESULT_OK)
 488                 return;
 489
 490         enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
 491
 492         /* setup HDMI engine */
 493         REG_UPDATE_5(HDMI_CONTROL,
 494                 HDMI_PACKET_GEN_VERSION, 1,
 495                 HDMI_KEEPOUT_MODE, 1,
 496                 HDMI_DEEP_COLOR_ENABLE, 0,
 497                 HDMI_DATA_SCRAMBLE_EN, 0,
 498                 HDMI_CLOCK_CHANNEL_RATE, 0);
 499
 500
 501         switch (crtc_timing->display_color_depth) {
 502         case COLOR_DEPTH_888:
 503                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 504                 break;
 505         case COLOR_DEPTH_101010:
 506                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 507                         REG_UPDATE_2(HDMI_CONTROL,
 508                                         HDMI_DEEP_COLOR_DEPTH, 1,
 509                                         HDMI_DEEP_COLOR_ENABLE, 0);
 510                 } else {
 511                         REG_UPDATE_2(HDMI_CONTROL,
 512                                         HDMI_DEEP_COLOR_DEPTH, 1,
 513                                         HDMI_DEEP_COLOR_ENABLE, 1);
 514                         }
 515                 break;
 516         case COLOR_DEPTH_121212:
 517                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 518                         REG_UPDATE_2(HDMI_CONTROL,
 519                                         HDMI_DEEP_COLOR_DEPTH, 2,
 520                                         HDMI_DEEP_COLOR_ENABLE, 0);
 521                 } else {
 522                         REG_UPDATE_2(HDMI_CONTROL,
 523                                         HDMI_DEEP_COLOR_DEPTH, 2,
 524                                         HDMI_DEEP_COLOR_ENABLE, 1);
 525                         }
 526                 break;
 527         case COLOR_DEPTH_161616:
 528                 REG_UPDATE_2(HDMI_CONTROL,
 529                                 HDMI_DEEP_COLOR_DEPTH, 3,
 530                                 HDMI_DEEP_COLOR_ENABLE, 1);
 531                 break;
 532         default:
 533                 break;
 534         }
 535
 536         if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 537                 /* enable HDMI data scrambler
 538                  * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 539                  * Clock channel frequency is 1/4 of character rate.
 540                  */
 541                 REG_UPDATE_2(HDMI_CONTROL,
 542                         HDMI_DATA_SCRAMBLE_EN, 1,
 543                         HDMI_CLOCK_CHANNEL_RATE, 1);
 544         } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 545
 546                 /* TODO: New feature for DCE11, still need to implement */
 547
 548                 /* enable HDMI data scrambler
 549                  * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 550                  * Clock channel frequency is the same
 551                  * as character rate
 552                  */
 553                 REG_UPDATE_2(HDMI_CONTROL,
 554                         HDMI_DATA_SCRAMBLE_EN, 1,
 555                         HDMI_CLOCK_CHANNEL_RATE, 0);
 556         }
 557
 558
 559         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 560                 HDMI_GC_CONT, 1,
 561                 HDMI_GC_SEND, 1,
 562                 HDMI_NULL_SEND, 1);
 563
 564         /* following belongs to audio */
 565         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 566
 567         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 568
 569         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 570                                 VBI_LINE_0 + 2);
 571
 572         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 573 }
 574
 575 /* setup stream encoder in dvi mode */
 576 void enc1_stream_encoder_dvi_set_stream_attribute(
 577         struct stream_encoder *enc,
 578         struct dc_crtc_timing *crtc_timing,
 579         bool is_dual_link)
 580 {
 581         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 582         struct bp_encoder_control cntl = {0};
 583
 584         cntl.action = ENCODER_CONTROL_SETUP;
 585         cntl.engine_id = enc1->base.id;
 586         cntl.signal = is_dual_link ?
 587                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 588         cntl.enable_dp_audio = false;
 589         cntl.pixel_clock = crtc_timing->pix_clk_khz;
 590         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 591
 592         if (enc1->base.bp->funcs->encoder_control(
 593                         enc1->base.bp, &cntl) != BP_RESULT_OK)
 594                 return;
 595
 596         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 597         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 598         enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
 599 }
 600
 601 void enc1_stream_encoder_set_mst_bandwidth(
 602         struct stream_encoder *enc,
 603         struct fixed31_32 avg_time_slots_per_mtp)
 604 {
 605         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 606         uint32_t x = dc_fixpt_floor(
 607                 avg_time_slots_per_mtp);
 608         uint32_t y = dc_fixpt_ceil(
 609                 dc_fixpt_shl(
 610                         dc_fixpt_sub_int(
 611                                 avg_time_slots_per_mtp,
 612                                 x),
 613                         26));
 614
 615         REG_SET_2(DP_MSE_RATE_CNTL, 0,
 616                 DP_MSE_RATE_X, x,
 617                 DP_MSE_RATE_Y, y);
 618
 619         /* wait for update to be completed on the link */
 620         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 621         /* is reset to 0 (not pending) */
 622         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 623                         0,
 624                         10, DP_MST_UPDATE_MAX_RETRY);
 625 }
 626
 627 static void enc1_stream_encoder_update_hdmi_info_packets(
 628         struct stream_encoder *enc,
 629         const struct encoder_info_frame *info_frame)
 630 {
 631         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 632
 633         /* for bring up, disable dp double  TODO */
 634         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 635
 636         enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
 637         enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
 638         enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
 639         enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
 640         enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
 641 }
 642
 643 static void enc1_stream_encoder_stop_hdmi_info_packets(
 644         struct stream_encoder *enc)
 645 {
 646         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 647
 648         /* stop generic packets 0 & 1 on HDMI */
 649         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 650                 HDMI_GENERIC1_CONT, 0,
 651                 HDMI_GENERIC1_LINE, 0,
 652                 HDMI_GENERIC1_SEND, 0,
 653                 HDMI_GENERIC0_CONT, 0,
 654                 HDMI_GENERIC0_LINE, 0,
 655                 HDMI_GENERIC0_SEND, 0);
 656
 657         /* stop generic packets 2 & 3 on HDMI */
 658         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 659                 HDMI_GENERIC0_CONT, 0,
 660                 HDMI_GENERIC0_LINE, 0,
 661                 HDMI_GENERIC0_SEND, 0,
 662                 HDMI_GENERIC1_CONT, 0,
 663                 HDMI_GENERIC1_LINE, 0,
 664                 HDMI_GENERIC1_SEND, 0);
 665
 666         /* stop generic packets 2 & 3 on HDMI */
 667         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 668                 HDMI_GENERIC0_CONT, 0,
 669                 HDMI_GENERIC0_LINE, 0,
 670                 HDMI_GENERIC0_SEND, 0,
 671                 HDMI_GENERIC1_CONT, 0,
 672                 HDMI_GENERIC1_LINE, 0,
 673                 HDMI_GENERIC1_SEND, 0);
 674
 675         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 676                 HDMI_GENERIC0_CONT, 0,
 677                 HDMI_GENERIC0_LINE, 0,
 678                 HDMI_GENERIC0_SEND, 0,
 679                 HDMI_GENERIC1_CONT, 0,
 680                 HDMI_GENERIC1_LINE, 0,
 681                 HDMI_GENERIC1_SEND, 0);
 682 }
 683
 684 void enc1_stream_encoder_update_dp_info_packets(
 685         struct stream_encoder *enc,
 686         const struct encoder_info_frame *info_frame)
 687 {
 688         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 689         uint32_t value = 0;
 690
 691         if (info_frame->vsc.valid)
 692                 enc1_update_generic_info_packet(
 693                                         enc1,
 694                                         0,  /* packetIndex */
 695                                         &info_frame->vsc);
 696
 697         if (info_frame->spd.valid)
 698                 enc1_update_generic_info_packet(
 699                                 enc1,
 700                                 2,  /* packetIndex */
 701                                 &info_frame->spd);
 702
 703         if (info_frame->hdrsmd.valid)
 704                 enc1_update_generic_info_packet(
 705                                 enc1,
 706                                 3,  /* packetIndex */
 707                                 &info_frame->hdrsmd);
 708
 709         /* enable/disable transmission of packet(s).
 710          * If enabled, packet transmission begins on the next frame
 711          */
 712         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 713         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 714         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 715
 716
 717         /* This bit is the master enable bit.
 718          * When enabling secondary stream engine,
 719          * this master bit must also be set.
 720          * This register shared with audio info frame.
 721          * Therefore we need to enable master bit
 722          * if at least on of the fields is not 0
 723          */
 724         value = REG_READ(DP_SEC_CNTL);
 725         if (value)
 726                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 727 }
 728
 729 void enc1_stream_encoder_stop_dp_info_packets(
 730         struct stream_encoder *enc)
 731 {
 732         /* stop generic packets on DP */
 733         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 734         uint32_t value = 0;
 735
 736         REG_SET_10(DP_SEC_CNTL, 0,
 737                 DP_SEC_GSP0_ENABLE, 0,
 738                 DP_SEC_GSP1_ENABLE, 0,
 739                 DP_SEC_GSP2_ENABLE, 0,
 740                 DP_SEC_GSP3_ENABLE, 0,
 741                 DP_SEC_GSP4_ENABLE, 0,
 742                 DP_SEC_GSP5_ENABLE, 0,
 743                 DP_SEC_GSP6_ENABLE, 0,
 744                 DP_SEC_GSP7_ENABLE, 0,
 745                 DP_SEC_MPG_ENABLE, 0,
 746                 DP_SEC_STREAM_ENABLE, 0);
 747
 748         /* this register shared with audio info frame.
 749          * therefore we need to keep master enabled
 750          * if at least one of the fields is not 0 */
 751         value = REG_READ(DP_SEC_CNTL);
 752         if (value)
 753                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 754
 755 }
 756
 757 void enc1_stream_encoder_dp_blank(
 758         struct stream_encoder *enc)
 759 {
 760         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 761         uint32_t retries = 0;
 762         uint32_t  reg1 = 0;
 763         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 764
 765         /* Note: For CZ, we are changing driver default to disable
 766          * stream deferred to next VBLANK. If results are positive, we
 767          * will make the same change to all DCE versions. There are a
 768          * handful of panels that cannot handle disable stream at
 769          * HBLANK and will result in a white line flash across the
 770          * screen on stream disable.
 771          */
 772         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 773         if ((reg1 & 0x1) == 0)
 774                 /*stream not enabled*/
 775                 return;
 776         /* Specify the video stream disable point
 777          * (2 = start of the next vertical blank)
 778          */
 779         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 780         /* Larger delay to wait until VBLANK - use max retry of
 781          * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 782          * a little more because we may not trust delay accuracy.
 783          */
 784         max_retries = DP_BLANK_MAX_RETRY * 150;
 785
 786         /* disable DP stream */
 787         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 788
 789         /* the encoder stops sending the video stream
 790          * at the start of the vertical blanking.
 791          * Poll for DP_VID_STREAM_STATUS == 0
 792          */
 793
 794         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 795                         0,
 796                         10, max_retries);
 797
 798         ASSERT(retries <= max_retries);
 799
 800         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 801          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 802          * complete, stream status will be stuck in video stream enabled state,
 803          * i.e. DP_VID_STREAM_STATUS stuck at 1.
 804          */
 805
 806         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 807 }
 808
 809 /* output video stream to link encoder */
 810 void enc1_stream_encoder_dp_unblank(
 811         struct stream_encoder *enc,
 812         const struct encoder_unblank_param *param)
 813 {
 814         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 815
 816         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 817                 uint32_t n_vid = 0x8000;
 818                 uint32_t m_vid;
 819
 820                 /* M / N = Fstream / Flink
 821                  * m_vid / n_vid = pixel rate / link rate
 822                  */
 823
 824                 uint64_t m_vid_l = n_vid;
 825
 826                 m_vid_l *= param->pixel_clk_khz;
 827                 m_vid_l = div_u64(m_vid_l,
 828                         param->link_settings.link_rate
 829                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 830
 831                 m_vid = (uint32_t) m_vid_l;
 832
 833                 /* enable auto measurement */
 834
 835                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 836
 837                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 838                  * therefore program initial value for Mvid and Nvid
 839                  */
 840
 841                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
 842
 843                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 844
 845                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
 846         }
 847
 848         /* set DIG_START to 0x1 to resync FIFO */
 849
 850         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
 851
 852         /* switch DP encoder to CRTC data */
 853
 854         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 855
 856         /* wait 100us for DIG/DP logic to prime
 857          * (i.e. a few video lines)
 858          */
 859         udelay(100);
 860
 861         /* the hardware would start sending video at the start of the next DP
 862          * frame (i.e. rising edge of the vblank).
 863          * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
 864          * register has no effect on enable transition! HW always guarantees
 865          * VID_STREAM enable at start of next frame, and this is not
 866          * programmable
 867          */
 868
 869         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
 870 }
 871
 872 void enc1_stream_encoder_set_avmute(
 873         struct stream_encoder *enc,
 874         bool enable)
 875 {
 876         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 877         unsigned int value = enable ? 1 : 0;
 878
 879         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
 880 }
 881
 882
 883 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
 884 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
 885
 886 #include "include/audio_types.h"
 887
 888 /**
 889 * speakersToChannels
 890 *
 891 * @brief
 892 *  translate speakers to channels
 893 *
 894 *  FL  - Front Left
 895 *  FR  - Front Right
 896 *  RL  - Rear Left
 897 *  RR  - Rear Right
 898 *  RC  - Rear Center
 899 *  FC  - Front Center
 900 *  FLC - Front Left Center
 901 *  FRC - Front Right Center
 902 *  RLC - Rear Left Center
 903 *  RRC - Rear Right Center
 904 *  LFE - Low Freq Effect
 905 *
 906 *               FC
 907 *          FLC      FRC
 908 *    FL                    FR
 909 *
 910 *                    LFE
 911 *              ()
 912 *
 913 *
 914 *    RL                    RR
 915 *          RLC      RRC
 916 *               RC
 917 *
 918 *             ch  8   7   6   5   4   3   2   1
 919 * 0b00000011      -   -   -   -   -   -   FR  FL
 920 * 0b00000111      -   -   -   -   -   LFE FR  FL
 921 * 0b00001011      -   -   -   -   FC  -   FR  FL
 922 * 0b00001111      -   -   -   -   FC  LFE FR  FL
 923 * 0b00010011      -   -   -   RC  -   -   FR  FL
 924 * 0b00010111      -   -   -   RC  -   LFE FR  FL
 925 * 0b00011011      -   -   -   RC  FC  -   FR  FL
 926 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
 927 * 0b00110011      -   -   RR  RL  -   -   FR  FL
 928 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
 929 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
 930 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
 931 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
 932 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
 933 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
 934 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
 935 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
 936 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
 937 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
 938 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
 939 * 0b11000011      FRC FLC -   -   -   -   FR  FL
 940 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
 941 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
 942 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
 943 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
 944 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
 945 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
 946 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
 947 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
 948 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
 949 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
 950 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
 951 *
 952 * @param
 953 *  speakers - speaker information as it comes from CEA audio block
 954 */
 955 /* translate speakers to channels */
 956
 957 union audio_cea_channels {
 958         uint8_t all;
 959         struct audio_cea_channels_bits {
 960                 uint32_t FL:1;
 961                 uint32_t FR:1;
 962                 uint32_t LFE:1;
 963                 uint32_t FC:1;
 964                 uint32_t RL_RC:1;
 965                 uint32_t RR:1;
 966                 uint32_t RC_RLC_FLC:1;
 967                 uint32_t RRC_FRC:1;
 968         } channels;
 969 };
 970
 971 struct audio_clock_info {
 972         /* pixel clock frequency*/
 973         uint32_t pixel_clock_in_10khz;
 974         /* N - 32KHz audio */
 975         uint32_t n_32khz;
 976         /* CTS - 32KHz audio*/
 977         uint32_t cts_32khz;
 978         uint32_t n_44khz;
 979         uint32_t cts_44khz;
 980         uint32_t n_48khz;
 981         uint32_t cts_48khz;
 982 };
 983
 984 /* 25.2MHz/1.001*/
 985 /* 25.2MHz/1.001*/
 986 /* 25.2MHz*/
 987 /* 27MHz */
 988 /* 27MHz*1.001*/
 989 /* 27MHz*1.001*/
 990 /* 54MHz*/
 991 /* 54MHz*1.001*/
 992 /* 74.25MHz/1.001*/
 993 /* 74.25MHz*/
 994 /* 148.5MHz/1.001*/
 995 /* 148.5MHz*/
 996
 997 static const struct audio_clock_info audio_clock_info_table[16] = {
 998         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
 999         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1000         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1001         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1002         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1003         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1004         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1005         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1006         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1007         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1008         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1009         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1010         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1011         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1012         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1013         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1014 };
1015
1016 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1017         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1018         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1019         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1020         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1021         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1022         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1023         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1024         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1025         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1026         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1027         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1028         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1029         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1030         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1031 };
1032
1033 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1034         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1035         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1036         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1037         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1038         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1039         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1040         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1041         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1042         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1043         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1044         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1045         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1046         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1047         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1048
1049
1050 };
1051
1052 static union audio_cea_channels speakers_to_channels(
1053         struct audio_speaker_flags speaker_flags)
1054 {
1055         union audio_cea_channels cea_channels = {0};
1056
1057         /* these are one to one */
1058         cea_channels.channels.FL = speaker_flags.FL_FR;
1059         cea_channels.channels.FR = speaker_flags.FL_FR;
1060         cea_channels.channels.LFE = speaker_flags.LFE;
1061         cea_channels.channels.FC = speaker_flags.FC;
1062
1063         /* if Rear Left and Right exist move RC speaker to channel 7
1064          * otherwise to channel 5
1065          */
1066         if (speaker_flags.RL_RR) {
1067                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1068                 cea_channels.channels.RR = speaker_flags.RL_RR;
1069                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1070         } else {
1071                 cea_channels.channels.RL_RC = speaker_flags.RC;
1072         }
1073
1074         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1075         if (speaker_flags.FLC_FRC) {
1076                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1077                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1078         } else {
1079                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1080                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1081         }
1082
1083         return cea_channels;
1084 }
1085
1086 static uint32_t calc_max_audio_packets_per_line(
1087         const struct audio_crtc_info *crtc_info)
1088 {
1089         uint32_t max_packets_per_line;
1090
1091         max_packets_per_line =
1092                 crtc_info->h_total - crtc_info->h_active;
1093
1094         if (crtc_info->pixel_repetition)
1095                 max_packets_per_line *= crtc_info->pixel_repetition;
1096
1097         /* for other hdmi features */
1098         max_packets_per_line -= 58;
1099         /* for Control Period */
1100         max_packets_per_line -= 16;
1101         /* Number of Audio Packets per Line */
1102         max_packets_per_line /= 32;
1103
1104         return max_packets_per_line;
1105 }
1106
1107 static void get_audio_clock_info(
1108         enum dc_color_depth color_depth,
1109         uint32_t crtc_pixel_clock_in_khz,
1110         uint32_t actual_pixel_clock_in_khz,
1111         struct audio_clock_info *audio_clock_info)
1112 {
1113         const struct audio_clock_info *clock_info;
1114         uint32_t index;
1115         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1116         uint32_t audio_array_size;
1117
1118         switch (color_depth) {
1119         case COLOR_DEPTH_161616:
1120                 clock_info = audio_clock_info_table_48bpc;
1121                 audio_array_size = ARRAY_SIZE(
1122                                 audio_clock_info_table_48bpc);
1123                 break;
1124         case COLOR_DEPTH_121212:
1125                 clock_info = audio_clock_info_table_36bpc;
1126                 audio_array_size = ARRAY_SIZE(
1127                                 audio_clock_info_table_36bpc);
1128                 break;
1129         default:
1130                 clock_info = audio_clock_info_table;
1131                 audio_array_size = ARRAY_SIZE(
1132                                 audio_clock_info_table);
1133                 break;
1134         }
1135
1136         if (clock_info != NULL) {
1137                 /* search for exact pixel clock in table */
1138                 for (index = 0; index < audio_array_size; index++) {
1139                         if (clock_info[index].pixel_clock_in_10khz >
1140                                 crtc_pixel_clock_in_10khz)
1141                                 break;  /* not match */
1142                         else if (clock_info[index].pixel_clock_in_10khz ==
1143                                         crtc_pixel_clock_in_10khz) {
1144                                 /* match found */
1145                                 *audio_clock_info = clock_info[index];
1146                                 return;
1147                         }
1148                 }
1149         }
1150
1151         /* not found */
1152         if (actual_pixel_clock_in_khz == 0)
1153                 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1154
1155         /* See HDMI spec  the table entry under
1156          *  pixel clock of "Other". */
1157         audio_clock_info->pixel_clock_in_10khz =
1158                         actual_pixel_clock_in_khz / 10;
1159         audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1160         audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1161         audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1162
1163         audio_clock_info->n_32khz = 4096;
1164         audio_clock_info->n_44khz = 6272;
1165         audio_clock_info->n_48khz = 6144;
1166 }
1167
1168 static void enc1_se_audio_setup(
1169         struct stream_encoder *enc,
1170         unsigned int az_inst,
1171         struct audio_info *audio_info)
1172 {
1173         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1174
1175         uint32_t speakers = 0;
1176         uint32_t channels = 0;
1177
1178         ASSERT(audio_info);
1179         if (audio_info == NULL)
1180                 /* This should not happen.it does so we don't get BSOD*/
1181                 return;
1182
1183         speakers = audio_info->flags.info.ALLSPEAKERS;
1184         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1185
1186         /* setup the audio stream source select (audio -> dig mapping) */
1187         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1188
1189         /* Channel allocation */
1190         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1191 }
1192
1193 static void enc1_se_setup_hdmi_audio(
1194         struct stream_encoder *enc,
1195         const struct audio_crtc_info *crtc_info)
1196 {
1197         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1198
1199         struct audio_clock_info audio_clock_info = {0};
1200         uint32_t max_packets_per_line;
1201
1202         /* For now still do calculation, although this field is ignored when
1203          * above HDMI_PACKET_GEN_VERSION set to 1
1204          */
1205         max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1206
1207         /* HDMI_AUDIO_PACKET_CONTROL */
1208         REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1209                         HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1210                         HDMI_AUDIO_DELAY_EN, 1);
1211
1212         /* AFMT_AUDIO_PACKET_CONTROL */
1213         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1214
1215         /* AFMT_AUDIO_PACKET_CONTROL2 */
1216         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1217                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1218                         AFMT_60958_OSF_OVRD, 0);
1219
1220         /* HDMI_ACR_PACKET_CONTROL */
1221         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1222                         HDMI_ACR_AUTO_SEND, 1,
1223                         HDMI_ACR_SOURCE, 0,
1224                         HDMI_ACR_AUDIO_PRIORITY, 0);
1225
1226         /* Program audio clock sample/regeneration parameters */
1227         get_audio_clock_info(crtc_info->color_depth,
1228                              crtc_info->requested_pixel_clock,
1229                              crtc_info->calculated_pixel_clock,
1230                              &audio_clock_info);
1231         DC_LOG_HW_AUDIO(
1232                         "\n%s:Input::requested_pixel_clock = %d"        \
1233                         "calculated_pixel_clock = %d \n", __func__,     \
1234                         crtc_info->requested_pixel_clock,               \
1235                         crtc_info->calculated_pixel_clock);
1236
1237         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1238         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1239
1240         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1241         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1242
1243         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1244         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1245
1246         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1247         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1248
1249         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1250         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1251
1252         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1253         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1254
1255         /* Video driver cannot know in advance which sample rate will
1256          * be used by HD Audio driver
1257          * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1258          * programmed below in interruppt callback
1259          */
1260
1261         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1262          * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1263          */
1264         REG_UPDATE_2(AFMT_60958_0,
1265                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1266                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1267
1268         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1269         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1270
1271         /* AFMT_60958_2 now keep this settings until
1272          * Programming guide comes out
1273          */
1274         REG_UPDATE_6(AFMT_60958_2,
1275                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1276                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1277                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1278                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1279                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1280                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1281 }
1282
1283 static void enc1_se_setup_dp_audio(
1284         struct stream_encoder *enc)
1285 {
1286         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1287
1288         /* --- DP Audio packet configurations --- */
1289
1290         /* ATP Configuration */
1291         REG_SET(DP_SEC_AUD_N, 0,
1292                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1293
1294         /* Async/auto-calc timestamp mode */
1295         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1296                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1297
1298         /* --- The following are the registers
1299          *  copied from the SetupHDMI ---
1300          */
1301
1302         /* AFMT_AUDIO_PACKET_CONTROL */
1303         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1304
1305         /* AFMT_AUDIO_PACKET_CONTROL2 */
1306         /* Program the ATP and AIP next */
1307         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1308                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1309                         AFMT_60958_OSF_OVRD, 0);
1310
1311         /* AFMT_INFOFRAME_CONTROL0 */
1312         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1313
1314         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1315         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1316 }
1317
1318 static void enc1_se_enable_audio_clock(
1319         struct stream_encoder *enc,
1320         bool enable)
1321 {
1322         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1323
1324         if (REG(AFMT_CNTL) == 0)
1325                 return;   /* DCE8/10 does not have this register */
1326
1327         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1328
1329         /* wait for AFMT clock to turn on,
1330          * expectation: this should complete in 1-2 reads
1331          *
1332          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1333          *
1334          * TODO: wait for clock_on does not work well. May need HW
1335          * program sequence. But audio seems work normally even without wait
1336          * for clock_on status change
1337          */
1338 }
1339
1340 static void enc1_se_enable_dp_audio(
1341         struct stream_encoder *enc)
1342 {
1343         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1344
1345         /* Enable Audio packets */
1346         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1347
1348         /* Program the ATP and AIP next */
1349         REG_UPDATE_2(DP_SEC_CNTL,
1350                         DP_SEC_ATP_ENABLE, 1,
1351                         DP_SEC_AIP_ENABLE, 1);
1352
1353         /* Program STREAM_ENABLE after all the other enables. */
1354         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1355 }
1356
1357 static void enc1_se_disable_dp_audio(
1358         struct stream_encoder *enc)
1359 {
1360         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1361         uint32_t value = 0;
1362
1363         /* Disable Audio packets */
1364         REG_UPDATE_5(DP_SEC_CNTL,
1365                         DP_SEC_ASP_ENABLE, 0,
1366                         DP_SEC_ATP_ENABLE, 0,
1367                         DP_SEC_AIP_ENABLE, 0,
1368                         DP_SEC_ACM_ENABLE, 0,
1369                         DP_SEC_STREAM_ENABLE, 0);
1370
1371         /* This register shared with encoder info frame. Therefore we need to
1372          * keep master enabled if at least on of the fields is not 0
1373          */
1374         value = REG_READ(DP_SEC_CNTL);
1375         if (value != 0)
1376                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1377
1378 }
1379
1380 void enc1_se_audio_mute_control(
1381         struct stream_encoder *enc,
1382         bool mute)
1383 {
1384         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1385
1386         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1387 }
1388
1389 void enc1_se_dp_audio_setup(
1390         struct stream_encoder *enc,
1391         unsigned int az_inst,
1392         struct audio_info *info)
1393 {
1394         enc1_se_audio_setup(enc, az_inst, info);
1395 }
1396
1397 void enc1_se_dp_audio_enable(
1398         struct stream_encoder *enc)
1399 {
1400         enc1_se_enable_audio_clock(enc, true);
1401         enc1_se_setup_dp_audio(enc);
1402         enc1_se_enable_dp_audio(enc);
1403 }
1404
1405 void enc1_se_dp_audio_disable(
1406         struct stream_encoder *enc)
1407 {
1408         enc1_se_disable_dp_audio(enc);
1409         enc1_se_enable_audio_clock(enc, false);
1410 }
1411
1412 void enc1_se_hdmi_audio_setup(
1413         struct stream_encoder *enc,
1414         unsigned int az_inst,
1415         struct audio_info *info,
1416         struct audio_crtc_info *audio_crtc_info)
1417 {
1418         enc1_se_enable_audio_clock(enc, true);
1419         enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1420         enc1_se_audio_setup(enc, az_inst, info);
1421 }
1422
1423 void enc1_se_hdmi_audio_disable(
1424         struct stream_encoder *enc)
1425 {
1426         enc1_se_enable_audio_clock(enc, false);
1427 }
1428
1429
1430 void enc1_setup_stereo_sync(
1431         struct stream_encoder *enc,
1432         int tg_inst, bool enable)
1433 {
1434         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1435         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1436         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1437 }
1438
1439
1440 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1441         .dp_set_stream_attribute =
1442                 enc1_stream_encoder_dp_set_stream_attribute,
1443         .hdmi_set_stream_attribute =
1444                 enc1_stream_encoder_hdmi_set_stream_attribute,
1445         .dvi_set_stream_attribute =
1446                 enc1_stream_encoder_dvi_set_stream_attribute,
1447         .set_mst_bandwidth =
1448                 enc1_stream_encoder_set_mst_bandwidth,
1449         .update_hdmi_info_packets =
1450                 enc1_stream_encoder_update_hdmi_info_packets,
1451         .stop_hdmi_info_packets =
1452                 enc1_stream_encoder_stop_hdmi_info_packets,
1453         .update_dp_info_packets =
1454                 enc1_stream_encoder_update_dp_info_packets,
1455         .stop_dp_info_packets =
1456                 enc1_stream_encoder_stop_dp_info_packets,
1457         .dp_blank =
1458                 enc1_stream_encoder_dp_blank,
1459         .dp_unblank =
1460                 enc1_stream_encoder_dp_unblank,
1461         .audio_mute_control = enc1_se_audio_mute_control,
1462
1463         .dp_audio_setup = enc1_se_dp_audio_setup,
1464         .dp_audio_enable = enc1_se_dp_audio_enable,
1465         .dp_audio_disable = enc1_se_dp_audio_disable,
1466
1467         .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1468         .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1469         .setup_stereo_sync  = enc1_setup_stereo_sync,
1470         .set_avmute = enc1_stream_encoder_set_avmute,
1471 };
1472
1473 void dcn10_stream_encoder_construct(
1474         struct dcn10_stream_encoder *enc1,
1475         struct dc_context *ctx,
1476         struct dc_bios *bp,
1477         enum engine_id eng_id,
1478         const struct dcn10_stream_enc_registers *regs,
1479         const struct dcn10_stream_encoder_shift *se_shift,
1480         const struct dcn10_stream_encoder_mask *se_mask)
1481 {
1482         enc1->base.funcs = &dcn10_str_enc_funcs;
1483         enc1->base.ctx = ctx;
1484         enc1->base.id = eng_id;
1485         enc1->base.bp = bp;
1486         enc1->regs = regs;
1487         enc1->se_shift = se_shift;
1488         enc1->se_mask = se_mask;
1489 }
1490