drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dce_calcs.h"
  27 #include "reg_helper.h"
  28 #include "basics/conversion.h"
  29 #include "dcn10_hubp.h"
  30
  31 #define REG(reg)\
  32         hubp1->hubp_regs->reg
  33
  34 #define CTX \
  35         hubp1->base.ctx
  36
  37 #undef FN
  38 #define FN(reg_name, field_name) \
  39         hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
  40
  41 void hubp1_set_blank(struct hubp *hubp, bool blank)
  42 {
  43         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  44         uint32_t blank_en = blank ? 1 : 0;
  45
  46         REG_UPDATE_2(DCHUBP_CNTL,
  47                         HUBP_BLANK_EN, blank_en,
  48                         HUBP_TTU_DISABLE, blank_en);
  49
  50         if (blank) {
  51                 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
  52
  53                 if (reg_val) {
  54                         /* init sequence workaround: in case HUBP is
  55                          * power gated, this wait would timeout.
  56                          *
  57                          * we just wrote reg_val to non-0, if it stay 0
  58                          * it means HUBP is gated
  59                          */
  60                         REG_WAIT(DCHUBP_CNTL,
  61                                         HUBP_NO_OUTSTANDING_REQ, 1,
  62                                         1, 200);
  63                 }
  64
  65                 hubp->mpcc_id = 0xf;
  66                 hubp->opp_id = 0xf;
  67         }
  68 }
  69
  70 static void hubp1_disconnect(struct hubp *hubp)
  71 {
  72         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  73
  74         REG_UPDATE(DCHUBP_CNTL,
  75                         HUBP_TTU_DISABLE, 1);
  76
  77         REG_UPDATE(CURSOR_CONTROL,
  78                         CURSOR_ENABLE, 0);
  79 }
  80
  81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
  82 {
  83         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  84         uint32_t disable = disable_hubp ? 1 : 0;
  85
  86         REG_UPDATE(DCHUBP_CNTL,
  87                         HUBP_DISABLE, disable);
  88 }
  89
  90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
  91 {
  92         uint32_t hubp_underflow = 0;
  93         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  94
  95         REG_GET(DCHUBP_CNTL,
  96                 HUBP_UNDERFLOW_STATUS,
  97                 &hubp_underflow);
  98
  99         return hubp_underflow;
 100 }
 101
 102 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
 103 {
 104         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 105         uint32_t blank_en = blank ? 1 : 0;
 106
 107         REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
 108 }
 109
 110 static void hubp1_vready_workaround(struct hubp *hubp,
 111                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 112 {
 113         uint32_t value = 0;
 114         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 115
 116         /* set HBUBREQ_DEBUG_DB[12] = 1 */
 117         value = REG_READ(HUBPREQ_DEBUG_DB);
 118
 119         /* hack mode disable */
 120         value |= 0x100;
 121         value &= ~0x1000;
 122
 123         if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
 124                 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
 125                 /* if (eco_fix_needed(otg_global_sync_timing)
 126                  * set HBUBREQ_DEBUG_DB[12] = 1 */
 127                 value |= 0x1000;
 128         }
 129
 130         REG_WRITE(HUBPREQ_DEBUG_DB, value);
 131 }
 132
 133 void hubp1_program_tiling(
 134         struct hubp *hubp,
 135         const union dc_tiling_info *info,
 136         const enum surface_pixel_format pixel_format)
 137 {
 138         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 139
 140         REG_UPDATE_6(DCSURF_ADDR_CONFIG,
 141                         NUM_PIPES, log_2(info->gfx9.num_pipes),
 142                         NUM_BANKS, log_2(info->gfx9.num_banks),
 143                         PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
 144                         NUM_SE, log_2(info->gfx9.num_shader_engines),
 145                         NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
 146                         MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
 147
 148         REG_UPDATE_4(DCSURF_TILING_CONFIG,
 149                         SW_MODE, info->gfx9.swizzle,
 150                         META_LINEAR, info->gfx9.meta_linear,
 151                         RB_ALIGNED, info->gfx9.rb_aligned,
 152                         PIPE_ALIGNED, info->gfx9.pipe_aligned);
 153 }
 154
 155 void hubp1_program_size(
 156         struct hubp *hubp,
 157         enum surface_pixel_format format,
 158         const union plane_size *plane_size,
 159         struct dc_plane_dcc_param *dcc)
 160 {
 161         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 162         uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
 163
 164         /* Program data and meta surface pitch (calculation from addrlib)
 165          * 444 or 420 luma
 166          */
 167         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
 168                 ASSERT(plane_size->video.chroma_pitch != 0);
 169                 /* Chroma pitch zero can cause system hang! */
 170
 171                 pitch = plane_size->video.luma_pitch - 1;
 172                 meta_pitch = dcc->video.meta_pitch_l - 1;
 173                 pitch_c = plane_size->video.chroma_pitch - 1;
 174                 meta_pitch_c = dcc->video.meta_pitch_c - 1;
 175         } else {
 176                 pitch = plane_size->grph.surface_pitch - 1;
 177                 meta_pitch = dcc->grph.meta_pitch - 1;
 178                 pitch_c = 0;
 179                 meta_pitch_c = 0;
 180         }
 181
 182         if (!dcc->enable) {
 183                 meta_pitch = 0;
 184                 meta_pitch_c = 0;
 185         }
 186
 187         REG_UPDATE_2(DCSURF_SURFACE_PITCH,
 188                         PITCH, pitch, META_PITCH, meta_pitch);
 189
 190         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 191                 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
 192                         PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
 193 }
 194
 195 void hubp1_program_rotation(
 196         struct hubp *hubp,
 197         enum dc_rotation_angle rotation,
 198         bool horizontal_mirror)
 199 {
 200         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 201         uint32_t mirror;
 202
 203
 204         if (horizontal_mirror)
 205                 mirror = 1;
 206         else
 207                 mirror = 0;
 208
 209         /* Program rotation angle and horz mirror - no mirror */
 210         if (rotation == ROTATION_ANGLE_0)
 211                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 212                                 ROTATION_ANGLE, 0,
 213                                 H_MIRROR_EN, mirror);
 214         else if (rotation == ROTATION_ANGLE_90)
 215                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 216                                 ROTATION_ANGLE, 1,
 217                                 H_MIRROR_EN, mirror);
 218         else if (rotation == ROTATION_ANGLE_180)
 219                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 220                                 ROTATION_ANGLE, 2,
 221                                 H_MIRROR_EN, mirror);
 222         else if (rotation == ROTATION_ANGLE_270)
 223                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 224                                 ROTATION_ANGLE, 3,
 225                                 H_MIRROR_EN, mirror);
 226 }
 227
 228 void hubp1_program_pixel_format(
 229         struct hubp *hubp,
 230         enum surface_pixel_format format)
 231 {
 232         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 233         uint32_t red_bar = 3;
 234         uint32_t blue_bar = 2;
 235
 236         /* swap for ABGR format */
 237         if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 238                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 239                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
 240                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 241                 red_bar = 2;
 242                 blue_bar = 3;
 243         }
 244
 245         REG_UPDATE_2(HUBPRET_CONTROL,
 246                         CROSSBAR_SRC_CB_B, blue_bar,
 247                         CROSSBAR_SRC_CR_R, red_bar);
 248
 249         /* Mapping is same as ipp programming (cnvc) */
 250
 251         switch (format) {
 252         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 253                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 254                                 SURFACE_PIXEL_FORMAT, 1);
 255                 break;
 256         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 257                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 258                                 SURFACE_PIXEL_FORMAT, 3);
 259                 break;
 260         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 261         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 262                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 263                                 SURFACE_PIXEL_FORMAT, 8);
 264                 break;
 265         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 266         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 267         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 268                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 269                                 SURFACE_PIXEL_FORMAT, 10);
 270                 break;
 271         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 272                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 273                                 SURFACE_PIXEL_FORMAT, 22);
 274                 break;
 275         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 276         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
 277                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 278                                 SURFACE_PIXEL_FORMAT, 24);
 279                 break;
 280
 281         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 282                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 283                                 SURFACE_PIXEL_FORMAT, 65);
 284                 break;
 285         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 286                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 287                                 SURFACE_PIXEL_FORMAT, 64);
 288                 break;
 289         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 290                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 291                                 SURFACE_PIXEL_FORMAT, 67);
 292                 break;
 293         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 294                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 295                                 SURFACE_PIXEL_FORMAT, 66);
 296                 break;
 297         default:
 298                 BREAK_TO_DEBUGGER();
 299                 break;
 300         }
 301
 302         /* don't see the need of program the xbar in DCN 1.0 */
 303 }
 304
 305 bool hubp1_program_surface_flip_and_addr(
 306         struct hubp *hubp,
 307         const struct dc_plane_address *address,
 308         bool flip_immediate)
 309 {
 310         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 311
 312         /* program flip type */
 313         REG_SET(DCSURF_FLIP_CONTROL, 0,
 314                         SURFACE_FLIP_TYPE, flip_immediate);
 315
 316         /* HW automatically latch rest of address register on write to
 317          * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
 318          *
 319          * program high first and then the low addr, order matters!
 320          */
 321         switch (address->type) {
 322         case PLN_ADDR_TYPE_GRAPHICS:
 323                 /* DCN1.0 does not support const color
 324                  * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
 325                  * base on address->grph.dcc_const_color
 326                  * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
 327                  * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
 328                  */
 329
 330                 if (address->grph.addr.quad_part == 0)
 331                         break;
 332
 333                 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
 334                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 335                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
 336
 337                 if (address->grph.meta_addr.quad_part != 0) {
 338                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 339                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 340                                         address->grph.meta_addr.high_part);
 341
 342                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 343                                         PRIMARY_META_SURFACE_ADDRESS,
 344                                         address->grph.meta_addr.low_part);
 345                 }
 346
 347                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 348                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 349                                 address->grph.addr.high_part);
 350
 351                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 352                                 PRIMARY_SURFACE_ADDRESS,
 353                                 address->grph.addr.low_part);
 354                 break;
 355         case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
 356                 if (address->video_progressive.luma_addr.quad_part == 0
 357                         || address->video_progressive.chroma_addr.quad_part == 0)
 358                         break;
 359
 360                 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 361                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 362                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 363                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 364                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 365
 366                 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
 367                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
 368                                 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
 369                                 address->video_progressive.chroma_meta_addr.high_part);
 370
 371                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
 372                                 PRIMARY_META_SURFACE_ADDRESS_C,
 373                                 address->video_progressive.chroma_meta_addr.low_part);
 374
 375                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 376                                 PRIMARY_META_SURFACE_ADDRESS_HIGH,
 377                                 address->video_progressive.luma_meta_addr.high_part);
 378
 379                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 380                                 PRIMARY_META_SURFACE_ADDRESS,
 381                                 address->video_progressive.luma_meta_addr.low_part);
 382                 }
 383
 384                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
 385                         PRIMARY_SURFACE_ADDRESS_HIGH_C,
 386                         address->video_progressive.chroma_addr.high_part);
 387
 388                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
 389                         PRIMARY_SURFACE_ADDRESS_C,
 390                         address->video_progressive.chroma_addr.low_part);
 391
 392                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 393                         PRIMARY_SURFACE_ADDRESS_HIGH,
 394                         address->video_progressive.luma_addr.high_part);
 395
 396                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 397                         PRIMARY_SURFACE_ADDRESS,
 398                         address->video_progressive.luma_addr.low_part);
 399                 break;
 400         case PLN_ADDR_TYPE_GRPH_STEREO:
 401                 if (address->grph_stereo.left_addr.quad_part == 0)
 402                         break;
 403                 if (address->grph_stereo.right_addr.quad_part == 0)
 404                         break;
 405
 406                 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
 407                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 408                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 409                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 410                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
 411                                 SECONDARY_SURFACE_TMZ, address->tmz_surface,
 412                                 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
 413                                 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
 414                                 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
 415
 416                 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 417
 418                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
 419                                         SECONDARY_META_SURFACE_ADDRESS_HIGH,
 420                                         address->grph_stereo.right_meta_addr.high_part);
 421
 422                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
 423                                         SECONDARY_META_SURFACE_ADDRESS,
 424                                         address->grph_stereo.right_meta_addr.low_part);
 425                 }
 426                 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
 427
 428                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 429                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 430                                         address->grph_stereo.left_meta_addr.high_part);
 431
 432                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 433                                         PRIMARY_META_SURFACE_ADDRESS,
 434                                         address->grph_stereo.left_meta_addr.low_part);
 435                 }
 436
 437                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
 438                                 SECONDARY_SURFACE_ADDRESS_HIGH,
 439                                 address->grph_stereo.right_addr.high_part);
 440
 441                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
 442                                 SECONDARY_SURFACE_ADDRESS,
 443                                 address->grph_stereo.right_addr.low_part);
 444
 445                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 446                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 447                                 address->grph_stereo.left_addr.high_part);
 448
 449                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 450                                 PRIMARY_SURFACE_ADDRESS,
 451                                 address->grph_stereo.left_addr.low_part);
 452                 break;
 453         default:
 454                 BREAK_TO_DEBUGGER();
 455                 break;
 456         }
 457
 458         hubp->request_address = *address;
 459
 460         return true;
 461 }
 462
 463 void hubp1_dcc_control(struct hubp *hubp, bool enable,
 464                 bool independent_64b_blks)
 465 {
 466         uint32_t dcc_en = enable ? 1 : 0;
 467         uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
 468         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 469
 470         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 471                         PRIMARY_SURFACE_DCC_EN, dcc_en,
 472                         PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
 473                         SECONDARY_SURFACE_DCC_EN, dcc_en,
 474                         SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 475 }
 476
 477 void hubp1_program_surface_config(
 478         struct hubp *hubp,
 479         enum surface_pixel_format format,
 480         union dc_tiling_info *tiling_info,
 481         union plane_size *plane_size,
 482         enum dc_rotation_angle rotation,
 483         struct dc_plane_dcc_param *dcc,
 484         bool horizontal_mirror)
 485 {
 486         hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
 487         hubp1_program_tiling(hubp, tiling_info, format);
 488         hubp1_program_size(hubp, format, plane_size, dcc);
 489         hubp1_program_rotation(hubp, rotation, horizontal_mirror);
 490         hubp1_program_pixel_format(hubp, format);
 491 }
 492
 493 void hubp1_program_requestor(
 494                 struct hubp *hubp,
 495                 struct _vcs_dpi_display_rq_regs_st *rq_regs)
 496 {
 497         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 498
 499         REG_UPDATE(HUBPRET_CONTROL,
 500                         DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
 501         REG_SET_4(DCN_EXPANSION_MODE, 0,
 502                         DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
 503                         PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
 504                         MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
 505                         CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 506         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
 507                 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
 508                 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
 509                 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
 510                 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
 511                 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
 512                 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
 513                 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
 514                 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
 515         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
 516                 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
 517                 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
 518                 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
 519                 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
 520                 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
 521                 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
 522                 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
 523                 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
 524 }
 525
 526
 527 void hubp1_program_deadline(
 528                 struct hubp *hubp,
 529                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 530                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 531 {
 532         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 533
 534         /* DLG - Per hubp */
 535         REG_SET_2(BLANK_OFFSET_0, 0,
 536                 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
 537                 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
 538
 539         REG_SET(BLANK_OFFSET_1, 0,
 540                 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
 541
 542         REG_SET(DST_DIMENSIONS, 0,
 543                 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
 544
 545         REG_SET_2(DST_AFTER_SCALER, 0,
 546                 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
 547                 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
 548
 549         if (REG(PREFETCH_SETTINS))
 550                 REG_SET_2(PREFETCH_SETTINS, 0,
 551                         DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 552                         VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 553         else
 554                 REG_SET_2(PREFETCH_SETTINGS, 0,
 555                         DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 556                         VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 557
 558         REG_SET_2(VBLANK_PARAMETERS_0, 0,
 559                 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
 560                 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
 561
 562         REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
 563                 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
 564
 565         /* DLG - Per luma/chroma */
 566         REG_SET(VBLANK_PARAMETERS_1, 0,
 567                 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
 568
 569         REG_SET(VBLANK_PARAMETERS_3, 0,
 570                 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
 571
 572         if (REG(NOM_PARAMETERS_0))
 573                 REG_SET(NOM_PARAMETERS_0, 0,
 574                         DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
 575
 576         if (REG(NOM_PARAMETERS_1))
 577                 REG_SET(NOM_PARAMETERS_1, 0,
 578                         REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
 579
 580         REG_SET(NOM_PARAMETERS_4, 0,
 581                 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
 582
 583         REG_SET(NOM_PARAMETERS_5, 0,
 584                 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
 585
 586         REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
 587                 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
 588                 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
 589
 590         REG_SET_2(PER_LINE_DELIVERY, 0,
 591                 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
 592                 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
 593
 594         if (REG(PREFETCH_SETTINS_C))
 595                 REG_SET(PREFETCH_SETTINS_C, 0,
 596                         VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 597         else
 598                 REG_SET(PREFETCH_SETTINGS_C, 0,
 599                         VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 600
 601         REG_SET(VBLANK_PARAMETERS_2, 0,
 602                 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
 603
 604         REG_SET(VBLANK_PARAMETERS_4, 0,
 605                 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
 606
 607         if (REG(NOM_PARAMETERS_2))
 608                 REG_SET(NOM_PARAMETERS_2, 0,
 609                         DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
 610
 611         if (REG(NOM_PARAMETERS_3))
 612                 REG_SET(NOM_PARAMETERS_3, 0,
 613                         REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
 614
 615         REG_SET(NOM_PARAMETERS_6, 0,
 616                 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
 617
 618         REG_SET(NOM_PARAMETERS_7, 0,
 619                 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
 620
 621         /* TTU - per hubp */
 622         REG_SET_2(DCN_TTU_QOS_WM, 0,
 623                 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
 624                 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
 625
 626         REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
 627                 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
 628                 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
 629
 630         /* TTU - per luma/chroma */
 631         /* Assumed surf0 is luma and 1 is chroma */
 632
 633         REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
 634                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
 635                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
 636                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
 637
 638         REG_SET(DCN_SURF0_TTU_CNTL1, 0,
 639                 REFCYC_PER_REQ_DELIVERY_PRE,
 640                 ttu_attr->refcyc_per_req_delivery_pre_l);
 641
 642         REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
 643                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
 644                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
 645                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
 646
 647         REG_SET(DCN_SURF1_TTU_CNTL1, 0,
 648                 REFCYC_PER_REQ_DELIVERY_PRE,
 649                 ttu_attr->refcyc_per_req_delivery_pre_c);
 650
 651         REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
 652                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
 653                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
 654                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
 655         REG_SET(DCN_CUR0_TTU_CNTL1, 0,
 656                 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
 657 }
 658
 659 static void hubp1_setup(
 660                 struct hubp *hubp,
 661                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 662                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
 663                 struct _vcs_dpi_display_rq_regs_st *rq_regs,
 664                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 665 {
 666         /* otg is locked when this func is called. Register are double buffered.
 667          * disable the requestors is not needed
 668          */
 669         hubp1_program_requestor(hubp, rq_regs);
 670         hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
 671         hubp1_vready_workaround(hubp, pipe_dest);
 672 }
 673
 674 bool hubp1_is_flip_pending(struct hubp *hubp)
 675 {
 676         uint32_t flip_pending = 0;
 677         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 678         struct dc_plane_address earliest_inuse_address;
 679
 680         REG_GET(DCSURF_FLIP_CONTROL,
 681                         SURFACE_FLIP_PENDING, &flip_pending);
 682
 683         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
 684                         SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
 685
 686         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 687                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
 688
 689         if (flip_pending)
 690                 return true;
 691
 692         if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
 693                 return true;
 694
 695         return false;
 696 }
 697
 698 uint32_t aperture_default_system = 1;
 699 uint32_t context0_default_system; /* = 0;*/
 700
 701 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
 702                 struct vm_system_aperture_param *apt)
 703 {
 704         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 705         PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
 706         PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
 707         PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
 708
 709         mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
 710         mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
 711         mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
 712
 713         REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
 714                 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
 715                 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
 716         REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
 717                 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
 718
 719         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
 720                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
 721         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
 722                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
 723
 724         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
 725                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
 726         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
 727                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
 728 }
 729
 730 static void hubp1_set_vm_context0_settings(struct hubp *hubp,
 731                 const struct vm_context0_param *vm0)
 732 {
 733         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 734         /* pte base */
 735         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
 736                         VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
 737         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
 738                         VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
 739
 740         /* pte start */
 741         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
 742                         VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
 743         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
 744                         VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
 745
 746         /* pte end */
 747         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
 748                         VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
 749         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
 750                         VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
 751
 752         /* fault handling */
 753         REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
 754                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
 755                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
 756         REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
 757                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
 758
 759         /* control: enable VM PTE*/
 760         REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 761                         ENABLE_L1_TLB, 1,
 762                         SYSTEM_ACCESS_MODE, 3);
 763 }
 764
 765 void min_set_viewport(
 766         struct hubp *hubp,
 767         const struct rect *viewport,
 768         const struct rect *viewport_c)
 769 {
 770         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 771
 772         REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
 773                   PRI_VIEWPORT_WIDTH, viewport->width,
 774                   PRI_VIEWPORT_HEIGHT, viewport->height);
 775
 776         REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
 777                   PRI_VIEWPORT_X_START, viewport->x,
 778                   PRI_VIEWPORT_Y_START, viewport->y);
 779
 780         /*for stereo*/
 781         REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
 782                   SEC_VIEWPORT_WIDTH, viewport->width,
 783                   SEC_VIEWPORT_HEIGHT, viewport->height);
 784
 785         REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
 786                   SEC_VIEWPORT_X_START, viewport->x,
 787                   SEC_VIEWPORT_Y_START, viewport->y);
 788
 789         /* DC supports NV12 only at the moment */
 790         REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
 791                   PRI_VIEWPORT_WIDTH_C, viewport_c->width,
 792                   PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
 793
 794         REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
 795                   PRI_VIEWPORT_X_START_C, viewport_c->x,
 796                   PRI_VIEWPORT_Y_START_C, viewport_c->y);
 797 }
 798
 799 void hubp1_read_state(struct hubp *hubp)
 800 {
 801         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 802         struct dcn_hubp_state *s = &hubp1->state;
 803         struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
 804         struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
 805         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 806
 807         /* Requester */
 808         REG_GET(HUBPRET_CONTROL,
 809                         DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
 810         REG_GET_4(DCN_EXPANSION_MODE,
 811                         DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
 812                         PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
 813                         MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
 814                         CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
 815         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
 816                 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
 817                 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
 818                 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
 819                 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
 820                 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
 821                 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
 822                 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
 823                 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
 824         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
 825                 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
 826                 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
 827                 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
 828                 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
 829                 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
 830                 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
 831                 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
 832                 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
 833
 834         /* DLG - Per hubp */
 835         REG_GET_2(BLANK_OFFSET_0,
 836                 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
 837                 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
 838
 839         REG_GET(BLANK_OFFSET_1,
 840                 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
 841
 842         REG_GET(DST_DIMENSIONS,
 843                 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
 844
 845         REG_GET_2(DST_AFTER_SCALER,
 846                 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
 847                 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
 848
 849         if (REG(PREFETCH_SETTINS))
 850                 REG_GET_2(PREFETCH_SETTINS,
 851                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
 852                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
 853         else
 854                 REG_GET_2(PREFETCH_SETTINGS,
 855                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
 856                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
 857
 858         REG_GET_2(VBLANK_PARAMETERS_0,
 859                 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
 860                 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
 861
 862         REG_GET(REF_FREQ_TO_PIX_FREQ,
 863                 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
 864
 865         /* DLG - Per luma/chroma */
 866         REG_GET(VBLANK_PARAMETERS_1,
 867                 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
 868
 869         REG_GET(VBLANK_PARAMETERS_3,
 870                 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
 871
 872         if (REG(NOM_PARAMETERS_0))
 873                 REG_GET(NOM_PARAMETERS_0,
 874                         DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
 875
 876         if (REG(NOM_PARAMETERS_1))
 877                 REG_GET(NOM_PARAMETERS_1,
 878                         REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
 879
 880         REG_GET(NOM_PARAMETERS_4,
 881                 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
 882
 883         REG_GET(NOM_PARAMETERS_5,
 884                 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
 885
 886         REG_GET_2(PER_LINE_DELIVERY_PRE,
 887                 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
 888                 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
 889
 890         REG_GET_2(PER_LINE_DELIVERY,
 891                 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
 892                 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
 893
 894         if (REG(PREFETCH_SETTINS_C))
 895                 REG_GET(PREFETCH_SETTINS_C,
 896                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
 897         else
 898                 REG_GET(PREFETCH_SETTINGS_C,
 899                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
 900
 901         REG_GET(VBLANK_PARAMETERS_2,
 902                 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
 903
 904         REG_GET(VBLANK_PARAMETERS_4,
 905                 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
 906
 907         if (REG(NOM_PARAMETERS_2))
 908                 REG_GET(NOM_PARAMETERS_2,
 909                         DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
 910
 911         if (REG(NOM_PARAMETERS_3))
 912                 REG_GET(NOM_PARAMETERS_3,
 913                         REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
 914
 915         REG_GET(NOM_PARAMETERS_6,
 916                 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
 917
 918         REG_GET(NOM_PARAMETERS_7,
 919                 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
 920
 921         /* TTU - per hubp */
 922         REG_GET_2(DCN_TTU_QOS_WM,
 923                 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
 924                 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
 925
 926         REG_GET_2(DCN_GLOBAL_TTU_CNTL,
 927                 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
 928                 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
 929
 930         /* TTU - per luma/chroma */
 931         /* Assumed surf0 is luma and 1 is chroma */
 932
 933         REG_GET_3(DCN_SURF0_TTU_CNTL0,
 934                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
 935                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
 936                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
 937
 938         REG_GET(DCN_SURF0_TTU_CNTL1,
 939                 REFCYC_PER_REQ_DELIVERY_PRE,
 940                 &ttu_attr->refcyc_per_req_delivery_pre_l);
 941
 942         REG_GET_3(DCN_SURF1_TTU_CNTL0,
 943                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
 944                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
 945                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
 946
 947         REG_GET(DCN_SURF1_TTU_CNTL1,
 948                 REFCYC_PER_REQ_DELIVERY_PRE,
 949                 &ttu_attr->refcyc_per_req_delivery_pre_c);
 950
 951         /* Rest of hubp */
 952         REG_GET(DCSURF_SURFACE_CONFIG,
 953                         SURFACE_PIXEL_FORMAT, &s->pixel_format);
 954
 955         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 956                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
 957
 958         REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
 959                         PRI_VIEWPORT_WIDTH, &s->viewport_width,
 960                         PRI_VIEWPORT_HEIGHT, &s->viewport_height);
 961
 962         REG_GET_2(DCSURF_SURFACE_CONFIG,
 963                         ROTATION_ANGLE, &s->rotation_angle,
 964                         H_MIRROR_EN, &s->h_mirror_en);
 965
 966         REG_GET(DCSURF_TILING_CONFIG,
 967                         SW_MODE, &s->sw_mode);
 968
 969         REG_GET(DCSURF_SURFACE_CONTROL,
 970                         PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
 971
 972         REG_GET_3(DCHUBP_CNTL,
 973                         HUBP_BLANK_EN, &s->blank_en,
 974                         HUBP_TTU_DISABLE, &s->ttu_disable,
 975                         HUBP_UNDERFLOW_STATUS, &s->underflow_status);
 976
 977         REG_GET(DCN_GLOBAL_TTU_CNTL,
 978                         MIN_TTU_VBLANK, &s->min_ttu_vblank);
 979
 980         REG_GET_2(DCN_TTU_QOS_WM,
 981                         QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
 982                         QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
 983 }
 984
 985 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
 986 {
 987         enum cursor_pitch hw_pitch;
 988
 989         switch (pitch) {
 990         case 64:
 991                 hw_pitch = CURSOR_PITCH_64_PIXELS;
 992                 break;
 993         case 128:
 994                 hw_pitch = CURSOR_PITCH_128_PIXELS;
 995                 break;
 996         case 256:
 997                 hw_pitch = CURSOR_PITCH_256_PIXELS;
 998                 break;
 999         default:
1000                 DC_ERR("Invalid cursor pitch of %d. "
1001                                 "Only 64/128/256 is supported on DCN.\n", pitch);
1002                 hw_pitch = CURSOR_PITCH_64_PIXELS;
1003                 break;
1004         }
1005         return hw_pitch;
1006 }
1007
1008 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
1009                 unsigned int cur_width,
1010                 enum dc_cursor_color_format format)
1011 {
1012         enum cursor_lines_per_chunk line_per_chunk;
1013
1014         if (format == CURSOR_MODE_MONO)
1015                 /* impl B. expansion in CUR Buffer reader */
1016                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1017         else if (cur_width <= 32)
1018                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1019         else if (cur_width <= 64)
1020                 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
1021         else if (cur_width <= 128)
1022                 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
1023         else
1024                 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
1025
1026         return line_per_chunk;
1027 }
1028
1029 void hubp1_cursor_set_attributes(
1030                 struct hubp *hubp,
1031                 const struct dc_cursor_attributes *attr)
1032 {
1033         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1034         enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
1035         enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
1036                         attr->width, attr->color_format);
1037
1038         hubp->curs_attr = *attr;
1039
1040         REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
1041                         CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
1042         REG_UPDATE(CURSOR_SURFACE_ADDRESS,
1043                         CURSOR_SURFACE_ADDRESS, attr->address.low_part);
1044
1045         REG_UPDATE_2(CURSOR_SIZE,
1046                         CURSOR_WIDTH, attr->width,
1047                         CURSOR_HEIGHT, attr->height);
1048
1049         REG_UPDATE_3(CURSOR_CONTROL,
1050                         CURSOR_MODE, attr->color_format,
1051                         CURSOR_PITCH, hw_pitch,
1052                         CURSOR_LINES_PER_CHUNK, lpc);
1053
1054         REG_SET_2(CURSOR_SETTINS, 0,
1055                         /* no shift of the cursor HDL schedule */
1056                         CURSOR0_DST_Y_OFFSET, 0,
1057                          /* used to shift the cursor chunk request deadline */
1058                         CURSOR0_CHUNK_HDL_ADJUST, 3);
1059 }
1060
1061 void hubp1_cursor_set_position(
1062                 struct hubp *hubp,
1063                 const struct dc_cursor_position *pos,
1064                 const struct dc_cursor_mi_param *param)
1065 {
1066         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1067         int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
1068         int x_hotspot = pos->x_hotspot;
1069         int y_hotspot = pos->y_hotspot;
1070         uint32_t dst_x_offset;
1071         uint32_t cur_en = pos->enable ? 1 : 0;
1072
1073         /*
1074          * Guard aganst cursor_set_position() from being called with invalid
1075          * attributes
1076          *
1077          * TODO: Look at combining cursor_set_position() and
1078          * cursor_set_attributes() into cursor_update()
1079          */
1080         if (hubp->curs_attr.address.quad_part == 0)
1081                 return;
1082
1083         if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1084                 src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
1085                 y_hotspot = pos->x_hotspot;
1086                 x_hotspot = pos->y_hotspot;
1087         }
1088
1089         if (param->mirror) {
1090                 x_hotspot = param->viewport.width - x_hotspot;
1091                 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
1092         }
1093
1094         dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1095         dst_x_offset *= param->ref_clk_khz;
1096         dst_x_offset /= param->pixel_clk_khz;
1097
1098         ASSERT(param->h_scale_ratio.value);
1099
1100         if (param->h_scale_ratio.value)
1101                 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1102                                 dc_fixpt_from_int(dst_x_offset),
1103                                 param->h_scale_ratio));
1104
1105         if (src_x_offset >= (int)param->viewport.width)
1106                 cur_en = 0;  /* not visible beyond right edge*/
1107
1108         if (src_x_offset + (int)hubp->curs_attr.width <= 0)
1109                 cur_en = 0;  /* not visible beyond left edge*/
1110
1111         if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1112                 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1113
1114         REG_UPDATE(CURSOR_CONTROL,
1115                         CURSOR_ENABLE, cur_en);
1116
1117         REG_SET_2(CURSOR_POSITION, 0,
1118                         CURSOR_X_POSITION, pos->x,
1119                         CURSOR_Y_POSITION, pos->y);
1120
1121         REG_SET_2(CURSOR_HOT_SPOT, 0,
1122                         CURSOR_HOT_SPOT_X, x_hotspot,
1123                         CURSOR_HOT_SPOT_Y, y_hotspot);
1124
1125         REG_SET(CURSOR_DST_OFFSET, 0,
1126                         CURSOR_DST_X_OFFSET, dst_x_offset);
1127         /* TODO Handle surface pixel formats other than 4:4:4 */
1128 }
1129
1130 void hubp1_clk_cntl(struct hubp *hubp, bool enable)
1131 {
1132         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1133         uint32_t clk_enable = enable ? 1 : 0;
1134
1135         REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1136 }
1137
1138 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1139 {
1140         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1141
1142         REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1143 }
1144
1145 static const struct hubp_funcs dcn10_hubp_funcs = {
1146         .hubp_program_surface_flip_and_addr =
1147                         hubp1_program_surface_flip_and_addr,
1148         .hubp_program_surface_config =
1149                         hubp1_program_surface_config,
1150         .hubp_is_flip_pending = hubp1_is_flip_pending,
1151         .hubp_setup = hubp1_setup,
1152         .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
1153         .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
1154         .set_blank = hubp1_set_blank,
1155         .dcc_control = hubp1_dcc_control,
1156         .mem_program_viewport = min_set_viewport,
1157         .set_hubp_blank_en = hubp1_set_hubp_blank_en,
1158         .set_cursor_attributes  = hubp1_cursor_set_attributes,
1159         .set_cursor_position    = hubp1_cursor_set_position,
1160         .hubp_disconnect = hubp1_disconnect,
1161         .hubp_clk_cntl = hubp1_clk_cntl,
1162         .hubp_vtg_sel = hubp1_vtg_sel,
1163         .hubp_read_state = hubp1_read_state,
1164         .hubp_disable_control =  hubp1_disable_control,
1165         .hubp_get_underflow_status = hubp1_get_underflow_status,
1166
1167 };
1168
1169 /*****************************************/
1170 /* Constructor, Destructor               */
1171 /*****************************************/
1172
1173 void dcn10_hubp_construct(
1174         struct dcn10_hubp *hubp1,
1175         struct dc_context *ctx,
1176         uint32_t inst,
1177         const struct dcn_mi_registers *hubp_regs,
1178         const struct dcn_mi_shift *hubp_shift,
1179         const struct dcn_mi_mask *hubp_mask)
1180 {
1181         hubp1->base.funcs = &dcn10_hubp_funcs;
1182         hubp1->base.ctx = ctx;
1183         hubp1->hubp_regs = hubp_regs;
1184         hubp1->hubp_shift = hubp_shift;
1185         hubp1->hubp_mask = hubp_mask;
1186         hubp1->base.inst = inst;
1187         hubp1->base.opp_id = 0xf;
1188         hubp1->base.mpcc_id = 0xf;
1189 }
1190
1191