drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "core_types.h"
  29
  30 #include "reg_helper.h"
  31 #include "dcn10_dpp.h"
  32 #include "basics/conversion.h"
  33
  34
  35 #define NUM_PHASES    64
  36 #define HORZ_MAX_TAPS 8
  37 #define VERT_MAX_TAPS 8
  38
  39 #define BLACK_OFFSET_RGB_Y 0x0
  40 #define BLACK_OFFSET_CBCR  0x8000
  41
  42 #define REG(reg)\
  43         dpp->tf_regs->reg
  44
  45 #define CTX \
  46         dpp->base.ctx
  47
  48 #undef FN
  49 #define FN(reg_name, field_name) \
  50         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  51
  52 enum dcn10_coef_filter_type_sel {
  53         SCL_COEF_LUMA_VERT_FILTER = 0,
  54         SCL_COEF_LUMA_HORZ_FILTER = 1,
  55         SCL_COEF_CHROMA_VERT_FILTER = 2,
  56         SCL_COEF_CHROMA_HORZ_FILTER = 3,
  57         SCL_COEF_ALPHA_VERT_FILTER = 4,
  58         SCL_COEF_ALPHA_HORZ_FILTER = 5
  59 };
  60
  61 enum dscl_autocal_mode {
  62         AUTOCAL_MODE_OFF = 0,
  63
  64         /* Autocal calculate the scaling ratio and initial phase and the
  65          * DSCL_MODE_SEL must be set to 1
  66          */
  67         AUTOCAL_MODE_AUTOSCALE = 1,
  68         /* Autocal perform auto centering without replication and the
  69          * DSCL_MODE_SEL must be set to 0
  70          */
  71         AUTOCAL_MODE_AUTOCENTER = 2,
  72         /* Autocal perform auto centering and auto replication and the
  73          * DSCL_MODE_SEL must be set to 0
  74          */
  75         AUTOCAL_MODE_AUTOREPLICATE = 3
  76 };
  77
  78 enum dscl_mode_sel {
  79         DSCL_MODE_SCALING_444_BYPASS = 0,
  80         DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
  81         DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
  82         DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
  83         DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
  84         DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
  85         DSCL_MODE_DSCL_BYPASS = 6
  86 };
  87
  88 static void dpp1_dscl_set_overscan(
  89         struct dcn10_dpp *dpp,
  90         const struct scaler_data *data)
  91 {
  92         uint32_t left = data->recout.x;
  93         uint32_t top = data->recout.y;
  94
  95         int right = data->h_active - data->recout.x - data->recout.width;
  96         int bottom = data->v_active - data->recout.y - data->recout.height;
  97
  98         if (right < 0) {
  99                 BREAK_TO_DEBUGGER();
 100                 right = 0;
 101         }
 102         if (bottom < 0) {
 103                 BREAK_TO_DEBUGGER();
 104                 bottom = 0;
 105         }
 106
 107         REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
 108                 EXT_OVERSCAN_LEFT, left,
 109                 EXT_OVERSCAN_RIGHT, right);
 110
 111         REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
 112                 EXT_OVERSCAN_BOTTOM, bottom,
 113                 EXT_OVERSCAN_TOP, top);
 114 }
 115
 116 static void dpp1_dscl_set_otg_blank(
 117                 struct dcn10_dpp *dpp, const struct scaler_data *data)
 118 {
 119         uint32_t h_blank_start = data->h_active;
 120         uint32_t h_blank_end = 0;
 121         uint32_t v_blank_start = data->v_active;
 122         uint32_t v_blank_end = 0;
 123
 124         REG_SET_2(OTG_H_BLANK, 0,
 125                         OTG_H_BLANK_START, h_blank_start,
 126                         OTG_H_BLANK_END, h_blank_end);
 127
 128         REG_SET_2(OTG_V_BLANK, 0,
 129                         OTG_V_BLANK_START, v_blank_start,
 130                         OTG_V_BLANK_END, v_blank_end);
 131 }
 132
 133 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
 134 {
 135         if (depth == LB_PIXEL_DEPTH_30BPP)
 136                 return 0; /* 10 bpc */
 137         else if (depth == LB_PIXEL_DEPTH_24BPP)
 138                 return 1; /* 8 bpc */
 139         else if (depth == LB_PIXEL_DEPTH_18BPP)
 140                 return 2; /* 6 bpc */
 141         else if (depth == LB_PIXEL_DEPTH_36BPP)
 142                 return 3; /* 12 bpc */
 143         else {
 144                 ASSERT(0);
 145                 return -1; /* Unsupported */
 146         }
 147 }
 148
 149 static bool dpp1_dscl_is_video_format(enum pixel_format format)
 150 {
 151         if (format >= PIXEL_FORMAT_VIDEO_BEGIN
 152                         && format <= PIXEL_FORMAT_VIDEO_END)
 153                 return true;
 154         else
 155                 return false;
 156 }
 157
 158 static bool dpp1_dscl_is_420_format(enum pixel_format format)
 159 {
 160         if (format == PIXEL_FORMAT_420BPP8 ||
 161                         format == PIXEL_FORMAT_420BPP10)
 162                 return true;
 163         else
 164                 return false;
 165 }
 166
 167 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
 168                 struct dpp *dpp_base,
 169                 const struct scaler_data *data,
 170                 bool dbg_always_scale)
 171 {
 172         const long long one = dc_fixpt_one.value;
 173
 174         if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
 175                 /* DSCL is processing data in fixed format */
 176                 if (data->format == PIXEL_FORMAT_FP16)
 177                         return DSCL_MODE_DSCL_BYPASS;
 178         }
 179
 180         if (data->ratios.horz.value == one
 181                         && data->ratios.vert.value == one
 182                         && data->ratios.horz_c.value == one
 183                         && data->ratios.vert_c.value == one
 184                         && !dbg_always_scale)
 185                 return DSCL_MODE_SCALING_444_BYPASS;
 186
 187         if (!dpp1_dscl_is_420_format(data->format)) {
 188                 if (dpp1_dscl_is_video_format(data->format))
 189                         return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
 190                 else
 191                         return DSCL_MODE_SCALING_444_RGB_ENABLE;
 192         }
 193         if (data->ratios.horz.value == one && data->ratios.vert.value == one)
 194                 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
 195         if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
 196                 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
 197
 198         return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
 199 }
 200
 201 static void dpp1_dscl_set_lb(
 202         struct dcn10_dpp *dpp,
 203         const struct line_buffer_params *lb_params,
 204         enum lb_memory_config mem_size_config)
 205 {
 206         /* LB */
 207         if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
 208                 /* DSCL caps: pixel data processed in fixed format */
 209                 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
 210                 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
 211
 212                 REG_SET_7(LB_DATA_FORMAT, 0,
 213                         PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
 214                         PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
 215                         PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
 216                         DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
 217                         DITHER_EN, 0, /* Dithering enable: Disabled */
 218                         INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
 219                         LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
 220         }
 221
 222         REG_SET_2(LB_MEMORY_CTRL, 0,
 223                 MEMORY_CONFIG, mem_size_config,
 224                 LB_MAX_PARTITIONS, 63);
 225 }
 226
 227 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
 228 {
 229         if (taps == 8)
 230                 return get_filter_8tap_64p(ratio);
 231         else if (taps == 7)
 232                 return get_filter_7tap_64p(ratio);
 233         else if (taps == 6)
 234                 return get_filter_6tap_64p(ratio);
 235         else if (taps == 5)
 236                 return get_filter_5tap_64p(ratio);
 237         else if (taps == 4)
 238                 return get_filter_4tap_64p(ratio);
 239         else if (taps == 3)
 240                 return get_filter_3tap_64p(ratio);
 241         else if (taps == 2)
 242                 return get_filter_2tap_64p();
 243         else if (taps == 1)
 244                 return NULL;
 245         else {
 246                 /* should never happen, bug */
 247                 BREAK_TO_DEBUGGER();
 248                 return NULL;
 249         }
 250 }
 251
 252 static void dpp1_dscl_set_scaler_filter(
 253                 struct dcn10_dpp *dpp,
 254                 uint32_t taps,
 255                 enum dcn10_coef_filter_type_sel filter_type,
 256                 const uint16_t *filter)
 257 {
 258         const int tap_pairs = (taps + 1) / 2;
 259         int phase;
 260         int pair;
 261         uint16_t odd_coef, even_coef;
 262
 263         REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
 264                 SCL_COEF_RAM_TAP_PAIR_IDX, 0,
 265                 SCL_COEF_RAM_PHASE, 0,
 266                 SCL_COEF_RAM_FILTER_TYPE, filter_type);
 267
 268         for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
 269                 for (pair = 0; pair < tap_pairs; pair++) {
 270                         even_coef = filter[phase * taps + 2 * pair];
 271                         if ((pair * 2 + 1) < taps)
 272                                 odd_coef = filter[phase * taps + 2 * pair + 1];
 273                         else
 274                                 odd_coef = 0;
 275
 276                         REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
 277                                 /* Even tap coefficient (bits 1:0 fixed to 0) */
 278                                 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
 279                                 /* Write/read control for even coefficient */
 280                                 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
 281                                 /* Odd tap coefficient (bits 1:0 fixed to 0) */
 282                                 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
 283                                 /* Write/read control for odd coefficient */
 284                                 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
 285                 }
 286         }
 287
 288 }
 289
 290 static void dpp1_dscl_set_scl_filter(
 291                 struct dcn10_dpp *dpp,
 292                 const struct scaler_data *scl_data,
 293                 bool chroma_coef_mode)
 294 {
 295         bool h_2tap_hardcode_coef_en = false;
 296         bool v_2tap_hardcode_coef_en = false;
 297         bool h_2tap_sharp_en = false;
 298         bool v_2tap_sharp_en = false;
 299         uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
 300         uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
 301         bool coef_ram_current;
 302         const uint16_t *filter_h = NULL;
 303         const uint16_t *filter_v = NULL;
 304         const uint16_t *filter_h_c = NULL;
 305         const uint16_t *filter_v_c = NULL;
 306
 307         h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
 308                                         && scl_data->taps.h_taps_c < 3
 309                 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
 310         v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
 311                                         && scl_data->taps.v_taps_c < 3
 312                 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
 313
 314         h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
 315         v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
 316
 317         REG_UPDATE_6(DSCL_2TAP_CONTROL,
 318                 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
 319                 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
 320                 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
 321                 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
 322                 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
 323                 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
 324
 325         if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
 326                 bool filter_updated = false;
 327
 328                 filter_h = dpp1_dscl_get_filter_coeffs_64p(
 329                                 scl_data->taps.h_taps, scl_data->ratios.horz);
 330                 filter_v = dpp1_dscl_get_filter_coeffs_64p(
 331                                 scl_data->taps.v_taps, scl_data->ratios.vert);
 332
 333                 filter_updated = (filter_h && (filter_h != dpp->filter_h))
 334                                 || (filter_v && (filter_v != dpp->filter_v));
 335
 336                 if (chroma_coef_mode) {
 337                         filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
 338                                         scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
 339                         filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
 340                                         scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
 341                         filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
 342                                                         || (filter_v_c && (filter_v_c != dpp->filter_v_c));
 343                 }
 344
 345                 if (filter_updated) {
 346                         uint32_t scl_mode = REG_READ(SCL_MODE);
 347
 348                         if (!h_2tap_hardcode_coef_en && filter_h) {
 349                                 dpp1_dscl_set_scaler_filter(
 350                                         dpp, scl_data->taps.h_taps,
 351                                         SCL_COEF_LUMA_HORZ_FILTER, filter_h);
 352                         }
 353                         dpp->filter_h = filter_h;
 354                         if (!v_2tap_hardcode_coef_en && filter_v) {
 355                                 dpp1_dscl_set_scaler_filter(
 356                                         dpp, scl_data->taps.v_taps,
 357                                         SCL_COEF_LUMA_VERT_FILTER, filter_v);
 358                         }
 359                         dpp->filter_v = filter_v;
 360                         if (chroma_coef_mode) {
 361                                 if (!h_2tap_hardcode_coef_en && filter_h_c) {
 362                                         dpp1_dscl_set_scaler_filter(
 363                                                 dpp, scl_data->taps.h_taps_c,
 364                                                 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
 365                                 }
 366                                 if (!v_2tap_hardcode_coef_en && filter_v_c) {
 367                                         dpp1_dscl_set_scaler_filter(
 368                                                 dpp, scl_data->taps.v_taps_c,
 369                                                 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
 370                                 }
 371                         }
 372                         dpp->filter_h_c = filter_h_c;
 373                         dpp->filter_v_c = filter_v_c;
 374
 375                         coef_ram_current = get_reg_field_value_ex(
 376                                 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
 377                                 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
 378
 379                         /* Swap coefficient RAM and set chroma coefficient mode */
 380                         REG_SET_2(SCL_MODE, scl_mode,
 381                                         SCL_COEF_RAM_SELECT, !coef_ram_current,
 382                                         SCL_CHROMA_COEF_MODE, chroma_coef_mode);
 383                 }
 384         }
 385 }
 386
 387 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
 388 {
 389         if (depth == LB_PIXEL_DEPTH_30BPP)
 390                 return 10;
 391         else if (depth == LB_PIXEL_DEPTH_24BPP)
 392                 return 8;
 393         else if (depth == LB_PIXEL_DEPTH_18BPP)
 394                 return 6;
 395         else if (depth == LB_PIXEL_DEPTH_36BPP)
 396                 return 12;
 397         else {
 398                 BREAK_TO_DEBUGGER();
 399                 return -1; /* Unsupported */
 400         }
 401 }
 402
 403 void dpp1_dscl_calc_lb_num_partitions(
 404                 const struct scaler_data *scl_data,
 405                 enum lb_memory_config lb_config,
 406                 int *num_part_y,
 407                 int *num_part_c)
 408 {
 409         int line_size = scl_data->viewport.width < scl_data->recout.width ?
 410                         scl_data->viewport.width : scl_data->recout.width;
 411         int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
 412                         scl_data->viewport_c.width : scl_data->recout.width;
 413         int lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
 414         int memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
 415         int memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
 416         int memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
 417         int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
 418
 419         if (lb_config == LB_MEMORY_CONFIG_1) {
 420                 lb_memory_size = 816;
 421                 lb_memory_size_c = 816;
 422                 lb_memory_size_a = 984;
 423         } else if (lb_config == LB_MEMORY_CONFIG_2) {
 424                 lb_memory_size = 1088;
 425                 lb_memory_size_c = 1088;
 426                 lb_memory_size_a = 1312;
 427         } else if (lb_config == LB_MEMORY_CONFIG_3) {
 428                 /* 420 mode: using 3rd mem from Y, Cr and Cb */
 429                 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
 430                 lb_memory_size_c = 816 + 1088;
 431                 lb_memory_size_a = 984 + 1312 + 456;
 432         } else {
 433                 lb_memory_size = 816 + 1088 + 848;
 434                 lb_memory_size_c = 816 + 1088 + 848;
 435                 lb_memory_size_a = 984 + 1312 + 456;
 436         }
 437         *num_part_y = lb_memory_size / memory_line_size_y;
 438         *num_part_c = lb_memory_size_c / memory_line_size_c;
 439         num_partitions_a = lb_memory_size_a / memory_line_size_a;
 440
 441         if (scl_data->lb_params.alpha_en
 442                         && (num_partitions_a < *num_part_y))
 443                 *num_part_y = num_partitions_a;
 444
 445         if (*num_part_y > 64)
 446                 *num_part_y = 64;
 447         if (*num_part_c > 64)
 448                 *num_part_c = 64;
 449
 450 }
 451
 452 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
 453 {
 454         if (ceil_vratio > 2)
 455                 return vtaps <= (num_partitions - ceil_vratio + 2);
 456         else
 457                 return vtaps <= num_partitions;
 458 }
 459
 460 /*find first match configuration which meets the min required lb size*/
 461 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
 462                 const struct scaler_data *scl_data)
 463 {
 464         int num_part_y, num_part_c;
 465         int vtaps = scl_data->taps.v_taps;
 466         int vtaps_c = scl_data->taps.v_taps_c;
 467         int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
 468         int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
 469         enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
 470
 471         if (dpp->base.ctx->dc->debug.use_max_lb)
 472                 return mem_cfg;
 473
 474         dpp->base.caps->dscl_calc_lb_num_partitions(
 475                         scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
 476
 477         if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
 478                         && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
 479                 return LB_MEMORY_CONFIG_1;
 480
 481         dpp->base.caps->dscl_calc_lb_num_partitions(
 482                         scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
 483
 484         if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
 485                         && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
 486                 return LB_MEMORY_CONFIG_2;
 487
 488         if (scl_data->format == PIXEL_FORMAT_420BPP8
 489                         || scl_data->format == PIXEL_FORMAT_420BPP10) {
 490                 dpp->base.caps->dscl_calc_lb_num_partitions(
 491                                 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
 492
 493                 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
 494                                 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
 495                         return LB_MEMORY_CONFIG_3;
 496         }
 497
 498         dpp->base.caps->dscl_calc_lb_num_partitions(
 499                         scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
 500
 501         /*Ensure we can support the requested number of vtaps*/
 502         ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
 503                         && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
 504
 505         return LB_MEMORY_CONFIG_0;
 506 }
 507
 508 void dpp1_dscl_set_scaler_auto_scale(
 509         struct dpp *dpp_base,
 510         const struct scaler_data *scl_data)
 511 {
 512         enum lb_memory_config lb_config;
 513         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 514         enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
 515                         dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
 516         bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
 517                                 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
 518
 519         dpp1_dscl_set_overscan(dpp, scl_data);
 520
 521         dpp1_dscl_set_otg_blank(dpp, scl_data);
 522
 523         REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 524
 525         if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
 526                 return;
 527
 528         lb_config =  dpp1_dscl_find_lb_memory_config(dpp, scl_data);
 529         dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
 530
 531         if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
 532                 return;
 533
 534         /* TODO: v_min */
 535         REG_SET_3(DSCL_AUTOCAL, 0,
 536                 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
 537                 AUTOCAL_NUM_PIPE, 0,
 538                 AUTOCAL_PIPE_ID, 0);
 539
 540         /* Black offsets */
 541         if (ycbcr)
 542                 REG_SET_2(SCL_BLACK_OFFSET, 0,
 543                                 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
 544                                 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
 545         else
 546
 547                 REG_SET_2(SCL_BLACK_OFFSET, 0,
 548                                 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
 549                                 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
 550
 551         REG_SET_4(SCL_TAP_CONTROL, 0,
 552                 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
 553                 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
 554                 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
 555                 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
 556
 557         dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
 558 }
 559
 560
 561 static void dpp1_dscl_set_manual_ratio_init(
 562                 struct dcn10_dpp *dpp, const struct scaler_data *data)
 563 {
 564         uint32_t init_frac = 0;
 565         uint32_t init_int = 0;
 566
 567         REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
 568                         SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5);
 569
 570         REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
 571                         SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5);
 572
 573         REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
 574                         SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5);
 575
 576         REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
 577                         SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5);
 578
 579         /*
 580          * 0.24 format for fraction, first five bits zeroed
 581          */
 582         init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
 583         init_int = dc_fixpt_floor(data->inits.h);
 584         REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
 585                 SCL_H_INIT_FRAC, init_frac,
 586                 SCL_H_INIT_INT, init_int);
 587
 588         init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
 589         init_int = dc_fixpt_floor(data->inits.h_c);
 590         REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
 591                 SCL_H_INIT_FRAC_C, init_frac,
 592                 SCL_H_INIT_INT_C, init_int);
 593
 594         init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
 595         init_int = dc_fixpt_floor(data->inits.v);
 596         REG_SET_2(SCL_VERT_FILTER_INIT, 0,
 597                 SCL_V_INIT_FRAC, init_frac,
 598                 SCL_V_INIT_INT, init_int);
 599
 600         init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
 601         init_int = dc_fixpt_floor(data->inits.v_bot);
 602         REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
 603                 SCL_V_INIT_FRAC_BOT, init_frac,
 604                 SCL_V_INIT_INT_BOT, init_int);
 605
 606         init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
 607         init_int = dc_fixpt_floor(data->inits.v_c);
 608         REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
 609                 SCL_V_INIT_FRAC_C, init_frac,
 610                 SCL_V_INIT_INT_C, init_int);
 611
 612         init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
 613         init_int = dc_fixpt_floor(data->inits.v_c_bot);
 614         REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
 615                 SCL_V_INIT_FRAC_BOT_C, init_frac,
 616                 SCL_V_INIT_INT_BOT_C, init_int);
 617 }
 618
 619
 620
 621 static void dpp1_dscl_set_recout(
 622                         struct dcn10_dpp *dpp, const struct rect *recout)
 623 {
 624         int visual_confirm_on = 0;
 625         if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
 626                 visual_confirm_on = 1;
 627
 628         REG_SET_2(RECOUT_START, 0,
 629                 /* First pixel of RECOUT */
 630                          RECOUT_START_X, recout->x,
 631                 /* First line of RECOUT */
 632                          RECOUT_START_Y, recout->y);
 633
 634         REG_SET_2(RECOUT_SIZE, 0,
 635                 /* Number of RECOUT horizontal pixels */
 636                          RECOUT_WIDTH, recout->width,
 637                 /* Number of RECOUT vertical lines */
 638                          RECOUT_HEIGHT, recout->height
 639                          - visual_confirm_on * 4 * (dpp->base.inst + 1));
 640 }
 641
 642 /* Main function to program scaler and line buffer in manual scaling mode */
 643 void dpp1_dscl_set_scaler_manual_scale(
 644         struct dpp *dpp_base,
 645         const struct scaler_data *scl_data)
 646 {
 647         enum lb_memory_config lb_config;
 648         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 649         enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
 650                         dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
 651         bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
 652                                 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
 653
 654         if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
 655                 return;
 656
 657         PERF_TRACE();
 658
 659         dpp->scl_data = *scl_data;
 660
 661         /* Autocal off */
 662         REG_SET_3(DSCL_AUTOCAL, 0,
 663                 AUTOCAL_MODE, AUTOCAL_MODE_OFF,
 664                 AUTOCAL_NUM_PIPE, 0,
 665                 AUTOCAL_PIPE_ID, 0);
 666
 667         /* Recout */
 668         dpp1_dscl_set_recout(dpp, &scl_data->recout);
 669
 670         /* MPC Size */
 671         REG_SET_2(MPC_SIZE, 0,
 672                 /* Number of horizontal pixels of MPC */
 673                          MPC_WIDTH, scl_data->h_active,
 674                 /* Number of vertical lines of MPC */
 675                          MPC_HEIGHT, scl_data->v_active);
 676
 677         /* SCL mode */
 678         REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 679
 680         if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
 681                 return;
 682
 683         /* LB */
 684         lb_config =  dpp1_dscl_find_lb_memory_config(dpp, scl_data);
 685         dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
 686
 687         if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
 688                 return;
 689
 690         /* Black offsets */
 691         if (ycbcr)
 692                 REG_SET_2(SCL_BLACK_OFFSET, 0,
 693                                 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
 694                                 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
 695         else
 696
 697                 REG_SET_2(SCL_BLACK_OFFSET, 0,
 698                                 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
 699                                 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
 700
 701         /* Manually calculate scale ratio and init values */
 702         dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
 703
 704         /* HTaps/VTaps */
 705         REG_SET_4(SCL_TAP_CONTROL, 0,
 706                 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
 707                 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
 708                 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
 709                 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
 710
 711         dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
 712         PERF_TRACE();
 713 }