drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "core_types.h"
  29
  30 #include "reg_helper.h"
  31 #include "dcn10_dpp.h"
  32 #include "basics/conversion.h"
  33
  34 #define NUM_PHASES    64
  35 #define HORZ_MAX_TAPS 8
  36 #define VERT_MAX_TAPS 8
  37
  38 #define BLACK_OFFSET_RGB_Y 0x0
  39 #define BLACK_OFFSET_CBCR  0x8000
  40
  41 #define REG(reg)\
  42         dpp->tf_regs->reg
  43
  44 #define CTX \
  45         dpp->base.ctx
  46
  47 #undef FN
  48 #define FN(reg_name, field_name) \
  49         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  50
  51 enum pixel_format_description {
  52         PIXEL_FORMAT_FIXED = 0,
  53         PIXEL_FORMAT_FIXED16,
  54         PIXEL_FORMAT_FLOAT
  55
  56 };
  57
  58 enum dcn10_coef_filter_type_sel {
  59         SCL_COEF_LUMA_VERT_FILTER = 0,
  60         SCL_COEF_LUMA_HORZ_FILTER = 1,
  61         SCL_COEF_CHROMA_VERT_FILTER = 2,
  62         SCL_COEF_CHROMA_HORZ_FILTER = 3,
  63         SCL_COEF_ALPHA_VERT_FILTER = 4,
  64         SCL_COEF_ALPHA_HORZ_FILTER = 5
  65 };
  66
  67 enum dscl_autocal_mode {
  68         AUTOCAL_MODE_OFF = 0,
  69
  70         /* Autocal calculate the scaling ratio and initial phase and the
  71          * DSCL_MODE_SEL must be set to 1
  72          */
  73         AUTOCAL_MODE_AUTOSCALE = 1,
  74         /* Autocal perform auto centering without replication and the
  75          * DSCL_MODE_SEL must be set to 0
  76          */
  77         AUTOCAL_MODE_AUTOCENTER = 2,
  78         /* Autocal perform auto centering and auto replication and the
  79          * DSCL_MODE_SEL must be set to 0
  80          */
  81         AUTOCAL_MODE_AUTOREPLICATE = 3
  82 };
  83
  84 enum dscl_mode_sel {
  85         DSCL_MODE_SCALING_444_BYPASS = 0,
  86         DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
  87         DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
  88         DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
  89         DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
  90         DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
  91         DSCL_MODE_DSCL_BYPASS = 6
  92 };
  93
  94 enum gamut_remap_select {
  95         GAMUT_REMAP_BYPASS = 0,
  96         GAMUT_REMAP_COEFF,
  97         GAMUT_REMAP_COMA_COEFF,
  98         GAMUT_REMAP_COMB_COEFF
  99 };
 100
 101 /* Program gamut remap in bypass mode */
 102 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
 103 {
 104         REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
 105                         CM_GAMUT_REMAP_MODE, 0);
 106         /* Gamut remap in bypass */
 107 }
 108
 109 #define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
 110
 111
 112 bool dpp_get_optimal_number_of_taps(
 113                 struct dpp *dpp,
 114                 struct scaler_data *scl_data,
 115                 const struct scaling_taps *in_taps)
 116 {
 117         uint32_t pixel_width;
 118
 119         if (scl_data->viewport.width > scl_data->recout.width)
 120                 pixel_width = scl_data->recout.width;
 121         else
 122                 pixel_width = scl_data->viewport.width;
 123
 124         /* TODO: add lb check */
 125
 126         /* No support for programming ratio of 4, drop to 3.99999.. */
 127         if (scl_data->ratios.horz.value == (4ll << 32))
 128                 scl_data->ratios.horz.value--;
 129         if (scl_data->ratios.vert.value == (4ll << 32))
 130                 scl_data->ratios.vert.value--;
 131         if (scl_data->ratios.horz_c.value == (4ll << 32))
 132                 scl_data->ratios.horz_c.value--;
 133         if (scl_data->ratios.vert_c.value == (4ll << 32))
 134                 scl_data->ratios.vert_c.value--;
 135
 136         /* Set default taps if none are provided */
 137         if (in_taps->h_taps == 0)
 138                 scl_data->taps.h_taps = 4;
 139         else
 140                 scl_data->taps.h_taps = in_taps->h_taps;
 141         if (in_taps->v_taps == 0)
 142                 scl_data->taps.v_taps = 4;
 143         else
 144                 scl_data->taps.v_taps = in_taps->v_taps;
 145         if (in_taps->v_taps_c == 0)
 146                 scl_data->taps.v_taps_c = 2;
 147         else
 148                 scl_data->taps.v_taps_c = in_taps->v_taps_c;
 149         if (in_taps->h_taps_c == 0)
 150                 scl_data->taps.h_taps_c = 2;
 151         /* Only 1 and even h_taps_c are supported by hw */
 152         else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
 153                 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
 154         else
 155                 scl_data->taps.h_taps_c = in_taps->h_taps_c;
 156
 157         if (!dpp->ctx->dc->debug.always_scale) {
 158                 if (IDENTITY_RATIO(scl_data->ratios.horz))
 159                         scl_data->taps.h_taps = 1;
 160                 if (IDENTITY_RATIO(scl_data->ratios.vert))
 161                         scl_data->taps.v_taps = 1;
 162                 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
 163                         scl_data->taps.h_taps_c = 1;
 164                 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
 165                         scl_data->taps.v_taps_c = 1;
 166         }
 167
 168         return true;
 169 }
 170
 171 void dpp_reset(struct dpp *dpp_base)
 172 {
 173         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 174
 175         dpp->filter_h_c = NULL;
 176         dpp->filter_v_c = NULL;
 177         dpp->filter_h = NULL;
 178         dpp->filter_v = NULL;
 179
 180         /* set boundary mode to 0 */
 181         REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
 182 }
 183
 184
 185
 186 static void dpp1_cm_set_regamma_pwl(
 187         struct dpp *dpp_base, const struct pwl_params *params)
 188 {
 189         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 190
 191         dpp1_cm_power_on_regamma_lut(dpp_base, true);
 192         dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
 193
 194         if (dpp->is_write_to_ram_a_safe)
 195                 dpp1_cm_program_regamma_luta_settings(dpp_base, params);
 196         else
 197                 dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
 198
 199         dpp1_cm_program_regamma_lut(
 200                         dpp_base, params->rgb_resulted, params->hw_points_num);
 201 }
 202
 203 static void dpp1_cm_set_regamma_mode(
 204         struct dpp *dpp_base,
 205         enum opp_regamma mode)
 206 {
 207         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 208         uint32_t re_mode = 0;
 209         uint32_t obuf_bypass = 0; /* need for pipe split */
 210         uint32_t obuf_hupscale = 0;
 211
 212         switch (mode) {
 213         case OPP_REGAMMA_BYPASS:
 214                 re_mode = 0;
 215                 break;
 216         case OPP_REGAMMA_SRGB:
 217                 re_mode = 1;
 218                 break;
 219         case OPP_REGAMMA_3_6:
 220                 re_mode = 2;
 221                 break;
 222         case OPP_REGAMMA_USER:
 223                 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
 224                 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
 225                 break;
 226         default:
 227                 break;
 228         }
 229
 230         REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
 231         REG_UPDATE_2(OBUF_CONTROL,
 232                         OBUF_BYPASS, obuf_bypass,
 233                         OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
 234 }
 235
 236 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
 237                                                 enum pixel_format_description *fmt)
 238 {
 239
 240         if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
 241                 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
 242                 *fmt = PIXEL_FORMAT_FLOAT;
 243         else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
 244                 *fmt = PIXEL_FORMAT_FIXED16;
 245         else
 246                 *fmt = PIXEL_FORMAT_FIXED;
 247 }
 248
 249 static void dpp1_set_degamma_format_float(
 250                 struct dpp *dpp_base,
 251                 bool is_float)
 252 {
 253         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 254
 255         if (is_float) {
 256                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
 257                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
 258         } else {
 259                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
 260                 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
 261         }
 262 }
 263
 264 void dpp1_cnv_setup (
 265                 struct dpp *dpp_base,
 266                 enum surface_pixel_format input_format,
 267                 enum expansion_mode mode)
 268 {
 269         uint32_t pixel_format;
 270         uint32_t alpha_en;
 271         enum pixel_format_description fmt ;
 272         enum dc_color_space color_space;
 273         enum dcn10_input_csc_select select;
 274         bool is_float;
 275         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 276         bool force_disable_cursor = false;
 277
 278         dpp1_setup_format_flags(input_format, &fmt);
 279         alpha_en = 1;
 280         pixel_format = 0;
 281         color_space = COLOR_SPACE_SRGB;
 282         select = INPUT_CSC_SELECT_BYPASS;
 283         is_float = false;
 284
 285         switch (fmt) {
 286         case PIXEL_FORMAT_FIXED:
 287         case PIXEL_FORMAT_FIXED16:
 288         /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
 289                 REG_SET_3(FORMAT_CONTROL, 0,
 290                         CNVC_BYPASS, 0,
 291                         FORMAT_EXPANSION_MODE, mode,
 292                         OUTPUT_FP, 0);
 293                 break;
 294         case PIXEL_FORMAT_FLOAT:
 295                 REG_SET_3(FORMAT_CONTROL, 0,
 296                         CNVC_BYPASS, 0,
 297                         FORMAT_EXPANSION_MODE, mode,
 298                         OUTPUT_FP, 1);
 299                 is_float = true;
 300                 break;
 301         default:
 302
 303                 break;
 304         }
 305
 306         dpp1_set_degamma_format_float(dpp_base, is_float);
 307
 308         switch (input_format) {
 309         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 310                 pixel_format = 1;
 311                 break;
 312         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 313                 pixel_format = 3;
 314                 alpha_en = 0;
 315                 break;
 316         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 317         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 318                 pixel_format = 8;
 319                 break;
 320         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 321         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 322                 pixel_format = 10;
 323                 break;
 324         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 325                 force_disable_cursor = false;
 326                 pixel_format = 65;
 327                 color_space = COLOR_SPACE_YCBCR709;
 328                 select = INPUT_CSC_SELECT_ICSC;
 329                 break;
 330         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 331                 force_disable_cursor = true;
 332                 pixel_format = 64;
 333                 color_space = COLOR_SPACE_YCBCR709;
 334                 select = INPUT_CSC_SELECT_ICSC;
 335                 break;
 336         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 337                 force_disable_cursor = true;
 338                 pixel_format = 67;
 339                 color_space = COLOR_SPACE_YCBCR709;
 340                 select = INPUT_CSC_SELECT_ICSC;
 341                 break;
 342         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 343                 force_disable_cursor = true;
 344                 pixel_format = 66;
 345                 color_space = COLOR_SPACE_YCBCR709;
 346                 select = INPUT_CSC_SELECT_ICSC;
 347                 break;
 348         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 349                 pixel_format = 22;
 350                 break;
 351         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 352                 pixel_format = 24;
 353                 break;
 354         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 355                 pixel_format = 25;
 356                 break;
 357         default:
 358                 break;
 359         }
 360         REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
 361                         CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
 362         REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 363
 364         dpp1_program_input_csc(dpp_base, color_space, select);
 365
 366         if (force_disable_cursor) {
 367                 REG_UPDATE(CURSOR_CONTROL,
 368                                 CURSOR_ENABLE, 0);
 369                 REG_UPDATE(CURSOR0_CONTROL,
 370                                 CUR0_ENABLE, 0);
 371         }
 372 }
 373
 374 void dpp1_set_cursor_attributes(
 375                 struct dpp *dpp_base,
 376                 const struct dc_cursor_attributes *attr)
 377 {
 378         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 379         enum dc_cursor_color_format color_format = attr->color_format;
 380
 381         REG_UPDATE_2(CURSOR0_CONTROL,
 382                         CUR0_MODE, color_format,
 383                         CUR0_EXPANSION_MODE, 0);
 384
 385         if (color_format == CURSOR_MODE_MONO) {
 386                 /* todo: clarify what to program these to */
 387                 REG_UPDATE(CURSOR0_COLOR0,
 388                                 CUR0_COLOR0, 0x00000000);
 389                 REG_UPDATE(CURSOR0_COLOR1,
 390                                 CUR0_COLOR1, 0xFFFFFFFF);
 391         }
 392
 393         /* TODO: Fixed vs float */
 394
 395         REG_UPDATE_3(FORMAT_CONTROL,
 396                                 CNVC_BYPASS, 0,
 397                                 FORMAT_CONTROL__ALPHA_EN, 1,
 398                                 FORMAT_EXPANSION_MODE, 0);
 399 }
 400
 401
 402 void dpp1_set_cursor_position(
 403                 struct dpp *dpp_base,
 404                 const struct dc_cursor_position *pos,
 405                 const struct dc_cursor_mi_param *param,
 406                 uint32_t width)
 407 {
 408         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 409         int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
 410         uint32_t cur_en = pos->enable ? 1 : 0;
 411
 412         if (src_x_offset >= (int)param->viewport_width)
 413                 cur_en = 0;  /* not visible beyond right edge*/
 414
 415         if (src_x_offset + (int)width < 0)
 416                 cur_en = 0;  /* not visible beyond left edge*/
 417
 418         REG_UPDATE(CURSOR0_CONTROL,
 419                         CUR0_ENABLE, cur_en);
 420
 421 }
 422
 423 static const struct dpp_funcs dcn10_dpp_funcs = {
 424                 .dpp_reset = dpp_reset,
 425                 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
 426                 .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
 427                 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
 428                 .opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
 429                 .opp_set_csc_default = dpp1_cm_set_output_csc_default,
 430                 .opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
 431                 .opp_program_regamma_lut = dpp1_cm_program_regamma_lut,
 432                 .opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
 433                 .opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
 434                 .opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
 435                 .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
 436                 .opp_set_regamma_mode = dpp1_cm_set_regamma_mode,
 437                 .ipp_set_degamma = dpp1_set_degamma,
 438                 .ipp_program_input_lut          = dpp1_program_input_lut,
 439                 .ipp_program_degamma_pwl        = dpp1_set_degamma_pwl,
 440                 .ipp_setup                      = dpp1_cnv_setup,
 441                 .ipp_full_bypass                = dpp1_full_bypass,
 442                 .set_cursor_attributes = dpp1_set_cursor_attributes,
 443                 .set_cursor_position = dpp1_set_cursor_position,
 444 };
 445
 446 static struct dpp_caps dcn10_dpp_cap = {
 447         .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
 448         .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
 449 };
 450
 451 /*****************************************/
 452 /* Constructor, Destructor               */
 453 /*****************************************/
 454
 455 void dpp1_construct(
 456         struct dcn10_dpp *dpp,
 457         struct dc_context *ctx,
 458         uint32_t inst,
 459         const struct dcn_dpp_registers *tf_regs,
 460         const struct dcn_dpp_shift *tf_shift,
 461         const struct dcn_dpp_mask *tf_mask)
 462 {
 463         dpp->base.ctx = ctx;
 464
 465         dpp->base.inst = inst;
 466         dpp->base.funcs = &dcn10_dpp_funcs;
 467         dpp->base.caps = &dcn10_dpp_cap;
 468
 469         dpp->tf_regs = tf_regs;
 470         dpp->tf_shift = tf_shift;
 471         dpp->tf_mask = tf_mask;
 472
 473         dpp->lb_pixel_depth_supported =
 474                 LB_PIXEL_DEPTH_18BPP |
 475                 LB_PIXEL_DEPTH_24BPP |
 476                 LB_PIXEL_DEPTH_30BPP;
 477
 478         dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 479         dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
 480 }