drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26
  27 #include "link_encoder.h"
  28 #include "stream_encoder.h"
  29
  30 #include "resource.h"
  31 #include "include/irq_service_interface.h"
  32 #include "../virtual/virtual_stream_encoder.h"
  33 #include "dce110/dce110_resource.h"
  34 #include "dce110/dce110_timing_generator.h"
  35 #include "irq/dce110/irq_service_dce110.h"
  36 #include "dce/dce_link_encoder.h"
  37 #include "dce/dce_stream_encoder.h"
  38
  39 #include "dce/dce_mem_input.h"
  40 #include "dce/dce_ipp.h"
  41 #include "dce/dce_transform.h"
  42 #include "dce/dce_opp.h"
  43 #include "dce/dce_clocks.h"
  44 #include "dce/dce_clock_source.h"
  45 #include "dce/dce_audio.h"
  46 #include "dce/dce_hwseq.h"
  47 #include "dce100/dce100_hw_sequencer.h"
  48
  49 #include "reg_helper.h"
  50
  51 #include "dce/dce_10_0_d.h"
  52 #include "dce/dce_10_0_sh_mask.h"
  53
  54 #include "dce/dce_dmcu.h"
  55 #include "dce/dce_abm.h"
  56
  57 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  58 #include "gmc/gmc_8_2_d.h"
  59 #include "gmc/gmc_8_2_sh_mask.h"
  60 #endif
  61
  62 #ifndef mmDP_DPHY_INTERNAL_CTRL
  63         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  64         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  65         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  66         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  67         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  68         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  69         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  70         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  71         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  72         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  73 #endif
  74
  75 #ifndef mmBIOS_SCRATCH_2
  76         #define mmBIOS_SCRATCH_2 0x05CB
  77         #define mmBIOS_SCRATCH_6 0x05CF
  78 #endif
  79
  80 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  81         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  82         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  83         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  84         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  85         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  86         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  87         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  88         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
  89 #endif
  90
  91 #ifndef mmDP_DPHY_FAST_TRAINING
  92         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
  93         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
  94         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
  95         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
  96         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
  97         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
  98         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
  99         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 100 #endif
 101
 102 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
 103         {
 104                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 105                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 106         },
 107         {
 108                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 109                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 110         },
 111         {
 112                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 113                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 114         },
 115         {
 116                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 117                 .dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 118         },
 119         {
 120                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 121                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 122         },
 123         {
 124                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 125                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 126         }
 127 };
 128
 129 /* set register offset */
 130 #define SR(reg_name)\
 131         .reg_name = mm ## reg_name
 132
 133 /* set register offset with instance */
 134 #define SRI(reg_name, block, id)\
 135         .reg_name = mm ## block ## id ## _ ## reg_name
 136
 137
 138 static const struct dce_disp_clk_registers disp_clk_regs = {
 139                 CLK_COMMON_REG_LIST_DCE_BASE()
 140 };
 141
 142 static const struct dce_disp_clk_shift disp_clk_shift = {
 143                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 144 };
 145
 146 static const struct dce_disp_clk_mask disp_clk_mask = {
 147                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 148 };
 149
 150 #define ipp_regs(id)\
 151 [id] = {\
 152                 IPP_DCE100_REG_LIST_DCE_BASE(id)\
 153 }
 154
 155 static const struct dce_ipp_registers ipp_regs[] = {
 156                 ipp_regs(0),
 157                 ipp_regs(1),
 158                 ipp_regs(2),
 159                 ipp_regs(3),
 160                 ipp_regs(4),
 161                 ipp_regs(5)
 162 };
 163
 164 static const struct dce_ipp_shift ipp_shift = {
 165                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 166 };
 167
 168 static const struct dce_ipp_mask ipp_mask = {
 169                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 170 };
 171
 172 #define transform_regs(id)\
 173 [id] = {\
 174                 XFM_COMMON_REG_LIST_DCE100(id)\
 175 }
 176
 177 static const struct dce_transform_registers xfm_regs[] = {
 178                 transform_regs(0),
 179                 transform_regs(1),
 180                 transform_regs(2),
 181                 transform_regs(3),
 182                 transform_regs(4),
 183                 transform_regs(5)
 184 };
 185
 186 static const struct dce_transform_shift xfm_shift = {
 187                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 188 };
 189
 190 static const struct dce_transform_mask xfm_mask = {
 191                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 192 };
 193
 194 #define aux_regs(id)\
 195 [id] = {\
 196         AUX_REG_LIST(id)\
 197 }
 198
 199 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 200                 aux_regs(0),
 201                 aux_regs(1),
 202                 aux_regs(2),
 203                 aux_regs(3),
 204                 aux_regs(4),
 205                 aux_regs(5)
 206 };
 207
 208 #define hpd_regs(id)\
 209 [id] = {\
 210         HPD_REG_LIST(id)\
 211 }
 212
 213 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 214                 hpd_regs(0),
 215                 hpd_regs(1),
 216                 hpd_regs(2),
 217                 hpd_regs(3),
 218                 hpd_regs(4),
 219                 hpd_regs(5)
 220 };
 221
 222 #define link_regs(id)\
 223 [id] = {\
 224         LE_DCE100_REG_LIST(id)\
 225 }
 226
 227 static const struct dce110_link_enc_registers link_enc_regs[] = {
 228         link_regs(0),
 229         link_regs(1),
 230         link_regs(2),
 231         link_regs(3),
 232         link_regs(4),
 233         link_regs(5),
 234         link_regs(6),
 235 };
 236
 237 #define stream_enc_regs(id)\
 238 [id] = {\
 239         SE_COMMON_REG_LIST_DCE_BASE(id),\
 240         .AFMT_CNTL = 0,\
 241 }
 242
 243 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 244         stream_enc_regs(0),
 245         stream_enc_regs(1),
 246         stream_enc_regs(2),
 247         stream_enc_regs(3),
 248         stream_enc_regs(4),
 249         stream_enc_regs(5),
 250         stream_enc_regs(6)
 251 };
 252
 253 static const struct dce_stream_encoder_shift se_shift = {
 254                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 255 };
 256
 257 static const struct dce_stream_encoder_mask se_mask = {
 258                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 259 };
 260
 261 #define opp_regs(id)\
 262 [id] = {\
 263         OPP_DCE_100_REG_LIST(id),\
 264 }
 265
 266 static const struct dce_opp_registers opp_regs[] = {
 267         opp_regs(0),
 268         opp_regs(1),
 269         opp_regs(2),
 270         opp_regs(3),
 271         opp_regs(4),
 272         opp_regs(5)
 273 };
 274
 275 static const struct dce_opp_shift opp_shift = {
 276         OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
 277 };
 278
 279 static const struct dce_opp_mask opp_mask = {
 280         OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
 281 };
 282
 283
 284 #define audio_regs(id)\
 285 [id] = {\
 286         AUD_COMMON_REG_LIST(id)\
 287 }
 288
 289 static const struct dce_audio_registers audio_regs[] = {
 290         audio_regs(0),
 291         audio_regs(1),
 292         audio_regs(2),
 293         audio_regs(3),
 294         audio_regs(4),
 295         audio_regs(5),
 296         audio_regs(6),
 297 };
 298
 299 static const struct dce_audio_shift audio_shift = {
 300                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 301 };
 302
 303 static const struct dce_aduio_mask audio_mask = {
 304                 AUD_COMMON_MASK_SH_LIST(_MASK)
 305 };
 306
 307 #define clk_src_regs(id)\
 308 [id] = {\
 309         CS_COMMON_REG_LIST_DCE_100_110(id),\
 310 }
 311
 312 static const struct dce110_clk_src_regs clk_src_regs[] = {
 313         clk_src_regs(0),
 314         clk_src_regs(1),
 315         clk_src_regs(2)
 316 };
 317
 318 static const struct dce110_clk_src_shift cs_shift = {
 319                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 320 };
 321
 322 static const struct dce110_clk_src_mask cs_mask = {
 323                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 324 };
 325
 326 static const struct dce_dmcu_registers dmcu_regs = {
 327                 DMCU_DCE110_COMMON_REG_LIST()
 328 };
 329
 330 static const struct dce_dmcu_shift dmcu_shift = {
 331                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 332 };
 333
 334 static const struct dce_dmcu_mask dmcu_mask = {
 335                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 336 };
 337
 338 static const struct dce_abm_registers abm_regs = {
 339                 ABM_DCE110_COMMON_REG_LIST()
 340 };
 341
 342 static const struct dce_abm_shift abm_shift = {
 343                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 344 };
 345
 346 static const struct dce_abm_mask abm_mask = {
 347                 ABM_MASK_SH_LIST_DCE110(_MASK)
 348 };
 349
 350 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
 351
 352 static const struct bios_registers bios_regs = {
 353         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 354 };
 355
 356 static const struct resource_caps res_cap = {
 357         .num_timing_generator = 6,
 358         .num_audio = 6,
 359         .num_stream_encoder = 6,
 360         .num_pll = 3
 361 };
 362
 363 #define CTX  ctx
 364 #define REG(reg) mm ## reg
 365
 366 #ifndef mmCC_DC_HDMI_STRAPS
 367 #define mmCC_DC_HDMI_STRAPS 0x1918
 368 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 369 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 370 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 371 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 372 #endif
 373
 374 static void read_dce_straps(
 375         struct dc_context *ctx,
 376         struct resource_straps *straps)
 377 {
 378         REG_GET_2(CC_DC_HDMI_STRAPS,
 379                         HDMI_DISABLE, &straps->hdmi_disable,
 380                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 381
 382         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 383 }
 384
 385 static struct audio *create_audio(
 386                 struct dc_context *ctx, unsigned int inst)
 387 {
 388         return dce_audio_create(ctx, inst,
 389                         &audio_regs[inst], &audio_shift, &audio_mask);
 390 }
 391
 392 static struct timing_generator *dce100_timing_generator_create(
 393                 struct dc_context *ctx,
 394                 uint32_t instance,
 395                 const struct dce110_timing_generator_offsets *offsets)
 396 {
 397         struct dce110_timing_generator *tg110 =
 398                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 399
 400         if (!tg110)
 401                 return NULL;
 402
 403         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 404         return &tg110->base;
 405 }
 406
 407 static struct stream_encoder *dce100_stream_encoder_create(
 408         enum engine_id eng_id,
 409         struct dc_context *ctx)
 410 {
 411         struct dce110_stream_encoder *enc110 =
 412                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 413
 414         if (!enc110)
 415                 return NULL;
 416
 417         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 418                                         &stream_enc_regs[eng_id], &se_shift, &se_mask);
 419         return &enc110->base;
 420 }
 421
 422 #define SRII(reg_name, block, id)\
 423         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 424
 425 static const struct dce_hwseq_registers hwseq_reg = {
 426                 HWSEQ_DCE10_REG_LIST()
 427 };
 428
 429 static const struct dce_hwseq_shift hwseq_shift = {
 430                 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
 431 };
 432
 433 static const struct dce_hwseq_mask hwseq_mask = {
 434                 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
 435 };
 436
 437 static struct dce_hwseq *dce100_hwseq_create(
 438         struct dc_context *ctx)
 439 {
 440         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 441
 442         if (hws) {
 443                 hws->ctx = ctx;
 444                 hws->regs = &hwseq_reg;
 445                 hws->shifts = &hwseq_shift;
 446                 hws->masks = &hwseq_mask;
 447         }
 448         return hws;
 449 }
 450
 451 static const struct resource_create_funcs res_create_funcs = {
 452         .read_dce_straps = read_dce_straps,
 453         .create_audio = create_audio,
 454         .create_stream_encoder = dce100_stream_encoder_create,
 455         .create_hwseq = dce100_hwseq_create,
 456 };
 457
 458 #define mi_inst_regs(id) { \
 459         MI_DCE8_REG_LIST(id), \
 460         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 461 }
 462 static const struct dce_mem_input_registers mi_regs[] = {
 463                 mi_inst_regs(0),
 464                 mi_inst_regs(1),
 465                 mi_inst_regs(2),
 466                 mi_inst_regs(3),
 467                 mi_inst_regs(4),
 468                 mi_inst_regs(5),
 469 };
 470
 471 static const struct dce_mem_input_shift mi_shifts = {
 472                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 473                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 474 };
 475
 476 static const struct dce_mem_input_mask mi_masks = {
 477                 MI_DCE8_MASK_SH_LIST(_MASK),
 478                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 479 };
 480
 481 static struct mem_input *dce100_mem_input_create(
 482         struct dc_context *ctx,
 483         uint32_t inst)
 484 {
 485         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 486                                                GFP_KERNEL);
 487
 488         if (!dce_mi) {
 489                 BREAK_TO_DEBUGGER();
 490                 return NULL;
 491         }
 492
 493         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 494         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 495         return &dce_mi->base;
 496 }
 497
 498 static void dce100_transform_destroy(struct transform **xfm)
 499 {
 500         kfree(TO_DCE_TRANSFORM(*xfm));
 501         *xfm = NULL;
 502 }
 503
 504 static struct transform *dce100_transform_create(
 505         struct dc_context *ctx,
 506         uint32_t inst)
 507 {
 508         struct dce_transform *transform =
 509                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 510
 511         if (!transform)
 512                 return NULL;
 513
 514         dce_transform_construct(transform, ctx, inst,
 515                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 516         return &transform->base;
 517 }
 518
 519 static struct input_pixel_processor *dce100_ipp_create(
 520         struct dc_context *ctx, uint32_t inst)
 521 {
 522         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 523
 524         if (!ipp) {
 525                 BREAK_TO_DEBUGGER();
 526                 return NULL;
 527         }
 528
 529         dce_ipp_construct(ipp, ctx, inst,
 530                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 531         return &ipp->base;
 532 }
 533
 534 static const struct encoder_feature_support link_enc_feature = {
 535                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 536                 .max_hdmi_pixel_clock = 300000,
 537                 .flags.bits.IS_HBR2_CAPABLE = true,
 538                 .flags.bits.IS_TPS3_CAPABLE = true,
 539                 .flags.bits.IS_YCBCR_CAPABLE = true
 540 };
 541
 542 struct link_encoder *dce100_link_encoder_create(
 543         const struct encoder_init_data *enc_init_data)
 544 {
 545         struct dce110_link_encoder *enc110 =
 546                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 547
 548         if (!enc110)
 549                 return NULL;
 550
 551         dce110_link_encoder_construct(enc110,
 552                                       enc_init_data,
 553                                       &link_enc_feature,
 554                                       &link_enc_regs[enc_init_data->transmitter],
 555                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 556                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 557         return &enc110->base;
 558 }
 559
 560 struct output_pixel_processor *dce100_opp_create(
 561         struct dc_context *ctx,
 562         uint32_t inst)
 563 {
 564         struct dce110_opp *opp =
 565                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 566
 567         if (!opp)
 568                 return NULL;
 569
 570         dce110_opp_construct(opp,
 571                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 572         return &opp->base;
 573 }
 574
 575 struct clock_source *dce100_clock_source_create(
 576         struct dc_context *ctx,
 577         struct dc_bios *bios,
 578         enum clock_source_id id,
 579         const struct dce110_clk_src_regs *regs,
 580         bool dp_clk_src)
 581 {
 582         struct dce110_clk_src *clk_src =
 583                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 584
 585         if (!clk_src)
 586                 return NULL;
 587
 588         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 589                         regs, &cs_shift, &cs_mask)) {
 590                 clk_src->base.dp_clk_src = dp_clk_src;
 591                 return &clk_src->base;
 592         }
 593
 594         BREAK_TO_DEBUGGER();
 595         return NULL;
 596 }
 597
 598 void dce100_clock_source_destroy(struct clock_source **clk_src)
 599 {
 600         kfree(TO_DCE110_CLK_SRC(*clk_src));
 601         *clk_src = NULL;
 602 }
 603
 604 static void destruct(struct dce110_resource_pool *pool)
 605 {
 606         unsigned int i;
 607
 608         for (i = 0; i < pool->base.pipe_count; i++) {
 609                 if (pool->base.opps[i] != NULL)
 610                         dce110_opp_destroy(&pool->base.opps[i]);
 611
 612                 if (pool->base.transforms[i] != NULL)
 613                         dce100_transform_destroy(&pool->base.transforms[i]);
 614
 615                 if (pool->base.ipps[i] != NULL)
 616                         dce_ipp_destroy(&pool->base.ipps[i]);
 617
 618                 if (pool->base.mis[i] != NULL) {
 619                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 620                         pool->base.mis[i] = NULL;
 621                 }
 622
 623                 if (pool->base.timing_generators[i] != NULL)    {
 624                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 625                         pool->base.timing_generators[i] = NULL;
 626                 }
 627         }
 628
 629         for (i = 0; i < pool->base.stream_enc_count; i++) {
 630                 if (pool->base.stream_enc[i] != NULL)
 631                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 632         }
 633
 634         for (i = 0; i < pool->base.clk_src_count; i++) {
 635                 if (pool->base.clock_sources[i] != NULL)
 636                         dce100_clock_source_destroy(&pool->base.clock_sources[i]);
 637         }
 638
 639         if (pool->base.dp_clock_source != NULL)
 640                 dce100_clock_source_destroy(&pool->base.dp_clock_source);
 641
 642         for (i = 0; i < pool->base.audio_count; i++)    {
 643                 if (pool->base.audios[i] != NULL)
 644                         dce_aud_destroy(&pool->base.audios[i]);
 645         }
 646
 647         if (pool->base.display_clock != NULL)
 648                 dce_disp_clk_destroy(&pool->base.display_clock);
 649
 650         if (pool->base.abm != NULL)
 651                                 dce_abm_destroy(&pool->base.abm);
 652
 653         if (pool->base.dmcu != NULL)
 654                         dce_dmcu_destroy(&pool->base.dmcu);
 655
 656         if (pool->base.irqs != NULL)
 657                 dal_irq_service_destroy(&pool->base.irqs);
 658 }
 659
 660 static enum dc_status build_mapped_resource(
 661                 const struct dc  *dc,
 662                 struct dc_state *context,
 663                 struct dc_stream_state *stream)
 664 {
 665         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 666
 667         if (!pipe_ctx)
 668                 return DC_ERROR_UNEXPECTED;
 669
 670         dce110_resource_build_pipe_hw_param(pipe_ctx);
 671
 672         resource_build_info_frame(pipe_ctx);
 673
 674         return DC_OK;
 675 }
 676
 677 bool dce100_validate_bandwidth(
 678         struct dc  *dc,
 679         struct dc_state *context)
 680 {
 681         int i;
 682         bool at_least_one_pipe = false;
 683
 684         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 685                 if (context->res_ctx.pipe_ctx[i].stream)
 686                         at_least_one_pipe = true;
 687         }
 688
 689         if (at_least_one_pipe) {
 690                 /* TODO implement when needed but for now hardcode max value*/
 691                 context->bw.dce.dispclk_khz = 681000;
 692                 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
 693         } else {
 694                 context->bw.dce.dispclk_khz = 0;
 695                 context->bw.dce.yclk_khz = 0;
 696         }
 697
 698         return true;
 699 }
 700
 701 static bool dce100_validate_surface_sets(
 702                 struct dc_state *context)
 703 {
 704         int i;
 705
 706         for (i = 0; i < context->stream_count; i++) {
 707                 if (context->stream_status[i].plane_count == 0)
 708                         continue;
 709
 710                 if (context->stream_status[i].plane_count > 1)
 711                         return false;
 712
 713                 if (context->stream_status[i].plane_states[0]->format
 714                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 715                         return false;
 716         }
 717
 718         return true;
 719 }
 720
 721 enum dc_status dce100_validate_global(
 722                 struct dc  *dc,
 723                 struct dc_state *context)
 724 {
 725         if (!dce100_validate_surface_sets(context))
 726                 return DC_FAIL_SURFACE_VALIDATE;
 727
 728         return DC_OK;
 729 }
 730
 731 enum dc_status dce100_add_stream_to_ctx(
 732                 struct dc *dc,
 733                 struct dc_state *new_ctx,
 734                 struct dc_stream_state *dc_stream)
 735 {
 736         enum dc_status result = DC_ERROR_UNEXPECTED;
 737
 738         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
 739
 740         if (result == DC_OK)
 741                 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
 742
 743         if (result == DC_OK)
 744                 result = build_mapped_resource(dc, new_ctx, dc_stream);
 745
 746         return result;
 747 }
 748
 749 static void dce100_destroy_resource_pool(struct resource_pool **pool)
 750 {
 751         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 752
 753         destruct(dce110_pool);
 754         kfree(dce110_pool);
 755         *pool = NULL;
 756 }
 757
 758 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
 759 {
 760
 761         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 762                 return DC_OK;
 763
 764         return DC_FAIL_SURFACE_VALIDATE;
 765 }
 766
 767 static const struct resource_funcs dce100_res_pool_funcs = {
 768         .destroy = dce100_destroy_resource_pool,
 769         .link_enc_create = dce100_link_encoder_create,
 770         .validate_bandwidth = dce100_validate_bandwidth,
 771         .validate_plane = dce100_validate_plane,
 772         .add_stream_to_ctx = dce100_add_stream_to_ctx,
 773         .validate_global = dce100_validate_global
 774 };
 775
 776 static bool construct(
 777         uint8_t num_virtual_links,
 778         struct dc  *dc,
 779         struct dce110_resource_pool *pool)
 780 {
 781         unsigned int i;
 782         struct dc_context *ctx = dc->ctx;
 783         struct dc_firmware_info info;
 784         struct dc_bios *bp;
 785         struct dm_pp_static_clock_info static_clk_info = {0};
 786
 787         ctx->dc_bios->regs = &bios_regs;
 788
 789         pool->base.res_cap = &res_cap;
 790         pool->base.funcs = &dce100_res_pool_funcs;
 791         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 792
 793         bp = ctx->dc_bios;
 794
 795         if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
 796                 info.external_clock_source_frequency_for_dp != 0) {
 797                 pool->base.dp_clock_source =
 798                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 799
 800                 pool->base.clock_sources[0] =
 801                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 802                 pool->base.clock_sources[1] =
 803                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 804                 pool->base.clock_sources[2] =
 805                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 806                 pool->base.clk_src_count = 3;
 807
 808         } else {
 809                 pool->base.dp_clock_source =
 810                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 811
 812                 pool->base.clock_sources[0] =
 813                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 814                 pool->base.clock_sources[1] =
 815                                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 816                 pool->base.clk_src_count = 2;
 817         }
 818
 819         if (pool->base.dp_clock_source == NULL) {
 820                 dm_error("DC: failed to create dp clock source!\n");
 821                 BREAK_TO_DEBUGGER();
 822                 goto res_create_fail;
 823         }
 824
 825         for (i = 0; i < pool->base.clk_src_count; i++) {
 826                 if (pool->base.clock_sources[i] == NULL) {
 827                         dm_error("DC: failed to create clock sources!\n");
 828                         BREAK_TO_DEBUGGER();
 829                         goto res_create_fail;
 830                 }
 831         }
 832
 833         pool->base.display_clock = dce_disp_clk_create(ctx,
 834                         &disp_clk_regs,
 835                         &disp_clk_shift,
 836                         &disp_clk_mask);
 837         if (pool->base.display_clock == NULL) {
 838                 dm_error("DC: failed to create display clock!\n");
 839                 BREAK_TO_DEBUGGER();
 840                 goto res_create_fail;
 841         }
 842
 843         pool->base.dmcu = dce_dmcu_create(ctx,
 844                         &dmcu_regs,
 845                         &dmcu_shift,
 846                         &dmcu_mask);
 847         if (pool->base.dmcu == NULL) {
 848                 dm_error("DC: failed to create dmcu!\n");
 849                 BREAK_TO_DEBUGGER();
 850                 goto res_create_fail;
 851         }
 852
 853         pool->base.abm = dce_abm_create(ctx,
 854                                 &abm_regs,
 855                                 &abm_shift,
 856                                 &abm_mask);
 857         if (pool->base.abm == NULL) {
 858                 dm_error("DC: failed to create abm!\n");
 859                 BREAK_TO_DEBUGGER();
 860                 goto res_create_fail;
 861         }
 862
 863         /* get static clock information for PPLIB or firmware, save
 864          * max_clock_state
 865          */
 866         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 867                 pool->base.display_clock->max_clks_state =
 868                                         static_clk_info.max_clocks_state;
 869         {
 870                 struct irq_service_init_data init_data;
 871                 init_data.ctx = dc->ctx;
 872                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
 873                 if (!pool->base.irqs)
 874                         goto res_create_fail;
 875         }
 876
 877         /*************************************************
 878         *  Resource + asic cap harcoding                *
 879         *************************************************/
 880         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 881         pool->base.pipe_count = res_cap.num_timing_generator;
 882         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
 883         dc->caps.max_downscale_ratio = 200;
 884         dc->caps.i2c_speed_in_khz = 40;
 885         dc->caps.max_cursor_size = 128;
 886         dc->caps.dual_link_dvi = true;
 887
 888         for (i = 0; i < pool->base.pipe_count; i++) {
 889                 pool->base.timing_generators[i] =
 890                         dce100_timing_generator_create(
 891                                 ctx,
 892                                 i,
 893                                 &dce100_tg_offsets[i]);
 894                 if (pool->base.timing_generators[i] == NULL) {
 895                         BREAK_TO_DEBUGGER();
 896                         dm_error("DC: failed to create tg!\n");
 897                         goto res_create_fail;
 898                 }
 899
 900                 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
 901                 if (pool->base.mis[i] == NULL) {
 902                         BREAK_TO_DEBUGGER();
 903                         dm_error(
 904                                 "DC: failed to create memory input!\n");
 905                         goto res_create_fail;
 906                 }
 907
 908                 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
 909                 if (pool->base.ipps[i] == NULL) {
 910                         BREAK_TO_DEBUGGER();
 911                         dm_error(
 912                                 "DC: failed to create input pixel processor!\n");
 913                         goto res_create_fail;
 914                 }
 915
 916                 pool->base.transforms[i] = dce100_transform_create(ctx, i);
 917                 if (pool->base.transforms[i] == NULL) {
 918                         BREAK_TO_DEBUGGER();
 919                         dm_error(
 920                                 "DC: failed to create transform!\n");
 921                         goto res_create_fail;
 922                 }
 923
 924                 pool->base.opps[i] = dce100_opp_create(ctx, i);
 925                 if (pool->base.opps[i] == NULL) {
 926                         BREAK_TO_DEBUGGER();
 927                         dm_error(
 928                                 "DC: failed to create output pixel processor!\n");
 929                         goto res_create_fail;
 930                 }
 931         }
 932
 933         dc->caps.max_planes =  pool->base.pipe_count;
 934
 935         if (!resource_construct(num_virtual_links, dc, &pool->base,
 936                         &res_create_funcs))
 937                 goto res_create_fail;
 938
 939         /* Create hardware sequencer */
 940         dce100_hw_sequencer_construct(dc);
 941         return true;
 942
 943 res_create_fail:
 944         destruct(pool);
 945
 946         return false;
 947 }
 948
 949 struct resource_pool *dce100_create_resource_pool(
 950         uint8_t num_virtual_links,
 951         struct dc  *dc)
 952 {
 953         struct dce110_resource_pool *pool =
 954                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
 955
 956         if (!pool)
 957                 return NULL;
 958
 959         if (construct(num_virtual_links, dc, pool))
 960                 return &pool->base;
 961
 962         BREAK_TO_DEBUGGER();
 963         return NULL;
 964 }
 965