drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc_bios_types.h"
  27 #include "dce_stream_encoder.h"
  28 #include "reg_helper.h"
  29
  30 enum DP_PIXEL_ENCODING {
  31 DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
  32 DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
  33 DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
  34 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
  35 DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
  36 DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
  37 DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
  38 };
  39
  40
  41 enum DP_COMPONENT_DEPTH {
  42 DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
  43 DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
  44 DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
  45 DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
  46 DP_COMPONENT_DEPTH_16BPC                 = 0x00000004,
  47 DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
  48 };
  49
  50
  51 #define REG(reg)\
  52         (enc110->regs->reg)
  53
  54 #undef FN
  55 #define FN(reg_name, field_name) \
  56         enc110->se_shift->field_name, enc110->se_mask->field_name
  57
  58 #define VBI_LINE_0 0
  59 #define DP_BLANK_MAX_RETRY 20
  60 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  61
  62 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
  63         #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
  64         #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
  65         #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
  66         #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
  67 #endif
  68
  69 enum {
  70         DP_MST_UPDATE_MAX_RETRY = 50
  71 };
  72
  73 #define DCE110_SE(audio)\
  74         container_of(audio, struct dce110_stream_encoder, base)
  75
  76 #define CTX \
  77         enc110->base.ctx
  78
  79 static void dce110_update_generic_info_packet(
  80         struct dce110_stream_encoder *enc110,
  81         uint32_t packet_index,
  82         const struct encoder_info_packet *info_packet)
  83 {
  84         uint32_t regval;
  85         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  86          * use 50 for now.
  87          */
  88         uint32_t max_retries = 50;
  89
  90         /*we need turn on clock before programming AFMT block*/
  91         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  92
  93         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
  94                 if (packet_index >= 8)
  95                         ASSERT(0);
  96
  97                 /* poll dig_update_lock is not locked -> asic internal signal
  98                  * assume otg master lock will unlock it
  99                  */
 100 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
 101                                 0, 10, max_retries);*/
 102
 103                 /* check if HW reading GSP memory */
 104                 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
 105                                 0, 10, max_retries);
 106
 107                 /* HW does is not reading GSP memory not reading too long ->
 108                  * something wrong. clear GPS memory access and notify?
 109                  * hw SW is writing to GSP memory
 110                  */
 111                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
 112         }
 113         /* choose which generic packet to use */
 114         {
 115                 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
 116                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
 117                                 AFMT_GENERIC_INDEX, packet_index);
 118         }
 119
 120         /* write generic packet header
 121          * (4th byte is for GENERIC0 only) */
 122         {
 123                 REG_SET_4(AFMT_GENERIC_HDR, 0,
 124                                 AFMT_GENERIC_HB0, info_packet->hb0,
 125                                 AFMT_GENERIC_HB1, info_packet->hb1,
 126                                 AFMT_GENERIC_HB2, info_packet->hb2,
 127                                 AFMT_GENERIC_HB3, info_packet->hb3);
 128         }
 129
 130         /* write generic packet contents
 131          * (we never use last 4 bytes)
 132          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
 133         {
 134                 const uint32_t *content =
 135                         (const uint32_t *) &info_packet->sb[0];
 136
 137                 REG_WRITE(AFMT_GENERIC_0, *content++);
 138                 REG_WRITE(AFMT_GENERIC_1, *content++);
 139                 REG_WRITE(AFMT_GENERIC_2, *content++);
 140                 REG_WRITE(AFMT_GENERIC_3, *content++);
 141                 REG_WRITE(AFMT_GENERIC_4, *content++);
 142                 REG_WRITE(AFMT_GENERIC_5, *content++);
 143                 REG_WRITE(AFMT_GENERIC_6, *content++);
 144                 REG_WRITE(AFMT_GENERIC_7, *content);
 145         }
 146
 147         if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
 148                 /* force double-buffered packet update */
 149                 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
 150                         AFMT_GENERIC0_UPDATE, (packet_index == 0),
 151                         AFMT_GENERIC2_UPDATE, (packet_index == 2));
 152         }
 153 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 154         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
 155                 switch (packet_index) {
 156                 case 0:
 157                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 158                                         AFMT_GENERIC0_FRAME_UPDATE, 1);
 159                         break;
 160                 case 1:
 161                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 162                                         AFMT_GENERIC1_FRAME_UPDATE, 1);
 163                         break;
 164                 case 2:
 165                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 166                                         AFMT_GENERIC2_FRAME_UPDATE, 1);
 167                         break;
 168                 case 3:
 169                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 170                                         AFMT_GENERIC3_FRAME_UPDATE, 1);
 171                         break;
 172                 case 4:
 173                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 174                                         AFMT_GENERIC4_FRAME_UPDATE, 1);
 175                         break;
 176                 case 5:
 177                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 178                                         AFMT_GENERIC5_FRAME_UPDATE, 1);
 179                         break;
 180                 case 6:
 181                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 182                                         AFMT_GENERIC6_FRAME_UPDATE, 1);
 183                         break;
 184                 case 7:
 185                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 186                                         AFMT_GENERIC7_FRAME_UPDATE, 1);
 187                         break;
 188                 default:
 189                         break;
 190                 }
 191         }
 192 #endif
 193 }
 194
 195 static void dce110_update_hdmi_info_packet(
 196         struct dce110_stream_encoder *enc110,
 197         uint32_t packet_index,
 198         const struct encoder_info_packet *info_packet)
 199 {
 200         struct dc_context *ctx = enc110->base.ctx;
 201         uint32_t cont, send, line;
 202
 203         if (info_packet->valid) {
 204                 dce110_update_generic_info_packet(
 205                         enc110,
 206                         packet_index,
 207                         info_packet);
 208
 209                 /* enable transmission of packet(s) -
 210                  * packet transmission begins on the next frame */
 211                 cont = 1;
 212                 /* send packet(s) every frame */
 213                 send = 1;
 214                 /* select line number to send packets on */
 215                 line = 2;
 216         } else {
 217                 cont = 0;
 218                 send = 0;
 219                 line = 0;
 220         }
 221
 222         /* choose which generic packet control to use */
 223         switch (packet_index) {
 224         case 0:
 225                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 226                                 HDMI_GENERIC0_CONT, cont,
 227                                 HDMI_GENERIC0_SEND, send,
 228                                 HDMI_GENERIC0_LINE, line);
 229                 break;
 230         case 1:
 231                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 232                                 HDMI_GENERIC1_CONT, cont,
 233                                 HDMI_GENERIC1_SEND, send,
 234                                 HDMI_GENERIC1_LINE, line);
 235                 break;
 236         case 2:
 237                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 238                                 HDMI_GENERIC0_CONT, cont,
 239                                 HDMI_GENERIC0_SEND, send,
 240                                 HDMI_GENERIC0_LINE, line);
 241                 break;
 242         case 3:
 243                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 244                                 HDMI_GENERIC1_CONT, cont,
 245                                 HDMI_GENERIC1_SEND, send,
 246                                 HDMI_GENERIC1_LINE, line);
 247                 break;
 248 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 249         case 4:
 250                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 251                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 252                                         HDMI_GENERIC0_CONT, cont,
 253                                         HDMI_GENERIC0_SEND, send,
 254                                         HDMI_GENERIC0_LINE, line);
 255                 break;
 256         case 5:
 257                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 258                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 259                                         HDMI_GENERIC1_CONT, cont,
 260                                         HDMI_GENERIC1_SEND, send,
 261                                         HDMI_GENERIC1_LINE, line);
 262                 break;
 263         case 6:
 264                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 265                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 266                                         HDMI_GENERIC0_CONT, cont,
 267                                         HDMI_GENERIC0_SEND, send,
 268                                         HDMI_GENERIC0_LINE, line);
 269                 break;
 270         case 7:
 271                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 272                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 273                                         HDMI_GENERIC1_CONT, cont,
 274                                         HDMI_GENERIC1_SEND, send,
 275                                         HDMI_GENERIC1_LINE, line);
 276                 break;
 277 #endif
 278         default:
 279                 /* invalid HW packet index */
 280                 dm_logger_write(
 281                         ctx->logger, LOG_WARNING,
 282                         "Invalid HW packet index: %s()\n",
 283                         __func__);
 284                 return;
 285         }
 286 }
 287
 288 /* setup stream encoder in dp mode */
 289 static void dce110_stream_encoder_dp_set_stream_attribute(
 290         struct stream_encoder *enc,
 291         struct dc_crtc_timing *crtc_timing,
 292         enum dc_color_space output_color_space)
 293 {
 294 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 295         uint32_t h_active_start;
 296         uint32_t v_active_start;
 297         uint32_t misc0 = 0;
 298         uint32_t misc1 = 0;
 299         uint32_t h_blank;
 300         uint32_t h_back_porch;
 301         uint8_t synchronous_clock = 0; /* asynchronous mode */
 302         uint8_t colorimetry_bpc;
 303 #endif
 304
 305         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 306
 307 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 308         if (REG(DP_DB_CNTL))
 309                 REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
 310 #endif
 311
 312         /* set pixel encoding */
 313         switch (crtc_timing->pixel_encoding) {
 314         case PIXEL_ENCODING_YCBCR422:
 315                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 316                                 DP_PIXEL_ENCODING_YCBCR422);
 317                 break;
 318         case PIXEL_ENCODING_YCBCR444:
 319                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 320                                 DP_PIXEL_ENCODING_YCBCR444);
 321
 322                 if (crtc_timing->flags.Y_ONLY)
 323                         if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
 324                                 /* HW testing only, no use case yet.
 325                                  * Color depth of Y-only could be
 326                                  * 8, 10, 12, 16 bits */
 327                                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 328                                                 DP_PIXEL_ENCODING_Y_ONLY);
 329                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 330                  * of Y-only mode.
 331                  * This bit is set in HW if register
 332                  * DP_PIXEL_ENCODING is programmed to 0x4 */
 333                 break;
 334         case PIXEL_ENCODING_YCBCR420:
 335                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 336                                 DP_PIXEL_ENCODING_YCBCR420);
 337                 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
 338                         REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
 339
 340 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 341                 if (enc110->se_mask->DP_VID_N_MUL)
 342                         REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 343 #endif
 344                 break;
 345         default:
 346                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 347                                 DP_PIXEL_ENCODING_RGB444);
 348                 break;
 349         }
 350
 351 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 352         if (REG(DP_MSA_MISC))
 353                 misc1 = REG_READ(DP_MSA_MISC);
 354 #endif
 355
 356         /* set color depth */
 357
 358         switch (crtc_timing->display_color_depth) {
 359         case COLOR_DEPTH_666:
 360                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 361                                 0);
 362                 break;
 363         case COLOR_DEPTH_888:
 364                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 365                                 DP_COMPONENT_DEPTH_8BPC);
 366                 break;
 367         case COLOR_DEPTH_101010:
 368                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 369                                 DP_COMPONENT_DEPTH_10BPC);
 370
 371                 break;
 372         case COLOR_DEPTH_121212:
 373                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 374                                 DP_COMPONENT_DEPTH_12BPC);
 375                 break;
 376         default:
 377                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 378                                 DP_COMPONENT_DEPTH_6BPC);
 379                 break;
 380         }
 381
 382         /* set dynamic range and YCbCr range */
 383         if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
 384                 REG_UPDATE_2(
 385                         DP_PIXEL_FORMAT,
 386                         DP_DYN_RANGE, 0,
 387                         DP_YCBCR_RANGE, 0);
 388
 389 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 390         switch (crtc_timing->display_color_depth) {
 391         case COLOR_DEPTH_666:
 392                 colorimetry_bpc = 0;
 393                 break;
 394         case COLOR_DEPTH_888:
 395                 colorimetry_bpc = 1;
 396                 break;
 397         case COLOR_DEPTH_101010:
 398                 colorimetry_bpc = 2;
 399                 break;
 400         case COLOR_DEPTH_121212:
 401                 colorimetry_bpc = 3;
 402                 break;
 403         default:
 404                 colorimetry_bpc = 0;
 405                 break;
 406         }
 407
 408         misc0 = misc0 | synchronous_clock;
 409         misc0 = colorimetry_bpc << 5;
 410
 411         if (REG(DP_MSA_TIMING_PARAM1)) {
 412                 switch (output_color_space) {
 413                 case COLOR_SPACE_SRGB:
 414                         misc0 = misc0 | 0x0;
 415                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 416                         break;
 417                 case COLOR_SPACE_SRGB_LIMITED:
 418                         misc0 = misc0 | 0x8; /* bit3=1 */
 419                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 420                         break;
 421                 case COLOR_SPACE_YCBCR601:
 422                         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 423                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 424                         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 425                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 426                         else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
 427                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 428                         break;
 429                 case COLOR_SPACE_YCBCR709:
 430                         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 431                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 432                         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 433                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 434                         else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
 435                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 436                         break;
 437                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 438                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 439                 case COLOR_SPACE_2020_YCBCR:
 440                 case COLOR_SPACE_ADOBERGB:
 441                 case COLOR_SPACE_UNKNOWN:
 442                 case COLOR_SPACE_YCBCR601_LIMITED:
 443                 case COLOR_SPACE_YCBCR709_LIMITED:
 444                         /* do nothing */
 445                         break;
 446                 }
 447
 448 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 449                 if (REG(DP_MSA_COLORIMETRY))
 450                         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 451
 452                 if (REG(DP_MSA_MISC))
 453                         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 454
 455         /* dcn new register
 456          * dc_crtc_timing is vesa dmt struct. data from edid
 457          */
 458                 if (REG(DP_MSA_TIMING_PARAM1))
 459                         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 460                                         DP_MSA_HTOTAL, crtc_timing->h_total,
 461                                         DP_MSA_VTOTAL, crtc_timing->v_total);
 462 #endif
 463
 464                 /* calcuate from vesa timing parameters
 465                  * h_active_start related to leading edge of sync
 466                  */
 467
 468                 h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
 469                                 crtc_timing->h_addressable - crtc_timing->h_border_right;
 470
 471                 h_back_porch = h_blank - crtc_timing->h_front_porch -
 472                                 crtc_timing->h_sync_width;
 473
 474                 /* start at begining of left border */
 475                 h_active_start = crtc_timing->h_sync_width + h_back_porch;
 476
 477
 478                 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
 479                                 crtc_timing->v_addressable - crtc_timing->v_border_bottom -
 480                                 crtc_timing->v_front_porch;
 481
 482
 483 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 484                 /* start at begining of left border */
 485                 if (REG(DP_MSA_TIMING_PARAM2))
 486                         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 487                                 DP_MSA_HSTART, h_active_start,
 488                                 DP_MSA_VSTART, v_active_start);
 489
 490                 if (REG(DP_MSA_TIMING_PARAM3))
 491                         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 492                                         DP_MSA_HSYNCWIDTH,
 493                                         crtc_timing->h_sync_width,
 494                                         DP_MSA_HSYNCPOLARITY,
 495                                         !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
 496                                         DP_MSA_VSYNCWIDTH,
 497                                         crtc_timing->v_sync_width,
 498                                         DP_MSA_VSYNCPOLARITY,
 499                                         !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
 500
 501                 /* HWDITH include border or overscan */
 502                 if (REG(DP_MSA_TIMING_PARAM4))
 503                         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 504                                 DP_MSA_HWIDTH, crtc_timing->h_border_left +
 505                                 crtc_timing->h_addressable + crtc_timing->h_border_right,
 506                                 DP_MSA_VHEIGHT, crtc_timing->v_border_top +
 507                                 crtc_timing->v_addressable + crtc_timing->v_border_bottom);
 508 #endif
 509         }
 510 #endif
 511 }
 512
 513 static void dce110_stream_encoder_set_stream_attribute_helper(
 514                 struct dce110_stream_encoder *enc110,
 515                 struct dc_crtc_timing *crtc_timing)
 516 {
 517         if (enc110->regs->TMDS_CNTL) {
 518                 switch (crtc_timing->pixel_encoding) {
 519                 case PIXEL_ENCODING_YCBCR422:
 520                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
 521                         break;
 522                 default:
 523                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
 524                         break;
 525                 }
 526                 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
 527         } else if (enc110->regs->DIG_FE_CNTL) {
 528                 switch (crtc_timing->pixel_encoding) {
 529                 case PIXEL_ENCODING_YCBCR422:
 530                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 531                         break;
 532                 default:
 533                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 534                         break;
 535                 }
 536                 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 537         }
 538
 539 }
 540
 541 /* setup stream encoder in hdmi mode */
 542 static void dce110_stream_encoder_hdmi_set_stream_attribute(
 543         struct stream_encoder *enc,
 544         struct dc_crtc_timing *crtc_timing,
 545         int actual_pix_clk_khz,
 546         bool enable_audio)
 547 {
 548         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 549         struct bp_encoder_control cntl = {0};
 550
 551         cntl.action = ENCODER_CONTROL_SETUP;
 552         cntl.engine_id = enc110->base.id;
 553         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 554         cntl.enable_dp_audio = enable_audio;
 555         cntl.pixel_clock = actual_pix_clk_khz;
 556         cntl.lanes_number = LANE_COUNT_FOUR;
 557
 558         if (enc110->base.bp->funcs->encoder_control(
 559                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 560                 return;
 561
 562         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 563
 564         /* setup HDMI engine */
 565         if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 566                 REG_UPDATE_3(HDMI_CONTROL,
 567                         HDMI_PACKET_GEN_VERSION, 1,
 568                         HDMI_KEEPOUT_MODE, 1,
 569                         HDMI_DEEP_COLOR_ENABLE, 0);
 570         } else if (enc110->regs->DIG_FE_CNTL) {
 571                 REG_UPDATE_5(HDMI_CONTROL,
 572                         HDMI_PACKET_GEN_VERSION, 1,
 573                         HDMI_KEEPOUT_MODE, 1,
 574                         HDMI_DEEP_COLOR_ENABLE, 0,
 575                         HDMI_DATA_SCRAMBLE_EN, 0,
 576                         HDMI_CLOCK_CHANNEL_RATE, 0);
 577         }
 578
 579         switch (crtc_timing->display_color_depth) {
 580         case COLOR_DEPTH_888:
 581                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 582                 break;
 583         case COLOR_DEPTH_101010:
 584                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 585                         REG_UPDATE_2(HDMI_CONTROL,
 586                                         HDMI_DEEP_COLOR_DEPTH, 1,
 587                                         HDMI_DEEP_COLOR_ENABLE, 0);
 588                 } else {
 589                         REG_UPDATE_2(HDMI_CONTROL,
 590                                         HDMI_DEEP_COLOR_DEPTH, 1,
 591                                         HDMI_DEEP_COLOR_ENABLE, 1);
 592                         }
 593                 break;
 594         case COLOR_DEPTH_121212:
 595                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 596                         REG_UPDATE_2(HDMI_CONTROL,
 597                                         HDMI_DEEP_COLOR_DEPTH, 2,
 598                                         HDMI_DEEP_COLOR_ENABLE, 0);
 599                 } else {
 600                         REG_UPDATE_2(HDMI_CONTROL,
 601                                         HDMI_DEEP_COLOR_DEPTH, 2,
 602                                         HDMI_DEEP_COLOR_ENABLE, 1);
 603                         }
 604                 break;
 605         case COLOR_DEPTH_161616:
 606                 REG_UPDATE_2(HDMI_CONTROL,
 607                                 HDMI_DEEP_COLOR_DEPTH, 3,
 608                                 HDMI_DEEP_COLOR_ENABLE, 1);
 609                 break;
 610         default:
 611                 break;
 612         }
 613
 614         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 615                 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 616                         /* enable HDMI data scrambler
 617                          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 618                          * Clock channel frequency is 1/4 of character rate.
 619                          */
 620                         REG_UPDATE_2(HDMI_CONTROL,
 621                                 HDMI_DATA_SCRAMBLE_EN, 1,
 622                                 HDMI_CLOCK_CHANNEL_RATE, 1);
 623                 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 624
 625                         /* TODO: New feature for DCE11, still need to implement */
 626
 627                         /* enable HDMI data scrambler
 628                          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 629                          * Clock channel frequency is the same
 630                          * as character rate
 631                          */
 632                         REG_UPDATE_2(HDMI_CONTROL,
 633                                 HDMI_DATA_SCRAMBLE_EN, 1,
 634                                 HDMI_CLOCK_CHANNEL_RATE, 0);
 635                 }
 636         }
 637
 638         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 639                 HDMI_GC_CONT, 1,
 640                 HDMI_GC_SEND, 1,
 641                 HDMI_NULL_SEND, 1);
 642
 643         /* following belongs to audio */
 644         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 645
 646         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 647
 648         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 649                                 VBI_LINE_0 + 2);
 650
 651         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 652
 653 }
 654
 655 /* setup stream encoder in dvi mode */
 656 static void dce110_stream_encoder_dvi_set_stream_attribute(
 657         struct stream_encoder *enc,
 658         struct dc_crtc_timing *crtc_timing,
 659         bool is_dual_link)
 660 {
 661         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 662         struct bp_encoder_control cntl = {0};
 663
 664         cntl.action = ENCODER_CONTROL_SETUP;
 665         cntl.engine_id = enc110->base.id;
 666         cntl.signal = is_dual_link ?
 667                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 668         cntl.enable_dp_audio = false;
 669         cntl.pixel_clock = crtc_timing->pix_clk_khz;
 670         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 671
 672         if (enc110->base.bp->funcs->encoder_control(
 673                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 674                 return;
 675
 676         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 677         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 678         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 679 }
 680
 681 static void dce110_stream_encoder_set_mst_bandwidth(
 682         struct stream_encoder *enc,
 683         struct fixed31_32 avg_time_slots_per_mtp)
 684 {
 685         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 686         uint32_t x = dal_fixed31_32_floor(
 687                 avg_time_slots_per_mtp);
 688         uint32_t y = dal_fixed31_32_ceil(
 689                 dal_fixed31_32_shl(
 690                         dal_fixed31_32_sub_int(
 691                                 avg_time_slots_per_mtp,
 692                                 x),
 693                         26));
 694
 695         {
 696                 REG_SET_2(DP_MSE_RATE_CNTL, 0,
 697                         DP_MSE_RATE_X, x,
 698                         DP_MSE_RATE_Y, y);
 699         }
 700
 701         /* wait for update to be completed on the link */
 702         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 703         /* is reset to 0 (not pending) */
 704         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 705                         0,
 706                         10, DP_MST_UPDATE_MAX_RETRY);
 707 }
 708
 709 static void dce110_stream_encoder_update_hdmi_info_packets(
 710         struct stream_encoder *enc,
 711         const struct encoder_info_frame *info_frame)
 712 {
 713         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 714
 715         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 716                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 717
 718                 if (info_frame->avi.valid) {
 719                         const uint32_t *content =
 720                                 (const uint32_t *) &info_frame->avi.sb[0];
 721
 722                         REG_WRITE(AFMT_AVI_INFO0, content[0]);
 723
 724                         REG_WRITE(AFMT_AVI_INFO1, content[1]);
 725
 726                         REG_WRITE(AFMT_AVI_INFO2, content[2]);
 727
 728                         REG_WRITE(AFMT_AVI_INFO3, content[3]);
 729
 730                         REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
 731                                                 info_frame->avi.hb1);
 732
 733                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 734                                         HDMI_AVI_INFO_SEND, 1,
 735                                         HDMI_AVI_INFO_CONT, 1);
 736
 737                         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
 738                                                         VBI_LINE_0 + 2);
 739
 740                 } else {
 741                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 742                                 HDMI_AVI_INFO_SEND, 0,
 743                                 HDMI_AVI_INFO_CONT, 0);
 744                 }
 745         }
 746
 747         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 748                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 749                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
 750                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
 751                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
 752                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
 753         }
 754
 755 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 756         if (enc110->se_mask->HDMI_DB_DISABLE) {
 757                 /* for bring up, disable dp double  TODO */
 758                 if (REG(HDMI_DB_CONTROL))
 759                         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 760
 761                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
 762                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
 763                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
 764                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
 765                 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
 766         }
 767 #endif
 768 }
 769
 770 static void dce110_stream_encoder_stop_hdmi_info_packets(
 771         struct stream_encoder *enc)
 772 {
 773         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 774
 775         /* stop generic packets 0 & 1 on HDMI */
 776         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 777                 HDMI_GENERIC1_CONT, 0,
 778                 HDMI_GENERIC1_LINE, 0,
 779                 HDMI_GENERIC1_SEND, 0,
 780                 HDMI_GENERIC0_CONT, 0,
 781                 HDMI_GENERIC0_LINE, 0,
 782                 HDMI_GENERIC0_SEND, 0);
 783
 784         /* stop generic packets 2 & 3 on HDMI */
 785         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 786                 HDMI_GENERIC0_CONT, 0,
 787                 HDMI_GENERIC0_LINE, 0,
 788                 HDMI_GENERIC0_SEND, 0,
 789                 HDMI_GENERIC1_CONT, 0,
 790                 HDMI_GENERIC1_LINE, 0,
 791                 HDMI_GENERIC1_SEND, 0);
 792
 793 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 794         /* stop generic packets 2 & 3 on HDMI */
 795         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 796                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 797                         HDMI_GENERIC0_CONT, 0,
 798                         HDMI_GENERIC0_LINE, 0,
 799                         HDMI_GENERIC0_SEND, 0,
 800                         HDMI_GENERIC1_CONT, 0,
 801                         HDMI_GENERIC1_LINE, 0,
 802                         HDMI_GENERIC1_SEND, 0);
 803
 804         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 805                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 806                         HDMI_GENERIC0_CONT, 0,
 807                         HDMI_GENERIC0_LINE, 0,
 808                         HDMI_GENERIC0_SEND, 0,
 809                         HDMI_GENERIC1_CONT, 0,
 810                         HDMI_GENERIC1_LINE, 0,
 811                         HDMI_GENERIC1_SEND, 0);
 812 #endif
 813 }
 814
 815 static void dce110_stream_encoder_update_dp_info_packets(
 816         struct stream_encoder *enc,
 817         const struct encoder_info_frame *info_frame)
 818 {
 819         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 820         uint32_t value = REG_READ(DP_SEC_CNTL);
 821
 822         if (info_frame->vsc.valid)
 823                 dce110_update_generic_info_packet(
 824                                         enc110,
 825                                         0,  /* packetIndex */
 826                                         &info_frame->vsc);
 827
 828         if (info_frame->spd.valid)
 829                 dce110_update_generic_info_packet(
 830                                 enc110,
 831                                 2,  /* packetIndex */
 832                                 &info_frame->spd);
 833
 834         if (info_frame->hdrsmd.valid)
 835                 dce110_update_generic_info_packet(
 836                                 enc110,
 837                                 3,  /* packetIndex */
 838                                 &info_frame->hdrsmd);
 839
 840         /* enable/disable transmission of packet(s).
 841         *  If enabled, packet transmission begins on the next frame
 842         */
 843         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 844         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 845         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 846
 847         /* This bit is the master enable bit.
 848         * When enabling secondary stream engine,
 849         * this master bit must also be set.
 850         * This register shared with audio info frame.
 851         * Therefore we need to enable master bit
 852         * if at least on of the fields is not 0
 853         */
 854         if (value)
 855                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 856 }
 857
 858 static void dce110_stream_encoder_stop_dp_info_packets(
 859         struct stream_encoder *enc)
 860 {
 861         /* stop generic packets on DP */
 862         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 863         uint32_t value = REG_READ(DP_SEC_CNTL);
 864
 865         if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
 866                 REG_SET_7(DP_SEC_CNTL, 0,
 867                         DP_SEC_GSP0_ENABLE, 0,
 868                         DP_SEC_GSP1_ENABLE, 0,
 869                         DP_SEC_GSP2_ENABLE, 0,
 870                         DP_SEC_GSP3_ENABLE, 0,
 871                         DP_SEC_AVI_ENABLE, 0,
 872                         DP_SEC_MPG_ENABLE, 0,
 873                         DP_SEC_STREAM_ENABLE, 0);
 874         }
 875
 876 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 877         if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
 878                 REG_SET_10(DP_SEC_CNTL, 0,
 879                         DP_SEC_GSP0_ENABLE, 0,
 880                         DP_SEC_GSP1_ENABLE, 0,
 881                         DP_SEC_GSP2_ENABLE, 0,
 882                         DP_SEC_GSP3_ENABLE, 0,
 883                         DP_SEC_GSP4_ENABLE, 0,
 884                         DP_SEC_GSP5_ENABLE, 0,
 885                         DP_SEC_GSP6_ENABLE, 0,
 886                         DP_SEC_GSP7_ENABLE, 0,
 887                         DP_SEC_MPG_ENABLE, 0,
 888                         DP_SEC_STREAM_ENABLE, 0);
 889         }
 890 #endif
 891         /* this register shared with audio info frame.
 892          * therefore we need to keep master enabled
 893          * if at least one of the fields is not 0 */
 894
 895         if (value)
 896                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 897
 898 }
 899
 900 static void dce110_stream_encoder_dp_blank(
 901         struct stream_encoder *enc)
 902 {
 903         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 904         uint32_t retries = 0;
 905         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 906
 907         /* Note: For CZ, we are changing driver default to disable
 908          * stream deferred to next VBLANK. If results are positive, we
 909          * will make the same change to all DCE versions. There are a
 910          * handful of panels that cannot handle disable stream at
 911          * HBLANK and will result in a white line flash across the
 912          * screen on stream disable. */
 913
 914         /* Specify the video stream disable point
 915          * (2 = start of the next vertical blank) */
 916         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 917         /* Larger delay to wait until VBLANK - use max retry of
 918         * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 919         * a little more because we may not trust delay accuracy.
 920         */
 921         max_retries = DP_BLANK_MAX_RETRY * 150;
 922
 923         /* disable DP stream */
 924         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 925
 926         /* the encoder stops sending the video stream
 927         * at the start of the vertical blanking.
 928         * Poll for DP_VID_STREAM_STATUS == 0
 929         */
 930
 931         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 932                         0,
 933                         10, max_retries);
 934
 935         ASSERT(retries <= max_retries);
 936
 937         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 938         * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 939         * complete, stream status will be stuck in video stream enabled state,
 940         * i.e. DP_VID_STREAM_STATUS stuck at 1.
 941         */
 942
 943         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 944 }
 945
 946 /* output video stream to link encoder */
 947 static void dce110_stream_encoder_dp_unblank(
 948         struct stream_encoder *enc,
 949         const struct encoder_unblank_param *param)
 950 {
 951         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 952
 953         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 954                 uint32_t n_vid = 0x8000;
 955                 uint32_t m_vid;
 956
 957                 /* M / N = Fstream / Flink
 958                 * m_vid / n_vid = pixel rate / link rate
 959                 */
 960
 961                 uint64_t m_vid_l = n_vid;
 962
 963                 m_vid_l *= param->pixel_clk_khz;
 964                 m_vid_l = div_u64(m_vid_l,
 965                         param->link_settings.link_rate
 966                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 967
 968                 m_vid = (uint32_t) m_vid_l;
 969
 970                 /* enable auto measurement */
 971
 972                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 973
 974                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 975                  * therefore program initial value for Mvid and Nvid
 976                  */
 977
 978                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
 979
 980                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 981
 982                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
 983         }
 984
 985         /* set DIG_START to 0x1 to resync FIFO */
 986
 987         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
 988
 989         /* switch DP encoder to CRTC data */
 990
 991         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 992
 993         /* wait 100us for DIG/DP logic to prime
 994         * (i.e. a few video lines)
 995         */
 996         udelay(100);
 997
 998         /* the hardware would start sending video at the start of the next DP
 999         * frame (i.e. rising edge of the vblank).
1000         * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1001         * register has no effect on enable transition! HW always guarantees
1002         * VID_STREAM enable at start of next frame, and this is not
1003         * programmable
1004         */
1005
1006         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1007 }
1008
1009 static void dce110_stream_encoder_set_avmute(
1010         struct stream_encoder *enc,
1011         bool enable)
1012 {
1013         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1014         unsigned int value = enable ? 1 : 0;
1015
1016         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1017 }
1018
1019
1020 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1021 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1022
1023 #include "include/audio_types.h"
1024
1025 /**
1026 * speakersToChannels
1027 *
1028 * @brief
1029 *  translate speakers to channels
1030 *
1031 *  FL  - Front Left
1032 *  FR  - Front Right
1033 *  RL  - Rear Left
1034 *  RR  - Rear Right
1035 *  RC  - Rear Center
1036 *  FC  - Front Center
1037 *  FLC - Front Left Center
1038 *  FRC - Front Right Center
1039 *  RLC - Rear Left Center
1040 *  RRC - Rear Right Center
1041 *  LFE - Low Freq Effect
1042 *
1043 *               FC
1044 *          FLC      FRC
1045 *    FL                    FR
1046 *
1047 *                    LFE
1048 *              ()
1049 *
1050 *
1051 *    RL                    RR
1052 *          RLC      RRC
1053 *               RC
1054 *
1055 *             ch  8   7   6   5   4   3   2   1
1056 * 0b00000011      -   -   -   -   -   -   FR  FL
1057 * 0b00000111      -   -   -   -   -   LFE FR  FL
1058 * 0b00001011      -   -   -   -   FC  -   FR  FL
1059 * 0b00001111      -   -   -   -   FC  LFE FR  FL
1060 * 0b00010011      -   -   -   RC  -   -   FR  FL
1061 * 0b00010111      -   -   -   RC  -   LFE FR  FL
1062 * 0b00011011      -   -   -   RC  FC  -   FR  FL
1063 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
1064 * 0b00110011      -   -   RR  RL  -   -   FR  FL
1065 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
1066 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
1067 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
1068 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
1069 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
1070 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
1071 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
1072 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
1073 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
1074 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
1075 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
1076 * 0b11000011      FRC FLC -   -   -   -   FR  FL
1077 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
1078 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
1079 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
1080 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
1081 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
1082 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
1083 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
1084 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
1085 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
1086 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
1087 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
1088 *
1089 * @param
1090 *  speakers - speaker information as it comes from CEA audio block
1091 */
1092 /* translate speakers to channels */
1093
1094 union audio_cea_channels {
1095         uint8_t all;
1096         struct audio_cea_channels_bits {
1097                 uint32_t FL:1;
1098                 uint32_t FR:1;
1099                 uint32_t LFE:1;
1100                 uint32_t FC:1;
1101                 uint32_t RL_RC:1;
1102                 uint32_t RR:1;
1103                 uint32_t RC_RLC_FLC:1;
1104                 uint32_t RRC_FRC:1;
1105         } channels;
1106 };
1107
1108 struct audio_clock_info {
1109         /* pixel clock frequency*/
1110         uint32_t pixel_clock_in_10khz;
1111         /* N - 32KHz audio */
1112         uint32_t n_32khz;
1113         /* CTS - 32KHz audio*/
1114         uint32_t cts_32khz;
1115         uint32_t n_44khz;
1116         uint32_t cts_44khz;
1117         uint32_t n_48khz;
1118         uint32_t cts_48khz;
1119 };
1120
1121 /* 25.2MHz/1.001*/
1122 /* 25.2MHz/1.001*/
1123 /* 25.2MHz*/
1124 /* 27MHz */
1125 /* 27MHz*1.001*/
1126 /* 27MHz*1.001*/
1127 /* 54MHz*/
1128 /* 54MHz*1.001*/
1129 /* 74.25MHz/1.001*/
1130 /* 74.25MHz*/
1131 /* 148.5MHz/1.001*/
1132 /* 148.5MHz*/
1133
1134 static const struct audio_clock_info audio_clock_info_table[16] = {
1135         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1136         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1137         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1138         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1139         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1140         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1141         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1142         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1143         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1144         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1145         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1146         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1147         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1148         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1149         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1150         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1151 };
1152
1153 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1154         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1155         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1156         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1157         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1158         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1159         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1160         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1161         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1162         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1163         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1164         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1165         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1166         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1167         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1168 };
1169
1170 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1171         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1172         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1173         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1174         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1175         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1176         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1177         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1178         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1179         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1180         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1181         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1182         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1183         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1184         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1185
1186
1187 };
1188
1189 static union audio_cea_channels speakers_to_channels(
1190         struct audio_speaker_flags speaker_flags)
1191 {
1192         union audio_cea_channels cea_channels = {0};
1193
1194         /* these are one to one */
1195         cea_channels.channels.FL = speaker_flags.FL_FR;
1196         cea_channels.channels.FR = speaker_flags.FL_FR;
1197         cea_channels.channels.LFE = speaker_flags.LFE;
1198         cea_channels.channels.FC = speaker_flags.FC;
1199
1200         /* if Rear Left and Right exist move RC speaker to channel 7
1201          * otherwise to channel 5
1202          */
1203         if (speaker_flags.RL_RR) {
1204                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1205                 cea_channels.channels.RR = speaker_flags.RL_RR;
1206                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1207         } else {
1208                 cea_channels.channels.RL_RC = speaker_flags.RC;
1209         }
1210
1211         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1212         if (speaker_flags.FLC_FRC) {
1213                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1214                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1215         } else {
1216                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1217                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1218         }
1219
1220         return cea_channels;
1221 }
1222
1223 static uint32_t calc_max_audio_packets_per_line(
1224         const struct audio_crtc_info *crtc_info)
1225 {
1226         uint32_t max_packets_per_line;
1227
1228         max_packets_per_line =
1229                 crtc_info->h_total - crtc_info->h_active;
1230
1231         if (crtc_info->pixel_repetition)
1232                 max_packets_per_line *= crtc_info->pixel_repetition;
1233
1234         /* for other hdmi features */
1235         max_packets_per_line -= 58;
1236         /* for Control Period */
1237         max_packets_per_line -= 16;
1238         /* Number of Audio Packets per Line */
1239         max_packets_per_line /= 32;
1240
1241         return max_packets_per_line;
1242 }
1243
1244 static void get_audio_clock_info(
1245         enum dc_color_depth color_depth,
1246         uint32_t crtc_pixel_clock_in_khz,
1247         uint32_t actual_pixel_clock_in_khz,
1248         struct audio_clock_info *audio_clock_info)
1249 {
1250         const struct audio_clock_info *clock_info;
1251         uint32_t index;
1252         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1253         uint32_t audio_array_size;
1254
1255         switch (color_depth) {
1256         case COLOR_DEPTH_161616:
1257                 clock_info = audio_clock_info_table_48bpc;
1258                 audio_array_size = ARRAY_SIZE(
1259                                 audio_clock_info_table_48bpc);
1260                 break;
1261         case COLOR_DEPTH_121212:
1262                 clock_info = audio_clock_info_table_36bpc;
1263                 audio_array_size = ARRAY_SIZE(
1264                                 audio_clock_info_table_36bpc);
1265                 break;
1266         default:
1267                 clock_info = audio_clock_info_table;
1268                 audio_array_size = ARRAY_SIZE(
1269                                 audio_clock_info_table);
1270                 break;
1271         }
1272
1273         if (clock_info != NULL) {
1274                 /* search for exact pixel clock in table */
1275                 for (index = 0; index < audio_array_size; index++) {
1276                         if (clock_info[index].pixel_clock_in_10khz >
1277                                 crtc_pixel_clock_in_10khz)
1278                                 break;  /* not match */
1279                         else if (clock_info[index].pixel_clock_in_10khz ==
1280                                         crtc_pixel_clock_in_10khz) {
1281                                 /* match found */
1282                                 *audio_clock_info = clock_info[index];
1283                                 return;
1284                         }
1285                 }
1286         }
1287
1288         /* not found */
1289         if (actual_pixel_clock_in_khz == 0)
1290                 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1291
1292         /* See HDMI spec  the table entry under
1293          *  pixel clock of "Other". */
1294         audio_clock_info->pixel_clock_in_10khz =
1295                         actual_pixel_clock_in_khz / 10;
1296         audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1297         audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1298         audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1299
1300         audio_clock_info->n_32khz = 4096;
1301         audio_clock_info->n_44khz = 6272;
1302         audio_clock_info->n_48khz = 6144;
1303 }
1304
1305 static void dce110_se_audio_setup(
1306         struct stream_encoder *enc,
1307         unsigned int az_inst,
1308         struct audio_info *audio_info)
1309 {
1310         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1311
1312         uint32_t speakers = 0;
1313         uint32_t channels = 0;
1314
1315         ASSERT(audio_info);
1316         if (audio_info == NULL)
1317                 /* This should not happen.it does so we don't get BSOD*/
1318                 return;
1319
1320         speakers = audio_info->flags.info.ALLSPEAKERS;
1321         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1322
1323         /* setup the audio stream source select (audio -> dig mapping) */
1324         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1325
1326         /* Channel allocation */
1327         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1328 }
1329
1330 static void dce110_se_setup_hdmi_audio(
1331         struct stream_encoder *enc,
1332         const struct audio_crtc_info *crtc_info)
1333 {
1334         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1335
1336         struct audio_clock_info audio_clock_info = {0};
1337         uint32_t max_packets_per_line;
1338
1339         /* For now still do calculation, although this field is ignored when
1340         above HDMI_PACKET_GEN_VERSION set to 1 */
1341         max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1342
1343         /* HDMI_AUDIO_PACKET_CONTROL */
1344         REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1345                         HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1346                         HDMI_AUDIO_DELAY_EN, 1);
1347
1348         /* AFMT_AUDIO_PACKET_CONTROL */
1349         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1350
1351         /* AFMT_AUDIO_PACKET_CONTROL2 */
1352         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1353                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1354                         AFMT_60958_OSF_OVRD, 0);
1355
1356         /* HDMI_ACR_PACKET_CONTROL */
1357         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1358                         HDMI_ACR_AUTO_SEND, 1,
1359                         HDMI_ACR_SOURCE, 0,
1360                         HDMI_ACR_AUDIO_PRIORITY, 0);
1361
1362         /* Program audio clock sample/regeneration parameters */
1363         get_audio_clock_info(crtc_info->color_depth,
1364                              crtc_info->requested_pixel_clock,
1365                              crtc_info->calculated_pixel_clock,
1366                              &audio_clock_info);
1367         dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
1368                         "\n%s:Input::requested_pixel_clock = %d"        \
1369                         "calculated_pixel_clock = %d \n", __func__,     \
1370                         crtc_info->requested_pixel_clock,               \
1371                         crtc_info->calculated_pixel_clock);
1372
1373         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1374         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1375
1376         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1377         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1378
1379         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1380         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1381
1382         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1383         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1384
1385         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1386         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1387
1388         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1389         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1390
1391         /* Video driver cannot know in advance which sample rate will
1392            be used by HD Audio driver
1393            HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1394            programmed below in interruppt callback */
1395
1396         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1397         AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1398         REG_UPDATE_2(AFMT_60958_0,
1399                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1400                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1401
1402         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1403         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1404
1405         /*AFMT_60958_2 now keep this settings until
1406          *  Programming guide comes out*/
1407         REG_UPDATE_6(AFMT_60958_2,
1408                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1409                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1410                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1411                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1412                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1413                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1414 }
1415
1416 static void dce110_se_setup_dp_audio(
1417         struct stream_encoder *enc)
1418 {
1419         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1420
1421         /* --- DP Audio packet configurations --- */
1422
1423         /* ATP Configuration */
1424         REG_SET(DP_SEC_AUD_N, 0,
1425                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1426
1427         /* Async/auto-calc timestamp mode */
1428         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1429                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1430
1431         /* --- The following are the registers
1432          *  copied from the SetupHDMI --- */
1433
1434         /* AFMT_AUDIO_PACKET_CONTROL */
1435         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1436
1437         /* AFMT_AUDIO_PACKET_CONTROL2 */
1438         /* Program the ATP and AIP next */
1439         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1440                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1441                         AFMT_60958_OSF_OVRD, 0);
1442
1443         /* AFMT_INFOFRAME_CONTROL0 */
1444         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1445
1446         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1447         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1448 }
1449
1450 static void dce110_se_enable_audio_clock(
1451         struct stream_encoder *enc,
1452         bool enable)
1453 {
1454         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1455
1456         if (REG(AFMT_CNTL) == 0)
1457                 return;   /* DCE8/10 does not have this register */
1458
1459         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1460
1461         /* wait for AFMT clock to turn on,
1462          * expectation: this should complete in 1-2 reads
1463          *
1464          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1465          *
1466          * TODO: wait for clock_on does not work well. May need HW
1467          * program sequence. But audio seems work normally even without wait
1468          * for clock_on status change
1469          */
1470 }
1471
1472 static void dce110_se_enable_dp_audio(
1473         struct stream_encoder *enc)
1474 {
1475         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1476
1477         /* Enable Audio packets */
1478         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1479
1480         /* Program the ATP and AIP next */
1481         REG_UPDATE_2(DP_SEC_CNTL,
1482                         DP_SEC_ATP_ENABLE, 1,
1483                         DP_SEC_AIP_ENABLE, 1);
1484
1485         /* Program STREAM_ENABLE after all the other enables. */
1486         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1487 }
1488
1489 static void dce110_se_disable_dp_audio(
1490         struct stream_encoder *enc)
1491 {
1492         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1493         uint32_t value = REG_READ(DP_SEC_CNTL);
1494
1495         /* Disable Audio packets */
1496         REG_UPDATE_5(DP_SEC_CNTL,
1497                         DP_SEC_ASP_ENABLE, 0,
1498                         DP_SEC_ATP_ENABLE, 0,
1499                         DP_SEC_AIP_ENABLE, 0,
1500                         DP_SEC_ACM_ENABLE, 0,
1501                         DP_SEC_STREAM_ENABLE, 0);
1502
1503         /* This register shared with encoder info frame. Therefore we need to
1504         keep master enabled if at least on of the fields is not 0 */
1505         if (value != 0)
1506                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1507
1508 }
1509
1510 void dce110_se_audio_mute_control(
1511         struct stream_encoder *enc,
1512         bool mute)
1513 {
1514         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1515
1516         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1517 }
1518
1519 void dce110_se_dp_audio_setup(
1520         struct stream_encoder *enc,
1521         unsigned int az_inst,
1522         struct audio_info *info)
1523 {
1524         dce110_se_audio_setup(enc, az_inst, info);
1525 }
1526
1527 void dce110_se_dp_audio_enable(
1528         struct stream_encoder *enc)
1529 {
1530         dce110_se_enable_audio_clock(enc, true);
1531         dce110_se_setup_dp_audio(enc);
1532         dce110_se_enable_dp_audio(enc);
1533 }
1534
1535 void dce110_se_dp_audio_disable(
1536         struct stream_encoder *enc)
1537 {
1538         dce110_se_disable_dp_audio(enc);
1539         dce110_se_enable_audio_clock(enc, false);
1540 }
1541
1542 void dce110_se_hdmi_audio_setup(
1543         struct stream_encoder *enc,
1544         unsigned int az_inst,
1545         struct audio_info *info,
1546         struct audio_crtc_info *audio_crtc_info)
1547 {
1548         dce110_se_enable_audio_clock(enc, true);
1549         dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1550         dce110_se_audio_setup(enc, az_inst, info);
1551 }
1552
1553 void dce110_se_hdmi_audio_disable(
1554         struct stream_encoder *enc)
1555 {
1556         dce110_se_enable_audio_clock(enc, false);
1557 }
1558
1559
1560 static void setup_stereo_sync(
1561         struct stream_encoder *enc,
1562         int tg_inst, bool enable)
1563 {
1564         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1565         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1566         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1567 }
1568
1569
1570 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1571         .dp_set_stream_attribute =
1572                 dce110_stream_encoder_dp_set_stream_attribute,
1573         .hdmi_set_stream_attribute =
1574                 dce110_stream_encoder_hdmi_set_stream_attribute,
1575         .dvi_set_stream_attribute =
1576                 dce110_stream_encoder_dvi_set_stream_attribute,
1577         .set_mst_bandwidth =
1578                 dce110_stream_encoder_set_mst_bandwidth,
1579         .update_hdmi_info_packets =
1580                 dce110_stream_encoder_update_hdmi_info_packets,
1581         .stop_hdmi_info_packets =
1582                 dce110_stream_encoder_stop_hdmi_info_packets,
1583         .update_dp_info_packets =
1584                 dce110_stream_encoder_update_dp_info_packets,
1585         .stop_dp_info_packets =
1586                 dce110_stream_encoder_stop_dp_info_packets,
1587         .dp_blank =
1588                 dce110_stream_encoder_dp_blank,
1589         .dp_unblank =
1590                 dce110_stream_encoder_dp_unblank,
1591         .audio_mute_control = dce110_se_audio_mute_control,
1592
1593         .dp_audio_setup = dce110_se_dp_audio_setup,
1594         .dp_audio_enable = dce110_se_dp_audio_enable,
1595         .dp_audio_disable = dce110_se_dp_audio_disable,
1596
1597         .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1598         .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1599         .setup_stereo_sync  = setup_stereo_sync,
1600         .set_avmute = dce110_stream_encoder_set_avmute,
1601
1602 };
1603
1604 void dce110_stream_encoder_construct(
1605         struct dce110_stream_encoder *enc110,
1606         struct dc_context *ctx,
1607         struct dc_bios *bp,
1608         enum engine_id eng_id,
1609         const struct dce110_stream_enc_registers *regs,
1610         const struct dce_stream_encoder_shift *se_shift,
1611         const struct dce_stream_encoder_mask *se_mask)
1612 {
1613         enc110->base.funcs = &dce110_str_enc_funcs;
1614         enc110->base.ctx = ctx;
1615         enc110->base.id = eng_id;
1616         enc110->base.bp = bp;
1617         enc110->regs = regs;
1618         enc110->se_shift = se_shift;
1619         enc110->se_mask = se_mask;
1620 }