drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6
   7 #include "inc/core_types.h"
   8 #include "link_hwss.h"
   9 #include "dc_link_ddc.h"
  10 #include "core_status.h"
  11 #include "dpcd_defs.h"
  12
  13 #include "resource.h"
  14 #define DC_LOGGER \
  15         link->ctx->logger
  16
  17 /* maximum pre emphasis level allowed for each voltage swing level*/
  18 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
  19                 PRE_EMPHASIS_LEVEL3,
  20                 PRE_EMPHASIS_LEVEL2,
  21                 PRE_EMPHASIS_LEVEL1,
  22                 PRE_EMPHASIS_DISABLED };
  23
  24 enum {
  25         POST_LT_ADJ_REQ_LIMIT = 6,
  26         POST_LT_ADJ_REQ_TIMEOUT = 200
  27 };
  28
  29 enum {
  30         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  31         /* to avoid infinite loop where-in the receiver
  32          * switches between different VS
  33          */
  34         LINK_TRAINING_MAX_CR_RETRY = 100
  35 };
  36
  37 static bool decide_fallback_link_setting(
  38                 struct dc_link_settings initial_link_settings,
  39                 struct dc_link_settings *current_link_setting,
  40                 enum link_training_result training_result);
  41 static struct dc_link_settings get_common_supported_link_settings (
  42                 struct dc_link_settings link_setting_a,
  43                 struct dc_link_settings link_setting_b);
  44
  45 static void wait_for_training_aux_rd_interval(
  46         struct dc_link *link,
  47         uint32_t default_wait_in_micro_secs)
  48 {
  49         union training_aux_rd_interval training_rd_interval;
  50
  51         /* overwrite the delay if rev > 1.1*/
  52         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  53                 /* DP 1.2 or later - retrieve delay through
  54                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  55                 core_link_read_dpcd(
  56                         link,
  57                         DP_TRAINING_AUX_RD_INTERVAL,
  58                         (uint8_t *)&training_rd_interval,
  59                         sizeof(training_rd_interval));
  60
  61                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  62                         default_wait_in_micro_secs =
  63                                 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  64         }
  65
  66         udelay(default_wait_in_micro_secs);
  67
  68         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  69                 __func__,
  70                 default_wait_in_micro_secs);
  71 }
  72
  73 static void dpcd_set_training_pattern(
  74         struct dc_link *link,
  75         union dpcd_training_pattern dpcd_pattern)
  76 {
  77         core_link_write_dpcd(
  78                 link,
  79                 DP_TRAINING_PATTERN_SET,
  80                 &dpcd_pattern.raw,
  81                 1);
  82
  83         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
  84                 __func__,
  85                 DP_TRAINING_PATTERN_SET,
  86                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
  87 }
  88
  89 static void dpcd_set_link_settings(
  90         struct dc_link *link,
  91         const struct link_training_settings *lt_settings)
  92 {
  93         uint8_t rate = (uint8_t)
  94         (lt_settings->link_settings.link_rate);
  95
  96         union down_spread_ctrl downspread = {{0}};
  97         union lane_count_set lane_count_set = {{0}};
  98         uint8_t link_set_buffer[2];
  99
 100         downspread.raw = (uint8_t)
 101         (lt_settings->link_settings.link_spread);
 102
 103         lane_count_set.bits.LANE_COUNT_SET =
 104         lt_settings->link_settings.lane_count;
 105
 106         lane_count_set.bits.ENHANCED_FRAMING = 1;
 107
 108         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 109                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 110
 111         link_set_buffer[0] = rate;
 112         link_set_buffer[1] = lane_count_set.raw;
 113
 114         core_link_write_dpcd(link, DP_LINK_BW_SET,
 115         link_set_buffer, 2);
 116         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 117         &downspread.raw, sizeof(downspread));
 118
 119         DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
 120                 __func__,
 121                 DP_LINK_BW_SET,
 122                 lt_settings->link_settings.link_rate,
 123                 DP_LANE_COUNT_SET,
 124                 lt_settings->link_settings.lane_count,
 125                 DP_DOWNSPREAD_CTRL,
 126                 lt_settings->link_settings.link_spread);
 127
 128 }
 129
 130 static enum dpcd_training_patterns
 131         hw_training_pattern_to_dpcd_training_pattern(
 132         struct dc_link *link,
 133         enum hw_dp_training_pattern pattern)
 134 {
 135         enum dpcd_training_patterns dpcd_tr_pattern =
 136         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 137
 138         switch (pattern) {
 139         case HW_DP_TRAINING_PATTERN_1:
 140                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 141                 break;
 142         case HW_DP_TRAINING_PATTERN_2:
 143                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 144                 break;
 145         case HW_DP_TRAINING_PATTERN_3:
 146                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 147                 break;
 148         case HW_DP_TRAINING_PATTERN_4:
 149                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 150                 break;
 151         default:
 152                 ASSERT(0);
 153                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 154                         __func__, pattern);
 155                 break;
 156         }
 157
 158         return dpcd_tr_pattern;
 159
 160 }
 161
 162 static void dpcd_set_lt_pattern_and_lane_settings(
 163         struct dc_link *link,
 164         const struct link_training_settings *lt_settings,
 165         enum hw_dp_training_pattern pattern)
 166 {
 167         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 168         const uint32_t dpcd_base_lt_offset =
 169         DP_TRAINING_PATTERN_SET;
 170         uint8_t dpcd_lt_buffer[5] = {0};
 171         union dpcd_training_pattern dpcd_pattern = {{0}};
 172         uint32_t lane;
 173         uint32_t size_in_bytes;
 174         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 175
 176         /*****************************************************************
 177         * DpcdAddress_TrainingPatternSet
 178         *****************************************************************/
 179         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 180                 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
 181
 182         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
 183                 = dpcd_pattern.raw;
 184
 185         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 186                 __func__,
 187                 DP_TRAINING_PATTERN_SET,
 188                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 189
 190         /*****************************************************************
 191         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 192         *****************************************************************/
 193         for (lane = 0; lane <
 194                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 195
 196                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 197                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 198                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 199                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 200
 201                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 202                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 203                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 204                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 205                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 206                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 207         }
 208
 209         /* concatinate everything into one buffer*/
 210
 211         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 212
 213          // 0x00103 - 0x00102
 214         memmove(
 215                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
 216                 dpcd_lane,
 217                 size_in_bytes);
 218
 219         DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 220                 __func__,
 221                 DP_TRAINING_LANE0_SET,
 222                 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 223                 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 224                 dpcd_lane[0].bits.MAX_SWING_REACHED,
 225                 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 226
 227         if (edp_workaround) {
 228                 /* for eDP write in 2 parts because the 5-byte burst is
 229                 * causing issues on some eDP panels (EPR#366724)
 230                 */
 231                 core_link_write_dpcd(
 232                         link,
 233                         DP_TRAINING_PATTERN_SET,
 234                         &dpcd_pattern.raw,
 235                         sizeof(dpcd_pattern.raw) );
 236
 237                 core_link_write_dpcd(
 238                         link,
 239                         DP_TRAINING_LANE0_SET,
 240                         (uint8_t *)(dpcd_lane),
 241                         size_in_bytes);
 242
 243                 } else
 244                 /* write it all in (1 + number-of-lanes)-byte burst*/
 245                         core_link_write_dpcd(
 246                                 link,
 247                                 dpcd_base_lt_offset,
 248                                 dpcd_lt_buffer,
 249                                 size_in_bytes + sizeof(dpcd_pattern.raw) );
 250
 251         link->cur_lane_setting = lt_settings->lane_settings[0];
 252 }
 253
 254 static bool is_cr_done(enum dc_lane_count ln_count,
 255         union lane_status *dpcd_lane_status)
 256 {
 257         bool done = true;
 258         uint32_t lane;
 259         /*LANEx_CR_DONE bits All 1's?*/
 260         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 261                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 262                         done = false;
 263         }
 264         return done;
 265
 266 }
 267
 268 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 269         union lane_status *dpcd_lane_status,
 270         union lane_align_status_updated *lane_status_updated)
 271 {
 272         bool done = true;
 273         uint32_t lane;
 274         if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
 275                 done = false;
 276         else {
 277                 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 278                         if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
 279                                 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 280                                 done = false;
 281                 }
 282         }
 283         return done;
 284
 285 }
 286
 287 static void update_drive_settings(
 288                 struct link_training_settings *dest,
 289                 struct link_training_settings src)
 290 {
 291         uint32_t lane;
 292         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 293                 dest->lane_settings[lane].VOLTAGE_SWING =
 294                         src.lane_settings[lane].VOLTAGE_SWING;
 295                 dest->lane_settings[lane].PRE_EMPHASIS =
 296                         src.lane_settings[lane].PRE_EMPHASIS;
 297                 dest->lane_settings[lane].POST_CURSOR2 =
 298                         src.lane_settings[lane].POST_CURSOR2;
 299         }
 300 }
 301
 302 static uint8_t get_nibble_at_index(const uint8_t *buf,
 303         uint32_t index)
 304 {
 305         uint8_t nibble;
 306         nibble = buf[index / 2];
 307
 308         if (index % 2)
 309                 nibble >>= 4;
 310         else
 311                 nibble &= 0x0F;
 312
 313         return nibble;
 314 }
 315
 316 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 317         enum dc_voltage_swing voltage)
 318 {
 319         enum dc_pre_emphasis pre_emphasis;
 320         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 321
 322         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 323                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 324
 325         return pre_emphasis;
 326
 327 }
 328
 329 static void find_max_drive_settings(
 330         const struct link_training_settings *link_training_setting,
 331         struct link_training_settings *max_lt_setting)
 332 {
 333         uint32_t lane;
 334         struct dc_lane_settings max_requested;
 335
 336         max_requested.VOLTAGE_SWING =
 337                 link_training_setting->
 338                 lane_settings[0].VOLTAGE_SWING;
 339         max_requested.PRE_EMPHASIS =
 340                 link_training_setting->
 341                 lane_settings[0].PRE_EMPHASIS;
 342         /*max_requested.postCursor2 =
 343          * link_training_setting->laneSettings[0].postCursor2;*/
 344
 345         /* Determine what the maximum of the requested settings are*/
 346         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 347                         lane++) {
 348                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 349                         max_requested.VOLTAGE_SWING)
 350
 351                         max_requested.VOLTAGE_SWING =
 352                         link_training_setting->
 353                         lane_settings[lane].VOLTAGE_SWING;
 354
 355                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 356                                 max_requested.PRE_EMPHASIS)
 357                         max_requested.PRE_EMPHASIS =
 358                         link_training_setting->
 359                         lane_settings[lane].PRE_EMPHASIS;
 360
 361                 /*
 362                 if (link_training_setting->laneSettings[lane].postCursor2 >
 363                  max_requested.postCursor2)
 364                 {
 365                 max_requested.postCursor2 =
 366                 link_training_setting->laneSettings[lane].postCursor2;
 367                 }
 368                 */
 369         }
 370
 371         /* make sure the requested settings are
 372          * not higher than maximum settings*/
 373         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 374                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 375
 376         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 377                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 378         /*
 379         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 380         max_requested.postCursor2 = PostCursor2_MaxLevel;
 381         */
 382
 383         /* make sure the pre-emphasis matches the voltage swing*/
 384         if (max_requested.PRE_EMPHASIS >
 385                 get_max_pre_emphasis_for_voltage_swing(
 386                         max_requested.VOLTAGE_SWING))
 387                 max_requested.PRE_EMPHASIS =
 388                 get_max_pre_emphasis_for_voltage_swing(
 389                         max_requested.VOLTAGE_SWING);
 390
 391         /*
 392          * Post Cursor2 levels are completely independent from
 393          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 394          * can only be applied to each allowable combination of voltage
 395          * swing and pre-emphasis levels */
 396          /* if ( max_requested.postCursor2 >
 397           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 398           *  max_requested.postCursor2 =
 399           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 400           */
 401
 402         max_lt_setting->link_settings.link_rate =
 403                 link_training_setting->link_settings.link_rate;
 404         max_lt_setting->link_settings.lane_count =
 405         link_training_setting->link_settings.lane_count;
 406         max_lt_setting->link_settings.link_spread =
 407                 link_training_setting->link_settings.link_spread;
 408
 409         for (lane = 0; lane <
 410                 link_training_setting->link_settings.lane_count;
 411                 lane++) {
 412                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 413                         max_requested.VOLTAGE_SWING;
 414                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 415                         max_requested.PRE_EMPHASIS;
 416                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 417                  * max_requested.postCursor2;
 418                  */
 419         }
 420
 421 }
 422
 423 static void get_lane_status_and_drive_settings(
 424         struct dc_link *link,
 425         const struct link_training_settings *link_training_setting,
 426         union lane_status *ln_status,
 427         union lane_align_status_updated *ln_status_updated,
 428         struct link_training_settings *req_settings)
 429 {
 430         uint8_t dpcd_buf[6] = {0};
 431         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
 432         struct link_training_settings request_settings = {{0}};
 433         uint32_t lane;
 434
 435         memset(req_settings, '\0', sizeof(struct link_training_settings));
 436
 437         core_link_read_dpcd(
 438                 link,
 439                 DP_LANE0_1_STATUS,
 440                 (uint8_t *)(dpcd_buf),
 441                 sizeof(dpcd_buf));
 442
 443         for (lane = 0; lane <
 444                 (uint32_t)(link_training_setting->link_settings.lane_count);
 445                 lane++) {
 446
 447                 ln_status[lane].raw =
 448                         get_nibble_at_index(&dpcd_buf[0], lane);
 449                 dpcd_lane_adjust[lane].raw =
 450                         get_nibble_at_index(&dpcd_buf[4], lane);
 451         }
 452
 453         ln_status_updated->raw = dpcd_buf[2];
 454
 455         DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
 456                 __func__,
 457                 DP_LANE0_1_STATUS, dpcd_buf[0],
 458                 DP_LANE2_3_STATUS, dpcd_buf[1]);
 459
 460         DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
 461                 __func__,
 462                 DP_ADJUST_REQUEST_LANE0_1,
 463                 dpcd_buf[4],
 464                 DP_ADJUST_REQUEST_LANE2_3,
 465                 dpcd_buf[5]);
 466
 467         /*copy to req_settings*/
 468         request_settings.link_settings.lane_count =
 469                 link_training_setting->link_settings.lane_count;
 470         request_settings.link_settings.link_rate =
 471                 link_training_setting->link_settings.link_rate;
 472         request_settings.link_settings.link_spread =
 473                 link_training_setting->link_settings.link_spread;
 474
 475         for (lane = 0; lane <
 476                 (uint32_t)(link_training_setting->link_settings.lane_count);
 477                 lane++) {
 478
 479                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 480                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 481                                 VOLTAGE_SWING_LANE);
 482                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 483                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 484                                 PRE_EMPHASIS_LANE);
 485         }
 486
 487         /*Note: for postcursor2, read adjusted
 488          * postcursor2 settings from*/
 489         /*DpcdAddress_AdjustRequestPostCursor2 =
 490          *0x020C (not implemented yet)*/
 491
 492         /* we find the maximum of the requested settings across all lanes*/
 493         /* and set this maximum for all lanes*/
 494         find_max_drive_settings(&request_settings, req_settings);
 495
 496         /* if post cursor 2 is needed in the future,
 497          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 498          */
 499
 500 }
 501
 502 static void dpcd_set_lane_settings(
 503         struct dc_link *link,
 504         const struct link_training_settings *link_training_setting)
 505 {
 506         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 507         uint32_t lane;
 508
 509         for (lane = 0; lane <
 510                 (uint32_t)(link_training_setting->
 511                 link_settings.lane_count);
 512                 lane++) {
 513                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 514                         (uint8_t)(link_training_setting->
 515                         lane_settings[lane].VOLTAGE_SWING);
 516                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 517                         (uint8_t)(link_training_setting->
 518                         lane_settings[lane].PRE_EMPHASIS);
 519                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 520                         (link_training_setting->
 521                         lane_settings[lane].VOLTAGE_SWING ==
 522                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 523                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 524                         (link_training_setting->
 525                         lane_settings[lane].PRE_EMPHASIS ==
 526                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 527         }
 528
 529         core_link_write_dpcd(link,
 530                 DP_TRAINING_LANE0_SET,
 531                 (uint8_t *)(dpcd_lane),
 532                 link_training_setting->link_settings.lane_count);
 533
 534         /*
 535         if (LTSettings.link.rate == LinkRate_High2)
 536         {
 537                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 538                 for ( uint32_t lane = 0;
 539                 lane < lane_count_DPMax; lane++)
 540                 {
 541                         dpcd_lane2[lane].bits.post_cursor2_set =
 542                         static_cast<unsigned char>(
 543                         LTSettings.laneSettings[lane].postCursor2);
 544                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 545                 }
 546                 m_pDpcdAccessSrv->WriteDpcdData(
 547                 DpcdAddress_Lane0Set2,
 548                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 549                 LTSettings.link.lanes);
 550         }
 551         */
 552
 553         DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 554                 __func__,
 555                 DP_TRAINING_LANE0_SET,
 556                 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 557                 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 558                 dpcd_lane[0].bits.MAX_SWING_REACHED,
 559                 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 560
 561         link->cur_lane_setting = link_training_setting->lane_settings[0];
 562
 563 }
 564
 565 static bool is_max_vs_reached(
 566         const struct link_training_settings *lt_settings)
 567 {
 568         uint32_t lane;
 569         for (lane = 0; lane <
 570                 (uint32_t)(lt_settings->link_settings.lane_count);
 571                 lane++) {
 572                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 573                         == VOLTAGE_SWING_MAX_LEVEL)
 574                         return true;
 575         }
 576         return false;
 577
 578 }
 579
 580 void dc_link_dp_set_drive_settings(
 581         struct dc_link *link,
 582         struct link_training_settings *lt_settings)
 583 {
 584         /* program ASIC PHY settings*/
 585         dp_set_hw_lane_settings(link, lt_settings);
 586
 587         /* Notify DP sink the PHY settings from source */
 588         dpcd_set_lane_settings(link, lt_settings);
 589 }
 590
 591 static bool perform_post_lt_adj_req_sequence(
 592         struct dc_link *link,
 593         struct link_training_settings *lt_settings)
 594 {
 595         enum dc_lane_count lane_count =
 596         lt_settings->link_settings.lane_count;
 597
 598         uint32_t adj_req_count;
 599         uint32_t adj_req_timer;
 600         bool req_drv_setting_changed;
 601         uint32_t lane;
 602
 603         req_drv_setting_changed = false;
 604         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 605         adj_req_count++) {
 606
 607                 req_drv_setting_changed = false;
 608
 609                 for (adj_req_timer = 0;
 610                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 611                         adj_req_timer++) {
 612
 613                         struct link_training_settings req_settings;
 614                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 615                         union lane_align_status_updated
 616                                 dpcd_lane_status_updated;
 617
 618                         get_lane_status_and_drive_settings(
 619                         link,
 620                         lt_settings,
 621                         dpcd_lane_status,
 622                         &dpcd_lane_status_updated,
 623                         &req_settings);
 624
 625                         if (dpcd_lane_status_updated.bits.
 626                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 627                                 return true;
 628
 629                         if (!is_cr_done(lane_count, dpcd_lane_status))
 630                                 return false;
 631
 632                         if (!is_ch_eq_done(
 633                                 lane_count,
 634                                 dpcd_lane_status,
 635                                 &dpcd_lane_status_updated))
 636                                 return false;
 637
 638                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 639
 640                                 if (lt_settings->
 641                                 lane_settings[lane].VOLTAGE_SWING !=
 642                                 req_settings.lane_settings[lane].
 643                                 VOLTAGE_SWING ||
 644                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 645                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 646
 647                                         req_drv_setting_changed = true;
 648                                         break;
 649                                 }
 650                         }
 651
 652                         if (req_drv_setting_changed) {
 653                                 update_drive_settings(
 654                                         lt_settings,req_settings);
 655
 656                                 dc_link_dp_set_drive_settings(link,
 657                                                 lt_settings);
 658                                 break;
 659                         }
 660
 661                         msleep(1);
 662                 }
 663
 664                 if (!req_drv_setting_changed) {
 665                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 666                                 __func__);
 667
 668                         ASSERT(0);
 669                         return true;
 670                 }
 671         }
 672         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 673                 __func__);
 674
 675         ASSERT(0);
 676         return true;
 677
 678 }
 679
 680 static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
 681 {
 682         enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
 683         struct encoder_feature_support *features = &link->link_enc->features;
 684         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 685
 686         if (features->flags.bits.IS_TPS3_CAPABLE)
 687                 highest_tp = HW_DP_TRAINING_PATTERN_3;
 688
 689         if (features->flags.bits.IS_TPS4_CAPABLE)
 690                 highest_tp = HW_DP_TRAINING_PATTERN_4;
 691
 692         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 693                 highest_tp >= HW_DP_TRAINING_PATTERN_4)
 694                 return HW_DP_TRAINING_PATTERN_4;
 695
 696         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 697                 highest_tp >= HW_DP_TRAINING_PATTERN_3)
 698                 return HW_DP_TRAINING_PATTERN_3;
 699
 700         return HW_DP_TRAINING_PATTERN_2;
 701 }
 702
 703 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 704                                         union lane_status *dpcd_lane_status)
 705 {
 706         enum link_training_result result = LINK_TRAINING_SUCCESS;
 707
 708         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 709                 result = LINK_TRAINING_CR_FAIL_LANE0;
 710         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 711                 result = LINK_TRAINING_CR_FAIL_LANE1;
 712         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 713                 result = LINK_TRAINING_CR_FAIL_LANE23;
 714         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 715                 result = LINK_TRAINING_CR_FAIL_LANE23;
 716         return result;
 717 }
 718
 719 static enum link_training_result perform_channel_equalization_sequence(
 720         struct dc_link *link,
 721         struct link_training_settings *lt_settings)
 722 {
 723         struct link_training_settings req_settings;
 724         enum hw_dp_training_pattern hw_tr_pattern;
 725         uint32_t retries_ch_eq;
 726         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 727         union lane_align_status_updated dpcd_lane_status_updated = {{0}};
 728         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};
 729
 730         hw_tr_pattern = get_supported_tp(link);
 731
 732         dp_set_hw_training_pattern(link, hw_tr_pattern);
 733
 734         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 735                 retries_ch_eq++) {
 736
 737                 dp_set_hw_lane_settings(link, lt_settings);
 738
 739                 /* 2. update DPCD*/
 740                 if (!retries_ch_eq)
 741                         /* EPR #361076 - write as a 5-byte burst,
 742                          * but only for the 1-st iteration*/
 743                         dpcd_set_lt_pattern_and_lane_settings(
 744                                 link,
 745                                 lt_settings,
 746                                 hw_tr_pattern);
 747                 else
 748                         dpcd_set_lane_settings(link, lt_settings);
 749
 750                 /* 3. wait for receiver to lock-on*/
 751                 wait_for_training_aux_rd_interval(link, 400);
 752
 753                 /* 4. Read lane status and requested
 754                  * drive settings as set by the sink*/
 755
 756                 get_lane_status_and_drive_settings(
 757                         link,
 758                         lt_settings,
 759                         dpcd_lane_status,
 760                         &dpcd_lane_status_updated,
 761                         &req_settings);
 762
 763                 /* 5. check CR done*/
 764                 if (!is_cr_done(lane_count, dpcd_lane_status))
 765                         return LINK_TRAINING_EQ_FAIL_CR;
 766
 767                 /* 6. check CHEQ done*/
 768                 if (is_ch_eq_done(lane_count,
 769                         dpcd_lane_status,
 770                         &dpcd_lane_status_updated))
 771                         return LINK_TRAINING_SUCCESS;
 772
 773                 /* 7. update VS/PE/PC2 in lt_settings*/
 774                 update_drive_settings(lt_settings, req_settings);
 775         }
 776
 777         return LINK_TRAINING_EQ_FAIL_EQ;
 778
 779 }
 780
 781 static enum link_training_result perform_clock_recovery_sequence(
 782         struct dc_link *link,
 783         struct link_training_settings *lt_settings)
 784 {
 785         uint32_t retries_cr;
 786         uint32_t retry_count;
 787         uint32_t lane;
 788         struct link_training_settings req_settings;
 789         enum dc_lane_count lane_count =
 790         lt_settings->link_settings.lane_count;
 791         enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
 792         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 793         union lane_align_status_updated dpcd_lane_status_updated;
 794
 795         retries_cr = 0;
 796         retry_count = 0;
 797         /* initial drive setting (VS/PE/PC2)*/
 798         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 799                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
 800                 VOLTAGE_SWING_LEVEL0;
 801                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
 802                 PRE_EMPHASIS_DISABLED;
 803                 lt_settings->lane_settings[lane].POST_CURSOR2 =
 804                 POST_CURSOR2_DISABLED;
 805         }
 806
 807         dp_set_hw_training_pattern(link, hw_tr_pattern);
 808
 809         /* najeeb - The synaptics MST hub can put the LT in
 810         * infinite loop by switching the VS
 811         */
 812         /* between level 0 and level 1 continuously, here
 813         * we try for CR lock for LinkTrainingMaxCRRetry count*/
 814         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
 815         (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
 816
 817                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
 818                 memset(&dpcd_lane_status_updated, '\0',
 819                 sizeof(dpcd_lane_status_updated));
 820
 821                 /* 1. call HWSS to set lane settings*/
 822                 dp_set_hw_lane_settings(
 823                                 link,
 824                                 lt_settings);
 825
 826                 /* 2. update DPCD of the receiver*/
 827                 if (!retries_cr)
 828                         /* EPR #361076 - write as a 5-byte burst,
 829                          * but only for the 1-st iteration.*/
 830                         dpcd_set_lt_pattern_and_lane_settings(
 831                                         link,
 832                                         lt_settings,
 833                                         hw_tr_pattern);
 834                 else
 835                         dpcd_set_lane_settings(
 836                                         link,
 837                                         lt_settings);
 838
 839                 /* 3. wait receiver to lock-on*/
 840                 wait_for_training_aux_rd_interval(
 841                                 link,
 842                                 100);
 843
 844                 /* 4. Read lane status and requested drive
 845                 * settings as set by the sink
 846                 */
 847                 get_lane_status_and_drive_settings(
 848                                 link,
 849                                 lt_settings,
 850                                 dpcd_lane_status,
 851                                 &dpcd_lane_status_updated,
 852                                 &req_settings);
 853
 854                 /* 5. check CR done*/
 855                 if (is_cr_done(lane_count, dpcd_lane_status))
 856                         return LINK_TRAINING_SUCCESS;
 857
 858                 /* 6. max VS reached*/
 859                 if (is_max_vs_reached(lt_settings))
 860                         break;
 861
 862                 /* 7. same voltage*/
 863                 /* Note: VS same for all lanes,
 864                 * so comparing first lane is sufficient*/
 865                 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
 866                         req_settings.lane_settings[0].VOLTAGE_SWING)
 867                         retries_cr++;
 868                 else
 869                         retries_cr = 0;
 870
 871                 /* 8. update VS/PE/PC2 in lt_settings*/
 872                 update_drive_settings(lt_settings, req_settings);
 873
 874                 retry_count++;
 875         }
 876
 877         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
 878                 ASSERT(0);
 879                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
 880                         __func__,
 881                         LINK_TRAINING_MAX_CR_RETRY);
 882
 883         }
 884
 885         return get_cr_failure(lane_count, dpcd_lane_status);
 886 }
 887
 888 static inline enum link_training_result perform_link_training_int(
 889         struct dc_link *link,
 890         struct link_training_settings *lt_settings,
 891         enum link_training_result status)
 892 {
 893         union lane_count_set lane_count_set = { {0} };
 894         union dpcd_training_pattern dpcd_pattern = { {0} };
 895
 896         /* 3. set training not in progress*/
 897         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 898         dpcd_set_training_pattern(link, dpcd_pattern);
 899
 900         /* 4. mainlink output idle pattern*/
 901         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 902
 903         /*
 904          * 5. post training adjust if required
 905          * If the upstream DPTX and downstream DPRX both support TPS4,
 906          * TPS4 must be used instead of POST_LT_ADJ_REQ.
 907          */
 908         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
 909                         get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
 910                 return status;
 911
 912         if (status == LINK_TRAINING_SUCCESS &&
 913                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
 914                 status = LINK_TRAINING_LQA_FAIL;
 915
 916         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
 917         lane_count_set.bits.ENHANCED_FRAMING = 1;
 918         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 919
 920         core_link_write_dpcd(
 921                 link,
 922                 DP_LANE_COUNT_SET,
 923                 &lane_count_set.raw,
 924                 sizeof(lane_count_set));
 925
 926         return status;
 927 }
 928
 929 enum link_training_result dc_link_dp_perform_link_training(
 930         struct dc_link *link,
 931         const struct dc_link_settings *link_setting,
 932         bool skip_video_pattern)
 933 {
 934         enum link_training_result status = LINK_TRAINING_SUCCESS;
 935
 936         char *link_rate = "Unknown";
 937         char *lt_result = "Unknown";
 938
 939         struct link_training_settings lt_settings;
 940
 941         memset(&lt_settings, '\0', sizeof(lt_settings));
 942
 943         lt_settings.link_settings.link_rate = link_setting->link_rate;
 944         lt_settings.link_settings.lane_count = link_setting->lane_count;
 945
 946         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
 947
 948         /* TODO hard coded to SS for now
 949          * lt_settings.link_settings.link_spread =
 950          * dal_display_path_is_ss_supported(
 951          * path_mode->display_path) ?
 952          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
 953          * LINK_SPREAD_DISABLED;
 954          */
 955         lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
 956
 957         /* 1. set link rate, lane count and spread*/
 958         dpcd_set_link_settings(link, &lt_settings);
 959
 960         /* 2. perform link training (set link training done
 961          *  to false is done as well)*/
 962         status = perform_clock_recovery_sequence(link, &lt_settings);
 963         if (status == LINK_TRAINING_SUCCESS) {
 964                 status = perform_channel_equalization_sequence(link,
 965                                 &lt_settings);
 966         }
 967
 968         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
 969                 status = perform_link_training_int(link,
 970                                 &lt_settings,
 971                                 status);
 972         }
 973
 974         /* 6. print status message*/
 975         switch (lt_settings.link_settings.link_rate) {
 976
 977         case LINK_RATE_LOW:
 978                 link_rate = "RBR";
 979                 break;
 980         case LINK_RATE_HIGH:
 981                 link_rate = "HBR";
 982                 break;
 983         case LINK_RATE_HIGH2:
 984                 link_rate = "HBR2";
 985                 break;
 986         case LINK_RATE_RBR2:
 987                 link_rate = "RBR2";
 988                 break;
 989         case LINK_RATE_HIGH3:
 990                 link_rate = "HBR3";
 991                 break;
 992         default:
 993                 break;
 994         }
 995
 996         switch (status) {
 997         case LINK_TRAINING_SUCCESS:
 998                 lt_result = "pass";
 999                 break;
1000         case LINK_TRAINING_CR_FAIL_LANE0:
1001                 lt_result = "CR failed lane0";
1002                 break;
1003         case LINK_TRAINING_CR_FAIL_LANE1:
1004                 lt_result = "CR failed lane1";
1005                 break;
1006         case LINK_TRAINING_CR_FAIL_LANE23:
1007                 lt_result = "CR failed lane23";
1008                 break;
1009         case LINK_TRAINING_EQ_FAIL_CR:
1010                 lt_result = "CR failed in EQ";
1011                 break;
1012         case LINK_TRAINING_EQ_FAIL_EQ:
1013                 lt_result = "EQ failed";
1014                 break;
1015         case LINK_TRAINING_LQA_FAIL:
1016                 lt_result = "LQA failed";
1017                 break;
1018         default:
1019                 break;
1020         }
1021
1022         /* Connectivity log: link training */
1023         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
1024                         link_rate,
1025                         lt_settings.link_settings.lane_count,
1026                         lt_result,
1027                         lt_settings.lane_settings[0].VOLTAGE_SWING,
1028                         lt_settings.lane_settings[0].PRE_EMPHASIS);
1029
1030         return status;
1031 }
1032
1033
1034 bool perform_link_training_with_retries(
1035         struct dc_link *link,
1036         const struct dc_link_settings *link_setting,
1037         bool skip_video_pattern,
1038         int attempts)
1039 {
1040         uint8_t j;
1041         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1042
1043         for (j = 0; j < attempts; ++j) {
1044
1045                 if (dc_link_dp_perform_link_training(
1046                                 link,
1047                                 link_setting,
1048                                 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1049                         return true;
1050
1051                 msleep(delay_between_attempts);
1052                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1053         }
1054
1055         return false;
1056 }
1057
1058 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1059 {
1060         /* Set Default link settings */
1061         struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1062                         LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1063
1064         /* Higher link settings based on feature supported */
1065         if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1066                 max_link_cap.link_rate = LINK_RATE_HIGH2;
1067
1068         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1069                 max_link_cap.link_rate = LINK_RATE_HIGH3;
1070
1071         /* Lower link settings based on sink's link cap */
1072         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1073                 max_link_cap.lane_count =
1074                                 link->reported_link_cap.lane_count;
1075         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1076                 max_link_cap.link_rate =
1077                                 link->reported_link_cap.link_rate;
1078         if (link->reported_link_cap.link_spread <
1079                         max_link_cap.link_spread)
1080                 max_link_cap.link_spread =
1081                                 link->reported_link_cap.link_spread;
1082         return max_link_cap;
1083 }
1084
1085 bool dp_hbr_verify_link_cap(
1086         struct dc_link *link,
1087         struct dc_link_settings *known_limit_link_setting)
1088 {
1089         struct dc_link_settings max_link_cap = {0};
1090         struct dc_link_settings cur_link_setting = {0};
1091         struct dc_link_settings *cur = &cur_link_setting;
1092         struct dc_link_settings initial_link_settings = {0};
1093         bool success;
1094         bool skip_link_training;
1095         bool skip_video_pattern;
1096         struct clock_source *dp_cs;
1097         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1098         enum link_training_result status;
1099
1100         success = false;
1101         skip_link_training = false;
1102
1103         max_link_cap = get_max_link_cap(link);
1104
1105         /* TODO implement override and monitor patch later */
1106
1107         /* try to train the link from high to low to
1108          * find the physical link capability
1109          */
1110         /* disable PHY done possible by BIOS, will be done by driver itself */
1111         dp_disable_link_phy(link, link->connector_signal);
1112
1113         dp_cs = link->dc->res_pool->dp_clock_source;
1114
1115         if (dp_cs)
1116                 dp_cs_id = dp_cs->id;
1117         else {
1118                 /*
1119                  * dp clock source is not initialized for some reason.
1120                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1121                  */
1122                 ASSERT(dp_cs);
1123         }
1124
1125         /* link training starts with the maximum common settings
1126          * supported by both sink and ASIC.
1127          */
1128         initial_link_settings = get_common_supported_link_settings(
1129                         *known_limit_link_setting,
1130                         max_link_cap);
1131         cur_link_setting = initial_link_settings;
1132         do {
1133                 skip_video_pattern = true;
1134
1135                 if (cur->link_rate == LINK_RATE_LOW)
1136                         skip_video_pattern = false;
1137
1138                 dp_enable_link_phy(
1139                                 link,
1140                                 link->connector_signal,
1141                                 dp_cs_id,
1142                                 cur);
1143
1144
1145                 if (skip_link_training)
1146                         success = true;
1147                 else {
1148                         status = dc_link_dp_perform_link_training(
1149                                                         link,
1150                                                         cur,
1151                                                         skip_video_pattern);
1152                         if (status == LINK_TRAINING_SUCCESS)
1153                                 success = true;
1154                 }
1155
1156                 if (success)
1157                         link->verified_link_cap = *cur;
1158
1159                 /* always disable the link before trying another
1160                  * setting or before returning we'll enable it later
1161                  * based on the actual mode we're driving
1162                  */
1163                 dp_disable_link_phy(link, link->connector_signal);
1164         } while (!success && decide_fallback_link_setting(
1165                         initial_link_settings, cur, status));
1166
1167         /* Link Training failed for all Link Settings
1168          *  (Lane Count is still unknown)
1169          */
1170         if (!success) {
1171                 /* If all LT fails for all settings,
1172                  * set verified = failed safe (1 lane low)
1173                  */
1174                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1175                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
1176
1177                 link->verified_link_cap.link_spread =
1178                 LINK_SPREAD_DISABLED;
1179         }
1180
1181
1182         return success;
1183 }
1184
1185 static struct dc_link_settings get_common_supported_link_settings (
1186                 struct dc_link_settings link_setting_a,
1187                 struct dc_link_settings link_setting_b)
1188 {
1189         struct dc_link_settings link_settings = {0};
1190
1191         link_settings.lane_count =
1192                 (link_setting_a.lane_count <=
1193                         link_setting_b.lane_count) ?
1194                         link_setting_a.lane_count :
1195                         link_setting_b.lane_count;
1196         link_settings.link_rate =
1197                 (link_setting_a.link_rate <=
1198                         link_setting_b.link_rate) ?
1199                         link_setting_a.link_rate :
1200                         link_setting_b.link_rate;
1201         link_settings.link_spread = LINK_SPREAD_DISABLED;
1202
1203         /* in DP compliance test, DPR-120 may have
1204          * a random value in its MAX_LINK_BW dpcd field.
1205          * We map it to the maximum supported link rate that
1206          * is smaller than MAX_LINK_BW in this case.
1207          */
1208         if (link_settings.link_rate > LINK_RATE_HIGH3) {
1209                 link_settings.link_rate = LINK_RATE_HIGH3;
1210         } else if (link_settings.link_rate < LINK_RATE_HIGH3
1211                         && link_settings.link_rate > LINK_RATE_HIGH2) {
1212                 link_settings.link_rate = LINK_RATE_HIGH2;
1213         } else if (link_settings.link_rate < LINK_RATE_HIGH2
1214                         && link_settings.link_rate > LINK_RATE_HIGH) {
1215                 link_settings.link_rate = LINK_RATE_HIGH;
1216         } else if (link_settings.link_rate < LINK_RATE_HIGH
1217                         && link_settings.link_rate > LINK_RATE_LOW) {
1218                 link_settings.link_rate = LINK_RATE_LOW;
1219         } else if (link_settings.link_rate < LINK_RATE_LOW) {
1220                 link_settings.link_rate = LINK_RATE_UNKNOWN;
1221         }
1222
1223         return link_settings;
1224 }
1225
1226 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1227 {
1228         return lane_count <= LANE_COUNT_ONE;
1229 }
1230
1231 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1232 {
1233         return link_rate <= LINK_RATE_LOW;
1234 }
1235
1236 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1237 {
1238         switch (lane_count) {
1239         case LANE_COUNT_FOUR:
1240                 return LANE_COUNT_TWO;
1241         case LANE_COUNT_TWO:
1242                 return LANE_COUNT_ONE;
1243         case LANE_COUNT_ONE:
1244                 return LANE_COUNT_UNKNOWN;
1245         default:
1246                 return LANE_COUNT_UNKNOWN;
1247         }
1248 }
1249
1250 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1251 {
1252         switch (link_rate) {
1253         case LINK_RATE_HIGH3:
1254                 return LINK_RATE_HIGH2;
1255         case LINK_RATE_HIGH2:
1256                 return LINK_RATE_HIGH;
1257         case LINK_RATE_HIGH:
1258                 return LINK_RATE_LOW;
1259         case LINK_RATE_LOW:
1260                 return LINK_RATE_UNKNOWN;
1261         default:
1262                 return LINK_RATE_UNKNOWN;
1263         }
1264 }
1265
1266 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1267 {
1268         switch (lane_count) {
1269         case LANE_COUNT_ONE:
1270                 return LANE_COUNT_TWO;
1271         case LANE_COUNT_TWO:
1272                 return LANE_COUNT_FOUR;
1273         default:
1274                 return LANE_COUNT_UNKNOWN;
1275         }
1276 }
1277
1278 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1279 {
1280         switch (link_rate) {
1281         case LINK_RATE_LOW:
1282                 return LINK_RATE_HIGH;
1283         case LINK_RATE_HIGH:
1284                 return LINK_RATE_HIGH2;
1285         case LINK_RATE_HIGH2:
1286                 return LINK_RATE_HIGH3;
1287         default:
1288                 return LINK_RATE_UNKNOWN;
1289         }
1290 }
1291
1292 /*
1293  * function: set link rate and lane count fallback based
1294  * on current link setting and last link training result
1295  * return value:
1296  *                      true - link setting could be set
1297  *                      false - has reached minimum setting
1298  *                                      and no further fallback could be done
1299  */
1300 static bool decide_fallback_link_setting(
1301                 struct dc_link_settings initial_link_settings,
1302                 struct dc_link_settings *current_link_setting,
1303                 enum link_training_result training_result)
1304 {
1305         if (!current_link_setting)
1306                 return false;
1307
1308         switch (training_result) {
1309         case LINK_TRAINING_CR_FAIL_LANE0:
1310         case LINK_TRAINING_CR_FAIL_LANE1:
1311         case LINK_TRAINING_CR_FAIL_LANE23:
1312         case LINK_TRAINING_LQA_FAIL:
1313         {
1314                 if (!reached_minimum_link_rate
1315                                 (current_link_setting->link_rate)) {
1316                         current_link_setting->link_rate =
1317                                 reduce_link_rate(
1318                                         current_link_setting->link_rate);
1319                 } else if (!reached_minimum_lane_count
1320                                 (current_link_setting->lane_count)) {
1321                         current_link_setting->link_rate =
1322                                 initial_link_settings.link_rate;
1323                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1324                                 return false;
1325                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1326                                 current_link_setting->lane_count =
1327                                                 LANE_COUNT_ONE;
1328                         else if (training_result ==
1329                                         LINK_TRAINING_CR_FAIL_LANE23)
1330                                 current_link_setting->lane_count =
1331                                                 LANE_COUNT_TWO;
1332                         else
1333                                 current_link_setting->lane_count =
1334                                         reduce_lane_count(
1335                                         current_link_setting->lane_count);
1336                 } else {
1337                         return false;
1338                 }
1339                 break;
1340         }
1341         case LINK_TRAINING_EQ_FAIL_EQ:
1342         {
1343                 if (!reached_minimum_lane_count
1344                                 (current_link_setting->lane_count)) {
1345                         current_link_setting->lane_count =
1346                                 reduce_lane_count(
1347                                         current_link_setting->lane_count);
1348                 } else if (!reached_minimum_link_rate
1349                                 (current_link_setting->link_rate)) {
1350                         current_link_setting->link_rate =
1351                                 reduce_link_rate(
1352                                         current_link_setting->link_rate);
1353                 } else {
1354                         return false;
1355                 }
1356                 break;
1357         }
1358         case LINK_TRAINING_EQ_FAIL_CR:
1359         {
1360                 if (!reached_minimum_link_rate
1361                                 (current_link_setting->link_rate)) {
1362                         current_link_setting->link_rate =
1363                                 reduce_link_rate(
1364                                         current_link_setting->link_rate);
1365                 } else {
1366                         return false;
1367                 }
1368                 break;
1369         }
1370         default:
1371                 return false;
1372         }
1373         return true;
1374 }
1375
1376 static uint32_t bandwidth_in_kbps_from_timing(
1377         const struct dc_crtc_timing *timing)
1378 {
1379         uint32_t bits_per_channel = 0;
1380         uint32_t kbps;
1381
1382         switch (timing->display_color_depth) {
1383         case COLOR_DEPTH_666:
1384                 bits_per_channel = 6;
1385                 break;
1386         case COLOR_DEPTH_888:
1387                 bits_per_channel = 8;
1388                 break;
1389         case COLOR_DEPTH_101010:
1390                 bits_per_channel = 10;
1391                 break;
1392         case COLOR_DEPTH_121212:
1393                 bits_per_channel = 12;
1394                 break;
1395         case COLOR_DEPTH_141414:
1396                 bits_per_channel = 14;
1397                 break;
1398         case COLOR_DEPTH_161616:
1399                 bits_per_channel = 16;
1400                 break;
1401         default:
1402                 break;
1403         }
1404
1405         ASSERT(bits_per_channel != 0);
1406
1407         kbps = timing->pix_clk_khz;
1408         kbps *= bits_per_channel;
1409
1410         if (timing->flags.Y_ONLY != 1) {
1411                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1412                 kbps *= 3;
1413                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1414                         kbps /= 2;
1415                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1416                         kbps = kbps * 2 / 3;
1417         }
1418
1419         return kbps;
1420
1421 }
1422
1423 static uint32_t bandwidth_in_kbps_from_link_settings(
1424         const struct dc_link_settings *link_setting)
1425 {
1426         uint32_t link_rate_in_kbps = link_setting->link_rate *
1427                 LINK_RATE_REF_FREQ_IN_KHZ;
1428
1429         uint32_t lane_count  = link_setting->lane_count;
1430         uint32_t kbps = link_rate_in_kbps;
1431         kbps *= lane_count;
1432         kbps *= 8;   /* 8 bits per byte*/
1433
1434         return kbps;
1435
1436 }
1437
1438 bool dp_validate_mode_timing(
1439         struct dc_link *link,
1440         const struct dc_crtc_timing *timing)
1441 {
1442         uint32_t req_bw;
1443         uint32_t max_bw;
1444
1445         const struct dc_link_settings *link_setting;
1446
1447         /*always DP fail safe mode*/
1448         if (timing->pix_clk_khz == (uint32_t)25175 &&
1449                 timing->h_addressable == (uint32_t)640 &&
1450                 timing->v_addressable == (uint32_t)480)
1451                 return true;
1452
1453         /* We always use verified link settings */
1454         link_setting = &link->verified_link_cap;
1455
1456         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1457         /*if (flags.DYNAMIC_VALIDATION == 1 &&
1458                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1459                 link_setting = &link->verified_link_cap;
1460         */
1461
1462         req_bw = bandwidth_in_kbps_from_timing(timing);
1463         max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1464
1465         if (req_bw <= max_bw) {
1466                 /* remember the biggest mode here, during
1467                  * initial link training (to get
1468                  * verified_link_cap), LS sends event about
1469                  * cannot train at reported cap to upper
1470                  * layer and upper layer will re-enumerate modes.
1471                  * this is not necessary if the lower
1472                  * verified_link_cap is enough to drive
1473                  * all the modes */
1474
1475                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1476                 /* if (flags.DYNAMIC_VALIDATION == 1)
1477                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
1478                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1479                 return true;
1480         } else
1481                 return false;
1482 }
1483
1484 void decide_link_settings(struct dc_stream_state *stream,
1485         struct dc_link_settings *link_setting)
1486 {
1487
1488         struct dc_link_settings initial_link_setting = {
1489                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1490         struct dc_link_settings current_link_setting =
1491                         initial_link_setting;
1492         struct dc_link *link;
1493         uint32_t req_bw;
1494         uint32_t link_bw;
1495
1496         req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
1497
1498         link = stream->sink->link;
1499
1500         /* if preferred is specified through AMDDP, use it, if it's enough
1501          * to drive the mode
1502          */
1503         if (link->preferred_link_setting.lane_count !=
1504                         LANE_COUNT_UNKNOWN &&
1505                         link->preferred_link_setting.link_rate !=
1506                                         LINK_RATE_UNKNOWN) {
1507                 *link_setting =  link->preferred_link_setting;
1508                 return;
1509         }
1510
1511         /* MST doesn't perform link training for now
1512          * TODO: add MST specific link training routine
1513          */
1514         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1515                 *link_setting = link->verified_link_cap;
1516                 return;
1517         }
1518
1519         /* EDP use the link cap setting */
1520         if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
1521                 *link_setting = link->verified_link_cap;
1522                 return;
1523         }
1524
1525         /* search for the minimum link setting that:
1526          * 1. is supported according to the link training result
1527          * 2. could support the b/w requested by the timing
1528          */
1529         while (current_link_setting.link_rate <=
1530                         link->verified_link_cap.link_rate) {
1531                 link_bw = bandwidth_in_kbps_from_link_settings(
1532                                 &current_link_setting);
1533                 if (req_bw <= link_bw) {
1534                         *link_setting = current_link_setting;
1535                         return;
1536                 }
1537
1538                 if (current_link_setting.lane_count <
1539                                 link->verified_link_cap.lane_count) {
1540                         current_link_setting.lane_count =
1541                                         increase_lane_count(
1542                                                         current_link_setting.lane_count);
1543                 } else {
1544                         current_link_setting.link_rate =
1545                                         increase_link_rate(
1546                                                         current_link_setting.link_rate);
1547                         current_link_setting.lane_count =
1548                                         initial_link_setting.lane_count;
1549                 }
1550         }
1551
1552         BREAK_TO_DEBUGGER();
1553         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
1554
1555         *link_setting = link->verified_link_cap;
1556 }
1557
1558 /*************************Short Pulse IRQ***************************/
1559
1560 static bool hpd_rx_irq_check_link_loss_status(
1561         struct dc_link *link,
1562         union hpd_irq_data *hpd_irq_dpcd_data)
1563 {
1564         uint8_t irq_reg_rx_power_state = 0;
1565         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1566         union lane_status lane_status;
1567         uint32_t lane;
1568         bool sink_status_changed;
1569         bool return_code;
1570
1571         sink_status_changed = false;
1572         return_code = false;
1573
1574         if (link->cur_link_settings.lane_count == 0)
1575                 return return_code;
1576
1577         /*1. Check that Link Status changed, before re-training.*/
1578
1579         /*parse lane status*/
1580         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1581                 /* check status of lanes 0,1
1582                  * changed DpcdAddress_Lane01Status (0x202)
1583                  */
1584                 lane_status.raw = get_nibble_at_index(
1585                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1586                         lane);
1587
1588                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1589                         !lane_status.bits.CR_DONE_0 ||
1590                         !lane_status.bits.SYMBOL_LOCKED_0) {
1591                         /* if one of the channel equalization, clock
1592                          * recovery or symbol lock is dropped
1593                          * consider it as (link has been
1594                          * dropped) dp sink status has changed
1595                          */
1596                         sink_status_changed = true;
1597                         break;
1598                 }
1599         }
1600
1601         /* Check interlane align.*/
1602         if (sink_status_changed ||
1603                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1604
1605                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1606
1607                 return_code = true;
1608
1609                 /*2. Check that we can handle interrupt: Not in FS DOS,
1610                  *  Not in "Display Timeout" state, Link is trained.
1611                  */
1612                 dpcd_result = core_link_read_dpcd(link,
1613                         DP_SET_POWER,
1614                         &irq_reg_rx_power_state,
1615                         sizeof(irq_reg_rx_power_state));
1616
1617                 if (dpcd_result != DC_OK) {
1618                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1619                                 __func__);
1620                 } else {
1621                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1622                                 return_code = false;
1623                 }
1624         }
1625
1626         return return_code;
1627 }
1628
1629 static enum dc_status read_hpd_rx_irq_data(
1630         struct dc_link *link,
1631         union hpd_irq_data *irq_data)
1632 {
1633         static enum dc_status retval;
1634
1635         /* The HW reads 16 bytes from 200h on HPD,
1636          * but if we get an AUX_DEFER, the HW cannot retry
1637          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1638          * fail, so we now explicitly read 6 bytes which is
1639          * the req from the above mentioned test cases.
1640          *
1641          * For DP 1.4 we need to read those from 2002h range.
1642          */
1643         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1644                 retval = core_link_read_dpcd(
1645                         link,
1646                         DP_SINK_COUNT,
1647                         irq_data->raw,
1648                         sizeof(union hpd_irq_data));
1649         else {
1650                 /* Read 2 bytes at this location,... */
1651                 retval = core_link_read_dpcd(
1652                         link,
1653                         DP_SINK_COUNT_ESI,
1654                         irq_data->raw,
1655                         2);
1656
1657                 if (retval != DC_OK)
1658                         return retval;
1659
1660                 /* ... then read remaining 4 at the other location */
1661                 retval = core_link_read_dpcd(
1662                         link,
1663                         DP_LANE0_1_STATUS_ESI,
1664                         &irq_data->raw[2],
1665                         4);
1666         }
1667
1668         return retval;
1669 }
1670
1671 static bool allow_hpd_rx_irq(const struct dc_link *link)
1672 {
1673         /*
1674          * Don't handle RX IRQ unless one of following is met:
1675          * 1) The link is established (cur_link_settings != unknown)
1676          * 2) We kicked off MST detection
1677          * 3) We know we're dealing with an active dongle
1678          */
1679
1680         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1681                 (link->type == dc_connection_mst_branch) ||
1682                 is_dp_active_dongle(link))
1683                 return true;
1684
1685         return false;
1686 }
1687
1688 static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
1689 {
1690         union dpcd_psr_configuration psr_configuration;
1691
1692         if (!link->psr_enabled)
1693                 return false;
1694
1695         dm_helpers_dp_read_dpcd(
1696                 link->ctx,
1697                 link,
1698                 368,/*DpcdAddress_PSR_Enable_Cfg*/
1699                 &psr_configuration.raw,
1700                 sizeof(psr_configuration.raw));
1701
1702
1703         if (psr_configuration.bits.ENABLE) {
1704                 unsigned char dpcdbuf[3] = {0};
1705                 union psr_error_status psr_error_status;
1706                 union psr_sink_psr_status psr_sink_psr_status;
1707
1708                 dm_helpers_dp_read_dpcd(
1709                         link->ctx,
1710                         link,
1711                         0x2006, /*DpcdAddress_PSR_Error_Status*/
1712                         (unsigned char *) dpcdbuf,
1713                         sizeof(dpcdbuf));
1714
1715                 /*DPCD 2006h   ERROR STATUS*/
1716                 psr_error_status.raw = dpcdbuf[0];
1717                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
1718                 psr_sink_psr_status.raw = dpcdbuf[2];
1719
1720                 if (psr_error_status.bits.LINK_CRC_ERROR ||
1721                                 psr_error_status.bits.RFB_STORAGE_ERROR) {
1722                         /* Acknowledge and clear error bits */
1723                         dm_helpers_dp_write_dpcd(
1724                                 link->ctx,
1725                                 link,
1726                                 8198,/*DpcdAddress_PSR_Error_Status*/
1727                                 &psr_error_status.raw,
1728                                 sizeof(psr_error_status.raw));
1729
1730                         /* PSR error, disable and re-enable PSR */
1731                         dc_link_set_psr_enable(link, false, true);
1732                         dc_link_set_psr_enable(link, true, true);
1733
1734                         return true;
1735                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1736                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1737                         /* No error is detect, PSR is active.
1738                          * We should return with IRQ_HPD handled without
1739                          * checking for loss of sync since PSR would have
1740                          * powered down main link.
1741                          */
1742                         return true;
1743                 }
1744         }
1745         return false;
1746 }
1747
1748 static void dp_test_send_link_training(struct dc_link *link)
1749 {
1750         struct dc_link_settings link_settings = {0};
1751
1752         core_link_read_dpcd(
1753                         link,
1754                         DP_TEST_LANE_COUNT,
1755                         (unsigned char *)(&link_settings.lane_count),
1756                         1);
1757         core_link_read_dpcd(
1758                         link,
1759                         DP_TEST_LINK_RATE,
1760                         (unsigned char *)(&link_settings.link_rate),
1761                         1);
1762
1763         /* Set preferred link settings */
1764         link->verified_link_cap.lane_count = link_settings.lane_count;
1765         link->verified_link_cap.link_rate = link_settings.link_rate;
1766
1767         dp_retrain_link_dp_test(link, &link_settings, false);
1768 }
1769
1770 /* TODO hbr2 compliance eye output is unstable
1771  * (toggling on and off) with debugger break
1772  * This caueses intermittent PHY automation failure
1773  * Need to look into the root cause */
1774 static uint8_t force_tps4_for_cp2520 = 1;
1775
1776 static void dp_test_send_phy_test_pattern(struct dc_link *link)
1777 {
1778         union phy_test_pattern dpcd_test_pattern;
1779         union lane_adjust dpcd_lane_adjustment[2];
1780         unsigned char dpcd_post_cursor_2_adjustment = 0;
1781         unsigned char test_80_bit_pattern[
1782                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1783                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
1784         enum dp_test_pattern test_pattern;
1785         struct dc_link_training_settings link_settings;
1786         union lane_adjust dpcd_lane_adjust;
1787         unsigned int lane;
1788         struct link_training_settings link_training_settings;
1789         int i = 0;
1790
1791         dpcd_test_pattern.raw = 0;
1792         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1793         memset(&link_settings, 0, sizeof(link_settings));
1794
1795         /* get phy test pattern and pattern parameters from DP receiver */
1796         core_link_read_dpcd(
1797                         link,
1798                         DP_TEST_PHY_PATTERN,
1799                         &dpcd_test_pattern.raw,
1800                         sizeof(dpcd_test_pattern));
1801         core_link_read_dpcd(
1802                         link,
1803                         DP_ADJUST_REQUEST_LANE0_1,
1804                         &dpcd_lane_adjustment[0].raw,
1805                         sizeof(dpcd_lane_adjustment));
1806
1807         /*get post cursor 2 parameters
1808          * For DP 1.1a or eariler, this DPCD register's value is 0
1809          * For DP 1.2 or later:
1810          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1811          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1812          */
1813         core_link_read_dpcd(
1814                         link,
1815                         DP_ADJUST_REQUEST_POST_CURSOR2,
1816                         &dpcd_post_cursor_2_adjustment,
1817                         sizeof(dpcd_post_cursor_2_adjustment));
1818
1819         /* translate request */
1820         switch (dpcd_test_pattern.bits.PATTERN) {
1821         case PHY_TEST_PATTERN_D10_2:
1822                 test_pattern = DP_TEST_PATTERN_D102;
1823                 break;
1824         case PHY_TEST_PATTERN_SYMBOL_ERROR:
1825                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
1826                 break;
1827         case PHY_TEST_PATTERN_PRBS7:
1828                 test_pattern = DP_TEST_PATTERN_PRBS7;
1829                 break;
1830         case PHY_TEST_PATTERN_80BIT_CUSTOM:
1831                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
1832                 break;
1833         case PHY_TEST_PATTERN_CP2520_1:
1834                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1835                 test_pattern = (force_tps4_for_cp2520 == 1) ?
1836                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1837                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1838                 break;
1839         case PHY_TEST_PATTERN_CP2520_2:
1840                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1841                 test_pattern = (force_tps4_for_cp2520 == 1) ?
1842                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1843                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1844                 break;
1845         case PHY_TEST_PATTERN_CP2520_3:
1846                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1847                 break;
1848         default:
1849                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1850         break;
1851         }
1852
1853         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1854                 core_link_read_dpcd(
1855                                 link,
1856                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
1857                                 test_80_bit_pattern,
1858                                 sizeof(test_80_bit_pattern));
1859
1860         /* prepare link training settings */
1861         link_settings.link = link->cur_link_settings;
1862
1863         for (lane = 0; lane <
1864                 (unsigned int)(link->cur_link_settings.lane_count);
1865                 lane++) {
1866                 dpcd_lane_adjust.raw =
1867                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1868                 link_settings.lane_settings[lane].VOLTAGE_SWING =
1869                         (enum dc_voltage_swing)
1870                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1871                 link_settings.lane_settings[lane].PRE_EMPHASIS =
1872                         (enum dc_pre_emphasis)
1873                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1874                 link_settings.lane_settings[lane].POST_CURSOR2 =
1875                         (enum dc_post_cursor2)
1876                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1877         }
1878
1879         for (i = 0; i < 4; i++)
1880                 link_training_settings.lane_settings[i] =
1881                                 link_settings.lane_settings[i];
1882         link_training_settings.link_settings = link_settings.link;
1883         link_training_settings.allow_invalid_msa_timing_param = false;
1884         /*Usage: Measure DP physical lane signal
1885          * by DP SI test equipment automatically.
1886          * PHY test pattern request is generated by equipment via HPD interrupt.
1887          * HPD needs to be active all the time. HPD should be active
1888          * all the time. Do not touch it.
1889          * forward request to DS
1890          */
1891         dc_link_dp_set_test_pattern(
1892                 link,
1893                 test_pattern,
1894                 &link_training_settings,
1895                 test_80_bit_pattern,
1896                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1897                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
1898 }
1899
1900 static void dp_test_send_link_test_pattern(struct dc_link *link)
1901 {
1902         union link_test_pattern dpcd_test_pattern;
1903         union test_misc dpcd_test_params;
1904         enum dp_test_pattern test_pattern;
1905
1906         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1907         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1908
1909         /* get link test pattern and pattern parameters */
1910         core_link_read_dpcd(
1911                         link,
1912                         DP_TEST_PATTERN,
1913                         &dpcd_test_pattern.raw,
1914                         sizeof(dpcd_test_pattern));
1915         core_link_read_dpcd(
1916                         link,
1917                         DP_TEST_MISC0,
1918                         &dpcd_test_params.raw,
1919                         sizeof(dpcd_test_params));
1920
1921         switch (dpcd_test_pattern.bits.PATTERN) {
1922         case LINK_TEST_PATTERN_COLOR_RAMP:
1923                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1924         break;
1925         case LINK_TEST_PATTERN_VERTICAL_BARS:
1926                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1927         break; /* black and white */
1928         case LINK_TEST_PATTERN_COLOR_SQUARES:
1929                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1930                                 TEST_DYN_RANGE_VESA ?
1931                                 DP_TEST_PATTERN_COLOR_SQUARES :
1932                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1933         break;
1934         default:
1935                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1936         break;
1937         }
1938
1939         dc_link_dp_set_test_pattern(
1940                         link,
1941                         test_pattern,
1942                         NULL,
1943                         NULL,
1944                         0);
1945 }
1946
1947 static void handle_automated_test(struct dc_link *link)
1948 {
1949         union test_request test_request;
1950         union test_response test_response;
1951
1952         memset(&test_request, 0, sizeof(test_request));
1953         memset(&test_response, 0, sizeof(test_response));
1954
1955         core_link_read_dpcd(
1956                 link,
1957                 DP_TEST_REQUEST,
1958                 &test_request.raw,
1959                 sizeof(union test_request));
1960         if (test_request.bits.LINK_TRAINING) {
1961                 /* ACK first to let DP RX test box monitor LT sequence */
1962                 test_response.bits.ACK = 1;
1963                 core_link_write_dpcd(
1964                         link,
1965                         DP_TEST_RESPONSE,
1966                         &test_response.raw,
1967                         sizeof(test_response));
1968                 dp_test_send_link_training(link);
1969                 /* no acknowledge request is needed again */
1970                 test_response.bits.ACK = 0;
1971         }
1972         if (test_request.bits.LINK_TEST_PATTRN) {
1973                 dp_test_send_link_test_pattern(link);
1974                 test_response.bits.ACK = 1;
1975         }
1976         if (test_request.bits.PHY_TEST_PATTERN) {
1977                 dp_test_send_phy_test_pattern(link);
1978                 test_response.bits.ACK = 1;
1979         }
1980         if (!test_request.raw)
1981                 /* no requests, revert all test signals
1982                  * TODO: revert all test signals
1983                  */
1984                 test_response.bits.ACK = 1;
1985         /* send request acknowledgment */
1986         if (test_response.bits.ACK)
1987                 core_link_write_dpcd(
1988                         link,
1989                         DP_TEST_RESPONSE,
1990                         &test_response.raw,
1991                         sizeof(test_response));
1992 }
1993
1994 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data)
1995 {
1996         union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
1997         union device_service_irq device_service_clear = { { 0 } };
1998         enum dc_status result = DDC_RESULT_UNKNOWN;
1999         bool status = false;
2000         /* For use cases related to down stream connection status change,
2001          * PSR and device auto test, refer to function handle_sst_hpd_irq
2002          * in DAL2.1*/
2003
2004         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2005                 __func__, link->link_index);
2006
2007
2008          /* All the "handle_hpd_irq_xxx()" methods
2009                  * should be called only after
2010                  * dal_dpsst_ls_read_hpd_irq_data
2011                  * Order of calls is important too
2012                  */
2013         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2014         if (out_hpd_irq_dpcd_data)
2015                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2016
2017         if (result != DC_OK) {
2018                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2019                         __func__);
2020                 return false;
2021         }
2022
2023         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2024                 device_service_clear.bits.AUTOMATED_TEST = 1;
2025                 core_link_write_dpcd(
2026                         link,
2027                         DP_DEVICE_SERVICE_IRQ_VECTOR,
2028                         &device_service_clear.raw,
2029                         sizeof(device_service_clear.raw));
2030                 device_service_clear.raw = 0;
2031                 handle_automated_test(link);
2032                 return false;
2033         }
2034
2035         if (!allow_hpd_rx_irq(link)) {
2036                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2037                         __func__, link->link_index);
2038                 return false;
2039         }
2040
2041         if (handle_hpd_irq_psr_sink(link))
2042                 /* PSR-related error was detected and handled */
2043                 return true;
2044
2045         /* If PSR-related error handled, Main link may be off,
2046          * so do not handle as a normal sink status change interrupt.
2047          */
2048
2049         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2050                 return true;
2051
2052         /* check if we have MST msg and return since we poll for it */
2053         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2054                 return false;
2055
2056         /* For now we only handle 'Downstream port status' case.
2057          * If we got sink count changed it means
2058          * Downstream port status changed,
2059          * then DM should call DC to do the detection. */
2060         if (hpd_rx_irq_check_link_loss_status(
2061                 link,
2062                 &hpd_irq_dpcd_data)) {
2063                 /* Connectivity log: link loss */
2064                 CONN_DATA_LINK_LOSS(link,
2065                                         hpd_irq_dpcd_data.raw,
2066                                         sizeof(hpd_irq_dpcd_data),
2067                                         "Status: ");
2068
2069                 perform_link_training_with_retries(link,
2070                         &link->cur_link_settings,
2071                         true, LINK_TRAINING_ATTEMPTS);
2072
2073                 status = false;
2074         }
2075
2076         if (link->type == dc_connection_active_dongle &&
2077                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2078                         != link->dpcd_sink_count)
2079                 status = true;
2080
2081         /* reasons for HPD RX:
2082          * 1. Link Loss - ie Re-train the Link
2083          * 2. MST sideband message
2084          * 3. Automated Test - ie. Internal Commit
2085          * 4. CP (copy protection) - (not interesting for DM???)
2086          * 5. DRR
2087          * 6. Downstream Port status changed
2088          * -ie. Detect - this the only one
2089          * which is interesting for DM because
2090          * it must call dc_link_detect.
2091          */
2092         return status;
2093 }
2094
2095 /*query dpcd for version and mst cap addresses*/
2096 bool is_mst_supported(struct dc_link *link)
2097 {
2098         bool mst          = false;
2099         enum dc_status st = DC_OK;
2100         union dpcd_rev rev;
2101         union mstm_cap cap;
2102
2103         rev.raw  = 0;
2104         cap.raw  = 0;
2105
2106         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
2107                         sizeof(rev));
2108
2109         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2110
2111                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
2112                                 &cap.raw, sizeof(cap));
2113                 if (st == DC_OK && cap.bits.MST_CAP == 1)
2114                         mst = true;
2115         }
2116         return mst;
2117
2118 }
2119
2120 bool is_dp_active_dongle(const struct dc_link *link)
2121 {
2122         enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2123
2124         return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2125                         (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2126                         (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2127 }
2128
2129 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2130 {
2131         switch (bpc) {
2132         case DOWN_STREAM_MAX_8BPC:
2133                 return 8;
2134         case DOWN_STREAM_MAX_10BPC:
2135                 return 10;
2136         case DOWN_STREAM_MAX_12BPC:
2137                 return 12;
2138         case DOWN_STREAM_MAX_16BPC:
2139                 return 16;
2140         default:
2141                 break;
2142         }
2143
2144         return -1;
2145 }
2146
2147 static void get_active_converter_info(
2148         uint8_t data, struct dc_link *link)
2149 {
2150         union dp_downstream_port_present ds_port = { .byte = data };
2151
2152         /* decode converter info*/
2153         if (!ds_port.fields.PORT_PRESENT) {
2154                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2155                 ddc_service_set_dongle_type(link->ddc,
2156                                 link->dpcd_caps.dongle_type);
2157                 return;
2158         }
2159
2160         switch (ds_port.fields.PORT_TYPE) {
2161         case DOWNSTREAM_VGA:
2162                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2163                 break;
2164         case DOWNSTREAM_DVI_HDMI:
2165                 /* At this point we don't know is it DVI or HDMI,
2166                  * assume DVI.*/
2167                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2168                 break;
2169         default:
2170                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2171                 break;
2172         }
2173
2174         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
2175                 uint8_t det_caps[4];
2176                 union dwnstream_port_caps_byte0 *port_caps =
2177                         (union dwnstream_port_caps_byte0 *)det_caps;
2178                 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
2179                                 det_caps, sizeof(det_caps));
2180
2181                 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2182                 case DOWN_STREAM_DETAILED_VGA:
2183                         link->dpcd_caps.dongle_type =
2184                                 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2185                         break;
2186                 case DOWN_STREAM_DETAILED_DVI:
2187                         link->dpcd_caps.dongle_type =
2188                                 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2189                         break;
2190                 case DOWN_STREAM_DETAILED_HDMI:
2191                         link->dpcd_caps.dongle_type =
2192                                 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2193
2194                         link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
2195                         if (ds_port.fields.DETAILED_CAPS) {
2196
2197                                 union dwnstream_port_caps_byte3_hdmi
2198                                         hdmi_caps = {.raw = det_caps[3] };
2199                                 union dwnstream_port_caps_byte2
2200                                         hdmi_color_caps = {.raw = det_caps[2] };
2201                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2202                                         det_caps[1] * 25000;
2203
2204                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
2205                                         hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
2206                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2207                                         hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2208                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2209                                         hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2210                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2211                                         hdmi_caps.bits.YCrCr422_CONVERSION;
2212                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2213                                         hdmi_caps.bits.YCrCr420_CONVERSION;
2214
2215                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2216                                         translate_dpcd_max_bpc(
2217                                                 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
2218
2219                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
2220                         }
2221
2222                         break;
2223                 }
2224         }
2225
2226         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
2227
2228         {
2229                 struct dp_device_vendor_id dp_id;
2230
2231                 /* read IEEE branch device id */
2232                 core_link_read_dpcd(
2233                         link,
2234                         DP_BRANCH_OUI,
2235                         (uint8_t *)&dp_id,
2236                         sizeof(dp_id));
2237
2238                 link->dpcd_caps.branch_dev_id =
2239                         (dp_id.ieee_oui[0] << 16) +
2240                         (dp_id.ieee_oui[1] << 8) +
2241                         dp_id.ieee_oui[2];
2242
2243                 memmove(
2244                         link->dpcd_caps.branch_dev_name,
2245                         dp_id.ieee_device_id,
2246                         sizeof(dp_id.ieee_device_id));
2247         }
2248
2249         {
2250                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2251
2252                 core_link_read_dpcd(
2253                         link,
2254                         DP_BRANCH_REVISION_START,
2255                         (uint8_t *)&dp_hw_fw_revision,
2256                         sizeof(dp_hw_fw_revision));
2257
2258                 link->dpcd_caps.branch_hw_revision =
2259                         dp_hw_fw_revision.ieee_hw_rev;
2260         }
2261 }
2262
2263 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
2264                 int length)
2265 {
2266         int retry = 0;
2267         union dp_downstream_port_present ds_port = { 0 };
2268
2269         if (!link->dpcd_caps.dpcd_rev.raw) {
2270                 do {
2271                         dp_receiver_power_ctrl(link, true);
2272                         core_link_read_dpcd(link, DP_DPCD_REV,
2273                                                         dpcd_data, length);
2274                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
2275                                 DP_DPCD_REV -
2276                                 DP_DPCD_REV];
2277                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2278         }
2279
2280         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2281                                  DP_DPCD_REV];
2282
2283         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2284                 switch (link->dpcd_caps.branch_dev_id) {
2285                 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2286                  * all internal circuits including AUX communication preventing
2287                  * reading DPCD table and EDID (spec violation).
2288                  * Encoder will skip DP RX power down on disable_output to
2289                  * keep receiver powered all the time.*/
2290                 case DP_BRANCH_DEVICE_ID_1:
2291                 case DP_BRANCH_DEVICE_ID_4:
2292                         link->wa_flags.dp_keep_receiver_powered = true;
2293                         break;
2294
2295                 /* TODO: May need work around for other dongles. */
2296                 default:
2297                         link->wa_flags.dp_keep_receiver_powered = false;
2298                         break;
2299                 }
2300         } else
2301                 link->wa_flags.dp_keep_receiver_powered = false;
2302 }
2303
2304 static bool retrieve_link_cap(struct dc_link *link)
2305 {
2306         uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
2307
2308         union down_stream_port_count down_strm_port_count;
2309         union edp_configuration_cap edp_config_cap;
2310         union dp_downstream_port_present ds_port = { 0 };
2311         enum dc_status status = DC_ERROR_UNEXPECTED;
2312         uint32_t read_dpcd_retry_cnt = 3;
2313         int i;
2314
2315         memset(dpcd_data, '\0', sizeof(dpcd_data));
2316         memset(&down_strm_port_count,
2317                 '\0', sizeof(union down_stream_port_count));
2318         memset(&edp_config_cap, '\0',
2319                 sizeof(union edp_configuration_cap));
2320
2321         for (i = 0; i < read_dpcd_retry_cnt; i++) {
2322                 status = core_link_read_dpcd(
2323                                 link,
2324                                 DP_DPCD_REV,
2325                                 dpcd_data,
2326                                 sizeof(dpcd_data));
2327                 if (status == DC_OK)
2328                         break;
2329         }
2330
2331         if (status != DC_OK) {
2332                 dm_error("%s: Read dpcd data failed.\n", __func__);
2333                 return false;
2334         }
2335
2336         {
2337                 union training_aux_rd_interval aux_rd_interval;
2338
2339                 aux_rd_interval.raw =
2340                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
2341
2342                 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2343                         core_link_read_dpcd(
2344                                 link,
2345                                 DP_DP13_DPCD_REV,
2346                                 dpcd_data,
2347                                 sizeof(dpcd_data));
2348                 }
2349         }
2350
2351         link->dpcd_caps.dpcd_rev.raw =
2352                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2353
2354         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2355                                  DP_DPCD_REV];
2356
2357         get_active_converter_info(ds_port.byte, link);
2358
2359         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2360
2361         link->dpcd_caps.allow_invalid_MSA_timing_param =
2362                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2363
2364         link->dpcd_caps.max_ln_count.raw = dpcd_data[
2365                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
2366
2367         link->dpcd_caps.max_down_spread.raw = dpcd_data[
2368                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
2369
2370         link->reported_link_cap.lane_count =
2371                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
2372         link->reported_link_cap.link_rate = dpcd_data[
2373                 DP_MAX_LINK_RATE - DP_DPCD_REV];
2374         link->reported_link_cap.link_spread =
2375                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2376                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2377
2378         edp_config_cap.raw = dpcd_data[
2379                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
2380         link->dpcd_caps.panel_mode_edp =
2381                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2382         link->dpcd_caps.dpcd_display_control_capable =
2383                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
2384
2385         link->test_pattern_enabled = false;
2386         link->compliance_test_state.raw = 0;
2387
2388         /* read sink count */
2389         core_link_read_dpcd(link,
2390                         DP_SINK_COUNT,
2391                         &link->dpcd_caps.sink_count.raw,
2392                         sizeof(link->dpcd_caps.sink_count.raw));
2393
2394         /* Connectivity log: detection */
2395         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
2396
2397         return true;
2398 }
2399
2400 bool detect_dp_sink_caps(struct dc_link *link)
2401 {
2402         return retrieve_link_cap(link);
2403
2404         /* dc init_hw has power encoder using default
2405          * signal for connector. For native DP, no
2406          * need to power up encoder again. If not native
2407          * DP, hw_init may need check signal or power up
2408          * encoder here.
2409          */
2410         /* TODO save sink caps in link->sink */
2411 }
2412
2413 void detect_edp_sink_caps(struct dc_link *link)
2414 {
2415         retrieve_link_cap(link);
2416
2417         if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
2418                 link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
2419
2420         link->verified_link_cap = link->reported_link_cap;
2421 }
2422
2423 void dc_link_dp_enable_hpd(const struct dc_link *link)
2424 {
2425         struct link_encoder *encoder = link->link_enc;
2426
2427         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2428                 encoder->funcs->enable_hpd(encoder);
2429 }
2430
2431 void dc_link_dp_disable_hpd(const struct dc_link *link)
2432 {
2433         struct link_encoder *encoder = link->link_enc;
2434
2435         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2436                 encoder->funcs->disable_hpd(encoder);
2437 }
2438
2439 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2440 {
2441         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2442                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2443                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
2444                 return true;
2445         else
2446                 return false;
2447 }
2448
2449 static void set_crtc_test_pattern(struct dc_link *link,
2450                                 struct pipe_ctx *pipe_ctx,
2451                                 enum dp_test_pattern test_pattern)
2452 {
2453         enum controller_dp_test_pattern controller_test_pattern;
2454         enum dc_color_depth color_depth = pipe_ctx->
2455                 stream->timing.display_color_depth;
2456         struct bit_depth_reduction_params params;
2457
2458         memset(&params, 0, sizeof(params));
2459
2460         switch (test_pattern) {
2461         case DP_TEST_PATTERN_COLOR_SQUARES:
2462                 controller_test_pattern =
2463                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2464         break;
2465         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2466                 controller_test_pattern =
2467                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2468         break;
2469         case DP_TEST_PATTERN_VERTICAL_BARS:
2470                 controller_test_pattern =
2471                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2472         break;
2473         case DP_TEST_PATTERN_HORIZONTAL_BARS:
2474                 controller_test_pattern =
2475                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2476         break;
2477         case DP_TEST_PATTERN_COLOR_RAMP:
2478                 controller_test_pattern =
2479                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2480         break;
2481         default:
2482                 controller_test_pattern =
2483                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2484         break;
2485         }
2486
2487         switch (test_pattern) {
2488         case DP_TEST_PATTERN_COLOR_SQUARES:
2489         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2490         case DP_TEST_PATTERN_VERTICAL_BARS:
2491         case DP_TEST_PATTERN_HORIZONTAL_BARS:
2492         case DP_TEST_PATTERN_COLOR_RAMP:
2493         {
2494                 /* disable bit depth reduction */
2495                 pipe_ctx->stream->bit_depth_params = params;
2496                 pipe_ctx->stream_res.opp->funcs->
2497                         opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
2498
2499                 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2500                                 controller_test_pattern, color_depth);
2501         }
2502         break;
2503         case DP_TEST_PATTERN_VIDEO_MODE:
2504         {
2505                 /* restore bitdepth reduction */
2506                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2507                                         &params);
2508                 pipe_ctx->stream->bit_depth_params = params;
2509                 pipe_ctx->stream_res.opp->funcs->
2510                         opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
2511
2512                 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2513                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2514                                 color_depth);
2515         }
2516         break;
2517
2518         default:
2519         break;
2520         }
2521 }
2522
2523 bool dc_link_dp_set_test_pattern(
2524         struct dc_link *link,
2525         enum dp_test_pattern test_pattern,
2526         const struct link_training_settings *p_link_settings,
2527         const unsigned char *p_custom_pattern,
2528         unsigned int cust_pattern_size)
2529 {
2530         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2531         struct pipe_ctx *pipe_ctx = &pipes[0];
2532         unsigned int lane;
2533         unsigned int i;
2534         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2535         union dpcd_training_pattern training_pattern;
2536         enum dpcd_phy_test_patterns pattern;
2537
2538         memset(&training_pattern, 0, sizeof(training_pattern));
2539
2540         for (i = 0; i < MAX_PIPES; i++) {
2541                 if (pipes[i].stream->sink->link == link) {
2542                         pipe_ctx = &pipes[i];
2543                         break;
2544                 }
2545         }
2546
2547         /* Reset CRTC Test Pattern if it is currently running and request
2548          * is VideoMode Reset DP Phy Test Pattern if it is currently running
2549          * and request is VideoMode
2550          */
2551         if (link->test_pattern_enabled && test_pattern ==
2552                         DP_TEST_PATTERN_VIDEO_MODE) {
2553                 /* Set CRTC Test Pattern */
2554                 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2555                 dp_set_hw_test_pattern(link, test_pattern,
2556                                 (uint8_t *)p_custom_pattern,
2557                                 (uint32_t)cust_pattern_size);
2558
2559                 /* Unblank Stream */
2560                 link->dc->hwss.unblank_stream(
2561                         pipe_ctx,
2562                         &link->verified_link_cap);
2563                 /* TODO:m_pHwss->MuteAudioEndpoint
2564                  * (pPathMode->pDisplayPath, false);
2565                  */
2566
2567                 /* Reset Test Pattern state */
2568                 link->test_pattern_enabled = false;
2569
2570                 return true;
2571         }
2572
2573         /* Check for PHY Test Patterns */
2574         if (is_dp_phy_pattern(test_pattern)) {
2575                 /* Set DPCD Lane Settings before running test pattern */
2576                 if (p_link_settings != NULL) {
2577                         dp_set_hw_lane_settings(link, p_link_settings);
2578                         dpcd_set_lane_settings(link, p_link_settings);
2579                 }
2580
2581                 /* Blank stream if running test pattern */
2582                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2583                         /*TODO:
2584                          * m_pHwss->
2585                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2586                          */
2587                         /* Blank stream */
2588                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
2589                 }
2590
2591                 dp_set_hw_test_pattern(link, test_pattern,
2592                                 (uint8_t *)p_custom_pattern,
2593                                 (uint32_t)cust_pattern_size);
2594
2595                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2596                         /* Set Test Pattern state */
2597                         link->test_pattern_enabled = true;
2598                         if (p_link_settings != NULL)
2599                                 dpcd_set_link_settings(link,
2600                                                 p_link_settings);
2601                 }
2602
2603                 switch (test_pattern) {
2604                 case DP_TEST_PATTERN_VIDEO_MODE:
2605                         pattern = PHY_TEST_PATTERN_NONE;
2606                         break;
2607                 case DP_TEST_PATTERN_D102:
2608                         pattern = PHY_TEST_PATTERN_D10_2;
2609                         break;
2610                 case DP_TEST_PATTERN_SYMBOL_ERROR:
2611                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
2612                         break;
2613                 case DP_TEST_PATTERN_PRBS7:
2614                         pattern = PHY_TEST_PATTERN_PRBS7;
2615                         break;
2616                 case DP_TEST_PATTERN_80BIT_CUSTOM:
2617                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
2618                         break;
2619                 case DP_TEST_PATTERN_CP2520_1:
2620                         pattern = PHY_TEST_PATTERN_CP2520_1;
2621                         break;
2622                 case DP_TEST_PATTERN_CP2520_2:
2623                         pattern = PHY_TEST_PATTERN_CP2520_2;
2624                         break;
2625                 case DP_TEST_PATTERN_CP2520_3:
2626                         pattern = PHY_TEST_PATTERN_CP2520_3;
2627                         break;
2628                 default:
2629                         return false;
2630                 }
2631
2632                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2633                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2634                         return false;
2635
2636                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
2637                         /* tell receiver that we are sending qualification
2638                          * pattern DP 1.2 or later - DP receiver's link quality
2639                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
2640                          * register (0x10B~0x10E)\
2641                          */
2642                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2643                                 link_qual_pattern[lane] =
2644                                                 (unsigned char)(pattern);
2645
2646                         core_link_write_dpcd(link,
2647                                         DP_LINK_QUAL_LANE0_SET,
2648                                         link_qual_pattern,
2649                                         sizeof(link_qual_pattern));
2650                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2651                            link->dpcd_caps.dpcd_rev.raw == 0) {
2652                         /* tell receiver that we are sending qualification
2653                          * pattern DP 1.1a or earlier - DP receiver's link
2654                          * quality pattern is set using
2655                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2656                          * register (0x102). We will use v_1.3 when we are
2657                          * setting test pattern for DP 1.1.
2658                          */
2659                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2660                                             &training_pattern.raw,
2661                                             sizeof(training_pattern));
2662                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
2663                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2664                                              &training_pattern.raw,
2665                                              sizeof(training_pattern));
2666                 }
2667         } else {
2668         /* CRTC Patterns */
2669                 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2670                 /* Set Test Pattern state */
2671                 link->test_pattern_enabled = true;
2672         }
2673
2674         return true;
2675 }
2676
2677 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
2678 {
2679         unsigned char mstmCntl;
2680
2681         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2682         if (enable)
2683                 mstmCntl |= DP_MST_EN;
2684         else
2685                 mstmCntl &= (~DP_MST_EN);
2686
2687         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2688 }