drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39
  40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  41 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int uvd_v6_0_start(struct amdgpu_device *adev);
  43 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  44 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  45 static int uvd_v6_0_set_clockgating_state(void *handle,
  46                                           enum amd_clockgating_state state);
  47 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  48                                  bool enable);
  49
  50 /**
  51  * uvd_v6_0_ring_get_rptr - get read pointer
  52  *
  53  * @ring: amdgpu_ring pointer
  54  *
  55  * Returns the current hardware read pointer
  56  */
  57 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         return RREG32(mmUVD_RBC_RB_RPTR);
  62 }
  63
  64 /**
  65  * uvd_v6_0_ring_get_wptr - get write pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware write pointer
  70  */
  71 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32(mmUVD_RBC_RB_WPTR);
  76 }
  77
  78 /**
  79  * uvd_v6_0_ring_set_wptr - set write pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Commits the write pointer to the hardware
  84  */
  85 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  90 }
  91
  92 static int uvd_v6_0_early_init(void *handle)
  93 {
  94         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  95
  96         if (!(adev->flags & AMD_IS_APU) &&
  97             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
  98                 return -ENOENT;
  99
 100         uvd_v6_0_set_ring_funcs(adev);
 101         uvd_v6_0_set_irq_funcs(adev);
 102
 103         return 0;
 104 }
 105
 106 static int uvd_v6_0_sw_init(void *handle)
 107 {
 108         struct amdgpu_ring *ring;
 109         int r;
 110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 111
 112         /* UVD TRAP */
 113         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
 114         if (r)
 115                 return r;
 116
 117         r = amdgpu_uvd_sw_init(adev);
 118         if (r)
 119                 return r;
 120
 121         r = amdgpu_uvd_resume(adev);
 122         if (r)
 123                 return r;
 124
 125         ring = &adev->uvd.ring;
 126         sprintf(ring->name, "uvd");
 127         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 128
 129         return r;
 130 }
 131
 132 static int uvd_v6_0_sw_fini(void *handle)
 133 {
 134         int r;
 135         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 136
 137         r = amdgpu_uvd_suspend(adev);
 138         if (r)
 139                 return r;
 140
 141         return amdgpu_uvd_sw_fini(adev);
 142 }
 143
 144 /**
 145  * uvd_v6_0_hw_init - start and test UVD block
 146  *
 147  * @adev: amdgpu_device pointer
 148  *
 149  * Initialize the hardware, boot up the VCPU and do some testing
 150  */
 151 static int uvd_v6_0_hw_init(void *handle)
 152 {
 153         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 154         struct amdgpu_ring *ring = &adev->uvd.ring;
 155         uint32_t tmp;
 156         int r;
 157
 158         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 159         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 160         uvd_v6_0_enable_mgcg(adev, true);
 161
 162         ring->ready = true;
 163         r = amdgpu_ring_test_ring(ring);
 164         if (r) {
 165                 ring->ready = false;
 166                 goto done;
 167         }
 168
 169         r = amdgpu_ring_alloc(ring, 10);
 170         if (r) {
 171                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 172                 goto done;
 173         }
 174
 175         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 176         amdgpu_ring_write(ring, tmp);
 177         amdgpu_ring_write(ring, 0xFFFFF);
 178
 179         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 180         amdgpu_ring_write(ring, tmp);
 181         amdgpu_ring_write(ring, 0xFFFFF);
 182
 183         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 184         amdgpu_ring_write(ring, tmp);
 185         amdgpu_ring_write(ring, 0xFFFFF);
 186
 187         /* Clear timeout status bits */
 188         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 189         amdgpu_ring_write(ring, 0x8);
 190
 191         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 192         amdgpu_ring_write(ring, 3);
 193
 194         amdgpu_ring_commit(ring);
 195
 196 done:
 197         if (!r)
 198                 DRM_INFO("UVD initialized successfully.\n");
 199
 200         return r;
 201 }
 202
 203 /**
 204  * uvd_v6_0_hw_fini - stop the hardware block
 205  *
 206  * @adev: amdgpu_device pointer
 207  *
 208  * Stop the UVD block, mark ring as not ready any more
 209  */
 210 static int uvd_v6_0_hw_fini(void *handle)
 211 {
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213         struct amdgpu_ring *ring = &adev->uvd.ring;
 214
 215         if (RREG32(mmUVD_STATUS) != 0)
 216                 uvd_v6_0_stop(adev);
 217
 218         ring->ready = false;
 219
 220         return 0;
 221 }
 222
 223 static int uvd_v6_0_suspend(void *handle)
 224 {
 225         int r;
 226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 227
 228         r = uvd_v6_0_hw_fini(adev);
 229         if (r)
 230                 return r;
 231
 232         return amdgpu_uvd_suspend(adev);
 233 }
 234
 235 static int uvd_v6_0_resume(void *handle)
 236 {
 237         int r;
 238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 239
 240         r = amdgpu_uvd_resume(adev);
 241         if (r)
 242                 return r;
 243
 244         return uvd_v6_0_hw_init(adev);
 245 }
 246
 247 /**
 248  * uvd_v6_0_mc_resume - memory controller programming
 249  *
 250  * @adev: amdgpu_device pointer
 251  *
 252  * Let the UVD memory controller know it's offsets
 253  */
 254 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 255 {
 256         uint64_t offset;
 257         uint32_t size;
 258
 259         /* programm memory controller bits 0-27 */
 260         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 261                         lower_32_bits(adev->uvd.gpu_addr));
 262         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 263                         upper_32_bits(adev->uvd.gpu_addr));
 264
 265         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 266         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 267         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 268         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 269
 270         offset += size;
 271         size = AMDGPU_UVD_HEAP_SIZE;
 272         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 273         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 274
 275         offset += size;
 276         size = AMDGPU_UVD_STACK_SIZE +
 277                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 278         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 279         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 280
 281         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 282         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 283         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 284
 285         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 286 }
 287
 288 #if 0
 289 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 290                 bool enable)
 291 {
 292         u32 data, data1;
 293
 294         data = RREG32(mmUVD_CGC_GATE);
 295         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 296         if (enable) {
 297                 data |= UVD_CGC_GATE__SYS_MASK |
 298                                 UVD_CGC_GATE__UDEC_MASK |
 299                                 UVD_CGC_GATE__MPEG2_MASK |
 300                                 UVD_CGC_GATE__RBC_MASK |
 301                                 UVD_CGC_GATE__LMI_MC_MASK |
 302                                 UVD_CGC_GATE__IDCT_MASK |
 303                                 UVD_CGC_GATE__MPRD_MASK |
 304                                 UVD_CGC_GATE__MPC_MASK |
 305                                 UVD_CGC_GATE__LBSI_MASK |
 306                                 UVD_CGC_GATE__LRBBM_MASK |
 307                                 UVD_CGC_GATE__UDEC_RE_MASK |
 308                                 UVD_CGC_GATE__UDEC_CM_MASK |
 309                                 UVD_CGC_GATE__UDEC_IT_MASK |
 310                                 UVD_CGC_GATE__UDEC_DB_MASK |
 311                                 UVD_CGC_GATE__UDEC_MP_MASK |
 312                                 UVD_CGC_GATE__WCB_MASK |
 313                                 UVD_CGC_GATE__VCPU_MASK |
 314                                 UVD_CGC_GATE__SCPU_MASK;
 315                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 316                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 317                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 318                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 319                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 320                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 321                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 322                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 323                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 324                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 325                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 326                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 327                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 328         } else {
 329                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 330                                 UVD_CGC_GATE__UDEC_MASK |
 331                                 UVD_CGC_GATE__MPEG2_MASK |
 332                                 UVD_CGC_GATE__RBC_MASK |
 333                                 UVD_CGC_GATE__LMI_MC_MASK |
 334                                 UVD_CGC_GATE__LMI_UMC_MASK |
 335                                 UVD_CGC_GATE__IDCT_MASK |
 336                                 UVD_CGC_GATE__MPRD_MASK |
 337                                 UVD_CGC_GATE__MPC_MASK |
 338                                 UVD_CGC_GATE__LBSI_MASK |
 339                                 UVD_CGC_GATE__LRBBM_MASK |
 340                                 UVD_CGC_GATE__UDEC_RE_MASK |
 341                                 UVD_CGC_GATE__UDEC_CM_MASK |
 342                                 UVD_CGC_GATE__UDEC_IT_MASK |
 343                                 UVD_CGC_GATE__UDEC_DB_MASK |
 344                                 UVD_CGC_GATE__UDEC_MP_MASK |
 345                                 UVD_CGC_GATE__WCB_MASK |
 346                                 UVD_CGC_GATE__VCPU_MASK |
 347                                 UVD_CGC_GATE__SCPU_MASK);
 348                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 349                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 350                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 351                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 352                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 353                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 354                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 355                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 356                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 357                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 358                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 359                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 360                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 361         }
 362         WREG32(mmUVD_CGC_GATE, data);
 363         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 364 }
 365 #endif
 366
 367 /**
 368  * uvd_v6_0_start - start UVD block
 369  *
 370  * @adev: amdgpu_device pointer
 371  *
 372  * Setup and start the UVD block
 373  */
 374 static int uvd_v6_0_start(struct amdgpu_device *adev)
 375 {
 376         struct amdgpu_ring *ring = &adev->uvd.ring;
 377         uint32_t rb_bufsz, tmp;
 378         uint32_t lmi_swap_cntl;
 379         uint32_t mp_swap_cntl;
 380         int i, j, r;
 381
 382         /* disable DPG */
 383         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 384
 385         /* disable byte swapping */
 386         lmi_swap_cntl = 0;
 387         mp_swap_cntl = 0;
 388
 389         uvd_v6_0_mc_resume(adev);
 390
 391         /* disable interupt */
 392         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 393
 394         /* stall UMC and register bus before resetting VCPU */
 395         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 396         mdelay(1);
 397
 398         /* put LMI, VCPU, RBC etc... into reset */
 399         WREG32(mmUVD_SOFT_RESET,
 400                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 401                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 402                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 403                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 404                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 405                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 406                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 407                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 408         mdelay(5);
 409
 410         /* take UVD block out of reset */
 411         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 412         mdelay(5);
 413
 414         /* initialize UVD memory controller */
 415         WREG32(mmUVD_LMI_CTRL,
 416                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 417                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 418                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 419                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 420                 UVD_LMI_CTRL__REQ_MODE_MASK |
 421                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 422
 423 #ifdef __BIG_ENDIAN
 424         /* swap (8 in 32) RB and IB */
 425         lmi_swap_cntl = 0xa;
 426         mp_swap_cntl = 0;
 427 #endif
 428         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 429         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 430
 431         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 432         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 433         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 434         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 435         WREG32(mmUVD_MPC_SET_ALU, 0);
 436         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 437
 438         /* take all subblocks out of reset, except VCPU */
 439         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 440         mdelay(5);
 441
 442         /* enable VCPU clock */
 443         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 444
 445         /* enable UMC */
 446         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 447
 448         /* boot up the VCPU */
 449         WREG32(mmUVD_SOFT_RESET, 0);
 450         mdelay(10);
 451
 452         for (i = 0; i < 10; ++i) {
 453                 uint32_t status;
 454
 455                 for (j = 0; j < 100; ++j) {
 456                         status = RREG32(mmUVD_STATUS);
 457                         if (status & 2)
 458                                 break;
 459                         mdelay(10);
 460                 }
 461                 r = 0;
 462                 if (status & 2)
 463                         break;
 464
 465                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 466                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 467                 mdelay(10);
 468                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 469                 mdelay(10);
 470                 r = -1;
 471         }
 472
 473         if (r) {
 474                 DRM_ERROR("UVD not responding, giving up!!!\n");
 475                 return r;
 476         }
 477         /* enable master interrupt */
 478         WREG32_P(mmUVD_MASTINT_EN,
 479                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 480                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 481
 482         /* clear the bit 4 of UVD_STATUS */
 483         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 484
 485         /* force RBC into idle state */
 486         rb_bufsz = order_base_2(ring->ring_size);
 487         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 488         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 489         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 490         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 491         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 492         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 493         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 494
 495         /* set the write pointer delay */
 496         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 497
 498         /* set the wb address */
 499         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 500
 501         /* programm the RB_BASE for ring buffer */
 502         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 503                         lower_32_bits(ring->gpu_addr));
 504         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 505                         upper_32_bits(ring->gpu_addr));
 506
 507         /* Initialize the ring buffer's read and write pointers */
 508         WREG32(mmUVD_RBC_RB_RPTR, 0);
 509
 510         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 511         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 512
 513         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 514
 515         return 0;
 516 }
 517
 518 /**
 519  * uvd_v6_0_stop - stop UVD block
 520  *
 521  * @adev: amdgpu_device pointer
 522  *
 523  * stop the UVD block
 524  */
 525 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 526 {
 527         /* force RBC into idle state */
 528         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 529
 530         /* Stall UMC and register bus before resetting VCPU */
 531         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 532         mdelay(1);
 533
 534         /* put VCPU into reset */
 535         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 536         mdelay(5);
 537
 538         /* disable VCPU clock */
 539         WREG32(mmUVD_VCPU_CNTL, 0x0);
 540
 541         /* Unstall UMC and register bus */
 542         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 543
 544         WREG32(mmUVD_STATUS, 0);
 545 }
 546
 547 /**
 548  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 549  *
 550  * @ring: amdgpu_ring pointer
 551  * @fence: fence to emit
 552  *
 553  * Write a fence and a trap command to the ring.
 554  */
 555 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 556                                      unsigned flags)
 557 {
 558         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 559
 560         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 561         amdgpu_ring_write(ring, seq);
 562         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 563         amdgpu_ring_write(ring, addr & 0xffffffff);
 564         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 565         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 566         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 567         amdgpu_ring_write(ring, 0);
 568
 569         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 570         amdgpu_ring_write(ring, 0);
 571         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 572         amdgpu_ring_write(ring, 0);
 573         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 574         amdgpu_ring_write(ring, 2);
 575 }
 576
 577 /**
 578  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 579  *
 580  * @ring: amdgpu_ring pointer
 581  *
 582  * Emits an hdp flush.
 583  */
 584 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 585 {
 586         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 587         amdgpu_ring_write(ring, 0);
 588 }
 589
 590 /**
 591  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 592  *
 593  * @ring: amdgpu_ring pointer
 594  *
 595  * Emits an hdp invalidate.
 596  */
 597 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 598 {
 599         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 600         amdgpu_ring_write(ring, 1);
 601 }
 602
 603 /**
 604  * uvd_v6_0_ring_test_ring - register write test
 605  *
 606  * @ring: amdgpu_ring pointer
 607  *
 608  * Test if we can successfully write to the context register
 609  */
 610 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 611 {
 612         struct amdgpu_device *adev = ring->adev;
 613         uint32_t tmp = 0;
 614         unsigned i;
 615         int r;
 616
 617         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 618         r = amdgpu_ring_alloc(ring, 3);
 619         if (r) {
 620                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 621                           ring->idx, r);
 622                 return r;
 623         }
 624         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 625         amdgpu_ring_write(ring, 0xDEADBEEF);
 626         amdgpu_ring_commit(ring);
 627         for (i = 0; i < adev->usec_timeout; i++) {
 628                 tmp = RREG32(mmUVD_CONTEXT_ID);
 629                 if (tmp == 0xDEADBEEF)
 630                         break;
 631                 DRM_UDELAY(1);
 632         }
 633
 634         if (i < adev->usec_timeout) {
 635                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 636                          ring->idx, i);
 637         } else {
 638                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 639                           ring->idx, tmp);
 640                 r = -EINVAL;
 641         }
 642         return r;
 643 }
 644
 645 /**
 646  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 647  *
 648  * @ring: amdgpu_ring pointer
 649  * @ib: indirect buffer to execute
 650  *
 651  * Write ring commands to execute the indirect buffer
 652  */
 653 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 654                                   struct amdgpu_ib *ib,
 655                                   unsigned vm_id, bool ctx_switch)
 656 {
 657         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
 658         amdgpu_ring_write(ring, vm_id);
 659
 660         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 661         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 662         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 663         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 664         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 665         amdgpu_ring_write(ring, ib->length_dw);
 666 }
 667
 668 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 669                                          unsigned vm_id, uint64_t pd_addr)
 670 {
 671         uint32_t reg;
 672
 673         if (vm_id < 8)
 674                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
 675         else
 676                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
 677
 678         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 679         amdgpu_ring_write(ring, reg << 2);
 680         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 681         amdgpu_ring_write(ring, pd_addr >> 12);
 682         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 683         amdgpu_ring_write(ring, 0x8);
 684
 685         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 686         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 687         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 688         amdgpu_ring_write(ring, 1 << vm_id);
 689         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 690         amdgpu_ring_write(ring, 0x8);
 691
 692         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 693         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 694         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 695         amdgpu_ring_write(ring, 0);
 696         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 697         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
 698         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 699         amdgpu_ring_write(ring, 0xC);
 700 }
 701
 702 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 703 {
 704         uint32_t seq = ring->fence_drv.sync_seq;
 705         uint64_t addr = ring->fence_drv.gpu_addr;
 706
 707         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 708         amdgpu_ring_write(ring, lower_32_bits(addr));
 709         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 710         amdgpu_ring_write(ring, upper_32_bits(addr));
 711         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 712         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 713         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
 714         amdgpu_ring_write(ring, seq);
 715         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 716         amdgpu_ring_write(ring, 0xE);
 717 }
 718
 719 static bool uvd_v6_0_is_idle(void *handle)
 720 {
 721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 722
 723         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 724 }
 725
 726 static int uvd_v6_0_wait_for_idle(void *handle)
 727 {
 728         unsigned i;
 729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 730
 731         for (i = 0; i < adev->usec_timeout; i++) {
 732                 if (uvd_v6_0_is_idle(handle))
 733                         return 0;
 734         }
 735         return -ETIMEDOUT;
 736 }
 737
 738 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
 739 static bool uvd_v6_0_check_soft_reset(void *handle)
 740 {
 741         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 742         u32 srbm_soft_reset = 0;
 743         u32 tmp = RREG32(mmSRBM_STATUS);
 744
 745         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
 746             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
 747             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
 748                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 749
 750         if (srbm_soft_reset) {
 751                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
 752                 return true;
 753         } else {
 754                 adev->uvd.srbm_soft_reset = 0;
 755                 return false;
 756         }
 757 }
 758
 759 static int uvd_v6_0_pre_soft_reset(void *handle)
 760 {
 761         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 762
 763         if (!adev->uvd.srbm_soft_reset)
 764                 return 0;
 765
 766         uvd_v6_0_stop(adev);
 767         return 0;
 768 }
 769
 770 static int uvd_v6_0_soft_reset(void *handle)
 771 {
 772         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 773         u32 srbm_soft_reset;
 774
 775         if (!adev->uvd.srbm_soft_reset)
 776                 return 0;
 777         srbm_soft_reset = adev->uvd.srbm_soft_reset;
 778
 779         if (srbm_soft_reset) {
 780                 u32 tmp;
 781
 782                 tmp = RREG32(mmSRBM_SOFT_RESET);
 783                 tmp |= srbm_soft_reset;
 784                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 785                 WREG32(mmSRBM_SOFT_RESET, tmp);
 786                 tmp = RREG32(mmSRBM_SOFT_RESET);
 787
 788                 udelay(50);
 789
 790                 tmp &= ~srbm_soft_reset;
 791                 WREG32(mmSRBM_SOFT_RESET, tmp);
 792                 tmp = RREG32(mmSRBM_SOFT_RESET);
 793
 794                 /* Wait a little for things to settle down */
 795                 udelay(50);
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int uvd_v6_0_post_soft_reset(void *handle)
 802 {
 803         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 804
 805         if (!adev->uvd.srbm_soft_reset)
 806                 return 0;
 807
 808         mdelay(5);
 809
 810         return uvd_v6_0_start(adev);
 811 }
 812
 813 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 814                                         struct amdgpu_irq_src *source,
 815                                         unsigned type,
 816                                         enum amdgpu_interrupt_state state)
 817 {
 818         // TODO
 819         return 0;
 820 }
 821
 822 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 823                                       struct amdgpu_irq_src *source,
 824                                       struct amdgpu_iv_entry *entry)
 825 {
 826         DRM_DEBUG("IH: UVD TRAP\n");
 827         amdgpu_fence_process(&adev->uvd.ring);
 828         return 0;
 829 }
 830
 831 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
 832 {
 833         uint32_t data1, data3;
 834
 835         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 836         data3 = RREG32(mmUVD_CGC_GATE);
 837
 838         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 839                      UVD_SUVD_CGC_GATE__SIT_MASK |
 840                      UVD_SUVD_CGC_GATE__SMP_MASK |
 841                      UVD_SUVD_CGC_GATE__SCM_MASK |
 842                      UVD_SUVD_CGC_GATE__SDB_MASK |
 843                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 844                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 845                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 846                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 847                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 848                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 849                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 850                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 851
 852         if (enable) {
 853                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
 854                         UVD_CGC_GATE__UDEC_MASK      |
 855                         UVD_CGC_GATE__MPEG2_MASK     |
 856                         UVD_CGC_GATE__RBC_MASK       |
 857                         UVD_CGC_GATE__LMI_MC_MASK    |
 858                         UVD_CGC_GATE__LMI_UMC_MASK   |
 859                         UVD_CGC_GATE__IDCT_MASK      |
 860                         UVD_CGC_GATE__MPRD_MASK      |
 861                         UVD_CGC_GATE__MPC_MASK       |
 862                         UVD_CGC_GATE__LBSI_MASK      |
 863                         UVD_CGC_GATE__LRBBM_MASK     |
 864                         UVD_CGC_GATE__UDEC_RE_MASK   |
 865                         UVD_CGC_GATE__UDEC_CM_MASK   |
 866                         UVD_CGC_GATE__UDEC_IT_MASK   |
 867                         UVD_CGC_GATE__UDEC_DB_MASK   |
 868                         UVD_CGC_GATE__UDEC_MP_MASK   |
 869                         UVD_CGC_GATE__WCB_MASK       |
 870                         UVD_CGC_GATE__JPEG_MASK      |
 871                         UVD_CGC_GATE__SCPU_MASK      |
 872                         UVD_CGC_GATE__JPEG2_MASK);
 873                 /* only in pg enabled, we can gate clock to vcpu*/
 874                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 875                         data3 |= UVD_CGC_GATE__VCPU_MASK;
 876
 877                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
 878         } else {
 879                 data3 = 0;
 880         }
 881
 882         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 883         WREG32(mmUVD_CGC_GATE, data3);
 884 }
 885
 886 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
 887 {
 888         uint32_t data, data2;
 889
 890         data = RREG32(mmUVD_CGC_CTRL);
 891         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 892
 893
 894         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 895                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 896
 897
 898         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 899                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 900                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 901
 902         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 903                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 904                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 905                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 906                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 907                         UVD_CGC_CTRL__SYS_MODE_MASK |
 908                         UVD_CGC_CTRL__UDEC_MODE_MASK |
 909                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
 910                         UVD_CGC_CTRL__REGS_MODE_MASK |
 911                         UVD_CGC_CTRL__RBC_MODE_MASK |
 912                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 913                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 914                         UVD_CGC_CTRL__IDCT_MODE_MASK |
 915                         UVD_CGC_CTRL__MPRD_MODE_MASK |
 916                         UVD_CGC_CTRL__MPC_MODE_MASK |
 917                         UVD_CGC_CTRL__LBSI_MODE_MASK |
 918                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
 919                         UVD_CGC_CTRL__WCB_MODE_MASK |
 920                         UVD_CGC_CTRL__VCPU_MODE_MASK |
 921                         UVD_CGC_CTRL__JPEG_MODE_MASK |
 922                         UVD_CGC_CTRL__SCPU_MODE_MASK |
 923                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
 924         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 925                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 926                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 927                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 928                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 929
 930         WREG32(mmUVD_CGC_CTRL, data);
 931         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 932 }
 933
 934 #if 0
 935 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
 936 {
 937         uint32_t data, data1, cgc_flags, suvd_flags;
 938
 939         data = RREG32(mmUVD_CGC_GATE);
 940         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 941
 942         cgc_flags = UVD_CGC_GATE__SYS_MASK |
 943                 UVD_CGC_GATE__UDEC_MASK |
 944                 UVD_CGC_GATE__MPEG2_MASK |
 945                 UVD_CGC_GATE__RBC_MASK |
 946                 UVD_CGC_GATE__LMI_MC_MASK |
 947                 UVD_CGC_GATE__IDCT_MASK |
 948                 UVD_CGC_GATE__MPRD_MASK |
 949                 UVD_CGC_GATE__MPC_MASK |
 950                 UVD_CGC_GATE__LBSI_MASK |
 951                 UVD_CGC_GATE__LRBBM_MASK |
 952                 UVD_CGC_GATE__UDEC_RE_MASK |
 953                 UVD_CGC_GATE__UDEC_CM_MASK |
 954                 UVD_CGC_GATE__UDEC_IT_MASK |
 955                 UVD_CGC_GATE__UDEC_DB_MASK |
 956                 UVD_CGC_GATE__UDEC_MP_MASK |
 957                 UVD_CGC_GATE__WCB_MASK |
 958                 UVD_CGC_GATE__VCPU_MASK |
 959                 UVD_CGC_GATE__SCPU_MASK |
 960                 UVD_CGC_GATE__JPEG_MASK |
 961                 UVD_CGC_GATE__JPEG2_MASK;
 962
 963         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 964                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 965                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 966                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 967                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 968
 969         data |= cgc_flags;
 970         data1 |= suvd_flags;
 971
 972         WREG32(mmUVD_CGC_GATE, data);
 973         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 974 }
 975 #endif
 976
 977 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
 978                                  bool enable)
 979 {
 980         u32 orig, data;
 981
 982         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 983                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 984                 data |= 0xfff;
 985                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 986
 987                 orig = data = RREG32(mmUVD_CGC_CTRL);
 988                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 989                 if (orig != data)
 990                         WREG32(mmUVD_CGC_CTRL, data);
 991         } else {
 992                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 993                 data &= ~0xfff;
 994                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 995
 996                 orig = data = RREG32(mmUVD_CGC_CTRL);
 997                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 998                 if (orig != data)
 999                         WREG32(mmUVD_CGC_CTRL, data);
1000         }
1001 }
1002
1003 static int uvd_v6_0_set_clockgating_state(void *handle,
1004                                           enum amd_clockgating_state state)
1005 {
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1008
1009         if (enable) {
1010                 /* wait for STATUS to clear */
1011                 if (uvd_v6_0_wait_for_idle(handle))
1012                         return -EBUSY;
1013                 uvd_v6_0_enable_clock_gating(adev, true);
1014                 /* enable HW gates because UVD is idle */
1015 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1016         } else {
1017                 /* disable HW gating and enable Sw gating */
1018                 uvd_v6_0_enable_clock_gating(adev, false);
1019         }
1020         uvd_v6_0_set_sw_clock_gating(adev);
1021         return 0;
1022 }
1023
1024 static int uvd_v6_0_set_powergating_state(void *handle,
1025                                           enum amd_powergating_state state)
1026 {
1027         /* This doesn't actually powergate the UVD block.
1028          * That's done in the dpm code via the SMC.  This
1029          * just re-inits the block as necessary.  The actual
1030          * gating still happens in the dpm code.  We should
1031          * revisit this when there is a cleaner line between
1032          * the smc and the hw blocks
1033          */
1034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035         int ret = 0;
1036
1037         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1038
1039         if (state == AMD_PG_STATE_GATE) {
1040                 uvd_v6_0_stop(adev);
1041         } else {
1042                 ret = uvd_v6_0_start(adev);
1043                 if (ret)
1044                         goto out;
1045         }
1046
1047 out:
1048         return ret;
1049 }
1050
1051 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1052 {
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054         int data;
1055
1056         mutex_lock(&adev->pm.mutex);
1057
1058         if (adev->flags & AMD_IS_APU)
1059                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1060         else
1061                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1062
1063         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1064                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1065                 goto out;
1066         }
1067
1068         /* AMD_CG_SUPPORT_UVD_MGCG */
1069         data = RREG32(mmUVD_CGC_CTRL);
1070         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1071                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1072
1073 out:
1074         mutex_unlock(&adev->pm.mutex);
1075 }
1076
1077 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1078         .name = "uvd_v6_0",
1079         .early_init = uvd_v6_0_early_init,
1080         .late_init = NULL,
1081         .sw_init = uvd_v6_0_sw_init,
1082         .sw_fini = uvd_v6_0_sw_fini,
1083         .hw_init = uvd_v6_0_hw_init,
1084         .hw_fini = uvd_v6_0_hw_fini,
1085         .suspend = uvd_v6_0_suspend,
1086         .resume = uvd_v6_0_resume,
1087         .is_idle = uvd_v6_0_is_idle,
1088         .wait_for_idle = uvd_v6_0_wait_for_idle,
1089         .check_soft_reset = uvd_v6_0_check_soft_reset,
1090         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1091         .soft_reset = uvd_v6_0_soft_reset,
1092         .post_soft_reset = uvd_v6_0_post_soft_reset,
1093         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1094         .set_powergating_state = uvd_v6_0_set_powergating_state,
1095         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1096 };
1097
1098 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1099         .type = AMDGPU_RING_TYPE_UVD,
1100         .align_mask = 0xf,
1101         .nop = PACKET0(mmUVD_NO_OP, 0),
1102         .support_64bit_ptrs = false,
1103         .get_rptr = uvd_v6_0_ring_get_rptr,
1104         .get_wptr = uvd_v6_0_ring_get_wptr,
1105         .set_wptr = uvd_v6_0_ring_set_wptr,
1106         .parse_cs = amdgpu_uvd_ring_parse_cs,
1107         .emit_frame_size =
1108                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1109                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1110                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1111                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1112         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1113         .emit_ib = uvd_v6_0_ring_emit_ib,
1114         .emit_fence = uvd_v6_0_ring_emit_fence,
1115         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1116         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1117         .test_ring = uvd_v6_0_ring_test_ring,
1118         .test_ib = amdgpu_uvd_ring_test_ib,
1119         .insert_nop = amdgpu_ring_insert_nop,
1120         .pad_ib = amdgpu_ring_generic_pad_ib,
1121         .begin_use = amdgpu_uvd_ring_begin_use,
1122         .end_use = amdgpu_uvd_ring_end_use,
1123 };
1124
1125 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1126         .type = AMDGPU_RING_TYPE_UVD,
1127         .align_mask = 0xf,
1128         .nop = PACKET0(mmUVD_NO_OP, 0),
1129         .support_64bit_ptrs = false,
1130         .get_rptr = uvd_v6_0_ring_get_rptr,
1131         .get_wptr = uvd_v6_0_ring_get_wptr,
1132         .set_wptr = uvd_v6_0_ring_set_wptr,
1133         .emit_frame_size =
1134                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1135                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1136                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1137                 20 + /* uvd_v6_0_ring_emit_vm_flush */
1138                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1139         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1140         .emit_ib = uvd_v6_0_ring_emit_ib,
1141         .emit_fence = uvd_v6_0_ring_emit_fence,
1142         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1143         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1144         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1145         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1146         .test_ring = uvd_v6_0_ring_test_ring,
1147         .test_ib = amdgpu_uvd_ring_test_ib,
1148         .insert_nop = amdgpu_ring_insert_nop,
1149         .pad_ib = amdgpu_ring_generic_pad_ib,
1150         .begin_use = amdgpu_uvd_ring_begin_use,
1151         .end_use = amdgpu_uvd_ring_end_use,
1152 };
1153
1154 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1155 {
1156         if (adev->asic_type >= CHIP_POLARIS10) {
1157                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1158                 DRM_INFO("UVD is enabled in VM mode\n");
1159         } else {
1160                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1161                 DRM_INFO("UVD is enabled in physical mode\n");
1162         }
1163 }
1164
1165 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1166         .set = uvd_v6_0_set_interrupt_state,
1167         .process = uvd_v6_0_process_interrupt,
1168 };
1169
1170 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1171 {
1172         adev->uvd.irq.num_types = 1;
1173         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1174 }
1175
1176 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1177 {
1178                 .type = AMD_IP_BLOCK_TYPE_UVD,
1179                 .major = 6,
1180                 .minor = 0,
1181                 .rev = 0,
1182                 .funcs = &uvd_v6_0_ip_funcs,
1183 };
1184
1185 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1186 {
1187                 .type = AMD_IP_BLOCK_TYPE_UVD,
1188                 .major = 6,
1189                 .minor = 2,
1190                 .rev = 0,
1191                 .funcs = &uvd_v6_0_ip_funcs,
1192 };
1193
1194 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1195 {
1196                 .type = AMD_IP_BLOCK_TYPE_UVD,
1197                 .major = 6,
1198                 .minor = 3,
1199                 .rev = 0,
1200                 .funcs = &uvd_v6_0_ip_funcs,
1201 };