drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  65
  66
  67 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  68 {
  69         SDMA0_REGISTER_OFFSET,
  70         SDMA1_REGISTER_OFFSET
  71 };
  72
  73 static const u32 golden_settings_tonga_a11[] =
  74 {
  75         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  76         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  77         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  78         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  79         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  80         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  81         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  82         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  83         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  84         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  85 };
  86
  87 static const u32 tonga_mgcg_cgcg_init[] =
  88 {
  89         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  90         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  91 };
  92
  93 static const u32 golden_settings_fiji_a10[] =
  94 {
  95         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  96         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  97         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  98         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  99         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 100         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 101         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 102         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 103 };
 104
 105 static const u32 fiji_mgcg_cgcg_init[] =
 106 {
 107         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 108         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 109 };
 110
 111 static const u32 golden_settings_polaris11_a11[] =
 112 {
 113         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 114         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 115         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 116         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 117         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 118         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 119         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 120         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 121         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 122         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 123 };
 124
 125 static const u32 golden_settings_polaris10_a11[] =
 126 {
 127         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 128         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 129         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 130         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 131         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 132         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 133         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 134         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 135         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 136         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 137 };
 138
 139 static const u32 cz_golden_settings_a11[] =
 140 {
 141         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 142         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 143         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 144         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 145         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 146         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 147         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 148         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 149         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 150         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 151         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 152         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 153 };
 154
 155 static const u32 cz_mgcg_cgcg_init[] =
 156 {
 157         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 158         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 159 };
 160
 161 static const u32 stoney_golden_settings_a11[] =
 162 {
 163         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 164         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 165         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 166         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 167 };
 168
 169 static const u32 stoney_mgcg_cgcg_init[] =
 170 {
 171         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 172 };
 173
 174 /*
 175  * sDMA - System DMA
 176  * Starting with CIK, the GPU has new asynchronous
 177  * DMA engines.  These engines are used for compute
 178  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 179  * and each one supports 1 ring buffer used for gfx
 180  * and 2 queues used for compute.
 181  *
 182  * The programming model is very similar to the CP
 183  * (ring buffer, IBs, etc.), but sDMA has it's own
 184  * packet format that is different from the PM4 format
 185  * used by the CP. sDMA supports copying data, writing
 186  * embedded data, solid fills, and a number of other
 187  * things.  It also has support for tiling/detiling of
 188  * buffers.
 189  */
 190
 191 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 192 {
 193         switch (adev->asic_type) {
 194         case CHIP_FIJI:
 195                 amdgpu_program_register_sequence(adev,
 196                                                  fiji_mgcg_cgcg_init,
 197                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 198                 amdgpu_program_register_sequence(adev,
 199                                                  golden_settings_fiji_a10,
 200                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 201                 break;
 202         case CHIP_TONGA:
 203                 amdgpu_program_register_sequence(adev,
 204                                                  tonga_mgcg_cgcg_init,
 205                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 206                 amdgpu_program_register_sequence(adev,
 207                                                  golden_settings_tonga_a11,
 208                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 209                 break;
 210         case CHIP_POLARIS11:
 211         case CHIP_POLARIS12:
 212                 amdgpu_program_register_sequence(adev,
 213                                                  golden_settings_polaris11_a11,
 214                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 215                 break;
 216         case CHIP_POLARIS10:
 217                 amdgpu_program_register_sequence(adev,
 218                                                  golden_settings_polaris10_a11,
 219                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 220                 break;
 221         case CHIP_CARRIZO:
 222                 amdgpu_program_register_sequence(adev,
 223                                                  cz_mgcg_cgcg_init,
 224                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 225                 amdgpu_program_register_sequence(adev,
 226                                                  cz_golden_settings_a11,
 227                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 228                 break;
 229         case CHIP_STONEY:
 230                 amdgpu_program_register_sequence(adev,
 231                                                  stoney_mgcg_cgcg_init,
 232                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 233                 amdgpu_program_register_sequence(adev,
 234                                                  stoney_golden_settings_a11,
 235                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 236                 break;
 237         default:
 238                 break;
 239         }
 240 }
 241
 242 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 243 {
 244         int i;
 245         for (i = 0; i < adev->sdma.num_instances; i++) {
 246                 release_firmware(adev->sdma.instance[i].fw);
 247                 adev->sdma.instance[i].fw = NULL;
 248         }
 249 }
 250
 251 /**
 252  * sdma_v3_0_init_microcode - load ucode images from disk
 253  *
 254  * @adev: amdgpu_device pointer
 255  *
 256  * Use the firmware interface to load the ucode images into
 257  * the driver (not loaded into hw).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 261 {
 262         const char *chip_name;
 263         char fw_name[30];
 264         int err = 0, i;
 265         struct amdgpu_firmware_info *info = NULL;
 266         const struct common_firmware_header *header = NULL;
 267         const struct sdma_firmware_header_v1_0 *hdr;
 268
 269         DRM_DEBUG("\n");
 270
 271         switch (adev->asic_type) {
 272         case CHIP_TONGA:
 273                 chip_name = "tonga";
 274                 break;
 275         case CHIP_FIJI:
 276                 chip_name = "fiji";
 277                 break;
 278         case CHIP_POLARIS11:
 279                 chip_name = "polaris11";
 280                 break;
 281         case CHIP_POLARIS10:
 282                 chip_name = "polaris10";
 283                 break;
 284         case CHIP_POLARIS12:
 285                 chip_name = "polaris12";
 286                 break;
 287         case CHIP_CARRIZO:
 288                 chip_name = "carrizo";
 289                 break;
 290         case CHIP_STONEY:
 291                 chip_name = "stoney";
 292                 break;
 293         default: BUG();
 294         }
 295
 296         for (i = 0; i < adev->sdma.num_instances; i++) {
 297                 if (i == 0)
 298                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 299                 else
 300                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 301                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 302                 if (err)
 303                         goto out;
 304                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 305                 if (err)
 306                         goto out;
 307                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 308                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 309                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 310                 if (adev->sdma.instance[i].feature_version >= 20)
 311                         adev->sdma.instance[i].burst_nop = true;
 312
 313                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 314                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 315                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 316                         info->fw = adev->sdma.instance[i].fw;
 317                         header = (const struct common_firmware_header *)info->fw->data;
 318                         adev->firmware.fw_size +=
 319                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 320                 }
 321         }
 322 out:
 323         if (err) {
 324                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 325                 for (i = 0; i < adev->sdma.num_instances; i++) {
 326                         release_firmware(adev->sdma.instance[i].fw);
 327                         adev->sdma.instance[i].fw = NULL;
 328                 }
 329         }
 330         return err;
 331 }
 332
 333 /**
 334  * sdma_v3_0_ring_get_rptr - get the current read pointer
 335  *
 336  * @ring: amdgpu ring pointer
 337  *
 338  * Get the current rptr from the hardware (VI+).
 339  */
 340 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 341 {
 342         /* XXX check if swapping is necessary on BE */
 343         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 344 }
 345
 346 /**
 347  * sdma_v3_0_ring_get_wptr - get the current write pointer
 348  *
 349  * @ring: amdgpu ring pointer
 350  *
 351  * Get the current wptr from the hardware (VI+).
 352  */
 353 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 354 {
 355         struct amdgpu_device *adev = ring->adev;
 356         u32 wptr;
 357
 358         if (ring->use_doorbell) {
 359                 /* XXX check if swapping is necessary on BE */
 360                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 361         } else {
 362                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 363
 364                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 365         }
 366
 367         return wptr;
 368 }
 369
 370 /**
 371  * sdma_v3_0_ring_set_wptr - commit the write pointer
 372  *
 373  * @ring: amdgpu ring pointer
 374  *
 375  * Write the wptr back to the hardware (VI+).
 376  */
 377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 378 {
 379         struct amdgpu_device *adev = ring->adev;
 380
 381         if (ring->use_doorbell) {
 382                 /* XXX check if swapping is necessary on BE */
 383                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2;
 384                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
 385         } else {
 386                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 387
 388                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
 389         }
 390 }
 391
 392 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 393 {
 394         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 395         int i;
 396
 397         for (i = 0; i < count; i++)
 398                 if (sdma && sdma->burst_nop && (i == 0))
 399                         amdgpu_ring_write(ring, ring->funcs->nop |
 400                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 401                 else
 402                         amdgpu_ring_write(ring, ring->funcs->nop);
 403 }
 404
 405 /**
 406  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 407  *
 408  * @ring: amdgpu ring pointer
 409  * @ib: IB object to schedule
 410  *
 411  * Schedule an IB in the DMA ring (VI).
 412  */
 413 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 414                                    struct amdgpu_ib *ib,
 415                                    unsigned vm_id, bool ctx_switch)
 416 {
 417         u32 vmid = vm_id & 0xf;
 418
 419         /* IB packet must end on a 8 DW boundary */
 420         sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 421
 422         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 423                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 424         /* base must be 32 byte aligned */
 425         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 426         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 427         amdgpu_ring_write(ring, ib->length_dw);
 428         amdgpu_ring_write(ring, 0);
 429         amdgpu_ring_write(ring, 0);
 430
 431 }
 432
 433 /**
 434  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 435  *
 436  * @ring: amdgpu ring pointer
 437  *
 438  * Emit an hdp flush packet on the requested DMA ring.
 439  */
 440 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 441 {
 442         u32 ref_and_mask = 0;
 443
 444         if (ring == &ring->adev->sdma.instance[0].ring)
 445                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 446         else
 447                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 448
 449         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 450                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 451                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 452         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 453         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 454         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 455         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 456         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 457                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 458 }
 459
 460 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 461 {
 462         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 463                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 464         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 465         amdgpu_ring_write(ring, 1);
 466 }
 467
 468 /**
 469  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 470  *
 471  * @ring: amdgpu ring pointer
 472  * @fence: amdgpu fence object
 473  *
 474  * Add a DMA fence packet to the ring to write
 475  * the fence seq number and DMA trap packet to generate
 476  * an interrupt if needed (VI).
 477  */
 478 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 479                                       unsigned flags)
 480 {
 481         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 482         /* write the fence */
 483         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 484         amdgpu_ring_write(ring, lower_32_bits(addr));
 485         amdgpu_ring_write(ring, upper_32_bits(addr));
 486         amdgpu_ring_write(ring, lower_32_bits(seq));
 487
 488         /* optionally write high bits as well */
 489         if (write64bit) {
 490                 addr += 4;
 491                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 492                 amdgpu_ring_write(ring, lower_32_bits(addr));
 493                 amdgpu_ring_write(ring, upper_32_bits(addr));
 494                 amdgpu_ring_write(ring, upper_32_bits(seq));
 495         }
 496
 497         /* generate an interrupt */
 498         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 499         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 500 }
 501
 502 /**
 503  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Stop the gfx async dma ring buffers (VI).
 508  */
 509 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 510 {
 511         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 512         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 513         u32 rb_cntl, ib_cntl;
 514         int i;
 515
 516         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 517             (adev->mman.buffer_funcs_ring == sdma1))
 518                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 519
 520         for (i = 0; i < adev->sdma.num_instances; i++) {
 521                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 522                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 523                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 524                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 525                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 526                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 527         }
 528         sdma0->ready = false;
 529         sdma1->ready = false;
 530 }
 531
 532 /**
 533  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 534  *
 535  * @adev: amdgpu_device pointer
 536  *
 537  * Stop the compute async dma queues (VI).
 538  */
 539 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 540 {
 541         /* XXX todo */
 542 }
 543
 544 /**
 545  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 546  *
 547  * @adev: amdgpu_device pointer
 548  * @enable: enable/disable the DMA MEs context switch.
 549  *
 550  * Halt or unhalt the async dma engines context switch (VI).
 551  */
 552 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 553 {
 554         u32 f32_cntl, phase_quantum = 0;
 555         int i;
 556
 557         if (amdgpu_sdma_phase_quantum) {
 558                 unsigned value = amdgpu_sdma_phase_quantum;
 559                 unsigned unit = 0;
 560
 561                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 562                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 563                         value = (value + 1) >> 1;
 564                         unit++;
 565                 }
 566                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 567                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 568                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 569                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 570                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 571                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 572                         WARN_ONCE(1,
 573                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 574                                   value << unit);
 575                 }
 576                 phase_quantum =
 577                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 578                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 579         }
 580
 581         for (i = 0; i < adev->sdma.num_instances; i++) {
 582                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 583                 if (enable) {
 584                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 585                                         AUTO_CTXSW_ENABLE, 1);
 586                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 587                                         ATC_L1_ENABLE, 1);
 588                         if (amdgpu_sdma_phase_quantum) {
 589                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 590                                        phase_quantum);
 591                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 592                                        phase_quantum);
 593                         }
 594                 } else {
 595                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 596                                         AUTO_CTXSW_ENABLE, 0);
 597                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 598                                         ATC_L1_ENABLE, 1);
 599                 }
 600
 601                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 602         }
 603 }
 604
 605 /**
 606  * sdma_v3_0_enable - stop the async dma engines
 607  *
 608  * @adev: amdgpu_device pointer
 609  * @enable: enable/disable the DMA MEs.
 610  *
 611  * Halt or unhalt the async dma engines (VI).
 612  */
 613 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 614 {
 615         u32 f32_cntl;
 616         int i;
 617
 618         if (!enable) {
 619                 sdma_v3_0_gfx_stop(adev);
 620                 sdma_v3_0_rlc_stop(adev);
 621         }
 622
 623         for (i = 0; i < adev->sdma.num_instances; i++) {
 624                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 625                 if (enable)
 626                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 627                 else
 628                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 629                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 630         }
 631 }
 632
 633 /**
 634  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 635  *
 636  * @adev: amdgpu_device pointer
 637  *
 638  * Set up the gfx DMA ring buffers and enable them (VI).
 639  * Returns 0 for success, error for failure.
 640  */
 641 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 642 {
 643         struct amdgpu_ring *ring;
 644         u32 rb_cntl, ib_cntl;
 645         u32 rb_bufsz;
 646         u32 wb_offset;
 647         u32 doorbell;
 648         int i, j, r;
 649
 650         for (i = 0; i < adev->sdma.num_instances; i++) {
 651                 ring = &adev->sdma.instance[i].ring;
 652                 amdgpu_ring_clear_ring(ring);
 653                 wb_offset = (ring->rptr_offs * 4);
 654
 655                 mutex_lock(&adev->srbm_mutex);
 656                 for (j = 0; j < 16; j++) {
 657                         vi_srbm_select(adev, 0, 0, 0, j);
 658                         /* SDMA GFX */
 659                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 660                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 661                 }
 662                 vi_srbm_select(adev, 0, 0, 0, 0);
 663                 mutex_unlock(&adev->srbm_mutex);
 664
 665                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 666                        adev->gfx.config.gb_addr_config & 0x70);
 667
 668                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 669
 670                 /* Set ring buffer size in dwords */
 671                 rb_bufsz = order_base_2(ring->ring_size / 4);
 672                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 673                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 674 #ifdef __BIG_ENDIAN
 675                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 676                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 677                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 678 #endif
 679                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 680
 681                 /* Initialize the ring buffer's read and write pointers */
 682                 ring->wptr = 0;
 683                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 684                 sdma_v3_0_ring_set_wptr(ring);
 685                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 686                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 687
 688                 /* set the wb address whether it's enabled or not */
 689                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 690                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 691                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 692                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 693
 694                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 695
 696                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 697                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 698
 699                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 700
 701                 if (ring->use_doorbell) {
 702                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 703                                                  OFFSET, ring->doorbell_index);
 704                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 705                 } else {
 706                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 707                 }
 708                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 709
 710                 /* enable DMA RB */
 711                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 712                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 713
 714                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 715                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 716 #ifdef __BIG_ENDIAN
 717                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 718 #endif
 719                 /* enable DMA IBs */
 720                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 721
 722                 ring->ready = true;
 723         }
 724
 725         /* unhalt the MEs */
 726         sdma_v3_0_enable(adev, true);
 727         /* enable sdma ring preemption */
 728         sdma_v3_0_ctx_switch_enable(adev, true);
 729
 730         for (i = 0; i < adev->sdma.num_instances; i++) {
 731                 ring = &adev->sdma.instance[i].ring;
 732                 r = amdgpu_ring_test_ring(ring);
 733                 if (r) {
 734                         ring->ready = false;
 735                         return r;
 736                 }
 737
 738                 if (adev->mman.buffer_funcs_ring == ring)
 739                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 740         }
 741
 742         return 0;
 743 }
 744
 745 /**
 746  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 747  *
 748  * @adev: amdgpu_device pointer
 749  *
 750  * Set up the compute DMA queues and enable them (VI).
 751  * Returns 0 for success, error for failure.
 752  */
 753 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 754 {
 755         /* XXX todo */
 756         return 0;
 757 }
 758
 759 /**
 760  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 761  *
 762  * @adev: amdgpu_device pointer
 763  *
 764  * Loads the sDMA0/1 ucode.
 765  * Returns 0 for success, -EINVAL if the ucode is not available.
 766  */
 767 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 768 {
 769         const struct sdma_firmware_header_v1_0 *hdr;
 770         const __le32 *fw_data;
 771         u32 fw_size;
 772         int i, j;
 773
 774         /* halt the MEs */
 775         sdma_v3_0_enable(adev, false);
 776
 777         for (i = 0; i < adev->sdma.num_instances; i++) {
 778                 if (!adev->sdma.instance[i].fw)
 779                         return -EINVAL;
 780                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 781                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 782                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 783                 fw_data = (const __le32 *)
 784                         (adev->sdma.instance[i].fw->data +
 785                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 786                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 787                 for (j = 0; j < fw_size; j++)
 788                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 789                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 790         }
 791
 792         return 0;
 793 }
 794
 795 /**
 796  * sdma_v3_0_start - setup and start the async dma engines
 797  *
 798  * @adev: amdgpu_device pointer
 799  *
 800  * Set up the DMA engines and enable them (VI).
 801  * Returns 0 for success, error for failure.
 802  */
 803 static int sdma_v3_0_start(struct amdgpu_device *adev)
 804 {
 805         int r, i;
 806
 807         if (!adev->pp_enabled) {
 808                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
 809                         r = sdma_v3_0_load_microcode(adev);
 810                         if (r)
 811                                 return r;
 812                 } else {
 813                         for (i = 0; i < adev->sdma.num_instances; i++) {
 814                                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 815                                                                                  (i == 0) ?
 816                                                                                  AMDGPU_UCODE_ID_SDMA0 :
 817                                                                                  AMDGPU_UCODE_ID_SDMA1);
 818                                 if (r)
 819                                         return -EINVAL;
 820                         }
 821                 }
 822         }
 823
 824         /* disable sdma engine before programing it */
 825         sdma_v3_0_ctx_switch_enable(adev, false);
 826         sdma_v3_0_enable(adev, false);
 827
 828         /* start the gfx rings and rlc compute queues */
 829         r = sdma_v3_0_gfx_resume(adev);
 830         if (r)
 831                 return r;
 832         r = sdma_v3_0_rlc_resume(adev);
 833         if (r)
 834                 return r;
 835
 836         return 0;
 837 }
 838
 839 /**
 840  * sdma_v3_0_ring_test_ring - simple async dma engine test
 841  *
 842  * @ring: amdgpu_ring structure holding ring information
 843  *
 844  * Test the DMA engine by writing using it to write an
 845  * value to memory. (VI).
 846  * Returns 0 for success, error for failure.
 847  */
 848 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 849 {
 850         struct amdgpu_device *adev = ring->adev;
 851         unsigned i;
 852         unsigned index;
 853         int r;
 854         u32 tmp;
 855         u64 gpu_addr;
 856
 857         r = amdgpu_wb_get(adev, &index);
 858         if (r) {
 859                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 860                 return r;
 861         }
 862
 863         gpu_addr = adev->wb.gpu_addr + (index * 4);
 864         tmp = 0xCAFEDEAD;
 865         adev->wb.wb[index] = cpu_to_le32(tmp);
 866
 867         r = amdgpu_ring_alloc(ring, 5);
 868         if (r) {
 869                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 870                 amdgpu_wb_free(adev, index);
 871                 return r;
 872         }
 873
 874         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 875                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 876         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 877         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 878         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 879         amdgpu_ring_write(ring, 0xDEADBEEF);
 880         amdgpu_ring_commit(ring);
 881
 882         for (i = 0; i < adev->usec_timeout; i++) {
 883                 tmp = le32_to_cpu(adev->wb.wb[index]);
 884                 if (tmp == 0xDEADBEEF)
 885                         break;
 886                 DRM_UDELAY(1);
 887         }
 888
 889         if (i < adev->usec_timeout) {
 890                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 891         } else {
 892                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 893                           ring->idx, tmp);
 894                 r = -EINVAL;
 895         }
 896         amdgpu_wb_free(adev, index);
 897
 898         return r;
 899 }
 900
 901 /**
 902  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 903  *
 904  * @ring: amdgpu_ring structure holding ring information
 905  *
 906  * Test a simple IB in the DMA ring (VI).
 907  * Returns 0 on success, error on failure.
 908  */
 909 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 910 {
 911         struct amdgpu_device *adev = ring->adev;
 912         struct amdgpu_ib ib;
 913         struct dma_fence *f = NULL;
 914         unsigned index;
 915         u32 tmp = 0;
 916         u64 gpu_addr;
 917         long r;
 918
 919         r = amdgpu_wb_get(adev, &index);
 920         if (r) {
 921                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 922                 return r;
 923         }
 924
 925         gpu_addr = adev->wb.gpu_addr + (index * 4);
 926         tmp = 0xCAFEDEAD;
 927         adev->wb.wb[index] = cpu_to_le32(tmp);
 928         memset(&ib, 0, sizeof(ib));
 929         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 930         if (r) {
 931                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 932                 goto err0;
 933         }
 934
 935         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 936                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 937         ib.ptr[1] = lower_32_bits(gpu_addr);
 938         ib.ptr[2] = upper_32_bits(gpu_addr);
 939         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 940         ib.ptr[4] = 0xDEADBEEF;
 941         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 942         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 943         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 944         ib.length_dw = 8;
 945
 946         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 947         if (r)
 948                 goto err1;
 949
 950         r = dma_fence_wait_timeout(f, false, timeout);
 951         if (r == 0) {
 952                 DRM_ERROR("amdgpu: IB test timed out\n");
 953                 r = -ETIMEDOUT;
 954                 goto err1;
 955         } else if (r < 0) {
 956                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 957                 goto err1;
 958         }
 959         tmp = le32_to_cpu(adev->wb.wb[index]);
 960         if (tmp == 0xDEADBEEF) {
 961                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 962                 r = 0;
 963         } else {
 964                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 965                 r = -EINVAL;
 966         }
 967 err1:
 968         amdgpu_ib_free(adev, &ib, NULL);
 969         dma_fence_put(f);
 970 err0:
 971         amdgpu_wb_free(adev, index);
 972         return r;
 973 }
 974
 975 /**
 976  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 977  *
 978  * @ib: indirect buffer to fill with commands
 979  * @pe: addr of the page entry
 980  * @src: src addr to copy from
 981  * @count: number of page entries to update
 982  *
 983  * Update PTEs by copying them from the GART using sDMA (CIK).
 984  */
 985 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 986                                   uint64_t pe, uint64_t src,
 987                                   unsigned count)
 988 {
 989         unsigned bytes = count * 8;
 990
 991         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 992                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 993         ib->ptr[ib->length_dw++] = bytes;
 994         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 995         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 996         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 997         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 998         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 999 }
1000
1001 /**
1002  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1003  *
1004  * @ib: indirect buffer to fill with commands
1005  * @pe: addr of the page entry
1006  * @value: dst addr to write into pe
1007  * @count: number of page entries to update
1008  * @incr: increase next addr by incr bytes
1009  *
1010  * Update PTEs by writing them manually using sDMA (CIK).
1011  */
1012 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1013                                    uint64_t value, unsigned count,
1014                                    uint32_t incr)
1015 {
1016         unsigned ndw = count * 2;
1017
1018         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1019                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1020         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1021         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1022         ib->ptr[ib->length_dw++] = ndw;
1023         for (; ndw > 0; ndw -= 2) {
1024                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1025                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1026                 value += incr;
1027         }
1028 }
1029
1030 /**
1031  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1032  *
1033  * @ib: indirect buffer to fill with commands
1034  * @pe: addr of the page entry
1035  * @addr: dst addr to write into pe
1036  * @count: number of page entries to update
1037  * @incr: increase next addr by incr bytes
1038  * @flags: access flags
1039  *
1040  * Update the page tables using sDMA (CIK).
1041  */
1042 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1043                                      uint64_t addr, unsigned count,
1044                                      uint32_t incr, uint64_t flags)
1045 {
1046         /* for physically contiguous pages (vram) */
1047         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1048         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1049         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1050         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1051         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1052         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1053         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1054         ib->ptr[ib->length_dw++] = incr; /* increment size */
1055         ib->ptr[ib->length_dw++] = 0;
1056         ib->ptr[ib->length_dw++] = count; /* number of entries */
1057 }
1058
1059 /**
1060  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1061  *
1062  * @ib: indirect buffer to fill with padding
1063  *
1064  */
1065 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1066 {
1067         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1068         u32 pad_count;
1069         int i;
1070
1071         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1072         for (i = 0; i < pad_count; i++)
1073                 if (sdma && sdma->burst_nop && (i == 0))
1074                         ib->ptr[ib->length_dw++] =
1075                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1076                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1077                 else
1078                         ib->ptr[ib->length_dw++] =
1079                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1080 }
1081
1082 /**
1083  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1084  *
1085  * @ring: amdgpu_ring pointer
1086  *
1087  * Make sure all previous operations are completed (CIK).
1088  */
1089 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1090 {
1091         uint32_t seq = ring->fence_drv.sync_seq;
1092         uint64_t addr = ring->fence_drv.gpu_addr;
1093
1094         /* wait for idle */
1095         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1096                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1097                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1098                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1099         amdgpu_ring_write(ring, addr & 0xfffffffc);
1100         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1101         amdgpu_ring_write(ring, seq); /* reference */
1102         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1103         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1104                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1105 }
1106
1107 /**
1108  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1109  *
1110  * @ring: amdgpu_ring pointer
1111  * @vm: amdgpu_vm pointer
1112  *
1113  * Update the page table base and flush the VM TLB
1114  * using sDMA (VI).
1115  */
1116 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1117                                          unsigned vm_id, uint64_t pd_addr)
1118 {
1119         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1120                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1121         if (vm_id < 8) {
1122                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1123         } else {
1124                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1125         }
1126         amdgpu_ring_write(ring, pd_addr >> 12);
1127
1128         /* flush TLB */
1129         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1130                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1131         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1132         amdgpu_ring_write(ring, 1 << vm_id);
1133
1134         /* wait for flush */
1135         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1136                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1137                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1138         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1139         amdgpu_ring_write(ring, 0);
1140         amdgpu_ring_write(ring, 0); /* reference */
1141         amdgpu_ring_write(ring, 0); /* mask */
1142         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1143                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1144 }
1145
1146 static int sdma_v3_0_early_init(void *handle)
1147 {
1148         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1149
1150         switch (adev->asic_type) {
1151         case CHIP_STONEY:
1152                 adev->sdma.num_instances = 1;
1153                 break;
1154         default:
1155                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1156                 break;
1157         }
1158
1159         sdma_v3_0_set_ring_funcs(adev);
1160         sdma_v3_0_set_buffer_funcs(adev);
1161         sdma_v3_0_set_vm_pte_funcs(adev);
1162         sdma_v3_0_set_irq_funcs(adev);
1163
1164         return 0;
1165 }
1166
1167 static int sdma_v3_0_sw_init(void *handle)
1168 {
1169         struct amdgpu_ring *ring;
1170         int r, i;
1171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172
1173         /* SDMA trap event */
1174         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
1175                               &adev->sdma.trap_irq);
1176         if (r)
1177                 return r;
1178
1179         /* SDMA Privileged inst */
1180         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
1181                               &adev->sdma.illegal_inst_irq);
1182         if (r)
1183                 return r;
1184
1185         /* SDMA Privileged inst */
1186         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
1187                               &adev->sdma.illegal_inst_irq);
1188         if (r)
1189                 return r;
1190
1191         r = sdma_v3_0_init_microcode(adev);
1192         if (r) {
1193                 DRM_ERROR("Failed to load sdma firmware!\n");
1194                 return r;
1195         }
1196
1197         for (i = 0; i < adev->sdma.num_instances; i++) {
1198                 ring = &adev->sdma.instance[i].ring;
1199                 ring->ring_obj = NULL;
1200                 ring->use_doorbell = true;
1201                 ring->doorbell_index = (i == 0) ?
1202                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1203
1204                 sprintf(ring->name, "sdma%d", i);
1205                 r = amdgpu_ring_init(adev, ring, 1024,
1206                                      &adev->sdma.trap_irq,
1207                                      (i == 0) ?
1208                                      AMDGPU_SDMA_IRQ_TRAP0 :
1209                                      AMDGPU_SDMA_IRQ_TRAP1);
1210                 if (r)
1211                         return r;
1212         }
1213
1214         return r;
1215 }
1216
1217 static int sdma_v3_0_sw_fini(void *handle)
1218 {
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220         int i;
1221
1222         for (i = 0; i < adev->sdma.num_instances; i++)
1223                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1224
1225         sdma_v3_0_free_microcode(adev);
1226         return 0;
1227 }
1228
1229 static int sdma_v3_0_hw_init(void *handle)
1230 {
1231         int r;
1232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233
1234         sdma_v3_0_init_golden_registers(adev);
1235
1236         r = sdma_v3_0_start(adev);
1237         if (r)
1238                 return r;
1239
1240         return r;
1241 }
1242
1243 static int sdma_v3_0_hw_fini(void *handle)
1244 {
1245         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1246
1247         sdma_v3_0_ctx_switch_enable(adev, false);
1248         sdma_v3_0_enable(adev, false);
1249
1250         return 0;
1251 }
1252
1253 static int sdma_v3_0_suspend(void *handle)
1254 {
1255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256
1257         return sdma_v3_0_hw_fini(adev);
1258 }
1259
1260 static int sdma_v3_0_resume(void *handle)
1261 {
1262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263
1264         return sdma_v3_0_hw_init(adev);
1265 }
1266
1267 static bool sdma_v3_0_is_idle(void *handle)
1268 {
1269         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270         u32 tmp = RREG32(mmSRBM_STATUS2);
1271
1272         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1273                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1274             return false;
1275
1276         return true;
1277 }
1278
1279 static int sdma_v3_0_wait_for_idle(void *handle)
1280 {
1281         unsigned i;
1282         u32 tmp;
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284
1285         for (i = 0; i < adev->usec_timeout; i++) {
1286                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1287                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1288
1289                 if (!tmp)
1290                         return 0;
1291                 udelay(1);
1292         }
1293         return -ETIMEDOUT;
1294 }
1295
1296 static bool sdma_v3_0_check_soft_reset(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         u32 srbm_soft_reset = 0;
1300         u32 tmp = RREG32(mmSRBM_STATUS2);
1301
1302         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1303             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1304                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1305                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1306         }
1307
1308         if (srbm_soft_reset) {
1309                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1310                 return true;
1311         } else {
1312                 adev->sdma.srbm_soft_reset = 0;
1313                 return false;
1314         }
1315 }
1316
1317 static int sdma_v3_0_pre_soft_reset(void *handle)
1318 {
1319         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320         u32 srbm_soft_reset = 0;
1321
1322         if (!adev->sdma.srbm_soft_reset)
1323                 return 0;
1324
1325         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1326
1327         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1328             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1329                 sdma_v3_0_ctx_switch_enable(adev, false);
1330                 sdma_v3_0_enable(adev, false);
1331         }
1332
1333         return 0;
1334 }
1335
1336 static int sdma_v3_0_post_soft_reset(void *handle)
1337 {
1338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339         u32 srbm_soft_reset = 0;
1340
1341         if (!adev->sdma.srbm_soft_reset)
1342                 return 0;
1343
1344         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1345
1346         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1347             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1348                 sdma_v3_0_gfx_resume(adev);
1349                 sdma_v3_0_rlc_resume(adev);
1350         }
1351
1352         return 0;
1353 }
1354
1355 static int sdma_v3_0_soft_reset(void *handle)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358         u32 srbm_soft_reset = 0;
1359         u32 tmp;
1360
1361         if (!adev->sdma.srbm_soft_reset)
1362                 return 0;
1363
1364         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1365
1366         if (srbm_soft_reset) {
1367                 tmp = RREG32(mmSRBM_SOFT_RESET);
1368                 tmp |= srbm_soft_reset;
1369                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1370                 WREG32(mmSRBM_SOFT_RESET, tmp);
1371                 tmp = RREG32(mmSRBM_SOFT_RESET);
1372
1373                 udelay(50);
1374
1375                 tmp &= ~srbm_soft_reset;
1376                 WREG32(mmSRBM_SOFT_RESET, tmp);
1377                 tmp = RREG32(mmSRBM_SOFT_RESET);
1378
1379                 /* Wait a little for things to settle down */
1380                 udelay(50);
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1387                                         struct amdgpu_irq_src *source,
1388                                         unsigned type,
1389                                         enum amdgpu_interrupt_state state)
1390 {
1391         u32 sdma_cntl;
1392
1393         switch (type) {
1394         case AMDGPU_SDMA_IRQ_TRAP0:
1395                 switch (state) {
1396                 case AMDGPU_IRQ_STATE_DISABLE:
1397                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1398                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1399                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1400                         break;
1401                 case AMDGPU_IRQ_STATE_ENABLE:
1402                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1403                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1404                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1405                         break;
1406                 default:
1407                         break;
1408                 }
1409                 break;
1410         case AMDGPU_SDMA_IRQ_TRAP1:
1411                 switch (state) {
1412                 case AMDGPU_IRQ_STATE_DISABLE:
1413                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1414                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1415                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1416                         break;
1417                 case AMDGPU_IRQ_STATE_ENABLE:
1418                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1419                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1420                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1421                         break;
1422                 default:
1423                         break;
1424                 }
1425                 break;
1426         default:
1427                 break;
1428         }
1429         return 0;
1430 }
1431
1432 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1433                                       struct amdgpu_irq_src *source,
1434                                       struct amdgpu_iv_entry *entry)
1435 {
1436         u8 instance_id, queue_id;
1437
1438         instance_id = (entry->ring_id & 0x3) >> 0;
1439         queue_id = (entry->ring_id & 0xc) >> 2;
1440         DRM_DEBUG("IH: SDMA trap\n");
1441         switch (instance_id) {
1442         case 0:
1443                 switch (queue_id) {
1444                 case 0:
1445                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1446                         break;
1447                 case 1:
1448                         /* XXX compute */
1449                         break;
1450                 case 2:
1451                         /* XXX compute */
1452                         break;
1453                 }
1454                 break;
1455         case 1:
1456                 switch (queue_id) {
1457                 case 0:
1458                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1459                         break;
1460                 case 1:
1461                         /* XXX compute */
1462                         break;
1463                 case 2:
1464                         /* XXX compute */
1465                         break;
1466                 }
1467                 break;
1468         }
1469         return 0;
1470 }
1471
1472 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1473                                               struct amdgpu_irq_src *source,
1474                                               struct amdgpu_iv_entry *entry)
1475 {
1476         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1477         schedule_work(&adev->reset_work);
1478         return 0;
1479 }
1480
1481 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1482                 struct amdgpu_device *adev,
1483                 bool enable)
1484 {
1485         uint32_t temp, data;
1486         int i;
1487
1488         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1489                 for (i = 0; i < adev->sdma.num_instances; i++) {
1490                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1491                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1492                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1493                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1494                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1495                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1496                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1497                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1498                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1499                         if (data != temp)
1500                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1501                 }
1502         } else {
1503                 for (i = 0; i < adev->sdma.num_instances; i++) {
1504                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1505                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1506                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1507                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1508                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1509                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1510                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1511                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1512                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1513
1514                         if (data != temp)
1515                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1516                 }
1517         }
1518 }
1519
1520 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1521                 struct amdgpu_device *adev,
1522                 bool enable)
1523 {
1524         uint32_t temp, data;
1525         int i;
1526
1527         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1528                 for (i = 0; i < adev->sdma.num_instances; i++) {
1529                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1530                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1531
1532                         if (temp != data)
1533                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1534                 }
1535         } else {
1536                 for (i = 0; i < adev->sdma.num_instances; i++) {
1537                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1538                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1539
1540                         if (temp != data)
1541                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1542                 }
1543         }
1544 }
1545
1546 static int sdma_v3_0_set_clockgating_state(void *handle,
1547                                           enum amd_clockgating_state state)
1548 {
1549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1550
1551         if (amdgpu_sriov_vf(adev))
1552                 return 0;
1553
1554         switch (adev->asic_type) {
1555         case CHIP_FIJI:
1556         case CHIP_CARRIZO:
1557         case CHIP_STONEY:
1558                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1559                                 state == AMD_CG_STATE_GATE);
1560                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1561                                 state == AMD_CG_STATE_GATE);
1562                 break;
1563         default:
1564                 break;
1565         }
1566         return 0;
1567 }
1568
1569 static int sdma_v3_0_set_powergating_state(void *handle,
1570                                           enum amd_powergating_state state)
1571 {
1572         return 0;
1573 }
1574
1575 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1576 {
1577         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1578         int data;
1579
1580         if (amdgpu_sriov_vf(adev))
1581                 *flags = 0;
1582
1583         /* AMD_CG_SUPPORT_SDMA_MGCG */
1584         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1585         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1586                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1587
1588         /* AMD_CG_SUPPORT_SDMA_LS */
1589         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1590         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1591                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1592 }
1593
1594 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1595         .name = "sdma_v3_0",
1596         .early_init = sdma_v3_0_early_init,
1597         .late_init = NULL,
1598         .sw_init = sdma_v3_0_sw_init,
1599         .sw_fini = sdma_v3_0_sw_fini,
1600         .hw_init = sdma_v3_0_hw_init,
1601         .hw_fini = sdma_v3_0_hw_fini,
1602         .suspend = sdma_v3_0_suspend,
1603         .resume = sdma_v3_0_resume,
1604         .is_idle = sdma_v3_0_is_idle,
1605         .wait_for_idle = sdma_v3_0_wait_for_idle,
1606         .check_soft_reset = sdma_v3_0_check_soft_reset,
1607         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1608         .post_soft_reset = sdma_v3_0_post_soft_reset,
1609         .soft_reset = sdma_v3_0_soft_reset,
1610         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1611         .set_powergating_state = sdma_v3_0_set_powergating_state,
1612         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1613 };
1614
1615 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1616         .type = AMDGPU_RING_TYPE_SDMA,
1617         .align_mask = 0xf,
1618         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1619         .support_64bit_ptrs = false,
1620         .get_rptr = sdma_v3_0_ring_get_rptr,
1621         .get_wptr = sdma_v3_0_ring_get_wptr,
1622         .set_wptr = sdma_v3_0_ring_set_wptr,
1623         .emit_frame_size =
1624                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1625                 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
1626                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1627                 12 + /* sdma_v3_0_ring_emit_vm_flush */
1628                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1629         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1630         .emit_ib = sdma_v3_0_ring_emit_ib,
1631         .emit_fence = sdma_v3_0_ring_emit_fence,
1632         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1633         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1634         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1635         .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1636         .test_ring = sdma_v3_0_ring_test_ring,
1637         .test_ib = sdma_v3_0_ring_test_ib,
1638         .insert_nop = sdma_v3_0_ring_insert_nop,
1639         .pad_ib = sdma_v3_0_ring_pad_ib,
1640 };
1641
1642 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1643 {
1644         int i;
1645
1646         for (i = 0; i < adev->sdma.num_instances; i++)
1647                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1648 }
1649
1650 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1651         .set = sdma_v3_0_set_trap_irq_state,
1652         .process = sdma_v3_0_process_trap_irq,
1653 };
1654
1655 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1656         .process = sdma_v3_0_process_illegal_inst_irq,
1657 };
1658
1659 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1660 {
1661         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1662         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1663         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1664 }
1665
1666 /**
1667  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1668  *
1669  * @ring: amdgpu_ring structure holding ring information
1670  * @src_offset: src GPU address
1671  * @dst_offset: dst GPU address
1672  * @byte_count: number of bytes to xfer
1673  *
1674  * Copy GPU buffers using the DMA engine (VI).
1675  * Used by the amdgpu ttm implementation to move pages if
1676  * registered as the asic copy callback.
1677  */
1678 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1679                                        uint64_t src_offset,
1680                                        uint64_t dst_offset,
1681                                        uint32_t byte_count)
1682 {
1683         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1684                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1685         ib->ptr[ib->length_dw++] = byte_count;
1686         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1687         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1688         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1689         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1690         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1691 }
1692
1693 /**
1694  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1695  *
1696  * @ring: amdgpu_ring structure holding ring information
1697  * @src_data: value to write to buffer
1698  * @dst_offset: dst GPU address
1699  * @byte_count: number of bytes to xfer
1700  *
1701  * Fill GPU buffers using the DMA engine (VI).
1702  */
1703 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1704                                        uint32_t src_data,
1705                                        uint64_t dst_offset,
1706                                        uint32_t byte_count)
1707 {
1708         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1709         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1710         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1711         ib->ptr[ib->length_dw++] = src_data;
1712         ib->ptr[ib->length_dw++] = byte_count;
1713 }
1714
1715 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1716         .copy_max_bytes = 0x1fffff,
1717         .copy_num_dw = 7,
1718         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1719
1720         .fill_max_bytes = 0x1fffff,
1721         .fill_num_dw = 5,
1722         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1723 };
1724
1725 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1726 {
1727         if (adev->mman.buffer_funcs == NULL) {
1728                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1729                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1730         }
1731 }
1732
1733 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1734         .copy_pte = sdma_v3_0_vm_copy_pte,
1735         .write_pte = sdma_v3_0_vm_write_pte,
1736         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1737 };
1738
1739 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1740 {
1741         unsigned i;
1742
1743         if (adev->vm_manager.vm_pte_funcs == NULL) {
1744                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1745                 for (i = 0; i < adev->sdma.num_instances; i++)
1746                         adev->vm_manager.vm_pte_rings[i] =
1747                                 &adev->sdma.instance[i].ring;
1748
1749                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1750         }
1751 }
1752
1753 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1754 {
1755         .type = AMD_IP_BLOCK_TYPE_SDMA,
1756         .major = 3,
1757         .minor = 0,
1758         .rev = 0,
1759         .funcs = &sdma_v3_0_ip_funcs,
1760 };
1761
1762 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1763 {
1764         .type = AMD_IP_BLOCK_TYPE_SDMA,
1765         .major = 3,
1766         .minor = 1,
1767         .rev = 0,
1768         .funcs = &sdma_v3_0_ip_funcs,
1769 };