drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  56
  57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  58 {
  59         SDMA0_REGISTER_OFFSET,
  60         SDMA1_REGISTER_OFFSET
  61 };
  62
  63 static const u32 golden_settings_iceland_a11[] =
  64 {
  65         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  67         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  68         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  69 };
  70
  71 static const u32 iceland_mgcg_cgcg_init[] =
  72 {
  73         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  74         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  75 };
  76
  77 /*
  78  * sDMA - System DMA
  79  * Starting with CIK, the GPU has new asynchronous
  80  * DMA engines.  These engines are used for compute
  81  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  82  * and each one supports 1 ring buffer used for gfx
  83  * and 2 queues used for compute.
  84  *
  85  * The programming model is very similar to the CP
  86  * (ring buffer, IBs, etc.), but sDMA has it's own
  87  * packet format that is different from the PM4 format
  88  * used by the CP. sDMA supports copying data, writing
  89  * embedded data, solid fills, and a number of other
  90  * things.  It also has support for tiling/detiling of
  91  * buffers.
  92  */
  93
  94 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  95 {
  96         switch (adev->asic_type) {
  97         case CHIP_TOPAZ:
  98                 amdgpu_device_program_register_sequence(adev,
  99                                                         iceland_mgcg_cgcg_init,
 100                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 101                 amdgpu_device_program_register_sequence(adev,
 102                                                         golden_settings_iceland_a11,
 103                                                         ARRAY_SIZE(golden_settings_iceland_a11));
 104                 break;
 105         default:
 106                 break;
 107         }
 108 }
 109
 110 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 111 {
 112         int i;
 113         for (i = 0; i < adev->sdma.num_instances; i++) {
 114                 release_firmware(adev->sdma.instance[i].fw);
 115                 adev->sdma.instance[i].fw = NULL;
 116         }
 117 }
 118
 119 /**
 120  * sdma_v2_4_init_microcode - load ucode images from disk
 121  *
 122  * @adev: amdgpu_device pointer
 123  *
 124  * Use the firmware interface to load the ucode images into
 125  * the driver (not loaded into hw).
 126  * Returns 0 on success, error on failure.
 127  */
 128 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 129 {
 130         const char *chip_name;
 131         char fw_name[30];
 132         int err = 0, i;
 133         struct amdgpu_firmware_info *info = NULL;
 134         const struct common_firmware_header *header = NULL;
 135         const struct sdma_firmware_header_v1_0 *hdr;
 136
 137         DRM_DEBUG("\n");
 138
 139         switch (adev->asic_type) {
 140         case CHIP_TOPAZ:
 141                 chip_name = "topaz";
 142                 break;
 143         default: BUG();
 144         }
 145
 146         for (i = 0; i < adev->sdma.num_instances; i++) {
 147                 if (i == 0)
 148                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 149                 else
 150                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 151                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 152                 if (err)
 153                         goto out;
 154                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 155                 if (err)
 156                         goto out;
 157                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 158                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 159                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 160                 if (adev->sdma.instance[i].feature_version >= 20)
 161                         adev->sdma.instance[i].burst_nop = true;
 162
 163                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 164                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 165                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 166                         info->fw = adev->sdma.instance[i].fw;
 167                         header = (const struct common_firmware_header *)info->fw->data;
 168                         adev->firmware.fw_size +=
 169                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 170                 }
 171         }
 172
 173 out:
 174         if (err) {
 175                 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
 176                 for (i = 0; i < adev->sdma.num_instances; i++) {
 177                         release_firmware(adev->sdma.instance[i].fw);
 178                         adev->sdma.instance[i].fw = NULL;
 179                 }
 180         }
 181         return err;
 182 }
 183
 184 /**
 185  * sdma_v2_4_ring_get_rptr - get the current read pointer
 186  *
 187  * @ring: amdgpu ring pointer
 188  *
 189  * Get the current rptr from the hardware (VI+).
 190  */
 191 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 192 {
 193         /* XXX check if swapping is necessary on BE */
 194         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 195 }
 196
 197 /**
 198  * sdma_v2_4_ring_get_wptr - get the current write pointer
 199  *
 200  * @ring: amdgpu ring pointer
 201  *
 202  * Get the current wptr from the hardware (VI+).
 203  */
 204 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 205 {
 206         struct amdgpu_device *adev = ring->adev;
 207         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 208
 209         return wptr;
 210 }
 211
 212 /**
 213  * sdma_v2_4_ring_set_wptr - commit the write pointer
 214  *
 215  * @ring: amdgpu ring pointer
 216  *
 217  * Write the wptr back to the hardware (VI+).
 218  */
 219 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 220 {
 221         struct amdgpu_device *adev = ring->adev;
 222
 223         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 224 }
 225
 226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 227 {
 228         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 229         int i;
 230
 231         for (i = 0; i < count; i++)
 232                 if (sdma && sdma->burst_nop && (i == 0))
 233                         amdgpu_ring_write(ring, ring->funcs->nop |
 234                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 235                 else
 236                         amdgpu_ring_write(ring, ring->funcs->nop);
 237 }
 238
 239 /**
 240  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 241  *
 242  * @ring: amdgpu ring pointer
 243  * @ib: IB object to schedule
 244  *
 245  * Schedule an IB in the DMA ring (VI).
 246  */
 247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 248                                    struct amdgpu_job *job,
 249                                    struct amdgpu_ib *ib,
 250                                    uint32_t flags)
 251 {
 252         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 253
 254         /* IB packet must end on a 8 DW boundary */
 255         sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 256
 257         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 258                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 259         /* base must be 32 byte aligned */
 260         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 261         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 262         amdgpu_ring_write(ring, ib->length_dw);
 263         amdgpu_ring_write(ring, 0);
 264         amdgpu_ring_write(ring, 0);
 265
 266 }
 267
 268 /**
 269  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 270  *
 271  * @ring: amdgpu ring pointer
 272  *
 273  * Emit an hdp flush packet on the requested DMA ring.
 274  */
 275 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 276 {
 277         u32 ref_and_mask = 0;
 278
 279         if (ring->me == 0)
 280                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 281         else
 282                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 283
 284         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 285                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 286                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 287         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 288         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 289         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 290         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 291         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 292                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 293 }
 294
 295 /**
 296  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 297  *
 298  * @ring: amdgpu ring pointer
 299  * @fence: amdgpu fence object
 300  *
 301  * Add a DMA fence packet to the ring to write
 302  * the fence seq number and DMA trap packet to generate
 303  * an interrupt if needed (VI).
 304  */
 305 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 306                                       unsigned flags)
 307 {
 308         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 309         /* write the fence */
 310         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 311         amdgpu_ring_write(ring, lower_32_bits(addr));
 312         amdgpu_ring_write(ring, upper_32_bits(addr));
 313         amdgpu_ring_write(ring, lower_32_bits(seq));
 314
 315         /* optionally write high bits as well */
 316         if (write64bit) {
 317                 addr += 4;
 318                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 319                 amdgpu_ring_write(ring, lower_32_bits(addr));
 320                 amdgpu_ring_write(ring, upper_32_bits(addr));
 321                 amdgpu_ring_write(ring, upper_32_bits(seq));
 322         }
 323
 324         /* generate an interrupt */
 325         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 326         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 327 }
 328
 329 /**
 330  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 331  *
 332  * @adev: amdgpu_device pointer
 333  *
 334  * Stop the gfx async dma ring buffers (VI).
 335  */
 336 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 337 {
 338         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 339         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 340         u32 rb_cntl, ib_cntl;
 341         int i;
 342
 343         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 344             (adev->mman.buffer_funcs_ring == sdma1))
 345                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 346
 347         for (i = 0; i < adev->sdma.num_instances; i++) {
 348                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 349                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 350                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 351                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 352                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 353                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 354         }
 355         sdma0->sched.ready = false;
 356         sdma1->sched.ready = false;
 357 }
 358
 359 /**
 360  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 361  *
 362  * @adev: amdgpu_device pointer
 363  *
 364  * Stop the compute async dma queues (VI).
 365  */
 366 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 367 {
 368         /* XXX todo */
 369 }
 370
 371 /**
 372  * sdma_v2_4_enable - stop the async dma engines
 373  *
 374  * @adev: amdgpu_device pointer
 375  * @enable: enable/disable the DMA MEs.
 376  *
 377  * Halt or unhalt the async dma engines (VI).
 378  */
 379 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 380 {
 381         u32 f32_cntl;
 382         int i;
 383
 384         if (!enable) {
 385                 sdma_v2_4_gfx_stop(adev);
 386                 sdma_v2_4_rlc_stop(adev);
 387         }
 388
 389         for (i = 0; i < adev->sdma.num_instances; i++) {
 390                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 391                 if (enable)
 392                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 393                 else
 394                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 395                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 396         }
 397 }
 398
 399 /**
 400  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 401  *
 402  * @adev: amdgpu_device pointer
 403  *
 404  * Set up the gfx DMA ring buffers and enable them (VI).
 405  * Returns 0 for success, error for failure.
 406  */
 407 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 408 {
 409         struct amdgpu_ring *ring;
 410         u32 rb_cntl, ib_cntl;
 411         u32 rb_bufsz;
 412         u32 wb_offset;
 413         int i, j, r;
 414
 415         for (i = 0; i < adev->sdma.num_instances; i++) {
 416                 ring = &adev->sdma.instance[i].ring;
 417                 wb_offset = (ring->rptr_offs * 4);
 418
 419                 mutex_lock(&adev->srbm_mutex);
 420                 for (j = 0; j < 16; j++) {
 421                         vi_srbm_select(adev, 0, 0, 0, j);
 422                         /* SDMA GFX */
 423                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 424                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 425                 }
 426                 vi_srbm_select(adev, 0, 0, 0, 0);
 427                 mutex_unlock(&adev->srbm_mutex);
 428
 429                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 430                        adev->gfx.config.gb_addr_config & 0x70);
 431
 432                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 433
 434                 /* Set ring buffer size in dwords */
 435                 rb_bufsz = order_base_2(ring->ring_size / 4);
 436                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 437                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 438 #ifdef __BIG_ENDIAN
 439                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 440                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 441                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 442 #endif
 443                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 444
 445                 /* Initialize the ring buffer's read and write pointers */
 446                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 447                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 448                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 449                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 450
 451                 /* set the wb address whether it's enabled or not */
 452                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 453                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 454                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 455                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 456
 457                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 458
 459                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 460                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 461
 462                 ring->wptr = 0;
 463                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 464
 465                 /* enable DMA RB */
 466                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 467                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 468
 469                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 470                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 471 #ifdef __BIG_ENDIAN
 472                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 473 #endif
 474                 /* enable DMA IBs */
 475                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 476
 477                 ring->sched.ready = true;
 478         }
 479
 480         sdma_v2_4_enable(adev, true);
 481         for (i = 0; i < adev->sdma.num_instances; i++) {
 482                 ring = &adev->sdma.instance[i].ring;
 483                 r = amdgpu_ring_test_helper(ring);
 484                 if (r)
 485                         return r;
 486
 487                 if (adev->mman.buffer_funcs_ring == ring)
 488                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 489         }
 490
 491         return 0;
 492 }
 493
 494 /**
 495  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 496  *
 497  * @adev: amdgpu_device pointer
 498  *
 499  * Set up the compute DMA queues and enable them (VI).
 500  * Returns 0 for success, error for failure.
 501  */
 502 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 503 {
 504         /* XXX todo */
 505         return 0;
 506 }
 507
 508
 509 /**
 510  * sdma_v2_4_start - setup and start the async dma engines
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Set up the DMA engines and enable them (VI).
 515  * Returns 0 for success, error for failure.
 516  */
 517 static int sdma_v2_4_start(struct amdgpu_device *adev)
 518 {
 519         int r;
 520
 521         /* halt the engine before programing */
 522         sdma_v2_4_enable(adev, false);
 523
 524         /* start the gfx rings and rlc compute queues */
 525         r = sdma_v2_4_gfx_resume(adev);
 526         if (r)
 527                 return r;
 528         r = sdma_v2_4_rlc_resume(adev);
 529         if (r)
 530                 return r;
 531
 532         return 0;
 533 }
 534
 535 /**
 536  * sdma_v2_4_ring_test_ring - simple async dma engine test
 537  *
 538  * @ring: amdgpu_ring structure holding ring information
 539  *
 540  * Test the DMA engine by writing using it to write an
 541  * value to memory. (VI).
 542  * Returns 0 for success, error for failure.
 543  */
 544 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 545 {
 546         struct amdgpu_device *adev = ring->adev;
 547         unsigned i;
 548         unsigned index;
 549         int r;
 550         u32 tmp;
 551         u64 gpu_addr;
 552
 553         r = amdgpu_device_wb_get(adev, &index);
 554         if (r)
 555                 return r;
 556
 557         gpu_addr = adev->wb.gpu_addr + (index * 4);
 558         tmp = 0xCAFEDEAD;
 559         adev->wb.wb[index] = cpu_to_le32(tmp);
 560
 561         r = amdgpu_ring_alloc(ring, 5);
 562         if (r)
 563                 goto error_free_wb;
 564
 565         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 566                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 567         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 568         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 569         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 570         amdgpu_ring_write(ring, 0xDEADBEEF);
 571         amdgpu_ring_commit(ring);
 572
 573         for (i = 0; i < adev->usec_timeout; i++) {
 574                 tmp = le32_to_cpu(adev->wb.wb[index]);
 575                 if (tmp == 0xDEADBEEF)
 576                         break;
 577                 DRM_UDELAY(1);
 578         }
 579
 580         if (i >= adev->usec_timeout)
 581                 r = -ETIMEDOUT;
 582
 583 error_free_wb:
 584         amdgpu_device_wb_free(adev, index);
 585         return r;
 586 }
 587
 588 /**
 589  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 590  *
 591  * @ring: amdgpu_ring structure holding ring information
 592  *
 593  * Test a simple IB in the DMA ring (VI).
 594  * Returns 0 on success, error on failure.
 595  */
 596 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 597 {
 598         struct amdgpu_device *adev = ring->adev;
 599         struct amdgpu_ib ib;
 600         struct dma_fence *f = NULL;
 601         unsigned index;
 602         u32 tmp = 0;
 603         u64 gpu_addr;
 604         long r;
 605
 606         r = amdgpu_device_wb_get(adev, &index);
 607         if (r)
 608                 return r;
 609
 610         gpu_addr = adev->wb.gpu_addr + (index * 4);
 611         tmp = 0xCAFEDEAD;
 612         adev->wb.wb[index] = cpu_to_le32(tmp);
 613         memset(&ib, 0, sizeof(ib));
 614         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 615         if (r)
 616                 goto err0;
 617
 618         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 619                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 620         ib.ptr[1] = lower_32_bits(gpu_addr);
 621         ib.ptr[2] = upper_32_bits(gpu_addr);
 622         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 623         ib.ptr[4] = 0xDEADBEEF;
 624         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 625         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 626         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 627         ib.length_dw = 8;
 628
 629         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 630         if (r)
 631                 goto err1;
 632
 633         r = dma_fence_wait_timeout(f, false, timeout);
 634         if (r == 0) {
 635                 r = -ETIMEDOUT;
 636                 goto err1;
 637         } else if (r < 0) {
 638                 goto err1;
 639         }
 640         tmp = le32_to_cpu(adev->wb.wb[index]);
 641         if (tmp == 0xDEADBEEF)
 642                 r = 0;
 643         else
 644                 r = -EINVAL;
 645
 646 err1:
 647         amdgpu_ib_free(adev, &ib, NULL);
 648         dma_fence_put(f);
 649 err0:
 650         amdgpu_device_wb_free(adev, index);
 651         return r;
 652 }
 653
 654 /**
 655  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 656  *
 657  * @ib: indirect buffer to fill with commands
 658  * @pe: addr of the page entry
 659  * @src: src addr to copy from
 660  * @count: number of page entries to update
 661  *
 662  * Update PTEs by copying them from the GART using sDMA (CIK).
 663  */
 664 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 665                                   uint64_t pe, uint64_t src,
 666                                   unsigned count)
 667 {
 668         unsigned bytes = count * 8;
 669
 670         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 671                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 672         ib->ptr[ib->length_dw++] = bytes;
 673         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 674         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 675         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 676         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 677         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 678 }
 679
 680 /**
 681  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 682  *
 683  * @ib: indirect buffer to fill with commands
 684  * @pe: addr of the page entry
 685  * @value: dst addr to write into pe
 686  * @count: number of page entries to update
 687  * @incr: increase next addr by incr bytes
 688  *
 689  * Update PTEs by writing them manually using sDMA (CIK).
 690  */
 691 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 692                                    uint64_t value, unsigned count,
 693                                    uint32_t incr)
 694 {
 695         unsigned ndw = count * 2;
 696
 697         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 698                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 699         ib->ptr[ib->length_dw++] = pe;
 700         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 701         ib->ptr[ib->length_dw++] = ndw;
 702         for (; ndw > 0; ndw -= 2) {
 703                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 704                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 705                 value += incr;
 706         }
 707 }
 708
 709 /**
 710  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 711  *
 712  * @ib: indirect buffer to fill with commands
 713  * @pe: addr of the page entry
 714  * @addr: dst addr to write into pe
 715  * @count: number of page entries to update
 716  * @incr: increase next addr by incr bytes
 717  * @flags: access flags
 718  *
 719  * Update the page tables using sDMA (CIK).
 720  */
 721 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 722                                      uint64_t addr, unsigned count,
 723                                      uint32_t incr, uint64_t flags)
 724 {
 725         /* for physically contiguous pages (vram) */
 726         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 727         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 728         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 729         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 730         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 731         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 732         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 733         ib->ptr[ib->length_dw++] = incr; /* increment size */
 734         ib->ptr[ib->length_dw++] = 0;
 735         ib->ptr[ib->length_dw++] = count; /* number of entries */
 736 }
 737
 738 /**
 739  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 740  *
 741  * @ib: indirect buffer to fill with padding
 742  *
 743  */
 744 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 745 {
 746         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 747         u32 pad_count;
 748         int i;
 749
 750         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 751         for (i = 0; i < pad_count; i++)
 752                 if (sdma && sdma->burst_nop && (i == 0))
 753                         ib->ptr[ib->length_dw++] =
 754                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 755                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 756                 else
 757                         ib->ptr[ib->length_dw++] =
 758                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 759 }
 760
 761 /**
 762  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 763  *
 764  * @ring: amdgpu_ring pointer
 765  *
 766  * Make sure all previous operations are completed (CIK).
 767  */
 768 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 769 {
 770         uint32_t seq = ring->fence_drv.sync_seq;
 771         uint64_t addr = ring->fence_drv.gpu_addr;
 772
 773         /* wait for idle */
 774         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 775                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 776                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 777                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 778         amdgpu_ring_write(ring, addr & 0xfffffffc);
 779         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 780         amdgpu_ring_write(ring, seq); /* reference */
 781         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 782         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 783                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 784 }
 785
 786 /**
 787  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 788  *
 789  * @ring: amdgpu_ring pointer
 790  * @vm: amdgpu_vm pointer
 791  *
 792  * Update the page table base and flush the VM TLB
 793  * using sDMA (VI).
 794  */
 795 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 796                                          unsigned vmid, uint64_t pd_addr)
 797 {
 798         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 799
 800         /* wait for flush */
 801         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 802                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 803                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 804         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 805         amdgpu_ring_write(ring, 0);
 806         amdgpu_ring_write(ring, 0); /* reference */
 807         amdgpu_ring_write(ring, 0); /* mask */
 808         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 809                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 810 }
 811
 812 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
 813                                      uint32_t reg, uint32_t val)
 814 {
 815         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 816                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 817         amdgpu_ring_write(ring, reg);
 818         amdgpu_ring_write(ring, val);
 819 }
 820
 821 static int sdma_v2_4_early_init(void *handle)
 822 {
 823         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 824
 825         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 826
 827         sdma_v2_4_set_ring_funcs(adev);
 828         sdma_v2_4_set_buffer_funcs(adev);
 829         sdma_v2_4_set_vm_pte_funcs(adev);
 830         sdma_v2_4_set_irq_funcs(adev);
 831
 832         return 0;
 833 }
 834
 835 static int sdma_v2_4_sw_init(void *handle)
 836 {
 837         struct amdgpu_ring *ring;
 838         int r, i;
 839         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 840
 841         /* SDMA trap event */
 842         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
 843                               &adev->sdma.trap_irq);
 844         if (r)
 845                 return r;
 846
 847         /* SDMA Privileged inst */
 848         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 849                               &adev->sdma.illegal_inst_irq);
 850         if (r)
 851                 return r;
 852
 853         /* SDMA Privileged inst */
 854         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
 855                               &adev->sdma.illegal_inst_irq);
 856         if (r)
 857                 return r;
 858
 859         r = sdma_v2_4_init_microcode(adev);
 860         if (r) {
 861                 DRM_ERROR("Failed to load sdma firmware!\n");
 862                 return r;
 863         }
 864
 865         for (i = 0; i < adev->sdma.num_instances; i++) {
 866                 ring = &adev->sdma.instance[i].ring;
 867                 ring->ring_obj = NULL;
 868                 ring->use_doorbell = false;
 869                 sprintf(ring->name, "sdma%d", i);
 870                 r = amdgpu_ring_init(adev, ring, 1024,
 871                                      &adev->sdma.trap_irq,
 872                                      (i == 0) ?
 873                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
 874                                      AMDGPU_SDMA_IRQ_INSTANCE1);
 875                 if (r)
 876                         return r;
 877         }
 878
 879         return r;
 880 }
 881
 882 static int sdma_v2_4_sw_fini(void *handle)
 883 {
 884         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 885         int i;
 886
 887         for (i = 0; i < adev->sdma.num_instances; i++)
 888                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 889
 890         sdma_v2_4_free_microcode(adev);
 891         return 0;
 892 }
 893
 894 static int sdma_v2_4_hw_init(void *handle)
 895 {
 896         int r;
 897         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 898
 899         sdma_v2_4_init_golden_registers(adev);
 900
 901         r = sdma_v2_4_start(adev);
 902         if (r)
 903                 return r;
 904
 905         return r;
 906 }
 907
 908 static int sdma_v2_4_hw_fini(void *handle)
 909 {
 910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 911
 912         sdma_v2_4_enable(adev, false);
 913
 914         return 0;
 915 }
 916
 917 static int sdma_v2_4_suspend(void *handle)
 918 {
 919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 920
 921         return sdma_v2_4_hw_fini(adev);
 922 }
 923
 924 static int sdma_v2_4_resume(void *handle)
 925 {
 926         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 927
 928         return sdma_v2_4_hw_init(adev);
 929 }
 930
 931 static bool sdma_v2_4_is_idle(void *handle)
 932 {
 933         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 934         u32 tmp = RREG32(mmSRBM_STATUS2);
 935
 936         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
 937                    SRBM_STATUS2__SDMA1_BUSY_MASK))
 938             return false;
 939
 940         return true;
 941 }
 942
 943 static int sdma_v2_4_wait_for_idle(void *handle)
 944 {
 945         unsigned i;
 946         u32 tmp;
 947         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 948
 949         for (i = 0; i < adev->usec_timeout; i++) {
 950                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
 951                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
 952
 953                 if (!tmp)
 954                         return 0;
 955                 udelay(1);
 956         }
 957         return -ETIMEDOUT;
 958 }
 959
 960 static int sdma_v2_4_soft_reset(void *handle)
 961 {
 962         u32 srbm_soft_reset = 0;
 963         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 964         u32 tmp = RREG32(mmSRBM_STATUS2);
 965
 966         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
 967                 /* sdma0 */
 968                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 969                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
 970                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 971                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
 972         }
 973         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
 974                 /* sdma1 */
 975                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 976                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
 977                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 978                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
 979         }
 980
 981         if (srbm_soft_reset) {
 982                 tmp = RREG32(mmSRBM_SOFT_RESET);
 983                 tmp |= srbm_soft_reset;
 984                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 985                 WREG32(mmSRBM_SOFT_RESET, tmp);
 986                 tmp = RREG32(mmSRBM_SOFT_RESET);
 987
 988                 udelay(50);
 989
 990                 tmp &= ~srbm_soft_reset;
 991                 WREG32(mmSRBM_SOFT_RESET, tmp);
 992                 tmp = RREG32(mmSRBM_SOFT_RESET);
 993
 994                 /* Wait a little for things to settle down */
 995                 udelay(50);
 996         }
 997
 998         return 0;
 999 }
1000
1001 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1002                                         struct amdgpu_irq_src *src,
1003                                         unsigned type,
1004                                         enum amdgpu_interrupt_state state)
1005 {
1006         u32 sdma_cntl;
1007
1008         switch (type) {
1009         case AMDGPU_SDMA_IRQ_INSTANCE0:
1010                 switch (state) {
1011                 case AMDGPU_IRQ_STATE_DISABLE:
1012                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1013                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1014                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1015                         break;
1016                 case AMDGPU_IRQ_STATE_ENABLE:
1017                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1018                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1019                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1020                         break;
1021                 default:
1022                         break;
1023                 }
1024                 break;
1025         case AMDGPU_SDMA_IRQ_INSTANCE1:
1026                 switch (state) {
1027                 case AMDGPU_IRQ_STATE_DISABLE:
1028                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1029                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1030                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1031                         break;
1032                 case AMDGPU_IRQ_STATE_ENABLE:
1033                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1034                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1035                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1036                         break;
1037                 default:
1038                         break;
1039                 }
1040                 break;
1041         default:
1042                 break;
1043         }
1044         return 0;
1045 }
1046
1047 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1048                                       struct amdgpu_irq_src *source,
1049                                       struct amdgpu_iv_entry *entry)
1050 {
1051         u8 instance_id, queue_id;
1052
1053         instance_id = (entry->ring_id & 0x3) >> 0;
1054         queue_id = (entry->ring_id & 0xc) >> 2;
1055         DRM_DEBUG("IH: SDMA trap\n");
1056         switch (instance_id) {
1057         case 0:
1058                 switch (queue_id) {
1059                 case 0:
1060                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1061                         break;
1062                 case 1:
1063                         /* XXX compute */
1064                         break;
1065                 case 2:
1066                         /* XXX compute */
1067                         break;
1068                 }
1069                 break;
1070         case 1:
1071                 switch (queue_id) {
1072                 case 0:
1073                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1074                         break;
1075                 case 1:
1076                         /* XXX compute */
1077                         break;
1078                 case 2:
1079                         /* XXX compute */
1080                         break;
1081                 }
1082                 break;
1083         }
1084         return 0;
1085 }
1086
1087 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1088                                               struct amdgpu_irq_src *source,
1089                                               struct amdgpu_iv_entry *entry)
1090 {
1091         u8 instance_id, queue_id;
1092
1093         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1094         instance_id = (entry->ring_id & 0x3) >> 0;
1095         queue_id = (entry->ring_id & 0xc) >> 2;
1096
1097         if (instance_id <= 1 && queue_id == 0)
1098                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1099         return 0;
1100 }
1101
1102 static int sdma_v2_4_set_clockgating_state(void *handle,
1103                                           enum amd_clockgating_state state)
1104 {
1105         /* XXX handled via the smc on VI */
1106         return 0;
1107 }
1108
1109 static int sdma_v2_4_set_powergating_state(void *handle,
1110                                           enum amd_powergating_state state)
1111 {
1112         return 0;
1113 }
1114
1115 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1116         .name = "sdma_v2_4",
1117         .early_init = sdma_v2_4_early_init,
1118         .late_init = NULL,
1119         .sw_init = sdma_v2_4_sw_init,
1120         .sw_fini = sdma_v2_4_sw_fini,
1121         .hw_init = sdma_v2_4_hw_init,
1122         .hw_fini = sdma_v2_4_hw_fini,
1123         .suspend = sdma_v2_4_suspend,
1124         .resume = sdma_v2_4_resume,
1125         .is_idle = sdma_v2_4_is_idle,
1126         .wait_for_idle = sdma_v2_4_wait_for_idle,
1127         .soft_reset = sdma_v2_4_soft_reset,
1128         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1129         .set_powergating_state = sdma_v2_4_set_powergating_state,
1130 };
1131
1132 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1133         .type = AMDGPU_RING_TYPE_SDMA,
1134         .align_mask = 0xf,
1135         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1136         .support_64bit_ptrs = false,
1137         .get_rptr = sdma_v2_4_ring_get_rptr,
1138         .get_wptr = sdma_v2_4_ring_get_wptr,
1139         .set_wptr = sdma_v2_4_ring_set_wptr,
1140         .emit_frame_size =
1141                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1142                 3 + /* hdp invalidate */
1143                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1144                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1145                 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1146         .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1147         .emit_ib = sdma_v2_4_ring_emit_ib,
1148         .emit_fence = sdma_v2_4_ring_emit_fence,
1149         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1150         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1151         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1152         .test_ring = sdma_v2_4_ring_test_ring,
1153         .test_ib = sdma_v2_4_ring_test_ib,
1154         .insert_nop = sdma_v2_4_ring_insert_nop,
1155         .pad_ib = sdma_v2_4_ring_pad_ib,
1156         .emit_wreg = sdma_v2_4_ring_emit_wreg,
1157 };
1158
1159 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1160 {
1161         int i;
1162
1163         for (i = 0; i < adev->sdma.num_instances; i++) {
1164                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1165                 adev->sdma.instance[i].ring.me = i;
1166         }
1167 }
1168
1169 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1170         .set = sdma_v2_4_set_trap_irq_state,
1171         .process = sdma_v2_4_process_trap_irq,
1172 };
1173
1174 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1175         .process = sdma_v2_4_process_illegal_inst_irq,
1176 };
1177
1178 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1179 {
1180         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1181         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1182         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1183 }
1184
1185 /**
1186  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1187  *
1188  * @ring: amdgpu_ring structure holding ring information
1189  * @src_offset: src GPU address
1190  * @dst_offset: dst GPU address
1191  * @byte_count: number of bytes to xfer
1192  *
1193  * Copy GPU buffers using the DMA engine (VI).
1194  * Used by the amdgpu ttm implementation to move pages if
1195  * registered as the asic copy callback.
1196  */
1197 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1198                                        uint64_t src_offset,
1199                                        uint64_t dst_offset,
1200                                        uint32_t byte_count)
1201 {
1202         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1203                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1204         ib->ptr[ib->length_dw++] = byte_count;
1205         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1206         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1207         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1208         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1209         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1210 }
1211
1212 /**
1213  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1214  *
1215  * @ring: amdgpu_ring structure holding ring information
1216  * @src_data: value to write to buffer
1217  * @dst_offset: dst GPU address
1218  * @byte_count: number of bytes to xfer
1219  *
1220  * Fill GPU buffers using the DMA engine (VI).
1221  */
1222 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1223                                        uint32_t src_data,
1224                                        uint64_t dst_offset,
1225                                        uint32_t byte_count)
1226 {
1227         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1228         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1229         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1230         ib->ptr[ib->length_dw++] = src_data;
1231         ib->ptr[ib->length_dw++] = byte_count;
1232 }
1233
1234 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1235         .copy_max_bytes = 0x1fffff,
1236         .copy_num_dw = 7,
1237         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1238
1239         .fill_max_bytes = 0x1fffff,
1240         .fill_num_dw = 7,
1241         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1242 };
1243
1244 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1245 {
1246         adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1247         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1248 }
1249
1250 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1251         .copy_pte_num_dw = 7,
1252         .copy_pte = sdma_v2_4_vm_copy_pte,
1253
1254         .write_pte = sdma_v2_4_vm_write_pte,
1255         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1256 };
1257
1258 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1259 {
1260         struct drm_gpu_scheduler *sched;
1261         unsigned i;
1262
1263         adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1264         for (i = 0; i < adev->sdma.num_instances; i++) {
1265                 sched = &adev->sdma.instance[i].ring.sched;
1266                 adev->vm_manager.vm_pte_rqs[i] =
1267                         &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1268         }
1269         adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
1270 }
1271
1272 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1273 {
1274         .type = AMD_IP_BLOCK_TYPE_SDMA,
1275         .major = 2,
1276         .minor = 4,
1277         .rev = 0,
1278         .funcs = &sdma_v2_4_ip_funcs,
1279 };