drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v11_0.h"
  31
  32 #include "mp/mp_11_0_offset.h"
  33 #include "mp/mp_11_0_sh_mask.h"
  34 #include "gc/gc_9_0_offset.h"
  35 #include "sdma0/sdma0_4_0_offset.h"
  36 #include "nbio/nbio_7_4_offset.h"
  37
  38 #include "oss/osssys_4_0_offset.h"
  39 #include "oss/osssys_4_0_sh_mask.h"
  40
  41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  49 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  50 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  52
  53 /* address block */
  54 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  55 /* navi10 reg offset define */
  56 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  57 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  58 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  59 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  60
  61 static int psp_v11_0_init_microcode(struct psp_context *psp)
  62 {
  63         struct amdgpu_device *adev = psp->adev;
  64         const char *chip_name;
  65         char fw_name[30];
  66         int err = 0;
  67         const struct psp_firmware_header_v1_0 *sos_hdr;
  68         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
  69         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
  70         const struct psp_firmware_header_v1_0 *asd_hdr;
  71         const struct ta_firmware_header_v1_0 *ta_hdr;
  72
  73         DRM_DEBUG("\n");
  74
  75         switch (adev->asic_type) {
  76         case CHIP_VEGA20:
  77                 chip_name = "vega20";
  78                 break;
  79         case CHIP_NAVI10:
  80                 chip_name = "navi10";
  81                 break;
  82         case CHIP_NAVI14:
  83                 chip_name = "navi14";
  84                 break;
  85         case CHIP_NAVI12:
  86                 chip_name = "navi12";
  87                 break;
  88         case CHIP_ARCTURUS:
  89                 chip_name = "arcturus";
  90                 break;
  91         default:
  92                 BUG();
  93         }
  94
  95         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  96         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
  97         if (err)
  98                 goto out;
  99
 100         err = amdgpu_ucode_validate(adev->psp.sos_fw);
 101         if (err)
 102                 goto out;
 103
 104         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
 105         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
 106
 107         switch (sos_hdr->header.header_version_major) {
 108         case 1:
 109                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
 110                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
 111                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
 112                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
 113                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
 114                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
 115                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 116                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
 117                 if (sos_hdr->header.header_version_minor == 1) {
 118                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
 119                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
 120                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 121                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
 122                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
 123                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 124                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
 125                 }
 126                 if (sos_hdr->header.header_version_minor == 2) {
 127                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
 128                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
 129                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 130                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
 131                 }
 132                 break;
 133         default:
 134                 dev_err(adev->dev,
 135                         "Unsupported psp sos firmware\n");
 136                 err = -EINVAL;
 137                 goto out;
 138         }
 139
 140         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 141         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 142         if (err)
 143                 goto out1;
 144
 145         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 146         if (err)
 147                 goto out1;
 148
 149         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 150         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
 151         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 152         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 153         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 154                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 155
 156         switch (adev->asic_type) {
 157         case CHIP_VEGA20:
 158                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 159                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 160                 if (err) {
 161                         release_firmware(adev->psp.ta_fw);
 162                         adev->psp.ta_fw = NULL;
 163                         dev_info(adev->dev,
 164                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 165                 } else {
 166                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 167                         if (err)
 168                                 goto out2;
 169
 170                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 171                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 172                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 173                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 174                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 175                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 176                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 177                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 178                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 179                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 180                 }
 181                 break;
 182         case CHIP_NAVI10:
 183         case CHIP_NAVI14:
 184         case CHIP_NAVI12:
 185         case CHIP_ARCTURUS:
 186                 break;
 187         default:
 188                 BUG();
 189         }
 190
 191         return 0;
 192
 193 out2:
 194         release_firmware(adev->psp.ta_fw);
 195         adev->psp.ta_fw = NULL;
 196 out1:
 197         release_firmware(adev->psp.asd_fw);
 198         adev->psp.asd_fw = NULL;
 199 out:
 200         dev_err(adev->dev,
 201                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 202         release_firmware(adev->psp.sos_fw);
 203         adev->psp.sos_fw = NULL;
 204
 205         return err;
 206 }
 207
 208 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 209 {
 210         int ret;
 211         uint32_t psp_gfxdrv_command_reg = 0;
 212         struct amdgpu_device *adev = psp->adev;
 213         uint32_t sol_reg;
 214
 215         /* Check tOS sign of life register to confirm sys driver and sOS
 216          * are already been loaded.
 217          */
 218         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 219         if (sol_reg) {
 220                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 221                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 222                 return 0;
 223         }
 224
 225         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 226         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 227                            0x80000000, 0x80000000, false);
 228         if (ret)
 229                 return ret;
 230
 231         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 232
 233         /* Copy PSP KDB binary to memory */
 234         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 235
 236         /* Provide the sys driver to bootloader */
 237         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 238                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 239         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 240         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 241                psp_gfxdrv_command_reg);
 242
 243         /* Wait for bootloader to signify that is ready having  bit 31 of C2PMSG_35 set to 1*/
 244         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 245                            0x80000000, 0x80000000, false);
 246
 247         return ret;
 248 }
 249
 250 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 251 {
 252         int ret;
 253         uint32_t psp_gfxdrv_command_reg = 0;
 254         struct amdgpu_device *adev = psp->adev;
 255         uint32_t sol_reg;
 256
 257         /* Check sOS sign of life register to confirm sys driver and sOS
 258          * are already been loaded.
 259          */
 260         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 261         if (sol_reg) {
 262                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 263                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 264                 return 0;
 265         }
 266
 267         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 268         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 269                            0x80000000, 0x80000000, false);
 270         if (ret)
 271                 return ret;
 272
 273         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 274
 275         /* Copy PSP System Driver binary to memory */
 276         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 277
 278         /* Provide the sys driver to bootloader */
 279         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 280                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 281         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 282         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 283                psp_gfxdrv_command_reg);
 284
 285         /* there might be handshake issue with hardware which needs delay */
 286         mdelay(20);
 287
 288         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 289                            0x80000000, 0x80000000, false);
 290
 291         return ret;
 292 }
 293
 294 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 295 {
 296         int ret;
 297         unsigned int psp_gfxdrv_command_reg = 0;
 298         struct amdgpu_device *adev = psp->adev;
 299         uint32_t sol_reg;
 300
 301         /* Check sOS sign of life register to confirm sys driver and sOS
 302          * are already been loaded.
 303          */
 304         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 305         if (sol_reg)
 306                 return 0;
 307
 308         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 309         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 310                            0x80000000, 0x80000000, false);
 311         if (ret)
 312                 return ret;
 313
 314         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 315
 316         /* Copy Secure OS binary to PSP memory */
 317         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 318
 319         /* Provide the PSP secure OS to bootloader */
 320         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 321                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 322         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 323         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 324                psp_gfxdrv_command_reg);
 325
 326         /* there might be handshake issue with hardware which needs delay */
 327         mdelay(20);
 328         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 329                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 330                            0, true);
 331
 332         return ret;
 333 }
 334
 335 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 336 {
 337         struct amdgpu_device *adev = psp->adev;
 338         uint32_t tmp;
 339
 340         /* Change IH ring for VMC */
 341         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 342         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 343         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 344
 345         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 346         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 347         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 348
 349         mdelay(20);
 350         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 351                      0x80000000, 0x8000FFFF, false);
 352
 353         /* Change IH ring for UMC */
 354         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 355         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 356
 357         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 358         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 359         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 360
 361         mdelay(20);
 362         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 363                      0x80000000, 0x8000FFFF, false);
 364 }
 365
 366 static int psp_v11_0_ring_init(struct psp_context *psp,
 367                               enum psp_ring_type ring_type)
 368 {
 369         int ret = 0;
 370         struct psp_ring *ring;
 371         struct amdgpu_device *adev = psp->adev;
 372
 373         psp_v11_0_reroute_ih(psp);
 374
 375         ring = &psp->km_ring;
 376
 377         ring->ring_type = ring_type;
 378
 379         /* allocate 4k Page of Local Frame Buffer memory for ring */
 380         ring->ring_size = 0x1000;
 381         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 382                                       AMDGPU_GEM_DOMAIN_VRAM,
 383                                       &adev->firmware.rbuf,
 384                                       &ring->ring_mem_mc_addr,
 385                                       (void **)&ring->ring_mem);
 386         if (ret) {
 387                 ring->ring_size = 0;
 388                 return ret;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 395 {
 396         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 397                 return true;
 398         return false;
 399 }
 400
 401 static int psp_v11_0_ring_create(struct psp_context *psp,
 402                                 enum psp_ring_type ring_type)
 403 {
 404         int ret = 0;
 405         unsigned int psp_ring_reg = 0;
 406         struct psp_ring *ring = &psp->km_ring;
 407         struct amdgpu_device *adev = psp->adev;
 408
 409         if (psp_v11_0_support_vmr_ring(psp)) {
 410                 /* Write low address of the ring to C2PMSG_102 */
 411                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 412                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 413                 /* Write high address of the ring to C2PMSG_103 */
 414                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 415                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 416
 417                 /* Write the ring initialization command to C2PMSG_101 */
 418                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 419                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 420
 421                 /* there might be handshake issue with hardware which needs delay */
 422                 mdelay(20);
 423
 424                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 425                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 426                                    0x80000000, 0x8000FFFF, false);
 427
 428         } else {
 429                 /* Write low address of the ring to C2PMSG_69 */
 430                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 431                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 432                 /* Write high address of the ring to C2PMSG_70 */
 433                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 434                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 435                 /* Write size of ring to C2PMSG_71 */
 436                 psp_ring_reg = ring->ring_size;
 437                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 438                 /* Write the ring initialization command to C2PMSG_64 */
 439                 psp_ring_reg = ring_type;
 440                 psp_ring_reg = psp_ring_reg << 16;
 441                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 442
 443                 /* there might be handshake issue with hardware which needs delay */
 444                 mdelay(20);
 445
 446                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 447                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 448                                    0x80000000, 0x8000FFFF, false);
 449         }
 450
 451         return ret;
 452 }
 453
 454 static int psp_v11_0_ring_stop(struct psp_context *psp,
 455                               enum psp_ring_type ring_type)
 456 {
 457         int ret = 0;
 458         struct amdgpu_device *adev = psp->adev;
 459
 460         /* Write the ring destroy command*/
 461         if (psp_v11_0_support_vmr_ring(psp))
 462                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 463                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 464         else
 465                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 466                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 467
 468         /* there might be handshake issue with hardware which needs delay */
 469         mdelay(20);
 470
 471         /* Wait for response flag (bit 31) */
 472         if (psp_v11_0_support_vmr_ring(psp))
 473                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 474                                    0x80000000, 0x80000000, false);
 475         else
 476                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 477                                    0x80000000, 0x80000000, false);
 478
 479         return ret;
 480 }
 481
 482 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 483                                  enum psp_ring_type ring_type)
 484 {
 485         int ret = 0;
 486         struct psp_ring *ring = &psp->km_ring;
 487         struct amdgpu_device *adev = psp->adev;
 488
 489         ret = psp_v11_0_ring_stop(psp, ring_type);
 490         if (ret)
 491                 DRM_ERROR("Fail to stop psp ring\n");
 492
 493         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 494                               &ring->ring_mem_mc_addr,
 495                               (void **)&ring->ring_mem);
 496
 497         return ret;
 498 }
 499
 500 static int psp_v11_0_cmd_submit(struct psp_context *psp,
 501                                struct amdgpu_firmware_info *ucode,
 502                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 503                                int index)
 504 {
 505         unsigned int psp_write_ptr_reg = 0;
 506         struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
 507         struct psp_ring *ring = &psp->km_ring;
 508         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 509         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 510                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 511         struct amdgpu_device *adev = psp->adev;
 512         uint32_t ring_size_dw = ring->ring_size / 4;
 513         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 514
 515         /* KM (GPCOM) prepare write pointer */
 516         if (psp_v11_0_support_vmr_ring(psp))
 517                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 518         else
 519                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 520
 521         /* Update KM RB frame pointer to new frame */
 522         /* write_frame ptr increments by size of rb_frame in bytes */
 523         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 524         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 525                 write_frame = ring_buffer_start;
 526         else
 527                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 528         /* Check invalid write_frame ptr address */
 529         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 530                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 531                           ring_buffer_start, ring_buffer_end, write_frame);
 532                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 533                 return -EINVAL;
 534         }
 535
 536         /* Initialize KM RB frame */
 537         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 538
 539         /* Update KM RB frame */
 540         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 541         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 542         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 543         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 544         write_frame->fence_value = index;
 545
 546         /* Update the write Pointer in DWORDs */
 547         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 548         if (psp_v11_0_support_vmr_ring(psp)) {
 549                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
 550                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 551         } else
 552                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 553
 554         return 0;
 555 }
 556
 557 static int
 558 psp_v11_0_sram_map(struct amdgpu_device *adev,
 559                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 560                   unsigned int *sram_data_reg_offset,
 561                   enum AMDGPU_UCODE_ID ucode_id)
 562 {
 563         int ret = 0;
 564
 565         switch (ucode_id) {
 566 /* TODO: needs to confirm */
 567 #if 0
 568         case AMDGPU_UCODE_ID_SMC:
 569                 *sram_offset = 0;
 570                 *sram_addr_reg_offset = 0;
 571                 *sram_data_reg_offset = 0;
 572                 break;
 573 #endif
 574
 575         case AMDGPU_UCODE_ID_CP_CE:
 576                 *sram_offset = 0x0;
 577                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 578                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 579                 break;
 580
 581         case AMDGPU_UCODE_ID_CP_PFP:
 582                 *sram_offset = 0x0;
 583                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 584                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 585                 break;
 586
 587         case AMDGPU_UCODE_ID_CP_ME:
 588                 *sram_offset = 0x0;
 589                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 590                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 591                 break;
 592
 593         case AMDGPU_UCODE_ID_CP_MEC1:
 594                 *sram_offset = 0x10000;
 595                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 596                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 597                 break;
 598
 599         case AMDGPU_UCODE_ID_CP_MEC2:
 600                 *sram_offset = 0x10000;
 601                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 602                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 603                 break;
 604
 605         case AMDGPU_UCODE_ID_RLC_G:
 606                 *sram_offset = 0x2000;
 607                 if (adev->asic_type < CHIP_NAVI10) {
 608                         *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 609                         *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 610                 } else {
 611                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
 612                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
 613                 }
 614                 break;
 615
 616         case AMDGPU_UCODE_ID_SDMA0:
 617                 *sram_offset = 0x0;
 618                 if (adev->asic_type < CHIP_NAVI10) {
 619                         *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 620                         *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 621                 } else {
 622                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
 623                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
 624                 }
 625                 break;
 626
 627 /* TODO: needs to confirm */
 628 #if 0
 629         case AMDGPU_UCODE_ID_SDMA1:
 630                 *sram_offset = ;
 631                 *sram_addr_reg_offset = ;
 632                 break;
 633
 634         case AMDGPU_UCODE_ID_UVD:
 635                 *sram_offset = ;
 636                 *sram_addr_reg_offset = ;
 637                 break;
 638
 639         case AMDGPU_UCODE_ID_VCE:
 640                 *sram_offset = ;
 641                 *sram_addr_reg_offset = ;
 642                 break;
 643 #endif
 644
 645         case AMDGPU_UCODE_ID_MAXIMUM:
 646         default:
 647                 ret = -EINVAL;
 648                 break;
 649         }
 650
 651         return ret;
 652 }
 653
 654 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 655                                        struct amdgpu_firmware_info *ucode,
 656                                        enum AMDGPU_UCODE_ID ucode_type)
 657 {
 658         int err = 0;
 659         unsigned int fw_sram_reg_val = 0;
 660         unsigned int fw_sram_addr_reg_offset = 0;
 661         unsigned int fw_sram_data_reg_offset = 0;
 662         unsigned int ucode_size;
 663         uint32_t *ucode_mem = NULL;
 664         struct amdgpu_device *adev = psp->adev;
 665
 666         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 667                                 &fw_sram_data_reg_offset, ucode_type);
 668         if (err)
 669                 return false;
 670
 671         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 672
 673         ucode_size = ucode->ucode_size;
 674         ucode_mem = (uint32_t *)ucode->kaddr;
 675         while (ucode_size) {
 676                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 677
 678                 if (*ucode_mem != fw_sram_reg_val)
 679                         return false;
 680
 681                 ucode_mem++;
 682                 /* 4 bytes */
 683                 ucode_size -= 4;
 684         }
 685
 686         return true;
 687 }
 688
 689 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 690 {
 691         int ret;
 692         uint32_t offset;
 693         struct amdgpu_device *adev = psp->adev;
 694
 695         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 696
 697         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 698
 699         if (ret) {
 700                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 701                 return -EINVAL;
 702         }
 703
 704         /*send the mode 1 reset command*/
 705         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 706
 707         msleep(500);
 708
 709         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 710
 711         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 712
 713         if (ret) {
 714                 DRM_INFO("psp mode 1 reset failed!\n");
 715                 return -EINVAL;
 716         }
 717
 718         DRM_INFO("psp mode1 reset succeed \n");
 719
 720         return 0;
 721 }
 722
 723 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 724  * For now, return success and hack the hive_id so high level code can
 725  * start testing
 726  */
 727 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 728         int number_devices, struct psp_xgmi_topology_info *topology)
 729 {
 730         struct ta_xgmi_shared_memory *xgmi_cmd;
 731         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 732         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 733         int i;
 734         int ret;
 735
 736         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 737                 return -EINVAL;
 738
 739         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 740         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 741
 742         /* Fill in the shared memory with topology information as input */
 743         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 744         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 745         topology_info_input->num_nodes = number_devices;
 746
 747         for (i = 0; i < topology_info_input->num_nodes; i++) {
 748                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 749                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 750                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 751                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 752         }
 753
 754         /* Invoke xgmi ta to get the topology information */
 755         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 756         if (ret)
 757                 return ret;
 758
 759         /* Read the output topology information from the shared memory */
 760         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 761         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 762         for (i = 0; i < topology->num_nodes; i++) {
 763                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 764                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 765                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 766                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 773         int number_devices, struct psp_xgmi_topology_info *topology)
 774 {
 775         struct ta_xgmi_shared_memory *xgmi_cmd;
 776         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 777         int i;
 778
 779         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 780                 return -EINVAL;
 781
 782         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 783         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 784
 785         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 786         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 787         topology_info_input->num_nodes = number_devices;
 788
 789         for (i = 0; i < topology_info_input->num_nodes; i++) {
 790                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 791                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 792                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 793                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 794         }
 795
 796         /* Invoke xgmi ta to set topology information */
 797         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 798 }
 799
 800 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 801 {
 802         struct ta_xgmi_shared_memory *xgmi_cmd;
 803         int ret;
 804
 805         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 806         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 807
 808         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 809
 810         /* Invoke xgmi ta to get hive id */
 811         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 812         if (ret)
 813                 return ret;
 814
 815         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 816
 817         return 0;
 818 }
 819
 820 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 821 {
 822         struct ta_xgmi_shared_memory *xgmi_cmd;
 823         int ret;
 824
 825         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 826         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 827
 828         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 829
 830         /* Invoke xgmi ta to get the node id */
 831         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 832         if (ret)
 833                 return ret;
 834
 835         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 836
 837         return 0;
 838 }
 839
 840 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 841                 struct ta_ras_trigger_error_input *info)
 842 {
 843         struct ta_ras_shared_memory *ras_cmd;
 844         int ret;
 845
 846         if (!psp->ras.ras_initialized)
 847                 return -EINVAL;
 848
 849         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 850         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 851
 852         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 853         ras_cmd->ras_in_message.trigger_error = *info;
 854
 855         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 856         if (ret)
 857                 return -EINVAL;
 858
 859         return ras_cmd->ras_status;
 860 }
 861
 862 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 863 {
 864 #if 0
 865         // not support yet.
 866         struct ta_ras_shared_memory *ras_cmd;
 867         int ret;
 868
 869         if (!psp->ras.ras_initialized)
 870                 return -EINVAL;
 871
 872         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 873         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 874
 875         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 876         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 877
 878         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 879         if (ret)
 880                 return -EINVAL;
 881
 882         return ras_cmd->ras_status;
 883 #else
 884         return -EINVAL;
 885 #endif
 886 }
 887
 888 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 889 {
 890         return psp_rlc_autoload_start(psp);
 891 }
 892
 893 static const struct psp_funcs psp_v11_0_funcs = {
 894         .init_microcode = psp_v11_0_init_microcode,
 895         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 896         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 897         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 898         .ring_init = psp_v11_0_ring_init,
 899         .ring_create = psp_v11_0_ring_create,
 900         .ring_stop = psp_v11_0_ring_stop,
 901         .ring_destroy = psp_v11_0_ring_destroy,
 902         .cmd_submit = psp_v11_0_cmd_submit,
 903         .compare_sram_data = psp_v11_0_compare_sram_data,
 904         .mode1_reset = psp_v11_0_mode1_reset,
 905         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
 906         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
 907         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
 908         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
 909         .support_vmr_ring = psp_v11_0_support_vmr_ring,
 910         .ras_trigger_error = psp_v11_0_ras_trigger_error,
 911         .ras_cure_posion = psp_v11_0_ras_cure_posion,
 912         .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
 913 };
 914
 915 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 916 {
 917         psp->funcs = &psp_v11_0_funcs;
 918 }