drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41
  42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v8_0_wait_for_idle(void *handle);
  45
  46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  49
  50 static const u32 golden_settings_tonga_a11[] =
  51 {
  52         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  53         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  54         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  55         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  58         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  59 };
  60
  61 static const u32 tonga_mgcg_cgcg_init[] =
  62 {
  63         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  64 };
  65
  66 static const u32 golden_settings_fiji_a10[] =
  67 {
  68         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  70         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  71         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72 };
  73
  74 static const u32 fiji_mgcg_cgcg_init[] =
  75 {
  76         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  77 };
  78
  79 static const u32 golden_settings_polaris11_a11[] =
  80 {
  81         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  82         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  83         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  84         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  85 };
  86
  87 static const u32 golden_settings_polaris10_a11[] =
  88 {
  89         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  90         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  91         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  92         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  93         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  94 };
  95
  96 static const u32 cz_mgcg_cgcg_init[] =
  97 {
  98         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  99 };
 100
 101 static const u32 stoney_mgcg_cgcg_init[] =
 102 {
 103         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 104         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 105 };
 106
 107 static const u32 golden_settings_stoney_common[] =
 108 {
 109         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 110         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 111 };
 112
 113 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 114 {
 115         switch (adev->asic_type) {
 116         case CHIP_FIJI:
 117                 amdgpu_program_register_sequence(adev,
 118                                                  fiji_mgcg_cgcg_init,
 119                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 120                 amdgpu_program_register_sequence(adev,
 121                                                  golden_settings_fiji_a10,
 122                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 123                 break;
 124         case CHIP_TONGA:
 125                 amdgpu_program_register_sequence(adev,
 126                                                  tonga_mgcg_cgcg_init,
 127                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 128                 amdgpu_program_register_sequence(adev,
 129                                                  golden_settings_tonga_a11,
 130                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 131                 break;
 132         case CHIP_POLARIS11:
 133                 amdgpu_program_register_sequence(adev,
 134                                                  golden_settings_polaris11_a11,
 135                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 136                 break;
 137         case CHIP_POLARIS10:
 138                 amdgpu_program_register_sequence(adev,
 139                                                  golden_settings_polaris10_a11,
 140                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 141                 break;
 142         case CHIP_CARRIZO:
 143                 amdgpu_program_register_sequence(adev,
 144                                                  cz_mgcg_cgcg_init,
 145                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 146                 break;
 147         case CHIP_STONEY:
 148                 amdgpu_program_register_sequence(adev,
 149                                                  stoney_mgcg_cgcg_init,
 150                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 151                 amdgpu_program_register_sequence(adev,
 152                                                  golden_settings_stoney_common,
 153                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 154                 break;
 155         default:
 156                 break;
 157         }
 158 }
 159
 160 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 161                              struct amdgpu_mode_mc_save *save)
 162 {
 163         u32 blackout;
 164
 165         if (adev->mode_info.num_crtc)
 166                 amdgpu_display_stop_mc_access(adev, save);
 167
 168         gmc_v8_0_wait_for_idle(adev);
 169
 170         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 171         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 172                 /* Block CPU access */
 173                 WREG32(mmBIF_FB_EN, 0);
 174                 /* blackout the MC */
 175                 blackout = REG_SET_FIELD(blackout,
 176                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 177                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 178         }
 179         /* wait for the MC to settle */
 180         udelay(100);
 181 }
 182
 183 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 184                                struct amdgpu_mode_mc_save *save)
 185 {
 186         u32 tmp;
 187
 188         /* unblackout the MC */
 189         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 190         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 191         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 192         /* allow CPU access */
 193         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 194         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 195         WREG32(mmBIF_FB_EN, tmp);
 196
 197         if (adev->mode_info.num_crtc)
 198                 amdgpu_display_resume_mc_access(adev, save);
 199 }
 200
 201 /**
 202  * gmc_v8_0_init_microcode - load ucode images from disk
 203  *
 204  * @adev: amdgpu_device pointer
 205  *
 206  * Use the firmware interface to load the ucode images into
 207  * the driver (not loaded into hw).
 208  * Returns 0 on success, error on failure.
 209  */
 210 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 211 {
 212         const char *chip_name;
 213         char fw_name[30];
 214         int err;
 215
 216         DRM_DEBUG("\n");
 217
 218         switch (adev->asic_type) {
 219         case CHIP_TONGA:
 220                 chip_name = "tonga";
 221                 break;
 222         case CHIP_POLARIS11:
 223                 chip_name = "polaris11";
 224                 break;
 225         case CHIP_POLARIS10:
 226                 chip_name = "polaris10";
 227                 break;
 228         case CHIP_FIJI:
 229         case CHIP_CARRIZO:
 230         case CHIP_STONEY:
 231                 return 0;
 232         default: BUG();
 233         }
 234
 235         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 236         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 237         if (err)
 238                 goto out;
 239         err = amdgpu_ucode_validate(adev->mc.fw);
 240
 241 out:
 242         if (err) {
 243                 printk(KERN_ERR
 244                        "mc: Failed to load firmware \"%s\"\n",
 245                        fw_name);
 246                 release_firmware(adev->mc.fw);
 247                 adev->mc.fw = NULL;
 248         }
 249         return err;
 250 }
 251
 252 /**
 253  * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
 254  *
 255  * @adev: amdgpu_device pointer
 256  *
 257  * Load the GDDR MC ucode into the hw (CIK).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
 261 {
 262         const struct mc_firmware_header_v1_0 *hdr;
 263         const __le32 *fw_data = NULL;
 264         const __le32 *io_mc_regs = NULL;
 265         u32 running;
 266         int i, ucode_size, regs_size;
 267
 268         if (!adev->mc.fw)
 269                 return -EINVAL;
 270
 271         /* Skip MC ucode loading on SR-IOV capable boards.
 272          * vbios does this for us in asic_init in that case.
 273          * Skip MC ucode loading on VF, because hypervisor will do that
 274          * for this adaptor.
 275          */
 276         if (amdgpu_sriov_bios(adev))
 277                 return 0;
 278
 279         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 280         amdgpu_ucode_print_mc_hdr(&hdr->header);
 281
 282         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 283         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 284         io_mc_regs = (const __le32 *)
 285                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 286         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 287         fw_data = (const __le32 *)
 288                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 289
 290         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 291
 292         if (running == 0) {
 293                 /* reset the engine and set to writable */
 294                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 295                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 296
 297                 /* load mc io regs */
 298                 for (i = 0; i < regs_size; i++) {
 299                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 300                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 301                 }
 302                 /* load the MC ucode */
 303                 for (i = 0; i < ucode_size; i++)
 304                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 305
 306                 /* put the engine back into the active state */
 307                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 308                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 309                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 310
 311                 /* wait for training to complete */
 312                 for (i = 0; i < adev->usec_timeout; i++) {
 313                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 314                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 315                                 break;
 316                         udelay(1);
 317                 }
 318                 for (i = 0; i < adev->usec_timeout; i++) {
 319                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 320                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 321                                 break;
 322                         udelay(1);
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 330                                        struct amdgpu_mc *mc)
 331 {
 332         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 333                 /* leave room for at least 1024M GTT */
 334                 dev_warn(adev->dev, "limiting VRAM\n");
 335                 mc->real_vram_size = 0xFFC0000000ULL;
 336                 mc->mc_vram_size = 0xFFC0000000ULL;
 337         }
 338         amdgpu_vram_location(adev, &adev->mc, 0);
 339         adev->mc.gtt_base_align = 0;
 340         amdgpu_gtt_location(adev, mc);
 341 }
 342
 343 /**
 344  * gmc_v8_0_mc_program - program the GPU memory controller
 345  *
 346  * @adev: amdgpu_device pointer
 347  *
 348  * Set the location of vram, gart, and AGP in the GPU's
 349  * physical address space (CIK).
 350  */
 351 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 352 {
 353         struct amdgpu_mode_mc_save save;
 354         u32 tmp;
 355         int i, j;
 356
 357         /* Initialize HDP */
 358         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 359                 WREG32((0xb05 + j), 0x00000000);
 360                 WREG32((0xb06 + j), 0x00000000);
 361                 WREG32((0xb07 + j), 0x00000000);
 362                 WREG32((0xb08 + j), 0x00000000);
 363                 WREG32((0xb09 + j), 0x00000000);
 364         }
 365         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 366
 367         if (adev->mode_info.num_crtc)
 368                 amdgpu_display_set_vga_render_state(adev, false);
 369
 370         gmc_v8_0_mc_stop(adev, &save);
 371         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 372                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 373         }
 374         /* Update configuration */
 375         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 376                adev->mc.vram_start >> 12);
 377         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 378                adev->mc.vram_end >> 12);
 379         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 380                adev->vram_scratch.gpu_addr >> 12);
 381         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 382         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 383         WREG32(mmMC_VM_FB_LOCATION, tmp);
 384         /* XXX double check these! */
 385         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 386         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 387         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 388         WREG32(mmMC_VM_AGP_BASE, 0);
 389         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 390         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 391         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 392                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 393         }
 394         gmc_v8_0_mc_resume(adev, &save);
 395
 396         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 397
 398         tmp = RREG32(mmHDP_MISC_CNTL);
 399         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 400         WREG32(mmHDP_MISC_CNTL, tmp);
 401
 402         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 403         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 404 }
 405
 406 /**
 407  * gmc_v8_0_mc_init - initialize the memory controller driver params
 408  *
 409  * @adev: amdgpu_device pointer
 410  *
 411  * Look up the amount of vram, vram width, and decide how to place
 412  * vram and gart within the GPU's physical address space (CIK).
 413  * Returns 0 for success.
 414  */
 415 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 416 {
 417         u32 tmp;
 418         int chansize, numchan;
 419
 420         /* Get VRAM informations */
 421         tmp = RREG32(mmMC_ARB_RAMCFG);
 422         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 423                 chansize = 64;
 424         } else {
 425                 chansize = 32;
 426         }
 427         tmp = RREG32(mmMC_SHARED_CHMAP);
 428         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 429         case 0:
 430         default:
 431                 numchan = 1;
 432                 break;
 433         case 1:
 434                 numchan = 2;
 435                 break;
 436         case 2:
 437                 numchan = 4;
 438                 break;
 439         case 3:
 440                 numchan = 8;
 441                 break;
 442         case 4:
 443                 numchan = 3;
 444                 break;
 445         case 5:
 446                 numchan = 6;
 447                 break;
 448         case 6:
 449                 numchan = 10;
 450                 break;
 451         case 7:
 452                 numchan = 12;
 453                 break;
 454         case 8:
 455                 numchan = 16;
 456                 break;
 457         }
 458         adev->mc.vram_width = numchan * chansize;
 459         /* Could aper size report 0 ? */
 460         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 461         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 462         /* size in MB on si */
 463         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 464         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 465         adev->mc.visible_vram_size = adev->mc.aper_size;
 466
 467         /* In case the PCI BAR is larger than the actual amount of vram */
 468         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 469                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 470
 471         /* unless the user had overridden it, set the gart
 472          * size equal to the 1024 or vram, whichever is larger.
 473          */
 474         if (amdgpu_gart_size == -1)
 475                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 476         else
 477                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 478
 479         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * GART
 486  * VMID 0 is the physical GPU addresses as used by the kernel.
 487  * VMIDs 1-15 are used for userspace clients and are handled
 488  * by the amdgpu vm/hsa code.
 489  */
 490
 491 /**
 492  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 493  *
 494  * @adev: amdgpu_device pointer
 495  * @vmid: vm instance to flush
 496  *
 497  * Flush the TLB for the requested page table (CIK).
 498  */
 499 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 500                                         uint32_t vmid)
 501 {
 502         /* flush hdp cache */
 503         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 504
 505         /* bits 0-15 are the VM contexts0-15 */
 506         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 507 }
 508
 509 /**
 510  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 511  *
 512  * @adev: amdgpu_device pointer
 513  * @cpu_pt_addr: cpu address of the page table
 514  * @gpu_page_idx: entry in the page table to update
 515  * @addr: dst addr to write into pte/pde
 516  * @flags: access flags
 517  *
 518  * Update the page tables using the CPU.
 519  */
 520 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 521                                      void *cpu_pt_addr,
 522                                      uint32_t gpu_page_idx,
 523                                      uint64_t addr,
 524                                      uint32_t flags)
 525 {
 526         void __iomem *ptr = (void *)cpu_pt_addr;
 527         uint64_t value;
 528
 529         /*
 530          * PTE format on VI:
 531          * 63:40 reserved
 532          * 39:12 4k physical page base address
 533          * 11:7 fragment
 534          * 6 write
 535          * 5 read
 536          * 4 exe
 537          * 3 reserved
 538          * 2 snooped
 539          * 1 system
 540          * 0 valid
 541          *
 542          * PDE format on VI:
 543          * 63:59 block fragment size
 544          * 58:40 reserved
 545          * 39:1 physical base address of PTE
 546          * bits 5:1 must be 0.
 547          * 0 valid
 548          */
 549         value = addr & 0x000000FFFFFFF000ULL;
 550         value |= flags;
 551         writeq(value, ptr + (gpu_page_idx * 8));
 552
 553         return 0;
 554 }
 555
 556 /**
 557  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 558  *
 559  * @adev: amdgpu_device pointer
 560  * @value: true redirects VM faults to the default page
 561  */
 562 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 563                                               bool value)
 564 {
 565         u32 tmp;
 566
 567         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 568         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 569                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 570         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 571                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 572         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 573                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 574         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 575                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 576         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 577                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 578         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 579                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 580         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 581                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 582         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 583 }
 584
 585 /**
 586  * gmc_v8_0_gart_enable - gart enable
 587  *
 588  * @adev: amdgpu_device pointer
 589  *
 590  * This sets up the TLBs, programs the page tables for VMID0,
 591  * sets up the hw for VMIDs 1-15 which are allocated on
 592  * demand, and sets up the global locations for the LDS, GDS,
 593  * and GPUVM for FSA64 clients (CIK).
 594  * Returns 0 for success, errors for failure.
 595  */
 596 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 597 {
 598         int r, i;
 599         u32 tmp;
 600
 601         if (adev->gart.robj == NULL) {
 602                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 603                 return -EINVAL;
 604         }
 605         r = amdgpu_gart_table_vram_pin(adev);
 606         if (r)
 607                 return r;
 608         /* Setup TLB control */
 609         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 610         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 611         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 612         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 613         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 614         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 615         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 616         /* Setup L2 cache */
 617         tmp = RREG32(mmVM_L2_CNTL);
 618         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 619         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 620         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 621         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 622         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 623         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 624         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 625         WREG32(mmVM_L2_CNTL, tmp);
 626         tmp = RREG32(mmVM_L2_CNTL2);
 627         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 628         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 629         WREG32(mmVM_L2_CNTL2, tmp);
 630         tmp = RREG32(mmVM_L2_CNTL3);
 631         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 632         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 633         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 634         WREG32(mmVM_L2_CNTL3, tmp);
 635         /* XXX: set to enable PTE/PDE in system memory */
 636         tmp = RREG32(mmVM_L2_CNTL4);
 637         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 638         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 639         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 640         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 641         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 642         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 643         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 644         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 645         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 646         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 647         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 648         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 649         WREG32(mmVM_L2_CNTL4, tmp);
 650         /* setup context0 */
 651         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 652         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 653         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 654         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 655                         (u32)(adev->dummy_page.addr >> 12));
 656         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 657         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 658         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 659         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 660         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 661         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 662
 663         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 664         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 665         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 666
 667         /* empty context1-15 */
 668         /* FIXME start with 4G, once using 2 level pt switch to full
 669          * vm size space
 670          */
 671         /* set vm size, must be a multiple of 4 */
 672         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 673         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 674         for (i = 1; i < 16; i++) {
 675                 if (i < 8)
 676                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 677                                adev->gart.table_addr >> 12);
 678                 else
 679                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 680                                adev->gart.table_addr >> 12);
 681         }
 682
 683         /* enable context1-15 */
 684         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 685                (u32)(adev->dummy_page.addr >> 12));
 686         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 687         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 688         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 689         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 690         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 691         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 692         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 693         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 694         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 695         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 696         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 697         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 698                             amdgpu_vm_block_size - 9);
 699         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 700         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 701                 gmc_v8_0_set_fault_enable_default(adev, false);
 702         else
 703                 gmc_v8_0_set_fault_enable_default(adev, true);
 704
 705         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 706         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 707                  (unsigned)(adev->mc.gtt_size >> 20),
 708                  (unsigned long long)adev->gart.table_addr);
 709         adev->gart.ready = true;
 710         return 0;
 711 }
 712
 713 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 714 {
 715         int r;
 716
 717         if (adev->gart.robj) {
 718                 WARN(1, "R600 PCIE GART already initialized\n");
 719                 return 0;
 720         }
 721         /* Initialize common gart structure */
 722         r = amdgpu_gart_init(adev);
 723         if (r)
 724                 return r;
 725         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 726         return amdgpu_gart_table_vram_alloc(adev);
 727 }
 728
 729 /**
 730  * gmc_v8_0_gart_disable - gart disable
 731  *
 732  * @adev: amdgpu_device pointer
 733  *
 734  * This disables all VM page table (CIK).
 735  */
 736 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 737 {
 738         u32 tmp;
 739
 740         /* Disable all tables */
 741         WREG32(mmVM_CONTEXT0_CNTL, 0);
 742         WREG32(mmVM_CONTEXT1_CNTL, 0);
 743         /* Setup TLB control */
 744         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 745         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 746         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 747         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 748         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 749         /* Setup L2 cache */
 750         tmp = RREG32(mmVM_L2_CNTL);
 751         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 752         WREG32(mmVM_L2_CNTL, tmp);
 753         WREG32(mmVM_L2_CNTL2, 0);
 754         amdgpu_gart_table_vram_unpin(adev);
 755 }
 756
 757 /**
 758  * gmc_v8_0_gart_fini - vm fini callback
 759  *
 760  * @adev: amdgpu_device pointer
 761  *
 762  * Tears down the driver GART/VM setup (CIK).
 763  */
 764 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 765 {
 766         amdgpu_gart_table_vram_free(adev);
 767         amdgpu_gart_fini(adev);
 768 }
 769
 770 /*
 771  * vm
 772  * VMID 0 is the physical GPU addresses as used by the kernel.
 773  * VMIDs 1-15 are used for userspace clients and are handled
 774  * by the amdgpu vm/hsa code.
 775  */
 776 /**
 777  * gmc_v8_0_vm_init - cik vm init callback
 778  *
 779  * @adev: amdgpu_device pointer
 780  *
 781  * Inits cik specific vm parameters (number of VMs, base of vram for
 782  * VMIDs 1-15) (CIK).
 783  * Returns 0 for success.
 784  */
 785 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 786 {
 787         /*
 788          * number of VMs
 789          * VMID 0 is reserved for System
 790          * amdgpu graphics/compute will use VMIDs 1-7
 791          * amdkfd will use VMIDs 8-15
 792          */
 793         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 794         amdgpu_vm_manager_init(adev);
 795
 796         /* base offset of vram pages */
 797         if (adev->flags & AMD_IS_APU) {
 798                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 799                 tmp <<= 22;
 800                 adev->vm_manager.vram_base_offset = tmp;
 801         } else
 802                 adev->vm_manager.vram_base_offset = 0;
 803
 804         return 0;
 805 }
 806
 807 /**
 808  * gmc_v8_0_vm_fini - cik vm fini callback
 809  *
 810  * @adev: amdgpu_device pointer
 811  *
 812  * Tear down any asic specific VM setup (CIK).
 813  */
 814 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
 815 {
 816 }
 817
 818 /**
 819  * gmc_v8_0_vm_decode_fault - print human readable fault info
 820  *
 821  * @adev: amdgpu_device pointer
 822  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 823  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 824  *
 825  * Print human readable fault information (CIK).
 826  */
 827 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 828                                      u32 status, u32 addr, u32 mc_client)
 829 {
 830         u32 mc_id;
 831         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 832         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 833                                         PROTECTIONS);
 834         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 835                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 836
 837         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 838                               MEMORY_CLIENT_ID);
 839
 840         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 841                protections, vmid, addr,
 842                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 843                              MEMORY_CLIENT_RW) ?
 844                "write" : "read", block, mc_client, mc_id);
 845 }
 846
 847 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 848 {
 849         switch (mc_seq_vram_type) {
 850         case MC_SEQ_MISC0__MT__GDDR1:
 851                 return AMDGPU_VRAM_TYPE_GDDR1;
 852         case MC_SEQ_MISC0__MT__DDR2:
 853                 return AMDGPU_VRAM_TYPE_DDR2;
 854         case MC_SEQ_MISC0__MT__GDDR3:
 855                 return AMDGPU_VRAM_TYPE_GDDR3;
 856         case MC_SEQ_MISC0__MT__GDDR4:
 857                 return AMDGPU_VRAM_TYPE_GDDR4;
 858         case MC_SEQ_MISC0__MT__GDDR5:
 859                 return AMDGPU_VRAM_TYPE_GDDR5;
 860         case MC_SEQ_MISC0__MT__HBM:
 861                 return AMDGPU_VRAM_TYPE_HBM;
 862         case MC_SEQ_MISC0__MT__DDR3:
 863                 return AMDGPU_VRAM_TYPE_DDR3;
 864         default:
 865                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 866         }
 867 }
 868
 869 static int gmc_v8_0_early_init(void *handle)
 870 {
 871         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 872
 873         gmc_v8_0_set_gart_funcs(adev);
 874         gmc_v8_0_set_irq_funcs(adev);
 875
 876         return 0;
 877 }
 878
 879 static int gmc_v8_0_late_init(void *handle)
 880 {
 881         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 882
 883         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 884                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 885         else
 886                 return 0;
 887 }
 888
 889 #define mmMC_SEQ_MISC0_FIJI 0xA71
 890
 891 static int gmc_v8_0_sw_init(void *handle)
 892 {
 893         int r;
 894         int dma_bits;
 895         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 896
 897         if (adev->flags & AMD_IS_APU) {
 898                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 899         } else {
 900                 u32 tmp;
 901
 902                 if (adev->asic_type == CHIP_FIJI)
 903                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
 904                 else
 905                         tmp = RREG32(mmMC_SEQ_MISC0);
 906                 tmp &= MC_SEQ_MISC0__MT__MASK;
 907                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 908         }
 909
 910         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 911         if (r)
 912                 return r;
 913
 914         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 915         if (r)
 916                 return r;
 917
 918         /* Adjust VM size here.
 919          * Currently set to 4GB ((1 << 20) 4k pages).
 920          * Max GPUVM size for cayman and SI is 40 bits.
 921          */
 922         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 923
 924         /* Set the internal MC address mask
 925          * This is the max address of the GPU's
 926          * internal address space.
 927          */
 928         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 929
 930         /* set DMA mask + need_dma32 flags.
 931          * PCIE - can handle 40-bits.
 932          * IGP - can handle 40-bits
 933          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 934          */
 935         adev->need_dma32 = false;
 936         dma_bits = adev->need_dma32 ? 32 : 40;
 937         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 938         if (r) {
 939                 adev->need_dma32 = true;
 940                 dma_bits = 32;
 941                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 942         }
 943         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 944         if (r) {
 945                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 946                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 947         }
 948
 949         r = gmc_v8_0_init_microcode(adev);
 950         if (r) {
 951                 DRM_ERROR("Failed to load mc firmware!\n");
 952                 return r;
 953         }
 954
 955         r = gmc_v8_0_mc_init(adev);
 956         if (r)
 957                 return r;
 958
 959         /* Memory manager */
 960         r = amdgpu_bo_init(adev);
 961         if (r)
 962                 return r;
 963
 964         r = gmc_v8_0_gart_init(adev);
 965         if (r)
 966                 return r;
 967
 968         if (!adev->vm_manager.enabled) {
 969                 r = gmc_v8_0_vm_init(adev);
 970                 if (r) {
 971                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 972                         return r;
 973                 }
 974                 adev->vm_manager.enabled = true;
 975         }
 976
 977         return r;
 978 }
 979
 980 static int gmc_v8_0_sw_fini(void *handle)
 981 {
 982         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 983
 984         if (adev->vm_manager.enabled) {
 985                 amdgpu_vm_manager_fini(adev);
 986                 gmc_v8_0_vm_fini(adev);
 987                 adev->vm_manager.enabled = false;
 988         }
 989         gmc_v8_0_gart_fini(adev);
 990         amdgpu_gem_force_release(adev);
 991         amdgpu_bo_fini(adev);
 992
 993         return 0;
 994 }
 995
 996 static int gmc_v8_0_hw_init(void *handle)
 997 {
 998         int r;
 999         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1000
1001         gmc_v8_0_init_golden_registers(adev);
1002
1003         gmc_v8_0_mc_program(adev);
1004
1005         if (adev->asic_type == CHIP_TONGA) {
1006                 r = gmc_v8_0_mc_load_microcode(adev);
1007                 if (r) {
1008                         DRM_ERROR("Failed to load MC firmware!\n");
1009                         return r;
1010                 }
1011         }
1012
1013         r = gmc_v8_0_gart_enable(adev);
1014         if (r)
1015                 return r;
1016
1017         return r;
1018 }
1019
1020 static int gmc_v8_0_hw_fini(void *handle)
1021 {
1022         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023
1024         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1025         gmc_v8_0_gart_disable(adev);
1026
1027         return 0;
1028 }
1029
1030 static int gmc_v8_0_suspend(void *handle)
1031 {
1032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033
1034         if (adev->vm_manager.enabled) {
1035                 gmc_v8_0_vm_fini(adev);
1036                 adev->vm_manager.enabled = false;
1037         }
1038         gmc_v8_0_hw_fini(adev);
1039
1040         return 0;
1041 }
1042
1043 static int gmc_v8_0_resume(void *handle)
1044 {
1045         int r;
1046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1047
1048         r = gmc_v8_0_hw_init(adev);
1049         if (r)
1050                 return r;
1051
1052         if (!adev->vm_manager.enabled) {
1053                 r = gmc_v8_0_vm_init(adev);
1054                 if (r) {
1055                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1056                         return r;
1057                 }
1058                 adev->vm_manager.enabled = true;
1059         }
1060
1061         return r;
1062 }
1063
1064 static bool gmc_v8_0_is_idle(void *handle)
1065 {
1066         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067         u32 tmp = RREG32(mmSRBM_STATUS);
1068
1069         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1070                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1071                 return false;
1072
1073         return true;
1074 }
1075
1076 static int gmc_v8_0_wait_for_idle(void *handle)
1077 {
1078         unsigned i;
1079         u32 tmp;
1080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1081
1082         for (i = 0; i < adev->usec_timeout; i++) {
1083                 /* read MC_STATUS */
1084                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1085                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1086                                                SRBM_STATUS__MCC_BUSY_MASK |
1087                                                SRBM_STATUS__MCD_BUSY_MASK |
1088                                                SRBM_STATUS__VMC_BUSY_MASK |
1089                                                SRBM_STATUS__VMC1_BUSY_MASK);
1090                 if (!tmp)
1091                         return 0;
1092                 udelay(1);
1093         }
1094         return -ETIMEDOUT;
1095
1096 }
1097
1098 static bool gmc_v8_0_check_soft_reset(void *handle)
1099 {
1100         u32 srbm_soft_reset = 0;
1101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102         u32 tmp = RREG32(mmSRBM_STATUS);
1103
1104         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1105                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1106                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1107
1108         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1109                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1110                 if (!(adev->flags & AMD_IS_APU))
1111                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1112                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1113         }
1114         if (srbm_soft_reset) {
1115                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1116                 return true;
1117         } else {
1118                 adev->mc.srbm_soft_reset = 0;
1119                 return false;
1120         }
1121 }
1122
1123 static int gmc_v8_0_pre_soft_reset(void *handle)
1124 {
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         if (!adev->mc.srbm_soft_reset)
1128                 return 0;
1129
1130         gmc_v8_0_mc_stop(adev, &adev->mc.save);
1131         if (gmc_v8_0_wait_for_idle(adev)) {
1132                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int gmc_v8_0_soft_reset(void *handle)
1139 {
1140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141         u32 srbm_soft_reset;
1142
1143         if (!adev->mc.srbm_soft_reset)
1144                 return 0;
1145         srbm_soft_reset = adev->mc.srbm_soft_reset;
1146
1147         if (srbm_soft_reset) {
1148                 u32 tmp;
1149
1150                 tmp = RREG32(mmSRBM_SOFT_RESET);
1151                 tmp |= srbm_soft_reset;
1152                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1153                 WREG32(mmSRBM_SOFT_RESET, tmp);
1154                 tmp = RREG32(mmSRBM_SOFT_RESET);
1155
1156                 udelay(50);
1157
1158                 tmp &= ~srbm_soft_reset;
1159                 WREG32(mmSRBM_SOFT_RESET, tmp);
1160                 tmp = RREG32(mmSRBM_SOFT_RESET);
1161
1162                 /* Wait a little for things to settle down */
1163                 udelay(50);
1164         }
1165
1166         return 0;
1167 }
1168
1169 static int gmc_v8_0_post_soft_reset(void *handle)
1170 {
1171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172
1173         if (!adev->mc.srbm_soft_reset)
1174                 return 0;
1175
1176         gmc_v8_0_mc_resume(adev, &adev->mc.save);
1177         return 0;
1178 }
1179
1180 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1181                                              struct amdgpu_irq_src *src,
1182                                              unsigned type,
1183                                              enum amdgpu_interrupt_state state)
1184 {
1185         u32 tmp;
1186         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1187                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1188                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1189                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1190                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1191                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1192                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1193
1194         switch (state) {
1195         case AMDGPU_IRQ_STATE_DISABLE:
1196                 /* system context */
1197                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1198                 tmp &= ~bits;
1199                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1200                 /* VMs */
1201                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1202                 tmp &= ~bits;
1203                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1204                 break;
1205         case AMDGPU_IRQ_STATE_ENABLE:
1206                 /* system context */
1207                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1208                 tmp |= bits;
1209                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1210                 /* VMs */
1211                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1212                 tmp |= bits;
1213                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1214                 break;
1215         default:
1216                 break;
1217         }
1218
1219         return 0;
1220 }
1221
1222 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1223                                       struct amdgpu_irq_src *source,
1224                                       struct amdgpu_iv_entry *entry)
1225 {
1226         u32 addr, status, mc_client;
1227
1228         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1229         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1230         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1231         /* reset addr and status */
1232         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1233
1234         if (!addr && !status)
1235                 return 0;
1236
1237         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1238                 gmc_v8_0_set_fault_enable_default(adev, false);
1239
1240         if (printk_ratelimit()) {
1241                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1242                         entry->src_id, entry->src_data);
1243                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1244                         addr);
1245                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1246                         status);
1247                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1248         }
1249
1250         return 0;
1251 }
1252
1253 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1254                                                      bool enable)
1255 {
1256         uint32_t data;
1257
1258         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1259                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1260                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1261                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1262
1263                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1264                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1265                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1266
1267                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1268                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1269                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1270
1271                 data = RREG32(mmMC_XPB_CLK_GAT);
1272                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1273                 WREG32(mmMC_XPB_CLK_GAT, data);
1274
1275                 data = RREG32(mmATC_MISC_CG);
1276                 data |= ATC_MISC_CG__ENABLE_MASK;
1277                 WREG32(mmATC_MISC_CG, data);
1278
1279                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1280                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1281                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1282
1283                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1284                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1285                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1286
1287                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1288                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1289                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1290
1291                 data = RREG32(mmVM_L2_CG);
1292                 data |= VM_L2_CG__ENABLE_MASK;
1293                 WREG32(mmVM_L2_CG, data);
1294         } else {
1295                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1296                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1297                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1298
1299                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1300                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1301                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1302
1303                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1304                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1305                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1306
1307                 data = RREG32(mmMC_XPB_CLK_GAT);
1308                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1309                 WREG32(mmMC_XPB_CLK_GAT, data);
1310
1311                 data = RREG32(mmATC_MISC_CG);
1312                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1313                 WREG32(mmATC_MISC_CG, data);
1314
1315                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1316                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1317                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1318
1319                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1320                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1321                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1322
1323                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1324                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1325                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1326
1327                 data = RREG32(mmVM_L2_CG);
1328                 data &= ~VM_L2_CG__ENABLE_MASK;
1329                 WREG32(mmVM_L2_CG, data);
1330         }
1331 }
1332
1333 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1334                                        bool enable)
1335 {
1336         uint32_t data;
1337
1338         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1339                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1340                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1341                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1342
1343                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1344                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1345                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1346
1347                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1348                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1349                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1350
1351                 data = RREG32(mmMC_XPB_CLK_GAT);
1352                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1353                 WREG32(mmMC_XPB_CLK_GAT, data);
1354
1355                 data = RREG32(mmATC_MISC_CG);
1356                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1357                 WREG32(mmATC_MISC_CG, data);
1358
1359                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1360                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1361                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1362
1363                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1364                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1365                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1366
1367                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1368                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1369                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1370
1371                 data = RREG32(mmVM_L2_CG);
1372                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1373                 WREG32(mmVM_L2_CG, data);
1374         } else {
1375                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1376                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1377                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1378
1379                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1380                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1381                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1382
1383                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1384                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1385                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1386
1387                 data = RREG32(mmMC_XPB_CLK_GAT);
1388                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1389                 WREG32(mmMC_XPB_CLK_GAT, data);
1390
1391                 data = RREG32(mmATC_MISC_CG);
1392                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1393                 WREG32(mmATC_MISC_CG, data);
1394
1395                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1396                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1397                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1398
1399                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1400                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1401                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1402
1403                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1404                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1405                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1406
1407                 data = RREG32(mmVM_L2_CG);
1408                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1409                 WREG32(mmVM_L2_CG, data);
1410         }
1411 }
1412
1413 static int gmc_v8_0_set_clockgating_state(void *handle,
1414                                           enum amd_clockgating_state state)
1415 {
1416         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1417
1418         switch (adev->asic_type) {
1419         case CHIP_FIJI:
1420                 fiji_update_mc_medium_grain_clock_gating(adev,
1421                                 state == AMD_CG_STATE_GATE ? true : false);
1422                 fiji_update_mc_light_sleep(adev,
1423                                 state == AMD_CG_STATE_GATE ? true : false);
1424                 break;
1425         default:
1426                 break;
1427         }
1428         return 0;
1429 }
1430
1431 static int gmc_v8_0_set_powergating_state(void *handle,
1432                                           enum amd_powergating_state state)
1433 {
1434         return 0;
1435 }
1436
1437 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1438         .name = "gmc_v8_0",
1439         .early_init = gmc_v8_0_early_init,
1440         .late_init = gmc_v8_0_late_init,
1441         .sw_init = gmc_v8_0_sw_init,
1442         .sw_fini = gmc_v8_0_sw_fini,
1443         .hw_init = gmc_v8_0_hw_init,
1444         .hw_fini = gmc_v8_0_hw_fini,
1445         .suspend = gmc_v8_0_suspend,
1446         .resume = gmc_v8_0_resume,
1447         .is_idle = gmc_v8_0_is_idle,
1448         .wait_for_idle = gmc_v8_0_wait_for_idle,
1449         .check_soft_reset = gmc_v8_0_check_soft_reset,
1450         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1451         .soft_reset = gmc_v8_0_soft_reset,
1452         .post_soft_reset = gmc_v8_0_post_soft_reset,
1453         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1454         .set_powergating_state = gmc_v8_0_set_powergating_state,
1455 };
1456
1457 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1458         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1459         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1460 };
1461
1462 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1463         .set = gmc_v8_0_vm_fault_interrupt_state,
1464         .process = gmc_v8_0_process_interrupt,
1465 };
1466
1467 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1468 {
1469         if (adev->gart.gart_funcs == NULL)
1470                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1471 }
1472
1473 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1474 {
1475         adev->mc.vm_fault.num_types = 1;
1476         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1477 }
1478
1479 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1480 {
1481         .type = AMD_IP_BLOCK_TYPE_GMC,
1482         .major = 8,
1483         .minor = 0,
1484         .rev = 0,
1485         .funcs = &gmc_v8_0_ip_funcs,
1486 };
1487
1488 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1489 {
1490         .type = AMD_IP_BLOCK_TYPE_GMC,
1491         .major = 8,
1492         .minor = 1,
1493         .rev = 0,
1494         .funcs = &gmc_v8_0_ip_funcs,
1495 };
1496
1497 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1498 {
1499         .type = AMD_IP_BLOCK_TYPE_GMC,
1500         .major = 8,
1501         .minor = 5,
1502         .rev = 0,
1503         .funcs = &gmc_v8_0_ip_funcs,
1504 };