drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 #include "amdgpu_atombios.h"
  41
  42 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v7_0_wait_for_idle(void *handle);
  45
  46 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  47 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  49
  50 static const u32 golden_settings_iceland_a11[] =
  51 {
  52         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  53         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  54         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  56 };
  57
  58 static const u32 iceland_mgcg_cgcg_init[] =
  59 {
  60         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  61 };
  62
  63 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  64 {
  65         switch (adev->asic_type) {
  66         case CHIP_TOPAZ:
  67                 amdgpu_program_register_sequence(adev,
  68                                                  iceland_mgcg_cgcg_init,
  69                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  70                 amdgpu_program_register_sequence(adev,
  71                                                  golden_settings_iceland_a11,
  72                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  73                 break;
  74         default:
  75                 break;
  76         }
  77 }
  78
  79 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  80                              struct amdgpu_mode_mc_save *save)
  81 {
  82         u32 blackout;
  83
  84         if (adev->mode_info.num_crtc)
  85                 amdgpu_display_stop_mc_access(adev, save);
  86
  87         gmc_v7_0_wait_for_idle((void *)adev);
  88
  89         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  90         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  91                 /* Block CPU access */
  92                 WREG32(mmBIF_FB_EN, 0);
  93                 /* blackout the MC */
  94                 blackout = REG_SET_FIELD(blackout,
  95                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  96                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  97         }
  98         /* wait for the MC to settle */
  99         udelay(100);
 100 }
 101
 102 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
 103                                struct amdgpu_mode_mc_save *save)
 104 {
 105         u32 tmp;
 106
 107         /* unblackout the MC */
 108         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 109         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 110         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 111         /* allow CPU access */
 112         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 113         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 114         WREG32(mmBIF_FB_EN, tmp);
 115
 116         if (adev->mode_info.num_crtc)
 117                 amdgpu_display_resume_mc_access(adev, save);
 118 }
 119
 120 /**
 121  * gmc_v7_0_init_microcode - load ucode images from disk
 122  *
 123  * @adev: amdgpu_device pointer
 124  *
 125  * Use the firmware interface to load the ucode images into
 126  * the driver (not loaded into hw).
 127  * Returns 0 on success, error on failure.
 128  */
 129 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 130 {
 131         const char *chip_name;
 132         char fw_name[30];
 133         int err;
 134
 135         DRM_DEBUG("\n");
 136
 137         switch (adev->asic_type) {
 138         case CHIP_BONAIRE:
 139                 chip_name = "bonaire";
 140                 break;
 141         case CHIP_HAWAII:
 142                 chip_name = "hawaii";
 143                 break;
 144         case CHIP_TOPAZ:
 145                 chip_name = "topaz";
 146                 break;
 147         case CHIP_KAVERI:
 148         case CHIP_KABINI:
 149         case CHIP_MULLINS:
 150                 return 0;
 151         default: BUG();
 152         }
 153
 154         if (adev->asic_type == CHIP_TOPAZ)
 155                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 156         else
 157                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 158
 159         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 160         if (err)
 161                 goto out;
 162         err = amdgpu_ucode_validate(adev->mc.fw);
 163
 164 out:
 165         if (err) {
 166                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 167                 release_firmware(adev->mc.fw);
 168                 adev->mc.fw = NULL;
 169         }
 170         return err;
 171 }
 172
 173 /**
 174  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 175  *
 176  * @adev: amdgpu_device pointer
 177  *
 178  * Load the GDDR MC ucode into the hw (CIK).
 179  * Returns 0 on success, error on failure.
 180  */
 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 182 {
 183         const struct mc_firmware_header_v1_0 *hdr;
 184         const __le32 *fw_data = NULL;
 185         const __le32 *io_mc_regs = NULL;
 186         u32 running;
 187         int i, ucode_size, regs_size;
 188
 189         if (!adev->mc.fw)
 190                 return -EINVAL;
 191
 192         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 193         amdgpu_ucode_print_mc_hdr(&hdr->header);
 194
 195         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 196         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 197         io_mc_regs = (const __le32 *)
 198                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 199         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 200         fw_data = (const __le32 *)
 201                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 202
 203         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 204
 205         if (running == 0) {
 206                 /* reset the engine and set to writable */
 207                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 208                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 209
 210                 /* load mc io regs */
 211                 for (i = 0; i < regs_size; i++) {
 212                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 213                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 214                 }
 215                 /* load the MC ucode */
 216                 for (i = 0; i < ucode_size; i++)
 217                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 218
 219                 /* put the engine back into the active state */
 220                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 221                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 222                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 223
 224                 /* wait for training to complete */
 225                 for (i = 0; i < adev->usec_timeout; i++) {
 226                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 227                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 228                                 break;
 229                         udelay(1);
 230                 }
 231                 for (i = 0; i < adev->usec_timeout; i++) {
 232                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 233                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 234                                 break;
 235                         udelay(1);
 236                 }
 237         }
 238
 239         return 0;
 240 }
 241
 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 243                                        struct amdgpu_mc *mc)
 244 {
 245         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 246                 /* leave room for at least 1024M GTT */
 247                 dev_warn(adev->dev, "limiting VRAM\n");
 248                 mc->real_vram_size = 0xFFC0000000ULL;
 249                 mc->mc_vram_size = 0xFFC0000000ULL;
 250         }
 251         amdgpu_vram_location(adev, &adev->mc, 0);
 252         adev->mc.gtt_base_align = 0;
 253         amdgpu_gtt_location(adev, mc);
 254 }
 255
 256 /**
 257  * gmc_v7_0_mc_program - program the GPU memory controller
 258  *
 259  * @adev: amdgpu_device pointer
 260  *
 261  * Set the location of vram, gart, and AGP in the GPU's
 262  * physical address space (CIK).
 263  */
 264 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 265 {
 266         struct amdgpu_mode_mc_save save;
 267         u32 tmp;
 268         int i, j;
 269
 270         /* Initialize HDP */
 271         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 272                 WREG32((0xb05 + j), 0x00000000);
 273                 WREG32((0xb06 + j), 0x00000000);
 274                 WREG32((0xb07 + j), 0x00000000);
 275                 WREG32((0xb08 + j), 0x00000000);
 276                 WREG32((0xb09 + j), 0x00000000);
 277         }
 278         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 279
 280         if (adev->mode_info.num_crtc)
 281                 amdgpu_display_set_vga_render_state(adev, false);
 282
 283         gmc_v7_0_mc_stop(adev, &save);
 284         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 285                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 286         }
 287         /* Update configuration */
 288         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 289                adev->mc.vram_start >> 12);
 290         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 291                adev->mc.vram_end >> 12);
 292         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 293                adev->vram_scratch.gpu_addr >> 12);
 294         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 295         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 296         WREG32(mmMC_VM_FB_LOCATION, tmp);
 297         /* XXX double check these! */
 298         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 299         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 300         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 301         WREG32(mmMC_VM_AGP_BASE, 0);
 302         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 303         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 304         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 305                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 306         }
 307         gmc_v7_0_mc_resume(adev, &save);
 308
 309         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 310
 311         tmp = RREG32(mmHDP_MISC_CNTL);
 312         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 313         WREG32(mmHDP_MISC_CNTL, tmp);
 314
 315         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 316         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 317 }
 318
 319 /**
 320  * gmc_v7_0_mc_init - initialize the memory controller driver params
 321  *
 322  * @adev: amdgpu_device pointer
 323  *
 324  * Look up the amount of vram, vram width, and decide how to place
 325  * vram and gart within the GPU's physical address space (CIK).
 326  * Returns 0 for success.
 327  */
 328 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 329 {
 330         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 331         if (!adev->mc.vram_width) {
 332                 u32 tmp;
 333                 int chansize, numchan;
 334
 335                 /* Get VRAM informations */
 336                 tmp = RREG32(mmMC_ARB_RAMCFG);
 337                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 338                         chansize = 64;
 339                 } else {
 340                         chansize = 32;
 341                 }
 342                 tmp = RREG32(mmMC_SHARED_CHMAP);
 343                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 344                 case 0:
 345                 default:
 346                         numchan = 1;
 347                         break;
 348                 case 1:
 349                         numchan = 2;
 350                         break;
 351                 case 2:
 352                         numchan = 4;
 353                         break;
 354                 case 3:
 355                         numchan = 8;
 356                         break;
 357                 case 4:
 358                         numchan = 3;
 359                         break;
 360                 case 5:
 361                         numchan = 6;
 362                         break;
 363                 case 6:
 364                         numchan = 10;
 365                         break;
 366                 case 7:
 367                         numchan = 12;
 368                         break;
 369                 case 8:
 370                         numchan = 16;
 371                         break;
 372                 }
 373                 adev->mc.vram_width = numchan * chansize;
 374         }
 375         /* Could aper size report 0 ? */
 376         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 377         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 378         /* size in MB on si */
 379         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 380         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 381
 382 #ifdef CONFIG_X86_64
 383         if (adev->flags & AMD_IS_APU) {
 384                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 385                 adev->mc.aper_size = adev->mc.real_vram_size;
 386         }
 387 #endif
 388
 389         /* In case the PCI BAR is larger than the actual amount of vram */
 390         adev->mc.visible_vram_size = adev->mc.aper_size;
 391         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 392                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 393
 394         /* unless the user had overridden it, set the gart
 395          * size equal to the 1024 or vram, whichever is larger.
 396          */
 397         if (amdgpu_gart_size == -1)
 398                 adev->mc.gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
 399                                         adev->mc.mc_vram_size);
 400         else
 401                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 402
 403         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * GART
 410  * VMID 0 is the physical GPU addresses as used by the kernel.
 411  * VMIDs 1-15 are used for userspace clients and are handled
 412  * by the amdgpu vm/hsa code.
 413  */
 414
 415 /**
 416  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @vmid: vm instance to flush
 420  *
 421  * Flush the TLB for the requested page table (CIK).
 422  */
 423 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 424                                         uint32_t vmid)
 425 {
 426         /* flush hdp cache */
 427         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 428
 429         /* bits 0-15 are the VM contexts0-15 */
 430         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 431 }
 432
 433 /**
 434  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 435  *
 436  * @adev: amdgpu_device pointer
 437  * @cpu_pt_addr: cpu address of the page table
 438  * @gpu_page_idx: entry in the page table to update
 439  * @addr: dst addr to write into pte/pde
 440  * @flags: access flags
 441  *
 442  * Update the page tables using the CPU.
 443  */
 444 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 445                                      void *cpu_pt_addr,
 446                                      uint32_t gpu_page_idx,
 447                                      uint64_t addr,
 448                                      uint64_t flags)
 449 {
 450         void __iomem *ptr = (void *)cpu_pt_addr;
 451         uint64_t value;
 452
 453         value = addr & 0xFFFFFFFFFFFFF000ULL;
 454         value |= flags;
 455         writeq(value, ptr + (gpu_page_idx * 8));
 456
 457         return 0;
 458 }
 459
 460 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
 461                                           uint32_t flags)
 462 {
 463         uint64_t pte_flag = 0;
 464
 465         if (flags & AMDGPU_VM_PAGE_READABLE)
 466                 pte_flag |= AMDGPU_PTE_READABLE;
 467         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 468                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 469         if (flags & AMDGPU_VM_PAGE_PRT)
 470                 pte_flag |= AMDGPU_PTE_PRT;
 471
 472         return pte_flag;
 473 }
 474
 475 static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 476 {
 477         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 478         return addr;
 479 }
 480
 481 /**
 482  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 483  *
 484  * @adev: amdgpu_device pointer
 485  * @value: true redirects VM faults to the default page
 486  */
 487 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 488                                               bool value)
 489 {
 490         u32 tmp;
 491
 492         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 493         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 494                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 495         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 496                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 497         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 498                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 499         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 500                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 501         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 502                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 503         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 504                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 505         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 506 }
 507
 508 /**
 509  * gmc_v7_0_set_prt - set PRT VM fault
 510  *
 511  * @adev: amdgpu_device pointer
 512  * @enable: enable/disable VM fault handling for PRT
 513  */
 514 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 515 {
 516         uint32_t tmp;
 517
 518         if (enable && !adev->mc.prt_warning) {
 519                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 520                 adev->mc.prt_warning = true;
 521         }
 522
 523         tmp = RREG32(mmVM_PRT_CNTL);
 524         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 525                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 526         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 527                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 528         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 529                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 530         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 531                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 532         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 533                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 534         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 535                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 536         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 537                             MASK_PDE0_FAULT, enable);
 538         WREG32(mmVM_PRT_CNTL, tmp);
 539
 540         if (enable) {
 541                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 542                 uint32_t high = adev->vm_manager.max_pfn;
 543
 544                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 545                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 546                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 547                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 548                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 549                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 550                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 551                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 552         } else {
 553                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 554                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 555                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 556                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 557                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 558                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 559                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 560                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 561         }
 562 }
 563
 564 /**
 565  * gmc_v7_0_gart_enable - gart enable
 566  *
 567  * @adev: amdgpu_device pointer
 568  *
 569  * This sets up the TLBs, programs the page tables for VMID0,
 570  * sets up the hw for VMIDs 1-15 which are allocated on
 571  * demand, and sets up the global locations for the LDS, GDS,
 572  * and GPUVM for FSA64 clients (CIK).
 573  * Returns 0 for success, errors for failure.
 574  */
 575 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 576 {
 577         int r, i;
 578         u32 tmp;
 579
 580         if (adev->gart.robj == NULL) {
 581                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 582                 return -EINVAL;
 583         }
 584         r = amdgpu_gart_table_vram_pin(adev);
 585         if (r)
 586                 return r;
 587         /* Setup TLB control */
 588         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 589         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 590         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 591         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 592         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 593         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 594         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 595         /* Setup L2 cache */
 596         tmp = RREG32(mmVM_L2_CNTL);
 597         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 598         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 599         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 600         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 601         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 602         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 603         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 604         WREG32(mmVM_L2_CNTL, tmp);
 605         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 606         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 607         WREG32(mmVM_L2_CNTL2, tmp);
 608         tmp = RREG32(mmVM_L2_CNTL3);
 609         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 610         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 611         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 612         WREG32(mmVM_L2_CNTL3, tmp);
 613         /* setup context0 */
 614         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 615         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 616         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 617         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 618                         (u32)(adev->dummy_page.addr >> 12));
 619         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 620         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 621         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 622         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 623         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 624         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 625
 626         WREG32(0x575, 0);
 627         WREG32(0x576, 0);
 628         WREG32(0x577, 0);
 629
 630         /* empty context1-15 */
 631         /* FIXME start with 4G, once using 2 level pt switch to full
 632          * vm size space
 633          */
 634         /* set vm size, must be a multiple of 4 */
 635         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 636         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 637         for (i = 1; i < 16; i++) {
 638                 if (i < 8)
 639                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 640                                adev->gart.table_addr >> 12);
 641                 else
 642                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 643                                adev->gart.table_addr >> 12);
 644         }
 645
 646         /* enable context1-15 */
 647         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 648                (u32)(adev->dummy_page.addr >> 12));
 649         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 650         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 651         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 652         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 653         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 654                             adev->vm_manager.block_size - 9);
 655         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 656         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 657                 gmc_v7_0_set_fault_enable_default(adev, false);
 658         else
 659                 gmc_v7_0_set_fault_enable_default(adev, true);
 660
 661         if (adev->asic_type == CHIP_KAVERI) {
 662                 tmp = RREG32(mmCHUB_CONTROL);
 663                 tmp &= ~BYPASS_VM;
 664                 WREG32(mmCHUB_CONTROL, tmp);
 665         }
 666
 667         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 668         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 669                  (unsigned)(adev->mc.gtt_size >> 20),
 670                  (unsigned long long)adev->gart.table_addr);
 671         adev->gart.ready = true;
 672         return 0;
 673 }
 674
 675 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 676 {
 677         int r;
 678
 679         if (adev->gart.robj) {
 680                 WARN(1, "R600 PCIE GART already initialized\n");
 681                 return 0;
 682         }
 683         /* Initialize common gart structure */
 684         r = amdgpu_gart_init(adev);
 685         if (r)
 686                 return r;
 687         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 688         adev->gart.gart_pte_flags = 0;
 689         return amdgpu_gart_table_vram_alloc(adev);
 690 }
 691
 692 /**
 693  * gmc_v7_0_gart_disable - gart disable
 694  *
 695  * @adev: amdgpu_device pointer
 696  *
 697  * This disables all VM page table (CIK).
 698  */
 699 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 700 {
 701         u32 tmp;
 702
 703         /* Disable all tables */
 704         WREG32(mmVM_CONTEXT0_CNTL, 0);
 705         WREG32(mmVM_CONTEXT1_CNTL, 0);
 706         /* Setup TLB control */
 707         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 708         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 709         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 710         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 711         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 712         /* Setup L2 cache */
 713         tmp = RREG32(mmVM_L2_CNTL);
 714         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 715         WREG32(mmVM_L2_CNTL, tmp);
 716         WREG32(mmVM_L2_CNTL2, 0);
 717         amdgpu_gart_table_vram_unpin(adev);
 718 }
 719
 720 /**
 721  * gmc_v7_0_gart_fini - vm fini callback
 722  *
 723  * @adev: amdgpu_device pointer
 724  *
 725  * Tears down the driver GART/VM setup (CIK).
 726  */
 727 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 728 {
 729         amdgpu_gart_table_vram_free(adev);
 730         amdgpu_gart_fini(adev);
 731 }
 732
 733 /**
 734  * gmc_v7_0_vm_decode_fault - print human readable fault info
 735  *
 736  * @adev: amdgpu_device pointer
 737  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 738  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 739  *
 740  * Print human readable fault information (CIK).
 741  */
 742 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 743                                      u32 status, u32 addr, u32 mc_client)
 744 {
 745         u32 mc_id;
 746         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 747         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 748                                         PROTECTIONS);
 749         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 750                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 751
 752         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 753                               MEMORY_CLIENT_ID);
 754
 755         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 756                protections, vmid, addr,
 757                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 758                              MEMORY_CLIENT_RW) ?
 759                "write" : "read", block, mc_client, mc_id);
 760 }
 761
 762
 763 static const u32 mc_cg_registers[] = {
 764         mmMC_HUB_MISC_HUB_CG,
 765         mmMC_HUB_MISC_SIP_CG,
 766         mmMC_HUB_MISC_VM_CG,
 767         mmMC_XPB_CLK_GAT,
 768         mmATC_MISC_CG,
 769         mmMC_CITF_MISC_WR_CG,
 770         mmMC_CITF_MISC_RD_CG,
 771         mmMC_CITF_MISC_VM_CG,
 772         mmVM_L2_CG,
 773 };
 774
 775 static const u32 mc_cg_ls_en[] = {
 776         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 777         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 778         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 779         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 780         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 781         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 782         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 783         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 784         VM_L2_CG__MEM_LS_ENABLE_MASK,
 785 };
 786
 787 static const u32 mc_cg_en[] = {
 788         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 789         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 790         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 791         MC_XPB_CLK_GAT__ENABLE_MASK,
 792         ATC_MISC_CG__ENABLE_MASK,
 793         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 794         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 795         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 796         VM_L2_CG__ENABLE_MASK,
 797 };
 798
 799 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 800                                   bool enable)
 801 {
 802         int i;
 803         u32 orig, data;
 804
 805         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 806                 orig = data = RREG32(mc_cg_registers[i]);
 807                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 808                         data |= mc_cg_ls_en[i];
 809                 else
 810                         data &= ~mc_cg_ls_en[i];
 811                 if (data != orig)
 812                         WREG32(mc_cg_registers[i], data);
 813         }
 814 }
 815
 816 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 817                                     bool enable)
 818 {
 819         int i;
 820         u32 orig, data;
 821
 822         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 823                 orig = data = RREG32(mc_cg_registers[i]);
 824                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 825                         data |= mc_cg_en[i];
 826                 else
 827                         data &= ~mc_cg_en[i];
 828                 if (data != orig)
 829                         WREG32(mc_cg_registers[i], data);
 830         }
 831 }
 832
 833 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 834                                      bool enable)
 835 {
 836         u32 orig, data;
 837
 838         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 839
 840         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 841                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 842                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 843                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 844                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 845         } else {
 846                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 847                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 848                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 849                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 850         }
 851
 852         if (orig != data)
 853                 WREG32_PCIE(ixPCIE_CNTL2, data);
 854 }
 855
 856 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 857                                      bool enable)
 858 {
 859         u32 orig, data;
 860
 861         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 862
 863         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 864                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 865         else
 866                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 867
 868         if (orig != data)
 869                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 870 }
 871
 872 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 873                                    bool enable)
 874 {
 875         u32 orig, data;
 876
 877         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 878
 879         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 880                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 881         else
 882                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 883
 884         if (orig != data)
 885                 WREG32(mmHDP_MEM_POWER_LS, data);
 886 }
 887
 888 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 889 {
 890         switch (mc_seq_vram_type) {
 891         case MC_SEQ_MISC0__MT__GDDR1:
 892                 return AMDGPU_VRAM_TYPE_GDDR1;
 893         case MC_SEQ_MISC0__MT__DDR2:
 894                 return AMDGPU_VRAM_TYPE_DDR2;
 895         case MC_SEQ_MISC0__MT__GDDR3:
 896                 return AMDGPU_VRAM_TYPE_GDDR3;
 897         case MC_SEQ_MISC0__MT__GDDR4:
 898                 return AMDGPU_VRAM_TYPE_GDDR4;
 899         case MC_SEQ_MISC0__MT__GDDR5:
 900                 return AMDGPU_VRAM_TYPE_GDDR5;
 901         case MC_SEQ_MISC0__MT__HBM:
 902                 return AMDGPU_VRAM_TYPE_HBM;
 903         case MC_SEQ_MISC0__MT__DDR3:
 904                 return AMDGPU_VRAM_TYPE_DDR3;
 905         default:
 906                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 907         }
 908 }
 909
 910 static int gmc_v7_0_early_init(void *handle)
 911 {
 912         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 913
 914         gmc_v7_0_set_gart_funcs(adev);
 915         gmc_v7_0_set_irq_funcs(adev);
 916
 917         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 918         adev->mc.shared_aperture_end =
 919                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 920         adev->mc.private_aperture_start =
 921                 adev->mc.shared_aperture_end + 1;
 922         adev->mc.private_aperture_end =
 923                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 924
 925         return 0;
 926 }
 927
 928 static int gmc_v7_0_late_init(void *handle)
 929 {
 930         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 931
 932         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 933                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 934         else
 935                 return 0;
 936 }
 937
 938 static int gmc_v7_0_sw_init(void *handle)
 939 {
 940         int r;
 941         int dma_bits;
 942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 943
 944         if (adev->flags & AMD_IS_APU) {
 945                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 946         } else {
 947                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 948                 tmp &= MC_SEQ_MISC0__MT__MASK;
 949                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 950         }
 951
 952         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 953         if (r)
 954                 return r;
 955
 956         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 957         if (r)
 958                 return r;
 959
 960         /* Adjust VM size here.
 961          * Currently set to 4GB ((1 << 20) 4k pages).
 962          * Max GPUVM size for cayman and SI is 40 bits.
 963          */
 964         amdgpu_vm_adjust_size(adev, 64);
 965         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 966
 967         /* Set the internal MC address mask
 968          * This is the max address of the GPU's
 969          * internal address space.
 970          */
 971         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 972
 973         adev->mc.stolen_size = 256 * 1024;
 974
 975         /* set DMA mask + need_dma32 flags.
 976          * PCIE - can handle 40-bits.
 977          * IGP - can handle 40-bits
 978          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 979          */
 980         adev->need_dma32 = false;
 981         dma_bits = adev->need_dma32 ? 32 : 40;
 982         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 983         if (r) {
 984                 adev->need_dma32 = true;
 985                 dma_bits = 32;
 986                 pr_warn("amdgpu: No suitable DMA available\n");
 987         }
 988         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 989         if (r) {
 990                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 991                 pr_warn("amdgpu: No coherent DMA available\n");
 992         }
 993
 994         r = gmc_v7_0_init_microcode(adev);
 995         if (r) {
 996                 DRM_ERROR("Failed to load mc firmware!\n");
 997                 return r;
 998         }
 999
1000         r = gmc_v7_0_mc_init(adev);
1001         if (r)
1002                 return r;
1003
1004         /* Memory manager */
1005         r = amdgpu_bo_init(adev);
1006         if (r)
1007                 return r;
1008
1009         r = gmc_v7_0_gart_init(adev);
1010         if (r)
1011                 return r;
1012
1013         /*
1014          * number of VMs
1015          * VMID 0 is reserved for System
1016          * amdgpu graphics/compute will use VMIDs 1-7
1017          * amdkfd will use VMIDs 8-15
1018          */
1019         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1020         adev->vm_manager.num_level = 1;
1021         amdgpu_vm_manager_init(adev);
1022
1023         /* base offset of vram pages */
1024         if (adev->flags & AMD_IS_APU) {
1025                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1026
1027                 tmp <<= 22;
1028                 adev->vm_manager.vram_base_offset = tmp;
1029         } else {
1030                 adev->vm_manager.vram_base_offset = 0;
1031         }
1032
1033         return 0;
1034 }
1035
1036 static int gmc_v7_0_sw_fini(void *handle)
1037 {
1038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039
1040         amdgpu_vm_manager_fini(adev);
1041         gmc_v7_0_gart_fini(adev);
1042         amdgpu_gem_force_release(adev);
1043         amdgpu_bo_fini(adev);
1044
1045         return 0;
1046 }
1047
1048 static int gmc_v7_0_hw_init(void *handle)
1049 {
1050         int r;
1051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053         gmc_v7_0_init_golden_registers(adev);
1054
1055         gmc_v7_0_mc_program(adev);
1056
1057         if (!(adev->flags & AMD_IS_APU)) {
1058                 r = gmc_v7_0_mc_load_microcode(adev);
1059                 if (r) {
1060                         DRM_ERROR("Failed to load MC firmware!\n");
1061                         return r;
1062                 }
1063         }
1064
1065         r = gmc_v7_0_gart_enable(adev);
1066         if (r)
1067                 return r;
1068
1069         return r;
1070 }
1071
1072 static int gmc_v7_0_hw_fini(void *handle)
1073 {
1074         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1075
1076         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1077         gmc_v7_0_gart_disable(adev);
1078
1079         return 0;
1080 }
1081
1082 static int gmc_v7_0_suspend(void *handle)
1083 {
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         gmc_v7_0_hw_fini(adev);
1087
1088         return 0;
1089 }
1090
1091 static int gmc_v7_0_resume(void *handle)
1092 {
1093         int r;
1094         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1095
1096         r = gmc_v7_0_hw_init(adev);
1097         if (r)
1098                 return r;
1099
1100         amdgpu_vm_reset_all_ids(adev);
1101
1102         return 0;
1103 }
1104
1105 static bool gmc_v7_0_is_idle(void *handle)
1106 {
1107         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1108         u32 tmp = RREG32(mmSRBM_STATUS);
1109
1110         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1111                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1112                 return false;
1113
1114         return true;
1115 }
1116
1117 static int gmc_v7_0_wait_for_idle(void *handle)
1118 {
1119         unsigned i;
1120         u32 tmp;
1121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122
1123         for (i = 0; i < adev->usec_timeout; i++) {
1124                 /* read MC_STATUS */
1125                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1126                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1127                                                SRBM_STATUS__MCC_BUSY_MASK |
1128                                                SRBM_STATUS__MCD_BUSY_MASK |
1129                                                SRBM_STATUS__VMC_BUSY_MASK);
1130                 if (!tmp)
1131                         return 0;
1132                 udelay(1);
1133         }
1134         return -ETIMEDOUT;
1135
1136 }
1137
1138 static int gmc_v7_0_soft_reset(void *handle)
1139 {
1140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141         struct amdgpu_mode_mc_save save;
1142         u32 srbm_soft_reset = 0;
1143         u32 tmp = RREG32(mmSRBM_STATUS);
1144
1145         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1146                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1147                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1148
1149         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1150                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1151                 if (!(adev->flags & AMD_IS_APU))
1152                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1153                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1154         }
1155
1156         if (srbm_soft_reset) {
1157                 gmc_v7_0_mc_stop(adev, &save);
1158                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1159                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1160                 }
1161
1162
1163                 tmp = RREG32(mmSRBM_SOFT_RESET);
1164                 tmp |= srbm_soft_reset;
1165                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1166                 WREG32(mmSRBM_SOFT_RESET, tmp);
1167                 tmp = RREG32(mmSRBM_SOFT_RESET);
1168
1169                 udelay(50);
1170
1171                 tmp &= ~srbm_soft_reset;
1172                 WREG32(mmSRBM_SOFT_RESET, tmp);
1173                 tmp = RREG32(mmSRBM_SOFT_RESET);
1174
1175                 /* Wait a little for things to settle down */
1176                 udelay(50);
1177
1178                 gmc_v7_0_mc_resume(adev, &save);
1179                 udelay(50);
1180         }
1181
1182         return 0;
1183 }
1184
1185 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1186                                              struct amdgpu_irq_src *src,
1187                                              unsigned type,
1188                                              enum amdgpu_interrupt_state state)
1189 {
1190         u32 tmp;
1191         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1192                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1193                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1194                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1195                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1196                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1197
1198         switch (state) {
1199         case AMDGPU_IRQ_STATE_DISABLE:
1200                 /* system context */
1201                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1202                 tmp &= ~bits;
1203                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1204                 /* VMs */
1205                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1206                 tmp &= ~bits;
1207                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1208                 break;
1209         case AMDGPU_IRQ_STATE_ENABLE:
1210                 /* system context */
1211                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1212                 tmp |= bits;
1213                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1214                 /* VMs */
1215                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1216                 tmp |= bits;
1217                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1218                 break;
1219         default:
1220                 break;
1221         }
1222
1223         return 0;
1224 }
1225
1226 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1227                                       struct amdgpu_irq_src *source,
1228                                       struct amdgpu_iv_entry *entry)
1229 {
1230         u32 addr, status, mc_client;
1231
1232         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1233         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1234         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1235         /* reset addr and status */
1236         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1237
1238         if (!addr && !status)
1239                 return 0;
1240
1241         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1242                 gmc_v7_0_set_fault_enable_default(adev, false);
1243
1244         if (printk_ratelimit()) {
1245                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1246                         entry->src_id, entry->src_data[0]);
1247                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1248                         addr);
1249                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1250                         status);
1251                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int gmc_v7_0_set_clockgating_state(void *handle,
1258                                           enum amd_clockgating_state state)
1259 {
1260         bool gate = false;
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263         if (state == AMD_CG_STATE_GATE)
1264                 gate = true;
1265
1266         if (!(adev->flags & AMD_IS_APU)) {
1267                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1268                 gmc_v7_0_enable_mc_ls(adev, gate);
1269         }
1270         gmc_v7_0_enable_bif_mgls(adev, gate);
1271         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1272         gmc_v7_0_enable_hdp_ls(adev, gate);
1273
1274         return 0;
1275 }
1276
1277 static int gmc_v7_0_set_powergating_state(void *handle,
1278                                           enum amd_powergating_state state)
1279 {
1280         return 0;
1281 }
1282
1283 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1284         .name = "gmc_v7_0",
1285         .early_init = gmc_v7_0_early_init,
1286         .late_init = gmc_v7_0_late_init,
1287         .sw_init = gmc_v7_0_sw_init,
1288         .sw_fini = gmc_v7_0_sw_fini,
1289         .hw_init = gmc_v7_0_hw_init,
1290         .hw_fini = gmc_v7_0_hw_fini,
1291         .suspend = gmc_v7_0_suspend,
1292         .resume = gmc_v7_0_resume,
1293         .is_idle = gmc_v7_0_is_idle,
1294         .wait_for_idle = gmc_v7_0_wait_for_idle,
1295         .soft_reset = gmc_v7_0_soft_reset,
1296         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1297         .set_powergating_state = gmc_v7_0_set_powergating_state,
1298 };
1299
1300 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1301         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1302         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1303         .set_prt = gmc_v7_0_set_prt,
1304         .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
1305         .get_vm_pde = gmc_v7_0_get_vm_pde
1306 };
1307
1308 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1309         .set = gmc_v7_0_vm_fault_interrupt_state,
1310         .process = gmc_v7_0_process_interrupt,
1311 };
1312
1313 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1314 {
1315         if (adev->gart.gart_funcs == NULL)
1316                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1317 }
1318
1319 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1320 {
1321         adev->mc.vm_fault.num_types = 1;
1322         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1323 }
1324
1325 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1326 {
1327         .type = AMD_IP_BLOCK_TYPE_GMC,
1328         .major = 7,
1329         .minor = 0,
1330         .rev = 0,
1331         .funcs = &gmc_v7_0_ip_funcs,
1332 };
1333
1334 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1335 {
1336         .type = AMD_IP_BLOCK_TYPE_GMC,
1337         .major = 7,
1338         .minor = 4,
1339         .rev = 0,
1340         .funcs = &gmc_v7_0_ip_funcs,
1341 };