drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53
  54 /*
  55  * Global memory.
  56  */
  57 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  58 {
  59         return ttm_mem_global_init(ref->object);
  60 }
  61
  62 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  63 {
  64         ttm_mem_global_release(ref->object);
  65 }
  66
  67 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  68 {
  69         struct drm_global_reference *global_ref;
  70         struct amdgpu_ring *ring;
  71         struct amd_sched_rq *rq;
  72         int r;
  73
  74         adev->mman.mem_global_referenced = false;
  75         global_ref = &adev->mman.mem_global_ref;
  76         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  77         global_ref->size = sizeof(struct ttm_mem_global);
  78         global_ref->init = &amdgpu_ttm_mem_global_init;
  79         global_ref->release = &amdgpu_ttm_mem_global_release;
  80         r = drm_global_item_ref(global_ref);
  81         if (r) {
  82                 DRM_ERROR("Failed setting up TTM memory accounting "
  83                           "subsystem.\n");
  84                 goto error_mem;
  85         }
  86
  87         adev->mman.bo_global_ref.mem_glob =
  88                 adev->mman.mem_global_ref.object;
  89         global_ref = &adev->mman.bo_global_ref.ref;
  90         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  91         global_ref->size = sizeof(struct ttm_bo_global);
  92         global_ref->init = &ttm_bo_global_init;
  93         global_ref->release = &ttm_bo_global_release;
  94         r = drm_global_item_ref(global_ref);
  95         if (r) {
  96                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  97                 goto error_bo;
  98         }
  99
 100         ring = adev->mman.buffer_funcs_ring;
 101         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 102         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 103                                   rq, amdgpu_sched_jobs);
 104         if (r) {
 105                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 106                 goto error_entity;
 107         }
 108
 109         adev->mman.mem_global_referenced = true;
 110
 111         return 0;
 112
 113 error_entity:
 114         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 115 error_bo:
 116         drm_global_item_unref(&adev->mman.mem_global_ref);
 117 error_mem:
 118         return r;
 119 }
 120
 121 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 122 {
 123         if (adev->mman.mem_global_referenced) {
 124                 amd_sched_entity_fini(adev->mman.entity.sched,
 125                                       &adev->mman.entity);
 126                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 127                 drm_global_item_unref(&adev->mman.mem_global_ref);
 128                 adev->mman.mem_global_referenced = false;
 129         }
 130 }
 131
 132 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 133 {
 134         return 0;
 135 }
 136
 137 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 138                                 struct ttm_mem_type_manager *man)
 139 {
 140         struct amdgpu_device *adev;
 141
 142         adev = amdgpu_ttm_adev(bdev);
 143
 144         switch (type) {
 145         case TTM_PL_SYSTEM:
 146                 /* System memory */
 147                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 148                 man->available_caching = TTM_PL_MASK_CACHING;
 149                 man->default_caching = TTM_PL_FLAG_CACHED;
 150                 break;
 151         case TTM_PL_TT:
 152                 man->func = &amdgpu_gtt_mgr_func;
 153                 man->gpu_offset = adev->mc.gtt_start;
 154                 man->available_caching = TTM_PL_MASK_CACHING;
 155                 man->default_caching = TTM_PL_FLAG_CACHED;
 156                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 157                 break;
 158         case TTM_PL_VRAM:
 159                 /* "On-card" video ram */
 160                 man->func = &amdgpu_vram_mgr_func;
 161                 man->gpu_offset = adev->mc.vram_start;
 162                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 163                              TTM_MEMTYPE_FLAG_MAPPABLE;
 164                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 165                 man->default_caching = TTM_PL_FLAG_WC;
 166                 break;
 167         case AMDGPU_PL_GDS:
 168         case AMDGPU_PL_GWS:
 169         case AMDGPU_PL_OA:
 170                 /* On-chip GDS memory*/
 171                 man->func = &ttm_bo_manager_func;
 172                 man->gpu_offset = 0;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 174                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 175                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 176                 break;
 177         default:
 178                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 179                 return -EINVAL;
 180         }
 181         return 0;
 182 }
 183
 184 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 185                                 struct ttm_placement *placement)
 186 {
 187         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 188         struct amdgpu_bo *abo;
 189         static struct ttm_place placements = {
 190                 .fpfn = 0,
 191                 .lpfn = 0,
 192                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 193         };
 194         unsigned i;
 195
 196         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 197                 placement->placement = &placements;
 198                 placement->busy_placement = &placements;
 199                 placement->num_placement = 1;
 200                 placement->num_busy_placement = 1;
 201                 return;
 202         }
 203         abo = container_of(bo, struct amdgpu_bo, tbo);
 204         switch (bo->mem.mem_type) {
 205         case TTM_PL_VRAM:
 206                 if (adev->mman.buffer_funcs &&
 207                     adev->mman.buffer_funcs_ring &&
 208                     adev->mman.buffer_funcs_ring->ready == false) {
 209                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 210                 } else {
 211                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 212                         for (i = 0; i < abo->placement.num_placement; ++i) {
 213                                 if (!(abo->placements[i].flags &
 214                                       TTM_PL_FLAG_TT))
 215                                         continue;
 216
 217                                 if (abo->placements[i].lpfn)
 218                                         continue;
 219
 220                                 /* set an upper limit to force directly
 221                                  * allocating address space for the BO.
 222                                  */
 223                                 abo->placements[i].lpfn =
 224                                         adev->mc.gtt_size >> PAGE_SHIFT;
 225                         }
 226                 }
 227                 break;
 228         case TTM_PL_TT:
 229         default:
 230                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 231         }
 232         *placement = abo->placement;
 233 }
 234
 235 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 236 {
 237         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 238
 239         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 240                 return -EPERM;
 241         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 242                                           filp->private_data);
 243 }
 244
 245 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 246                              struct ttm_mem_reg *new_mem)
 247 {
 248         struct ttm_mem_reg *old_mem = &bo->mem;
 249
 250         BUG_ON(old_mem->mm_node != NULL);
 251         *old_mem = *new_mem;
 252         new_mem->mm_node = NULL;
 253 }
 254
 255 static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 256                                struct drm_mm_node *mm_node,
 257                                struct ttm_mem_reg *mem,
 258                                uint64_t *addr)
 259 {
 260         int r;
 261
 262         switch (mem->mem_type) {
 263         case TTM_PL_TT:
 264                 r = amdgpu_ttm_bind(bo, mem);
 265                 if (r)
 266                         return r;
 267
 268         case TTM_PL_VRAM:
 269                 *addr = mm_node->start << PAGE_SHIFT;
 270                 *addr += bo->bdev->man[mem->mem_type].gpu_offset;
 271                 break;
 272         default:
 273                 DRM_ERROR("Unknown placement %d\n", mem->mem_type);
 274                 return -EINVAL;
 275         }
 276
 277         return 0;
 278 }
 279
 280 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 281                             bool evict, bool no_wait_gpu,
 282                             struct ttm_mem_reg *new_mem,
 283                             struct ttm_mem_reg *old_mem)
 284 {
 285         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 286         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 287
 288         struct drm_mm_node *old_mm, *new_mm;
 289         uint64_t old_start, old_size, new_start, new_size;
 290         unsigned long num_pages;
 291         struct dma_fence *fence = NULL;
 292         int r;
 293
 294         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 295
 296         if (!ring->ready) {
 297                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 298                 return -EINVAL;
 299         }
 300
 301         old_mm = old_mem->mm_node;
 302         r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start);
 303         if (r)
 304                 return r;
 305         old_size = old_mm->size;
 306
 307
 308         new_mm = new_mem->mm_node;
 309         r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start);
 310         if (r)
 311                 return r;
 312         new_size = new_mm->size;
 313
 314         num_pages = new_mem->num_pages;
 315         while (num_pages) {
 316                 unsigned long cur_pages = min(old_size, new_size);
 317                 struct dma_fence *next;
 318
 319                 r = amdgpu_copy_buffer(ring, old_start, new_start,
 320                                        cur_pages * PAGE_SIZE,
 321                                        bo->resv, &next, false);
 322                 if (r)
 323                         goto error;
 324
 325                 dma_fence_put(fence);
 326                 fence = next;
 327
 328                 num_pages -= cur_pages;
 329                 if (!num_pages)
 330                         break;
 331
 332                 old_size -= cur_pages;
 333                 if (!old_size) {
 334                         r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
 335                                                 &old_start);
 336                         if (r)
 337                                 goto error;
 338                         old_size = old_mm->size;
 339                 } else {
 340                         old_start += cur_pages * PAGE_SIZE;
 341                 }
 342
 343                 new_size -= cur_pages;
 344                 if (!new_size) {
 345                         r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem,
 346                                                 &new_start);
 347                         if (r)
 348                                 goto error;
 349
 350                         new_size = new_mm->size;
 351                 } else {
 352                         new_start += cur_pages * PAGE_SIZE;
 353                 }
 354         }
 355
 356         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 357         dma_fence_put(fence);
 358         return r;
 359
 360 error:
 361         if (fence)
 362                 dma_fence_wait(fence, false);
 363         dma_fence_put(fence);
 364         return r;
 365 }
 366
 367 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 368                                 bool evict, bool interruptible,
 369                                 bool no_wait_gpu,
 370                                 struct ttm_mem_reg *new_mem)
 371 {
 372         struct amdgpu_device *adev;
 373         struct ttm_mem_reg *old_mem = &bo->mem;
 374         struct ttm_mem_reg tmp_mem;
 375         struct ttm_place placements;
 376         struct ttm_placement placement;
 377         int r;
 378
 379         adev = amdgpu_ttm_adev(bo->bdev);
 380         tmp_mem = *new_mem;
 381         tmp_mem.mm_node = NULL;
 382         placement.num_placement = 1;
 383         placement.placement = &placements;
 384         placement.num_busy_placement = 1;
 385         placement.busy_placement = &placements;
 386         placements.fpfn = 0;
 387         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 388         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 389         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 390                              interruptible, no_wait_gpu);
 391         if (unlikely(r)) {
 392                 return r;
 393         }
 394
 395         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 396         if (unlikely(r)) {
 397                 goto out_cleanup;
 398         }
 399
 400         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 401         if (unlikely(r)) {
 402                 goto out_cleanup;
 403         }
 404         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 405         if (unlikely(r)) {
 406                 goto out_cleanup;
 407         }
 408         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 409 out_cleanup:
 410         ttm_bo_mem_put(bo, &tmp_mem);
 411         return r;
 412 }
 413
 414 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 415                                 bool evict, bool interruptible,
 416                                 bool no_wait_gpu,
 417                                 struct ttm_mem_reg *new_mem)
 418 {
 419         struct amdgpu_device *adev;
 420         struct ttm_mem_reg *old_mem = &bo->mem;
 421         struct ttm_mem_reg tmp_mem;
 422         struct ttm_placement placement;
 423         struct ttm_place placements;
 424         int r;
 425
 426         adev = amdgpu_ttm_adev(bo->bdev);
 427         tmp_mem = *new_mem;
 428         tmp_mem.mm_node = NULL;
 429         placement.num_placement = 1;
 430         placement.placement = &placements;
 431         placement.num_busy_placement = 1;
 432         placement.busy_placement = &placements;
 433         placements.fpfn = 0;
 434         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 435         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 436         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 437                              interruptible, no_wait_gpu);
 438         if (unlikely(r)) {
 439                 return r;
 440         }
 441         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 442         if (unlikely(r)) {
 443                 goto out_cleanup;
 444         }
 445         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 446         if (unlikely(r)) {
 447                 goto out_cleanup;
 448         }
 449 out_cleanup:
 450         ttm_bo_mem_put(bo, &tmp_mem);
 451         return r;
 452 }
 453
 454 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 455                         bool evict, bool interruptible,
 456                         bool no_wait_gpu,
 457                         struct ttm_mem_reg *new_mem)
 458 {
 459         struct amdgpu_device *adev;
 460         struct amdgpu_bo *abo;
 461         struct ttm_mem_reg *old_mem = &bo->mem;
 462         int r;
 463
 464         /* Can't move a pinned BO */
 465         abo = container_of(bo, struct amdgpu_bo, tbo);
 466         if (WARN_ON_ONCE(abo->pin_count > 0))
 467                 return -EINVAL;
 468
 469         adev = amdgpu_ttm_adev(bo->bdev);
 470
 471         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 472                 amdgpu_move_null(bo, new_mem);
 473                 return 0;
 474         }
 475         if ((old_mem->mem_type == TTM_PL_TT &&
 476              new_mem->mem_type == TTM_PL_SYSTEM) ||
 477             (old_mem->mem_type == TTM_PL_SYSTEM &&
 478              new_mem->mem_type == TTM_PL_TT)) {
 479                 /* bind is enough */
 480                 amdgpu_move_null(bo, new_mem);
 481                 return 0;
 482         }
 483         if (adev->mman.buffer_funcs == NULL ||
 484             adev->mman.buffer_funcs_ring == NULL ||
 485             !adev->mman.buffer_funcs_ring->ready) {
 486                 /* use memcpy */
 487                 goto memcpy;
 488         }
 489
 490         if (old_mem->mem_type == TTM_PL_VRAM &&
 491             new_mem->mem_type == TTM_PL_SYSTEM) {
 492                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 493                                         no_wait_gpu, new_mem);
 494         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 495                    new_mem->mem_type == TTM_PL_VRAM) {
 496                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 497                                             no_wait_gpu, new_mem);
 498         } else {
 499                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 500         }
 501
 502         if (r) {
 503 memcpy:
 504                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 505                 if (r) {
 506                         return r;
 507                 }
 508         }
 509
 510         /* update statistics */
 511         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 512         return 0;
 513 }
 514
 515 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 516 {
 517         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 518         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 519
 520         mem->bus.addr = NULL;
 521         mem->bus.offset = 0;
 522         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 523         mem->bus.base = 0;
 524         mem->bus.is_iomem = false;
 525         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 526                 return -EINVAL;
 527         switch (mem->mem_type) {
 528         case TTM_PL_SYSTEM:
 529                 /* system memory */
 530                 return 0;
 531         case TTM_PL_TT:
 532                 break;
 533         case TTM_PL_VRAM:
 534                 mem->bus.offset = mem->start << PAGE_SHIFT;
 535                 /* check if it's visible */
 536                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 537                         return -EINVAL;
 538                 mem->bus.base = adev->mc.aper_base;
 539                 mem->bus.is_iomem = true;
 540                 break;
 541         default:
 542                 return -EINVAL;
 543         }
 544         return 0;
 545 }
 546
 547 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 548 {
 549 }
 550
 551 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 552                                            unsigned long page_offset)
 553 {
 554         struct drm_mm_node *mm = bo->mem.mm_node;
 555         uint64_t size = mm->size;
 556         uint64_t offset = page_offset;
 557
 558         page_offset = do_div(offset, size);
 559         mm += offset;
 560         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
 561 }
 562
 563 /*
 564  * TTM backend functions.
 565  */
 566 struct amdgpu_ttm_gup_task_list {
 567         struct list_head        list;
 568         struct task_struct      *task;
 569 };
 570
 571 struct amdgpu_ttm_tt {
 572         struct ttm_dma_tt       ttm;
 573         struct amdgpu_device    *adev;
 574         u64                     offset;
 575         uint64_t                userptr;
 576         struct mm_struct        *usermm;
 577         uint32_t                userflags;
 578         spinlock_t              guptasklock;
 579         struct list_head        guptasks;
 580         atomic_t                mmu_invalidations;
 581         struct list_head        list;
 582 };
 583
 584 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 585 {
 586         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 587         unsigned int flags = 0;
 588         unsigned pinned = 0;
 589         int r;
 590
 591         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 592                 flags |= FOLL_WRITE;
 593
 594         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 595                 /* check that we only use anonymous memory
 596                    to prevent problems with writeback */
 597                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 598                 struct vm_area_struct *vma;
 599
 600                 vma = find_vma(gtt->usermm, gtt->userptr);
 601                 if (!vma || vma->vm_file || vma->vm_end < end)
 602                         return -EPERM;
 603         }
 604
 605         do {
 606                 unsigned num_pages = ttm->num_pages - pinned;
 607                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 608                 struct page **p = pages + pinned;
 609                 struct amdgpu_ttm_gup_task_list guptask;
 610
 611                 guptask.task = current;
 612                 spin_lock(&gtt->guptasklock);
 613                 list_add(&guptask.list, &gtt->guptasks);
 614                 spin_unlock(&gtt->guptasklock);
 615
 616                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 617
 618                 spin_lock(&gtt->guptasklock);
 619                 list_del(&guptask.list);
 620                 spin_unlock(&gtt->guptasklock);
 621
 622                 if (r < 0)
 623                         goto release_pages;
 624
 625                 pinned += r;
 626
 627         } while (pinned < ttm->num_pages);
 628
 629         return 0;
 630
 631 release_pages:
 632         release_pages(pages, pinned, 0);
 633         return r;
 634 }
 635
 636 /* prepare the sg table with the user pages */
 637 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 638 {
 639         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 640         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 641         unsigned nents;
 642         int r;
 643
 644         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 645         enum dma_data_direction direction = write ?
 646                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 647
 648         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 649                                       ttm->num_pages << PAGE_SHIFT,
 650                                       GFP_KERNEL);
 651         if (r)
 652                 goto release_sg;
 653
 654         r = -ENOMEM;
 655         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 656         if (nents != ttm->sg->nents)
 657                 goto release_sg;
 658
 659         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 660                                          gtt->ttm.dma_address, ttm->num_pages);
 661
 662         return 0;
 663
 664 release_sg:
 665         kfree(ttm->sg);
 666         return r;
 667 }
 668
 669 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 670 {
 671         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 672         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 673         struct sg_page_iter sg_iter;
 674
 675         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 676         enum dma_data_direction direction = write ?
 677                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 678
 679         /* double check that we don't free the table twice */
 680         if (!ttm->sg->sgl)
 681                 return;
 682
 683         /* free the sg table and pages again */
 684         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 685
 686         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 687                 struct page *page = sg_page_iter_page(&sg_iter);
 688                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 689                         set_page_dirty(page);
 690
 691                 mark_page_accessed(page);
 692                 put_page(page);
 693         }
 694
 695         sg_free_table(ttm->sg);
 696 }
 697
 698 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 699                                    struct ttm_mem_reg *bo_mem)
 700 {
 701         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 702         int r;
 703
 704         if (gtt->userptr) {
 705                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 706                 if (r) {
 707                         DRM_ERROR("failed to pin userptr\n");
 708                         return r;
 709                 }
 710         }
 711         if (!ttm->num_pages) {
 712                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 713                      ttm->num_pages, bo_mem, ttm);
 714         }
 715
 716         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 717             bo_mem->mem_type == AMDGPU_PL_GWS ||
 718             bo_mem->mem_type == AMDGPU_PL_OA)
 719                 return -EINVAL;
 720
 721         return 0;
 722 }
 723
 724 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 725 {
 726         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 727
 728         return gtt && !list_empty(&gtt->list);
 729 }
 730
 731 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 732 {
 733         struct ttm_tt *ttm = bo->ttm;
 734         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 735         uint64_t flags;
 736         int r;
 737
 738         if (!ttm || amdgpu_ttm_is_bound(ttm))
 739                 return 0;
 740
 741         r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
 742                                  NULL, bo_mem);
 743         if (r) {
 744                 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
 745                 return r;
 746         }
 747
 748         spin_lock(&gtt->adev->gtt_list_lock);
 749         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 750         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 751         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 752                 ttm->pages, gtt->ttm.dma_address, flags);
 753
 754         if (r) {
 755                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 756                           ttm->num_pages, gtt->offset);
 757                 goto error_gart_bind;
 758         }
 759
 760         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 761 error_gart_bind:
 762         spin_unlock(&gtt->adev->gtt_list_lock);
 763         return r;
 764 }
 765
 766 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 767 {
 768         struct amdgpu_ttm_tt *gtt, *tmp;
 769         struct ttm_mem_reg bo_mem;
 770         uint64_t flags;
 771         int r;
 772
 773         bo_mem.mem_type = TTM_PL_TT;
 774         spin_lock(&adev->gtt_list_lock);
 775         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 776                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 777                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 778                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 779                                      flags);
 780                 if (r) {
 781                         spin_unlock(&adev->gtt_list_lock);
 782                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 783                                   gtt->ttm.ttm.num_pages, gtt->offset);
 784                         return r;
 785                 }
 786         }
 787         spin_unlock(&adev->gtt_list_lock);
 788         return 0;
 789 }
 790
 791 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 792 {
 793         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 794         int r;
 795
 796         if (gtt->userptr)
 797                 amdgpu_ttm_tt_unpin_userptr(ttm);
 798
 799         if (!amdgpu_ttm_is_bound(ttm))
 800                 return 0;
 801
 802         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 803         spin_lock(&gtt->adev->gtt_list_lock);
 804         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 805         if (r) {
 806                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 807                           gtt->ttm.ttm.num_pages, gtt->offset);
 808                 goto error_unbind;
 809         }
 810         list_del_init(&gtt->list);
 811 error_unbind:
 812         spin_unlock(&gtt->adev->gtt_list_lock);
 813         return r;
 814 }
 815
 816 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 817 {
 818         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 819
 820         ttm_dma_tt_fini(&gtt->ttm);
 821         kfree(gtt);
 822 }
 823
 824 static struct ttm_backend_func amdgpu_backend_func = {
 825         .bind = &amdgpu_ttm_backend_bind,
 826         .unbind = &amdgpu_ttm_backend_unbind,
 827         .destroy = &amdgpu_ttm_backend_destroy,
 828 };
 829
 830 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 831                                     unsigned long size, uint32_t page_flags,
 832                                     struct page *dummy_read_page)
 833 {
 834         struct amdgpu_device *adev;
 835         struct amdgpu_ttm_tt *gtt;
 836
 837         adev = amdgpu_ttm_adev(bdev);
 838
 839         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 840         if (gtt == NULL) {
 841                 return NULL;
 842         }
 843         gtt->ttm.ttm.func = &amdgpu_backend_func;
 844         gtt->adev = adev;
 845         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 846                 kfree(gtt);
 847                 return NULL;
 848         }
 849         INIT_LIST_HEAD(&gtt->list);
 850         return &gtt->ttm.ttm;
 851 }
 852
 853 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 854 {
 855         struct amdgpu_device *adev;
 856         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 857         unsigned i;
 858         int r;
 859         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 860
 861         if (ttm->state != tt_unpopulated)
 862                 return 0;
 863
 864         if (gtt && gtt->userptr) {
 865                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 866                 if (!ttm->sg)
 867                         return -ENOMEM;
 868
 869                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 870                 ttm->state = tt_unbound;
 871                 return 0;
 872         }
 873
 874         if (slave && ttm->sg) {
 875                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 876                                                  gtt->ttm.dma_address, ttm->num_pages);
 877                 ttm->state = tt_unbound;
 878                 return 0;
 879         }
 880
 881         adev = amdgpu_ttm_adev(ttm->bdev);
 882
 883 #ifdef CONFIG_SWIOTLB
 884         if (swiotlb_nr_tbl()) {
 885                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 886         }
 887 #endif
 888
 889         r = ttm_pool_populate(ttm);
 890         if (r) {
 891                 return r;
 892         }
 893
 894         for (i = 0; i < ttm->num_pages; i++) {
 895                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 896                                                        0, PAGE_SIZE,
 897                                                        PCI_DMA_BIDIRECTIONAL);
 898                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 899                         while (i--) {
 900                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 901                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 902                                 gtt->ttm.dma_address[i] = 0;
 903                         }
 904                         ttm_pool_unpopulate(ttm);
 905                         return -EFAULT;
 906                 }
 907         }
 908         return 0;
 909 }
 910
 911 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 912 {
 913         struct amdgpu_device *adev;
 914         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 915         unsigned i;
 916         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 917
 918         if (gtt && gtt->userptr) {
 919                 kfree(ttm->sg);
 920                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 921                 return;
 922         }
 923
 924         if (slave)
 925                 return;
 926
 927         adev = amdgpu_ttm_adev(ttm->bdev);
 928
 929 #ifdef CONFIG_SWIOTLB
 930         if (swiotlb_nr_tbl()) {
 931                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 932                 return;
 933         }
 934 #endif
 935
 936         for (i = 0; i < ttm->num_pages; i++) {
 937                 if (gtt->ttm.dma_address[i]) {
 938                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 939                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 940                 }
 941         }
 942
 943         ttm_pool_unpopulate(ttm);
 944 }
 945
 946 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 947                               uint32_t flags)
 948 {
 949         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 950
 951         if (gtt == NULL)
 952                 return -EINVAL;
 953
 954         gtt->userptr = addr;
 955         gtt->usermm = current->mm;
 956         gtt->userflags = flags;
 957         spin_lock_init(&gtt->guptasklock);
 958         INIT_LIST_HEAD(&gtt->guptasks);
 959         atomic_set(&gtt->mmu_invalidations, 0);
 960
 961         return 0;
 962 }
 963
 964 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 965 {
 966         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 967
 968         if (gtt == NULL)
 969                 return NULL;
 970
 971         return gtt->usermm;
 972 }
 973
 974 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 975                                   unsigned long end)
 976 {
 977         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 978         struct amdgpu_ttm_gup_task_list *entry;
 979         unsigned long size;
 980
 981         if (gtt == NULL || !gtt->userptr)
 982                 return false;
 983
 984         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 985         if (gtt->userptr > end || gtt->userptr + size <= start)
 986                 return false;
 987
 988         spin_lock(&gtt->guptasklock);
 989         list_for_each_entry(entry, &gtt->guptasks, list) {
 990                 if (entry->task == current) {
 991                         spin_unlock(&gtt->guptasklock);
 992                         return false;
 993                 }
 994         }
 995         spin_unlock(&gtt->guptasklock);
 996
 997         atomic_inc(&gtt->mmu_invalidations);
 998
 999         return true;
1000 }
1001
1002 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1003                                        int *last_invalidated)
1004 {
1005         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1006         int prev_invalidated = *last_invalidated;
1007
1008         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1009         return prev_invalidated != *last_invalidated;
1010 }
1011
1012 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1013 {
1014         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1015
1016         if (gtt == NULL)
1017                 return false;
1018
1019         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1020 }
1021
1022 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1023                                  struct ttm_mem_reg *mem)
1024 {
1025         uint64_t flags = 0;
1026
1027         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1028                 flags |= AMDGPU_PTE_VALID;
1029
1030         if (mem && mem->mem_type == TTM_PL_TT) {
1031                 flags |= AMDGPU_PTE_SYSTEM;
1032
1033                 if (ttm->caching_state == tt_cached)
1034                         flags |= AMDGPU_PTE_SNOOPED;
1035         }
1036
1037         flags |= adev->gart.gart_pte_flags;
1038         flags |= AMDGPU_PTE_READABLE;
1039
1040         if (!amdgpu_ttm_tt_is_readonly(ttm))
1041                 flags |= AMDGPU_PTE_WRITEABLE;
1042
1043         return flags;
1044 }
1045
1046 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1047                                             const struct ttm_place *place)
1048 {
1049         unsigned long num_pages = bo->mem.num_pages;
1050         struct drm_mm_node *node = bo->mem.mm_node;
1051
1052         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1053                 return ttm_bo_eviction_valuable(bo, place);
1054
1055         switch (bo->mem.mem_type) {
1056         case TTM_PL_TT:
1057                 return true;
1058
1059         case TTM_PL_VRAM:
1060                 /* Check each drm MM node individually */
1061                 while (num_pages) {
1062                         if (place->fpfn < (node->start + node->size) &&
1063                             !(place->lpfn && place->lpfn <= node->start))
1064                                 return true;
1065
1066                         num_pages -= node->size;
1067                         ++node;
1068                 }
1069                 break;
1070
1071         default:
1072                 break;
1073         }
1074
1075         return ttm_bo_eviction_valuable(bo, place);
1076 }
1077
1078 static struct ttm_bo_driver amdgpu_bo_driver = {
1079         .ttm_tt_create = &amdgpu_ttm_tt_create,
1080         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1081         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1082         .invalidate_caches = &amdgpu_invalidate_caches,
1083         .init_mem_type = &amdgpu_init_mem_type,
1084         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1085         .evict_flags = &amdgpu_evict_flags,
1086         .move = &amdgpu_bo_move,
1087         .verify_access = &amdgpu_verify_access,
1088         .move_notify = &amdgpu_bo_move_notify,
1089         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1090         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1091         .io_mem_free = &amdgpu_ttm_io_mem_free,
1092         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1093 };
1094
1095 int amdgpu_ttm_init(struct amdgpu_device *adev)
1096 {
1097         int r;
1098
1099         r = amdgpu_ttm_global_init(adev);
1100         if (r) {
1101                 return r;
1102         }
1103         /* No others user of address space so set it to 0 */
1104         r = ttm_bo_device_init(&adev->mman.bdev,
1105                                adev->mman.bo_global_ref.ref.object,
1106                                &amdgpu_bo_driver,
1107                                adev->ddev->anon_inode->i_mapping,
1108                                DRM_FILE_PAGE_OFFSET,
1109                                adev->need_dma32);
1110         if (r) {
1111                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1112                 return r;
1113         }
1114         adev->mman.initialized = true;
1115         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1116                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1117         if (r) {
1118                 DRM_ERROR("Failed initializing VRAM heap.\n");
1119                 return r;
1120         }
1121         /* Change the size here instead of the init above so only lpfn is affected */
1122         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1123
1124         r = amdgpu_bo_create(adev, adev->mc.stolen_size, PAGE_SIZE, true,
1125                              AMDGPU_GEM_DOMAIN_VRAM,
1126                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1127                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1128                              NULL, NULL, &adev->stollen_vga_memory);
1129         if (r) {
1130                 return r;
1131         }
1132         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1133         if (r)
1134                 return r;
1135         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1136         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1137         if (r) {
1138                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1139                 return r;
1140         }
1141         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1142                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1143         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1144                                 adev->mc.gtt_size >> PAGE_SHIFT);
1145         if (r) {
1146                 DRM_ERROR("Failed initializing GTT heap.\n");
1147                 return r;
1148         }
1149         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1150                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1151
1152         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1153         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1154         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1155         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1156         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1157         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1158         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1159         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1160         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1161         /* GDS Memory */
1162         if (adev->gds.mem.total_size) {
1163                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1164                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1165                 if (r) {
1166                         DRM_ERROR("Failed initializing GDS heap.\n");
1167                         return r;
1168                 }
1169         }
1170
1171         /* GWS */
1172         if (adev->gds.gws.total_size) {
1173                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1174                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1175                 if (r) {
1176                         DRM_ERROR("Failed initializing gws heap.\n");
1177                         return r;
1178                 }
1179         }
1180
1181         /* OA */
1182         if (adev->gds.oa.total_size) {
1183                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1184                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1185                 if (r) {
1186                         DRM_ERROR("Failed initializing oa heap.\n");
1187                         return r;
1188                 }
1189         }
1190
1191         r = amdgpu_ttm_debugfs_init(adev);
1192         if (r) {
1193                 DRM_ERROR("Failed to init debugfs\n");
1194                 return r;
1195         }
1196         return 0;
1197 }
1198
1199 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1200 {
1201         int r;
1202
1203         if (!adev->mman.initialized)
1204                 return;
1205         amdgpu_ttm_debugfs_fini(adev);
1206         if (adev->stollen_vga_memory) {
1207                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, true);
1208                 if (r == 0) {
1209                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1210                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1211                 }
1212                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1213         }
1214         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1215         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1216         if (adev->gds.mem.total_size)
1217                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1218         if (adev->gds.gws.total_size)
1219                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1220         if (adev->gds.oa.total_size)
1221                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1222         ttm_bo_device_release(&adev->mman.bdev);
1223         amdgpu_gart_fini(adev);
1224         amdgpu_ttm_global_fini(adev);
1225         adev->mman.initialized = false;
1226         DRM_INFO("amdgpu: ttm finalized\n");
1227 }
1228
1229 /* this should only be called at bootup or when userspace
1230  * isn't running */
1231 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1232 {
1233         struct ttm_mem_type_manager *man;
1234
1235         if (!adev->mman.initialized)
1236                 return;
1237
1238         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1239         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1240         man->size = size >> PAGE_SHIFT;
1241 }
1242
1243 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1244 {
1245         struct drm_file *file_priv;
1246         struct amdgpu_device *adev;
1247
1248         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1249                 return -EINVAL;
1250
1251         file_priv = filp->private_data;
1252         adev = file_priv->minor->dev->dev_private;
1253         if (adev == NULL)
1254                 return -EINVAL;
1255
1256         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1257 }
1258
1259 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1260                        uint64_t src_offset,
1261                        uint64_t dst_offset,
1262                        uint32_t byte_count,
1263                        struct reservation_object *resv,
1264                        struct dma_fence **fence, bool direct_submit)
1265 {
1266         struct amdgpu_device *adev = ring->adev;
1267         struct amdgpu_job *job;
1268
1269         uint32_t max_bytes;
1270         unsigned num_loops, num_dw;
1271         unsigned i;
1272         int r;
1273
1274         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1275         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1276         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1277
1278         /* for IB padding */
1279         while (num_dw & 0x7)
1280                 num_dw++;
1281
1282         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1283         if (r)
1284                 return r;
1285
1286         if (resv) {
1287                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1288                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1289                 if (r) {
1290                         DRM_ERROR("sync failed (%d).\n", r);
1291                         goto error_free;
1292                 }
1293         }
1294
1295         for (i = 0; i < num_loops; i++) {
1296                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1297
1298                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1299                                         dst_offset, cur_size_in_bytes);
1300
1301                 src_offset += cur_size_in_bytes;
1302                 dst_offset += cur_size_in_bytes;
1303                 byte_count -= cur_size_in_bytes;
1304         }
1305
1306         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1307         WARN_ON(job->ibs[0].length_dw > num_dw);
1308         if (direct_submit) {
1309                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1310                                        NULL, fence);
1311                 job->fence = dma_fence_get(*fence);
1312                 if (r)
1313                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1314                 amdgpu_job_free(job);
1315         } else {
1316                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1317                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1318                 if (r)
1319                         goto error_free;
1320         }
1321
1322         return r;
1323
1324 error_free:
1325         amdgpu_job_free(job);
1326         return r;
1327 }
1328
1329 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1330                        uint32_t src_data,
1331                        struct reservation_object *resv,
1332                        struct dma_fence **fence)
1333 {
1334         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1335         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1336         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1337
1338         struct drm_mm_node *mm_node;
1339         unsigned long num_pages;
1340         unsigned int num_loops, num_dw;
1341
1342         struct amdgpu_job *job;
1343         int r;
1344
1345         if (!ring->ready) {
1346                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1347                 return -EINVAL;
1348         }
1349
1350         num_pages = bo->tbo.num_pages;
1351         mm_node = bo->tbo.mem.mm_node;
1352         num_loops = 0;
1353         while (num_pages) {
1354                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1355
1356                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1357                 num_pages -= mm_node->size;
1358                 ++mm_node;
1359         }
1360         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1361
1362         /* for IB padding */
1363         num_dw += 64;
1364
1365         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1366         if (r)
1367                 return r;
1368
1369         if (resv) {
1370                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1371                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1372                 if (r) {
1373                         DRM_ERROR("sync failed (%d).\n", r);
1374                         goto error_free;
1375                 }
1376         }
1377
1378         num_pages = bo->tbo.num_pages;
1379         mm_node = bo->tbo.mem.mm_node;
1380
1381         while (num_pages) {
1382                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1383                 uint64_t dst_addr;
1384
1385                 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1386                                         &bo->tbo.mem, &dst_addr);
1387                 if (r)
1388                         return r;
1389
1390                 while (byte_count) {
1391                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1392
1393                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1394                                                 dst_addr, cur_size_in_bytes);
1395
1396                         dst_addr += cur_size_in_bytes;
1397                         byte_count -= cur_size_in_bytes;
1398                 }
1399
1400                 num_pages -= mm_node->size;
1401                 ++mm_node;
1402         }
1403
1404         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1405         WARN_ON(job->ibs[0].length_dw > num_dw);
1406         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1407                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1408         if (r)
1409                 goto error_free;
1410
1411         return 0;
1412
1413 error_free:
1414         amdgpu_job_free(job);
1415         return r;
1416 }
1417
1418 #if defined(CONFIG_DEBUG_FS)
1419
1420 extern void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager
1421                                  *man);
1422 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1423 {
1424         struct drm_info_node *node = (struct drm_info_node *)m->private;
1425         unsigned ttm_pl = *(int *)node->info_ent->data;
1426         struct drm_device *dev = node->minor->dev;
1427         struct amdgpu_device *adev = dev->dev_private;
1428         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1429         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1430         struct drm_printer p = drm_seq_file_printer(m);
1431
1432         spin_lock(&glob->lru_lock);
1433         drm_mm_print(mm, &p);
1434         spin_unlock(&glob->lru_lock);
1435         switch (ttm_pl) {
1436         case TTM_PL_VRAM:
1437                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1438                            adev->mman.bdev.man[ttm_pl].size,
1439                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1440                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1441                 break;
1442         case TTM_PL_TT:
1443                 amdgpu_gtt_mgr_print(m, &adev->mman.bdev.man[TTM_PL_TT]);
1444                 break;
1445         }
1446         return 0;
1447 }
1448
1449 static int ttm_pl_vram = TTM_PL_VRAM;
1450 static int ttm_pl_tt = TTM_PL_TT;
1451
1452 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1453         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1454         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1455         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1456 #ifdef CONFIG_SWIOTLB
1457         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1458 #endif
1459 };
1460
1461 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1462                                     size_t size, loff_t *pos)
1463 {
1464         struct amdgpu_device *adev = file_inode(f)->i_private;
1465         ssize_t result = 0;
1466         int r;
1467
1468         if (size & 0x3 || *pos & 0x3)
1469                 return -EINVAL;
1470
1471         if (*pos >= adev->mc.mc_vram_size)
1472                 return -ENXIO;
1473
1474         while (size) {
1475                 unsigned long flags;
1476                 uint32_t value;
1477
1478                 if (*pos >= adev->mc.mc_vram_size)
1479                         return result;
1480
1481                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1482                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1483                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1484                 value = RREG32(mmMM_DATA);
1485                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1486
1487                 r = put_user(value, (uint32_t *)buf);
1488                 if (r)
1489                         return r;
1490
1491                 result += 4;
1492                 buf += 4;
1493                 *pos += 4;
1494                 size -= 4;
1495         }
1496
1497         return result;
1498 }
1499
1500 static const struct file_operations amdgpu_ttm_vram_fops = {
1501         .owner = THIS_MODULE,
1502         .read = amdgpu_ttm_vram_read,
1503         .llseek = default_llseek
1504 };
1505
1506 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1507
1508 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1509                                    size_t size, loff_t *pos)
1510 {
1511         struct amdgpu_device *adev = file_inode(f)->i_private;
1512         ssize_t result = 0;
1513         int r;
1514
1515         while (size) {
1516                 loff_t p = *pos / PAGE_SIZE;
1517                 unsigned off = *pos & ~PAGE_MASK;
1518                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1519                 struct page *page;
1520                 void *ptr;
1521
1522                 if (p >= adev->gart.num_cpu_pages)
1523                         return result;
1524
1525                 page = adev->gart.pages[p];
1526                 if (page) {
1527                         ptr = kmap(page);
1528                         ptr += off;
1529
1530                         r = copy_to_user(buf, ptr, cur_size);
1531                         kunmap(adev->gart.pages[p]);
1532                 } else
1533                         r = clear_user(buf, cur_size);
1534
1535                 if (r)
1536                         return -EFAULT;
1537
1538                 result += cur_size;
1539                 buf += cur_size;
1540                 *pos += cur_size;
1541                 size -= cur_size;
1542         }
1543
1544         return result;
1545 }
1546
1547 static const struct file_operations amdgpu_ttm_gtt_fops = {
1548         .owner = THIS_MODULE,
1549         .read = amdgpu_ttm_gtt_read,
1550         .llseek = default_llseek
1551 };
1552
1553 #endif
1554
1555 #endif
1556
1557 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1558 {
1559 #if defined(CONFIG_DEBUG_FS)
1560         unsigned count;
1561
1562         struct drm_minor *minor = adev->ddev->primary;
1563         struct dentry *ent, *root = minor->debugfs_root;
1564
1565         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1566                                   adev, &amdgpu_ttm_vram_fops);
1567         if (IS_ERR(ent))
1568                 return PTR_ERR(ent);
1569         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1570         adev->mman.vram = ent;
1571
1572 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1573         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1574                                   adev, &amdgpu_ttm_gtt_fops);
1575         if (IS_ERR(ent))
1576                 return PTR_ERR(ent);
1577         i_size_write(ent->d_inode, adev->mc.gtt_size);
1578         adev->mman.gtt = ent;
1579
1580 #endif
1581         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1582
1583 #ifdef CONFIG_SWIOTLB
1584         if (!swiotlb_nr_tbl())
1585                 --count;
1586 #endif
1587
1588         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1589 #else
1590
1591         return 0;
1592 #endif
1593 }
1594
1595 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1596 {
1597 #if defined(CONFIG_DEBUG_FS)
1598
1599         debugfs_remove(adev->mman.vram);
1600         adev->mman.vram = NULL;
1601
1602 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1603         debugfs_remove(adev->mman.gtt);
1604         adev->mman.gtt = NULL;
1605 #endif
1606
1607 #endif
1608 }