drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35
  36 static void psp_set_funcs(struct amdgpu_device *adev);
  37
  38 static int psp_early_init(void *handle)
  39 {
  40         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  41
  42         psp_set_funcs(adev);
  43
  44         return 0;
  45 }
  46
  47 static int psp_sw_init(void *handle)
  48 {
  49         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  50         struct psp_context *psp = &adev->psp;
  51         int ret;
  52
  53         switch (adev->asic_type) {
  54         case CHIP_VEGA10:
  55         case CHIP_VEGA12:
  56                 psp_v3_1_set_psp_funcs(psp);
  57                 break;
  58         case CHIP_RAVEN:
  59                 psp_v10_0_set_psp_funcs(psp);
  60                 break;
  61         case CHIP_VEGA20:
  62                 psp_v11_0_set_psp_funcs(psp);
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         psp->adev = adev;
  69
  70         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  71                 return 0;
  72
  73         ret = psp_init_microcode(psp);
  74         if (ret) {
  75                 DRM_ERROR("Failed to load psp firmware!\n");
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int psp_sw_fini(void *handle)
  83 {
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  87                 return 0;
  88
  89         release_firmware(adev->psp.sos_fw);
  90         adev->psp.sos_fw = NULL;
  91         release_firmware(adev->psp.asd_fw);
  92         adev->psp.asd_fw = NULL;
  93         release_firmware(adev->psp.ta_fw);
  94         adev->psp.ta_fw = NULL;
  95         return 0;
  96 }
  97
  98 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  99                  uint32_t reg_val, uint32_t mask, bool check_changed)
 100 {
 101         uint32_t val;
 102         int i;
 103         struct amdgpu_device *adev = psp->adev;
 104
 105         for (i = 0; i < adev->usec_timeout; i++) {
 106                 val = RREG32(reg_index);
 107                 if (check_changed) {
 108                         if (val != reg_val)
 109                                 return 0;
 110                 } else {
 111                         if ((val & mask) == reg_val)
 112                                 return 0;
 113                 }
 114                 udelay(1);
 115         }
 116
 117         return -ETIME;
 118 }
 119
 120 static int
 121 psp_cmd_submit_buf(struct psp_context *psp,
 122                    struct amdgpu_firmware_info *ucode,
 123                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 124 {
 125         int ret;
 126         int index;
 127
 128         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 129
 130         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 131
 132         index = atomic_inc_return(&psp->fence_value);
 133         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 134                              fence_mc_addr, index);
 135         if (ret) {
 136                 atomic_dec(&psp->fence_value);
 137                 return ret;
 138         }
 139
 140         while (*((unsigned int *)psp->fence_buf) != index)
 141                 msleep(1);
 142
 143         /* the status field must be 0 after FW is loaded */
 144         if (ucode && psp->cmd_buf_mem->resp.status) {
 145                 DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
 146                           psp->cmd_buf_mem->resp.status, ucode->ucode_id);
 147                 return -EINVAL;
 148         }
 149
 150         if (ucode) {
 151                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 152                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 153         }
 154
 155         return ret;
 156 }
 157
 158 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 159                                  struct psp_gfx_cmd_resp *cmd,
 160                                  uint64_t tmr_mc, uint32_t size)
 161 {
 162         if (psp_support_vmr_ring(psp))
 163                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 164         else
 165                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 166         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 167         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 168         cmd->cmd.cmd_setup_tmr.buf_size = size;
 169 }
 170
 171 /* Set up Trusted Memory Region */
 172 static int psp_tmr_init(struct psp_context *psp)
 173 {
 174         int ret;
 175
 176         /*
 177          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 178          * physical).
 179          *
 180          * Note: this memory need be reserved till the driver
 181          * uninitializes.
 182          */
 183         ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
 184                                       AMDGPU_GEM_DOMAIN_VRAM,
 185                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 186
 187         return ret;
 188 }
 189
 190 static int psp_tmr_load(struct psp_context *psp)
 191 {
 192         int ret;
 193         struct psp_gfx_cmd_resp *cmd;
 194
 195         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 196         if (!cmd)
 197                 return -ENOMEM;
 198
 199         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
 200         DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
 201                         PSP_TMR_SIZE, psp->tmr_mc_addr);
 202
 203         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 204                                  psp->fence_buf_mc_addr);
 205         if (ret)
 206                 goto failed;
 207
 208         kfree(cmd);
 209
 210         return 0;
 211
 212 failed:
 213         kfree(cmd);
 214         return ret;
 215 }
 216
 217 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 218                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 219                                  uint32_t size, uint32_t shared_size)
 220 {
 221         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 222         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 223         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 224         cmd->cmd.cmd_load_ta.app_len = size;
 225
 226         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 227         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 228         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 229 }
 230
 231 static int psp_asd_init(struct psp_context *psp)
 232 {
 233         int ret;
 234
 235         /*
 236          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 237          * physical) for shared ASD <-> Driver
 238          */
 239         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 240                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 241                                       &psp->asd_shared_bo,
 242                                       &psp->asd_shared_mc_addr,
 243                                       &psp->asd_shared_buf);
 244
 245         return ret;
 246 }
 247
 248 static int psp_asd_load(struct psp_context *psp)
 249 {
 250         int ret;
 251         struct psp_gfx_cmd_resp *cmd;
 252
 253         /* If PSP version doesn't match ASD version, asd loading will be failed.
 254          * add workaround to bypass it for sriov now.
 255          * TODO: add version check to make it common
 256          */
 257         if (amdgpu_sriov_vf(psp->adev))
 258                 return 0;
 259
 260         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 261         if (!cmd)
 262                 return -ENOMEM;
 263
 264         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 265         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 266
 267         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 268                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 269
 270         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 271                                  psp->fence_buf_mc_addr);
 272
 273         kfree(cmd);
 274
 275         return ret;
 276 }
 277
 278 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 279                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 280                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 281 {
 282         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 283         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 284         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 285         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 286
 287         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 288         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 289         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 290 }
 291
 292 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 293 {
 294         int ret;
 295
 296         /*
 297          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 298          * physical) for xgmi ta <-> Driver
 299          */
 300         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 301                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 302                                       &psp->xgmi_context.xgmi_shared_bo,
 303                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 304                                       &psp->xgmi_context.xgmi_shared_buf);
 305
 306         return ret;
 307 }
 308
 309 static int psp_xgmi_load(struct psp_context *psp)
 310 {
 311         int ret;
 312         struct psp_gfx_cmd_resp *cmd;
 313
 314         /*
 315          * TODO: bypass the loading in sriov for now
 316          */
 317         if (amdgpu_sriov_vf(psp->adev))
 318                 return 0;
 319
 320         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 321         if (!cmd)
 322                 return -ENOMEM;
 323
 324         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 325         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 326
 327         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 328                                       psp->xgmi_context.xgmi_shared_mc_addr,
 329                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 330
 331         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 332                                  psp->fence_buf_mc_addr);
 333
 334         if (!ret) {
 335                 psp->xgmi_context.initialized = 1;
 336                 psp->xgmi_context.session_id = cmd->resp.session_id;
 337         }
 338
 339         kfree(cmd);
 340
 341         return ret;
 342 }
 343
 344 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 345                                             uint32_t xgmi_session_id)
 346 {
 347         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 348         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 349 }
 350
 351 static int psp_xgmi_unload(struct psp_context *psp)
 352 {
 353         int ret;
 354         struct psp_gfx_cmd_resp *cmd;
 355
 356         /*
 357          * TODO: bypass the unloading in sriov for now
 358          */
 359         if (amdgpu_sriov_vf(psp->adev))
 360                 return 0;
 361
 362         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 363         if (!cmd)
 364                 return -ENOMEM;
 365
 366         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 367
 368         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 369                                  psp->fence_buf_mc_addr);
 370
 371         kfree(cmd);
 372
 373         return ret;
 374 }
 375
 376 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 377                                             uint32_t ta_cmd_id,
 378                                             uint32_t xgmi_session_id)
 379 {
 380         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 381         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 382         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 383         /* Note: cmd_invoke_cmd.buf is not used for now */
 384 }
 385
 386 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 387 {
 388         int ret;
 389         struct psp_gfx_cmd_resp *cmd;
 390
 391         /*
 392          * TODO: bypass the loading in sriov for now
 393         */
 394         if (amdgpu_sriov_vf(psp->adev))
 395                 return 0;
 396
 397         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 398         if (!cmd)
 399                 return -ENOMEM;
 400
 401         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 402                                         psp->xgmi_context.session_id);
 403
 404         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 405                                  psp->fence_buf_mc_addr);
 406
 407         kfree(cmd);
 408
 409         return ret;
 410 }
 411
 412 static int psp_xgmi_terminate(struct psp_context *psp)
 413 {
 414         int ret;
 415
 416         if (!psp->xgmi_context.initialized)
 417                 return 0;
 418
 419         ret = psp_xgmi_unload(psp);
 420         if (ret)
 421                 return ret;
 422
 423         psp->xgmi_context.initialized = 0;
 424
 425         /* free xgmi shared memory */
 426         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 427                         &psp->xgmi_context.xgmi_shared_mc_addr,
 428                         &psp->xgmi_context.xgmi_shared_buf);
 429
 430         return 0;
 431 }
 432
 433 static int psp_xgmi_initialize(struct psp_context *psp)
 434 {
 435         struct ta_xgmi_shared_memory *xgmi_cmd;
 436         int ret;
 437
 438         if (!psp->xgmi_context.initialized) {
 439                 ret = psp_xgmi_init_shared_buf(psp);
 440                 if (ret)
 441                         return ret;
 442         }
 443
 444         /* Load XGMI TA */
 445         ret = psp_xgmi_load(psp);
 446         if (ret)
 447                 return ret;
 448
 449         /* Initialize XGMI session */
 450         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 451         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 452         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 453
 454         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 455
 456         return ret;
 457 }
 458
 459 static int psp_hw_start(struct psp_context *psp)
 460 {
 461         struct amdgpu_device *adev = psp->adev;
 462         int ret;
 463
 464         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 465                 ret = psp_bootloader_load_sysdrv(psp);
 466                 if (ret)
 467                         return ret;
 468
 469                 ret = psp_bootloader_load_sos(psp);
 470                 if (ret)
 471                         return ret;
 472         }
 473
 474         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 475         if (ret)
 476                 return ret;
 477
 478         ret = psp_tmr_load(psp);
 479         if (ret)
 480                 return ret;
 481
 482         ret = psp_asd_load(psp);
 483         if (ret)
 484                 return ret;
 485
 486         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 487                 ret = psp_xgmi_initialize(psp);
 488                 /* Warning the XGMI seesion initialize failure
 489                  * Instead of stop driver initialization
 490                  */
 491                 if (ret)
 492                         dev_err(psp->adev->dev,
 493                                 "XGMI: Failed to initialize XGMI session\n");
 494         }
 495         return 0;
 496 }
 497
 498 static int psp_np_fw_load(struct psp_context *psp)
 499 {
 500         int i, ret;
 501         struct amdgpu_firmware_info *ucode;
 502         struct amdgpu_device* adev = psp->adev;
 503
 504         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 505                 ucode = &adev->firmware.ucode[i];
 506                 if (!ucode->fw)
 507                         continue;
 508
 509                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 510                     psp_smu_reload_quirk(psp))
 511                         continue;
 512                 if (amdgpu_sriov_vf(adev) &&
 513                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 514                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 515                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 516                         /*skip ucode loading in SRIOV VF */
 517                         continue;
 518
 519                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 520                 if (ret)
 521                         return ret;
 522
 523                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 524                                          psp->fence_buf_mc_addr);
 525                 if (ret)
 526                         return ret;
 527
 528 #if 0
 529                 /* check if firmware loaded sucessfully */
 530                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 531                         return -EINVAL;
 532 #endif
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int psp_load_fw(struct amdgpu_device *adev)
 539 {
 540         int ret;
 541         struct psp_context *psp = &adev->psp;
 542
 543         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
 544                 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 545                 goto skip_memalloc;
 546         }
 547
 548         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 549         if (!psp->cmd)
 550                 return -ENOMEM;
 551
 552         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 553                                         AMDGPU_GEM_DOMAIN_GTT,
 554                                         &psp->fw_pri_bo,
 555                                         &psp->fw_pri_mc_addr,
 556                                         &psp->fw_pri_buf);
 557         if (ret)
 558                 goto failed;
 559
 560         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 561                                         AMDGPU_GEM_DOMAIN_VRAM,
 562                                         &psp->fence_buf_bo,
 563                                         &psp->fence_buf_mc_addr,
 564                                         &psp->fence_buf);
 565         if (ret)
 566                 goto failed_mem2;
 567
 568         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 569                                       AMDGPU_GEM_DOMAIN_VRAM,
 570                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 571                                       (void **)&psp->cmd_buf_mem);
 572         if (ret)
 573                 goto failed_mem1;
 574
 575         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 576
 577         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 578         if (ret)
 579                 goto failed_mem;
 580
 581         ret = psp_tmr_init(psp);
 582         if (ret)
 583                 goto failed_mem;
 584
 585         ret = psp_asd_init(psp);
 586         if (ret)
 587                 goto failed_mem;
 588
 589 skip_memalloc:
 590         ret = psp_hw_start(psp);
 591         if (ret)
 592                 goto failed_mem;
 593
 594         ret = psp_np_fw_load(psp);
 595         if (ret)
 596                 goto failed_mem;
 597
 598         return 0;
 599
 600 failed_mem:
 601         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 602                               &psp->cmd_buf_mc_addr,
 603                               (void **)&psp->cmd_buf_mem);
 604 failed_mem1:
 605         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 606                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 607 failed_mem2:
 608         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 609                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 610 failed:
 611         kfree(psp->cmd);
 612         psp->cmd = NULL;
 613         return ret;
 614 }
 615
 616 static int psp_hw_init(void *handle)
 617 {
 618         int ret;
 619         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 620
 621
 622         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 623                 return 0;
 624
 625         mutex_lock(&adev->firmware.mutex);
 626         /*
 627          * This sequence is just used on hw_init only once, no need on
 628          * resume.
 629          */
 630         ret = amdgpu_ucode_init_bo(adev);
 631         if (ret)
 632                 goto failed;
 633
 634         ret = psp_load_fw(adev);
 635         if (ret) {
 636                 DRM_ERROR("PSP firmware loading failed\n");
 637                 goto failed;
 638         }
 639
 640         mutex_unlock(&adev->firmware.mutex);
 641         return 0;
 642
 643 failed:
 644         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 645         mutex_unlock(&adev->firmware.mutex);
 646         return -EINVAL;
 647 }
 648
 649 static int psp_hw_fini(void *handle)
 650 {
 651         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 652         struct psp_context *psp = &adev->psp;
 653
 654         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 655                 return 0;
 656
 657         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
 658             psp->xgmi_context.initialized == 1)
 659                 psp_xgmi_terminate(psp);
 660
 661         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 662
 663         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 664         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 665                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 666         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 667                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 668         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 669                               &psp->asd_shared_buf);
 670         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 671                               (void **)&psp->cmd_buf_mem);
 672
 673         kfree(psp->cmd);
 674         psp->cmd = NULL;
 675
 676         return 0;
 677 }
 678
 679 static int psp_suspend(void *handle)
 680 {
 681         int ret;
 682         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 683         struct psp_context *psp = &adev->psp;
 684
 685         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 686                 return 0;
 687
 688         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
 689             psp->xgmi_context.initialized == 1) {
 690                 ret = psp_xgmi_terminate(psp);
 691                 if (ret) {
 692                         DRM_ERROR("Failed to terminate xgmi ta\n");
 693                         return ret;
 694                 }
 695         }
 696
 697         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 698         if (ret) {
 699                 DRM_ERROR("PSP ring stop failed\n");
 700                 return ret;
 701         }
 702
 703         return 0;
 704 }
 705
 706 static int psp_resume(void *handle)
 707 {
 708         int ret;
 709         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 710         struct psp_context *psp = &adev->psp;
 711
 712         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 713                 return 0;
 714
 715         DRM_INFO("PSP is resuming...\n");
 716
 717         mutex_lock(&adev->firmware.mutex);
 718
 719         ret = psp_hw_start(psp);
 720         if (ret)
 721                 goto failed;
 722
 723         ret = psp_np_fw_load(psp);
 724         if (ret)
 725                 goto failed;
 726
 727         mutex_unlock(&adev->firmware.mutex);
 728
 729         return 0;
 730
 731 failed:
 732         DRM_ERROR("PSP resume failed\n");
 733         mutex_unlock(&adev->firmware.mutex);
 734         return ret;
 735 }
 736
 737 int psp_gpu_reset(struct amdgpu_device *adev)
 738 {
 739         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 740                 return 0;
 741
 742         return psp_mode1_reset(&adev->psp);
 743 }
 744
 745 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 746                                         enum AMDGPU_UCODE_ID ucode_type)
 747 {
 748         struct amdgpu_firmware_info *ucode = NULL;
 749
 750         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 751                 DRM_INFO("firmware is not loaded by PSP\n");
 752                 return true;
 753         }
 754
 755         if (!adev->firmware.fw_size)
 756                 return false;
 757
 758         ucode = &adev->firmware.ucode[ucode_type];
 759         if (!ucode->fw || !ucode->ucode_size)
 760                 return false;
 761
 762         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 763 }
 764
 765 static int psp_set_clockgating_state(void *handle,
 766                                      enum amd_clockgating_state state)
 767 {
 768         return 0;
 769 }
 770
 771 static int psp_set_powergating_state(void *handle,
 772                                      enum amd_powergating_state state)
 773 {
 774         return 0;
 775 }
 776
 777 const struct amd_ip_funcs psp_ip_funcs = {
 778         .name = "psp",
 779         .early_init = psp_early_init,
 780         .late_init = NULL,
 781         .sw_init = psp_sw_init,
 782         .sw_fini = psp_sw_fini,
 783         .hw_init = psp_hw_init,
 784         .hw_fini = psp_hw_fini,
 785         .suspend = psp_suspend,
 786         .resume = psp_resume,
 787         .is_idle = NULL,
 788         .check_soft_reset = NULL,
 789         .wait_for_idle = NULL,
 790         .soft_reset = NULL,
 791         .set_clockgating_state = psp_set_clockgating_state,
 792         .set_powergating_state = psp_set_powergating_state,
 793 };
 794
 795 static const struct amdgpu_psp_funcs psp_funcs = {
 796         .check_fw_loading_status = psp_check_fw_loading_status,
 797 };
 798
 799 static void psp_set_funcs(struct amdgpu_device *adev)
 800 {
 801         if (NULL == adev->firmware.funcs)
 802                 adev->firmware.funcs = &psp_funcs;
 803 }
 804
 805 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 806 {
 807         .type = AMD_IP_BLOCK_TYPE_PSP,
 808         .major = 3,
 809         .minor = 1,
 810         .rev = 0,
 811         .funcs = &psp_ip_funcs,
 812 };
 813
 814 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 815 {
 816         .type = AMD_IP_BLOCK_TYPE_PSP,
 817         .major = 10,
 818         .minor = 0,
 819         .rev = 0,
 820         .funcs = &psp_ip_funcs,
 821 };
 822
 823 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
 824 {
 825         .type = AMD_IP_BLOCK_TYPE_PSP,
 826         .major = 11,
 827         .minor = 0,
 828         .rev = 0,
 829         .funcs = &psp_ip_funcs,
 830 };